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1/*
2 * arch/arm/mach-tegra/include/mach/iomap.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 *
11 * Copyright (C) 2010-2011 NVIDIA Corporation
12 *
13 * This software is licensed under the terms of the GNU General Public
14 * License version 2, as published by the Free Software Foundation, and
15 * may be copied, distributed, and modified under those terms.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 */
23
24#ifndef __MACH_TEGRA_IOMAP_H
25#define __MACH_TEGRA_IOMAP_H
26
27#include <asm/sizes.h>
28
29#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
30#define TEGRA_NOR_FLASH_BASE 0xD0000000
31#define TEGRA_NOR_FLASH_SIZE SZ_256M
32#else
33#define TEGRA_NOR_FLASH_BASE 0x48000000
34#define TEGRA_NOR_FLASH_SIZE SZ_128M
35#endif
36
37#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
38#define TEGRA_DRAM_BASE 0x00000000
39#define TEGRA_DRAM_SIZE SZ_1G /* Maximum size */
40#else
41#define TEGRA_DRAM_BASE 0x80000000
42#define TEGRA_DRAM_SIZE (SZ_2G - SZ_1M) /* Maximum size */
43#endif
44
45#define TEGRA_IRAM_BASE 0x40000000
46#define TEGRA_IRAM_SIZE SZ_256K
47
48/* First 1K of IRAM is reserved for cpu reset handler. */
49#define TEGRA_RESET_HANDLER_BASE TEGRA_IRAM_BASE
50#define TEGRA_RESET_HANDLER_SIZE SZ_1K
51
52#define TEGRA_HOST1X_BASE 0x50000000
53#define TEGRA_HOST1X_SIZE 0x24000
54
55#define TEGRA_ARM_PERIF_BASE 0x50040000
56#define TEGRA_ARM_PERIF_SIZE SZ_8K
57
58#define TEGRA_MSELECT_BASE 0x50042000
59#define TEGRA_MSELECT_SIZE 80
60
61#define TEGRA_ARM_PL310_BASE 0x50043000
62#define TEGRA_ARM_PL310_SIZE SZ_4K
63
64#define TEGRA_ARM_INT_DIST_BASE 0x50041000
65#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
66
67#define TEGRA_MPE_BASE 0x54040000
68#define TEGRA_MPE_SIZE SZ_256K
69
70#define TEGRA_VI_BASE 0x54080000
71#define TEGRA_VI_SIZE SZ_256K
72
73#define TEGRA_ISP_BASE 0x54100000
74#define TEGRA_ISP_SIZE SZ_256K
75
76#define TEGRA_DISPLAY_BASE 0x54200000
77#define TEGRA_DISPLAY_SIZE SZ_256K
78
79#define TEGRA_DISPLAY2_BASE 0x54240000
80#define TEGRA_DISPLAY2_SIZE SZ_256K
81
82#define TEGRA_HDMI_BASE 0x54280000
83#define TEGRA_HDMI_SIZE SZ_256K
84
85#define TEGRA_DSI_BASE 0x54300000
86#define TEGRA_DSI_SIZE SZ_256K
87
88#define TEGRA_DSIB_BASE 0x54400000
89#define TEGRA_DSIB_SIZE SZ_256K
90
91#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
92
93#define TEGRA_GART_BASE 0x58000000
94#define TEGRA_GART_SIZE SZ_32M
95
96#else
97
98#define TEGRA_SMMU_BASE_TEGRA3_A01 0xe0000000
99#define TEGRA_SMMU_SIZE_TEGRA3_A01 SZ_256M
100#define TEGRA_SMMU_BASE 0x00001000
101#define TEGRA_SMMU_SIZE (SZ_1G - SZ_4K * 2)
102
103#endif
104
105#define TEGRA_RES_SEMA_SIZE SZ_4K
106#define TEGRA_RES_SEMA_BASE 0x60001000
107
108#define TEGRA_ARB_SEMA_BASE 0x60002000
109#define TEGRA_ARB_SEMA_SIZE SZ_4K
110
111#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
112#define TEGRA_PRIMARY_ICTLR_SIZE 64
113
114#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
115#define TEGRA_ARBGNT_ICTLR_SIZE 192
116
117#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
118#define TEGRA_SECONDARY_ICTLR_SIZE 64
119
120#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
121#define TEGRA_TERTIARY_ICTLR_SIZE 64
122
123#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
124#define TEGRA_QUATERNARY_ICTLR_SIZE 64
125
126#ifndef CONFIG_ARCH_TEGRA_2x_SOC
127
128#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
129#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
130
131#endif
132
133#define TEGRA_TMR1_BASE 0x60005000
134#define TEGRA_TMR1_SIZE SZ_8
135
136#define TEGRA_TMR2_BASE 0x60005008
137#define TEGRA_TMR2_SIZE SZ_8
138
139#define TEGRA_TMRUS_BASE 0x60005010
140#define TEGRA_TMRUS_SIZE 64
141
142#define TEGRA_TMR3_BASE 0x60005050
143#define TEGRA_TMR3_SIZE SZ_8
144
145#define TEGRA_TMR4_BASE 0x60005058
146#define TEGRA_TMR4_SIZE SZ_8
147
148#ifndef CONFIG_ARCH_TEGRA_2x_SOC
149
150#define TEGRA_TMR5_BASE 0x60005060
151#define TEGRA_TMR5_SIZE 8
152
153#define TEGRA_TMR6_BASE 0x60005068
154#define TEGRA_TMR6_SIZE 8
155
156#define TEGRA_TMR7_BASE 0x60005070
157#define TEGRA_TMR7_SIZE 8
158
159#define TEGRA_TMR8_BASE 0x60005078
160#define TEGRA_TMR8_SIZE 8
161
162#define TEGRA_TMR9_BASE 0x60005080
163#define TEGRA_TMR9_SIZE 8
164
165#define TEGRA_TMR10_BASE 0x60005088
166#define TEGRA_TMR10_SIZE 8
167
168#define TEGRA_WDT0_BASE 0x60005100
169#define TEGRA_WDT0_SIZE 32
170
171#define TEGRA_WDT1_BASE 0x60005120
172#define TEGRA_WDT1_SIZE 32
173
174#define TEGRA_WDT2_BASE 0x60005140
175#define TEGRA_WDT2_SIZE 32
176
177#define TEGRA_WDT3_BASE 0x60005160
178#define TEGRA_WDT3_SIZE 32
179
180#define TEGRA_WDT4_BASE 0x60005180
181#define TEGRA_WDT4_SIZE 32
182
183#endif
184
185#define TEGRA_CLK_RESET_BASE 0x60006000
186#define TEGRA_CLK_RESET_SIZE SZ_4K
187
188#define TEGRA_FLOW_CTRL_BASE 0x60007000
189#define TEGRA_FLOW_CTRL_SIZE 20
190
191#define TEGRA_AHB_DMA_BASE 0x60008000
192#define TEGRA_AHB_DMA_SIZE SZ_4K
193
194#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
195#define TEGRA_AHB_DMA_CH0_SIZE 32
196
197#define TEGRA_APB_DMA_BASE 0x6000A000
198#define TEGRA_APB_DMA_SIZE SZ_4K
199
200#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
201#define TEGRA_APB_DMA_CH0_SIZE 32
202
203#ifndef CONFIG_ARCH_TEGRA_2x_SOC
204
205#define TEGRA_AHB_ARB_BASE 0x6000C000
206#define TEGRA_AHB_ARB_SIZE 768 /* Overlaps with GISMO */
207
208#endif
209
210#define TEGRA_AHB_GIZMO_BASE 0x6000C004
211#define TEGRA_AHB_GIZMO_SIZE 0x10C
212
213#define TEGRA_SB_BASE 0x6000C200
214#define TEGRA_SB_SIZE 256
215
216#define TEGRA_STATMON_BASE 0x6000C400
217#define TEGRA_STATMON_SIZE SZ_1K
218
219#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
220
221#define TEGRA_ACTMON_BASE 0x6000C800
222#define TEGRA_ACTMON_SIZE SZ_1K
223
224#endif
225
226#define TEGRA_GPIO_BASE 0x6000D000
227#define TEGRA_GPIO_SIZE SZ_4K
228
229#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
230#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
231
232#define TEGRA_BSEA_BASE 0x60010000
233#define TEGRA_BSEA_SIZE SZ_4K
234
235#define TEGRA_VDE_BASE 0x6001A000
236#define TEGRA_VDE_SIZE 0x3c00
237
238#define TEGRA_APB_MISC_BASE 0x70000000
239#define TEGRA_APB_MISC_SIZE SZ_4K
240
241#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
242#define TEGRA_APB_MISC_DAS_SIZE SZ_128
243
244#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
245
246#define TEGRA_AC97_BASE 0x70002000
247#define TEGRA_AC97_SIZE SZ_512
248
249#define TEGRA_SPDIF_BASE 0x70002400
250#define TEGRA_SPDIF_SIZE SZ_512
251
252#define TEGRA_I2S1_BASE 0x70002800
253#define TEGRA_I2S1_SIZE SZ_256
254
255#define TEGRA_I2S2_BASE 0x70002A00
256#define TEGRA_I2S2_SIZE SZ_256
257
258#define TEGRA_PCIE_BASE 0x80000000
259#define TEGRA_PCIE_SIZE SZ_1G
260
261#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
262
263#define TEGRA_TSENSOR_BASE 0x70014000
264#define TEGRA_TSENSOR_SIZE SZ_4K
265
266#define TEGRA_HDA_BASE 0x70030000
267#define TEGRA_HDA_SIZE SZ_64K
268
269#define TEGRA_AUDIO_CLUSTER_BASE 0x70080000
270#define TEGRA_AUDIO_CLUSTER_SIZE SZ_4K
271
272#define TEGRA_APBIF0_BASE TEGRA_AUDIO_CLUSTER_BASE
273#define TEGRA_APBIF0_SIZE 32
274
275#define TEGRA_APBIF1_BASE 0x70080020
276#define TEGRA_APBIF1_SIZE 32
277
278#define TEGRA_APBIF2_BASE 0x70080040
279#define TEGRA_APBIF2_SIZE 32
280
281#define TEGRA_APBIF3_BASE 0x70080060
282#define TEGRA_APBIF3_SIZE 32
283
284#define TEGRA_AHUB_BASE 0x70080200
285#define TEGRA_AHUB_SIZE SZ_256
286
287#define TEGRA_I2S0_BASE 0x70080300
288#define TEGRA_I2S0_SIZE SZ_256
289
290#define TEGRA_I2S1_BASE 0x70080400
291#define TEGRA_I2S1_SIZE SZ_256
292
293#define TEGRA_I2S2_BASE 0x70080500
294#define TEGRA_I2S2_SIZE SZ_256
295
296#define TEGRA_I2S3_BASE 0x70080600
297#define TEGRA_I2S3_SIZE SZ_256
298
299#define TEGRA_I2S4_BASE 0x70080700
300#define TEGRA_I2S4_SIZE SZ_256
301
302#define TEGRA_DAM0_BASE 0x70080800
303#define TEGRA_DAM0_SIZE SZ_256
304
305#define TEGRA_DAM1_BASE 0x70080900
306#define TEGRA_DAM1_SIZE SZ_256
307
308#define TEGRA_DAM2_BASE 0x70080A00
309#define TEGRA_DAM2_SIZE SZ_256
310
311#define TEGRA_SPDIF_BASE 0x70080B00
312#define TEGRA_SPDIF_SIZE SZ_256
313
314#define TEGRA_PCIE_BASE 0x00000000
315#define TEGRA_PCIE_SIZE SZ_1G
316
317#endif
318
319#define TEGRA_UARTA_BASE 0x70006000
320#define TEGRA_UARTA_SIZE 64
321
322#define TEGRA_UARTB_BASE 0x70006040
323#define TEGRA_UARTB_SIZE 64
324
325#define TEGRA_UARTC_BASE 0x70006200
326#define TEGRA_UARTC_SIZE SZ_256
327
328#define TEGRA_UARTD_BASE 0x70006300
329#define TEGRA_UARTD_SIZE SZ_256
330
331#define TEGRA_UARTE_BASE 0x70006400
332#define TEGRA_UARTE_SIZE SZ_256
333
334#define TEGRA_NAND_BASE 0x70008000
335#define TEGRA_NAND_SIZE SZ_256
336
337#define TEGRA_HSMMC_BASE 0x70008500
338#define TEGRA_HSMMC_SIZE SZ_256
339
340#define TEGRA_SNOR_BASE 0x70009000
341#define TEGRA_SNOR_SIZE SZ_4K
342
343#define TEGRA_PWFM_BASE 0x7000A000
344#define TEGRA_PWFM_SIZE SZ_256
345
346#define TEGRA_PWFM0_BASE 0x7000A000
347#define TEGRA_PWFM0_SIZE 4
348
349#define TEGRA_PWFM1_BASE 0x7000A010
350#define TEGRA_PWFM1_SIZE 4
351
352#define TEGRA_PWFM2_BASE 0x7000A020
353#define TEGRA_PWFM2_SIZE 4
354
355#define TEGRA_PWFM3_BASE 0x7000A030
356#define TEGRA_PWFM3_SIZE 4
357
358#define TEGRA_MIPI_BASE 0x7000B000
359#define TEGRA_MIPI_SIZE SZ_256
360
361#define TEGRA_I2C_BASE 0x7000C000
362#define TEGRA_I2C_SIZE SZ_256
363
364#define TEGRA_TWC_BASE 0x7000C100
365#define TEGRA_TWC_SIZE SZ_256
366
367#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
368
369#define TEGRA_SPI_BASE 0x7000C380
370#define TEGRA_SPI_SIZE 48
371
372#else
373
374#define TEGRA_DTV_BASE 0x7000C300
375#define TEGRA_DTV_SIZE SZ_256
376
377#endif
378
379#define TEGRA_I2C2_BASE 0x7000C400
380#define TEGRA_I2C2_SIZE SZ_256
381
382#define TEGRA_I2C3_BASE 0x7000C500
383#define TEGRA_I2C3_SIZE SZ_256
384
385#define TEGRA_OWR_BASE 0x7000C600
386#define TEGRA_OWR_SIZE 80
387
388#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
389
390#define TEGRA_DVC_BASE 0x7000D000
391#define TEGRA_DVC_SIZE SZ_512
392
393#else
394
395#define TEGRA_I2C4_BASE 0x7000C700
396#define TEGRA_I2C4_SIZE SZ_512
397
398#define TEGRA_I2C5_BASE 0x7000D000
399#define TEGRA_I2C5_SIZE SZ_512
400
401#endif
402
403#define TEGRA_SPI1_BASE 0x7000D400
404#define TEGRA_SPI1_SIZE SZ_512
405
406#define TEGRA_SPI2_BASE 0x7000D600
407#define TEGRA_SPI2_SIZE SZ_512
408
409#define TEGRA_SPI3_BASE 0x7000D800
410#define TEGRA_SPI3_SIZE SZ_512
411
412#define TEGRA_SPI4_BASE 0x7000DA00
413#define TEGRA_SPI4_SIZE SZ_512
414
415#ifndef CONFIG_ARCH_TEGRA_2x_SOC
416
417#define TEGRA_SPI5_BASE 0x7000DC00
418#define TEGRA_SPI5_SIZE SZ_512
419
420#define TEGRA_SPI6_BASE 0x7000DE00
421#define TEGRA_SPI6_SIZE SZ_512
422
423#endif
424
425#define TEGRA_RTC_BASE 0x7000E000
426#define TEGRA_RTC_SIZE SZ_256
427
428#define TEGRA_KBC_BASE 0x7000E200
429#define TEGRA_KBC_SIZE SZ_256
430
431#define TEGRA_PMC_BASE 0x7000E400
432#define TEGRA_PMC_SIZE SZ_256
433
434#define TEGRA_MC_BASE 0x7000F000
435#define TEGRA_MC_SIZE SZ_1K
436
437#define TEGRA_EMC_BASE 0x7000F400
438#define TEGRA_EMC_SIZE SZ_1K
439
440#define TEGRA_FUSE_BASE 0x7000F800
441#define TEGRA_FUSE_SIZE SZ_1K
442
443#define TEGRA_KFUSE_BASE 0x7000FC00
444#define TEGRA_KFUSE_SIZE SZ_1K
445
446#define TEGRA_CSITE_BASE 0x70040000
447#define TEGRA_CSITE_SIZE SZ_256K
448
449#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
450
451#define TEGRA_USB_BASE 0xC5000000
452#define TEGRA_USB_SIZE SZ_16K
453
454#define TEGRA_USB2_BASE 0xC5004000
455#define TEGRA_USB2_SIZE SZ_16K
456
457#define TEGRA_USB3_BASE 0xC5008000
458#define TEGRA_USB3_SIZE SZ_16K
459
460#define TEGRA_SDMMC1_BASE 0xC8000000
461#define TEGRA_SDMMC1_SIZE SZ_512
462
463#define TEGRA_SDMMC2_BASE 0xC8000200
464#define TEGRA_SDMMC2_SIZE SZ_512
465
466#define TEGRA_SDMMC3_BASE 0xC8000400
467#define TEGRA_SDMMC3_SIZE SZ_512
468
469#define TEGRA_SDMMC4_BASE 0xC8000600
470#define TEGRA_SDMMC4_SIZE SZ_512
471
472#else
473
474#define TEGRA_SATA_BASE 0x70020000
475#define TEGRA_SATA_SIZE SZ_64K
476
477#define TEGRA_SATA_CONFIG_BASE 0x70021000
478#define TEGRA_SATA_CONFIG_SIZE SZ_4K
479
480#define TEGRA_SATA_BAR5_BASE 0x70027000
481#define TEGRA_SATA_BAR5_SIZE SZ_8K
482
483#define TEGRA_SDMMC1_BASE 0x78000000
484#define TEGRA_SDMMC1_SIZE SZ_512
485
486#define TEGRA_SDMMC2_BASE 0x78000200
487#define TEGRA_SDMMC2_SIZE SZ_512
488
489#define TEGRA_SDMMC3_BASE 0x78000400
490#define TEGRA_SDMMC3_SIZE SZ_512
491
492#define TEGRA_SDMMC4_BASE 0x78000600
493#define TEGRA_SDMMC4_SIZE SZ_512
494
495#define TEGRA_USB_BASE 0x7D000000
496#define TEGRA_USB_SIZE SZ_16K
497
498#define TEGRA_USB2_BASE 0x7D004000
499#define TEGRA_USB2_SIZE SZ_16K
500
501#define TEGRA_USB3_BASE 0x7D008000
502#define TEGRA_USB3_SIZE SZ_16K
503
504#define TEGRA_SE_BASE 0x70012000
505#define TEGRA_SE_SIZE SZ_8K
506
507#endif
508
509#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
510# define TEGRA_DEBUG_UART_BASE 0
511#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
512# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
513#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
514# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
515#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
516# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
517#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
518# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
519#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
520# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
521#endif
522
523#endif