Added missing tegra files.HEADmaster

58 files changed, 6220 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/include/mach/arb_sema.h b/arch/arm/mach-tegra/include/mach/arb_sema.h
new file mode 100644
index 00000000000..9283f079cf6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/arb_sema.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-tegra/include/mach/arb_sema.h
+ *
+ * Hardware arbitration semaphore interface
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_ARB_SEMA_H
+#define __MACH_TEGRA_ARB_SEMA_H
+
+enum tegra_arb_module {
+        TEGRA_ARB_BSEV = 0,
+        TEGRA_ARB_BSEA,
+};
+
+int tegra_arb_mutex_lock_timeout(enum tegra_arb_module lock, int msecs);
+
+int tegra_arb_mutex_unlock(enum tegra_arb_module lock);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/audio.h b/arch/arm/mach-tegra/include/mach/audio.h
new file mode 100644
index 00000000000..5950ececae0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/audio.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-tegra/include/mach/audio.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_TEGRA_AUDIO_H
+#define __ARCH_ARM_MACH_TEGRA_AUDIO_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <mach/i2s.h>
+
+#define FIFO1           0
+#define FIFO2           1
+
+/* FIXME: this is not enforced by the hardware. */
+#define I2S_FIFO_TX             FIFO1
+#define I2S_FIFO_RX             FIFO2
+
+#define TEGRA_AUDIO_ENABLE_TX   1
+#define TEGRA_AUDIO_ENABLE_RX   2
+
+struct tegra_audio_platform_data {
+        bool i2s_master;
+        bool dsp_master;
+        int i2s_master_clk; /* When I2S mode and master, the framesync rate. */
+        int dsp_master_clk; /* When DSP mode and master, the framesync rate. */
+        bool dma_on;
+        unsigned long i2s_clk_rate;
+        const char *dap_clk;
+        const char *audio_sync_clk;
+
+        int mode; /* I2S, LJM, RJM, etc. */
+        int fifo_fmt;
+        int bit_size;
+        int i2s_bus_width; /* 32-bit for 16-bit packed I2S */
+        int dsp_bus_width; /* 16-bit for DSP data format */
+        int mask; /* enable tx and rx? */
+        bool stereo_capture; /* True if hardware supports stereo */
+        void *driver_data;
+};
+
+#endif /* __ARCH_ARM_MACH_TEGRA_AUDIO_H */
diff --git a/arch/arm/mach-tegra/include/mach/csi.h b/arch/arm/mach-tegra/include/mach/csi.h
new file mode 100644
index 00000000000..575de6fb497
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/csi.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-tegra/include/mach/csi.h
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_CSI_H
+#define __MACH_TEGRA_CSI_H
+
+#define CSI_CILA_MIPI_CAL_CONFIG_0 0x22a
+#define  MIPI_CAL_TERMOSA(x)            (((x) & 0x1f) << 0)
+
+#define CSI_CILB_MIPI_CAL_CONFIG_0 0x22b
+#define  MIPI_CAL_TERMOSB(x)            (((x) & 0x1f) << 0)
+
+#define CSI_CIL_PAD_CONFIG 0x229
+#define  PAD_CIL_PDVREG(x)              (((x) & 0x01) << 1)
+
+#define CSI_DSI_MIPI_CAL_CONFIG 0x234
+#define  MIPI_CAL_HSPDOSD(x)            (((x) & 0x1f) << 16)
+#define  MIPI_CAL_HSPUOSD(x)            (((x) & 0x1f) << 8)
+
+#define CSI_MIPIBIAS_PAD_CONFIG 0x235
+#define  PAD_DRIV_DN_REF(x)             (((x) & 0x7) << 16)
+#define  PAD_DRIV_UP_REF(x)             (((x) & 0x7) << 8)
+
+int tegra_vi_csi_readl(u32 offset, u32 *val);
+int tegra_vi_csi_writel(u32 value, u32 offset);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
new file mode 100644
index 00000000000..a5f7210f2b2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -0,0 +1,570 @@
+/*
+ * arch/arm/mach-tegra/include/mach/dc.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Erik Gilling <konkers@google.com>
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_DC_H
+#define __MACH_TEGRA_DC_H
+
+#include <linux/pm.h>
+#include <linux/types.h>
+#include <drm/drm_fixed.h>
+
+#define TEGRA_MAX_DC            2
+#define DC_N_WINDOWS            3
+
+
+/* DSI pixel data format */
+enum {
+        TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
+        TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
+        TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
+        TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
+};
+
+/* DSI virtual channel number */
+enum {
+        TEGRA_DSI_VIRTUAL_CHANNEL_0,
+        TEGRA_DSI_VIRTUAL_CHANNEL_1,
+        TEGRA_DSI_VIRTUAL_CHANNEL_2,
+        TEGRA_DSI_VIRTUAL_CHANNEL_3,
+};
+
+/* DSI transmit method for video data */
+enum {
+        TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
+        TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
+};
+
+/* DSI HS clock mode */
+enum {
+        TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
+        TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
+};
+
+/* DSI burst mode setting in video mode. Each mode is assigned with a
+ * fixed value. The rationale behind this is to avoid change of these
+ * values, since the calculation of dsi clock depends on them. */
+enum {
+        TEGRA_DSI_VIDEO_NONE_BURST_MODE = 0,
+        TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END = 1,
+        TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
+        TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
+        TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
+        TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
+        TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
+};
+
+enum {
+        TEGRA_DSI_PACKET_CMD,
+        TEGRA_DSI_DELAY_MS,
+};
+
+struct tegra_dsi_cmd {
+        u8      cmd_type;
+        u8      data_id;
+        union {
+                u16 data_len;
+                u16 delay_ms;
+                struct {
+                        u8 data0;
+                        u8 data1;
+                } sp;
+        } sp_len_dly;
+        u8      *pdata;
+};
+
+#define DSI_CMD_SHORT(di, p0, p1)       { \
+                                        .cmd_type = TEGRA_DSI_PACKET_CMD, \
+                                        .data_id = di, \
+                                        .sp_len_dly.sp.data0 = p0, \
+                                        .sp_len_dly.sp.data1 = p1, \
+                                        }
+#define DSI_DLY_MS(ms)  { \
+                        .cmd_type = TEGRA_DSI_DELAY_MS, \
+                        .sp_len_dly.delay_ms = ms, \
+                        }
+
+#define DSI_CMD_LONG(di, ptr)   { \
+                                .cmd_type = TEGRA_DSI_PACKET_CMD, \
+                                .data_id = di, \
+                                .sp_len_dly.data_len = ARRAY_SIZE(ptr), \
+                                .pdata = ptr, \
+                                }
+
+struct dsi_phy_timing_ns {
+        u16             t_hsdexit_ns;
+        u16             t_hstrail_ns;
+        u16             t_datzero_ns;
+        u16             t_hsprepare_ns;
+
+        u16             t_clktrail_ns;
+        u16             t_clkpost_ns;
+        u16             t_clkzero_ns;
+        u16             t_tlpx_ns;
+
+        u16             t_clkprepare_ns;
+        u16             t_clkpre_ns;
+        u16             t_wakeup_ns;
+
+        u16             t_taget_ns;
+        u16             t_tasure_ns;
+        u16             t_tago_ns;
+};
+
+struct tegra_dsi_out {
+        u8              n_data_lanes;                   /* required */
+        u8              pixel_format;                   /* required */
+        u8              refresh_rate;                   /* required */
+        u8              rated_refresh_rate;
+        u8              panel_reset;                    /* required */
+        u8              virtual_channel;                /* required */
+        u8              dsi_instance;
+        u8              chip_id;
+        u8              chip_rev;
+
+        bool            panel_has_frame_buffer; /* required*/
+
+        struct tegra_dsi_cmd    *dsi_init_cmd;          /* required */
+        u16             n_init_cmd;                     /* required */
+
+        struct tegra_dsi_cmd    *dsi_early_suspend_cmd;
+        u16             n_early_suspend_cmd;
+
+        struct tegra_dsi_cmd    *dsi_late_resume_cmd;
+        u16             n_late_resume_cmd;
+
+        struct tegra_dsi_cmd    *dsi_suspend_cmd;       /* required */
+        u16             n_suspend_cmd;                  /* required */
+
+        u8              video_data_type;                /* required */
+        u8              video_clock_mode;
+        u8              video_burst_mode;
+
+        u16             panel_buffer_size_byte;
+        u16             panel_reset_timeout_msec;
+
+        bool            hs_cmd_mode_supported;
+        bool            hs_cmd_mode_on_blank_supported;
+        bool            enable_hs_clock_on_lp_cmd_mode;
+        bool            no_pkt_seq_eot; /* 1st generation panel may not
+                                         * support eot. Don't set it for
+                                         * most panels. */
+        bool            te_polarity_low;
+        bool            power_saving_suspend;
+
+        u32             max_panel_freq_khz;
+        u32             lp_cmd_mode_freq_khz;
+        u32             lp_read_cmd_mode_freq_khz;
+        u32             hs_clk_in_lp_cmd_mode_freq_khz;
+        u32             burst_mode_freq_khz;
+
+        struct dsi_phy_timing_ns phy_timing;
+};
+
+enum {
+        TEGRA_DC_STEREO_MODE_2D,
+        TEGRA_DC_STEREO_MODE_3D
+};
+
+enum {
+        TEGRA_DC_STEREO_LANDSCAPE,
+        TEGRA_DC_STEREO_PORTRAIT
+};
+
+struct tegra_stereo_out {
+        int  mode_2d_3d;
+        int  orientation;
+
+        void (*set_mode)(int mode);
+        void (*set_orientation)(int orientation);
+};
+
+struct tegra_dc_mode {
+        int     pclk;
+        int     rated_pclk;
+        int     h_ref_to_sync;
+        int     v_ref_to_sync;
+        int     h_sync_width;
+        int     v_sync_width;
+        int     h_back_porch;
+        int     v_back_porch;
+        int     h_active;
+        int     v_active;
+        int     h_front_porch;
+        int     v_front_porch;
+        int     stereo_mode;
+        u32     flags;
+};
+
+#define TEGRA_DC_MODE_FLAG_NEG_V_SYNC   (1 << 0)
+#define TEGRA_DC_MODE_FLAG_NEG_H_SYNC   (1 << 1)
+
+enum {
+        TEGRA_DC_OUT_RGB,
+        TEGRA_DC_OUT_HDMI,
+        TEGRA_DC_OUT_DSI,
+};
+
+struct tegra_dc_out_pin {
+        int     name;
+        int     pol;
+};
+
+enum {
+        TEGRA_DC_OUT_PIN_DATA_ENABLE,
+        TEGRA_DC_OUT_PIN_H_SYNC,
+        TEGRA_DC_OUT_PIN_V_SYNC,
+        TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
+};
+
+enum {
+        TEGRA_DC_OUT_PIN_POL_LOW,
+        TEGRA_DC_OUT_PIN_POL_HIGH,
+};
+
+enum {
+        TEGRA_DC_DISABLE_DITHER = 1,
+        TEGRA_DC_ORDERED_DITHER,
+        TEGRA_DC_ERRDIFF_DITHER,
+};
+
+typedef u8 tegra_dc_bl_output[256];
+typedef u8 *p_tegra_dc_bl_output;
+
+struct tegra_dc_sd_blp {
+        u16 time_constant;
+        u8 step;
+};
+
+struct tegra_dc_sd_fc {
+        u8 time_limit;
+        u8 threshold;
+};
+
+struct tegra_dc_sd_rgb {
+        u8 r;
+        u8 g;
+        u8 b;
+};
+
+struct tegra_dc_sd_agg_priorities {
+        u8 pri_lvl;
+        u8 agg[4];
+};
+
+struct tegra_dc_sd_settings {
+        unsigned enable;
+        bool use_auto_pwm;
+        u8 hw_update_delay;
+        u8 aggressiveness;
+        short bin_width;
+        u8 phase_in_settings;
+        u8 phase_in_adjustments;
+        u8 cmd;
+        u8 final_agg;
+        u16 cur_agg_step;
+        u16 phase_settings_step;
+        u16 phase_adj_step;
+        u16 num_phase_in_steps;
+
+        struct tegra_dc_sd_agg_priorities agg_priorities;
+
+        bool use_vid_luma;
+        struct tegra_dc_sd_rgb coeff;
+
+        struct tegra_dc_sd_fc fc;
+        struct tegra_dc_sd_blp blp;
+        u8 bltf[4][4][4];
+        struct tegra_dc_sd_rgb lut[4][9];
+
+        atomic_t *sd_brightness;
+        struct platform_device *bl_device;
+};
+
+enum {
+        NO_CMD = 0x0,
+        ENABLE = 0x1,
+        DISABLE = 0x2,
+        PHASE_IN = 0x4,
+        AGG_CHG = 0x8,
+};
+
+enum {
+        TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
+        TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
+        TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
+        TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
+        TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
+
+        TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
+        TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
+        TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
+
+        TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
+        TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
+        TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
+        TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
+};
+
+struct tegra_dc_out {
+        int                             type;
+        unsigned                        flags;
+
+        /* size in mm */
+        unsigned                        h_size;
+        unsigned                        v_size;
+
+        int                             dcc_bus;
+        int                             hotplug_gpio;
+        const char                      *parent_clk;
+        const char                      *parent_clk_backup;
+
+        unsigned                        max_pixclock;
+        unsigned                        order;
+        unsigned                        align;
+        unsigned                        depth;
+        unsigned                        dither;
+
+        struct tegra_dc_mode            *modes;
+        int                             n_modes;
+
+        struct tegra_dsi_out            *dsi;
+        struct tegra_stereo_out         *stereo;
+
+        unsigned                        height; /* mm */
+        unsigned                        width; /* mm */
+
+        struct tegra_dc_out_pin         *out_pins;
+        unsigned                        n_out_pins;
+
+        struct tegra_dc_sd_settings     *sd_settings;
+
+        u8                      *out_sel_configs;
+        unsigned                n_out_sel_configs;
+
+        int     (*enable)(void);
+        int     (*postpoweron)(void);
+        int     (*disable)(void);
+
+        int     (*hotplug_init)(void);
+        int     (*postsuspend)(void);
+};
+
+/* bits for tegra_dc_out.flags */
+#define TEGRA_DC_OUT_HOTPLUG_HIGH               (0 << 1)
+#define TEGRA_DC_OUT_HOTPLUG_LOW                (1 << 1)
+#define TEGRA_DC_OUT_HOTPLUG_MASK               (1 << 1)
+#define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON    (0 << 2)
+#define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND    (1 << 2)
+#define TEGRA_DC_OUT_NVHDCP_POLICY_MASK         (1 << 2)
+#define TEGRA_DC_OUT_CONTINUOUS_MODE            (0 << 3)
+#define TEGRA_DC_OUT_ONE_SHOT_MODE              (1 << 3)
+#define TEGRA_DC_OUT_N_SHOT_MODE                (1 << 4)
+
+#define TEGRA_DC_ALIGN_MSB              0
+#define TEGRA_DC_ALIGN_LSB              1
+
+#define TEGRA_DC_ORDER_RED_BLUE         0
+#define TEGRA_DC_ORDER_BLUE_RED         1
+
+struct tegra_dc;
+struct nvmap_handle_ref;
+
+struct tegra_dc_csc {
+        unsigned short yof;
+        unsigned short kyrgb;
+        unsigned short kur;
+        unsigned short kvr;
+        unsigned short kug;
+        unsigned short kvg;
+        unsigned short kub;
+        unsigned short kvb;
+};
+
+/* palette lookup table */
+struct tegra_dc_lut {
+        u8 r[256];
+        u8 g[256];
+        u8 b[256];
+};
+
+struct tegra_dc_win {
+        u8                      idx;
+        u8                      fmt;
+        u8                      ppflags; /* see TEGRA_WIN_PPFLAG* */
+        u32                     flags;
+
+        void                    *virt_addr;
+        dma_addr_t              phys_addr;
+        dma_addr_t              phys_addr_u;
+        dma_addr_t              phys_addr_v;
+        unsigned                stride;
+        unsigned                stride_uv;
+        fixed20_12              x;
+        fixed20_12              y;
+        fixed20_12              w;
+        fixed20_12              h;
+        unsigned                out_x;
+        unsigned                out_y;
+        unsigned                out_w;
+        unsigned                out_h;
+        unsigned                z;
+
+        struct tegra_dc_csc     csc;
+
+        int                     dirty;
+        int                     underflows;
+        struct tegra_dc         *dc;
+
+        struct nvmap_handle_ref *cur_handle;
+        unsigned                bandwidth;
+        unsigned                new_bandwidth;
+        struct tegra_dc_lut     lut;
+};
+
+#define TEGRA_WIN_PPFLAG_CP_ENABLE      (1 << 0) /* enable RGB color lut */
+#define TEGRA_WIN_PPFLAG_CP_FBOVERRIDE  (1 << 1) /* override fbdev color lut */
+
+#define TEGRA_WIN_FLAG_ENABLED          (1 << 0)
+#define TEGRA_WIN_FLAG_BLEND_PREMULT    (1 << 1)
+#define TEGRA_WIN_FLAG_BLEND_COVERAGE   (1 << 2)
+#define TEGRA_WIN_FLAG_INVERT_H         (1 << 3)
+#define TEGRA_WIN_FLAG_INVERT_V         (1 << 4)
+#define TEGRA_WIN_FLAG_TILED            (1 << 5)
+#define TEGRA_WIN_FLAG_H_FILTER         (1 << 6)
+#define TEGRA_WIN_FLAG_V_FILTER         (1 << 7)
+
+
+#define TEGRA_WIN_BLEND_FLAGS_MASK \
+        (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
+
+/* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
+ * and may change in new tegra architectures.
+ */
+#define TEGRA_WIN_FMT_P1                0
+#define TEGRA_WIN_FMT_P2                1
+#define TEGRA_WIN_FMT_P4                2
+#define TEGRA_WIN_FMT_P8                3
+#define TEGRA_WIN_FMT_B4G4R4A4          4
+#define TEGRA_WIN_FMT_B5G5R5A           5
+#define TEGRA_WIN_FMT_B5G6R5            6
+#define TEGRA_WIN_FMT_AB5G5R5           7
+#define TEGRA_WIN_FMT_B8G8R8A8          12
+#define TEGRA_WIN_FMT_R8G8B8A8          13
+#define TEGRA_WIN_FMT_B6x2G6x2R6x2A8    14
+#define TEGRA_WIN_FMT_R6x2G6x2B6x2A8    15
+#define TEGRA_WIN_FMT_YCbCr422          16
+#define TEGRA_WIN_FMT_YUV422            17
+#define TEGRA_WIN_FMT_YCbCr420P         18
+#define TEGRA_WIN_FMT_YUV420P           19
+#define TEGRA_WIN_FMT_YCbCr422P         20
+#define TEGRA_WIN_FMT_YUV422P           21
+#define TEGRA_WIN_FMT_YCbCr422R         22
+#define TEGRA_WIN_FMT_YUV422R           23
+#define TEGRA_WIN_FMT_YCbCr422RA        24
+#define TEGRA_WIN_FMT_YUV422RA          25
+
+struct tegra_fb_data {
+        int             win;
+
+        int             xres;
+        int             yres;
+        int             bits_per_pixel; /* -1 means autodetect */
+
+        unsigned long   flags;
+};
+
+#define TEGRA_FB_FLIP_ON_PROBE          (1 << 0)
+
+struct tegra_dc_platform_data {
+        unsigned long           flags;
+        unsigned long           emc_clk_rate;
+        struct tegra_dc_out     *default_out;
+        struct tegra_fb_data    *fb;
+};
+
+#define TEGRA_DC_FLAG_ENABLED           (1 << 0)
+
+struct tegra_dc *tegra_dc_get_dc(unsigned idx);
+struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
+bool tegra_dc_get_connected(struct tegra_dc *);
+
+void tegra_dc_blank(struct tegra_dc *dc);
+
+void tegra_dc_enable(struct tegra_dc *dc);
+void tegra_dc_disable(struct tegra_dc *dc);
+
+u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i);
+u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i);
+void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val);
+
+/* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
+ * with differenct dcs in one call
+ */
+int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
+int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
+
+int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
+struct fb_videomode;
+int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
+        bool stereo_mode);
+
+unsigned tegra_dc_get_out_height(const struct tegra_dc *dc);
+unsigned tegra_dc_get_out_width(const struct tegra_dc *dc);
+unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc);
+
+/* PM0 and PM1 signal control */
+#define TEGRA_PWM_PM0 0
+#define TEGRA_PWM_PM1 1
+
+struct tegra_dc_pwm_params {
+        int which_pwm;
+        void (*switch_to_sfio)(int);
+        int gpio_conf_to_sfio;
+        unsigned int period;
+        unsigned int clk_div;
+        unsigned int clk_select;
+        unsigned int duty_cycle;
+};
+
+void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
+
+int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len);
+void tegra_dc_host_trigger(struct tegra_dc *dc);
+
+int tegra_dc_update_csc(struct tegra_dc *dc, int win_index);
+
+int tegra_dc_update_lut(struct tegra_dc *dc, int win_index, int fboveride);
+
+/*
+ * In order to get a dc's current EDID, first call tegra_dc_get_edid() from an
+ * interruptible context.  The returned value (if non-NULL) points to a
+ * snapshot of the current state; after copying data from it, call
+ * tegra_dc_put_edid() on that pointer.  Do not dereference anything through
+ * that pointer after calling tegra_dc_put_edid().
+ */
+struct tegra_dc_edid {
+        size_t          len;
+        u8              buf[0];
+};
+struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc);
+void tegra_dc_put_edid(struct tegra_dc_edid *edid);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
new file mode 100644
index 00000000000..e0ebe65c165
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-tegra/include/mach/debug-macro.S
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/io.h>
+#include <mach/iomap.h>
+
+        .macro  addruart, rp, rv
+        ldr     \rp, =IO_APB_PHYS       @ physical
+        ldr     \rv, =IO_APB_VIRT        @ virtual
+        orr     \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
+        orr     \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
+        orr     \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF)
+        orr     \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
+
diff --git a/arch/arm/mach-tegra/include/mach/delay.h b/arch/arm/mach-tegra/include/mach/delay.h
new file mode 100644
index 00000000000..2defb7b9b65
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/delay.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-tegra/include/mach/delay.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *  Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MACH_TEGRA_DELAY_H
+#define __MACH_TEGRA_DELAY_H
+
+/* needed by loops_per_jiffy calculations */
+extern void __delay(int loops);
+
+extern void __udelay(unsigned long usecs);
+extern void __const_udelay(unsigned long usecs);
+
+/* we don't have any restrictions on maximum udelay length, but we'll enforce
+ * the same restriction as the ARM default so we don't introduce any
+ * incompatibilties in drivers.
+ */
+extern void __bad_udelay(void);
+
+#define MAX_UDELAY_MS 2
+
+#define udelay(n)                                                       \
+        ((__builtin_constant_p(n) && (n) > (MAX_UDELAY_MS * 1000)) ?    \
+                __bad_udelay() :                                        \
+                __udelay(n))
+
+#endif /* defined(__MACH_TEGRA_DELAY_H) */
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
new file mode 100644
index 00000000000..0b0a5d9fd1d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -0,0 +1,202 @@
+/*
+ * arch/arm/mach-tegra/include/mach/dma.h
+ *
+ * Copyright (c) 2008-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_DMA_H
+#define __MACH_TEGRA_DMA_H
+
+#include <linux/list.h>
+
+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
+
+struct tegra_dma_req;
+struct tegra_dma_channel;
+
+#define TEGRA_DMA_REQ_SEL_CNTR                  0
+#define TEGRA_DMA_REQ_SEL_I2S_2                 1
+#define TEGRA_DMA_REQ_SEL_APBIF_CH0             TEGRA_DMA_REQ_SEL_I2S_2
+#define TEGRA_DMA_REQ_SEL_I2S_1                 2
+#define TEGRA_DMA_REQ_SEL_APBIF_CH1             TEGRA_DMA_REQ_SEL_I2S_1
+#define TEGRA_DMA_REQ_SEL_SPD_I                 3
+#define TEGRA_DMA_REQ_SEL_APBIF_CH2             TEGRA_DMA_REQ_SEL_SPD_I
+#define TEGRA_DMA_REQ_SEL_UI_I                  4
+#define TEGRA_DMA_REQ_SEL_APBIF_CH3             TEGRA_DMA_REQ_SEL_UI_I
+#define TEGRA_DMA_REQ_SEL_MIPI                  5
+#define TEGRA_DMA_REQ_SEL_I2S2_2                6
+#define TEGRA_DMA_REQ_SEL_I2S2_1                7
+#define TEGRA_DMA_REQ_SEL_UARTA                 8
+#define TEGRA_DMA_REQ_SEL_UARTB                 9
+#define TEGRA_DMA_REQ_SEL_UARTC                 10
+#define TEGRA_DMA_REQ_SEL_SPI                   11
+#define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
+#define TEGRA_DMA_REQ_SEL_AC97                  12
+#define TEGRA_DMA_REQ_SEL_ACMODEM               13
+#define TEGRA_DMA_REQ_SEL_SL4B                  14
+#define TEGRA_DMA_REQ_SEL_SL2B1                 15
+#define TEGRA_DMA_REQ_SEL_SL2B2                 16
+#define TEGRA_DMA_REQ_SEL_SL2B3                 17
+#define TEGRA_DMA_REQ_SEL_SL2B4                 18
+#define TEGRA_DMA_REQ_SEL_UARTD                 19
+#define TEGRA_DMA_REQ_SEL_UARTE                 20
+#define TEGRA_DMA_REQ_SEL_I2C                   21
+#define TEGRA_DMA_REQ_SEL_I2C2                  22
+#define TEGRA_DMA_REQ_SEL_I2C3                  23
+#define TEGRA_DMA_REQ_SEL_DVC_I2C               24
+#define TEGRA_DMA_REQ_SEL_OWR                   25
+#define TEGRA_DMA_REQ_SEL_I2C4                  26
+#define TEGRA_DMA_REQ_SEL_SL2B5                 27
+#define TEGRA_DMA_REQ_SEL_SL2B6                 28
+#define TEGRA_DMA_REQ_SEL_INVALID               31
+
+enum tegra_dma_mode {
+        TEGRA_DMA_SHARED = 1,
+        TEGRA_DMA_MODE_CONTINUOUS = 2,
+        TEGRA_DMA_MODE_CONTINUOUS_DOUBLE = TEGRA_DMA_MODE_CONTINUOUS,
+        TEGRA_DMA_MODE_CONTINUOUS_SINGLE = 4,
+        TEGRA_DMA_MODE_ONESHOT = 8,
+};
+
+/*
+ * tegra_dma_req_status: Dma request status
+ * TEGRA_DMA_REQ_SUCCESS: The request has been successfully completed.
+ *              The byte_transferred tells number of bytes transferred.
+ * TEGRA_DMA_REQ_ERROR_ABORTED: The request is aborted by client after
+ *              calling tegra_dma_dequeue_req.
+ *              The byte_transferred tells number of bytes transferred
+ *              which may be more than request size due to buffer
+ *              wrap-up in continuous mode.
+ * TEGRA_DMA_REQ_ERROR_STOPPED: Applicable in continuous mode.
+ *              The request is stopped forcefully. This may be becasue of
+ *              - due to non-available of next request.
+ *              - not able to serve current interrupt before next buffer
+ *                completed by dma. This can happen if buffer req size is
+ *                not enough and it transfer completes before system actually
+ *                serve the previous dma interrupts.
+ *              The byte_transferred will not be accurate in this case. It will
+ *              just give an idea that how much approximately have been
+ *              transferred by dma.
+ * TEGRA_DMA_REQ_INFLIGHT: The request is configured in the dma register
+ *              for transfer.
+ */
+
+enum tegra_dma_req_status {
+        TEGRA_DMA_REQ_SUCCESS = 0,
+        TEGRA_DMA_REQ_ERROR_ABORTED,
+        TEGRA_DMA_REQ_ERROR_STOPPED,
+        TEGRA_DMA_REQ_INFLIGHT,
+};
+
+enum tegra_dma_req_buff_status {
+        TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
+        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
+        TEGRA_DMA_REQ_BUF_STATUS_FULL,
+};
+
+typedef void (*dma_callback)(struct tegra_dma_req *req);
+
+struct tegra_dma_req {
+        struct list_head node;
+        unsigned int modid;
+        int instance;
+
+        /* Called when the req is complete and from the DMA ISR context.
+         * When this is called the req structure is no longer queued by
+         * the DMA channel.
+         *
+         * State of the DMA depends on the number of req it has. If there are
+         * no DMA requests queued up, then it will STOP the DMA. It there are
+         * more requests in the DMA, then it will queue the next request.
+         */
+        dma_callback complete;
+
+        /*  This is a called from the DMA ISR context when the DMA is still in
+         *  progress and is actively filling same buffer.
+         *
+         *  In case of continuous mode receive, this threshold is 1/2 the buffer
+         *  size. In other cases, this will not even be called as there is no
+         *  hardware support for it.
+         *
+         * In the case of continuous mode receive, if there is next req already
+         * queued, DMA programs the HW to use that req when this req is
+         * completed. If there is no "next req" queued, then DMA ISR doesn't do
+         * anything before calling this callback.
+         *
+         *      This is mainly used by the cases, where the clients has queued
+         *      only one req and want to get some sort of DMA threshold
+         *      callback to program the next buffer.
+         *
+         */
+        dma_callback threshold;
+
+        /* 1 to copy to memory.
+         * 0 to copy from the memory to device FIFO */
+        int to_memory;
+
+        void *virt_addr;
+
+        unsigned long source_addr;
+        unsigned long dest_addr;
+        unsigned long dest_wrap;
+        unsigned long source_wrap;
+        unsigned long source_bus_width;
+        unsigned long dest_bus_width;
+        unsigned long req_sel;
+        unsigned int size;
+
+        int fixed_burst_size; /* only for dtv */
+
+        /* Updated by the DMA driver on the conpletion of the request. */
+        int bytes_transferred;
+        int status;
+
+        /* DMA completion tracking information */
+        int buffer_status;
+
+        /* Client specific data */
+        void *dev;
+};
+
+int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+void tegra_dma_flush(struct tegra_dma_channel *ch);
+
+bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req);
+int tegra_dma_get_transfer_count(struct tegra_dma_channel *ch,
+                        struct tegra_dma_req *req);
+bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
+
+struct tegra_dma_channel *tegra_dma_allocate_channel(int mode,
+                const char namefmt[], ...);
+void tegra_dma_free_channel(struct tegra_dma_channel *ch);
+int tegra_dma_cancel(struct tegra_dma_channel *ch);
+
+int __init tegra_dma_init(void);
+
+#else /* !defined(CONFIG_TEGRA_SYSTEM_DMA) */
+static inline int tegra_dma_init(void)
+{
+        return 0;
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/edp.h b/arch/arm/mach-tegra/include/mach/edp.h
new file mode 100644
index 00000000000..48321cae495
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/edp.h
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/mach-tegra/include/mach/edp.h
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_EDP_H
+#define __MACH_EDP_H
+
+#include <linux/debugfs.h>
+
+struct tegra_edp_entry {
+        char speedo_id;
+        char regulator_100mA;
+        char temperature;
+        char freq_limits[4];
+};
+
+struct tegra_edp_limits {
+        int temperature;
+        unsigned int freq_limits[4];
+};
+
+struct system_edp_entry {
+        char speedo_id;
+        char power_limit_100mW;
+        char freq_limits[4];
+};
+
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+
+
+int tegra_edp_update_thermal_zone(int temperature);
+void tegra_init_cpu_edp_limits(unsigned int regulator_mA);
+void tegra_init_system_edp_limits(unsigned int power_limit_mW);
+void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size);
+unsigned int tegra_get_edp_limit(void);
+void tegra_get_system_edp_limits(const unsigned int **limits);
+int tegra_system_edp_alarm(bool alarm);
+
+#else
+static inline void tegra_init_cpu_edp_limits(int regulator_mA)
+{}
+static inline void tegra_init_system_edp_limits(int power_limit_mW)
+{}
+static inline int tegra_edp_update_thermal_zone(int temperature)
+{ return -1; }
+static inline void tegra_get_cpu_edp_limits(struct tegra_edp_limits **limits,
+                                            int *size)
+{}
+static inline unsigned int tegra_get_edp_limit(void)
+{ return -1; }
+static inline void tegra_get_system_edp_limits(unsigned int **limits)
+{}
+static inline int tegra_system_edp_alarm(bool alarm)
+{ return -1; }
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static inline void tegra_edp_throttle_cpu_now(u8 factor)
+{}
+#else
+void tegra_edp_throttle_cpu_now(u8 factor);
+#endif
+
+#endif  /* __MACH_EDP_H */
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
new file mode 100644
index 00000000000..50d1b212da2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
+/* arch/arm/mach-tegra/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 Palm, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <mach/iomap.h>
+#include <mach/io.h>
+
+#if defined(CONFIG_ARM_GIC)
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
+
+        /* Uses the GIC interrupt controller built into the cpu */
+#define ICTRL_BASE (IO_CPU_VIRT + 0x40100)
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        movw \base, #(ICTRL_BASE & 0x0000ffff)
+        movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+#else
+#error "Unsupported configuration"
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/fb.h b/arch/arm/mach-tegra/include/mach/fb.h
new file mode 100644
index 00000000000..ced6f9c2cb4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/fb.h
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-tegra/include/mach/fb.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_FB_H
+#define __MACH_TEGRA_FB_H
+
+#include <linux/fb.h>
+
+struct nvhost_device;
+struct tegra_dc;
+struct tegra_fb_data;
+struct tegra_fb_info;
+struct resource;
+
+#ifdef CONFIG_FB_TEGRA
+struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev,
+                                        struct tegra_dc *dc,
+                                        struct tegra_fb_data *fb_data,
+                                        struct resource *fb_mem);
+void tegra_fb_unregister(struct tegra_fb_info *fb_info);
+void tegra_fb_update_monspecs(struct tegra_fb_info *fb_info,
+                              struct fb_monspecs *specs,
+                              bool (*mode_filter)(const struct tegra_dc *dc,
+                                                  struct fb_videomode *mode));
+#else
+static inline struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev,
+                                                      struct tegra_dc *dc,
+                                                      struct tegra_fb_data *fb_data,
+                                                      struct resource *fb_mem)
+{
+        return NULL;
+}
+
+static inline void tegra_fb_unregister(struct tegra_fb_info *fb_info)
+{
+}
+
+static inline void tegra_fb_update_monspecs(struct tegra_fb_info *fb_info,
+                                            struct fb_monspecs *specs,
+                                            bool (*mode_filter)(struct fb_videomode *mode))
+{
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/fiq.h b/arch/arm/mach-tegra/include/mach/fiq.h
new file mode 100644
index 00000000000..17625facf62
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/fiq.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ASM_ARCH_TEGRA_FIQ_H
+#define __ASM_ARCH_TEGRA_FIQ_H
+
+/* enable/disable an interrupt that is an FIQ (safe from FIQ context?) */
+void tegra_fiq_enable(int n);
+void tegra_fiq_disable(int n);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
new file mode 100644
index 00000000000..b7357ab0c4d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/gpio.h
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/mach-tegra/include/mach/gpio.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_GPIO_H
+#define __MACH_TEGRA_GPIO_H
+
+#include <linux/init.h>
+#include <mach/irqs.h>
+
+#define TEGRA_NR_GPIOS          INT_GPIO_NR
+#define ARCH_NR_GPIOS           (TEGRA_NR_GPIOS + 128)
+
+#include <asm-generic/gpio.h>
+#include "pinmux.h"
+
+struct gpio_init_pin_info {
+        char name[16];
+        int gpio_nr;
+        bool is_gpio;
+        bool is_input;
+        int value; /* Value if it is output*/
+};
+
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+
+#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio))
+#define TEGRA_IRQ_TO_GPIO(irq) ((irq) - INT_GPIO_BASE)
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        /* SOC gpio */
+        if (gpio < TEGRA_NR_GPIOS)
+                return INT_GPIO_BASE + gpio;
+
+        /* For non soc gpio, the external peripheral driver need to
+         * provide the implementation */
+        return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        /* SOC gpio */
+        if ((irq >= INT_GPIO_BASE) && (irq < INT_GPIO_BASE + INT_GPIO_NR))
+                return irq - INT_GPIO_BASE;
+
+        /* we don't supply reverse mappings for non-SOC gpios */
+        return -EIO;
+}
+
+struct tegra_gpio_table {
+        int     gpio;   /* GPIO number */
+        bool    enable; /* Enable for GPIO at init? */
+};
+
+void tegra_gpio_config(struct tegra_gpio_table *table, int num);
+void tegra_gpio_enable(int gpio);
+void tegra_gpio_disable(int gpio);
+int tegra_gpio_resume_init(void);
+void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value);
+void tegra_gpio_set_tristate(int gpio, enum tegra_tristate ts);
+int tegra_gpio_get_bank_int_nr(int gpio);
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpufuse.h b/arch/arm/mach-tegra/include/mach/gpufuse.h
new file mode 100644
index 00000000000..4aa6cb66d5d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/gpufuse.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-tegra/include/mach/gpufuse.h
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* Number of register sets to handle in host context switching */
+int tegra_gpu_register_sets(void);
+
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
new file mode 100644
index 00000000000..92600f75fd4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corp.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MACH_TEGRA_HARDWARE_H
+#define MACH_TEGRA_HARDWARE_H
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define pcibios_assign_all_busses()             1
+
+#else
+
+#define pcibios_assign_all_busses()             0
+#endif
+
+enum tegra_chipid {
+        TEGRA_CHIPID_UNKNOWN = 0,
+        TEGRA_CHIPID_TEGRA2 = 0x20,
+        TEGRA_CHIPID_TEGRA3 = 0x30,
+};
+
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_A04p,
+        TEGRA_REVISION_MAX,
+};
+
+enum tegra_chipid tegra_get_chipid(void);
+enum tegra_revision tegra_get_revision(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/hdmi-audio.h b/arch/arm/mach-tegra/include/mach/hdmi-audio.h
new file mode 100644
index 00000000000..7d760690081
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hdmi-audio.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-tegra/include/mach/hdmi-audio.h
+ *
+ * Copyright (c) 2008-2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_HDMI_AUDIO_H
+#define __MACH_TEGRA_HDMI_AUDIO_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+enum {
+        AUDIO_FREQ_32K = 32000,
+        AUDIO_FREQ_44_1K = 44100,
+        AUDIO_FREQ_48K = 48000,
+        AUDIO_FREQ_88_2K = 88200,
+        AUDIO_FREQ_96K = 96000,
+        AUDIO_FREQ_176_4K = 176400,
+        AUDIO_FREQ_192K = 192000,
+};
+
+enum {
+        AUTO = 0,
+        SPDIF,
+        HDA,
+};
+
+int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source);
+int tegra_hdmi_setup_hda_presence(void);
+
+#endif /* __MACH_TEGRA_HDMI_AUDIO_H */
diff --git a/arch/arm/mach-tegra/include/mach/i2s.h b/arch/arm/mach-tegra/include/mach/i2s.h
new file mode 100644
index 00000000000..42cce885cda
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/i2s.h
@@ -0,0 +1,316 @@
+/*
+ * arch/arm/mach-tegra/include/mach/i2s.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_TEGRA_I2S_H
+#define __ARCH_ARM_MACH_TEGRA_I2S_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+
+/* Offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */
+
+#define I2S_I2S_CTRL_0                  0
+#define I2S_I2S_STATUS_0                4
+#define I2S_I2S_TIMING_0                8
+#define I2S_I2S_FIFO_SCR_0              0x0c
+#define I2S_I2S_PCM_CTRL_0              0x10
+#define I2S_I2S_NW_CTRL_0               0x14
+#define I2S_I2S_TDM_CTRL_0              0x20
+#define I2S_I2S_TDM_TX_RX_CTRL_0        0x24
+#define I2S_I2S_FIFO1_0                 0x40
+#define I2S_I2S_FIFO2_0                 0x80
+
+/*
+ * I2S_I2S_CTRL_0
+ */
+
+#define I2S_I2S_CTRL_FIFO2_TX_ENABLE            (1<<30)
+#define I2S_I2S_CTRL_FIFO1_ENABLE               (1<<29)
+#define I2S_I2S_CTRL_FIFO2_ENABLE               (1<<28)
+#define I2S_I2S_CTRL_FIFO1_RX_ENABLE            (1<<27)
+#define I2S_I2S_CTRL_FIFO_LPBK_ENABLE           (1<<26)
+#define I2S_I2S_CTRL_MASTER_ENABLE              (1<<25)
+#define I2S_I2S_CTRL_L_R_CTRL                   (1<<24) /* 0 = L/R: low/high */
+
+#define I2S_BIT_FORMAT_I2S 0
+#define I2S_BIT_FORMAT_RJM 1
+#define I2S_BIT_FORMAT_LJM 2
+#define I2S_BIT_FORMAT_DSP 3
+#define I2S_BIT_FORMAT_SHIFT 10
+
+#define I2S_I2S_CTRL_BIT_FORMAT_MASK            (3<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_I2S             (I2S_BIT_FORMAT_I2S<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_RJM             (I2S_BIT_FORMAT_RJM<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_LJM             (I2S_BIT_FORMAT_LJM<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_DSP             (I2S_BIT_FORMAT_DSP<<10)
+
+#define I2S_BIT_SIZE_16 0
+#define I2S_BIT_SIZE_20 1
+#define I2S_BIT_SIZE_24 2
+#define I2S_BIT_SIZE_32 3
+#define I2S_BIT_SIZE_SHIFT 8
+
+#define I2S_I2S_CTRL_BIT_SIZE_MASK      (3 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_16        (I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_20        (I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_24        (I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_32        (I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT)
+
+#define I2S_FIFO_16_LSB 0
+#define I2S_FIFO_20_LSB 1
+#define I2S_FIFO_24_LSB 2
+#define I2S_FIFO_32     3
+#define I2S_FIFO_PACKED 7
+#define I2S_FIFO_SHIFT  4
+
+#define I2S_I2S_CTRL_FIFO_FORMAT_MASK           (7<<4)
+#define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB         \
+                (I2S_FIFO_16_LSB << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB         \
+                (I2S_FIFO_20_LSB << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB         \
+                (I2S_FIFO_24_LSB << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_32             \
+                (I2S_FIFO_32 << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_PACKED         \
+                (I2S_FIFO_PACKED << I2S_FIFO_SHIFT)
+
+#define I2S_I2S_IE_FIFO1_ERR                    (1<<3)
+#define I2S_I2S_IE_FIFO2_ERR                    (1<<2)
+#define I2S_I2S_QE_FIFO1                        (1<<1)
+#define I2S_I2S_QE_FIFO2                        (1<<0)
+
+/*
+ * I2S_I2S_STATUS_0
+ */
+
+#define I2S_I2S_STATUS_FIFO1_RDY                (1<<31)
+#define I2S_I2S_STATUS_FIFO2_RDY                (1<<30)
+#define I2S_I2S_STATUS_FIFO1_BSY                (1<<29)
+#define I2S_I2S_STATUS_FIFO2_BSY                (1<<28)
+#define I2S_I2S_STATUS_FIFO1_ERR                (1<<3)
+#define I2S_I2S_STATUS_FIFO2_ERR                (1<<2)
+#define I2S_I2S_STATUS_QS_FIFO1                 (1<<1)
+#define I2S_I2S_STATUS_QS_FIFO2                 (1<<0)
+
+/*
+ * I2S_I2S_TIMING_0
+ */
+
+#define I2S_I2S_TIMING_NON_SYM_ENABLE           (1<<12)
+#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT_MASK   0x7ff
+#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT        (1<<0)
+
+/*
+ * I2S_I2S_FIFO_SCR_0
+ */
+
+#define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK  0x3f
+#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
+#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
+
+#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_MASK    (0x3f<<24)
+#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_MASK    (0x3f<<16)
+
+#define I2S_I2S_FIFO_SCR_FIFO2_CLR                      (1<<12)
+#define I2S_I2S_FIFO_SCR_FIFO1_CLR                      (1<<8)
+
+#define I2S_FIFO_ATN_LVL_ONE_SLOT       0
+#define I2S_FIFO_ATN_LVL_FOUR_SLOTS     1
+#define I2S_FIFO_ATN_LVL_EIGHT_SLOTS    2
+#define I2S_FIFO_ATN_LVL_TWELVE_SLOTS   3
+#define I2S_FIFO2_ATN_LVL_SHIFT         4
+#define I2S_FIFO1_ATN_LVL_SHIFT         0
+
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK             \
+                (3 << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT         \
+                (I2S_FIFO_ATN_LVL_ONE_SLOT     << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS       \
+                (I2S_FIFO_ATN_LVL_FOUR_SLOTS   << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS      \
+                (I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS     \
+                (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
+
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK             \
+                (3 << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT         \
+                (I2S_FIFO_ATN_LVL_ONE_SLOT     << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS       \
+                (I2S_FIFO_ATN_LVL_FOUR_SLOTS   << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS      \
+                (I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS     \
+                (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
+/*
+ * I2S_I2S_PCM_CTRL_0
+ */
+#define I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ              0
+#define I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ                 1
+#define I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ              2
+#define I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ                 3
+#define I2S_PCM_TRM_EDGE_CTRL_SHIFT                     9
+
+#define I2S_I2S_PCM_TRM_EDGE_CTRL_MASK                  \
+                (3 << I2S_I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ          \
+                (I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ        \
+                << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ             \
+                (I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ     \
+                << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ          \
+                (I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ     \
+                << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ             \
+                (I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ        \
+                << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+
+#define I2S_PCM_TRM_MASK_BITS_ZERO                      0
+#define I2S_PCM_TRM_MASK_BITS_ONE                       1
+#define I2S_PCM_TRM_MASK_BITS_TWO                       2
+#define I2S_PCM_TRM_MASK_BITS_THREE                     3
+#define I2S_PCM_TRM_MASK_BITS_FOUR                      4
+#define I2S_PCM_TRM_MASK_BITS_FIVE                      5
+#define I2S_PCM_TRM_MASK_BITS_SIX                       6
+#define I2S_PCM_TRM_MASK_BITS_SEVEN                     7
+#define I2S_PCM_TRM_MASK_BITS_SHIFT                     6
+
+#define I2S_I2S_PCM_TRM_MASK_BITS_MASK                  \
+                (7 << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_ZERO                  \
+                (I2S_PCM_TRM_MASK_BITS_ZERO             \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_ONE                   \
+                (I2S_PCM_TRM_MASK_BITS_ONE              \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_TWO                   \
+                (I2S_PCM_TRM_MASK_BITS_TWO              \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_THREE                 \
+                (I2S_PCM_TRM_MASK_BITS_THREE            \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_FOUR                  \
+                (I2S_PCM_TRM_MASK_BITS_FOUR             \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_FIVE                  \
+                (I2S_PCM_TRM_MASK_BITS_FIVE             \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_SIX                   \
+                (I2S_PCM_TRM_MASK_BITS_SIX              \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_SEVEN                 \
+                (I2S_PCM_TRM_MASK_BITS_SEVEN            \
+                << I2S_PCM_TRM_MASK_BITS_SHIFT)
+
+#define I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL                 (1<<5)
+#define I2S_I2S_PCM_CTRL_TRM_MODE                       (1<<4)
+
+#define I2S_PCM_RCV_MASK_BITS_ZERO                      0
+#define I2S_PCM_RCV_MASK_BITS_ONE                       1
+#define I2S_PCM_RCV_MASK_BITS_TWO                       2
+#define I2S_PCM_RCV_MASK_BITS_THREE                     3
+#define I2S_PCM_RCV_MASK_BITS_FOUR                      4
+#define I2S_PCM_RCV_MASK_BITS_FIVE                      5
+#define I2S_PCM_RCV_MASK_BITS_SIX                       6
+#define I2S_PCM_RCV_MASK_BITS_SEVEN                     7
+#define I2S_PCM_RCV_MASK_BITS_SHIFT                     1
+
+#define I2S_I2S_PCM_RCV_MASK_BITS_MASK                  \
+                (7 << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_ZERO                  \
+                (I2S_PCM_RCV_MASK_BITS_ZERO             \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_ONE                   \
+                (I2S_PCM_RCV_MASK_BITS_ONE              \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_TWO                   \
+                (I2S_PCM_RCV_MASK_BITS_TWO              \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_THREE                 \
+                (I2S_PCM_RCV_MASK_BITS_THREE            \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_FOUR                  \
+                (I2S_PCM_RCV_MASK_BITS_FOUR             \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_FIVE                  \
+                (I2S_PCM_RCV_MASK_BITS_FIVE             \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_SIX                   \
+                (I2S_PCM_RCV_MASK_BITS_SIX              \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_SEVEN                 \
+                (I2S_PCM_RCV_MASK_BITS_SEVEN            \
+                << I2S_PCM_RCV_MASK_BITS_SHIFT)
+
+#define I2S_I2S_PCM_CTRL_RCV_MODE                       (1<<0)
+
+/*
+ * I2S_I2S_NW_CTRL_0
+ */
+
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT1                    0
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT2                    1
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT3                    2
+#define I2S_TRM_TLPHY_SLOT_SEL_SLOT4                    3
+#define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT             4
+
+#define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_MASK              \
+                (3 << I2S_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT1                \
+                (I2S_TRM_TLPHY_SLOT_SEL_SLOT1           \
+                << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT2                \
+                (I2S_TRM_TLPHY_SLOT_SEL_SLOT2           \
+                << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT3                \
+                (I2S_TRM_TLPHY_SLOT_SEL_SLOT3           \
+                << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT4                \
+                (I2S_TRM_TLPHY_SLOT_SEL_SLOT4           \
+                << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
+
+#define I2S_I2S_NW_CTRL_TRM_TLPHY_MODE                  (1<<3)
+
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT1                    0
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT2                    1
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT3                    2
+#define I2S_RCV_TLPHY_SLOT_SEL_SLOT4                    3
+#define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT             1
+
+#define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_MASK              \
+                (3 << I2S_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT1                \
+                (I2S_RCV_TLPHY_SLOT_SEL_SLOT1           \
+                << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT2                \
+                (I2S_RCV_TLPHY_SLOT_SEL_SLOT2           \
+                << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT3                \
+                (I2S_RCV_TLPHY_SLOT_SEL_SLOT3           \
+                << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+#define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT4                \
+                (I2S_RCV_TLPHY_SLOT_SEL_SLOT4           \
+                << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
+
+#define I2S_I2S_NW_CTRL_RCV_TLPHY_MODE                  (1<<0)
+
+#endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
new file mode 100644
index 00000000000..2b091bf83f3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -0,0 +1,136 @@
+/*
+ * arch/arm/mach-tegra/include/mach/io.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA Corporation.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IO_H
+#define __MACH_TEGRA_IO_H
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define IO_SPACE_LIMIT 0xffff
+#else
+#define IO_SPACE_LIMIT 0xffffffff
+#endif
+
+/* On TEGRA, many peripherals are very closely packed in
+ * two 256MB io windows (that actually only use about 64KB
+ * at the start of each).
+ *
+ * We will just map the first 1MB of each window (to minimize
+ * pt entries needed) and provide a macro to transform physical
+ * io addresses to an appropriate void __iomem *.
+ *
+ */
+
+#define IO_IRAM_PHYS    0x40000000
+#define IO_IRAM_VIRT    0xFE400000
+#define IO_IRAM_SIZE    SZ_256K
+
+#define IO_CPU_PHYS     0x50000000
+#define IO_CPU_VIRT     0xFE000000
+#define IO_CPU_SIZE     SZ_1M
+
+#define IO_PPSB_PHYS    0x60000000
+#define IO_PPSB_VIRT    0xFE200000
+#define IO_PPSB_SIZE    SZ_1M
+
+#define IO_APB_PHYS     0x70000000
+#define IO_APB_VIRT     0xFE300000
+#define IO_APB_SIZE     SZ_1M
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define IO_USB_PHYS     0xC5000000
+#else
+#define IO_USB_PHYS     0x7D000000
+#endif
+#define IO_USB_VIRT     0xFE500000
+#define IO_USB_SIZE     SZ_1M
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define IO_SDMMC_PHYS   0xC8000000
+#else
+#define IO_SDMMC_PHYS   0x78000000
+#endif
+#define IO_SDMMC_VIRT   0xFE600000
+#define IO_SDMMC_SIZE   SZ_1M
+
+#define IO_HOST1X_PHYS  0x54000000
+#define IO_HOST1X_VIRT  0xFE700000
+#define IO_HOST1X_SIZE  SZ_8M
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#define IO_PPCS_PHYS    0xC4000000
+#else
+#define IO_PPCS_PHYS    0x7C000000
+#endif
+#define IO_PPCS_VIRT    0xFE100000
+#define IO_PPCS_SIZE    SZ_1M
+
+#define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
+#define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
+
+#define IO_TO_VIRT(n) ( \
+        IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?           \
+                IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :     \
+        IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?             \
+                IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :       \
+        IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?             \
+                IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :       \
+        IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?           \
+                IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :     \
+        IO_TO_VIRT_BETWEEN((n), IO_HOST1X_PHYS, IO_HOST1X_SIZE) ?       \
+                IO_TO_VIRT_XLATE((n), IO_HOST1X_PHYS, IO_HOST1X_VIRT) : \
+        IO_TO_VIRT_BETWEEN((n), IO_USB_PHYS, IO_USB_SIZE) ?             \
+                IO_TO_VIRT_XLATE((n), IO_USB_PHYS, IO_USB_VIRT) :       \
+        IO_TO_VIRT_BETWEEN((n), IO_SDMMC_PHYS, IO_SDMMC_SIZE) ?         \
+                IO_TO_VIRT_XLATE((n), IO_SDMMC_PHYS, IO_SDMMC_VIRT) :   \
+        IO_TO_VIRT_BETWEEN((n), IO_PPCS_PHYS, IO_PPCS_SIZE) ?           \
+                IO_TO_VIRT_XLATE((n), IO_PPCS_PHYS, IO_PPCS_VIRT) :     \
+        0)
+
+#ifndef __ASSEMBLER__
+
+#define __arch_ioremap          tegra_ioremap
+#define __arch_iounmap          tegra_iounmap
+
+void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
+void tegra_iounmap(volatile void __iomem *addr);
+
+#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
+
+#if defined(CONFIG_TEGRA_PCI)
+extern void __iomem *tegra_pcie_io_base;
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
+}
+#else
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#endif
+
+#define __io(a)         __io(a)
+#define __mem_pci(a)    (a)
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/io_dpd.h b/arch/arm/mach-tegra/include/mach/io_dpd.h
new file mode 100644
index 00000000000..8d153792b79
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io_dpd.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-tegra/include/mach/io_dpd.h
+ *
+ * Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IO_DPD_H
+#define __MACH_TEGRA_IO_DPD_H
+
+/* Tegra io dpd APIs */
+#ifdef CONFIG_PM_SLEEP
+struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev); /* get handle */
+void tegra_io_dpd_enable(struct tegra_io_dpd *hnd); /* enable dpd */
+void tegra_io_dpd_disable(struct tegra_io_dpd *hnd); /* disable dpd */
+#else
+static inline struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev)
+{
+        return NULL;
+}
+static inline void tegra_io_dpd_enable(struct tegra_io_dpd *hnd)
+{
+        /* Do nothing */
+}
+static inline void tegra_io_dpd_disable(struct tegra_io_dpd *hnd)
+{
+        /* Do nothing */
+}
+#endif
+
+#endif /* end __MACH_TEGRA_IO_DPD_H */
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
new file mode 100644
index 00000000000..c491abafb8b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -0,0 +1,523 @@
+/*
+ * arch/arm/mach-tegra/include/mach/iomap.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IOMAP_H
+#define __MACH_TEGRA_IOMAP_H
+
+#include <asm/sizes.h>
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define TEGRA_NOR_FLASH_BASE            0xD0000000
+#define TEGRA_NOR_FLASH_SIZE            SZ_256M
+#else
+#define TEGRA_NOR_FLASH_BASE            0x48000000
+#define TEGRA_NOR_FLASH_SIZE            SZ_128M
+#endif
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define TEGRA_DRAM_BASE                 0x00000000
+#define TEGRA_DRAM_SIZE                 SZ_1G           /* Maximum size */
+#else
+#define TEGRA_DRAM_BASE                 0x80000000
+#define TEGRA_DRAM_SIZE                 (SZ_2G - SZ_1M) /* Maximum size */
+#endif
+
+#define TEGRA_IRAM_BASE                 0x40000000
+#define TEGRA_IRAM_SIZE                 SZ_256K
+
+/* First 1K of IRAM is reserved for cpu reset handler. */
+#define TEGRA_RESET_HANDLER_BASE        TEGRA_IRAM_BASE
+#define TEGRA_RESET_HANDLER_SIZE        SZ_1K
+
+#define TEGRA_HOST1X_BASE               0x50000000
+#define TEGRA_HOST1X_SIZE               0x24000
+
+#define TEGRA_ARM_PERIF_BASE            0x50040000
+#define TEGRA_ARM_PERIF_SIZE            SZ_8K
+
+#define TEGRA_MSELECT_BASE              0x50042000
+#define TEGRA_MSELECT_SIZE              80
+
+#define TEGRA_ARM_PL310_BASE            0x50043000
+#define TEGRA_ARM_PL310_SIZE            SZ_4K
+
+#define TEGRA_ARM_INT_DIST_BASE         0x50041000
+#define TEGRA_ARM_INT_DIST_SIZE         SZ_4K
+
+#define TEGRA_MPE_BASE                  0x54040000
+#define TEGRA_MPE_SIZE                  SZ_256K
+
+#define TEGRA_VI_BASE                   0x54080000
+#define TEGRA_VI_SIZE                   SZ_256K
+
+#define TEGRA_ISP_BASE                  0x54100000
+#define TEGRA_ISP_SIZE                  SZ_256K
+
+#define TEGRA_DISPLAY_BASE              0x54200000
+#define TEGRA_DISPLAY_SIZE              SZ_256K
+
+#define TEGRA_DISPLAY2_BASE             0x54240000
+#define TEGRA_DISPLAY2_SIZE             SZ_256K
+
+#define TEGRA_HDMI_BASE                 0x54280000
+#define TEGRA_HDMI_SIZE                 SZ_256K
+
+#define TEGRA_DSI_BASE                  0x54300000
+#define TEGRA_DSI_SIZE                  SZ_256K
+
+#define TEGRA_DSIB_BASE                 0x54400000
+#define TEGRA_DSIB_SIZE                 SZ_256K
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+
+#define TEGRA_GART_BASE                 0x58000000
+#define TEGRA_GART_SIZE                 SZ_32M
+
+#else
+
+#define TEGRA_SMMU_BASE_TEGRA3_A01      0xe0000000
+#define TEGRA_SMMU_SIZE_TEGRA3_A01      SZ_256M
+#define TEGRA_SMMU_BASE                 0x00001000
+#define TEGRA_SMMU_SIZE                 (SZ_1G - SZ_4K * 2)
+
+#endif
+
+#define TEGRA_RES_SEMA_SIZE             SZ_4K
+#define TEGRA_RES_SEMA_BASE             0x60001000
+
+#define TEGRA_ARB_SEMA_BASE             0x60002000
+#define TEGRA_ARB_SEMA_SIZE             SZ_4K
+
+#define TEGRA_PRIMARY_ICTLR_BASE        0x60004000
+#define TEGRA_PRIMARY_ICTLR_SIZE        64
+
+#define TEGRA_ARBGNT_ICTLR_BASE         0x60004040
+#define TEGRA_ARBGNT_ICTLR_SIZE         192
+
+#define TEGRA_SECONDARY_ICTLR_BASE      0x60004100
+#define TEGRA_SECONDARY_ICTLR_SIZE      64
+
+#define TEGRA_TERTIARY_ICTLR_BASE       0x60004200
+#define TEGRA_TERTIARY_ICTLR_SIZE       64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE     0x60004300
+#define TEGRA_QUATERNARY_ICTLR_SIZE     64
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+
+#define TEGRA_QUINARY_ICTLR_BASE        0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE        SZ_64
+
+#endif
+
+#define TEGRA_TMR1_BASE                 0x60005000
+#define TEGRA_TMR1_SIZE                 SZ_8
+
+#define TEGRA_TMR2_BASE                 0x60005008
+#define TEGRA_TMR2_SIZE                 SZ_8
+
+#define TEGRA_TMRUS_BASE                0x60005010
+#define TEGRA_TMRUS_SIZE                64
+
+#define TEGRA_TMR3_BASE                 0x60005050
+#define TEGRA_TMR3_SIZE                 SZ_8
+
+#define TEGRA_TMR4_BASE                 0x60005058
+#define TEGRA_TMR4_SIZE                 SZ_8
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+
+#define TEGRA_TMR5_BASE                 0x60005060
+#define TEGRA_TMR5_SIZE                 8
+
+#define TEGRA_TMR6_BASE                 0x60005068
+#define TEGRA_TMR6_SIZE                 8
+
+#define TEGRA_TMR7_BASE                 0x60005070
+#define TEGRA_TMR7_SIZE                 8
+
+#define TEGRA_TMR8_BASE                 0x60005078
+#define TEGRA_TMR8_SIZE                 8
+
+#define TEGRA_TMR9_BASE                 0x60005080
+#define TEGRA_TMR9_SIZE                 8
+
+#define TEGRA_TMR10_BASE                0x60005088
+#define TEGRA_TMR10_SIZE                8
+
+#define TEGRA_WDT0_BASE                 0x60005100
+#define TEGRA_WDT0_SIZE                 32
+
+#define TEGRA_WDT1_BASE                 0x60005120
+#define TEGRA_WDT1_SIZE                 32
+
+#define TEGRA_WDT2_BASE                 0x60005140
+#define TEGRA_WDT2_SIZE                 32
+
+#define TEGRA_WDT3_BASE                 0x60005160
+#define TEGRA_WDT3_SIZE                 32
+
+#define TEGRA_WDT4_BASE                 0x60005180
+#define TEGRA_WDT4_SIZE                 32
+
+#endif
+
+#define TEGRA_CLK_RESET_BASE            0x60006000
+#define TEGRA_CLK_RESET_SIZE            SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE            0x60007000
+#define TEGRA_FLOW_CTRL_SIZE            20
+
+#define TEGRA_AHB_DMA_BASE              0x60008000
+#define TEGRA_AHB_DMA_SIZE              SZ_4K
+
+#define TEGRA_AHB_DMA_CH0_BASE          0x60009000
+#define TEGRA_AHB_DMA_CH0_SIZE          32
+
+#define TEGRA_APB_DMA_BASE              0x6000A000
+#define TEGRA_APB_DMA_SIZE              SZ_4K
+
+#define TEGRA_APB_DMA_CH0_BASE          0x6000B000
+#define TEGRA_APB_DMA_CH0_SIZE          32
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+
+#define TEGRA_AHB_ARB_BASE              0x6000C000
+#define TEGRA_AHB_ARB_SIZE              768     /* Overlaps with GISMO */
+
+#endif
+
+#define TEGRA_AHB_GIZMO_BASE            0x6000C004
+#define TEGRA_AHB_GIZMO_SIZE            0x10C
+
+#define TEGRA_SB_BASE                   0x6000C200
+#define TEGRA_SB_SIZE                   256
+
+#define TEGRA_STATMON_BASE              0x6000C400
+#define TEGRA_STATMON_SIZE              SZ_1K
+
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
+
+#define TEGRA_ACTMON_BASE               0x6000C800
+#define TEGRA_ACTMON_SIZE               SZ_1K
+
+#endif
+
+#define TEGRA_GPIO_BASE                 0x6000D000
+#define TEGRA_GPIO_SIZE                 SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
+
+#define TEGRA_BSEA_BASE                 0x60010000
+#define TEGRA_BSEA_SIZE                 SZ_4K
+
+#define TEGRA_VDE_BASE                  0x6001A000
+#define TEGRA_VDE_SIZE                  0x3c00
+
+#define TEGRA_APB_MISC_BASE             0x70000000
+#define TEGRA_APB_MISC_SIZE             SZ_4K
+
+#define TEGRA_APB_MISC_DAS_BASE         0x70000c00
+#define TEGRA_APB_MISC_DAS_SIZE         SZ_128
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+
+#define TEGRA_AC97_BASE                 0x70002000
+#define TEGRA_AC97_SIZE                 SZ_512
+
+#define TEGRA_SPDIF_BASE                0x70002400
+#define TEGRA_SPDIF_SIZE                SZ_512
+
+#define TEGRA_I2S1_BASE                 0x70002800
+#define TEGRA_I2S1_SIZE                 SZ_256
+
+#define TEGRA_I2S2_BASE                 0x70002A00
+#define TEGRA_I2S2_SIZE                 SZ_256
+
+#define TEGRA_PCIE_BASE                 0x80000000
+#define TEGRA_PCIE_SIZE                 SZ_1G
+
+#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
+
+#define TEGRA_TSENSOR_BASE              0x70014000
+#define TEGRA_TSENSOR_SIZE              SZ_4K
+
+#define TEGRA_HDA_BASE                  0x70030000
+#define TEGRA_HDA_SIZE                  SZ_64K
+
+#define TEGRA_AUDIO_CLUSTER_BASE        0x70080000
+#define TEGRA_AUDIO_CLUSTER_SIZE        SZ_4K
+
+#define TEGRA_APBIF0_BASE               TEGRA_AUDIO_CLUSTER_BASE
+#define TEGRA_APBIF0_SIZE               32
+
+#define TEGRA_APBIF1_BASE               0x70080020
+#define TEGRA_APBIF1_SIZE               32
+
+#define TEGRA_APBIF2_BASE               0x70080040
+#define TEGRA_APBIF2_SIZE               32
+
+#define TEGRA_APBIF3_BASE               0x70080060
+#define TEGRA_APBIF3_SIZE               32
+
+#define TEGRA_AHUB_BASE                 0x70080200
+#define TEGRA_AHUB_SIZE                 SZ_256
+
+#define TEGRA_I2S0_BASE                 0x70080300
+#define TEGRA_I2S0_SIZE                 SZ_256
+
+#define TEGRA_I2S1_BASE                 0x70080400
+#define TEGRA_I2S1_SIZE                 SZ_256
+
+#define TEGRA_I2S2_BASE                 0x70080500
+#define TEGRA_I2S2_SIZE                 SZ_256
+
+#define TEGRA_I2S3_BASE                 0x70080600
+#define TEGRA_I2S3_SIZE                 SZ_256
+
+#define TEGRA_I2S4_BASE                 0x70080700
+#define TEGRA_I2S4_SIZE                 SZ_256
+
+#define TEGRA_DAM0_BASE                 0x70080800
+#define TEGRA_DAM0_SIZE                 SZ_256
+
+#define TEGRA_DAM1_BASE                 0x70080900
+#define TEGRA_DAM1_SIZE                 SZ_256
+
+#define TEGRA_DAM2_BASE                 0x70080A00
+#define TEGRA_DAM2_SIZE                 SZ_256
+
+#define TEGRA_SPDIF_BASE                0x70080B00
+#define TEGRA_SPDIF_SIZE                SZ_256
+
+#define TEGRA_PCIE_BASE                 0x00000000
+#define TEGRA_PCIE_SIZE                 SZ_1G
+
+#endif
+
+#define TEGRA_UARTA_BASE                0x70006000
+#define TEGRA_UARTA_SIZE                64
+
+#define TEGRA_UARTB_BASE                0x70006040
+#define TEGRA_UARTB_SIZE                64
+
+#define TEGRA_UARTC_BASE                0x70006200
+#define TEGRA_UARTC_SIZE                SZ_256
+
+#define TEGRA_UARTD_BASE                0x70006300
+#define TEGRA_UARTD_SIZE                SZ_256
+
+#define TEGRA_UARTE_BASE                0x70006400
+#define TEGRA_UARTE_SIZE                SZ_256
+
+#define TEGRA_NAND_BASE                 0x70008000
+#define TEGRA_NAND_SIZE                 SZ_256
+
+#define TEGRA_HSMMC_BASE                0x70008500
+#define TEGRA_HSMMC_SIZE                SZ_256
+
+#define TEGRA_SNOR_BASE                 0x70009000
+#define TEGRA_SNOR_SIZE                 SZ_4K
+
+#define TEGRA_PWFM_BASE                 0x7000A000
+#define TEGRA_PWFM_SIZE                 SZ_256
+
+#define TEGRA_PWFM0_BASE                0x7000A000
+#define TEGRA_PWFM0_SIZE                4
+
+#define TEGRA_PWFM1_BASE                0x7000A010
+#define TEGRA_PWFM1_SIZE                4
+
+#define TEGRA_PWFM2_BASE                0x7000A020
+#define TEGRA_PWFM2_SIZE                4
+
+#define TEGRA_PWFM3_BASE                0x7000A030
+#define TEGRA_PWFM3_SIZE                4
+
+#define TEGRA_MIPI_BASE                 0x7000B000
+#define TEGRA_MIPI_SIZE                 SZ_256
+
+#define TEGRA_I2C_BASE                  0x7000C000
+#define TEGRA_I2C_SIZE                  SZ_256
+
+#define TEGRA_TWC_BASE                  0x7000C100
+#define TEGRA_TWC_SIZE                  SZ_256
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+
+#define TEGRA_SPI_BASE                  0x7000C380
+#define TEGRA_SPI_SIZE                  48
+
+#else
+
+#define TEGRA_DTV_BASE                  0x7000C300
+#define TEGRA_DTV_SIZE                  SZ_256
+
+#endif
+
+#define TEGRA_I2C2_BASE                 0x7000C400
+#define TEGRA_I2C2_SIZE                 SZ_256
+
+#define TEGRA_I2C3_BASE                 0x7000C500
+#define TEGRA_I2C3_SIZE                 SZ_256
+
+#define TEGRA_OWR_BASE                  0x7000C600
+#define TEGRA_OWR_SIZE                  80
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+
+#define TEGRA_DVC_BASE                  0x7000D000
+#define TEGRA_DVC_SIZE                  SZ_512
+
+#else
+
+#define TEGRA_I2C4_BASE                 0x7000C700
+#define TEGRA_I2C4_SIZE                 SZ_512
+
+#define TEGRA_I2C5_BASE                 0x7000D000
+#define TEGRA_I2C5_SIZE                 SZ_512
+
+#endif
+
+#define TEGRA_SPI1_BASE                 0x7000D400
+#define TEGRA_SPI1_SIZE                 SZ_512
+
+#define TEGRA_SPI2_BASE                 0x7000D600
+#define TEGRA_SPI2_SIZE                 SZ_512
+
+#define TEGRA_SPI3_BASE                 0x7000D800
+#define TEGRA_SPI3_SIZE                 SZ_512
+
+#define TEGRA_SPI4_BASE                 0x7000DA00
+#define TEGRA_SPI4_SIZE                 SZ_512
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+
+#define TEGRA_SPI5_BASE                 0x7000DC00
+#define TEGRA_SPI5_SIZE                 SZ_512
+
+#define TEGRA_SPI6_BASE                 0x7000DE00
+#define TEGRA_SPI6_SIZE                 SZ_512
+
+#endif
+
+#define TEGRA_RTC_BASE                  0x7000E000
+#define TEGRA_RTC_SIZE                  SZ_256
+
+#define TEGRA_KBC_BASE                  0x7000E200
+#define TEGRA_KBC_SIZE                  SZ_256
+
+#define TEGRA_PMC_BASE                  0x7000E400
+#define TEGRA_PMC_SIZE                  SZ_256
+
+#define TEGRA_MC_BASE                   0x7000F000
+#define TEGRA_MC_SIZE                   SZ_1K
+
+#define TEGRA_EMC_BASE                  0x7000F400
+#define TEGRA_EMC_SIZE                  SZ_1K
+
+#define TEGRA_FUSE_BASE                 0x7000F800
+#define TEGRA_FUSE_SIZE                 SZ_1K
+
+#define TEGRA_KFUSE_BASE                0x7000FC00
+#define TEGRA_KFUSE_SIZE                SZ_1K
+
+#define TEGRA_CSITE_BASE                0x70040000
+#define TEGRA_CSITE_SIZE                SZ_256K
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+
+#define TEGRA_USB_BASE                  0xC5000000
+#define TEGRA_USB_SIZE                  SZ_16K
+
+#define TEGRA_USB2_BASE                 0xC5004000
+#define TEGRA_USB2_SIZE                 SZ_16K
+
+#define TEGRA_USB3_BASE                 0xC5008000
+#define TEGRA_USB3_SIZE                 SZ_16K
+
+#define TEGRA_SDMMC1_BASE               0xC8000000
+#define TEGRA_SDMMC1_SIZE               SZ_512
+
+#define TEGRA_SDMMC2_BASE               0xC8000200
+#define TEGRA_SDMMC2_SIZE               SZ_512
+
+#define TEGRA_SDMMC3_BASE               0xC8000400
+#define TEGRA_SDMMC3_SIZE               SZ_512
+
+#define TEGRA_SDMMC4_BASE               0xC8000600
+#define TEGRA_SDMMC4_SIZE               SZ_512
+
+#else
+
+#define TEGRA_SATA_BASE                 0x70020000
+#define TEGRA_SATA_SIZE                 SZ_64K
+
+#define TEGRA_SATA_CONFIG_BASE          0x70021000
+#define TEGRA_SATA_CONFIG_SIZE          SZ_4K
+
+#define TEGRA_SATA_BAR5_BASE            0x70027000
+#define TEGRA_SATA_BAR5_SIZE            SZ_8K
+
+#define TEGRA_SDMMC1_BASE               0x78000000
+#define TEGRA_SDMMC1_SIZE               SZ_512
+
+#define TEGRA_SDMMC2_BASE               0x78000200
+#define TEGRA_SDMMC2_SIZE               SZ_512
+
+#define TEGRA_SDMMC3_BASE               0x78000400
+#define TEGRA_SDMMC3_SIZE               SZ_512
+
+#define TEGRA_SDMMC4_BASE               0x78000600
+#define TEGRA_SDMMC4_SIZE               SZ_512
+
+#define TEGRA_USB_BASE                  0x7D000000
+#define TEGRA_USB_SIZE                  SZ_16K
+
+#define TEGRA_USB2_BASE                 0x7D004000
+#define TEGRA_USB2_SIZE                 SZ_16K
+
+#define TEGRA_USB3_BASE                 0x7D008000
+#define TEGRA_USB3_SIZE                 SZ_16K
+
+#define TEGRA_SE_BASE                   0x70012000
+#define TEGRA_SE_SIZE                   SZ_8K
+
+#endif
+
+#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
+# define TEGRA_DEBUG_UART_BASE 0
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/iovmm.h b/arch/arm/mach-tegra/include/mach/iovmm.h
new file mode 100644
index 00000000000..fd83a326e12
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iovmm.h
@@ -0,0 +1,323 @@
+/*
+ * arch/arm/mach-tegra/include/mach/iovmm.h
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed i the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/rbtree.h>
+#include <linux/rwsem.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#ifndef _MACH_TEGRA_IOVMM_H_
+#define _MACH_TEGRA_IOVMM_H_
+
+typedef u32 tegra_iovmm_addr_t;
+
+struct tegra_iovmm_device_ops;
+
+/*
+ * each I/O virtual memory manager unit should register a device with
+ * the iovmm system
+ */
+struct tegra_iovmm_device {
+        struct tegra_iovmm_device_ops   *ops;
+        const char                      *name;
+        struct list_head                list;
+        int                             pgsize_bits;
+};
+
+/*
+ * tegra_iovmm_domain serves a purpose analagous to mm_struct as defined in
+ * <linux/mm_types.h> - it defines a virtual address space within which
+ * tegra_iovmm_areas can be created.
+ */
+struct tegra_iovmm_domain {
+        atomic_t                clients;
+        atomic_t                locks;
+        spinlock_t              block_lock;  /* RB-tree for iovmm_area blocks */
+        unsigned long           flags;
+        wait_queue_head_t       delay_lock;  /* when lock_client fails */
+        struct rw_semaphore     map_lock;
+        struct rb_root          all_blocks;  /* ordered by address */
+        struct rb_root          free_blocks; /* ordered by size */
+        struct tegra_iovmm_device *dev;
+};
+
+/*
+ * tegra_iovmm_client is analagous to an individual task in the task group
+ * which owns an mm_struct.
+ */
+
+struct iovmm_share_group;
+
+struct tegra_iovmm_client {
+        const char                      *name;
+        unsigned long                   flags;
+        struct iovmm_share_group        *group;
+        struct tegra_iovmm_domain       *domain;
+        struct miscdevice               *misc_dev;
+        struct list_head                list;
+};
+
+/*
+ * tegra_iovmm_area serves a purpose analagous to vm_area_struct as defined
+ * in <linux/mm_types.h> - it defines a virtual memory area which can be
+ * mapped to physical memory by a client-provided mapping function. */
+
+struct tegra_iovmm_area {
+        struct tegra_iovmm_domain       *domain;
+        tegra_iovmm_addr_t              iovm_start;
+        size_t                          iovm_length;
+        pgprot_t                        pgprot;
+        struct tegra_iovmm_area_ops     *ops;
+};
+
+struct tegra_iovmm_device_ops {
+        /* maps a VMA using the page residency functions provided by the VMA */
+        int (*map)(struct tegra_iovmm_domain *domain,
+                struct tegra_iovmm_area *io_vma);
+        /* marks all PTEs in a VMA as invalid; decommits the virtual addres
+         * space (potentially freeing PDEs when decommit is true.) */
+        void (*unmap)(struct tegra_iovmm_domain *domain,
+                struct tegra_iovmm_area *io_vma, bool decommit);
+        void (*map_pfn)(struct tegra_iovmm_domain *domain,
+                struct tegra_iovmm_area *io_vma,
+                unsigned long offs, unsigned long pfn);
+        /*
+         * ensures that a domain is resident in the hardware's mapping region
+         * so that it may be used by a client
+         */
+        int (*lock_domain)(struct tegra_iovmm_domain *domain,
+                struct tegra_iovmm_client *client);
+        void (*unlock_domain)(struct tegra_iovmm_domain *domain,
+                struct tegra_iovmm_client *client);
+        /*
+         * allocates a vmm_domain for the specified client; may return the same
+         * domain for multiple clients
+         */
+        struct tegra_iovmm_domain* (*alloc_domain)(
+                struct tegra_iovmm_device *dev,
+                struct tegra_iovmm_client *client);
+        void (*free_domain)(struct tegra_iovmm_domain *domain,
+                struct tegra_iovmm_client *client);
+        int (*suspend)(struct tegra_iovmm_device *dev);
+        void (*resume)(struct tegra_iovmm_device *dev);
+};
+
+struct tegra_iovmm_area_ops {
+        /*
+         * ensures that the page of data starting at the specified offset
+         * from the start of the iovma is resident and pinned for use by
+         * DMA, returns the system pfn, or an invalid pfn if the
+         * operation fails.
+         */
+        unsigned long (*lock_makeresident)(struct tegra_iovmm_area *area,
+                tegra_iovmm_addr_t offs);
+        /* called when the page is unmapped from the I/O VMA */
+        void (*release)(struct tegra_iovmm_area *area, tegra_iovmm_addr_t offs);
+};
+
+#ifdef CONFIG_TEGRA_IOVMM
+/*
+ * called by clients to allocate an I/O VMM client mapping context which
+ * will be shared by all clients in the same share_group
+ */
+struct tegra_iovmm_client *tegra_iovmm_alloc_client(const char *name,
+        const char *share_group, struct miscdevice *misc_dev);
+
+size_t tegra_iovmm_get_vm_size(struct tegra_iovmm_client *client);
+
+void tegra_iovmm_free_client(struct tegra_iovmm_client *client);
+
+/*
+ * called by clients to ensure that their mapping context is resident
+ * before performing any DMA operations addressing I/O VMM regions.
+ * client_lock may return -EINTR.
+ */
+int tegra_iovmm_client_lock(struct tegra_iovmm_client *client);
+int tegra_iovmm_client_trylock(struct tegra_iovmm_client *client);
+
+/* called by clients after DMA operations are complete */
+void tegra_iovmm_client_unlock(struct tegra_iovmm_client *client);
+
+/*
+ * called by clients to allocate a new iovmm_area and reserve I/O virtual
+ * address space for it. if ops is NULL, clients should subsequently call
+ * tegra_iovmm_vm_map_pages and/or tegra_iovmm_vm_insert_pfn to explicitly
+ * map the I/O virtual address to an OS-allocated page or physical address,
+ * respectively. VM operations may be called before this call returns
+ */
+struct tegra_iovmm_area *tegra_iovmm_create_vm(
+        struct tegra_iovmm_client *client, struct tegra_iovmm_area_ops *ops,
+        size_t size, size_t align, pgprot_t pgprot, unsigned long iovm_start);
+
+/*
+ * called by clients to "zap" an iovmm_area, and replace all mappings
+ * in it with invalid ones, without freeing the virtual address range
+ */
+void tegra_iovmm_zap_vm(struct tegra_iovmm_area *vm);
+
+/*
+ * after zapping a demand-loaded iovmm_area, the client should unzap it
+ * to allow the VMM device to remap the page range.
+ */
+void tegra_iovmm_unzap_vm(struct tegra_iovmm_area *vm);
+
+/* called by clients to return an iovmm_area to the free pool for the domain */
+void tegra_iovmm_free_vm(struct tegra_iovmm_area *vm);
+
+/* returns size of largest free iovm block */
+size_t tegra_iovmm_get_max_free(struct tegra_iovmm_client *client);
+
+/*
+ * called by client software to map the page-aligned I/O address vaddr to
+ * a specific physical address pfn. I/O VMA should have been created with
+ * a NULL tegra_iovmm_area_ops structure.
+ */
+void tegra_iovmm_vm_insert_pfn(struct tegra_iovmm_area *area,
+        tegra_iovmm_addr_t vaddr, unsigned long pfn);
+
+/*
+ * called by clients to return the iovmm_area containing addr, or NULL if
+ * addr has not been allocated. caller should call tegra_iovmm_area_put when
+ * finished using the returned pointer
+ */
+struct tegra_iovmm_area *tegra_iovmm_find_area_get(
+        struct tegra_iovmm_client *client, tegra_iovmm_addr_t addr);
+
+struct tegra_iovmm_area *tegra_iovmm_area_get(struct tegra_iovmm_area *vm);
+void tegra_iovmm_area_put(struct tegra_iovmm_area *vm);
+
+/* called by drivers to initialize a tegra_iovmm_domain structure */
+int tegra_iovmm_domain_init(struct tegra_iovmm_domain *domain,
+        struct tegra_iovmm_device *dev, tegra_iovmm_addr_t start,
+        tegra_iovmm_addr_t end);
+
+/* called by drivers to register an I/O VMM device with the system */
+int tegra_iovmm_register(struct tegra_iovmm_device *dev);
+
+/* called by drivers to remove an I/O VMM device from the system */
+int tegra_iovmm_unregister(struct tegra_iovmm_device *dev);
+
+#else /* CONFIG_TEGRA_IOVMM */
+
+static inline struct tegra_iovmm_client *tegra_iovmm_alloc_client(
+        const char *name, const char *share_group, struct miscdevice *misc_dev)
+{
+        return NULL;
+}
+
+static inline size_t tegra_iovmm_get_vm_size(struct tegra_iovmm_client *client)
+{
+        return 0;
+}
+
+static inline void tegra_iovmm_free_client(struct tegra_iovmm_client *client)
+{
+}
+
+static inline int tegra_iovmm_client_lock(struct tegra_iovmm_client *client)
+{
+        return 0;
+}
+
+static inline int tegra_iovmm_client_trylock(struct tegra_iovmm_client *client)
+{
+        return 0;
+}
+
+static inline void tegra_iovmm_client_unlock(struct tegra_iovmm_client *client)
+{
+}
+
+static inline struct tegra_iovmm_area *tegra_iovmm_create_vm(
+        struct tegra_iovmm_client *client, struct tegra_iovmm_area_ops *ops,
+        size_t size, size_t align, pgprot_t pgprot, unsigned long iovm_start)
+{
+        return NULL;
+}
+
+static inline void tegra_iovmm_zap_vm(struct tegra_iovmm_area *vm)
+{
+}
+
+static inline void tegra_iovmm_unzap_vm(struct tegra_iovmm_area *vm)
+{
+}
+
+static inline void tegra_iovmm_free_vm(struct tegra_iovmm_area *vm)
+{
+}
+
+static inline size_t tegra_iovmm_get_max_free(struct tegra_iovmm_client *client)
+{
+        return 0;
+}
+
+static inline void tegra_iovmm_vm_insert_pfn(struct tegra_iovmm_area *area,
+        tegra_iovmm_addr_t vaddr, unsigned long pfn)
+{
+}
+
+static inline struct tegra_iovmm_area *tegra_iovmm_find_area_get(
+        struct tegra_iovmm_client *client, tegra_iovmm_addr_t addr)
+{
+        return NULL;
+}
+
+static inline struct tegra_iovmm_area *tegra_iovmm_area_get(
+        struct tegra_iovmm_area *vm)
+{
+        return NULL;
+}
+
+static inline void tegra_iovmm_area_put(struct tegra_iovmm_area *vm)
+{
+}
+
+static inline int tegra_iovmm_domain_init(struct tegra_iovmm_domain *domain,
+        struct tegra_iovmm_device *dev, tegra_iovmm_addr_t start,
+        tegra_iovmm_addr_t end)
+{
+        return 0;
+}
+
+static inline int tegra_iovmm_register(struct tegra_iovmm_device *dev)
+{
+        return 0;
+}
+
+static inline int tegra_iovmm_unregister(struct tegra_iovmm_device *dev)
+{
+        return 0;
+}
+
+static inline int tegra_iovmm_suspend(void)
+{
+        return 0;
+}
+
+static inline void tegra_iovmm_resume(void)
+{
+}
+
+#endif /* CONFIG_TEGRA_IOVMM */
+#endif /* _MACH_TEGRA_IOVMM_H_*/
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
new file mode 100644
index 00000000000..bf1b12559be
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -0,0 +1,391 @@
+/*
+ * arch/arm/mach-tegra/include/mach/irqs.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IRQS_H
+#define __MACH_TEGRA_IRQS_H
+
+#define INT_GIC_BASE                    0
+
+#define IRQ_LOCALTIMER                  29
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+/* Primary Interrupt Controller */
+#define INT_PRI_BASE                    (INT_GIC_BASE + 32)
+#define INT_TMR1                        (INT_PRI_BASE + 0)
+#define INT_TMR2                        (INT_PRI_BASE + 1)
+#define INT_RTC                         (INT_PRI_BASE + 2)
+#define INT_I2S2                        (INT_PRI_BASE + 3)
+#define INT_SHR_SEM_INBOX_IBF           (INT_PRI_BASE + 4)
+#define INT_SHR_SEM_INBOX_IBE           (INT_PRI_BASE + 5)
+#define INT_SHR_SEM_OUTBOX_IBF          (INT_PRI_BASE + 6)
+#define INT_SHR_SEM_OUTBOX_IBE          (INT_PRI_BASE + 7)
+#define INT_VDE_UCQ_ERROR               (INT_PRI_BASE + 8)
+#define INT_VDE_SYNC_TOKEN              (INT_PRI_BASE + 9)
+#define INT_VDE_BSE_V                   (INT_PRI_BASE + 10)
+#define INT_VDE_BSE_A                   (INT_PRI_BASE + 11)
+#define INT_VDE_SXE                     (INT_PRI_BASE + 12)
+#define INT_I2S1                        (INT_PRI_BASE + 13)
+#define INT_SDMMC1                      (INT_PRI_BASE + 14)
+#define INT_SDMMC2                      (INT_PRI_BASE + 15)
+#define INT_XIO                         (INT_PRI_BASE + 16)
+#define INT_VDE                         (INT_PRI_BASE + 17)
+#define INT_AVP_UCQ                     (INT_PRI_BASE + 18)
+#define INT_SDMMC3                      (INT_PRI_BASE + 19)
+#define INT_USB                         (INT_PRI_BASE + 20)
+#define INT_USB2                        (INT_PRI_BASE + 21)
+#define INT_PRI_RES_22                  (INT_PRI_BASE + 22)
+#define INT_EIDE                        (INT_PRI_BASE + 23)
+#define INT_NANDFLASH                   (INT_PRI_BASE + 24)
+#define INT_VCP                         (INT_PRI_BASE + 25)
+#define INT_APB_DMA                     (INT_PRI_BASE + 26)
+#define INT_AHB_DMA                     (INT_PRI_BASE + 27)
+#define INT_GNT_0                       (INT_PRI_BASE + 28)
+#define INT_GNT_1                       (INT_PRI_BASE + 29)
+#define INT_OWR                         (INT_PRI_BASE + 30)
+#define INT_SDMMC4                      (INT_PRI_BASE + 31)
+
+/* Secondary Interrupt Controller */
+#define INT_SEC_BASE                    (INT_PRI_BASE + 32)
+#define INT_GPIO1                       (INT_SEC_BASE + 0)
+#define INT_GPIO2                       (INT_SEC_BASE + 1)
+#define INT_GPIO3                       (INT_SEC_BASE + 2)
+#define INT_GPIO4                       (INT_SEC_BASE + 3)
+#define INT_UARTA                       (INT_SEC_BASE + 4)
+#define INT_UARTB                       (INT_SEC_BASE + 5)
+#define INT_I2C                         (INT_SEC_BASE + 6)
+#define INT_SPI                         (INT_SEC_BASE + 7)
+#define INT_TWC                         (INT_SEC_BASE + 8)
+#define INT_TMR3                        (INT_SEC_BASE + 9)
+#define INT_TMR4                        (INT_SEC_BASE + 10)
+#define INT_FLOW_RSM0                   (INT_SEC_BASE + 11)
+#define INT_FLOW_RSM1                   (INT_SEC_BASE + 12)
+#define INT_SPDIF                       (INT_SEC_BASE + 13)
+#define INT_UARTC                       (INT_SEC_BASE + 14)
+#define INT_MIPI                        (INT_SEC_BASE + 15)
+#define INT_EVENTA                      (INT_SEC_BASE + 16)
+#define INT_EVENTB                      (INT_SEC_BASE + 17)
+#define INT_EVENTC                      (INT_SEC_BASE + 18)
+#define INT_EVENTD                      (INT_SEC_BASE + 19)
+#define INT_VFIR                        (INT_SEC_BASE + 20)
+#define INT_DVC                         (INT_SEC_BASE + 21)
+#define INT_SYS_STATS_MON               (INT_SEC_BASE + 22)
+#define INT_GPIO5                       (INT_SEC_BASE + 23)
+#define INT_CPU0_PMU_INTR               (INT_SEC_BASE + 24)
+#define INT_CPU1_PMU_INTR               (INT_SEC_BASE + 25)
+#define INT_SEC_RES_26                  (INT_SEC_BASE + 26)
+#define INT_SPI_1                       (INT_SEC_BASE + 27)
+#define INT_APB_DMA_COP                 (INT_SEC_BASE + 28)
+#define INT_AHB_DMA_COP                 (INT_SEC_BASE + 29)
+#define INT_DMA_TX                      (INT_SEC_BASE + 30)
+#define INT_DMA_RX                      (INT_SEC_BASE + 31)
+
+/* Tertiary Interrupt Controller */
+#define INT_TRI_BASE                    (INT_SEC_BASE + 32)
+#define INT_HOST1X_COP_SYNCPT           (INT_TRI_BASE + 0)
+#define INT_HOST1X_MPCORE_SYNCPT        (INT_TRI_BASE + 1)
+#define INT_HOST1X_COP_GENERAL          (INT_TRI_BASE + 2)
+#define INT_HOST1X_MPCORE_GENERAL       (INT_TRI_BASE + 3)
+#define INT_MPE_GENERAL                 (INT_TRI_BASE + 4)
+#define INT_VI_GENERAL                  (INT_TRI_BASE + 5)
+#define INT_EPP_GENERAL                 (INT_TRI_BASE + 6)
+#define INT_ISP_GENERAL                 (INT_TRI_BASE + 7)
+#define INT_2D_GENERAL                  (INT_TRI_BASE + 8)
+#define INT_DISPLAY_GENERAL             (INT_TRI_BASE + 9)
+#define INT_DISPLAY_B_GENERAL           (INT_TRI_BASE + 10)
+#define INT_HDMI                        (INT_TRI_BASE + 11)
+#define INT_TVO_GENERAL                 (INT_TRI_BASE + 12)
+#define INT_MC_GENERAL                  (INT_TRI_BASE + 13)
+#define INT_EMC_GENERAL                 (INT_TRI_BASE + 14)
+#define INT_TRI_RES_15                  (INT_TRI_BASE + 15)
+#define INT_TRI_RES_16                  (INT_TRI_BASE + 16)
+#define INT_AC97                        (INT_TRI_BASE + 17)
+#define INT_SPI_2                       (INT_TRI_BASE + 18)
+#define INT_SPI_3                       (INT_TRI_BASE + 19)
+#define INT_I2C2                        (INT_TRI_BASE + 20)
+#define INT_KBC                         (INT_TRI_BASE + 21)
+#define INT_EXTERNAL_PMU                (INT_TRI_BASE + 22)
+#define INT_GPIO6                       (INT_TRI_BASE + 23)
+#define INT_TVDAC                       (INT_TRI_BASE + 24)
+#define INT_GPIO7                       (INT_TRI_BASE + 25)
+#define INT_UARTD                       (INT_TRI_BASE + 26)
+#define INT_UARTE                       (INT_TRI_BASE + 27)
+#define INT_I2C3                        (INT_TRI_BASE + 28)
+#define INT_SPI_4                       (INT_TRI_BASE + 29)
+#define INT_TRI_RES_30                  (INT_TRI_BASE + 30)
+#define INT_SW_RESERVED                 (INT_TRI_BASE + 31)
+
+/* Quaternary Interrupt Controller */
+#define INT_QUAD_BASE                   (INT_TRI_BASE + 32)
+#define INT_SNOR                        (INT_QUAD_BASE + 0)
+#define INT_USB3                        (INT_QUAD_BASE + 1)
+#define INT_PCIE_INTR                   (INT_QUAD_BASE + 2)
+#define INT_PCIE_MSI                    (INT_QUAD_BASE + 3)
+#define INT_QUAD_RES_4                  (INT_QUAD_BASE + 4)
+#define INT_QUAD_RES_5                  (INT_QUAD_BASE + 5)
+#define INT_QUAD_RES_6                  (INT_QUAD_BASE + 6)
+#define INT_QUAD_RES_7                  (INT_QUAD_BASE + 7)
+#define INT_APB_DMA_CH0                 (INT_QUAD_BASE + 8)
+#define INT_APB_DMA_CH1                 (INT_QUAD_BASE + 9)
+#define INT_APB_DMA_CH2                 (INT_QUAD_BASE + 10)
+#define INT_APB_DMA_CH3                 (INT_QUAD_BASE + 11)
+#define INT_APB_DMA_CH4                 (INT_QUAD_BASE + 12)
+#define INT_APB_DMA_CH5                 (INT_QUAD_BASE + 13)
+#define INT_APB_DMA_CH6                 (INT_QUAD_BASE + 14)
+#define INT_APB_DMA_CH7                 (INT_QUAD_BASE + 15)
+#define INT_APB_DMA_CH8                 (INT_QUAD_BASE + 16)
+#define INT_APB_DMA_CH9                 (INT_QUAD_BASE + 17)
+#define INT_APB_DMA_CH10                (INT_QUAD_BASE + 18)
+#define INT_APB_DMA_CH11                (INT_QUAD_BASE + 19)
+#define INT_APB_DMA_CH12                (INT_QUAD_BASE + 20)
+#define INT_APB_DMA_CH13                (INT_QUAD_BASE + 21)
+#define INT_APB_DMA_CH14                (INT_QUAD_BASE + 22)
+#define INT_APB_DMA_CH15                (INT_QUAD_BASE + 23)
+#define INT_QUAD_RES_24                 (INT_QUAD_BASE + 24)
+#define INT_QUAD_RES_25                 (INT_QUAD_BASE + 25)
+#define INT_QUAD_RES_26                 (INT_QUAD_BASE + 26)
+#define INT_QUAD_RES_27                 (INT_QUAD_BASE + 27)
+#define INT_QUAD_RES_28                 (INT_QUAD_BASE + 28)
+#define INT_QUAD_RES_29                 (INT_QUAD_BASE + 29)
+#define INT_QUAD_RES_30                 (INT_QUAD_BASE + 30)
+#define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
+
+#define INT_GIC_NR                      (INT_QUAD_BASE + 32)
+
+#define INT_MAIN_NR                     (INT_GIC_NR - INT_PRI_BASE)
+
+#define INT_SYNCPT_THRESH_BASE          (INT_QUAD_BASE + 32)
+#define INT_SYNCPT_THRESH_NR            32
+
+#define INT_GPIO_BASE                   (INT_SYNCPT_THRESH_BASE + \
+                                         INT_SYNCPT_THRESH_NR)
+#define INT_GPIO_NR                     (28 * 8)
+
+#define INT_PCI_MSI_BASE                (INT_GPIO_BASE + \
+                                         INT_GPIO_NR)
+#define INT_PCI_MSI_NR                  (0)
+
+#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
+
+/* Primary Interrupt Controller */
+#define INT_PRI_BASE                    (INT_GIC_BASE + 32)
+#define INT_TMR1                        (INT_PRI_BASE + 0)
+#define INT_TMR2                        (INT_PRI_BASE + 1)
+#define INT_RTC                         (INT_PRI_BASE + 2)
+#define INT_CEC                         (INT_PRI_BASE + 3)
+#define INT_SHR_SEM_INBOX_IBF           (INT_PRI_BASE + 4)
+#define INT_SHR_SEM_INBOX_IBE           (INT_PRI_BASE + 5)
+#define INT_SHR_SEM_OUTBOX_IBF          (INT_PRI_BASE + 6)
+#define INT_SHR_SEM_OUTBOX_IBE          (INT_PRI_BASE + 7)
+#define INT_VDE_UCQ_ERROR               (INT_PRI_BASE + 8)
+#define INT_VDE_SYNC_TOKEN              (INT_PRI_BASE + 9)
+#define INT_VDE_BSE_V                   (INT_PRI_BASE + 10)
+#define INT_VDE_BSE_A                   (INT_PRI_BASE + 11)
+#define INT_VDE_SXE                     (INT_PRI_BASE + 12)
+#define INT_SATA_RX_STAT                (INT_PRI_BASE + 13)
+#define INT_SDMMC1                      (INT_PRI_BASE + 14)
+#define INT_SDMMC2                      (INT_PRI_BASE + 15)
+#define INT_XIO                         (INT_PRI_BASE + 16)
+#define INT_VDE                         (INT_PRI_BASE + 17)
+#define INT_AVP_UCQ                     (INT_PRI_BASE + 18)
+#define INT_SDMMC3                      (INT_PRI_BASE + 19)
+#define INT_USB                         (INT_PRI_BASE + 20)
+#define INT_USB2                        (INT_PRI_BASE + 21)
+#define INT_HSMMC                       (INT_PRI_BASE + 22)
+#define INT_SATA_CTL                    (INT_PRI_BASE + 23)
+#define INT_NANDFLASH                   (INT_PRI_BASE + 24)
+#define INT_VCP                         (INT_PRI_BASE + 25)
+#define INT_APB_DMA                     (INT_PRI_BASE + 26)
+#define INT_AHB_DMA                     (INT_PRI_BASE + 27)
+#define INT_GNT_0                       (INT_PRI_BASE + 28)
+#define INT_GNT_1                       (INT_PRI_BASE + 29)
+#define INT_OWR                         (INT_PRI_BASE + 30)
+#define INT_SDMMC4                      (INT_PRI_BASE + 31)
+
+/* Secondary Interrupt Controller */
+#define INT_SEC_BASE                    (INT_PRI_BASE + 32)
+#define INT_GPIO1                       (INT_SEC_BASE + 0)
+#define INT_GPIO2                       (INT_SEC_BASE + 1)
+#define INT_GPIO3                       (INT_SEC_BASE + 2)
+#define INT_GPIO4                       (INT_SEC_BASE + 3)
+#define INT_UARTA                       (INT_SEC_BASE + 4)
+#define INT_UARTB                       (INT_SEC_BASE + 5)
+#define INT_I2C                         (INT_SEC_BASE + 6)
+#define INT_SPI                         (INT_SEC_BASE + 7)
+#define INT_DTV                         INT_SPI
+#define INT_TWC                         (INT_SEC_BASE + 8)
+#define INT_TMR3                        (INT_SEC_BASE + 9)
+#define INT_TMR4                        (INT_SEC_BASE + 10)
+#define INT_FLOW_RSM0                   (INT_SEC_BASE + 11)
+#define INT_FLOW_RSM1                   (INT_SEC_BASE + 12)
+#define INT_ACTMON                      (INT_SEC_BASE + 13)
+#define INT_UARTC                       (INT_SEC_BASE + 14)
+#define INT_MIPI                        (INT_SEC_BASE + 15)
+#define INT_EVENTA                      (INT_SEC_BASE + 16)
+#define INT_EVENTB                      (INT_SEC_BASE + 17)
+#define INT_EVENTC                      (INT_SEC_BASE + 18)
+#define INT_EVENTD                      (INT_SEC_BASE + 19)
+#define INT_VFIR                        (INT_SEC_BASE + 20)
+#define INT_I2C5                        (INT_SEC_BASE + 21)
+#define INT_SYS_STATS_MON               (INT_SEC_BASE + 22)
+#define INT_GPIO5                       (INT_SEC_BASE + 23)
+#define INT_SPEEDO_PMON_0               (INT_SEC_BASE + 24)
+#define INT_SPEEDO_PMON_1               (INT_SEC_BASE + 25)
+#define INT_SE                          (INT_SEC_BASE + 26)
+#define INT_SPI_1                       (INT_SEC_BASE + 27)
+#define INT_APB_DMA_COP                 (INT_SEC_BASE + 28)
+#define INT_AHB_DMA_COP                 (INT_SEC_BASE + 29)
+#define INT_DMA_TX                      (INT_SEC_BASE + 30)
+#define INT_DMA_RX                      (INT_SEC_BASE + 31)
+
+/* Tertiary Interrupt Controller */
+#define INT_TRI_BASE                    (INT_SEC_BASE + 32)
+#define INT_HOST1X_COP_SYNCPT           (INT_TRI_BASE + 0)
+#define INT_HOST1X_MPCORE_SYNCPT        (INT_TRI_BASE + 1)
+#define INT_HOST1X_COP_GENERAL          (INT_TRI_BASE + 2)
+#define INT_HOST1X_MPCORE_GENERAL       (INT_TRI_BASE + 3)
+#define INT_MPE_GENERAL                 (INT_TRI_BASE + 4)
+#define INT_VI_GENERAL                  (INT_TRI_BASE + 5)
+#define INT_EPP_GENERAL                 (INT_TRI_BASE + 6)
+#define INT_ISP_GENERAL                 (INT_TRI_BASE + 7)
+#define INT_2D_GENERAL                  (INT_TRI_BASE + 8)
+#define INT_DISPLAY_GENERAL             (INT_TRI_BASE + 9)
+#define INT_DISPLAY_B_GENERAL           (INT_TRI_BASE + 10)
+#define INT_HDMI                        (INT_TRI_BASE + 11)
+#define INT_TVO_GENERAL                 (INT_TRI_BASE + 12)
+#define INT_MC_GENERAL                  (INT_TRI_BASE + 13)
+#define INT_EMC_GENERAL                 (INT_TRI_BASE + 14)
+#define INT_SPI_6                       (INT_SEC_BASE + 15)
+#define INT_NOR_FLASH                   (INT_TRI_BASE + 16)
+#define INT_HDA                         (INT_TRI_BASE + 17)
+#define INT_SPI_2                       (INT_TRI_BASE + 18)
+#define INT_SPI_3                       (INT_TRI_BASE + 19)
+#define INT_I2C2                        (INT_TRI_BASE + 20)
+#define INT_KBC                         (INT_TRI_BASE + 21)
+#define INT_EXTERNAL_PMU                (INT_TRI_BASE + 22)
+#define INT_GPIO6                       (INT_TRI_BASE + 23)
+#define INT_TVDAC                       (INT_TRI_BASE + 24)
+#define INT_GPIO7                       (INT_TRI_BASE + 25)
+#define INT_UARTD                       (INT_TRI_BASE + 26)
+#define INT_UARTE                       (INT_TRI_BASE + 27)
+#define INT_I2C3                        (INT_TRI_BASE + 28)
+#define INT_SPI_4                       (INT_TRI_BASE + 29)
+#define INT_SPI_5                       (INT_TRI_BASE + 30)
+#define INT_SW_RESERVED                 (INT_TRI_BASE + 31)
+
+/* Quaternary Interrupt Controller */
+#define INT_QUAD_BASE                   (INT_TRI_BASE + 32)
+#define INT_SNOR                        (INT_QUAD_BASE + 0)
+#define INT_USB3                        (INT_QUAD_BASE + 1)
+#define INT_PCIE_INTR                   (INT_QUAD_BASE + 2)
+#define INT_PCIE_MSI                    (INT_QUAD_BASE + 3)
+#define INT_PCIE                        (INT_QUAD_BASE + 4)
+#define INT_AVP_CACHE                   (INT_QUAD_BASE + 5)
+#define INT_TSENSOR                     (INT_QUAD_BASE + 6)
+#define INT_AUDIO_CLUSTER               (INT_QUAD_BASE + 7)
+#define INT_APB_DMA_CH0                 (INT_QUAD_BASE + 8)
+#define INT_APB_DMA_CH1                 (INT_QUAD_BASE + 9)
+#define INT_APB_DMA_CH2                 (INT_QUAD_BASE + 10)
+#define INT_APB_DMA_CH3                 (INT_QUAD_BASE + 11)
+#define INT_APB_DMA_CH4                 (INT_QUAD_BASE + 12)
+#define INT_APB_DMA_CH5                 (INT_QUAD_BASE + 13)
+#define INT_APB_DMA_CH6                 (INT_QUAD_BASE + 14)
+#define INT_APB_DMA_CH7                 (INT_QUAD_BASE + 15)
+#define INT_APB_DMA_CH8                 (INT_QUAD_BASE + 16)
+#define INT_APB_DMA_CH9                 (INT_QUAD_BASE + 17)
+#define INT_APB_DMA_CH10                (INT_QUAD_BASE + 18)
+#define INT_APB_DMA_CH11                (INT_QUAD_BASE + 19)
+#define INT_APB_DMA_CH12                (INT_QUAD_BASE + 20)
+#define INT_APB_DMA_CH13                (INT_QUAD_BASE + 21)
+#define INT_APB_DMA_CH14                (INT_QUAD_BASE + 22)
+#define INT_APB_DMA_CH15                (INT_QUAD_BASE + 23)
+#define INT_I2C4                        (INT_QUAD_BASE + 24)
+#define INT_TMR5                        (INT_QUAD_BASE + 25)
+#define INT_TMR_SHARED                  (INT_QUAD_BASE + 26) /* Deprecated */
+#define INT_WDT_CPU                     (INT_QUAD_BASE + 27)
+#define INT_WDT_AVP                     (INT_QUAD_BASE + 28)
+#define INT_GPIO8                       (INT_QUAD_BASE + 29)
+#define INT_CAR                         (INT_QUAD_BASE + 30)
+#define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
+
+/* Quintary Interrupt Controller */
+#define INT_QUINT_BASE                  (INT_QUAD_BASE + 32)
+#define INT_APB_DMA_CH16                (INT_QUINT_BASE + 0)
+#define INT_APB_DMA_CH17                (INT_QUINT_BASE + 1)
+#define INT_APB_DMA_CH18                (INT_QUINT_BASE + 2)
+#define INT_APB_DMA_CH19                (INT_QUINT_BASE + 3)
+#define INT_APB_DMA_CH20                (INT_QUINT_BASE + 4)
+#define INT_APB_DMA_CH21                (INT_QUINT_BASE + 5)
+#define INT_APB_DMA_CH22                (INT_QUINT_BASE + 6)
+#define INT_APB_DMA_CH23                (INT_QUINT_BASE + 7)
+#define INT_APB_DMA_CH24                (INT_QUINT_BASE + 8)
+#define INT_APB_DMA_CH25                (INT_QUINT_BASE + 9)
+#define INT_APB_DMA_CH26                (INT_QUINT_BASE + 10)
+#define INT_APB_DMA_CH27                (INT_QUINT_BASE + 11)
+#define INT_APB_DMA_CH28                (INT_QUINT_BASE + 12)
+#define INT_APB_DMA_CH29                (INT_QUINT_BASE + 13)
+#define INT_APB_DMA_CH30                (INT_QUINT_BASE + 14)
+#define INT_APB_DMA_CH31                (INT_QUINT_BASE + 15)
+#define INT_CPU0_PMU_INTR               (INT_QUINT_BASE + 16)
+#define INT_CPU1_PMU_INTR               (INT_QUINT_BASE + 17)
+#define INT_CPU2_PMU_INTR               (INT_QUINT_BASE + 18)
+#define INT_CPU3_PMU_INTR               (INT_QUINT_BASE + 19)
+#define INT_CPU4_PMU_INTR               (INT_QUINT_BASE + 20)
+#define INT_CPU5_PMU_INTR               (INT_QUINT_BASE + 21)
+#define INT_CPU6_PMU_INTR               (INT_QUINT_BASE + 22)
+#define INT_CPU7_PMU_INTR               (INT_QUINT_BASE + 23)
+#define INT_TMR6                        (INT_QUINT_BASE + 24)
+#define INT_TMR7                        (INT_QUINT_BASE + 25)
+#define INT_TMR8                        (INT_QUINT_BASE + 26)
+#define INT_TMR9                        (INT_QUINT_BASE + 27)
+#define INT_TMR10                       (INT_QUINT_BASE + 28)
+#define INT_QUINT_RES_29                (INT_QUINT_BASE + 29)
+#define INT_QUINT_RES_30                (INT_QUINT_BASE + 30)
+#define INT_QUINT_RES_31                (INT_QUINT_BASE + 31)
+
+#define INT_GIC_NR                      (INT_QUINT_BASE + 32)
+
+#define INT_MAIN_NR                     (INT_GIC_NR - INT_PRI_BASE)
+
+#define INT_SYNCPT_THRESH_BASE          (INT_QUINT_BASE + 32)
+#define INT_SYNCPT_THRESH_NR            32
+
+#define INT_GPIO_BASE                   (INT_SYNCPT_THRESH_BASE + \
+                                         INT_SYNCPT_THRESH_NR)
+#define INT_GPIO_NR                     (32 * 8)
+
+#define INT_PCI_MSI_BASE                (INT_GPIO_BASE + \
+                                         INT_GPIO_NR)
+#define INT_PCI_MSI_NR                  (32 * 8)
+
+#endif
+
+#define FIQ_START                       INT_GIC_BASE
+
+#define TEGRA_NR_IRQS                   (INT_PCI_MSI_BASE + \
+                                                        INT_PCI_MSI_NR)
+
+#define INT_BOARD_BASE                  TEGRA_NR_IRQS
+
+#define NR_BOARD_IRQS                   64
+
+#define NR_IRQS                         (INT_BOARD_BASE + NR_BOARD_IRQS)
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
new file mode 100644
index 00000000000..7b68baa04f1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -0,0 +1,86 @@
+/*
+ * Platform definitions for tegra-kbc keyboard input driver
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef ASMARM_ARCH_TEGRA_KBC_H
+#define ASMARM_ARCH_TEGRA_KBC_H
+
+#include <linux/types.h>
+#include <linux/input/matrix_keypad.h>
+
+#define KBC_MAX_GPIO    24
+#define KBC_MAX_KPENT   8
+
+#define KBC_MAX_ROW     16
+#define KBC_MAX_COL     8
+#define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)
+
+#define KBC_PIN_GPIO_0          0
+#define KBC_PIN_GPIO_1          1
+#define KBC_PIN_GPIO_2          2
+#define KBC_PIN_GPIO_3          3
+#define KBC_PIN_GPIO_4          4
+#define KBC_PIN_GPIO_5          5
+#define KBC_PIN_GPIO_6          6
+#define KBC_PIN_GPIO_7          7
+#define KBC_PIN_GPIO_8          8
+#define KBC_PIN_GPIO_9          9
+#define KBC_PIN_GPIO_10         10
+#define KBC_PIN_GPIO_11         11
+#define KBC_PIN_GPIO_12         12
+#define KBC_PIN_GPIO_13         13
+#define KBC_PIN_GPIO_14         14
+#define KBC_PIN_GPIO_15         15
+#define KBC_PIN_GPIO_16         16
+#define KBC_PIN_GPIO_17         17
+#define KBC_PIN_GPIO_18         18
+#define KBC_PIN_GPIO_19         19
+#define KBC_PIN_GPIO_20         20
+#define KBC_PIN_GPIO_21         21
+#define KBC_PIN_GPIO_22         22
+#define KBC_PIN_GPIO_23         23
+
+struct tegra_kbc_pin_cfg {
+        bool is_row;
+        bool en;
+        unsigned char num;
+};
+
+struct tegra_kbc_wake_key {
+        u8 row:4;
+        u8 col:4;
+};
+
+struct tegra_kbc_platform_data {
+        unsigned int debounce_cnt;
+        unsigned int repeat_cnt;
+        unsigned int scan_count;
+
+        unsigned int wake_cnt; /* 0:wake on any key >1:wake on wake_cfg */
+        const struct tegra_kbc_wake_key *wake_cfg;
+
+        struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
+        const struct matrix_keymap_data *keymap_data;
+
+        bool wakeup;
+        bool use_fn_map;
+        bool use_ghost_filter;
+        bool disable_ev_rep;
+};
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/kfuse.h b/arch/arm/mach-tegra/include/mach/kfuse.h
new file mode 100644
index 00000000000..cfe85cc86ff
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/kfuse.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-tegra/kfuse.h
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* there are 144 32-bit values in total */
+#define KFUSE_DATA_SZ (144 * 4)
+
+int tegra_kfuse_read(void *dest, size_t len);
diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h
new file mode 100644
index 00000000000..f0d27f0b8ba
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h
@@ -0,0 +1,121 @@
+/*
+ * arch/arm/mach-tegra/include/mach/latency_allowance.h
+ *
+ * Copyright (C) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_LATENCY_ALLOWANCE_H_
+#define _MACH_TEGRA_LATENCY_ALLOWANCE_H_
+
+enum tegra_la_id {
+        TEGRA_LA_AFIR = 0,
+        TEGRA_LA_AFIW,
+        TEGRA_LA_AVPC_ARM7R,
+        TEGRA_LA_AVPC_ARM7W,
+        TEGRA_LA_DISPLAY_0A,
+        TEGRA_LA_DISPLAY_0B,
+        TEGRA_LA_DISPLAY_0C,
+        TEGRA_LA_DISPLAY_1B,
+        TEGRA_LA_DISPLAY_HC,
+        TEGRA_LA_DISPLAY_0AB,
+        TEGRA_LA_DISPLAY_0BB,
+        TEGRA_LA_DISPLAY_0CB,
+        TEGRA_LA_DISPLAY_1BB,
+        TEGRA_LA_DISPLAY_HCB,
+        TEGRA_LA_EPPUP,
+        TEGRA_LA_EPPU,
+        TEGRA_LA_EPPV,
+        TEGRA_LA_EPPY,
+        TEGRA_LA_G2PR,
+        TEGRA_LA_G2SR,
+        TEGRA_LA_G2DR,
+        TEGRA_LA_G2DW,
+        TEGRA_LA_HOST1X_DMAR,
+        TEGRA_LA_HOST1XR,
+        TEGRA_LA_HOST1XW,
+        TEGRA_LA_HDAR,
+        TEGRA_LA_HDAW,
+        TEGRA_LA_ISPW,
+        TEGRA_LA_MPCORER,
+        TEGRA_LA_MPCOREW,
+        TEGRA_LA_MPCORE_LPR,
+        TEGRA_LA_MPCORE_LPW,
+        TEGRA_LA_MPE_UNIFBR,
+        TEGRA_LA_MPE_IPRED,
+        TEGRA_LA_MPE_AMEMRD,
+        TEGRA_LA_MPE_CSRD,
+        TEGRA_LA_MPE_UNIFBW,
+        TEGRA_LA_MPE_CSWR,
+        TEGRA_LA_FDCDRD,
+        TEGRA_LA_IDXSRD,
+        TEGRA_LA_TEXSRD,
+        TEGRA_LA_FDCDWR,
+        TEGRA_LA_FDCDRD2,
+        TEGRA_LA_IDXSRD2,
+        TEGRA_LA_TEXSRD2,
+        TEGRA_LA_FDCDWR2,
+        TEGRA_LA_PPCS_AHBDMAR,
+        TEGRA_LA_PPCS_AHBSLVR,
+        TEGRA_LA_PPCS_AHBDMAW,
+        TEGRA_LA_PPCS_AHBSLVW,
+        TEGRA_LA_PTCR,
+        TEGRA_LA_SATAR,
+        TEGRA_LA_SATAW,
+        TEGRA_LA_VDE_BSEVR,
+        TEGRA_LA_VDE_MBER,
+        TEGRA_LA_VDE_MCER,
+        TEGRA_LA_VDE_TPER,
+        TEGRA_LA_VDE_BSEVW,
+        TEGRA_LA_VDE_DBGW,
+        TEGRA_LA_VDE_MBEW,
+        TEGRA_LA_VDE_TPMW,
+        TEGRA_LA_VI_RUV,
+        TEGRA_LA_VI_WSB,
+        TEGRA_LA_VI_WU,
+        TEGRA_LA_VI_WV,
+        TEGRA_LA_VI_WY,
+        TEGRA_LA_MAX_ID
+};
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_TEGRA_FPGA_PLATFORM)
+static inline int tegra_set_latency_allowance(enum tegra_la_id id,
+                                                int bandwidth_in_mbps)
+{
+        return 0;
+}
+
+static inline int tegra_enable_latency_scaling(enum tegra_la_id id,
+                                                unsigned int threshold_low,
+                                                unsigned int threshold_mid,
+                                                unsigned int threshold_high)
+{
+        return 0;
+}
+
+static inline void tegra_disable_latency_scaling(enum tegra_la_id id)
+{
+        return 0;
+}
+#else
+int tegra_set_latency_allowance(enum tegra_la_id id,
+                                unsigned int bandwidth_in_mbps);
+
+int tegra_enable_latency_scaling(enum tegra_la_id id,
+                                    unsigned int threshold_low,
+                                    unsigned int threshold_mid,
+                                    unsigned int threshold_high);
+
+void tegra_disable_latency_scaling(enum tegra_la_id id);
+#endif
+
+#endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
new file mode 100644
index 00000000000..86f1ff7d06b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-tegra/include/mach/legacy_irq.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
+#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
+
+void tegra_init_legacy_irq_cop(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/mc.h b/arch/arm/mach-tegra/include/mach/mc.h
new file mode 100644
index 00000000000..576153ad08d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/mc.h
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/mach-tegra/include/mach/mc.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_MC_H
+#define __MACH_TEGRA_MC_H
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define TEGRA_MC_FPRI_CTRL_AVPC         0x17c
+#define TEGRA_MC_FPRI_CTRL_DC           0x180
+#define TEGRA_MC_FPRI_CTRL_DCB          0x184
+#define TEGRA_MC_FPRI_CTRL_EPP          0x188
+#define TEGRA_MC_FPRI_CTRL_G2           0x18c
+#define TEGRA_MC_FPRI_CTRL_HC           0x190
+#define TEGRA_MC_FPRI_CTRL_ISP          0x194
+#define TEGRA_MC_FPRI_CTRL_MPCORE       0x198
+#define TEGRA_MC_FPRI_CTRL_MPEA         0x19c
+#define TEGRA_MC_FPRI_CTRL_MPEB         0x1a0
+#define TEGRA_MC_FPRI_CTRL_MPEC         0x1a4
+#define TEGRA_MC_FPRI_CTRL_NV           0x1a8
+#define TEGRA_MC_FPRI_CTRL_PPCS         0x1ac
+#define TEGRA_MC_FPRI_CTRL_VDE          0x1b0
+#define TEGRA_MC_FPRI_CTRL_VI           0x1b4
+
+#define TEGRA_MC_CLIENT_AVPCARM7R       ((TEGRA_MC_FPRI_CTRL_AVPC << 8) | 0)
+#define TEGRA_MC_CLIENT_AVPCARM7W       ((TEGRA_MC_FPRI_CTRL_AVPC << 8) | 2)
+#define TEGRA_MC_CLIENT_DISPLAY0A       ((TEGRA_MC_FPRI_CTRL_DC << 8) | 0)
+#define TEGRA_MC_CLIENT_DISPLAY0B       ((TEGRA_MC_FPRI_CTRL_DC << 8) | 2)
+#define TEGRA_MC_CLIENT_DISPLAY0C       ((TEGRA_MC_FPRI_CTRL_DC << 8) | 4)
+#define TEGRA_MC_CLIENT_DISPLAY1B       ((TEGRA_MC_FPRI_CTRL_DC << 8) | 6)
+#define TEGRA_MC_CLIENT_DISPLAYHC       ((TEGRA_MC_FPRI_CTRL_DC << 8) | 8)
+#define TEGRA_MC_CLIENT_DISPLAY0AB      ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 0)
+#define TEGRA_MC_CLIENT_DISPLAY0BB      ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 2)
+#define TEGRA_MC_CLIENT_DISPLAY0CB      ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 4)
+#define TEGRA_MC_CLIENT_DISPLAY1BB      ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 6)
+#define TEGRA_MC_CLIENT_DISPLAYHCB      ((TEGRA_MC_FPRI_CTRL_DCB << 8) | 8)
+#define TEGRA_MC_CLIENT_EPPUP           ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 0)
+#define TEGRA_MC_CLIENT_EPPU            ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 2)
+#define TEGRA_MC_CLIENT_EPPV            ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 4)
+#define TEGRA_MC_CLIENT_EPPY            ((TEGRA_MC_FPRI_CTRL_EPP << 8) | 6)
+#define TEGRA_MC_CLIENT_G2PR            ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 0)
+#define TEGRA_MC_CLIENT_G2SR            ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 2)
+#define TEGRA_MC_CLIENT_G2DR            ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 4)
+#define TEGRA_MC_CLIENT_G2DW            ((TEGRA_MC_FPRI_CTRL_G2 << 8) | 6)
+#define TEGRA_MC_CLIENT_HOST1XDMAR      ((TEGRA_MC_FPRI_CTRL_HC << 8) | 0)
+#define TEGRA_MC_CLIENT_HOST1XR         ((TEGRA_MC_FPRI_CTRL_HC << 8) | 2)
+#define TEGRA_MC_CLIENT_HOST1XW         ((TEGRA_MC_FPRI_CTRL_HC << 8) | 4)
+#define TEGRA_MC_CLIENT_ISPW            ((TEGRA_MC_FPRI_CTRL_ISP << 8) | 0)
+#define TEGRA_MC_CLIENT_MPCORER         ((TEGRA_MC_FPRI_CTRL_MPCORE << 8) | 0)
+#define TEGRA_MC_CLIENT_MPCOREW         ((TEGRA_MC_FPRI_CTRL_MPCORE << 8) | 2)
+#define TEGRA_MC_CLIENT_MPEAMEMRD       ((TEGRA_MC_FPRI_CTRL_MPEA << 8) | 0)
+#define TEGRA_MC_CLIENT_MPEUNIFBR       ((TEGRA_MC_FPRI_CTRL_MPEB << 8) | 0)
+#define TEGRA_MC_CLIENT_MPE_IPRED       ((TEGRA_MC_FPRI_CTRL_MPEB << 8) | 2)
+#define TEGRA_MC_CLIENT_MPEUNIFBW       ((TEGRA_MC_FPRI_CTRL_MPEB << 8) | 4)
+#define TEGRA_MC_CLIENT_MPECSRD         ((TEGRA_MC_FPRI_CTRL_MPEC << 8) | 0)
+#define TEGRA_MC_CLIENT_MPECSWR         ((TEGRA_MC_FPRI_CTRL_MPEC << 8) | 2)
+#define TEGRA_MC_CLIENT_FDCDRD          ((TEGRA_MC_FPRI_CTRL_NV << 8) | 0)
+#define TEGRA_MC_CLIENT_IDXSRD          ((TEGRA_MC_FPRI_CTRL_NV << 8) | 2)
+#define TEGRA_MC_CLIENT_TEXSRD          ((TEGRA_MC_FPRI_CTRL_NV << 8) | 4)
+#define TEGRA_MC_CLIENT_FDCDWR          ((TEGRA_MC_FPRI_CTRL_NV << 8) | 6)
+#define TEGRA_MC_CLIENT_PPCSAHBDMAR     ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 0)
+#define TEGRA_MC_CLIENT_PPCSAHBSLVR     ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 2)
+#define TEGRA_MC_CLIENT_PPCSAHBDMAW     ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 4)
+#define TEGRA_MC_CLIENT_PPCSAHBSLVW     ((TEGRA_MC_FPRI_CTRL_PPCS << 8) | 6)
+#define TEGRA_MC_CLIENT_VDEBSEVR        ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 0)
+#define TEGRA_MC_CLIENT_VDEMBER         ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 2)
+#define TEGRA_MC_CLIENT_VDEMCER         ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 4)
+#define TEGRA_MC_CLIENT_VDETPER         ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 6)
+#define TEGRA_MC_CLIENT_VDEBSEVW        ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 8)
+#define TEGRA_MC_CLIENT_VDEMBEW         ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 10)
+#define TEGRA_MC_CLIENT_VDETPMW         ((TEGRA_MC_FPRI_CTRL_VDE << 8) | 12)
+#define TEGRA_MC_CLIENT_VIRUV           ((TEGRA_MC_FPRI_CTRL_VI << 8) | 0)
+#define TEGRA_MC_CLIENT_VIWSB           ((TEGRA_MC_FPRI_CTRL_VI << 8) | 2)
+#define TEGRA_MC_CLIENT_VIWU            ((TEGRA_MC_FPRI_CTRL_VI << 8) | 4)
+#define TEGRA_MC_CLIENT_VIWV            ((TEGRA_MC_FPRI_CTRL_VI << 8) | 6)
+#define TEGRA_MC_CLIENT_VIWY            ((TEGRA_MC_FPRI_CTRL_VI << 8) | 8)
+
+#define TEGRA_MC_PRIO_LOWEST            0
+#define TEGRA_MC_PRIO_LOW               1
+#define TEGRA_MC_PRIO_MED               2
+#define TEGRA_MC_PRIO_HIGH              3
+#define TEGRA_MC_PRIO_MASK              3
+
+void tegra_mc_set_priority(unsigned long client, unsigned long prio);
+
+#else
+        /* !!!FIXME!!! IMPLEMENT ME */
+#define tegra_mc_set_priority(client, prio) \
+        do { /* nothing for now */ } while (0)
+#endif
+
+int tegra_mc_get_tiled_memory_bandwidth_multiplier(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
new file mode 100644
index 00000000000..5f51066482e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-tegra/include/mach/memory.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_MEMORY_H
+#define __MACH_TEGRA_MEMORY_H
+
+/* physical offset of RAM */
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#define PLAT_PHYS_OFFSET                UL(0)
+#else
+#define PLAT_PHYS_OFFSET                UL(0x80000000)
+#endif
+
+/*
+ * Unaligned DMA causes tegra dma to place data on 4-byte boundary after
+ * expected address. Call to skb_reserve(skb, NET_IP_ALIGN) was causing skb
+ * buffers in usbnet.c to become unaligned.
+ */
+#define NET_IP_ALIGN    0
+
+#define CONSISTENT_DMA_SIZE     (14 * SZ_1M)
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/nand.h b/arch/arm/mach-tegra/include/mach/nand.h
new file mode 100644
index 00000000000..91ad7d1c9ae
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/nand.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-tegra/include/mach/nand.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Dima Zavin <dmitriyz@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_NAND_H
+#define __MACH_TEGRA_NAND_H
+
+struct tegra_nand_chip_parms {
+        uint8_t vendor_id;
+        uint8_t device_id;
+        uint32_t flags;
+        uint8_t read_id_fourth_byte;
+        uint32_t capacity;
+
+        /* all timing info is in nanoseconds */
+        struct {
+                uint32_t trp;
+                uint32_t trh;
+                uint32_t twp;
+                uint32_t twh;
+                uint32_t tcs;
+                uint32_t twhr;
+                uint32_t tcr_tar_trr;
+                uint32_t twb;
+                uint32_t trp_resp;
+                uint32_t tadl;
+        } timing;
+};
+
+struct tegra_nand_platform {
+        uint8_t max_chips;
+        struct tegra_nand_chip_parms *chip_parms;
+        unsigned int nr_chip_parms;
+        struct mtd_partition *parts;
+        unsigned int nr_parts;
+        int wp_gpio;
+};
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/nvmap.h b/arch/arm/mach-tegra/include/mach/nvmap.h
new file mode 100644
index 00000000000..88f913fc29d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/nvmap.h
@@ -0,0 +1,158 @@
+/*
+ * arch/arm/mach-tegra/include/mach/nvmap.h
+ *
+ * structure declarations for nvmem and nvmap user-space ioctls
+ *
+ * Copyright (c) 2009-2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/ioctl.h>
+#include <linux/file.h>
+#include <linux/rbtree.h>
+
+#if !defined(__KERNEL__)
+#define __user
+#endif
+
+#ifndef __NVMAP_H
+#define __NVMAP_H
+
+#define NVMAP_HEAP_SYSMEM  (1ul<<31)
+#define NVMAP_HEAP_IOVMM   (1ul<<30)
+
+/* common carveout heaps */
+#define NVMAP_HEAP_CARVEOUT_IRAM    (1ul<<29)
+#define NVMAP_HEAP_CARVEOUT_VPR     (1ul<<28)
+#define NVMAP_HEAP_CARVEOUT_GENERIC (1ul<<0)
+
+#define NVMAP_HEAP_CARVEOUT_MASK    (NVMAP_HEAP_IOVMM - 1)
+
+/* allocation flags */
+#define NVMAP_HANDLE_UNCACHEABLE     (0x0ul << 0)
+#define NVMAP_HANDLE_WRITE_COMBINE   (0x1ul << 0)
+#define NVMAP_HANDLE_INNER_CACHEABLE (0x2ul << 0)
+#define NVMAP_HANDLE_CACHEABLE       (0x3ul << 0)
+#define NVMAP_HANDLE_CACHE_FLAG      (0x3ul << 0)
+
+#define NVMAP_HANDLE_SECURE          (0x1ul << 2)
+
+
+#if defined(__KERNEL__)
+
+#if defined(CONFIG_TEGRA_NVMAP)
+struct nvmap_handle;
+struct nvmap_client;
+struct nvmap_device;
+#define nvmap_ref_to_handle(_ref) (*(struct nvmap_handle **)(_ref))
+/* Convert User space handle to Kernel. */
+#define nvmap_convert_handle_u2k(h) (h)
+#elif defined(CONFIG_ION_TEGRA)
+/* For Ion Mem Manager support through nvmap_* API's. */
+#include "../../../../../drivers/gpu/ion/ion_priv.h"
+
+#define nvmap_client ion_client
+#define nvmap_device ion_device
+#define nvmap_handle ion_handle
+#define nvmap_handle_ref ion_handle
+#define nvmap_ref_to_handle(_ref) (struct ion_handle *)_ref
+/* Convert User space handle to Kernel. */
+#define nvmap_convert_handle_u2k(h) ({ \
+        if ((u32)h >= TASK_SIZE) { \
+                pr_err("Invalid user space handle."); \
+                BUG(); \
+        } \
+        (*((u32 *)h)); })
+#endif
+
+#define nvmap_id_to_handle(_id) ((struct nvmap_handle *)(_id))
+
+
+struct nvmap_pinarray_elem {
+        __u32 patch_mem;
+        __u32 patch_offset;
+        __u32 pin_mem;
+        __u32 pin_offset;
+        __u32 reloc_shift;
+};
+
+#if defined(CONFIG_TEGRA_NVMAP)
+/* handle_ref objects are client-local references to an nvmap_handle;
+ * they are distinct objects so that handles can be unpinned and
+ * unreferenced the correct number of times when a client abnormally
+ * terminates */
+struct nvmap_handle_ref {
+        struct nvmap_handle *handle;
+        struct rb_node  node;
+        atomic_t        dupes;  /* number of times to free on file close */
+        atomic_t        pin;    /* number of times to unpin on free */
+};
+#endif
+
+struct nvmap_client *nvmap_create_client(struct nvmap_device *dev,
+                                         const char *name);
+
+struct nvmap_handle_ref *nvmap_alloc(struct nvmap_client *client, size_t size,
+                                     size_t align, unsigned int flags,
+                                     unsigned int heap_mask);
+
+void nvmap_free(struct nvmap_client *client, struct nvmap_handle_ref *r);
+
+void *nvmap_mmap(struct nvmap_handle_ref *r);
+
+void nvmap_munmap(struct nvmap_handle_ref *r, void *addr);
+
+struct nvmap_client *nvmap_client_get_file(int fd);
+
+struct nvmap_client *nvmap_client_get(struct nvmap_client *client);
+
+void nvmap_client_put(struct nvmap_client *c);
+
+phys_addr_t nvmap_pin(struct nvmap_client *c, struct nvmap_handle_ref *r);
+
+phys_addr_t nvmap_handle_address(struct nvmap_client *c, unsigned long id);
+
+void nvmap_unpin(struct nvmap_client *client, struct nvmap_handle_ref *r);
+
+int nvmap_pin_array(struct nvmap_client *client, struct nvmap_handle *gather,
+                    const struct nvmap_pinarray_elem *arr, int nr,
+                    struct nvmap_handle **unique);
+
+void nvmap_unpin_handles(struct nvmap_client *client,
+                         struct nvmap_handle **h, int nr);
+
+int nvmap_patch_word(struct nvmap_client *client,
+                     struct nvmap_handle *patch,
+                     u32 patch_offset, u32 patch_value);
+
+struct nvmap_platform_carveout {
+        const char *name;
+        unsigned int usage_mask;
+        phys_addr_t base;
+        size_t size;
+        size_t buddy_size;
+};
+
+struct nvmap_platform_data {
+        const struct nvmap_platform_carveout *carveouts;
+        unsigned int nr_carveouts;
+};
+
+extern struct nvmap_device *nvmap_dev;
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/pci.h b/arch/arm/mach-tegra/include/mach/pci.h
new file mode 100644
index 00000000000..388ad320775
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pci.h
@@ -0,0 +1,38 @@
+/*
+ *  arch/arm/mach-tegra/include/mach/pci.h
+ *
+ *  Header file containing constants for the tegra PCIe driver.
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_PCI_H
+#define __MACH_PCI_H
+
+#include <linux/pci.h>
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        #define MAX_PCIE_SUPPORTED_PORTS 2
+#else
+        #define MAX_PCIE_SUPPORTED_PORTS 3
+#endif
+
+struct tegra_pci_platform_data {
+        int port_status[MAX_PCIE_SUPPORTED_PORTS];
+        bool use_dock_detect;
+        int gpio;
+};
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
new file mode 100644
index 00000000000..4c262634726
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
@@ -0,0 +1,184 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_T2_H
+#define __MACH_TEGRA_PINMUX_T2_H
+
+enum tegra_pingroup {
+        TEGRA_PINGROUP_ATA = 0,
+        TEGRA_PINGROUP_ATB,
+        TEGRA_PINGROUP_ATC,
+        TEGRA_PINGROUP_ATD,
+        TEGRA_PINGROUP_ATE,
+        TEGRA_PINGROUP_CDEV1,
+        TEGRA_PINGROUP_CDEV2,
+        TEGRA_PINGROUP_CRTP,
+        TEGRA_PINGROUP_CSUS,
+        TEGRA_PINGROUP_DAP1,
+        TEGRA_PINGROUP_DAP2,
+        TEGRA_PINGROUP_DAP3,
+        TEGRA_PINGROUP_DAP4,
+        TEGRA_PINGROUP_DDC,
+        TEGRA_PINGROUP_DTA,
+        TEGRA_PINGROUP_DTB,
+        TEGRA_PINGROUP_DTC,
+        TEGRA_PINGROUP_DTD,
+        TEGRA_PINGROUP_DTE,
+        TEGRA_PINGROUP_DTF,
+        TEGRA_PINGROUP_GMA,
+        TEGRA_PINGROUP_GMB,
+        TEGRA_PINGROUP_GMC,
+        TEGRA_PINGROUP_GMD,
+        TEGRA_PINGROUP_GME,
+        TEGRA_PINGROUP_GPU,
+        TEGRA_PINGROUP_GPU7,
+        TEGRA_PINGROUP_GPV,
+        TEGRA_PINGROUP_HDINT,
+        TEGRA_PINGROUP_I2CP,
+        TEGRA_PINGROUP_IRRX,
+        TEGRA_PINGROUP_IRTX,
+        TEGRA_PINGROUP_KBCA,
+        TEGRA_PINGROUP_KBCB,
+        TEGRA_PINGROUP_KBCC,
+        TEGRA_PINGROUP_KBCD,
+        TEGRA_PINGROUP_KBCE,
+        TEGRA_PINGROUP_KBCF,
+        TEGRA_PINGROUP_LCSN,
+        TEGRA_PINGROUP_LD0,
+        TEGRA_PINGROUP_LD1,
+        TEGRA_PINGROUP_LD10,
+        TEGRA_PINGROUP_LD11,
+        TEGRA_PINGROUP_LD12,
+        TEGRA_PINGROUP_LD13,
+        TEGRA_PINGROUP_LD14,
+        TEGRA_PINGROUP_LD15,
+        TEGRA_PINGROUP_LD16,
+        TEGRA_PINGROUP_LD17,
+        TEGRA_PINGROUP_LD2,
+        TEGRA_PINGROUP_LD3,
+        TEGRA_PINGROUP_LD4,
+        TEGRA_PINGROUP_LD5,
+        TEGRA_PINGROUP_LD6,
+        TEGRA_PINGROUP_LD7,
+        TEGRA_PINGROUP_LD8,
+        TEGRA_PINGROUP_LD9,
+        TEGRA_PINGROUP_LDC,
+        TEGRA_PINGROUP_LDI,
+        TEGRA_PINGROUP_LHP0,
+        TEGRA_PINGROUP_LHP1,
+        TEGRA_PINGROUP_LHP2,
+        TEGRA_PINGROUP_LHS,
+        TEGRA_PINGROUP_LM0,
+        TEGRA_PINGROUP_LM1,
+        TEGRA_PINGROUP_LPP,
+        TEGRA_PINGROUP_LPW0,
+        TEGRA_PINGROUP_LPW1,
+        TEGRA_PINGROUP_LPW2,
+        TEGRA_PINGROUP_LSC0,
+        TEGRA_PINGROUP_LSC1,
+        TEGRA_PINGROUP_LSCK,
+        TEGRA_PINGROUP_LSDA,
+        TEGRA_PINGROUP_LSDI,
+        TEGRA_PINGROUP_LSPI,
+        TEGRA_PINGROUP_LVP0,
+        TEGRA_PINGROUP_LVP1,
+        TEGRA_PINGROUP_LVS,
+        TEGRA_PINGROUP_OWC,
+        TEGRA_PINGROUP_PMC,
+        TEGRA_PINGROUP_PTA,
+        TEGRA_PINGROUP_RM,
+        TEGRA_PINGROUP_SDB,
+        TEGRA_PINGROUP_SDC,
+        TEGRA_PINGROUP_SDD,
+        TEGRA_PINGROUP_SDIO1,
+        TEGRA_PINGROUP_SLXA,
+        TEGRA_PINGROUP_SLXC,
+        TEGRA_PINGROUP_SLXD,
+        TEGRA_PINGROUP_SLXK,
+        TEGRA_PINGROUP_SPDI,
+        TEGRA_PINGROUP_SPDO,
+        TEGRA_PINGROUP_SPIA,
+        TEGRA_PINGROUP_SPIB,
+        TEGRA_PINGROUP_SPIC,
+        TEGRA_PINGROUP_SPID,
+        TEGRA_PINGROUP_SPIE,
+        TEGRA_PINGROUP_SPIF,
+        TEGRA_PINGROUP_SPIG,
+        TEGRA_PINGROUP_SPIH,
+        TEGRA_PINGROUP_UAA,
+        TEGRA_PINGROUP_UAB,
+        TEGRA_PINGROUP_UAC,
+        TEGRA_PINGROUP_UAD,
+        TEGRA_PINGROUP_UCA,
+        TEGRA_PINGROUP_UCB,
+        TEGRA_PINGROUP_UDA,
+        /* these pin groups only have pullup and pull down control */
+        TEGRA_PINGROUP_CK32,
+        TEGRA_PINGROUP_DDRC,
+        TEGRA_PINGROUP_PMCA,
+        TEGRA_PINGROUP_PMCB,
+        TEGRA_PINGROUP_PMCC,
+        TEGRA_PINGROUP_PMCD,
+        TEGRA_PINGROUP_PMCE,
+        TEGRA_PINGROUP_XM2C,
+        TEGRA_PINGROUP_XM2D,
+        TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+        TEGRA_DRIVE_PINGROUP_AO1 = 0,
+        TEGRA_DRIVE_PINGROUP_AO2,
+        TEGRA_DRIVE_PINGROUP_AT1,
+        TEGRA_DRIVE_PINGROUP_AT2,
+        TEGRA_DRIVE_PINGROUP_CDEV1,
+        TEGRA_DRIVE_PINGROUP_CDEV2,
+        TEGRA_DRIVE_PINGROUP_CSUS,
+        TEGRA_DRIVE_PINGROUP_DAP1,
+        TEGRA_DRIVE_PINGROUP_DAP2,
+        TEGRA_DRIVE_PINGROUP_DAP3,
+        TEGRA_DRIVE_PINGROUP_DAP4,
+        TEGRA_DRIVE_PINGROUP_DBG,
+        TEGRA_DRIVE_PINGROUP_LCD1,
+        TEGRA_DRIVE_PINGROUP_LCD2,
+        TEGRA_DRIVE_PINGROUP_SDMMC2,
+        TEGRA_DRIVE_PINGROUP_SDMMC3,
+        TEGRA_DRIVE_PINGROUP_SPI,
+        TEGRA_DRIVE_PINGROUP_UAA,
+        TEGRA_DRIVE_PINGROUP_UAB,
+        TEGRA_DRIVE_PINGROUP_UART2,
+        TEGRA_DRIVE_PINGROUP_UART3,
+        TEGRA_DRIVE_PINGROUP_VI1,
+        TEGRA_DRIVE_PINGROUP_VI2,
+        TEGRA_DRIVE_PINGROUP_XM2A,
+        TEGRA_DRIVE_PINGROUP_XM2C,
+        TEGRA_DRIVE_PINGROUP_XM2D,
+        TEGRA_DRIVE_PINGROUP_XM2CLK,
+        TEGRA_DRIVE_PINGROUP_MEMCOMP,
+        TEGRA_DRIVE_PINGROUP_SDIO1,
+        TEGRA_DRIVE_PINGROUP_CRT,
+        TEGRA_DRIVE_PINGROUP_DDC,
+        TEGRA_DRIVE_PINGROUP_GMA,
+        TEGRA_DRIVE_PINGROUP_GMB,
+        TEGRA_DRIVE_PINGROUP_GMC,
+        TEGRA_DRIVE_PINGROUP_GMD,
+        TEGRA_DRIVE_PINGROUP_GME,
+        TEGRA_DRIVE_PINGROUP_OWR,
+        TEGRA_DRIVE_PINGROUP_UAD,
+        TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t3.h b/arch/arm/mach-tegra/include/mach/pinmux-t3.h
new file mode 100644
index 00000000000..12fd5e8ffc1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t3.h
@@ -0,0 +1,321 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-t3.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_T3_H
+#define __MACH_TEGRA_PINMUX_T3_H
+
+#define TEGRA_PINMUX_HAS_IO_DIRECTION   1
+
+enum tegra_pingroup {
+        TEGRA_PINGROUP_ULPI_DATA0 = 0,
+        TEGRA_PINGROUP_ULPI_DATA1,
+        TEGRA_PINGROUP_ULPI_DATA2,
+        TEGRA_PINGROUP_ULPI_DATA3,
+        TEGRA_PINGROUP_ULPI_DATA4,
+        TEGRA_PINGROUP_ULPI_DATA5,
+        TEGRA_PINGROUP_ULPI_DATA6,
+        TEGRA_PINGROUP_ULPI_DATA7,
+        TEGRA_PINGROUP_ULPI_CLK,
+        TEGRA_PINGROUP_ULPI_DIR,
+        TEGRA_PINGROUP_ULPI_NXT,
+        TEGRA_PINGROUP_ULPI_STP,
+        TEGRA_PINGROUP_DAP3_FS,
+        TEGRA_PINGROUP_DAP3_DIN,
+        TEGRA_PINGROUP_DAP3_DOUT,
+        TEGRA_PINGROUP_DAP3_SCLK,
+        TEGRA_PINGROUP_GPIO_PV0,
+        TEGRA_PINGROUP_GPIO_PV1,
+        TEGRA_PINGROUP_SDMMC1_CLK,
+        TEGRA_PINGROUP_SDMMC1_CMD,
+        TEGRA_PINGROUP_SDMMC1_DAT3,
+        TEGRA_PINGROUP_SDMMC1_DAT2,
+        TEGRA_PINGROUP_SDMMC1_DAT1,
+        TEGRA_PINGROUP_SDMMC1_DAT0,
+        TEGRA_PINGROUP_GPIO_PV2,
+        TEGRA_PINGROUP_GPIO_PV3,
+        TEGRA_PINGROUP_CLK2_OUT,
+        TEGRA_PINGROUP_CLK2_REQ,
+        TEGRA_PINGROUP_LCD_PWR1,
+        TEGRA_PINGROUP_LCD_PWR2,
+        TEGRA_PINGROUP_LCD_SDIN,
+        TEGRA_PINGROUP_LCD_SDOUT,
+        TEGRA_PINGROUP_LCD_WR_N,
+        TEGRA_PINGROUP_LCD_CS0_N,
+        TEGRA_PINGROUP_LCD_DC0,
+        TEGRA_PINGROUP_LCD_SCK,
+        TEGRA_PINGROUP_LCD_PWR0,
+        TEGRA_PINGROUP_LCD_PCLK,
+        TEGRA_PINGROUP_LCD_DE,
+        TEGRA_PINGROUP_LCD_HSYNC,
+        TEGRA_PINGROUP_LCD_VSYNC,
+        TEGRA_PINGROUP_LCD_D0,
+        TEGRA_PINGROUP_LCD_D1,
+        TEGRA_PINGROUP_LCD_D2,
+        TEGRA_PINGROUP_LCD_D3,
+        TEGRA_PINGROUP_LCD_D4,
+        TEGRA_PINGROUP_LCD_D5,
+        TEGRA_PINGROUP_LCD_D6,
+        TEGRA_PINGROUP_LCD_D7,
+        TEGRA_PINGROUP_LCD_D8,
+        TEGRA_PINGROUP_LCD_D9,
+        TEGRA_PINGROUP_LCD_D10,
+        TEGRA_PINGROUP_LCD_D11,
+        TEGRA_PINGROUP_LCD_D12,
+        TEGRA_PINGROUP_LCD_D13,
+        TEGRA_PINGROUP_LCD_D14,
+        TEGRA_PINGROUP_LCD_D15,
+        TEGRA_PINGROUP_LCD_D16,
+        TEGRA_PINGROUP_LCD_D17,
+        TEGRA_PINGROUP_LCD_D18,
+        TEGRA_PINGROUP_LCD_D19,
+        TEGRA_PINGROUP_LCD_D20,
+        TEGRA_PINGROUP_LCD_D21,
+        TEGRA_PINGROUP_LCD_D22,
+        TEGRA_PINGROUP_LCD_D23,
+        TEGRA_PINGROUP_LCD_CS1_N,
+        TEGRA_PINGROUP_LCD_M1,
+        TEGRA_PINGROUP_LCD_DC1,
+        TEGRA_PINGROUP_HDMI_INT,
+        TEGRA_PINGROUP_DDC_SCL,
+        TEGRA_PINGROUP_DDC_SDA,
+        TEGRA_PINGROUP_CRT_HSYNC,
+        TEGRA_PINGROUP_CRT_VSYNC,
+        TEGRA_PINGROUP_VI_D0,
+        TEGRA_PINGROUP_VI_D1,
+        TEGRA_PINGROUP_VI_D2,
+        TEGRA_PINGROUP_VI_D3,
+        TEGRA_PINGROUP_VI_D4,
+        TEGRA_PINGROUP_VI_D5,
+        TEGRA_PINGROUP_VI_D6,
+        TEGRA_PINGROUP_VI_D7,
+        TEGRA_PINGROUP_VI_D8,
+        TEGRA_PINGROUP_VI_D9,
+        TEGRA_PINGROUP_VI_D10,
+        TEGRA_PINGROUP_VI_D11,
+        TEGRA_PINGROUP_VI_PCLK,
+        TEGRA_PINGROUP_VI_MCLK,
+        TEGRA_PINGROUP_VI_VSYNC,
+        TEGRA_PINGROUP_VI_HSYNC,
+        TEGRA_PINGROUP_UART2_RXD,
+        TEGRA_PINGROUP_UART2_TXD,
+        TEGRA_PINGROUP_UART2_RTS_N,
+        TEGRA_PINGROUP_UART2_CTS_N,
+        TEGRA_PINGROUP_UART3_TXD,
+        TEGRA_PINGROUP_UART3_RXD,
+        TEGRA_PINGROUP_UART3_CTS_N,
+        TEGRA_PINGROUP_UART3_RTS_N,
+        TEGRA_PINGROUP_GPIO_PU0,
+        TEGRA_PINGROUP_GPIO_PU1,
+        TEGRA_PINGROUP_GPIO_PU2,
+        TEGRA_PINGROUP_GPIO_PU3,
+        TEGRA_PINGROUP_GPIO_PU4,
+        TEGRA_PINGROUP_GPIO_PU5,
+        TEGRA_PINGROUP_GPIO_PU6,
+        TEGRA_PINGROUP_GEN1_I2C_SDA,
+        TEGRA_PINGROUP_GEN1_I2C_SCL,
+        TEGRA_PINGROUP_DAP4_FS,
+        TEGRA_PINGROUP_DAP4_DIN,
+        TEGRA_PINGROUP_DAP4_DOUT,
+        TEGRA_PINGROUP_DAP4_SCLK,
+        TEGRA_PINGROUP_CLK3_OUT,
+        TEGRA_PINGROUP_CLK3_REQ,
+        TEGRA_PINGROUP_GMI_WP_N,
+        TEGRA_PINGROUP_GMI_IORDY,
+        TEGRA_PINGROUP_GMI_WAIT,
+        TEGRA_PINGROUP_GMI_ADV_N,
+        TEGRA_PINGROUP_GMI_CLK,
+        TEGRA_PINGROUP_GMI_CS0_N,
+        TEGRA_PINGROUP_GMI_CS1_N,
+        TEGRA_PINGROUP_GMI_CS2_N,
+        TEGRA_PINGROUP_GMI_CS3_N,
+        TEGRA_PINGROUP_GMI_CS4_N,
+        TEGRA_PINGROUP_GMI_CS6_N,
+        TEGRA_PINGROUP_GMI_CS7_N,
+        TEGRA_PINGROUP_GMI_AD0,
+        TEGRA_PINGROUP_GMI_AD1,
+        TEGRA_PINGROUP_GMI_AD2,
+        TEGRA_PINGROUP_GMI_AD3,
+        TEGRA_PINGROUP_GMI_AD4,
+        TEGRA_PINGROUP_GMI_AD5,
+        TEGRA_PINGROUP_GMI_AD6,
+        TEGRA_PINGROUP_GMI_AD7,
+        TEGRA_PINGROUP_GMI_AD8,
+        TEGRA_PINGROUP_GMI_AD9,
+        TEGRA_PINGROUP_GMI_AD10,
+        TEGRA_PINGROUP_GMI_AD11,
+        TEGRA_PINGROUP_GMI_AD12,
+        TEGRA_PINGROUP_GMI_AD13,
+        TEGRA_PINGROUP_GMI_AD14,
+        TEGRA_PINGROUP_GMI_AD15,
+        TEGRA_PINGROUP_GMI_A16,
+        TEGRA_PINGROUP_GMI_A17,
+        TEGRA_PINGROUP_GMI_A18,
+        TEGRA_PINGROUP_GMI_A19,
+        TEGRA_PINGROUP_GMI_WR_N,
+        TEGRA_PINGROUP_GMI_OE_N,
+        TEGRA_PINGROUP_GMI_DQS,
+        TEGRA_PINGROUP_GMI_RST_N,
+        TEGRA_PINGROUP_GEN2_I2C_SCL,
+        TEGRA_PINGROUP_GEN2_I2C_SDA,
+        TEGRA_PINGROUP_SDMMC4_CLK,
+        TEGRA_PINGROUP_SDMMC4_CMD,
+        TEGRA_PINGROUP_SDMMC4_DAT0,
+        TEGRA_PINGROUP_SDMMC4_DAT1,
+        TEGRA_PINGROUP_SDMMC4_DAT2,
+        TEGRA_PINGROUP_SDMMC4_DAT3,
+        TEGRA_PINGROUP_SDMMC4_DAT4,
+        TEGRA_PINGROUP_SDMMC4_DAT5,
+        TEGRA_PINGROUP_SDMMC4_DAT6,
+        TEGRA_PINGROUP_SDMMC4_DAT7,
+        TEGRA_PINGROUP_SDMMC4_RST_N,
+        TEGRA_PINGROUP_CAM_MCLK,
+        TEGRA_PINGROUP_GPIO_PCC1,
+        TEGRA_PINGROUP_GPIO_PBB0,
+        TEGRA_PINGROUP_CAM_I2C_SCL,
+        TEGRA_PINGROUP_CAM_I2C_SDA,
+        TEGRA_PINGROUP_GPIO_PBB3,
+        TEGRA_PINGROUP_GPIO_PBB4,
+        TEGRA_PINGROUP_GPIO_PBB5,
+        TEGRA_PINGROUP_GPIO_PBB6,
+        TEGRA_PINGROUP_GPIO_PBB7,
+        TEGRA_PINGROUP_GPIO_PCC2,
+        TEGRA_PINGROUP_JTAG_RTCK,
+        TEGRA_PINGROUP_PWR_I2C_SCL,
+        TEGRA_PINGROUP_PWR_I2C_SDA,
+        TEGRA_PINGROUP_KB_ROW0,
+        TEGRA_PINGROUP_KB_ROW1,
+        TEGRA_PINGROUP_KB_ROW2,
+        TEGRA_PINGROUP_KB_ROW3,
+        TEGRA_PINGROUP_KB_ROW4,
+        TEGRA_PINGROUP_KB_ROW5,
+        TEGRA_PINGROUP_KB_ROW6,
+        TEGRA_PINGROUP_KB_ROW7,
+        TEGRA_PINGROUP_KB_ROW8,
+        TEGRA_PINGROUP_KB_ROW9,
+        TEGRA_PINGROUP_KB_ROW10,
+        TEGRA_PINGROUP_KB_ROW11,
+        TEGRA_PINGROUP_KB_ROW12,
+        TEGRA_PINGROUP_KB_ROW13,
+        TEGRA_PINGROUP_KB_ROW14,
+        TEGRA_PINGROUP_KB_ROW15,
+        TEGRA_PINGROUP_KB_COL0,
+        TEGRA_PINGROUP_KB_COL1,
+        TEGRA_PINGROUP_KB_COL2,
+        TEGRA_PINGROUP_KB_COL3,
+        TEGRA_PINGROUP_KB_COL4,
+        TEGRA_PINGROUP_KB_COL5,
+        TEGRA_PINGROUP_KB_COL6,
+        TEGRA_PINGROUP_KB_COL7,
+        TEGRA_PINGROUP_CLK_32K_OUT,
+        TEGRA_PINGROUP_SYS_CLK_REQ,
+        TEGRA_PINGROUP_CORE_PWR_REQ,
+        TEGRA_PINGROUP_CPU_PWR_REQ,
+        TEGRA_PINGROUP_PWR_INT_N,
+        TEGRA_PINGROUP_CLK_32K_IN,
+        TEGRA_PINGROUP_OWR,
+        TEGRA_PINGROUP_DAP1_FS,
+        TEGRA_PINGROUP_DAP1_DIN,
+        TEGRA_PINGROUP_DAP1_DOUT,
+        TEGRA_PINGROUP_DAP1_SCLK,
+        TEGRA_PINGROUP_CLK1_REQ,
+        TEGRA_PINGROUP_CLK1_OUT,
+        TEGRA_PINGROUP_SPDIF_IN,
+        TEGRA_PINGROUP_SPDIF_OUT,
+        TEGRA_PINGROUP_DAP2_FS,
+        TEGRA_PINGROUP_DAP2_DIN,
+        TEGRA_PINGROUP_DAP2_DOUT,
+        TEGRA_PINGROUP_DAP2_SCLK,
+        TEGRA_PINGROUP_SPI2_MOSI,
+        TEGRA_PINGROUP_SPI2_MISO,
+        TEGRA_PINGROUP_SPI2_CS0_N,
+        TEGRA_PINGROUP_SPI2_SCK,
+        TEGRA_PINGROUP_SPI1_MOSI,
+        TEGRA_PINGROUP_SPI1_SCK,
+        TEGRA_PINGROUP_SPI1_CS0_N,
+        TEGRA_PINGROUP_SPI1_MISO,
+        TEGRA_PINGROUP_SPI2_CS1_N,
+        TEGRA_PINGROUP_SPI2_CS2_N,
+        TEGRA_PINGROUP_SDMMC3_CLK,
+        TEGRA_PINGROUP_SDMMC3_CMD,
+        TEGRA_PINGROUP_SDMMC3_DAT0,
+        TEGRA_PINGROUP_SDMMC3_DAT1,
+        TEGRA_PINGROUP_SDMMC3_DAT2,
+        TEGRA_PINGROUP_SDMMC3_DAT3,
+        TEGRA_PINGROUP_SDMMC3_DAT4,
+        TEGRA_PINGROUP_SDMMC3_DAT5,
+        TEGRA_PINGROUP_SDMMC3_DAT6,
+        TEGRA_PINGROUP_SDMMC3_DAT7,
+        TEGRA_PINGROUP_PEX_L0_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L0_RST_N,
+        TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_WAKE_N,
+        TEGRA_PINGROUP_PEX_L1_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L1_RST_N,
+        TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_L2_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L2_RST_N,
+        TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
+        TEGRA_PINGROUP_HDMI_CEC,
+        TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+        TEGRA_DRIVE_PINGROUP_AO1 = 0,
+        TEGRA_DRIVE_PINGROUP_AO2,
+        TEGRA_DRIVE_PINGROUP_AT1,
+        TEGRA_DRIVE_PINGROUP_AT2,
+        TEGRA_DRIVE_PINGROUP_AT3,
+        TEGRA_DRIVE_PINGROUP_AT4,
+        TEGRA_DRIVE_PINGROUP_AT5,
+        TEGRA_DRIVE_PINGROUP_CDEV1,
+        TEGRA_DRIVE_PINGROUP_CDEV2,
+        TEGRA_DRIVE_PINGROUP_CSUS,
+        TEGRA_DRIVE_PINGROUP_DAP1,
+        TEGRA_DRIVE_PINGROUP_DAP2,
+        TEGRA_DRIVE_PINGROUP_DAP3,
+        TEGRA_DRIVE_PINGROUP_DAP4,
+        TEGRA_DRIVE_PINGROUP_DBG,
+        TEGRA_DRIVE_PINGROUP_LCD1,
+        TEGRA_DRIVE_PINGROUP_LCD2,
+        TEGRA_DRIVE_PINGROUP_SDIO2,
+        TEGRA_DRIVE_PINGROUP_SDIO3,
+        TEGRA_DRIVE_PINGROUP_SPI,
+        TEGRA_DRIVE_PINGROUP_UAA,
+        TEGRA_DRIVE_PINGROUP_UAB,
+        TEGRA_DRIVE_PINGROUP_UART2,
+        TEGRA_DRIVE_PINGROUP_UART3,
+        TEGRA_DRIVE_PINGROUP_VI1,
+        TEGRA_DRIVE_PINGROUP_SDIO1,
+        TEGRA_DRIVE_PINGROUP_CRT,
+        TEGRA_DRIVE_PINGROUP_DDC,
+        TEGRA_DRIVE_PINGROUP_GMA,
+        TEGRA_DRIVE_PINGROUP_GMB,
+        TEGRA_DRIVE_PINGROUP_GMC,
+        TEGRA_DRIVE_PINGROUP_GMD,
+        TEGRA_DRIVE_PINGROUP_GME,
+        TEGRA_DRIVE_PINGROUP_GMF,
+        TEGRA_DRIVE_PINGROUP_GMG,
+        TEGRA_DRIVE_PINGROUP_GMH,
+        TEGRA_DRIVE_PINGROUP_OWR,
+        TEGRA_DRIVE_PINGROUP_UAD,
+        TEGRA_DRIVE_PINGROUP_GPV,
+        TEGRA_DRIVE_PINGROUP_DEV3,
+        TEGRA_DRIVE_PINGROUP_CEC,
+        TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
new file mode 100644
index 00000000000..f485d0bb072
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -0,0 +1,375 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_H
+#define __MACH_TEGRA_PINMUX_H
+
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#include "pinmux-t2.h"
+#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#include "pinmux-t3.h"
+#else
+#error "Undefined Tegra architecture"
+#endif
+
+#define TEGRA_MUX_LIST \
+        TEGRA_MUX(NONE) \
+        TEGRA_MUX(AHB_CLK) \
+        TEGRA_MUX(APB_CLK) \
+        TEGRA_MUX(AUDIO_SYNC) \
+        TEGRA_MUX(CRT) \
+        TEGRA_MUX(DAP1) \
+        TEGRA_MUX(DAP2) \
+        TEGRA_MUX(DAP3) \
+        TEGRA_MUX(DAP4) \
+        TEGRA_MUX(DAP5) \
+        TEGRA_MUX(DISPLAYA) \
+        TEGRA_MUX(DISPLAYB) \
+        TEGRA_MUX(EMC_TEST0_DLL) \
+        TEGRA_MUX(EMC_TEST1_DLL) \
+        TEGRA_MUX(GMI) \
+        TEGRA_MUX(GMI_INT) \
+        TEGRA_MUX(HDMI) \
+        TEGRA_MUX(I2C1) \
+        TEGRA_MUX(I2C2) \
+        TEGRA_MUX(I2C3) \
+        TEGRA_MUX(IDE) \
+        TEGRA_MUX(IRDA) \
+        TEGRA_MUX(KBC) \
+        TEGRA_MUX(MIO) \
+        TEGRA_MUX(MIPI_HS) \
+        TEGRA_MUX(NAND) \
+        TEGRA_MUX(OSC) \
+        TEGRA_MUX(OWR) \
+        TEGRA_MUX(PCIE) \
+        TEGRA_MUX(PLLA_OUT) \
+        TEGRA_MUX(PLLC_OUT1) \
+        TEGRA_MUX(PLLM_OUT1) \
+        TEGRA_MUX(PLLP_OUT2) \
+        TEGRA_MUX(PLLP_OUT3) \
+        TEGRA_MUX(PLLP_OUT4) \
+        TEGRA_MUX(PWM) \
+        TEGRA_MUX(PWR_INTR) \
+        TEGRA_MUX(PWR_ON) \
+        TEGRA_MUX(RTCK) \
+        TEGRA_MUX(SDIO1) \
+        TEGRA_MUX(SDIO2) \
+        TEGRA_MUX(SDIO3) \
+        TEGRA_MUX(SDIO4) \
+        TEGRA_MUX(SFLASH) \
+        TEGRA_MUX(SPDIF) \
+        TEGRA_MUX(SPI1) \
+        TEGRA_MUX(SPI2) \
+        TEGRA_MUX(SPI2_ALT) \
+        TEGRA_MUX(SPI3) \
+        TEGRA_MUX(SPI4) \
+        TEGRA_MUX(TRACE) \
+        TEGRA_MUX(TWC) \
+        TEGRA_MUX(UARTA) \
+        TEGRA_MUX(UARTB) \
+        TEGRA_MUX(UARTC) \
+        TEGRA_MUX(UARTD) \
+        TEGRA_MUX(UARTE) \
+        TEGRA_MUX(ULPI) \
+        TEGRA_MUX(VI) \
+        TEGRA_MUX(VI_SENSOR_CLK) \
+        TEGRA_MUX(XIO) \
+        /* End of Tegra2 MUX selectors */ \
+        TEGRA_MUX(BLINK) \
+        TEGRA_MUX(CEC) \
+        TEGRA_MUX(CLK12) \
+        TEGRA_MUX(DAP) \
+        TEGRA_MUX(DAPSDMMC2) \
+        TEGRA_MUX(DDR) \
+        TEGRA_MUX(DEV3) \
+        TEGRA_MUX(DTV) \
+        TEGRA_MUX(VI_ALT1) \
+        TEGRA_MUX(VI_ALT2) \
+        TEGRA_MUX(VI_ALT3) \
+        TEGRA_MUX(EMC_DLL) \
+        TEGRA_MUX(EXTPERIPH1) \
+        TEGRA_MUX(EXTPERIPH2) \
+        TEGRA_MUX(EXTPERIPH3) \
+        TEGRA_MUX(GMI_ALT) \
+        TEGRA_MUX(HDA) \
+        TEGRA_MUX(HSI) \
+        TEGRA_MUX(I2C4) \
+        TEGRA_MUX(I2C5) \
+        TEGRA_MUX(I2CPWR) \
+        TEGRA_MUX(I2S0) \
+        TEGRA_MUX(I2S1) \
+        TEGRA_MUX(I2S2) \
+        TEGRA_MUX(I2S3) \
+        TEGRA_MUX(I2S4) \
+        TEGRA_MUX(NAND_ALT) \
+        TEGRA_MUX(POPSDIO4) \
+        TEGRA_MUX(POPSDMMC4) \
+        TEGRA_MUX(PWM0) \
+        TEGRA_MUX(PWM1) \
+        TEGRA_MUX(PWM2) \
+        TEGRA_MUX(PWM3) \
+        TEGRA_MUX(SATA) \
+        TEGRA_MUX(SPI5) \
+        TEGRA_MUX(SPI6) \
+        TEGRA_MUX(SYSCLK) \
+        TEGRA_MUX(VGP1) \
+        TEGRA_MUX(VGP2) \
+        TEGRA_MUX(VGP3) \
+        TEGRA_MUX(VGP4) \
+        TEGRA_MUX(VGP5) \
+        TEGRA_MUX(VGP6) \
+        /* End of Tegra3 MUX selectors */
+
+enum tegra_mux_func {
+#define TEGRA_MUX(mux) TEGRA_MUX_##mux,
+        TEGRA_MUX_LIST
+#undef  TEGRA_MUX
+        TEGRA_MUX_SAFE,         /* "Safe" default mux selector */
+        TEGRA_MAX_MUX,          /* Number of mux selectors */
+        TEGRA_MUX_TEGRA2_LAST = TEGRA_MUX_XIO,
+        TEGRA_MUX_TEGRA3_LAST = TEGRA_MUX_VGP6,
+
+        /* Mux selector aliases */
+        TEGRA_MUX_I2C    = TEGRA_MUX_I2C1,
+        TEGRA_MUX_SDMMC1 = TEGRA_MUX_SDIO1,
+        TEGRA_MUX_SDMMC2 = TEGRA_MUX_SDIO2,
+        TEGRA_MUX_SDMMC3 = TEGRA_MUX_SDIO3,
+        TEGRA_MUX_SDMMC4 = TEGRA_MUX_SDIO4,
+
+        /* Special mux selector values */
+        TEGRA_MUX_INVALID = 0x4000,
+        TEGRA_MUX_RSVD  = 0x8000,
+        TEGRA_MUX_RSVD0 = TEGRA_MUX_RSVD,
+        TEGRA_MUX_RSVD1 = 0x8001,
+        TEGRA_MUX_RSVD2 = 0x8002,
+        TEGRA_MUX_RSVD3 = 0x8003,
+        TEGRA_MUX_RSVD4 = 0x8004,
+};
+
+enum tegra_pullupdown {
+        TEGRA_PUPD_NORMAL = 0,
+        TEGRA_PUPD_PULL_DOWN,
+        TEGRA_PUPD_PULL_UP,
+};
+
+enum tegra_tristate {
+        TEGRA_TRI_NORMAL = 0,
+        TEGRA_TRI_TRISTATE = 1,
+};
+
+enum tegra_pin_io {
+        TEGRA_PIN_OUTPUT = 0,
+        TEGRA_PIN_INPUT = 1,
+};
+
+enum tegra_pin_lock {
+        TEGRA_PIN_LOCK_DEFAULT = 0,
+        TEGRA_PIN_LOCK_DISABLE,
+        TEGRA_PIN_LOCK_ENABLE,
+};
+
+enum tegra_pin_od {
+        TEGRA_PIN_OD_DEFAULT = 0,
+        TEGRA_PIN_OD_DISABLE,
+        TEGRA_PIN_OD_ENABLE,
+};
+
+enum tegra_pin_ioreset {
+        TEGRA_PIN_IO_RESET_DEFAULT = 0,
+        TEGRA_PIN_IO_RESET_DISABLE,
+        TEGRA_PIN_IO_RESET_ENABLE,
+};
+
+enum tegra_vddio {
+        TEGRA_VDDIO_BB = 0,
+        TEGRA_VDDIO_LCD,
+        TEGRA_VDDIO_VI,
+        TEGRA_VDDIO_UART,
+        TEGRA_VDDIO_DDR,
+        TEGRA_VDDIO_NAND,
+        TEGRA_VDDIO_SYS,
+        TEGRA_VDDIO_AUDIO,
+        TEGRA_VDDIO_SD,
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        TEGRA_VDDIO_CAM,
+        TEGRA_VDDIO_GMI,
+        TEGRA_VDDIO_PEXCTL,
+        TEGRA_VDDIO_SDMMC1,
+        TEGRA_VDDIO_SDMMC3,
+        TEGRA_VDDIO_SDMMC4,
+#endif
+};
+
+struct tegra_pingroup_config {
+        enum tegra_pingroup     pingroup;
+        enum tegra_mux_func     func;
+        enum tegra_pullupdown   pupd;
+        enum tegra_tristate     tristate;
+        enum tegra_pin_io       io;
+        enum tegra_pin_lock     lock;
+        enum tegra_pin_od       od;
+        enum tegra_pin_ioreset  ioreset;
+};
+
+enum tegra_slew {
+        TEGRA_SLEW_FASTEST = 0,
+        TEGRA_SLEW_FAST,
+        TEGRA_SLEW_SLOW,
+        TEGRA_SLEW_SLOWEST,
+        TEGRA_MAX_SLEW,
+};
+
+enum tegra_pull_strength {
+        TEGRA_PULL_0 = 0,
+        TEGRA_PULL_1,
+        TEGRA_PULL_2,
+        TEGRA_PULL_3,
+        TEGRA_PULL_4,
+        TEGRA_PULL_5,
+        TEGRA_PULL_6,
+        TEGRA_PULL_7,
+        TEGRA_PULL_8,
+        TEGRA_PULL_9,
+        TEGRA_PULL_10,
+        TEGRA_PULL_11,
+        TEGRA_PULL_12,
+        TEGRA_PULL_13,
+        TEGRA_PULL_14,
+        TEGRA_PULL_15,
+        TEGRA_PULL_16,
+        TEGRA_PULL_17,
+        TEGRA_PULL_18,
+        TEGRA_PULL_19,
+        TEGRA_PULL_20,
+        TEGRA_PULL_21,
+        TEGRA_PULL_22,
+        TEGRA_PULL_23,
+        TEGRA_PULL_24,
+        TEGRA_PULL_25,
+        TEGRA_PULL_26,
+        TEGRA_PULL_27,
+        TEGRA_PULL_28,
+        TEGRA_PULL_29,
+        TEGRA_PULL_30,
+        TEGRA_PULL_31,
+        TEGRA_PULL_32,
+        TEGRA_PULL_33,
+        TEGRA_PULL_34,
+        TEGRA_PULL_35,
+        TEGRA_PULL_36,
+        TEGRA_PULL_37,
+        TEGRA_PULL_38,
+        TEGRA_PULL_39,
+        TEGRA_PULL_40,
+        TEGRA_PULL_41,
+        TEGRA_PULL_42,
+        TEGRA_PULL_43,
+        TEGRA_PULL_44,
+        TEGRA_PULL_45,
+        TEGRA_PULL_46,
+        TEGRA_MAX_PULL,
+};
+
+enum tegra_drive {
+        TEGRA_DRIVE_DIV_8 = 0,
+        TEGRA_DRIVE_DIV_4,
+        TEGRA_DRIVE_DIV_2,
+        TEGRA_DRIVE_DIV_1,
+        TEGRA_MAX_DRIVE,
+};
+
+enum tegra_hsm {
+        TEGRA_HSM_DISABLE = 0,
+        TEGRA_HSM_ENABLE,
+};
+
+enum tegra_schmitt {
+        TEGRA_SCHMITT_DISABLE = 0,
+        TEGRA_SCHMITT_ENABLE,
+};
+
+struct tegra_drive_pingroup_config {
+        enum tegra_drive_pingroup pingroup;
+        enum tegra_hsm hsm;
+        enum tegra_schmitt schmitt;
+        enum tegra_drive drive;
+        enum tegra_pull_strength pull_down;
+        enum tegra_pull_strength pull_up;
+        enum tegra_slew slew_rising;
+        enum tegra_slew slew_falling;
+};
+
+struct tegra_drive_pingroup_desc {
+        const char *name;
+        s16 reg;
+        u8 drvup_offset;
+        u16 drvup_mask;
+        u8 drvdown_offset;
+        u16 drvdown_mask;
+        u8 slewrise_offset;
+        u16 slewrise_mask;
+        u8 slewfall_offset;
+        u16 slewfall_mask;
+};
+
+struct tegra_pingroup_desc {
+        const char *name;
+        int funcs[4];
+        int func_safe;
+        int vddio;
+        s16 tri_reg;    /* offset into the TRISTATE_REG_* register bank */
+        s16 mux_reg;    /* offset into the PIN_MUX_CTL_* register bank */
+        s16 pupd_reg;   /* offset into the PULL_UPDOWN_REG_* register bank */
+        s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
+        s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
+        s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
+        s8 lock_bit;    /* offser of the LOCK bit into mux register bit */
+        s8 od_bit;      /* offset of the OD bit into mux register bit */
+        s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
+        s8 io_default;
+        int gpionr;
+};
+
+extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
+extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
+extern const int gpio_to_pingroup[];
+
+int tegra_pinmux_get_func(enum tegra_pingroup pg);
+int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
+        enum tegra_tristate tristate);
+int tegra_pinmux_set_io(enum tegra_pingroup pg,
+        enum tegra_pin_io input);
+int tegra_pinmux_get_pingroup(int gpio_nr);
+int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
+        enum tegra_pullupdown pupd);
+
+void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
+        int len);
+
+void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
+        int len);
+void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
+        int len);
+void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
+        int len);
+void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
+        int len, enum tegra_tristate tristate);
+void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
+        int len, enum tegra_pullupdown pupd);
+
+void __init tegra_init_pinmux(void);
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
new file mode 100644
index 00000000000..b48a9288707
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -0,0 +1,35 @@
+/*
+ * include/asm-arm/arch-tegra/include/mach/sdhci.h
+ *
+ * Copyright (C) 2009 Palm, Inc.
+ * Author: Yvonne Yip <y@palm.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
+#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
+
+#include <linux/mmc/host.h>
+#include <asm/mach/mmc.h>
+
+struct tegra_sdhci_platform_data {
+        int cd_gpio;
+        int wp_gpio;
+        int power_gpio;
+        int is_8bit;
+        int pm_flags;
+        int pm_caps;
+        unsigned int max_clk_limit;
+        unsigned int tap_delay;
+        struct mmc_platform_data mmc_data;
+};
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h
new file mode 100644
index 00000000000..dad403a9cf0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/smmu.h
@@ -0,0 +1,63 @@
+/*
+ * IOMMU API for SMMU in Tegra30
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef MACH_SMMU_H
+#define MACH_SMMU_H
+
+enum smmu_hwgrp {
+        HWGRP_AFI,
+        HWGRP_AVPC,
+        HWGRP_DC,
+        HWGRP_DCB,
+        HWGRP_EPP,
+        HWGRP_G2,
+        HWGRP_HC,
+        HWGRP_HDA,
+        HWGRP_ISP,
+        HWGRP_MPE,
+        HWGRP_NV,
+        HWGRP_NV2,
+        HWGRP_PPCS,
+        HWGRP_SATA,
+        HWGRP_VDE,
+        HWGRP_VI,
+
+        HWGRP_COUNT,
+
+        HWGRP_END = ~0,
+};
+
+#define HWG_AFI         (1 << HWGRP_AFI)
+#define HWG_AVPC        (1 << HWGRP_AVPC)
+#define HWG_DC          (1 << HWGRP_DC)
+#define HWG_DCB         (1 << HWGRP_DCB)
+#define HWG_EPP         (1 << HWGRP_EPP)
+#define HWG_G2          (1 << HWGRP_G2)
+#define HWG_HC          (1 << HWGRP_HC)
+#define HWG_HDA         (1 << HWGRP_HDA)
+#define HWG_ISP         (1 << HWGRP_ISP)
+#define HWG_MPE         (1 << HWGRP_MPE)
+#define HWG_NV          (1 << HWGRP_NV)
+#define HWG_NV2         (1 << HWGRP_NV2)
+#define HWG_PPCS        (1 << HWGRP_PPCS)
+#define HWG_SATA        (1 << HWGRP_SATA)
+#define HWG_VDE         (1 << HWGRP_VDE)
+#define HWG_VI          (1 << HWGRP_VI)
+
+#endif  /* MACH_SMMU_H */
diff --git a/arch/arm/mach-tegra/include/mach/spdif.h b/arch/arm/mach-tegra/include/mach/spdif.h
new file mode 100644
index 00000000000..96103fae91b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/spdif.h
@@ -0,0 +1,392 @@
+/*
+ * arch/arm/mach-tegra/include/mach/spdif.h
+ *
+ *
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+
+#ifndef __ARCH_ARM_MACH_TEGRA_SPDIF_H
+#define __ARCH_ARM_MACH_TEGRA_SPDIF_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+
+/* Offsets from TEGRA_SPDIF_BASE */
+
+#define SPDIF_CTRL_0                    0x0
+#define SPDIF_STATUS_0                  0x4
+#define SPDIF_STROBE_CTRL_0             0x8
+#define SPDIF_DATA_FIFO_CSR_0           0x0C
+#define SPDIF_DATA_OUT_0                0x40
+#define SPDIF_DATA_IN_0                 0x80
+#define SPDIF_CH_STA_RX_A_0             0x100
+#define SPDIF_CH_STA_RX_B_0             0x104
+#define SPDIF_CH_STA_RX_C_0             0x108
+#define SPDIF_CH_STA_RX_D_0             0x10C
+#define SPDIF_CH_STA_RX_E_0             0x110
+#define SPDIF_CH_STA_RX_F_0             0x114
+#define SPDIF_CH_STA_TX_A_0             0x140
+#define SPDIF_CH_STA_TX_B_0             0x144
+#define SPDIF_CH_STA_TX_C_0             0x148
+#define SPDIF_CH_STA_TX_D_0             0x14C
+#define SPDIF_CH_STA_TX_E_0             0x150
+#define SPDIF_CH_STA_TX_F_0             0x154
+#define SPDIF_USR_STA_RX_A_0            0x180
+#define SPDIF_USR_DAT_TX_A_0            0x1C0
+
+/*
+ * Register SPDIF_CTRL_0
+ */
+
+/*
+ * 1=start capturing from left channel,0=start
+ * capturing from right channel.
+ */
+#define SPDIF_CTRL_0_CAP_LC                     (1<<30)
+
+/* SPDIF receiver(RX):  1=enable, 0=disable. */
+#define SPDIF_CTRL_0_RX_EN                      (1<<29)
+
+/* SPDIF Transmitter(TX):       1=enable, 0=disable. */
+#define SPDIF_CTRL_0_TX_EN                      (1<<28)
+
+/* Transmit Channel status:     1=enable, 0=disable. */
+#define SPDIF_CTRL_0_TC_EN                      (1<<27)
+
+/* Transmit user Data:          1=enable, 0=disable. */
+#define SPDIF_CTRL_0_TU_EN                      (1<<26)
+
+/* Interrupt on transmit error:  1=enable, 0=disable. */
+#define SPDIF_CTRL_0_IE_TXE                     (1<<25)
+
+/* Interrupt on receive error:   1=enable, 0=disable. */
+#define SPDIF_CTRL_0_IE_RXE                     (1<<24)
+
+/* Interrupt on invalid preamble:       1=enable, 0=disable. */
+#define SPDIF_CTRL_0_IE_P                       (1<<23)
+
+/* Interrupt on "B" preamble:      1=enable, 0=disable. */
+#define SPDIF_CTRL_0_IE_B                       (1<<22)
+
+/*
+ * Interrupt when block of channel status received:
+ * 1=enable, 0=disable.
+ */
+#define SPDIF_CTRL_0_IE_C                       (1<<21)
+
+/*
+ * Interrupt when a valid information unit (IU) recieve:
+ * 1=enable, 0=disable.
+ */
+#define SPDIF_CTRL_0_IE_U                       (1<<20)
+
+/*
+ * Interrupt when RX user FIFO attn. level is reached:
+ * 1=enable, 0=disable.
+ */
+#define SPDIF_CTRL_0_QE_RU                      (1<<19)
+
+/*
+ * Interrupt when TX user FIFO attn. level is reached:
+ * 1=enable, 0=disable.
+ */
+#define SPDIF_CTRL_0_QE_TU                      (1<<18)
+
+/*
+ * Interrupt when RX data FIFO attn. level is reached:
+ * 1=enable, 0=disable.
+ */
+#define SPDIF_CTRL_0_QE_RX                      (1<<17)
+
+/*
+ * Interrupt when TX data FIFO attn. level is reached:
+ * 1=enable, 0=disable.
+ */
+#define SPDIF_CTRL_0_QE_TX                      (1<<16)
+
+/* Loopback test mode:   1=enable internal loopback, 0=Normal mode. */
+#define SPDIF_CTRL_0_LBK_EN                     (1<<15)
+
+/*
+ * Pack data mode:
+ * 1=Packeted left/right channel data into a single word,
+ * 0=Single data (16 bit needs to be  padded to match the
+ * interface data bit size)
+ */
+#define SPDIF_CTRL_0_PACK                (1<<14)
+
+/*
+ * 00=16bit data
+ * 01=20bit data
+ * 10=24bit data
+ * 11=raw data
+ */
+#define SPDIF_BIT_MODE_MODE16BIT        (0)
+#define SPDIF_BIT_MODE_MODE20BIT        (1)
+#define SPDIF_BIT_MODE_MODE24BIT        (2)
+#define SPDIF_BIT_MODE_MODERAW          (3)
+#define SPDIF_CTRL_0_BIT_MODE_SHIFT     (12)
+
+#define SPDIF_CTRL_0_BIT_MODE_MASK              \
+                ((0x3) << SPDIF_CTRL_0_BIT_MODE_SHIFT)
+#define SPDIF_CTRL_0_BIT_MODE_MODE16BIT         \
+        (SPDIF_BIT_MODE_MODE16BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
+#define SPDIF_CTRL_0_BIT_MODE_MODE20BIT         \
+        (SPDIF_BIT_MODE_MODE20BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
+#define SPDIF_CTRL_0_BIT_MODE_MODE24BIT         \
+        (SPDIF_BIT_MODE_MODE24BIT << SPDIF_CTRL_0_BIT_MODE_SHIFT)
+#define SPDIF_CTRL_0_BIT_MODE_MODERAW           \
+                (SPDIF_BIT_MODE_MODERAW << SPDIF_CTRL_0_BIT_MODE_SHIFT)
+
+
+/*
+ *  SPDIF Status Register
+ * -------------------------
+ * Note:  IS_P, IS_B, IS_C, and IS_U are sticky bits.
+ * Software must write a 1 to the corresponding bit location
+ * to clear the status.
+ */
+
+/* Register SPDIF_STATUS_0 */
+
+/*
+ * Receiver(RX) shifter is busy receiving data.  1=busy, 0=not busy.
+ * This bit is asserted when the receiver first locked onto the
+ * preamble of the data stream after RX_EN is asserted.  This bit is
+ * deasserted when either,
+ * (a)  the end of a frame is reached after RX_EN is deeasserted, or
+ * (b)  the SPDIF data stream becomes inactive.
+ */
+#define SPDIF_STATUS_0_RX_BSY                   (1<<29)
+
+
+/*
+ * Transmitter(TX) shifter is busy transmitting data.
+ * 1=busy, 0=not busy.
+ * This bit is asserted when TX_EN is asserted.
+ * This bit is deasserted when the end of a frame is reached after
+ * TX_EN is deasserted.
+ */
+#define SPDIF_STATUS_0_TX_BSY                   (1<<28)
+
+/*
+ * TX is busy shifting out channel status.  1=busy, 0=not busy.
+ * This bit is asserted when both TX_EN and TC_EN are asserted and
+ * data from CH_STA_TX_A register is loaded into the internal shifter.
+ * This bit is deasserted when either,
+ * (a) the end of a frame is reached after TX_EN is deasserted, or
+ * (b) CH_STA_TX_F register is loaded into the internal shifter.
+ */
+#define SPDIF_STATUS_0_TC_BSY                   (1<<27)
+
+/*
+ * TX User data FIFO busy.  1=busy, 0=not busy.
+ * This bit is asserted when TX_EN and TXU_EN are asserted and
+ * there's data in the TX user FIFO.  This bit is deassert when either,
+ * (a) the end of a frame is reached after TX_EN is deasserted, or
+ * (b) there's no data left in the TX user FIFO.
+ */
+#define SPDIF_STATUS_0_TU_BSY                   (1<<26)
+
+/* Tx FIFO Underrun error status:       1=error, 0=no error */
+#define SPDIF_STATUS_0_TX_ERR                   (1<<25)
+
+/* Rx FIFO Overrun error status:         1=error, 0=no error */
+#define SPDIF_STATUS_0_RX_ERR                   (1<<24)
+
+/* Preamble status:     1=bad/missing preamble, 0=Preamble ok */
+#define SPDIF_STATUS_0_IS_P                     (1<<23)
+
+/* B-preamble detection status: 0=not detected, 1=B-preamble detected */
+#define SPDIF_STATUS_0_IS_B                     (1<<22)
+
+/*
+ * RX channel block data receive status:
+ * 1=received entire block of channel status,
+ * 0=entire block not recieved yet.
+ */
+#define SPDIF_STATUS_0_IS_C                     (1<<21)
+
+/* RX User Data Valid flag:  1=valid IU detected, 0 = no IU detected. */
+#define SPDIF_STATUS_0_IS_U                     (1<<20)
+
+/*
+ * RX User FIFO Status:
+ * 1=attention level reached, 0=attention level not reached.
+ */
+#define SPDIF_STATUS_0_QS_RU                    (1<<19)
+
+/*
+ * TX User FIFO Status:
+ * 1=attention level reached, 0=attention level not reached.
+ */
+#define SPDIF_STATUS_0_QS_TU                    (1<<18)
+
+/*
+ * RX Data FIFO Status:
+ * 1=attention level reached, 0=attention level not reached.
+ */
+#define SPDIF_STATUS_0_QS_RX                    (1<<17)
+
+/*
+ * TX Data FIFO Status:
+ * 1=attention level reached, 0=attention level not reached.
+ */
+#define SPDIF_STATUS_0_QS_TX                    (1<<16)
+
+
+/* SPDIF FIFO Configuration and Status Register */
+
+/* Register SPDIF_DATA_FIFO_CSR_0 */
+
+#define SPDIF_FIFO_ATN_LVL_ONE_SLOT             0
+#define SPDIF_FIFO_ATN_LVL_FOUR_SLOTS           1
+#define SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS          2
+#define SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS         3
+
+
+/* Clear Receiver User FIFO (RX USR.FIFO) */
+#define SPDIF_DATA_FIFO_CSR_0_RU_CLR            (1<<31)
+
+/*
+ * RX USR.FIFO Attention Level:
+ * 00=1-slot-full, 01=2-slots-full, 10=3-slots-full, 11=4-slots-full.
+ */
+
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1            (0)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2            (1)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3            (2)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4            (3)
+
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT          (29)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_MASK   \
+                (0x3 << SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1_WORD_FULL          \
+                (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU1 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2_WORD_FULL          \
+                (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU2 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3_WORD_FULL          \
+                (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU3 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
+#define SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4_WORD_FULL          \
+                (SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_RU4 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_RU_ATN_LVL_SHIF)
+
+/* Number of RX USR.FIFO levels with valid data. */
+#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT          (24)
+#define SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_MASK                   \
+                (0x1f << SPDIF_DATA_FIFO_CSR_0_FULL_COUNT_SHIFT)
+
+/* Clear Transmitter User FIFO (TX USR.FIFO) */
+#define SPDIF_DATA_FIFO_CSR_0_TU_CLR                     (1<<23)
+
+/*
+ * TxUSR.FIFO Attention Level:
+ * 11=4-slots-empty, 10=3-slots-empty, 01=2-slots-empty, 00=1-slot-empty.
+ */
+
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1            (0)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2            (1)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3            (2)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4            (3)
+
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT          (21)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_MASK                   \
+                (0x3 << SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1_WORD_EMPTY         \
+                (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU1 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2_WORD_EMPTY         \
+                (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU2 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3_WORD_EMPTY         \
+                (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU3 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4_WORD_EMPTY         \
+                (SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_TU4 <<        \
+                        SPDIF_DATA_FIFO_CSR_0_TU_ATN_LVL_SHIFT)
+
+/* Number of Tx USR.FIFO levels that could be filled. */
+#define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT              (16)
+#define SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_FIELD              \
+                ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TU_EMPTY_COUNT_SHIFT)
+
+/* Clear Receiver Data FIFO (RX DATA.FIFO). */
+#define SPDIF_DATA_FIFO_CSR_0_RX_CLR                    (1<<15)
+
+/*
+ * Rx FIFO Attention Level:
+ * 11=12-slots-full, 10=8-slots-full, 01=4-slots-full, 00=1-slot-full.
+ */
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT          (13)
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_MASK                   \
+                (0x3 << SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX1_WORD_FULL          \
+        (SPDIF_FIFO_ATN_LVL_ONE_SLOT <<                         \
+                SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX4_WORD_FULL          \
+                (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS <<               \
+                        SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX8_WORD_FULL          \
+                (SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS <<              \
+                        SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_RX12_WORD_FULL         \
+                (SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS <<             \
+                        SPDIF_DATA_FIFO_CSR_0_RX_ATN_LVL_SHIFT)
+
+
+/* Number of RX DATA.FIFO levels with valid data */
+#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT     (8)
+#define SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_FIELD     \
+        ((0x1f) << SPDIF_DATA_FIFO_CSR_0_RX_DATA_FIFO_FULL_COUNT_SHIFT)
+
+/* Clear Transmitter Data FIFO (TX DATA.FIFO) */
+#define SPDIF_DATA_FIFO_CSR_0_TX_CLR                    (1<<7)
+
+/*
+ * Tx FIFO Attention Level:
+ * 11=12-slots-empty, 10=8-slots-empty, 01=4-slots-empty, 00=1-slot-empty
+ */
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT          (5)
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_MASK                   \
+                (0x3 << SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX1_WORD_FULL          \
+                (SPDIF_FIFO_ATN_LVL_ONE_SLOT <<                 \
+                        SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX4_WORD_FULL          \
+                (SPDIF_FIFO_ATN_LVL_FOUR_SLOTS <<               \
+                        SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX8_WORD_FULL          \
+                (SPDIF_FIFO_ATN_LVL_EIGHT_SLOTS <<              \
+                        SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
+#define SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_TX12_WORD_FULL         \
+                (SPDIF_FIFO_ATN_LVL_TWELVE_SLOTS <<             \
+                        SPDIF_DATA_FIFO_CSR_0_TX_ATN_LVL_SHIFT)
+
+
+/* Number of Tx DATA.FIFO levels that could be filled. */
+#define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT              (0)
+#define SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_MASK               \
+                ((0x1f) << SPDIF_DATA_FIFO_CSR_0_TD_EMPTY_COUNT_SHIFT)
+
+
+#endif /* __ARCH_ARM_MACH_TEGRA_SPDIF_H */
diff --git a/arch/arm/mach-tegra/include/mach/spi.h b/arch/arm/mach-tegra/include/mach/spi.h
new file mode 100644
index 00000000000..171e4007b4b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/spi.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-tegra/include/mach/spi.h
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_SPI_H
+#define __MACH_TEGRA_SPI_H
+
+#include <linux/types.h>
+#include <linux/spi/spi.h>
+
+typedef int     (*callback)(void *client_data);
+
+/**
+ * register_spi_slave_callback - registers notification callback provided by
+ * the client.
+ * This callback indicate that the controller is all set to receive/transfer
+ * data.
+ * @spi: struct spi_device - refer to linux/spi/spi.h
+ * @func: Callback function
+ * @client_data: Data to be passed in callback
+ * Context: can not sleep
+ */
+int spi_tegra_register_callback(struct spi_device *spi, callback func,
+        void *client_data);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
new file mode 100644
index 00000000000..7bc605e5dc8
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-tegra/include/mach/system.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_SYSTEM_H
+#define __MACH_TEGRA_SYSTEM_H
+
+#include <mach/iomap.h>
+
+extern void (*arch_reset)(char mode, const char *cmd);
+
+static inline void arch_idle(void)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra-bb-power.h b/arch/arm/mach-tegra/include/mach/tegra-bb-power.h
new file mode 100644
index 00000000000..e0b7e3de326
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra-bb-power.h
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra-bb-power.h
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define GPIO_INVALID UINT_MAX
+
+union tegra_bb_gpio_id {
+        struct {
+                int mdm_reset;
+                int mdm_on;
+                int ap2mdm_ack;
+                int mdm2ap_ack;
+                int ap2mdm_ack2;
+                int mdm2ap_ack2;
+                int rsvd1;
+                int rsvd2;
+        } generic;
+        struct {
+                int bb_rst;
+                int bb_on;
+                int ipc_bb_wake;
+                int ipc_ap_wake;
+                int ipc_hsic_active;
+                int ipc_hsic_sus_req;
+                int rsvd1;
+                int rsvd2;
+        } xmm;
+        struct {
+                int pwr_status;
+                int pwr_on;
+                int uart_awr;
+                int uart_cwr;
+                int usb_awr;
+                int usb_cwr;
+                int service;
+                int resout2;
+        } m7400;
+};
+
+typedef struct platform_device* (*ehci_register_cb)(void);
+typedef void (*ehci_unregister_cb)(struct platform_device *);
+
+struct tegra_bb_pdata {
+        union tegra_bb_gpio_id *id;
+        struct platform_device *device;
+        ehci_register_cb ehci_register;
+        ehci_unregister_cb ehci_unregister;
+        int bb_id;
+};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h
new file mode 100644
index 00000000000..a47ef1982e4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_aic326x_pdata.h
+ *
+ * Copyright 2011 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MACH_TEGRA_TLVAIC326X_H
+#define __MACH_TEGRA_TLVAIC326X_H
+
+#define HIFI_CODEC              0
+#define BASEBAND                1
+#define BT_SCO                  2
+#define NUM_I2S_DEVICES         3
+
+struct baseband_config {
+        int rate;
+        int channels;
+};
+
+struct tegra_aic326x_platform_data {
+        int gpio_spkr_en;
+        int gpio_hp_det;
+        int gpio_hp_mute;
+        int gpio_int_mic_en;
+        int gpio_ext_mic_en;
+        int audio_port_id[NUM_I2S_DEVICES];
+        struct baseband_config baseband_param;
+};
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h
new file mode 100644
index 00000000000..34eb2f4fc37
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_asoc_pdata.h
+ *
+ * Copyright 2012 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define HIFI_CODEC              0
+#define BASEBAND                1
+#define BT_SCO                  2
+#define NUM_I2S_DEVICES         3
+
+struct baseband_config {
+        int rate;
+        int channels;
+};
+
+struct tegra_asoc_platform_data {
+        int gpio_spkr_en;
+        int gpio_hp_det;
+        int gpio_hp_mute;
+        int gpio_int_mic_en;
+        int gpio_ext_mic_en;
+        unsigned int debounce_time_hp;
+        int audio_port_id[NUM_I2S_DEVICES];
+        struct baseband_config baseband_param;
+};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_dc_ext.h b/arch/arm/mach-tegra/include/mach/tegra_dc_ext.h
new file mode 100644
index 00000000000..521039283d8
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_dc_ext.h
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_dc_ext.h
+ *
+ * Copyright (C) 2011, NVIDIA Corporation
+ *
+ * Author: Robert Morell <rmorell@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __MACH_TEGRA_DC_EXT_H
+#define __MACH_TEGRA_DC_EXT_H
+
+#include <linux/nvhost.h>
+
+struct tegra_dc_ext;
+
+#ifdef CONFIG_TEGRA_DC_EXTENSIONS
+int __init tegra_dc_ext_module_init(void);
+void __exit tegra_dc_ext_module_exit(void);
+
+struct tegra_dc_ext *tegra_dc_ext_register(struct nvhost_device *ndev,
+                                           struct tegra_dc *dc);
+void tegra_dc_ext_unregister(struct tegra_dc_ext *dc_ext);
+
+/* called by display controller on enable/disable */
+void tegra_dc_ext_enable(struct tegra_dc_ext *dc_ext);
+void tegra_dc_ext_disable(struct tegra_dc_ext *dc_ext);
+
+int tegra_dc_ext_process_hotplug(int output);
+
+#else /* CONFIG_TEGRA_DC_EXTENSIONS */
+
+static inline
+int tegra_dc_ext_module_init(void)
+{
+        return 0;
+}
+static inline
+void tegra_dc_ext_module_exit(void)
+{
+}
+
+static inline
+struct tegra_dc_ext *tegra_dc_ext_register(struct nvhost_device *ndev,
+                                           struct tegra_dc *dc)
+{
+        return NULL;
+}
+static inline
+void tegra_dc_ext_unregister(struct tegra_dc_ext *dc_ext)
+{
+}
+static inline
+void tegra_dc_ext_enable(struct tegra_dc_ext *dc_ext)
+{
+}
+static inline
+void tegra_dc_ext_disable(struct tegra_dc_ext *dc_ext)
+{
+}
+static inline
+int tegra_dc_ext_process_hotplug(int output)
+{
+        return 0;
+}
+#endif /* CONFIG_TEGRA_DC_EXTENSIONS */
+
+#endif /* __MACH_TEGRA_DC_EXT_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra_fb.h b/arch/arm/mach-tegra/include/mach/tegra_fb.h
new file mode 100644
index 00000000000..84ae8869b24
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fb.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_fb.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* Platform data structure to be passed to the driver */
+struct tegra_fb_lcd_data {
+        int     fb_xres;
+        int     fb_yres;
+        /* Resolution of the output to the LCD.  If different from the
+           framebuffer resolution, the Tegra display block will scale it */
+        int     lcd_xres;
+        int     lcd_yres;
+        int     bits_per_pixel;
+};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h b/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h
new file mode 100644
index 00000000000..4d1a0b54f2a
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h
@@ -0,0 +1,30 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/tegra_fiq_debugger.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_FIQ_DEBUGGER_H
+#define __MACH_TEGRA_FIQ_DEBUGGER_H
+
+#ifdef CONFIG_TEGRA_FIQ_DEBUGGER
+void tegra_serial_debug_init(unsigned int base, int irq,
+        struct clk *clk, int signal_irq, int wakeup_irq);
+#else
+static inline void tegra_serial_debug_init(unsigned int base, int irq,
+        struct clk *clk, int signal_irq, int wakeup_irq)
+{
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_fuse.h b/arch/arm/mach-tegra/include/mach/tegra_fuse.h
new file mode 100644
index 00000000000..d264745c70c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fuse.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_fuse.h
+ *
+ * Tegra Public Fuse header file
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_PUBLIC_FUSE_H_
+#define _MACH_TEGRA_PUBLIC_FUSE_H_
+
+int tegra_fuse_get_revision(u32 *rev);
+int tegra_fuse_get_tsensor_calibration_data(u32 *calib);
+int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits);
+
+#endif /* _MACH_TEGRA_PUBLIC_FUSE_H_*/
+
diff --git a/arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h
new file mode 100644
index 00000000000..eb59cf0962b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_max98088_pdata.h
+ *
+ * Copyright 2011 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define HIFI_CODEC              0
+#define BASEBAND                1
+#define BT_SCO                  2
+#define NUM_I2S_DEVICES         3
+
+struct baseband_config {
+        int rate;
+        int channels;
+};
+
+struct tegra_max98088_platform_data {
+        int gpio_spkr_en;
+        int gpio_hp_det;
+        int gpio_hp_mute;
+        int gpio_int_mic_en;
+        int gpio_ext_mic_en;
+        int audio_port_id[NUM_I2S_DEVICES];
+        struct baseband_config baseband_param;
+};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h b/arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h
new file mode 100644
index 00000000000..4ab8433dbbf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h
@@ -0,0 +1,107 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_odm_fuses.h
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_ODM_FUSES_H
+#define __MACH_TEGRA_ODM_FUSES_H
+
+#define SBK_DEVKEY_STATUS_SZ    sizeof(u32)
+
+/*
+ * fuse io parameters: params with sizes less than a byte are
+ * explicitly mentioned
+ */
+enum fuse_io_param {
+        DEVKEY,
+        JTAG_DIS, /* 1 bit long */
+        /*
+         * Programming the odm production fuse at the same
+         * time as the sbk or dev_key is not allowed as it is not possible to
+         * verify that the sbk or dev_key were programmed correctly.
+         */
+        ODM_PROD_MODE, /* 1 bit long */
+        SEC_BOOT_DEV_CFG,
+        SEC_BOOT_DEV_SEL, /* 3 bits long */
+        SBK,
+        SW_RSVD, /* 4 bits long */
+        IGNORE_DEV_SEL_STRAPS, /* 1 bit long */
+        ODM_RSVD,
+        SBK_DEVKEY_STATUS,
+        _PARAMS_U32 = 0x7FFFFFFF
+};
+
+#define MAX_PARAMS SBK_DEVKEY_STATUS
+
+/* the order of the members is pre-decided. please do not change */
+struct fuse_data {
+        u32 devkey;
+        u32 jtag_dis;
+        u32 odm_prod_mode;
+        u32 bootdev_cfg;
+        u32 bootdev_sel;
+        u32 sbk[4];
+        u32 sw_rsvd;
+        u32 ignore_devsel_straps;
+        u32 odm_rsvd[8];
+};
+
+/* secondary boot device options */
+enum {
+        SECBOOTDEV_SDMMC,
+        SECBOOTDEV_NOR,
+        SECBOOTDEV_SPI,
+        SECBOOTDEV_NAND,
+        SECBOOTDEV_LBANAND,
+        SECBOOTDEV_MUXONENAND,
+        _SECBOOTDEV_MAX,
+        _SECBOOTDEV_U32 = 0x7FFFFFFF
+};
+
+/*
+ * read the fuse settings
+ * @param: io_param_type - param type enum
+ * @param: size - read size in bytes
+ */
+int tegra_fuse_read(enum fuse_io_param io_param_type, u32 *data, int size);
+
+#define FLAGS_DEVKEY                    BIT(DEVKEY)
+#define FLAGS_JTAG_DIS                  BIT(JTAG_DIS)
+#define FLAGS_SBK_DEVKEY_STATUS         BIT(SBK_DEVKEY_STATUS)
+#define FLAGS_ODM_PROD_MODE             BIT(ODM_PROD_MODE)
+#define FLAGS_SEC_BOOT_DEV_CFG          BIT(SEC_BOOT_DEV_CFG)
+#define FLAGS_SEC_BOOT_DEV_SEL          BIT(SEC_BOOT_DEV_SEL)
+#define FLAGS_SBK                       BIT(SBK)
+#define FLAGS_SW_RSVD                   BIT(SW_RSVD)
+#define FLAGS_IGNORE_DEV_SEL_STRAPS     BIT(IGNORE_DEV_SEL_STRAPS)
+#define FLAGS_ODMRSVD                   BIT(ODM_RSVD)
+
+/*
+ * Prior to invoking this routine, the caller is responsible for supplying
+ * valid fuse programming voltage.
+ *
+ * @param: pgm_data - entire data to be programmed
+ * @flags: program flags (e.g. FLAGS_DEVKEY)
+ */
+int tegra_fuse_program(struct fuse_data *pgm_data, u32 flags);
+
+/* Disables the fuse programming until the next system reset */
+void tegra_fuse_program_disable(void);
+
+extern int (*tegra_fuse_regulator_en)(int);
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h
new file mode 100644
index 00000000000..bfd61c46005
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_p1852_pdata.h
+ *
+ * Copyright 2012 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_P1852_PDATA_H
+#define __MACH_TEGRA_P1852_PDATA_H
+
+#define NUM_AUDIO_CONTROLLERS 4
+
+/* data format supported */
+enum i2s_data_format {
+        format_i2s = 0x1,
+        format_dsp = 0x2,
+        format_rjm = 0x4,
+        format_ljm = 0x8,
+        format_tdm = 0x10
+};
+
+struct codec_info_s {
+        /* Name of the Codec Dai on the system */
+        char *codec_dai_name;
+        /* Name of the I2S controller dai its connected to */
+        char *cpu_dai_name;
+        char *codec_name;       /* Name of the Codec Driver */
+        char *name;                     /* Name of the Codec-Dai-Link */
+        enum i2s_data_format i2s_format;
+        int master;                     /* Codec is Master or Slave */
+};
+
+struct tegra_p1852_platform_data {
+        struct codec_info_s codec_info[NUM_AUDIO_CONTROLLERS];
+};
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h
new file mode 100644
index 00000000000..87dcda8e61f
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_rt5640_pdata.h
+ *
+ * Copyright 2011 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+struct tegra_rt5640_platform_data {
+        const char *codec_name;
+        const char *codec_dai_name;
+        int gpio_spkr_en;
+        int gpio_hp_det;
+        int gpio_hp_mute;
+        int gpio_int_mic_en;
+        int gpio_ext_mic_en;
+};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_smmu.h b/arch/arm/mach-tegra/include/mach/tegra_smmu.h
new file mode 100644
index 00000000000..c4401c45a48
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_smmu.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_smmu.h
+ *
+ * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
+struct tegra_smmu_window {
+        unsigned long start;
+        unsigned long end;
+};
+
+extern struct tegra_smmu_window *tegra_smmu_window(int wnum);
+extern int tegra_smmu_window_count(void);
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h b/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h
new file mode 100644
index 00000000000..0ce7fa40eb2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.c
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_USB_MODEM_POWER_H
+#define __MACH_TEGRA_USB_MODEM_POWER_H
+
+#include <linux/interrupt.h>
+
+/* modem capabilities */
+#define TEGRA_MODEM_AUTOSUSPEND 0x01
+#define TEGRA_MODEM_RECOVERY    0x02
+
+/* modem operations */
+struct tegra_modem_operations {
+        int (*init) (void);     /* modem init */
+        void (*start) (void);   /* modem start */
+        void (*stop) (void);    /* modem stop */
+        void (*suspend) (void); /* send L3 hint during system suspend */
+        void (*resume) (void);  /* send L3->0 hint during system resume */
+        void (*reset) (void);   /* modem reset */
+};
+
+/* tegra usb modem power platform data */
+struct tegra_usb_modem_power_platform_data {
+        const struct tegra_modem_operations *ops;
+        unsigned int wake_gpio; /* remote wakeup gpio */
+        unsigned int flags;     /* remote wakeup irq flags */
+};
+
+#endif /* __MACH_TEGRA_USB_MODEM_POWER_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h
new file mode 100644
index 00000000000..944e410b4ae
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
+ *
+ * Copyright 2011 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+struct tegra_wm8753_platform_data {
+        int gpio_spkr_en;
+        int gpio_hp_det;
+        int gpio_hp_mute;
+        int gpio_int_mic_en;
+        int gpio_ext_mic_en;
+        unsigned int debounce_time_hp;
+};
diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
new file mode 100644
index 00000000000..9d293344a7f
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h
+ *
+ * Copyright 2011 NVIDIA, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+struct tegra_wm8903_platform_data {
+        int gpio_spkr_en;
+        int gpio_hp_det;
+        int gpio_hp_mute;
+        int gpio_int_mic_en;
+        int gpio_ext_mic_en;
+};
diff --git a/arch/arm/mach-tegra/include/mach/thermal.h b/arch/arm/mach-tegra/include/mach/thermal.h
new file mode 100644
index 00000000000..ab7b34492d9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/thermal.h
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-tegra/thermal.h
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_THERMAL_H
+#define __MACH_THERMAL_H
+
+/* All units in millicelsius */
+struct tegra_thermal_data {
+        long temp_throttle;
+        long temp_shutdown;
+        long temp_offset;
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+        long edp_offset;
+        long hysteresis_edp;
+#endif
+#ifdef CONFIG_TEGRA_THERMAL_SYSFS
+        int tc1;
+        int tc2;
+        long passive_delay;
+#else
+        long hysteresis_throttle;
+#endif
+};
+
+struct tegra_thermal_device {
+        char *name;
+        void *data;
+        long offset;
+        int (*get_temp) (void *, long *);
+        int (*get_temp_low)(void *, long *);
+        int (*set_limits) (void *, long, long);
+        int (*set_alert)(void *, void (*)(void *), void *);
+        int (*set_shutdown_temp)(void *, long);
+};
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+int tegra_thermal_init(struct tegra_thermal_data *data);
+int tegra_thermal_set_device(struct tegra_thermal_device *device);
+int tegra_thermal_exit(void);
+#else
+static inline int tegra_thermal_init(struct tegra_thermal_data *data)
+{ return 0; }
+static inline int tegra_thermal_set_device(struct tegra_thermal_device *dev)
+{ return 0; }
+static inline int tegra_thermal_exit(void)
+{ return 0; }
+#endif
+
+#endif  /* __MACH_THERMAL_H */
diff --git a/arch/arm/mach-tegra/include/mach/tsensor.h b/arch/arm/mach-tegra/include/mach/tsensor.h
new file mode 100644
index 00000000000..190a38586c5
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tsensor.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tsensor.h
+ *
+ * Tegra tsensor header file
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_TSENSOR_H
+#define __MACH_TEGRA_TSENSOR_H
+
+#include <linux/types.h>
+
+#include <mach/edp.h>
+
+#define MAX_ZONES       16
+
+struct tegra_tsensor_data;
+
+struct tegra_tsensor_platform_data {
+        void (*probe_callback)(struct tegra_tsensor_data *);
+};
+
+int tsensor_thermal_get_temp(struct tegra_tsensor_data *data,
+                                long *milli_temp);
+int tsensor_thermal_get_temp_low(struct tegra_tsensor_data *data,
+                                        long *milli_temp);
+int tsensor_thermal_set_limits(struct tegra_tsensor_data *data,
+                                long lo_limit_milli,
+                                long hi_limit_milli);
+int tsensor_thermal_set_alert(struct tegra_tsensor_data *data,
+                                void (*alert_func)(void *),
+                                void *alert_data);
+int tsensor_thermal_set_shutdown_temp(struct tegra_tsensor_data *data,
+                                long shutdown_temp_milli);
+
+#endif /* __MACH_TEGRA_TSENSOR_H */
+
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
new file mode 100644
index 00000000000..b5bf001d613
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -0,0 +1,166 @@
+/*
+ * arch/arm/mach-tegra/include/mach/usb_phy.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_USB_PHY_H
+#define __MACH_USB_PHY_H
+
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/otg.h>
+#include <linux/platform_data/tegra_usb.h>
+
+struct tegra_utmip_config {
+        u8 hssync_start_delay;
+        u8 elastic_limit;
+        u8 idle_wait_delay;
+        u8 term_range_adj;
+        u8 xcvr_setup;
+        signed char xcvr_setup_offset;
+        u8 xcvr_use_fuses;
+        u8 xcvr_lsfslew;
+        u8 xcvr_lsrslew;
+};
+
+struct tegra_ulpi_trimmer {
+        u8 shadow_clk_delay;    /* 0 ~ 31 */
+        u8 clock_out_delay;     /* 0 ~ 31 */
+        u8 data_trimmer;        /* 0 ~ 7 */
+        u8 stpdirnxt_trimmer;   /* 0 ~ 7 */
+};
+
+struct tegra_ulpi_config {
+        int enable_gpio;
+        int reset_gpio;
+        const char *clk;
+        const struct tegra_ulpi_trimmer *trimmer;
+        int (*pre_phy_on)(void);
+        int (*post_phy_on)(void);
+        int (*pre_phy_off)(void);
+        int (*post_phy_off)(void);
+        void (*phy_restore_start)(void);
+        void (*phy_restore_end)(void);
+        int phy_restore_gpio; /* null phy restore ack from device */
+        int ulpi_dir_gpio; /* ulpi dir */
+        int ulpi_d0_gpio; /* usb linestate[0] */
+        int ulpi_d1_gpio; /* usb linestate[1] */
+};
+
+struct tegra_uhsic_config {
+        int enable_gpio;
+        int reset_gpio;
+        u8 sync_start_delay;
+        u8 idle_wait_delay;
+        u8 term_range_adj;
+        u8 elastic_underrun_limit;
+        u8 elastic_overrun_limit;
+        int (*postsuspend)(void);
+        int (*preresume)(void);
+        int (*usb_phy_ready)(void);
+        int (*post_phy_off)(void);
+};
+
+enum tegra_usb_phy_port_speed {
+        TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
+        TEGRA_USB_PHY_PORT_SPEED_LOW,
+        TEGRA_USB_PHY_PORT_SPEED_HIGH,
+};
+
+enum tegra_usb_phy_mode {
+        TEGRA_USB_PHY_MODE_DEVICE,
+        TEGRA_USB_PHY_MODE_HOST,
+};
+
+struct usb_phy_plat_data {
+        int instance;
+        int vbus_irq;
+        int vbus_gpio;
+        char * vbus_reg_supply;
+};
+
+struct tegra_xtal_freq;
+
+struct tegra_usb_phy {
+        int instance;
+        const struct tegra_xtal_freq *freq;
+        void __iomem *regs;
+        void __iomem *pad_regs;
+        struct clk *clk;
+        struct clk *pll_u;
+        struct clk *pad_clk;
+        enum tegra_usb_phy_mode mode;
+        void *config;
+        struct regulator *reg_vdd;
+        struct regulator *reg_vbus;
+        enum tegra_usb_phy_type usb_phy_type;
+        bool regulator_on;
+        struct otg_transceiver *ulpi;
+        int initialized;
+        bool power_on;
+        bool remote_wakeup;
+        int hotplug;
+        unsigned int xcvr_setup_value;
+};
+
+typedef int (*tegra_phy_fp)(struct tegra_usb_phy *phy, bool is_dpd);
+typedef void (*tegra_phy_restore_start_fp)(struct tegra_usb_phy *phy,
+                                           enum tegra_usb_phy_port_speed);
+typedef void (*tegra_phy_restore_end_fp)(struct tegra_usb_phy *phy);
+
+struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
+                        void *config, enum tegra_usb_phy_mode phy_mode,
+                        enum tegra_usb_phy_type usb_phy_type);
+
+int tegra_usb_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
+
+void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
+
+void tegra_usb_phy_power_off(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_usb_phy_postsuspend(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_usb_phy_preresume(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_usb_phy_postresume(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_ehci_pre_reset(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_ehci_post_reset(struct tegra_usb_phy *phy, bool is_dpd);
+
+void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
+                                 enum tegra_usb_phy_port_speed port_speed);
+
+void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
+
+void tegra_usb_phy_close(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_bus_connect(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_bus_reset(struct tegra_usb_phy *phy);
+
+int tegra_usb_phy_bus_idle(struct tegra_usb_phy *phy);
+
+bool tegra_usb_phy_is_device_connected(struct tegra_usb_phy *phy);
+
+bool tegra_usb_phy_charger_detect(struct tegra_usb_phy *phy);
+
+int __init tegra_usb_phy_init(struct usb_phy_plat_data *pdata, int size);
+
+bool tegra_usb_phy_is_remotewake_detected(struct tegra_usb_phy *phy);
+
+#endif /* __MACH_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
new file mode 100644
index 00000000000..db488e890b9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *      Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_VMALLOC_H
+#define __MACH_TEGRA_VMALLOC_H
+
+#include <asm/sizes.h>
+
+#define VMALLOC_END        0xF8000000UL
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/w1.h b/arch/arm/mach-tegra/include/mach/w1.h
new file mode 100644
index 00000000000..c96df7abdf9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/w1.h
@@ -0,0 +1,84 @@
+/*
+ * include/mach/w1.h
+ *
+ * Copyright (C) 2010 Motorola, Inc
+ * Author: Andrei Warkentin <andreiw@motorola.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_TEGRA_W1_H
+#define __ASM_ARM_ARCH_TEGRA_W1_H
+
+struct tegra_w1_timings {
+
+        /* tsu, trelease, trdv, tlow0, tlow1 and tslot are formed
+           into the value written into OWR_RST_PRESENCE_TCTL_0 register. */
+
+        /* Read data setup, Tsu = N owr clks, Range = tsu < 1,
+           Typical value = 0x1 */
+        uint32_t tsu;
+
+        /* Release 1-wire time, Trelease = N owr clks,
+           Range = 0 <= trelease < 45, Typical value = 0xf */
+        uint32_t trelease;
+
+        /*  Read data valid time, Trdv = N+1 owr clks, Range = Exactly 15 */
+        uint32_t trdv;
+
+        /* Write zero time low, Tlow0 = N+1 owr clks,
+           Range = 60 <= tlow0 < tslot < 120, typical value = 0x3c. */
+        uint32_t tlow0;
+
+        /* Write one time low, or TLOWR both are same Tlow1 = N+1 owr clks,
+           Range = 1 <= tlow1 < 15 TlowR = N+1 owr clks,
+           Range = 1 <= tlowR < 15, Typical value = 0x1. */
+        uint32_t tlow1;
+
+        /* Active time slot for write or read data, Tslot = N+1 owr clks,
+           Range = 60 <= tslot < 120, Typical value = 0x77. */
+        uint32_t tslot;
+
+        /* tpdl, tpdh, trstl, trsth are formed in the the value written
+           into the OWR_RST_PRESENCE_TCTL_0 register. */
+
+        /* Tpdl = N owr clks, Range = 60 <= tpdl < 240,
+           Typical value = 0x78. */
+        uint32_t tpdl;
+
+        /* Tpdh = N+1 owr clks, Range = 15 <= tpdh < 60.
+           Typical value = 0x1e. */
+        uint32_t tpdh;
+
+        /* Trstl = N+1 owr clks, Range = 480 <= trstl < infinity,
+           Typical value = 0x1df. */
+        uint32_t trstl;
+
+        /* Trsth = N+1 owr clks, Range = 480 <= trsth < infinity,
+         Typical value = 0x1df. */
+        uint32_t trsth;
+
+        /* Read data sample clock. Should be <= to (tlow1 - 6) clks,
+           6 clks are used for deglitch. If deglitch  bypassed it
+           is 3 clks, Typical value = 0x7. */
+        uint32_t rdsclk;
+
+        /* Presence sample clock. Should be <= to (tpdl - 6) clks,
+           6 clks are used for deglitch. If deglitch bypassed it is 3 clks,
+           Typical value = 0x50. */
+        uint32_t psclk;
+};
+
+struct tegra_w1_platform_data {
+        const char *clk_id;
+        struct tegra_w1_timings *timings;
+};
+
+#endif