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* ARM: dts: imx: ocram size is different between imx6q and imx6dlShawn Guo2014-04-16
| | | | | | | | | | The ocram on imx6q is 256 KiB while on imx6dl it's 128 KiB. Let's have separate node for imx6q and imx6dl. It also changes imx6q size 0x3f000 to 0x40000 to match the hardware. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: add sram for imx53 and imx6qPhilipp Zabel2014-04-16
| | | | | | | | This patch enables the On-Chip SRAM (OCRAM) on i.MX53 and i.MX6 SoCs. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00269945: ARM: imx: enable cpufreq and thermal support in defconfigShawn Guo2014-04-16
| | | | | | | | Enable cpufreq and thermal support in defconfig, so that cpufreq can be used as the cpu_cooling device to throttle CPUs when passive trip point gets crossed. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx: add tempmon node for imx6q thermal supportShawn Guo2014-04-16
| | | | | | | Mark ocotp as a syscon node and add tempmon for imx6q thermal support. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: remove board specific CLKO setupShawn Guo2014-04-16
| | | | | | | | | | | The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add the missing cko output selectionShawn Guo2014-04-16
| | | | | | | | The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and there is a multiplexer to select between cko1 and cko2. Add this missing selection as the clock cko. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add cko2 clocksShawn Guo2014-04-16
| | | | | | | It adds the missing cko2 clocks, including multiplexer, divider and gate. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add spdif gate clockShawn Guo2014-04-16
| | | | | | It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: add ethernet phy fixup for KSZ9031Sascha Hauer2014-04-16
| | | | | | | | | | The KSZ9031 is used on the i.MX6 based Data Modul eDM-QMX6 board. It needs the same fixup to the rx/tx delays as other i.MX6 boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: add ethernet phy fixup for AR8031Sascha Hauer2014-04-16
| | | | | | | | | The AR8031 is used on the i.MX6 based sabreSD, sabreauto and wandboard. All need the same fixup, so add it for all i.MX6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: call ksz9021 phy fixup for all i.MX6 boardsSascha Hauer2014-04-16
| | | | | | | | | | In current U-Boot the sabrelite, nitrogen6x and titanium all need the same fixup for the ksz9021 phy. Instead of limiting the fixup to a single board apply them for all. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx_v6_v7_defconfig: Enable imx-wm8962 by defaultNicolin Chen2014-04-16
| | | | | | | | | | Commit 42914fdde5bcda9f9118f20456d2c22300cda645 upstream. Enable imx-wm8962 and PM_RUNTIME, essential for WM8962 CODEC driver. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio supportNicolin Chen2014-04-16
| | | | | | | | | | Commit 77b38fc36c5dc6f99d1db0a3c216724e53e5e257 upstream. Enable WM8962 ALSA machine driver via devicetree. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUXNicolin Chen2014-04-16
| | | | | | | | | | Commit 48828700188f4b054e94ac08994bc5874e77a2c5 upstream. Enable SSI2 and its pin configuration in AUDMUX. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC supportNicolin Chen2014-04-16
| | | | | | | | | | Commit 20426febe6026ba251afcb5bb7b32ac72837bde2 upstream. Add WM8962 CODEC support and enable its parent I2C bus. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962Nicolin Chen2014-04-16
| | | | | | | | | | | Commit fdbfb43b39e7876fba7048ab930c4c72e7ec2561 upstream. On Sabre SD, system controls WM8962 power by pulling up/down GPIO_4_10, so add a regulator controled by GPIO_4_10 for WM8962. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx6qdl-sabresd: add clko1 iomux configurationNicolin Chen2014-04-16
| | | | | | | | | | Commit 521b43d41cd41ac8763603a7b923703d5d368bc9 upstream. Setting GPIO_0 pad as clko1 clock output to provide MCLK for WM8962. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresdNicolin Chen2014-04-16
| | | | | | | | | | Commit e7eccc7e16acfcc3e613e7c0df7e62528d24581c upstream. WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx: remove old DMA binding data from gpmi nodeShawn Guo2014-04-16
| | | | | | | | | | | | After mxs-dma driver adopts generic DMA device tree binding, gpmi channel interrupt number is defined in DMA controller node, and channel ID is listed in "dmas" property. So the DMA channel interrupt number in gpmi node "interrupts" property and fsl,gpmi-dma-channel which are used by old customized DMA binding can be removed now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx: use generic DMA bindings for SSI nodesShawn Guo2014-04-16
| | | | | | | Updates SSI nodes to adopt generic DMA bindings. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx6qdl/imx6sl: add the dma property for uartHuang Shijie2014-04-16
| | | | | | | | | | | Add the dma property for all the uart. Note: Add the dma property does not mean we enable the dma for this uart. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx: add #dma-cells property for sdmaHuang Shijie2014-04-16
| | | | | | | | Add the #dma-cells property for all the sdma in all the imx platforms. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00269945: ARM: imx: add CONFIG_GPIO_PCA953X into defconfigShawn Guo2014-04-16
| | | | | | | CONFIG_GPIO_PCA953X enables driver support for MAX7310 which is used on imx6qdl-sabreauto board for IO expanders. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00269945: ARM: dts: add uart3 support for imx6qdl-sabreautoShawn Guo2014-04-16
| | | | | | | | | On imx6qdl-sabreauto board, the pin function UART3_CTS is steered by the GPIO4 of MAX7310 Expander B, while UART3_RXD and UART3_TXD are steered by GPIO3 of MAX7310 Expander C. And both GPIOs need to be pulled high to assert UART3 on the board. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx6qdl: add a new pinctrl for uart3Huang Shijie2014-04-16
| | | | | | | | Add the a new pinctrl for uart3. In the imx6q{dl}-sabreauto boards, the uart3 is used for Bluetooth. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ENGR00269945: ARM: dts: add max7310 support for imx6qdl-sabreautoShawn Guo2014-04-16
| | | | | | | | On imx6qdl-sabreauto board, there are three IO expanders implemented by max7310, which are all controlled by I2C3. And GPIO5_4 is steering the I2C3_SDA availability, while GPIO1_15 is used to reset max7310. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00269945: select ARCH_HAS_RESET_CONTROLLER for IMXShawn Guo2014-04-16
| | | | | | | | Move ARCH_HAS_RESET_CONTROLLER from HAVE_IMX_SRC to ARCH_MXC to have it selected for the whole IMX family instead of SRC (System Reset Controller), since GPIO could be another reset controller in many cases. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: add more imx6q/dl pin groupsShawn Guo2014-04-16
| | | | | | | | | | Add more imx6q/dl pin groups for those supported boards, e.g. sabresd, sabreauto, arm2. IPU2 pin groups are added into imx6q.dtsi, since the block is only available on imx6q. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx: share pad macro names between imx6q and imx6dlShawn Guo2014-04-16
| | | | | | | | | | | | | | | | | | | | | The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board design can work with either chip plugged into the socket, e.g. sabresd and sabreauto boards. We currently define pin groups in imx6q.dtsi and imx6dl.dtsi respectively because the pad macro names are different between two chips. This brings a maintenance burden on having the same label point to the same pin group defined in two places. The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs pad macro names. Then the pin groups becomes completely common between imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the long term maintenance of imx6q/dt pin settings becomes easier. Unfortunately, the change brings some dramatic diff stat, but it's all about DTS file, and the ultimate net diff stat is good. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: add more pin groups for imx6q/dlShawn Guo2014-04-16
| | | | | | | The patch adds pin groups that are already defined by community kernel, so that both kernels can align on the pin group label names. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: imx6q{dl}: add DTE pads for uartShawn Guo2014-04-16
| | | | | | | | The uart2 in the imx6q-arm2 board is used as a DTE uart, this patch adds the necessary DTE pads for uart2. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Select MIGHT_HAVE_CACHE_L2X0Fabio Estevam2014-04-16
| | | | | | | | | | Select MIGHT_HAVE_CACHE_L2X0 for armv6 and armv7 i.MX SoCs. By selecting MIGHT_HAVE_CACHE_L2X0, the user still has the possibility to disable CACHE_L2X0 selection via menuconfig. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: fix imx_init_l2cache storage classVincent Stehlé2014-04-16
| | | | | | | | | | | | | | | This fixes the following compilation error: arch/arm/mach-imx/system.c:101:123: error: static declaration of ‘imx_init_l2cache’ follows non-static declaration In file included from arch/arm/mach-imx/system.c:32:0: arch/arm/mach-imx/common.h:165:13: note: previous declaration of ‘imx_init_l2cache’ was here arch/arm/mach-imx/system.c:101:123: warning: ‘imx_init_l2cache’ defined but not used [-Wunused-function] Signed-off-by: Vincent Stehlé <vincent.stehle@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: fix vf610 enet module clock selectionShawn Guo2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fec/enet driver calculates MDC rate with the formula below. ref_freq / ((MII_SPEED + 1) x 2) The ref_freq here is the fec internal module clock, which is missing from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly supplies RMII clock (50 MHz) as the source to fec. This results in the situation that fec driver gets ref_freq as 50 MHz, while physically it runs at 66 MHz (fec module clock physically sources from ipg which runs at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041 keeps swithing between Full and Half mode as below. libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half Add the missing module clock for ENET0 and ENET1, and correct the clock supplying in device tree to fix above issue. Thanks to Alison Wang <b18965@freescale.com> for debugging the issue. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6: change some clocks to fixup clocksLiu Ying2014-04-16
| | | | | | | | | | All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add common clock support for fixup muxLiu Ying2014-04-16
| | | | | | | | | | | | | | One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for multiplexer clock which is called before writing a value to clock registers to support this kind of multiplexer clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add common clock support for fixup divLiu Ying2014-04-16
| | | | | | | | | | | | | | One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for divider clock which is called before writing a value to clock registers to support this kind of divider clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: use imx specific L2 init function on imx6slShawn Guo2014-04-16
| | | | | | | The optimized L2 prefect and power setting done in imx_init_l2cache() can also benefit imx6sl, so let's call the function on imx6sl as well. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: let L2 initialization be a common functionShawn Guo2014-04-16
| | | | | | | | Move imx6q L2 initialization function imx6q_init_l2cache() into system.c, and rename it imx_init_l2cache(), so that other platforms other than imx6q can also use the function. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: add i.MX6 specific L2 cache configurationDirk Behme2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit b3a9c315378ff811bf34393f2f0a6e8b9ffced3b upstream. To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
* ARM: dts: i.MX6: configure L2 cache data and tag latencyDirk Behme2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | Commit 5a5ca56e057d206db13461b84a7da3a3543e1206 upstream. Configure the data and tag latency for the L2 cache. This improves the system performance. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] which does writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); In this patch we are doing the same via the device tree. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
* ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DLPhilipp Zabel2014-04-16
| | | | | | | i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: clk: add the eim_slow clockHuang Shijie2014-04-16
| | | | | | | | | | Commit 9545b2ed68eef1541219d5c6351c10e698a24f39 upstream. Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: clk: add different DualLite MLB clock configDirk Behme2014-04-16
| | | | | | | | | | | | | | | Commit fbcb441217dd2bce00e892fd5b2a481c2249f1a4 upstream. The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock configuration. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: disable pll8_mlb in mx6q_clksJiada Wang2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | Commit 7f96d2d4d86377df04c8856b8fd47b0ad58c98aa upstream. The MLB PLL clock's operation doesn't fit for clock framework and it should be handled internally in MLB driver. Remove initialization of pll8_mlb clock device but leave its declaration in mx6q_clks to avoid affecting imx6q clock numbering. [ shawn.guo: The MLB PLL is currently implemented as an imx pllv3 clock. But it does not really make too much sense, because the PLL does not have ENABLE, POWERDOWN and DIV_SELECT bits. Also commit 0e57446 (ARM i.MX6: correct MLB clock configuration) already removes the incorrect parenting on MLB PLL, now it's safe and reasonable to remove the PLL completely from clock framework, and let MLB driver handle the PLL per its particular need. ] Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: clk: add i.MX6 DualLite differencesDirk Behme2014-04-16
| | | | | | | | | | | | | | | | | | Commit 2e603ad98460fd0efab71e618d49a2ffc9aef67b upstream. The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and moves the gpu2_core configuration at that place. Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences by using cpu_is_mx6dl(). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00269945: ARM: imx: enable Vybrid build in defconfigShawn Guo2014-04-16
| | | | | | Enable Vybrid build with serial console support in defconfig. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add low-level debug for VybridShawn Guo2014-04-16
| | | | | | | Add low-level debug support for Vybrid, so that earlyprintk can be enabled for debugging early boot issue. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: add initial VF610 Tower board dts supportJingchang Lu2014-04-16
| | | | | | | | | | | Commit e77b74ee6c4115a0fe1fdb673dbf25ffe1277205 upstream. Add initial Freescale Vybrid VF610 Tower board support with uart and fec enabled. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: dts: add SoC level device tree source for VF610Jingchang Lu2014-04-16
| | | | | | | | | | Commit d02e13495d3a0e686c00990bc1d688336bdfe2bb upstream. Add SoC level device tree source for Freescale Vybrid VF610. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-12 09:24:34 -0400