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authorShawn Guo <shawn.guo@freescale.com>2013-07-09 23:06:17 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:00:38 -0400
commitada14d1c9627f564cf5ecc030502720c02e88eb2 (patch)
treeaffa41dac22f92ca62e5a2f76a5bc8a8a83c0276 /arch
parent6da84fb3f2ba5b517d0cbd1416c63e6fa6c1e5e7 (diff)
ARM: dts: add more pin groups for imx6q/dl
The patch adds pin groups that are already defined by community kernel, so that both kernels can align on the pin group label names. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi255
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi116
2 files changed, 368 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 62dc78126795..277e52fc1730 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -37,6 +37,54 @@
37 compatible = "fsl,imx6dl-iomuxc"; 37 compatible = "fsl,imx6dl-iomuxc";
38 reg = <0x020e0000 0x4000>; 38 reg = <0x020e0000 0x4000>;
39 39
40 audmux {
41 pinctrl_audmux_1: audmux-1 {
42 fsl,pins = <
43 MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
44 MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
45 MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
46 MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
47 >;
48 };
49
50 pinctrl_audmux_2: audmux-2 {
51 fsl,pins = <
52 MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
53 MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
54 MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
55 MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
56 >;
57 };
58 };
59
60 ecspi1 {
61 pinctrl_ecspi1_1: ecspi1grp-1 {
62 fsl,pins = <
63 MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
64 MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
65 MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
66 >;
67 };
68
69 pinctrl_ecspi1_2: ecspi1grp-2 {
70 fsl,pins = <
71 MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
72 MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
73 MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
74 >;
75 };
76 };
77
78 ecspi3 {
79 pinctrl_ecspi3_1: ecspi3grp-1 {
80 fsl,pins = <
81 MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
82 MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
83 MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
84 >;
85 };
86 };
87
40 enet { 88 enet {
41 pinctrl_enet_1: enetgrp-1 { 89 pinctrl_enet_1: enetgrp-1 {
42 fsl,pins = < 90 fsl,pins = <
@@ -78,6 +126,92 @@
78 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 126 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
79 >; 127 >;
80 }; 128 };
129
130 pinctrl_enet_3: enetgrp-3 {
131 fsl,pins = <
132 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
133 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
134 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
135 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
136 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
137 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
138 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
139 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
140 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
141 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
142 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
143 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
144 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
145 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
146 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
147 MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
148 >;
149 };
150 };
151
152 gpmi-nand {
153 pinctrl_gpmi_nand_1: gpmi-nand-1 {
154 fsl,pins = <
155 MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
156 MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
157 MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
158 MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
159 MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
160 MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
161 MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
162 MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
163 MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
164 MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
165 MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
166 MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
167 MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
168 MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
169 MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
170 MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
171 MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
172 >;
173 };
174 };
175
176 i2c1 {
177 pinctrl_i2c1_1: i2c1grp-1 {
178 fsl,pins = <
179 MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
180 MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
181 >;
182 };
183
184 pinctrl_i2c1_2: i2c1grp-2 {
185 fsl,pins = <
186 MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
187 MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
188 >;
189 };
190 };
191
192 i2c2 {
193 pinctrl_i2c2_1: i2c2grp-1 {
194 fsl,pins = <
195 MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
196 MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
197 >;
198 };
199
200 pinctrl_i2c2_2: i2c2grp-2 {
201 fsl,pins = <
202 MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
203 MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
204 >;
205 };
206 };
207
208 i2c3 {
209 pinctrl_i2c3_1: i2c3grp-1 {
210 fsl,pins = <
211 MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
212 MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
213 >;
214 };
81 }; 215 };
82 216
83 uart1 { 217 uart1 {
@@ -89,6 +223,24 @@
89 }; 223 };
90 }; 224 };
91 225
226 uart2 {
227 pinctrl_uart2_1: uart2grp-1 {
228 fsl,pins = <
229 MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
230 MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
231 >;
232 };
233
234 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
235 fsl,pins = <
236 MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
237 MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
238 MX6DL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
239 MX6DL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
240 >;
241 };
242 };
243
92 uart4 { 244 uart4 {
93 pinctrl_uart4_1: uart4grp-1 { 245 pinctrl_uart4_1: uart4grp-1 {
94 fsl,pins = < 246 fsl,pins = <
@@ -99,6 +251,12 @@
99 }; 251 };
100 252
101 usbotg { 253 usbotg {
254 pinctrl_usbotg_1: usbotggrp-1 {
255 fsl,pins = <
256 MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
257 >;
258 };
259
102 pinctrl_usbotg_2: usbotggrp-2 { 260 pinctrl_usbotg_2: usbotggrp-2 {
103 fsl,pins = < 261 fsl,pins = <
104 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 262 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
@@ -121,6 +279,17 @@
121 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 279 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
122 >; 280 >;
123 }; 281 };
282
283 pinctrl_usdhc2_2: usdhc2grp-2 {
284 fsl,pins = <
285 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
286 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
287 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
288 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
289 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
290 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
291 >;
292 };
124 }; 293 };
125 294
126 usdhc3 { 295 usdhc3 {
@@ -139,7 +308,7 @@
139 >; 308 >;
140 }; 309 };
141 310
142 pinctrl_usdhc3_2: usdhc3grp_2 { 311 pinctrl_usdhc3_2: usdhc3grp-2 {
143 fsl,pins = < 312 fsl,pins = <
144 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 313 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
145 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 314 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
@@ -151,7 +320,91 @@
151 }; 320 };
152 }; 321 };
153 322
323 usdhc4 {
324 pinctrl_usdhc4_1: usdhc4grp-1 {
325 fsl,pins = <
326 MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059
327 MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059
328 MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
329 MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
330 MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
331 MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
332 MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059
333 MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059
334 MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059
335 MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059
336 >;
337 };
154 338
339 pinctrl_usdhc4_2: usdhc4grp-2 {
340 fsl,pins = <
341 MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059
342 MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059
343 MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
344 MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
345 MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
346 MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
347 >;
348 };
349 };
350
351 weim {
352 pinctrl_weim_cs0_1: weim_cs0grp-1 {
353 fsl,pins = <
354 MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
355 >;
356 };
357
358 pinctrl_weim_nor_1: weim_norgrp-1 {
359 fsl,pins = <
360 MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
361 MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
362 MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
363 /* data */
364 MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
365 MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
366 MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
367 MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
368 MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
369 MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
370 MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
371 MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
372 MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
373 MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
374 MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
375 MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
376 MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
377 MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
378 MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
379 MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
380 /* address */
381 MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
382 MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
383 MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
384 MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
385 MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
386 MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
387 MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
388 MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
389 MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
390 MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
391 MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
392 MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
393 MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
394 MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
395 MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
396 MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
397 MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
398 MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
399 MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
400 MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
401 MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
402 MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
403 MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
404 MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
405 >;
406 };
407 };
155 }; 408 };
156 409
157 pxp: pxp@020f0000 { 410 pxp: pxp@020f0000 {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index dc54a72a3bcd..e0b7bad7f78f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -108,6 +108,14 @@
108 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 108 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
109 >; 109 >;
110 }; 110 };
111
112 pinctrl_ecspi1_2: ecspi1grp-2 {
113 fsl,pins = <
114 MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
115 MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
116 MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
117 >;
118 };
111 }; 119 };
112 120
113 ecspi3 { 121 ecspi3 {
@@ -161,6 +169,27 @@
161 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 169 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
162 >; 170 >;
163 }; 171 };
172
173 pinctrl_enet_3: enetgrp-3 {
174 fsl,pins = <
175 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
176 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
177 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
178 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
179 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
180 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
181 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
182 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
183 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
184 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
185 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
186 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
187 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
188 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
189 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
190 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
191 >;
192 };
164 }; 193 };
165 194
166 gpmi-nand { 195 gpmi-nand {
@@ -172,8 +201,6 @@
172 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 201 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
173 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 202 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
174 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 203 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
175 MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
176 MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
177 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 204 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
178 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 205 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
179 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 206 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
@@ -196,6 +223,13 @@
196 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 223 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
197 >; 224 >;
198 }; 225 };
226
227 pinctrl_i2c1_2: i2c1grp-2 {
228 fsl,pins = <
229 MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
230 MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
231 >;
232 };
199 }; 233 };
200 234
201 i2c2 { 235 i2c2 {
@@ -232,6 +266,15 @@
232 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 266 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
233 >; 267 >;
234 }; 268 };
269
270 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
271 fsl,pins = <
272 MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
273 MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
274 MX6Q_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
275 MX6Q_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
276 >;
277 };
235 }; 278 };
236 279
237 uart4 { 280 uart4 {
@@ -272,6 +315,17 @@
272 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 315 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
273 >; 316 >;
274 }; 317 };
318
319 pinctrl_usdhc2_2: usdhc2grp-2 {
320 fsl,pins = <
321 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
322 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
323 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
324 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
325 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
326 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
327 >;
328 };
275 }; 329 };
276 330
277 usdhc3 { 331 usdhc3 {
@@ -329,6 +383,64 @@
329 >; 383 >;
330 }; 384 };
331 }; 385 };
386
387 weim {
388 pinctrl_weim_cs0_1: weim_cs0grp-1 {
389 fsl,pins = <
390 MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
391 >;
392 };
393
394 pinctrl_weim_nor_1: weim_norgrp-1 {
395 fsl,pins = <
396 MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
397 MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
398 MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
399 /* data */
400 MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
401 MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
402 MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
403 MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
404 MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
405 MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
406 MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
407 MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
408 MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
409 MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
410 MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
411 MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
412 MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
413 MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
414 MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
415 MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
416 /* address */
417 MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
418 MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
419 MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
420 MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
421 MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
422 MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
423 MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
424 MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
425 MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
426 MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
427 MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
428 MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
429 MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
430 MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
431 MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
432 MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
433 MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
434 MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
435 MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
436 MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
437 MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
438 MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
439 MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
440 MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
441 >;
442 };
443 };
332 }; 444 };
333 }; 445 };
334 446
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 19:52:31 -0500