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-rw-r--r--arch/powerpc/include/asm/mmu.h49
1 files changed, 30 insertions, 19 deletions
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index eb20eb3b8fb0..25607604a7a5 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -48,7 +48,7 @@
48#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 48#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
49 49
50/* Enable >32-bit physical addresses on 32-bit processor, only used 50/* Enable >32-bit physical addresses on 32-bit processor, only used
51 * by CONFIG_6xx currently as BookE supports that from day 1 51 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
52 */ 52 */
53#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 53#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
54 54
@@ -131,16 +131,37 @@ DECLARE_PER_CPU(int, next_tlbcam_idx);
131#endif 131#endif
132 132
133enum { 133enum {
134 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx | 134 MMU_FTRS_POSSIBLE =
135 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E | 135#ifdef CONFIG_PPC_BOOK3S
136 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS | 136 MMU_FTR_HPTE_TABLE |
137 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX | 137#endif
138 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU | 138#ifdef CONFIG_PPC_8xx
139 MMU_FTR_TYPE_8xx |
140#endif
141#ifdef CONFIG_40x
142 MMU_FTR_TYPE_40x |
143#endif
144#ifdef CONFIG_44x
145 MMU_FTR_TYPE_44x |
146#endif
147#if defined(CONFIG_E200) || defined(CONFIG_E500)
148 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
149#endif
150#ifdef CONFIG_PPC_47x
151 MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
152#endif
153#ifdef CONFIG_PPC_BOOK3S_32
154 MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU |
155#endif
156#ifdef CONFIG_PPC_BOOK3E_64
139 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS | 157 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
158#endif
159#ifdef CONFIG_PPC_BOOK3S_64
140 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | 160 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
141 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | 161 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
142 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | 162 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
143 MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA | 163 MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
164#endif
144#ifdef CONFIG_PPC_RADIX_MMU 165#ifdef CONFIG_PPC_RADIX_MMU
145 MMU_FTR_TYPE_RADIX | 166 MMU_FTR_TYPE_RADIX |
146#endif 167#endif
@@ -338,21 +359,11 @@ static inline void mmu_early_init_devtree(void) { }
338#endif /* __ASSEMBLY__ */ 359#endif /* __ASSEMBLY__ */
339#endif 360#endif
340 361
341#if defined(CONFIG_PPC_STD_MMU_32) 362#if defined(CONFIG_PPC_BOOK3S_32)
342/* 32-bit classic hash table MMU */ 363/* 32-bit classic hash table MMU */
343#include <asm/book3s/32/mmu-hash.h> 364#include <asm/book3s/32/mmu-hash.h>
344#elif defined(CONFIG_40x) 365#elif defined(CONFIG_PPC_MMU_NOHASH)
345/* 40x-style software loaded TLB */ 366#include <asm/nohash/mmu.h>
346# include <asm/mmu-40x.h>
347#elif defined(CONFIG_44x)
348/* 44x-style software loaded TLB */
349# include <asm/mmu-44x.h>
350#elif defined(CONFIG_PPC_BOOK3E_MMU)
351/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
352# include <asm/mmu-book3e.h>
353#elif defined (CONFIG_PPC_8xx)
354/* Motorola/Freescale 8xx software loaded TLB */
355# include <asm/mmu-8xx.h>
356#endif 367#endif
357 368
358#endif /* __KERNEL__ */ 369#endif /* __KERNEL__ */