aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2016-12-05 20:01:33 -0500
committerDave Airlie <airlied@redhat.com>2016-12-05 20:01:33 -0500
commit17f1dfd01ca105f0d3609225c9e7079c7df483b2 (patch)
treea30e2b896d41f0bb5206825d07ffd49cff97ed64 /drivers/gpu/drm/amd/amdgpu
parent770ac20413ce654f6e4efaaf24e954ebb907fc3b (diff)
parente7b8243d3e0ace9f5130c3b5c3c52a50039a7501 (diff)
Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next
- lots of code cleanup - lots of bug fixes - expose rpm based fan info via hwmon - lots of clock and powergating fixes - SI register header cleanup and conversion to common format used by newer asics * 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (54 commits) drm/amdgpu: drop is_display_hung from display funcs drm/amdgpu/uvd: reduce IB parsing overhead on UVD5+ (v2) drm/amdgpu/uvd: consolidate code for fetching addr from ctx drm/amdgpu: Disable DPM in virtualization drm/amdgpu: use AMDGPU_GEM_CREATE_VRAM_CLEARED for VM PD/PTs (v2) drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2) drm/amdgpu: fix error handling in amdgpu_bo_create_restricted drm/amdgpu: fix amdgpu_fill_buffer (v2) drm/amdgpu: remove amdgpu_irq_get_delayed amdgpu: Wrap dev_err() calls on vm faults with printk_ratelimit() amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault() drm/amd/amdgpu: port of DCE v6 to new headers (v3) drm/amdgpu: cleanup unused iterator members for sdma v2.4 drm/amdgpu: cleanup unused iterator members for sdma v3 drm/amdgpu:impl vgt_flush for VI(V5) drm/amdgpu: enable uvd mgcg for Fiji. drm/amdgpu: refine cz uvd clock gate logic. drm/amdgpu: change log level to KERN_INFO in ci_dpm.c drm/amdgpu: always un-gate UVD REGS path. drm/amdgpu/sdma: fix typo in packet setup ...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c39
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c47
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c69
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c99
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c515
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_virtual.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c770
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c23
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c339
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_enums.h272
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c42
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c113
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c7
40 files changed, 1464 insertions, 1152 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 121a034fe27d..f53e52f4d672 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -92,13 +92,13 @@ extern int amdgpu_vm_debug;
92extern int amdgpu_sched_jobs; 92extern int amdgpu_sched_jobs;
93extern int amdgpu_sched_hw_submission; 93extern int amdgpu_sched_hw_submission;
94extern int amdgpu_powerplay; 94extern int amdgpu_powerplay;
95extern int amdgpu_powercontainment; 95extern int amdgpu_no_evict;
96extern int amdgpu_direct_gma_size;
96extern unsigned amdgpu_pcie_gen_cap; 97extern unsigned amdgpu_pcie_gen_cap;
97extern unsigned amdgpu_pcie_lane_cap; 98extern unsigned amdgpu_pcie_lane_cap;
98extern unsigned amdgpu_cg_mask; 99extern unsigned amdgpu_cg_mask;
99extern unsigned amdgpu_pg_mask; 100extern unsigned amdgpu_pg_mask;
100extern char *amdgpu_disable_cu; 101extern char *amdgpu_disable_cu;
101extern int amdgpu_sclk_deep_sleep_en;
102extern char *amdgpu_virtual_display; 102extern char *amdgpu_virtual_display;
103extern unsigned amdgpu_pp_feature_mask; 103extern unsigned amdgpu_pp_feature_mask;
104extern int amdgpu_vram_page_split; 104extern int amdgpu_vram_page_split;
@@ -1633,7 +1633,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1633#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1633#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1634#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1634#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1635#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1635#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1636#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
1637#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1636#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1638#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1637#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1639#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1638#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 2b6afe123f3d..b7e2762fcdd2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -70,7 +70,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
70 return false; 70 return false;
71 } 71 }
72 adev->bios = kmalloc(size, GFP_KERNEL); 72 adev->bios = kmalloc(size, GFP_KERNEL);
73 if (adev->bios == NULL) { 73 if (!adev->bios) {
74 iounmap(bios); 74 iounmap(bios);
75 return false; 75 return false;
76 } 76 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 78da52f90099..5a277495d6a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -841,16 +841,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
841 return amdgpu_cs_sync_rings(p); 841 return amdgpu_cs_sync_rings(p);
842} 842}
843 843
844static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
845{
846 if (r == -EDEADLK) {
847 r = amdgpu_gpu_reset(adev);
848 if (!r)
849 r = -EAGAIN;
850 }
851 return r;
852}
853
854static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 844static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
855 struct amdgpu_cs_parser *parser) 845 struct amdgpu_cs_parser *parser)
856{ 846{
@@ -1054,29 +1044,29 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1054 r = amdgpu_cs_parser_init(&parser, data); 1044 r = amdgpu_cs_parser_init(&parser, data);
1055 if (r) { 1045 if (r) {
1056 DRM_ERROR("Failed to initialize parser !\n"); 1046 DRM_ERROR("Failed to initialize parser !\n");
1057 amdgpu_cs_parser_fini(&parser, r, false); 1047 goto out;
1058 r = amdgpu_cs_handle_lockup(adev, r);
1059 return r;
1060 }
1061 r = amdgpu_cs_parser_bos(&parser, data);
1062 if (r == -ENOMEM)
1063 DRM_ERROR("Not enough memory for command submission!\n");
1064 else if (r && r != -ERESTARTSYS)
1065 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1066 else if (!r) {
1067 reserved_buffers = true;
1068 r = amdgpu_cs_ib_fill(adev, &parser);
1069 } 1048 }
1070 1049
1071 if (!r) { 1050 r = amdgpu_cs_parser_bos(&parser, data);
1072 r = amdgpu_cs_dependencies(adev, &parser); 1051 if (r) {
1073 if (r) 1052 if (r == -ENOMEM)
1074 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 1053 DRM_ERROR("Not enough memory for command submission!\n");
1054 else if (r != -ERESTARTSYS)
1055 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1056 goto out;
1075 } 1057 }
1076 1058
1059 reserved_buffers = true;
1060 r = amdgpu_cs_ib_fill(adev, &parser);
1077 if (r) 1061 if (r)
1078 goto out; 1062 goto out;
1079 1063
1064 r = amdgpu_cs_dependencies(adev, &parser);
1065 if (r) {
1066 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1067 goto out;
1068 }
1069
1080 for (i = 0; i < parser.job->num_ibs; i++) 1070 for (i = 0; i < parser.job->num_ibs; i++)
1081 trace_amdgpu_cs(&parser, i); 1071 trace_amdgpu_cs(&parser, i);
1082 1072
@@ -1088,7 +1078,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1088 1078
1089out: 1079out:
1090 amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 1080 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1091 r = amdgpu_cs_handle_lockup(adev, r);
1092 return r; 1081 return r;
1093} 1082}
1094 1083
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index deee2db36fce..fc790e5c46fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1017,8 +1017,8 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
1017 amdgpu_vm_block_size = 9; 1017 amdgpu_vm_block_size = 9;
1018 } 1018 }
1019 1019
1020 if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) || 1020 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1021 !amdgpu_check_pot_argument(amdgpu_vram_page_split)) { 1021 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1022 dev_warn(adev->dev, "invalid VRAM page split (%d)\n", 1022 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1023 amdgpu_vram_page_split); 1023 amdgpu_vram_page_split);
1024 amdgpu_vram_page_split = 1024; 1024 amdgpu_vram_page_split = 1024;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index bd85e35998e7..955d6f21e2b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -52,6 +52,8 @@ enum amdgpu_dpm_event_src {
52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
53}; 53};
54 54
55#define SCLK_DEEP_SLEEP_MASK 0x8
56
55struct amdgpu_ps { 57struct amdgpu_ps {
56 u32 caps; /* vbios flags */ 58 u32 caps; /* vbios flags */
57 u32 class; /* vbios flags */ 59 u32 class; /* vbios flags */
@@ -317,6 +319,11 @@ struct amdgpu_dpm_funcs {
317 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 319 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
318 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 320 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
319 321
322#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
323 ((adev)->pp_enabled ? \
324 (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \
325 -EINVAL)
326
320#define amdgpu_dpm_get_sclk(adev, l) \ 327#define amdgpu_dpm_get_sclk(adev, l) \
321 ((adev)->pp_enabled ? \ 328 ((adev)->pp_enabled ? \
322 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 329 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 42da6163b893..7914f999b1bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -91,8 +91,8 @@ int amdgpu_exp_hw_support = 0;
91int amdgpu_sched_jobs = 32; 91int amdgpu_sched_jobs = 32;
92int amdgpu_sched_hw_submission = 2; 92int amdgpu_sched_hw_submission = 2;
93int amdgpu_powerplay = -1; 93int amdgpu_powerplay = -1;
94int amdgpu_powercontainment = 1; 94int amdgpu_no_evict = 0;
95int amdgpu_sclk_deep_sleep_en = 1; 95int amdgpu_direct_gma_size = 0;
96unsigned amdgpu_pcie_gen_cap = 0; 96unsigned amdgpu_pcie_gen_cap = 0;
97unsigned amdgpu_pcie_lane_cap = 0; 97unsigned amdgpu_pcie_lane_cap = 0;
98unsigned amdgpu_cg_mask = 0xffffffff; 98unsigned amdgpu_cg_mask = 0xffffffff;
@@ -182,14 +182,14 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
182MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 182MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
183module_param_named(powerplay, amdgpu_powerplay, int, 0444); 183module_param_named(powerplay, amdgpu_powerplay, int, 0444);
184 184
185MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)");
186module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
187
188MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 185MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
189module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); 186module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
190 187
191MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); 188MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
192module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); 189module_param_named(no_evict, amdgpu_no_evict, int, 0444);
190
191MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
192module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
193 193
194MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 194MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
195module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 195module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 97928d7281f6..7b60fb79c3a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
382 if (!ring->fence_drv.fences) 382 if (!ring->fence_drv.fences)
383 return -ENOMEM; 383 return -ENOMEM;
384 384
385 timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 385 /* No need to setup the GPU scheduler for KIQ ring */
386 if (timeout == 0) { 386 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
387 /* 387 timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
388 * FIXME: 388 if (timeout == 0) {
389 * Delayed workqueue cannot use it directly, 389 /*
390 * so the scheduler will not use delayed workqueue if 390 * FIXME:
391 * MAX_SCHEDULE_TIMEOUT is set. 391 * Delayed workqueue cannot use it directly,
392 * Currently keep it simple and silly. 392 * so the scheduler will not use delayed workqueue if
393 */ 393 * MAX_SCHEDULE_TIMEOUT is set.
394 timeout = MAX_SCHEDULE_TIMEOUT; 394 * Currently keep it simple and silly.
395 } 395 */
396 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 396 timeout = MAX_SCHEDULE_TIMEOUT;
397 num_hw_submission, 397 }
398 timeout, ring->name); 398 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
399 if (r) { 399 num_hw_submission,
400 DRM_ERROR("Failed to create scheduler on ring %s.\n", 400 timeout, ring->name);
401 ring->name); 401 if (r) {
402 return r; 402 DRM_ERROR("Failed to create scheduler on ring %s.\n",
403 ring->name);
404 return r;
405 }
403 } 406 }
404 407
405 return 0; 408 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 9fa809876339..fb902932f571 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -424,15 +424,6 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
424 return 0; 424 return 0;
425} 425}
426 426
427bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
428 struct amdgpu_irq_src *src,
429 unsigned type)
430{
431 if ((type >= src->num_types) || !src->enabled_types)
432 return false;
433 return atomic_inc_return(&src->enabled_types[type]) == 1;
434}
435
436/** 427/**
437 * amdgpu_irq_put - disable interrupt 428 * amdgpu_irq_put - disable interrupt
438 * 429 *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index f016464035b8..1642f4108297 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -88,9 +88,6 @@ int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
88 unsigned type); 88 unsigned type);
89int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 89int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
90 unsigned type); 90 unsigned type);
91bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
92 struct amdgpu_irq_src *src,
93 unsigned type);
94int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 91int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
95 unsigned type); 92 unsigned type);
96bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 93bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 1e23334b07fb..202b4176b74e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -271,8 +271,6 @@ struct amdgpu_display_funcs {
271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
272 /* wait for vblank */ 272 /* wait for vblank */
273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
274 /* is dce hung */
275 bool (*is_display_hung)(struct amdgpu_device *adev);
276 /* set backlight level */ 274 /* set backlight level */
277 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 275 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
278 u8 level); 276 u8 level);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1479d09bd4dd..bf79b73e1538 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -128,17 +128,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
128 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 128 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
129 lpfn = adev->mc.real_vram_size >> PAGE_SHIFT; 129 lpfn = adev->mc.real_vram_size >> PAGE_SHIFT;
130 130
131 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
132 !(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
133 adev->mc.visible_vram_size < adev->mc.real_vram_size) {
134 places[c].fpfn = visible_pfn;
135 places[c].lpfn = lpfn;
136 places[c].flags = TTM_PL_FLAG_WC |
137 TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |
138 TTM_PL_FLAG_TOPDOWN;
139 c++;
140 }
141
142 places[c].fpfn = 0; 131 places[c].fpfn = 0;
143 places[c].lpfn = lpfn; 132 places[c].lpfn = lpfn;
144 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 133 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
@@ -382,39 +371,36 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
382 371
383 amdgpu_fill_placement_to_bo(bo, placement); 372 amdgpu_fill_placement_to_bo(bo, placement);
384 /* Kernel allocation are uninterruptible */ 373 /* Kernel allocation are uninterruptible */
374
375 if (!resv) {
376 bool locked;
377
378 reservation_object_init(&bo->tbo.ttm_resv);
379 locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock);
380 WARN_ON(!locked);
381 }
385 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 382 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
386 &bo->placement, page_align, !kernel, NULL, 383 &bo->placement, page_align, !kernel, NULL,
387 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 384 acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
388 if (unlikely(r != 0)) { 385 &amdgpu_ttm_bo_destroy);
386 if (unlikely(r != 0))
389 return r; 387 return r;
390 }
391 388
392 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 389 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
393 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 390 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
394 struct dma_fence *fence; 391 struct dma_fence *fence;
395 392
396 if (adev->mman.buffer_funcs_ring == NULL || 393 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
397 !adev->mman.buffer_funcs_ring->ready) { 394 if (unlikely(r))
398 r = -EBUSY;
399 goto fail_free;
400 }
401
402 r = amdgpu_bo_reserve(bo, false);
403 if (unlikely(r != 0))
404 goto fail_free;
405
406 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
407 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
408 if (unlikely(r != 0))
409 goto fail_unreserve; 395 goto fail_unreserve;
410 396
411 amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
412 amdgpu_bo_fence(bo, fence, false); 397 amdgpu_bo_fence(bo, fence, false);
413 amdgpu_bo_unreserve(bo);
414 dma_fence_put(bo->tbo.moving); 398 dma_fence_put(bo->tbo.moving);
415 bo->tbo.moving = dma_fence_get(fence); 399 bo->tbo.moving = dma_fence_get(fence);
416 dma_fence_put(fence); 400 dma_fence_put(fence);
417 } 401 }
402 if (!resv)
403 ww_mutex_unlock(&bo->tbo.resv->lock);
418 *bo_ptr = bo; 404 *bo_ptr = bo;
419 405
420 trace_amdgpu_bo_create(bo); 406 trace_amdgpu_bo_create(bo);
@@ -422,8 +408,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
422 return 0; 408 return 0;
423 409
424fail_unreserve: 410fail_unreserve:
425 amdgpu_bo_unreserve(bo); 411 ww_mutex_unlock(&bo->tbo.resv->lock);
426fail_free:
427 amdgpu_bo_unref(&bo); 412 amdgpu_bo_unref(&bo);
428 return r; 413 return r;
429} 414}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 274f3309aec9..723ae682bf25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -737,6 +737,21 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
737 return sprintf(buf, "%i\n", speed); 737 return sprintf(buf, "%i\n", speed);
738} 738}
739 739
740static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
741 struct device_attribute *attr,
742 char *buf)
743{
744 struct amdgpu_device *adev = dev_get_drvdata(dev);
745 int err;
746 u32 speed;
747
748 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
749 if (err)
750 return err;
751
752 return sprintf(buf, "%i\n", speed);
753}
754
740static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); 755static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
741static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 756static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
742static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 757static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
@@ -744,6 +759,7 @@ static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu
744static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 759static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
745static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 760static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
746static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 761static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
762static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
747 763
748static struct attribute *hwmon_attributes[] = { 764static struct attribute *hwmon_attributes[] = {
749 &sensor_dev_attr_temp1_input.dev_attr.attr, 765 &sensor_dev_attr_temp1_input.dev_attr.attr,
@@ -753,6 +769,7 @@ static struct attribute *hwmon_attributes[] = {
753 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 769 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
754 &sensor_dev_attr_pwm1_min.dev_attr.attr, 770 &sensor_dev_attr_pwm1_min.dev_attr.attr,
755 &sensor_dev_attr_pwm1_max.dev_attr.attr, 771 &sensor_dev_attr_pwm1_max.dev_attr.attr,
772 &sensor_dev_attr_fan1_input.dev_attr.attr,
756 NULL 773 NULL
757}; 774};
758 775
@@ -804,6 +821,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
804 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 821 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
805 return 0; 822 return 0;
806 823
824 /* requires powerplay */
825 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
826 return 0;
827
807 return effective_mode; 828 return effective_mode;
808} 829}
809 830
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index fa6baf31a35d..fc592c2b0e16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle)
155 ret = adev->powerplay.ip_funcs->sw_init( 155 ret = adev->powerplay.ip_funcs->sw_init(
156 adev->powerplay.pp_handle); 156 adev->powerplay.pp_handle);
157 157
158 if (adev->pp_enabled)
159 adev->pm.dpm_enabled = true;
160
161 return ret; 158 return ret;
162} 159}
163 160
@@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle)
187 ret = adev->powerplay.ip_funcs->hw_init( 184 ret = adev->powerplay.ip_funcs->hw_init(
188 adev->powerplay.pp_handle); 185 adev->powerplay.pp_handle);
189 186
187 if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
188 adev->pm.dpm_enabled = true;
189
190 return ret; 190 return ret;
191} 191}
192 192
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f2ad49c8e85b..574f0b79c690 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -44,7 +44,8 @@ enum amdgpu_ring_type {
44 AMDGPU_RING_TYPE_COMPUTE, 44 AMDGPU_RING_TYPE_COMPUTE,
45 AMDGPU_RING_TYPE_SDMA, 45 AMDGPU_RING_TYPE_SDMA,
46 AMDGPU_RING_TYPE_UVD, 46 AMDGPU_RING_TYPE_UVD,
47 AMDGPU_RING_TYPE_VCE 47 AMDGPU_RING_TYPE_VCE,
48 AMDGPU_RING_TYPE_KIQ
48}; 49};
49 50
50struct amdgpu_device; 51struct amdgpu_device;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 34a795463988..de9f919ae336 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -327,9 +327,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
327 return -EINVAL; 327 return -EINVAL;
328 328
329 *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL); 329 *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
330 if ((*sa_bo) == NULL) { 330 if (!(*sa_bo))
331 return -ENOMEM; 331 return -ENOMEM;
332 }
333 (*sa_bo)->manager = sa_manager; 332 (*sa_bo)->manager = sa_manager;
334 (*sa_bo)->fence = NULL; 333 (*sa_bo)->fence = NULL;
335 INIT_LIST_HEAD(&(*sa_bo)->olist); 334 INIT_LIST_HEAD(&(*sa_bo)->olist);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 1821c05484d0..8f18b8ed2b3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1382,28 +1382,40 @@ error_free:
1382} 1382}
1383 1383
1384int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1384int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1385 uint32_t src_data, 1385 uint32_t src_data,
1386 struct reservation_object *resv, 1386 struct reservation_object *resv,
1387 struct dma_fence **fence) 1387 struct dma_fence **fence)
1388{ 1388{
1389 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1389 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1390 struct amdgpu_job *job; 1390 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1391 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1391 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1392 1392
1393 uint32_t max_bytes, byte_count; 1393 struct drm_mm_node *mm_node;
1394 uint64_t dst_offset; 1394 unsigned long num_pages;
1395 unsigned int num_loops, num_dw; 1395 unsigned int num_loops, num_dw;
1396 unsigned int i; 1396
1397 struct amdgpu_job *job;
1397 int r; 1398 int r;
1398 1399
1399 byte_count = bo->tbo.num_pages << PAGE_SHIFT; 1400 if (!ring->ready) {
1400 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1401 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1401 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1402 return -EINVAL;
1403 }
1404
1405 num_pages = bo->tbo.num_pages;
1406 mm_node = bo->tbo.mem.mm_node;
1407 num_loops = 0;
1408 while (num_pages) {
1409 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1410
1411 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1412 num_pages -= mm_node->size;
1413 ++mm_node;
1414 }
1402 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1415 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1403 1416
1404 /* for IB padding */ 1417 /* for IB padding */
1405 while (num_dw & 0x7) 1418 num_dw += 64;
1406 num_dw++;
1407 1419
1408 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1420 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1409 if (r) 1421 if (r)
@@ -1411,28 +1423,43 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1411 1423
1412 if (resv) { 1424 if (resv) {
1413 r = amdgpu_sync_resv(adev, &job->sync, resv, 1425 r = amdgpu_sync_resv(adev, &job->sync, resv,
1414 AMDGPU_FENCE_OWNER_UNDEFINED); 1426 AMDGPU_FENCE_OWNER_UNDEFINED);
1415 if (r) { 1427 if (r) {
1416 DRM_ERROR("sync failed (%d).\n", r); 1428 DRM_ERROR("sync failed (%d).\n", r);
1417 goto error_free; 1429 goto error_free;
1418 } 1430 }
1419 } 1431 }
1420 1432
1421 dst_offset = bo->tbo.mem.start << PAGE_SHIFT; 1433 num_pages = bo->tbo.num_pages;
1422 for (i = 0; i < num_loops; i++) { 1434 mm_node = bo->tbo.mem.mm_node;
1423 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1424 1435
1425 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 1436 while (num_pages) {
1426 dst_offset, cur_size_in_bytes); 1437 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1438 uint64_t dst_addr;
1427 1439
1428 dst_offset += cur_size_in_bytes; 1440 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1429 byte_count -= cur_size_in_bytes; 1441 &bo->tbo.mem, &dst_addr);
1442 if (r)
1443 return r;
1444
1445 while (byte_count) {
1446 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1447
1448 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1449 dst_addr, cur_size_in_bytes);
1450
1451 dst_addr += cur_size_in_bytes;
1452 byte_count -= cur_size_in_bytes;
1453 }
1454
1455 num_pages -= mm_node->size;
1456 ++mm_node;
1430 } 1457 }
1431 1458
1432 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1459 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1433 WARN_ON(job->ibs[0].length_dw > num_dw); 1460 WARN_ON(job->ibs[0].length_dw > num_dw);
1434 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1461 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1435 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1462 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1436 if (r) 1463 if (r)
1437 goto error_free; 1464 goto error_free;
1438 1465
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index fb270c7e7171..a81dfaeeb8c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -360,6 +360,18 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
360 } 360 }
361} 361}
362 362
363static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
364{
365 uint32_t lo, hi;
366 uint64_t addr;
367
368 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
369 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
370 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
371
372 return addr;
373}
374
363/** 375/**
364 * amdgpu_uvd_cs_pass1 - first parsing round 376 * amdgpu_uvd_cs_pass1 - first parsing round
365 * 377 *
@@ -372,14 +384,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
372{ 384{
373 struct amdgpu_bo_va_mapping *mapping; 385 struct amdgpu_bo_va_mapping *mapping;
374 struct amdgpu_bo *bo; 386 struct amdgpu_bo *bo;
375 uint32_t cmd, lo, hi; 387 uint32_t cmd;
376 uint64_t addr; 388 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
377 int r = 0; 389 int r = 0;
378 390
379 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
380 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
381 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
382
383 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 391 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
384 if (mapping == NULL) { 392 if (mapping == NULL) {
385 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 393 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
@@ -698,18 +706,16 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
698{ 706{
699 struct amdgpu_bo_va_mapping *mapping; 707 struct amdgpu_bo_va_mapping *mapping;
700 struct amdgpu_bo *bo; 708 struct amdgpu_bo *bo;
701 uint32_t cmd, lo, hi; 709 uint32_t cmd;
702 uint64_t start, end; 710 uint64_t start, end;
703 uint64_t addr; 711 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
704 int r; 712 int r;
705 713
706 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
707 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
708 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
709
710 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 714 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
711 if (mapping == NULL) 715 if (mapping == NULL) {
716 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
712 return -EINVAL; 717 return -EINVAL;
718 }
713 719
714 start = amdgpu_bo_gpu_offset(bo); 720 start = amdgpu_bo_gpu_offset(bo);
715 721
@@ -893,10 +899,13 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
893 ctx.buf_sizes = buf_sizes; 899 ctx.buf_sizes = buf_sizes;
894 ctx.ib_idx = ib_idx; 900 ctx.ib_idx = ib_idx;
895 901
896 /* first round, make sure the buffers are actually in the UVD segment */ 902 /* first round only required on chips without UVD 64 bit address support */
897 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 903 if (!parser->adev->uvd.address_64_bit) {
898 if (r) 904 /* first round, make sure the buffers are actually in the UVD segment */
899 return r; 905 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
906 if (r)
907 return r;
908 }
900 909
901 /* second round, patch buffer addresses into the command stream */ 910 /* second round, patch buffer addresses into the command stream */
902 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 911 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 337c5b31d18d..1dda9321bd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -530,70 +530,6 @@ static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
530} 530}
531 531
532/** 532/**
533 * amdgpu_vm_clear_bo - initially clear the page dir/table
534 *
535 * @adev: amdgpu_device pointer
536 * @bo: bo to clear
537 *
538 * need to reserve bo first before calling it.
539 */
540static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
541 struct amdgpu_vm *vm,
542 struct amdgpu_bo *bo)
543{
544 struct amdgpu_ring *ring;
545 struct dma_fence *fence = NULL;
546 struct amdgpu_job *job;
547 struct amdgpu_pte_update_params params;
548 unsigned entries;
549 uint64_t addr;
550 int r;
551
552 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
553
554 r = reservation_object_reserve_shared(bo->tbo.resv);
555 if (r)
556 return r;
557
558 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
559 if (r)
560 goto error;
561
562 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
563 if (r)
564 goto error;
565
566 addr = amdgpu_bo_gpu_offset(bo);
567 entries = amdgpu_bo_size(bo) / 8;
568
569 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
570 if (r)
571 goto error;
572
573 memset(&params, 0, sizeof(params));
574 params.adev = adev;
575 params.ib = &job->ibs[0];
576 amdgpu_vm_do_set_ptes(&params, addr, 0, entries, 0, 0);
577 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
578
579 WARN_ON(job->ibs[0].length_dw > 64);
580 r = amdgpu_job_submit(job, ring, &vm->entity,
581 AMDGPU_FENCE_OWNER_VM, &fence);
582 if (r)
583 goto error_free;
584
585 amdgpu_bo_fence(bo, fence, true);
586 dma_fence_put(fence);
587 return 0;
588
589error_free:
590 amdgpu_job_free(job);
591
592error:
593 return r;
594}
595
596/**
597 * amdgpu_vm_map_gart - Resolve gart mapping of addr 533 * amdgpu_vm_map_gart - Resolve gart mapping of addr
598 * 534 *
599 * @pages_addr: optional DMA address to use for lookup 535 * @pages_addr: optional DMA address to use for lookup
@@ -1435,7 +1371,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1435 AMDGPU_GEM_DOMAIN_VRAM, 1371 AMDGPU_GEM_DOMAIN_VRAM,
1436 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 1372 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
1437 AMDGPU_GEM_CREATE_SHADOW | 1373 AMDGPU_GEM_CREATE_SHADOW |
1438 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1374 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1375 AMDGPU_GEM_CREATE_VRAM_CLEARED,
1439 NULL, resv, &pt); 1376 NULL, resv, &pt);
1440 if (r) 1377 if (r)
1441 goto error_free; 1378 goto error_free;
@@ -1445,22 +1382,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1445 */ 1382 */
1446 pt->parent = amdgpu_bo_ref(vm->page_directory); 1383 pt->parent = amdgpu_bo_ref(vm->page_directory);
1447 1384
1448 r = amdgpu_vm_clear_bo(adev, vm, pt);
1449 if (r) {
1450 amdgpu_bo_unref(&pt->shadow);
1451 amdgpu_bo_unref(&pt);
1452 goto error_free;
1453 }
1454
1455 if (pt->shadow) {
1456 r = amdgpu_vm_clear_bo(adev, vm, pt->shadow);
1457 if (r) {
1458 amdgpu_bo_unref(&pt->shadow);
1459 amdgpu_bo_unref(&pt);
1460 goto error_free;
1461 }
1462 }
1463
1464 vm->page_tables[pt_idx].bo = pt; 1385 vm->page_tables[pt_idx].bo = pt;
1465 vm->page_tables[pt_idx].addr = 0; 1386 vm->page_tables[pt_idx].addr = 0;
1466 } 1387 }
@@ -1642,7 +1563,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1642 AMDGPU_GEM_DOMAIN_VRAM, 1563 AMDGPU_GEM_DOMAIN_VRAM,
1643 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 1564 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
1644 AMDGPU_GEM_CREATE_SHADOW | 1565 AMDGPU_GEM_CREATE_SHADOW |
1645 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1566 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1567 AMDGPU_GEM_CREATE_VRAM_CLEARED,
1646 NULL, NULL, &vm->page_directory); 1568 NULL, NULL, &vm->page_directory);
1647 if (r) 1569 if (r)
1648 goto error_free_sched_entity; 1570 goto error_free_sched_entity;
@@ -1651,24 +1573,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1651 if (r) 1573 if (r)
1652 goto error_free_page_directory; 1574 goto error_free_page_directory;
1653 1575
1654 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
1655 if (r)
1656 goto error_unreserve;
1657
1658 if (vm->page_directory->shadow) {
1659 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory->shadow);
1660 if (r)
1661 goto error_unreserve;
1662 }
1663
1664 vm->last_eviction_counter = atomic64_read(&adev->num_evictions); 1576 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
1665 amdgpu_bo_unreserve(vm->page_directory); 1577 amdgpu_bo_unreserve(vm->page_directory);
1666 1578
1667 return 0; 1579 return 0;
1668 1580
1669error_unreserve:
1670 amdgpu_bo_unreserve(vm->page_directory);
1671
1672error_free_page_directory: 1581error_free_page_directory:
1673 amdgpu_bo_unref(&vm->page_directory->shadow); 1582 amdgpu_bo_unref(&vm->page_directory->shadow);
1674 amdgpu_bo_unref(&vm->page_directory); 1583 amdgpu_bo_unref(&vm->page_directory);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 180eed7c8bca..d710226a0fff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -108,7 +108,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man,
108 lpfn = man->size; 108 lpfn = man->size;
109 109
110 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS || 110 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS ||
111 amdgpu_vram_page_split == -1) { 111 place->lpfn || amdgpu_vram_page_split == -1) {
112 pages_per_node = ~0ul; 112 pages_per_node = ~0ul;
113 num_nodes = 1; 113 num_nodes = 1;
114 } else { 114 } else {
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1caff75ab9fc..1027f92de32b 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4202 4202
4203 if (!gate) { 4203 if (!gate) {
4204 /* turn the clocks on when decoding */ 4204 /* turn the clocks on when decoding */
4205 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
4206 AMD_CG_STATE_UNGATE);
4207 if (ret)
4208 return ret;
4209
4210 if (pi->caps_uvd_dpm || 4205 if (pi->caps_uvd_dpm ||
4211 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 4206 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4212 pi->smc_state_table.UvdBootLevel = 0; 4207 pi->smc_state_table.UvdBootLevel = 0;
@@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4223 ret = ci_enable_uvd_dpm(adev, false); 4218 ret = ci_enable_uvd_dpm(adev, false);
4224 if (ret) 4219 if (ret)
4225 return ret; 4220 return ret;
4226
4227 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
4228 AMD_CG_STATE_GATE);
4229 } 4221 }
4230 4222
4231 return ret; 4223 return ret;
@@ -5896,7 +5888,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
5896 pi->pcie_dpm_key_disabled = 0; 5888 pi->pcie_dpm_key_disabled = 0;
5897 pi->thermal_sclk_dpm_enabled = 0; 5889 pi->thermal_sclk_dpm_enabled = 0;
5898 5890
5899 if (amdgpu_sclk_deep_sleep_en) 5891 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
5900 pi->caps_sclk_ds = true; 5892 pi->caps_sclk_ds = true;
5901 else 5893 else
5902 pi->caps_sclk_ds = false; 5894 pi->caps_sclk_ds = false;
@@ -5999,7 +5991,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
5999 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK; 5991 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
6000 break; 5992 break;
6001 default: 5993 default:
6002 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift); 5994 DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
6003 break; 5995 break;
6004 } 5996 }
6005 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp); 5997 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 352b5fad5a06..ba2b66be9022 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev)
438 pi->caps_td_ramping = true; 438 pi->caps_td_ramping = true;
439 pi->caps_tcp_ramping = true; 439 pi->caps_tcp_ramping = true;
440 } 440 }
441 if (amdgpu_sclk_deep_sleep_en) 441 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
442 pi->caps_sclk_ds = true; 442 pi->caps_sclk_ds = true;
443 else 443 else
444 pi->caps_sclk_ds = false; 444 pi->caps_sclk_ds = false;
@@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
2111 2111
2112 if (gate) { 2112 if (gate) {
2113 if (pi->caps_uvd_pg) { 2113 if (pi->caps_uvd_pg) {
2114 /* disable clockgating so we can properly shut down the block */
2115 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 2114 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2116 AMD_CG_STATE_UNGATE); 2115 AMD_CG_STATE_GATE);
2117 if (ret) { 2116 if (ret) {
2118 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n"); 2117 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
2119 return; 2118 return;
@@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
2159 return; 2158 return;
2160 } 2159 }
2161 2160
2162 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
2163 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 2161 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2164 AMD_CG_STATE_GATE); 2162 AMD_CG_STATE_UNGATE);
2165 if (ret) { 2163 if (ret) {
2166 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n"); 2164 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
2167 return; 2165 return;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 65a954cb69ed..075aa0b1b075 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3749,7 +3749,6 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3749 .bandwidth_update = &dce_v10_0_bandwidth_update, 3749 .bandwidth_update = &dce_v10_0_bandwidth_update,
3750 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3750 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3751 .vblank_wait = &dce_v10_0_vblank_wait, 3751 .vblank_wait = &dce_v10_0_vblank_wait,
3752 .is_display_hung = &dce_v10_0_is_display_hung,
3753 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3752 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3754 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3753 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3755 .hpd_sense = &dce_v10_0_hpd_sense, 3754 .hpd_sense = &dce_v10_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index d807e876366b..a6717487ac78 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3805,7 +3805,6 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3805 .bandwidth_update = &dce_v11_0_bandwidth_update, 3805 .bandwidth_update = &dce_v11_0_bandwidth_update,
3806 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3806 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3807 .vblank_wait = &dce_v11_0_vblank_wait, 3807 .vblank_wait = &dce_v11_0_vblank_wait,
3808 .is_display_hung = &dce_v11_0_is_display_hung,
3809 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3808 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3810 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3809 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3811 .hpd_sense = &dce_v11_0_hpd_sense, 3810 .hpd_sense = &dce_v11_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bc9f2f423270..15d98ef696a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -30,8 +30,19 @@
30#include "atombios_encoders.h" 30#include "atombios_encoders.h"
31#include "amdgpu_pll.h" 31#include "amdgpu_pll.h"
32#include "amdgpu_connectors.h" 32#include "amdgpu_connectors.h"
33#include "si/si_reg.h" 33
34#include "si/sid.h" 34#include "bif/bif_3_0_d.h"
35#include "bif/bif_3_0_sh_mask.h"
36#include "oss/oss_1_0_d.h"
37#include "oss/oss_1_0_sh_mask.h"
38#include "gca/gfx_6_0_d.h"
39#include "gca/gfx_6_0_sh_mask.h"
40#include "gmc/gmc_6_0_d.h"
41#include "gmc/gmc_6_0_sh_mask.h"
42#include "dce/dce_6_0_d.h"
43#include "dce/dce_6_0_sh_mask.h"
44#include "gca/gfx_7_2_enum.h"
45#include "si_enums.h"
35 46
36static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 47static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
37static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 48static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -48,12 +59,12 @@ static const u32 crtc_offsets[6] =
48 59
49static const u32 hpd_offsets[] = 60static const u32 hpd_offsets[] =
50{ 61{
51 DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS, 62 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
52 DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS, 63 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
53 DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS, 64 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
54 DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS, 65 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
55 DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS, 66 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
56 DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS, 67 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
57}; 68};
58 69
59static const uint32_t dig_offsets[] = { 70static const uint32_t dig_offsets[] = {
@@ -73,32 +84,32 @@ static const struct {
73 uint32_t hpd; 84 uint32_t hpd;
74 85
75} interrupt_status_offsets[6] = { { 86} interrupt_status_offsets[6] = { {
76 .reg = DISP_INTERRUPT_STATUS, 87 .reg = mmDISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
80}, { 91}, {
81 .reg = DISP_INTERRUPT_STATUS_CONTINUE, 92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
85}, { 96}, {
86 .reg = DISP_INTERRUPT_STATUS_CONTINUE2, 97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
90}, { 101}, {
91 .reg = DISP_INTERRUPT_STATUS_CONTINUE3, 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
95}, { 106}, {
96 .reg = DISP_INTERRUPT_STATUS_CONTINUE4, 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
100}, { 111}, {
101 .reg = DISP_INTERRUPT_STATUS_CONTINUE5, 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
@@ -119,7 +130,7 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
119 130
120static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 131static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
121{ 132{
122 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) 133 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
123 return true; 134 return true;
124 else 135 else
125 return false; 136 return false;
@@ -129,8 +140,8 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
129{ 140{
130 u32 pos1, pos2; 141 u32 pos1, pos2;
131 142
132 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 143 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
133 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 144 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
134 145
135 if (pos1 != pos2) 146 if (pos1 != pos2)
136 return true; 147 return true;
@@ -152,7 +163,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
152 if (crtc >= adev->mode_info.num_crtc) 163 if (crtc >= adev->mode_info.num_crtc)
153 return; 164 return;
154 165
155 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) 166 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
156 return; 167 return;
157 168
158 /* depending on when we hit vblank, we may be close to active; if so, 169 /* depending on when we hit vblank, we may be close to active; if so,
@@ -180,7 +191,7 @@ static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
180 if (crtc >= adev->mode_info.num_crtc) 191 if (crtc >= adev->mode_info.num_crtc)
181 return 0; 192 return 0;
182 else 193 else
183 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 194 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
184} 195}
185 196
186static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 197static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
@@ -220,16 +231,16 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
220 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 231 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
221 232
222 /* flip at hsync for async, default is vsync */ 233 /* flip at hsync for async, default is vsync */
223 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 234 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
224 EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); 235 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
225 /* update the scanout addresses */ 236 /* update the scanout addresses */
226 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 237 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
227 upper_32_bits(crtc_base)); 238 upper_32_bits(crtc_base));
228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 239 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
229 (u32)crtc_base); 240 (u32)crtc_base);
230 241
231 /* post the write */ 242 /* post the write */
232 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 243 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
233} 244}
234 245
235static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 246static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -237,8 +248,8 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
237{ 248{
238 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 249 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
239 return -EINVAL; 250 return -EINVAL;
240 *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]); 251 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
241 *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 252 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
242 253
243 return 0; 254 return 0;
244 255
@@ -261,7 +272,7 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
261 if (hpd >= adev->mode_info.num_hpd) 272 if (hpd >= adev->mode_info.num_hpd)
262 return connected; 273 return connected;
263 274
264 if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE) 275 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
265 connected = true; 276 connected = true;
266 277
267 return connected; 278 return connected;
@@ -284,12 +295,12 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
284 if (hpd >= adev->mode_info.num_hpd) 295 if (hpd >= adev->mode_info.num_hpd)
285 return; 296 return;
286 297
287 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 298 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
288 if (connected) 299 if (connected)
289 tmp &= ~DC_HPDx_INT_POLARITY; 300 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
290 else 301 else
291 tmp |= DC_HPDx_INT_POLARITY; 302 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
292 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 303 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
293} 304}
294 305
295/** 306/**
@@ -312,9 +323,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
312 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 323 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
313 continue; 324 continue;
314 325
315 tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 326 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
316 tmp |= DC_HPDx_EN; 327 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
317 WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 328 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
318 329
319 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 330 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
320 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 331 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
@@ -323,9 +334,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
323 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 334 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
324 * also avoid interrupt storms during dpms. 335 * also avoid interrupt storms during dpms.
325 */ 336 */
326 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 337 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
327 tmp &= ~DC_HPDx_INT_EN; 338 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
328 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 339 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
329 continue; 340 continue;
330 } 341 }
331 342
@@ -355,9 +366,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
355 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 366 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
356 continue; 367 continue;
357 368
358 tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 369 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
359 tmp &= ~DC_HPDx_EN; 370 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
360 WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 371 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
361 372
362 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 373 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
363 } 374 }
@@ -365,14 +376,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
365 376
366static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 377static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
367{ 378{
368 return SI_DC_GPIO_HPD_A; 379 return mmDC_GPIO_HPD_A;
369}
370
371static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
372{
373 DRM_INFO("xxxx: dce_v6_0_is_display_hung ----no imp!!!!!\n");
374
375 return true;
376} 380}
377 381
378static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) 382static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
@@ -380,7 +384,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
380 if (crtc >= adev->mode_info.num_crtc) 384 if (crtc >= adev->mode_info.num_crtc)
381 return 0; 385 return 0;
382 else 386 else
383 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 387 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
384} 388}
385 389
386static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, 390static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
@@ -389,25 +393,25 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
389 u32 crtc_enabled, tmp, frame_count; 393 u32 crtc_enabled, tmp, frame_count;
390 int i, j; 394 int i, j;
391 395
392 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 396 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
393 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 397 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
394 398
395 /* disable VGA render */ 399 /* disable VGA render */
396 WREG32(VGA_RENDER_CONTROL, 0); 400 WREG32(mmVGA_RENDER_CONTROL, 0);
397 401
398 /* blank the display controllers */ 402 /* blank the display controllers */
399 for (i = 0; i < adev->mode_info.num_crtc; i++) { 403 for (i = 0; i < adev->mode_info.num_crtc; i++) {
400 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; 404 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
401 if (crtc_enabled) { 405 if (crtc_enabled) {
402 save->crtc_enabled[i] = true; 406 save->crtc_enabled[i] = true;
403 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 407 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
404 408
405 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { 409 if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
406 dce_v6_0_vblank_wait(adev, i); 410 dce_v6_0_vblank_wait(adev, i);
407 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 411 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
408 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 412 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
409 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 413 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
410 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
411 } 415 }
412 /* wait for the next frame */ 416 /* wait for the next frame */
413 frame_count = evergreen_get_vblank_counter(adev, i); 417 frame_count = evergreen_get_vblank_counter(adev, i);
@@ -418,11 +422,11 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
418 } 422 }
419 423
420 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 424 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
421 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 425 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
422 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 426 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
423 tmp &= ~EVERGREEN_CRTC_MASTER_EN; 427 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
424 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 428 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
425 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 429 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
426 save->crtc_enabled[i] = false; 430 save->crtc_enabled[i] = false;
427 /* ***** */ 431 /* ***** */
428 } else { 432 } else {
@@ -439,41 +443,41 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
439 443
440 /* update crtc base addresses */ 444 /* update crtc base addresses */
441 for (i = 0; i < adev->mode_info.num_crtc; i++) { 445 for (i = 0; i < adev->mode_info.num_crtc; i++) {
442 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 446 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
443 upper_32_bits(adev->mc.vram_start)); 447 upper_32_bits(adev->mc.vram_start));
444 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 448 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
445 upper_32_bits(adev->mc.vram_start)); 449 upper_32_bits(adev->mc.vram_start));
446 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 450 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
447 (u32)adev->mc.vram_start); 451 (u32)adev->mc.vram_start);
448 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 452 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
449 (u32)adev->mc.vram_start); 453 (u32)adev->mc.vram_start);
450 } 454 }
451 455
452 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 456 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
453 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); 457 WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
454 458
455 /* unlock regs and wait for update */ 459 /* unlock regs and wait for update */
456 for (i = 0; i < adev->mode_info.num_crtc; i++) { 460 for (i = 0; i < adev->mode_info.num_crtc; i++) {
457 if (save->crtc_enabled[i]) { 461 if (save->crtc_enabled[i]) {
458 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); 462 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
459 if ((tmp & 0x7) != 3) { 463 if ((tmp & 0x7) != 3) {
460 tmp &= ~0x7; 464 tmp &= ~0x7;
461 tmp |= 0x3; 465 tmp |= 0x3;
462 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 466 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
463 } 467 }
464 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 468 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
465 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { 469 if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
466 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 470 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
467 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); 471 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
468 } 472 }
469 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); 473 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
470 if (tmp & 1) { 474 if (tmp & 1) {
471 tmp &= ~1; 475 tmp &= ~1;
472 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 476 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
473 } 477 }
474 for (j = 0; j < adev->usec_timeout; j++) { 478 for (j = 0; j < adev->usec_timeout; j++) {
475 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 479 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
476 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) 480 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
477 break; 481 break;
478 udelay(1); 482 udelay(1);
479 } 483 }
@@ -481,9 +485,9 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
481 } 485 }
482 486
483 /* Unlock vga access */ 487 /* Unlock vga access */
484 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 488 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
485 mdelay(1); 489 mdelay(1);
486 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 490 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
487 491
488} 492}
489 493
@@ -491,8 +495,8 @@ static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
491 bool render) 495 bool render)
492{ 496{
493 if (!render) 497 if (!render)
494 WREG32(R_000300_VGA_RENDER_CONTROL, 498 WREG32(mmVGA_RENDER_CONTROL,
495 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 499 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
496 500
497} 501}
498 502
@@ -526,14 +530,14 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev)
526 530
527 /*Disable crtc*/ 531 /*Disable crtc*/
528 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 532 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
529 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & 533 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
530 EVERGREEN_CRTC_MASTER_EN; 534 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
531 if (crtc_enabled) { 535 if (crtc_enabled) {
532 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 537 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
534 tmp &= ~EVERGREEN_CRTC_MASTER_EN; 538 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
535 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 539 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 540 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 } 541 }
538 } 542 }
539 } 543 }
@@ -569,19 +573,23 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
569 case 6: 573 case 6:
570 if (dither == AMDGPU_FMT_DITHER_ENABLE) 574 if (dither == AMDGPU_FMT_DITHER_ENABLE)
571 /* XXX sort out optimal dither settings */ 575 /* XXX sort out optimal dither settings */
572 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | 576 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
573 FMT_SPATIAL_DITHER_EN); 577 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
578 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
574 else 579 else
575 tmp |= FMT_TRUNCATE_EN; 580 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
576 break; 581 break;
577 case 8: 582 case 8:
578 if (dither == AMDGPU_FMT_DITHER_ENABLE) 583 if (dither == AMDGPU_FMT_DITHER_ENABLE)
579 /* XXX sort out optimal dither settings */ 584 /* XXX sort out optimal dither settings */
580 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | 585 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
581 FMT_RGB_RANDOM_ENABLE | 586 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
582 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 587 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
588 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
589 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
583 else 590 else
584 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 591 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
592 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
585 break; 593 break;
586 case 10: 594 case 10:
587 default: 595 default:
@@ -589,7 +597,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
589 break; 597 break;
590 } 598 }
591 599
592 WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 600 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
593} 601}
594 602
595/** 603/**
@@ -603,7 +611,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
603 */ 611 */
604static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 612static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
605{ 613{
606 u32 tmp = RREG32(MC_SHARED_CHMAP); 614 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
607 615
608 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 616 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
609 case 0: 617 case 0:
@@ -1100,28 +1108,28 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
1100 } 1108 }
1101 1109
1102 /* select wm A */ 1110 /* select wm A */
1103 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1111 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1104 tmp = arb_control3; 1112 tmp = arb_control3;
1105 tmp &= ~LATENCY_WATERMARK_MASK(3); 1113 tmp &= ~LATENCY_WATERMARK_MASK(3);
1106 tmp |= LATENCY_WATERMARK_MASK(1); 1114 tmp |= LATENCY_WATERMARK_MASK(1);
1107 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1115 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1108 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, 1116 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1109 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 1117 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1110 LATENCY_HIGH_WATERMARK(line_time))); 1118 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1111 /* select wm B */ 1119 /* select wm B */
1112 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1120 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1113 tmp &= ~LATENCY_WATERMARK_MASK(3); 1121 tmp &= ~LATENCY_WATERMARK_MASK(3);
1114 tmp |= LATENCY_WATERMARK_MASK(2); 1122 tmp |= LATENCY_WATERMARK_MASK(2);
1115 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1123 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1116 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, 1124 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1117 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 1125 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1118 LATENCY_HIGH_WATERMARK(line_time))); 1126 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1119 /* restore original selection */ 1127 /* restore original selection */
1120 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1128 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1121 1129
1122 /* write the priority marks */ 1130 /* write the priority marks */
1123 WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1131 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1124 WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1132 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1125 1133
1126 /* save values for DPM */ 1134 /* save values for DPM */
1127 amdgpu_crtc->line_time = line_time; 1135 amdgpu_crtc->line_time = line_time;
@@ -1139,7 +1147,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1139 /* 1147 /*
1140 * Line Buffer Setup 1148 * Line Buffer Setup
1141 * There are 3 line buffers, each one shared by 2 display controllers. 1149 * There are 3 line buffers, each one shared by 2 display controllers.
1142 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1150 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1143 * the display controllers. The paritioning is done via one of four 1151 * the display controllers. The paritioning is done via one of four
1144 * preset allocations specified in bits 21:20: 1152 * preset allocations specified in bits 21:20:
1145 * 0 - half lb 1153 * 0 - half lb
@@ -1162,14 +1170,14 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1162 buffer_alloc = 0; 1170 buffer_alloc = 0;
1163 } 1171 }
1164 1172
1165 WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1173 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1166 DC_LB_MEMORY_CONFIG(tmp)); 1174 DC_LB_MEMORY_CONFIG(tmp));
1167 1175
1168 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1176 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1169 DMIF_BUFFERS_ALLOCATED(buffer_alloc)); 1177 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1170 for (i = 0; i < adev->usec_timeout; i++) { 1178 for (i = 0; i < adev->usec_timeout; i++) {
1171 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1179 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1172 DMIF_BUFFERS_ALLOCATED_COMPLETED) 1180 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1173 break; 1181 break;
1174 udelay(1); 1182 udelay(1);
1175 } 1183 }
@@ -1411,12 +1419,12 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1411 1419
1412static const u32 vga_control_regs[6] = 1420static const u32 vga_control_regs[6] =
1413{ 1421{
1414 AVIVO_D1VGA_CONTROL, 1422 mmD1VGA_CONTROL,
1415 AVIVO_D2VGA_CONTROL, 1423 mmD2VGA_CONTROL,
1416 EVERGREEN_D3VGA_CONTROL, 1424 mmD3VGA_CONTROL,
1417 EVERGREEN_D4VGA_CONTROL, 1425 mmD4VGA_CONTROL,
1418 EVERGREEN_D5VGA_CONTROL, 1426 mmD5VGA_CONTROL,
1419 EVERGREEN_D6VGA_CONTROL, 1427 mmD6VGA_CONTROL,
1420}; 1428};
1421 1429
1422static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1430static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
@@ -1436,7 +1444,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1436 struct drm_device *dev = crtc->dev; 1444 struct drm_device *dev = crtc->dev;
1437 struct amdgpu_device *adev = dev->dev_private; 1445 struct amdgpu_device *adev = dev->dev_private;
1438 1446
1439 WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1447 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1440} 1448}
1441 1449
1442static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1450static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
@@ -1452,7 +1460,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1452 struct amdgpu_bo *abo; 1460 struct amdgpu_bo *abo;
1453 uint64_t fb_location, tiling_flags; 1461 uint64_t fb_location, tiling_flags;
1454 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1462 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1455 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1463 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1456 u32 viewport_w, viewport_h; 1464 u32 viewport_w, viewport_h;
1457 int r; 1465 int r;
1458 bool bypass_lut = false; 1466 bool bypass_lut = false;
@@ -1496,64 +1504,64 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1496 1504
1497 switch (target_fb->pixel_format) { 1505 switch (target_fb->pixel_format) {
1498 case DRM_FORMAT_C8: 1506 case DRM_FORMAT_C8:
1499 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1507 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1500 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1508 GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1501 break; 1509 break;
1502 case DRM_FORMAT_XRGB4444: 1510 case DRM_FORMAT_XRGB4444:
1503 case DRM_FORMAT_ARGB4444: 1511 case DRM_FORMAT_ARGB4444:
1504 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1512 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1505 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1513 GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1506#ifdef __BIG_ENDIAN 1514#ifdef __BIG_ENDIAN
1507 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1515 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1508#endif 1516#endif
1509 break; 1517 break;
1510 case DRM_FORMAT_XRGB1555: 1518 case DRM_FORMAT_XRGB1555:
1511 case DRM_FORMAT_ARGB1555: 1519 case DRM_FORMAT_ARGB1555:
1512 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1520 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1513 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1521 GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1514#ifdef __BIG_ENDIAN 1522#ifdef __BIG_ENDIAN
1515 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1523 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1516#endif 1524#endif
1517 break; 1525 break;
1518 case DRM_FORMAT_BGRX5551: 1526 case DRM_FORMAT_BGRX5551:
1519 case DRM_FORMAT_BGRA5551: 1527 case DRM_FORMAT_BGRA5551:
1520 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1528 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1521 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1529 GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1522#ifdef __BIG_ENDIAN 1530#ifdef __BIG_ENDIAN
1523 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1531 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1524#endif 1532#endif
1525 break; 1533 break;
1526 case DRM_FORMAT_RGB565: 1534 case DRM_FORMAT_RGB565:
1527 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1535 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1528 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1536 GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1529#ifdef __BIG_ENDIAN 1537#ifdef __BIG_ENDIAN
1530 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1538 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1531#endif 1539#endif
1532 break; 1540 break;
1533 case DRM_FORMAT_XRGB8888: 1541 case DRM_FORMAT_XRGB8888:
1534 case DRM_FORMAT_ARGB8888: 1542 case DRM_FORMAT_ARGB8888:
1535 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1543 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1536 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1544 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1537#ifdef __BIG_ENDIAN 1545#ifdef __BIG_ENDIAN
1538 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1546 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1539#endif 1547#endif
1540 break; 1548 break;
1541 case DRM_FORMAT_XRGB2101010: 1549 case DRM_FORMAT_XRGB2101010:
1542 case DRM_FORMAT_ARGB2101010: 1550 case DRM_FORMAT_ARGB2101010:
1543 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1551 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1544 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1552 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1545#ifdef __BIG_ENDIAN 1553#ifdef __BIG_ENDIAN
1546 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1554 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1547#endif 1555#endif
1548 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1556 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1549 bypass_lut = true; 1557 bypass_lut = true;
1550 break; 1558 break;
1551 case DRM_FORMAT_BGRX1010102: 1559 case DRM_FORMAT_BGRX1010102:
1552 case DRM_FORMAT_BGRA1010102: 1560 case DRM_FORMAT_BGRA1010102:
1553 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1561 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1554 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1562 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1555#ifdef __BIG_ENDIAN 1563#ifdef __BIG_ENDIAN
1556 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1564 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1557#endif 1565#endif
1558 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1566 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1559 bypass_lut = true; 1567 bypass_lut = true;
@@ -1573,75 +1581,75 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1573 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1581 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1574 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1582 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1575 1583
1576 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1584 fb_format |= GRPH_NUM_BANKS(num_banks);
1577 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1585 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1578 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1586 fb_format |= GRPH_TILE_SPLIT(tile_split);
1579 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1587 fb_format |= GRPH_BANK_WIDTH(bankw);
1580 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1588 fb_format |= GRPH_BANK_HEIGHT(bankh);
1581 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1589 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1582 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1590 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1583 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1591 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1584 } 1592 }
1585 1593
1586 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1594 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1587 fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config); 1595 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1588 1596
1589 dce_v6_0_vga_enable(crtc, false); 1597 dce_v6_0_vga_enable(crtc, false);
1590 1598
1591 /* Make sure surface address is updated at vertical blank rather than 1599 /* Make sure surface address is updated at vertical blank rather than
1592 * horizontal blank 1600 * horizontal blank
1593 */ 1601 */
1594 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 1602 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1595 1603
1596 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1604 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1597 upper_32_bits(fb_location)); 1605 upper_32_bits(fb_location));
1598 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1606 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1599 upper_32_bits(fb_location)); 1607 upper_32_bits(fb_location));
1600 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1608 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1601 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1609 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1602 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1610 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1603 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1611 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1604 WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1612 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1605 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap); 1613 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1606 1614
1607 /* 1615 /*
1608 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1616 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1609 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1617 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1610 * retain the full precision throughout the pipeline. 1618 * retain the full precision throughout the pipeline.
1611 */ 1619 */
1612 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, 1620 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1613 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1621 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1614 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1622 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1615 1623
1616 if (bypass_lut) 1624 if (bypass_lut)
1617 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1625 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1618 1626
1619 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 1627 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1620 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 1628 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1621 WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0); 1629 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1622 WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 1630 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1623 WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 1631 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1624 WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 1632 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1625 1633
1626 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1634 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1627 WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 1635 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1628 1636
1629 dce_v6_0_grph_enable(crtc, true); 1637 dce_v6_0_grph_enable(crtc, true);
1630 1638
1631 WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 1639 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1632 target_fb->height); 1640 target_fb->height);
1633 x &= ~3; 1641 x &= ~3;
1634 y &= ~1; 1642 y &= ~1;
1635 WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset, 1643 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1636 (x << 16) | y); 1644 (x << 16) | y);
1637 viewport_w = crtc->mode.hdisplay; 1645 viewport_w = crtc->mode.hdisplay;
1638 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1646 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1639 1647
1640 WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 1648 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1641 (viewport_w << 16) | viewport_h); 1649 (viewport_w << 16) | viewport_h);
1642 1650
1643 /* set pageflip to happen anywhere in vblank interval */ 1651 /* set pageflip to happen anywhere in vblank interval */
1644 WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 1652 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1645 1653
1646 if (!atomic && fb && fb != crtc->primary->fb) { 1654 if (!atomic && fb && fb != crtc->primary->fb) {
1647 amdgpu_fb = to_amdgpu_framebuffer(fb); 1655 amdgpu_fb = to_amdgpu_framebuffer(fb);
@@ -1668,10 +1676,10 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1668 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1676 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1669 1677
1670 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1678 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1671 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 1679 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
1672 EVERGREEN_INTERLEAVE_EN); 1680 INTERLEAVE_EN);
1673 else 1681 else
1674 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 1682 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1675} 1683}
1676 1684
1677static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 1685static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
@@ -1684,54 +1692,52 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
1684 1692
1685 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 1693 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
1686 1694
1687 WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 1695 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1688 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 1696 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
1689 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 1697 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
1690 WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 1698 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
1691 NI_GRPH_PRESCALE_BYPASS); 1699 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
1692 WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 1700 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
1693 NI_OVL_PRESCALE_BYPASS); 1701 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
1694 WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1702 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1695 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 1703 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
1696 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 1704 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
1697
1698
1699 1705
1700 WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 1706 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
1701 1707
1702 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 1708 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
1703 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 1709 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
1704 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 1710 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
1705 1711
1706 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 1712 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
1707 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 1713 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
1708 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 1714 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
1709 1715
1710 WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 1716 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
1711 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 1717 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
1712 1718
1713 WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 1719 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
1714 for (i = 0; i < 256; i++) { 1720 for (i = 0; i < 256; i++) {
1715 WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 1721 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
1716 (amdgpu_crtc->lut_r[i] << 20) | 1722 (amdgpu_crtc->lut_r[i] << 20) |
1717 (amdgpu_crtc->lut_g[i] << 10) | 1723 (amdgpu_crtc->lut_g[i] << 10) |
1718 (amdgpu_crtc->lut_b[i] << 0)); 1724 (amdgpu_crtc->lut_b[i] << 0));
1719 } 1725 }
1720 1726
1721 WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1727 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1722 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 1728 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
1723 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 1729 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
1724 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 1730 ICON_DEGAMMA_MODE(0) |
1725 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 1731 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
1726 WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 1732 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
1727 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 1733 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
1728 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 1734 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
1729 WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1735 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1730 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 1736 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
1731 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 1737 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
1732 WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 1738 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1733 (NI_OUTPUT_CSC_GRPH_MODE(0) | 1739 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
1734 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 1740 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
1735 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 1741 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
1736 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 1742 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
1737 1743
@@ -1810,12 +1816,12 @@ static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
1810 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1816 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1811 uint32_t cur_lock; 1817 uint32_t cur_lock;
1812 1818
1813 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset); 1819 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
1814 if (lock) 1820 if (lock)
1815 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 1821 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1816 else 1822 else
1817 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 1823 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1818 WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 1824 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
1819} 1825}
1820 1826
1821static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 1827static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
@@ -1823,9 +1829,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
1823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1829 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1824 struct amdgpu_device *adev = crtc->dev->dev_private; 1830 struct amdgpu_device *adev = crtc->dev->dev_private;
1825 1831
1826 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, 1832 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1827 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 1833 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1828 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 1834 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1829 1835
1830 1836
1831} 1837}
@@ -1835,15 +1841,15 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
1835 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1841 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1836 struct amdgpu_device *adev = crtc->dev->dev_private; 1842 struct amdgpu_device *adev = crtc->dev->dev_private;
1837 1843
1838 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1844 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1839 upper_32_bits(amdgpu_crtc->cursor_addr)); 1845 upper_32_bits(amdgpu_crtc->cursor_addr));
1840 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1846 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1841 lower_32_bits(amdgpu_crtc->cursor_addr)); 1847 lower_32_bits(amdgpu_crtc->cursor_addr));
1842 1848
1843 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, 1849 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1844 EVERGREEN_CURSOR_EN | 1850 CUR_CONTROL__CURSOR_EN_MASK |
1845 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 1851 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1846 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 1852 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1847 1853
1848} 1854}
1849 1855
@@ -1870,9 +1876,9 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1870 y = 0; 1876 y = 0;
1871 } 1877 }
1872 1878
1873 WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 1879 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1874 WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 1880 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1875 WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset, 1881 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
1876 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 1882 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1877 1883
1878 amdgpu_crtc->cursor_x = x; 1884 amdgpu_crtc->cursor_x = x;
@@ -2478,14 +2484,14 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2478 2484
2479 switch (state) { 2485 switch (state) {
2480 case AMDGPU_IRQ_STATE_DISABLE: 2486 case AMDGPU_IRQ_STATE_DISABLE:
2481 interrupt_mask = RREG32(INT_MASK + reg_block); 2487 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2482 interrupt_mask &= ~VBLANK_INT_MASK; 2488 interrupt_mask &= ~VBLANK_INT_MASK;
2483 WREG32(INT_MASK + reg_block, interrupt_mask); 2489 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2484 break; 2490 break;
2485 case AMDGPU_IRQ_STATE_ENABLE: 2491 case AMDGPU_IRQ_STATE_ENABLE:
2486 interrupt_mask = RREG32(INT_MASK + reg_block); 2492 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2487 interrupt_mask |= VBLANK_INT_MASK; 2493 interrupt_mask |= VBLANK_INT_MASK;
2488 WREG32(INT_MASK + reg_block, interrupt_mask); 2494 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2489 break; 2495 break;
2490 default: 2496 default:
2491 break; 2497 break;
@@ -2513,14 +2519,14 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2513 2519
2514 switch (state) { 2520 switch (state) {
2515 case AMDGPU_IRQ_STATE_DISABLE: 2521 case AMDGPU_IRQ_STATE_DISABLE:
2516 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); 2522 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2517 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 2523 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2518 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2524 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2519 break; 2525 break;
2520 case AMDGPU_IRQ_STATE_ENABLE: 2526 case AMDGPU_IRQ_STATE_ENABLE:
2521 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); 2527 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2522 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 2528 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2523 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2529 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2524 break; 2530 break;
2525 default: 2531 default:
2526 break; 2532 break;
@@ -2588,7 +2594,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2588 switch (entry->src_data) { 2594 switch (entry->src_data) {
2589 case 0: /* vblank */ 2595 case 0: /* vblank */
2590 if (disp_int & interrupt_status_offsets[crtc].vblank) 2596 if (disp_int & interrupt_status_offsets[crtc].vblank)
2591 WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 2597 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2592 else 2598 else
2593 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2599 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2594 2600
@@ -2599,7 +2605,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2599 break; 2605 break;
2600 case 1: /* vline */ 2606 case 1: /* vline */
2601 if (disp_int & interrupt_status_offsets[crtc].vline) 2607 if (disp_int & interrupt_status_offsets[crtc].vline)
2602 WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 2608 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2603 else 2609 else
2604 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2610 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2605 2611
@@ -2625,12 +2631,12 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2625 return -EINVAL; 2631 return -EINVAL;
2626 } 2632 }
2627 2633
2628 reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]); 2634 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
2629 if (state == AMDGPU_IRQ_STATE_DISABLE) 2635 if (state == AMDGPU_IRQ_STATE_DISABLE)
2630 WREG32(GRPH_INT_CONTROL + crtc_offsets[type], 2636 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2631 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2637 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2632 else 2638 else
2633 WREG32(GRPH_INT_CONTROL + crtc_offsets[type], 2639 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2634 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2640 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2635 2641
2636 return 0; 2642 return 0;
@@ -2653,9 +2659,9 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2653 return -EINVAL; 2659 return -EINVAL;
2654 } 2660 }
2655 2661
2656 if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) & 2662 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
2657 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 2663 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2658 WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id], 2664 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
2659 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 2665 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2660 2666
2661 /* IRQ could occur when in initial stage */ 2667 /* IRQ could occur when in initial stage */
@@ -2706,9 +2712,9 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
2706 mask = interrupt_status_offsets[hpd].hpd; 2712 mask = interrupt_status_offsets[hpd].hpd;
2707 2713
2708 if (disp_int & mask) { 2714 if (disp_int & mask) {
2709 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 2715 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
2710 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 2716 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
2711 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 2717 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
2712 schedule_work(&adev->hotplug_work); 2718 schedule_work(&adev->hotplug_work);
2713 DRM_INFO("IH: HPD%d\n", hpd + 1); 2719 DRM_INFO("IH: HPD%d\n", hpd + 1);
2714 } 2720 }
@@ -3024,7 +3030,6 @@ static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3024 .bandwidth_update = &dce_v6_0_bandwidth_update, 3030 .bandwidth_update = &dce_v6_0_bandwidth_update,
3025 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3031 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3026 .vblank_wait = &dce_v6_0_vblank_wait, 3032 .vblank_wait = &dce_v6_0_vblank_wait,
3027 .is_display_hung = &dce_v6_0_is_display_hung,
3028 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3033 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3029 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3034 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3030 .hpd_sense = &dce_v6_0_hpd_sense, 3035 .hpd_sense = &dce_v6_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 4ae59914bc32..a699896eeabc 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3586,7 +3586,6 @@ static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3586 .bandwidth_update = &dce_v8_0_bandwidth_update, 3586 .bandwidth_update = &dce_v8_0_bandwidth_update,
3587 .vblank_get_counter = &dce_v8_0_vblank_get_counter, 3587 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3588 .vblank_wait = &dce_v8_0_vblank_wait, 3588 .vblank_wait = &dce_v8_0_vblank_wait,
3589 .is_display_hung = &dce_v8_0_is_display_hung,
3590 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3589 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3591 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3590 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3592 .hpd_sense = &dce_v8_0_hpd_sense, 3591 .hpd_sense = &dce_v8_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 81cbf0b05dff..a2442534e17b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -95,11 +95,6 @@ static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
95 return 0; 95 return 0;
96} 96}
97 97
98static bool dce_virtual_is_display_hung(struct amdgpu_device *adev)
99{
100 return false;
101}
102
103static void dce_virtual_stop_mc_access(struct amdgpu_device *adev, 98static void dce_virtual_stop_mc_access(struct amdgpu_device *adev,
104 struct amdgpu_mode_mc_save *save) 99 struct amdgpu_mode_mc_save *save)
105{ 100{
@@ -691,7 +686,6 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
691 .bandwidth_update = &dce_virtual_bandwidth_update, 686 .bandwidth_update = &dce_virtual_bandwidth_update,
692 .vblank_get_counter = &dce_virtual_vblank_get_counter, 687 .vblank_get_counter = &dce_virtual_vblank_get_counter,
693 .vblank_wait = &dce_virtual_vblank_wait, 688 .vblank_wait = &dce_virtual_vblank_wait,
694 .is_display_hung = &dce_virtual_is_display_hung,
695 .backlight_set_level = NULL, 689 .backlight_set_level = NULL,
696 .backlight_get_level = NULL, 690 .backlight_get_level = NULL,
697 .hpd_sense = &dce_virtual_hpd_sense, 691 .hpd_sense = &dce_virtual_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 21c086e02e7b..879a94bbfe12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -26,15 +26,18 @@
26#include "amdgpu_gfx.h" 26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h" 27#include "amdgpu_ucode.h"
28#include "si/clearstate_si.h" 28#include "si/clearstate_si.h"
29#include "si/sid.h" 29#include "bif/bif_3_0_d.h"
30 30#include "bif/bif_3_0_sh_mask.h"
31#define GFX6_NUM_GFX_RINGS 1 31#include "oss/oss_1_0_d.h"
32#define GFX6_NUM_COMPUTE_RINGS 2 32#include "oss/oss_1_0_sh_mask.h"
33#define STATIC_PER_CU_PG_ENABLE (1 << 3) 33#include "gca/gfx_6_0_d.h"
34#define DYN_PER_CU_PG_ENABLE (1 << 2) 34#include "gca/gfx_6_0_sh_mask.h"
35#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 35#include "gmc/gmc_6_0_d.h"
36#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 36#include "gmc/gmc_6_0_sh_mask.h"
37 37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
38 41
39static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 42static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
40static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 43static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -70,6 +73,15 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *bu
70//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 73//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
71static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 74static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
72 75
76#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79#define MICRO_TILE_MODE(x) ((x) << 0)
80#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81#define BANK_WIDTH(x) ((x) << 14)
82#define BANK_HEIGHT(x) ((x) << 16)
83#define MACRO_TILE_ASPECT(x) ((x) << 18)
84#define NUM_BANKS(x) ((x) << 20)
73 85
74static const u32 verde_rlc_save_restore_register_list[] = 86static const u32 verde_rlc_save_restore_register_list[] =
75{ 87{
@@ -400,8 +412,8 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
400 } 412 }
401 413
402 if (adev->asic_type == CHIP_VERDE || 414 if (adev->asic_type == CHIP_VERDE ||
403 adev->asic_type == CHIP_OLAND || 415 adev->asic_type == CHIP_OLAND ||
404 adev->asic_type == CHIP_HAINAN) { 416 adev->asic_type == CHIP_HAINAN) {
405 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
406 switch (reg_offset) { 418 switch (reg_offset) {
407 case 0: 419 case 0:
@@ -414,7 +426,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
416 break; 428 break;
417 case 1: 429 case 1:
418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 430 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 431 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 432 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -434,7 +446,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
436 break; 448 break;
437 case 3: 449 case 3:
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 450 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 451 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 452 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -444,7 +456,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
446 break; 458 break;
447 case 4: 459 case 4:
448 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 460 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
449 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 461 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -454,7 +466,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
456 break; 468 break;
457 case 5: 469 case 5:
458 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 470 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
459 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 471 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 472 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -464,7 +476,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
466 break; 478 break;
467 case 6: 479 case 6:
468 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 480 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 481 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -474,7 +486,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
476 break; 488 break;
477 case 7: 489 case 7:
478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 490 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
479 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 491 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
480 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 492 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -484,7 +496,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 496 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 497 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
486 break; 498 break;
487 case 8: 499 case 8:
488 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 500 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
489 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 501 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 502 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -494,7 +506,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
496 break; 508 break;
497 case 9: 509 case 9:
498 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 510 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
499 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 511 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
500 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -504,7 +516,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
506 break; 518 break;
507 case 10: 519 case 10:
508 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 520 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 521 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 522 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -514,7 +526,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
516 break; 528 break;
517 case 11: 529 case 11:
518 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 530 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
519 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 531 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -524,7 +536,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
526 break; 538 break;
527 case 12: 539 case 12:
528 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 540 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
529 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 541 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
530 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 542 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -534,7 +546,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
536 break; 548 break;
537 case 13: 549 case 13:
538 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 550 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
539 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 551 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 552 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -544,7 +556,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
546 break; 558 break;
547 case 14: 559 case 14:
548 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 560 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
549 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 561 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 562 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -554,7 +566,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
556 break; 568 break;
557 case 15: 569 case 15:
558 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 570 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 571 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 572 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -564,7 +576,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 576 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 577 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
566 break; 578 break;
567 case 16: 579 case 16:
568 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 580 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
569 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 581 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 582 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -574,7 +586,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
576 break; 588 break;
577 case 17: 589 case 17:
578 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 590 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 591 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 592 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -584,7 +596,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
586 break; 598 break;
587 case 21: 599 case 21:
588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 600 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
589 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 601 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 602 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -594,7 +606,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
596 break; 608 break;
597 case 22: 609 case 22:
598 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 610 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 611 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
600 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 612 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -604,7 +616,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
606 break; 618 break;
607 case 23: 619 case 23:
608 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 620 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
609 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 621 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 622 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -614,7 +626,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
616 break; 628 break;
617 case 24: 629 case 24:
618 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 630 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
619 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 631 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
620 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 632 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -624,7 +636,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
626 break; 638 break;
627 case 25: 639 case 25:
628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 640 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
629 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 641 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 642 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -639,7 +651,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
639 break; 651 break;
640 } 652 }
641 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 653 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
642 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); 654 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
643 } 655 }
644 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 656 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 657 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
@@ -879,7 +891,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
879 break; 891 break;
880 } 892 }
881 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 893 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
882 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); 894 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
883 } 895 }
884 } else{ 896 } else{
885 897
@@ -894,19 +906,23 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
894 u32 data; 906 u32 data;
895 907
896 if (instance == 0xffffffff) 908 if (instance == 0xffffffff)
897 data = INSTANCE_BROADCAST_WRITES; 909 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
898 else 910 else
899 data = INSTANCE_INDEX(instance); 911 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
900 912
901 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 913 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
902 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 914 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
915 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
903 else if (se_num == 0xffffffff) 916 else if (se_num == 0xffffffff)
904 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 917 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
918 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
905 else if (sh_num == 0xffffffff) 919 else if (sh_num == 0xffffffff)
906 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); 920 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
921 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
907 else 922 else
908 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); 923 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
909 WREG32(GRBM_GFX_INDEX, data); 924 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
925 WREG32(mmGRBM_GFX_INDEX, data);
910} 926}
911 927
912static u32 gfx_v6_0_create_bitmask(u32 bit_width) 928static u32 gfx_v6_0_create_bitmask(u32 bit_width)
@@ -920,11 +936,11 @@ static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
920{ 936{
921 u32 data, mask; 937 u32 data, mask;
922 938
923 data = RREG32(CC_RB_BACKEND_DISABLE); 939 data = RREG32(mmCC_RB_BACKEND_DISABLE);
924 data &= BACKEND_DISABLE_MASK; 940 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
925 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); 941 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
926 942
927 data >>= BACKEND_DISABLE_SHIFT; 943 data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
928 944
929 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se); 945 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
930 946
@@ -936,14 +952,23 @@ static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
936 switch (adev->asic_type) { 952 switch (adev->asic_type) {
937 case CHIP_TAHITI: 953 case CHIP_TAHITI:
938 case CHIP_PITCAIRN: 954 case CHIP_PITCAIRN:
939 *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) | 955 *rconf |=
940 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2); 956 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
957 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
958 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
959 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
960 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
961 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
962 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
941 break; 963 break;
942 case CHIP_VERDE: 964 case CHIP_VERDE:
943 *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1); 965 *rconf |=
966 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
967 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
968 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
944 break; 969 break;
945 case CHIP_OLAND: 970 case CHIP_OLAND:
946 *rconf |= RB_YSEL; 971 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
947 break; 972 break;
948 case CHIP_HAINAN: 973 case CHIP_HAINAN:
949 *rconf |= 0x0; 974 *rconf |= 0x0;
@@ -981,24 +1006,24 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
981 int idx = (se / 2) * 2; 1006 int idx = (se / 2) * 2;
982 1007
983 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1008 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
984 raster_config_se &= ~SE_MAP_MASK; 1009 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
985 1010
986 if (!se_mask[idx]) { 1011 if (!se_mask[idx]) {
987 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1012 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
988 } else { 1013 } else {
989 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1014 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
990 } 1015 }
991 } 1016 }
992 1017
993 pkr0_mask &= rb_mask; 1018 pkr0_mask &= rb_mask;
994 pkr1_mask &= rb_mask; 1019 pkr1_mask &= rb_mask;
995 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1020 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
996 raster_config_se &= ~PKR_MAP_MASK; 1021 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
997 1022
998 if (!pkr0_mask) { 1023 if (!pkr0_mask) {
999 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1024 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1000 } else { 1025 } else {
1001 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1026 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1002 } 1027 }
1003 } 1028 }
1004 1029
@@ -1009,14 +1034,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1009 rb0_mask &= rb_mask; 1034 rb0_mask &= rb_mask;
1010 rb1_mask &= rb_mask; 1035 rb1_mask &= rb_mask;
1011 if (!rb0_mask || !rb1_mask) { 1036 if (!rb0_mask || !rb1_mask) {
1012 raster_config_se &= ~RB_MAP_PKR0_MASK; 1037 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1013 1038
1014 if (!rb0_mask) { 1039 if (!rb0_mask) {
1015 raster_config_se |= 1040 raster_config_se |=
1016 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1041 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1017 } else { 1042 } else {
1018 raster_config_se |= 1043 raster_config_se |=
1019 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1044 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1020 } 1045 }
1021 } 1046 }
1022 1047
@@ -1026,14 +1051,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1026 rb0_mask &= rb_mask; 1051 rb0_mask &= rb_mask;
1027 rb1_mask &= rb_mask; 1052 rb1_mask &= rb_mask;
1028 if (!rb0_mask || !rb1_mask) { 1053 if (!rb0_mask || !rb1_mask) {
1029 raster_config_se &= ~RB_MAP_PKR1_MASK; 1054 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1030 1055
1031 if (!rb0_mask) { 1056 if (!rb0_mask) {
1032 raster_config_se |= 1057 raster_config_se |=
1033 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1058 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1034 } else { 1059 } else {
1035 raster_config_se |= 1060 raster_config_se |=
1036 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1061 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1037 } 1062 }
1038 } 1063 }
1039 } 1064 }
@@ -1041,7 +1066,7 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1041 1066
1042 /* GRBM_GFX_INDEX has a different offset on SI */ 1067 /* GRBM_GFX_INDEX has a different offset on SI */
1043 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1068 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1044 WREG32(PA_SC_RASTER_CONFIG, raster_config_se); 1069 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1045 } 1070 }
1046 1071
1047 /* GRBM_GFX_INDEX has a different offset on SI */ 1072 /* GRBM_GFX_INDEX has a different offset on SI */
@@ -1063,7 +1088,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1063 for (j = 0; j < sh_per_se; j++) { 1088 for (j = 0; j < sh_per_se; j++) {
1064 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1089 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1065 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); 1090 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1066 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 1091 disabled_rbs |= data << ((i * sh_per_se + j) * 2);
1067 } 1092 }
1068 } 1093 }
1069 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1094 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
@@ -1105,7 +1130,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1105 1130
1106 if (!adev->gfx.config.backend_enable_mask || 1131 if (!adev->gfx.config.backend_enable_mask ||
1107 adev->gfx.config.num_rbs >= num_rb_pipes) 1132 adev->gfx.config.num_rbs >= num_rb_pipes)
1108 WREG32(PA_SC_RASTER_CONFIG, data); 1133 WREG32(mmPA_SC_RASTER_CONFIG, data);
1109 else 1134 else
1110 gfx_v6_0_write_harvested_raster_configs(adev, data, 1135 gfx_v6_0_write_harvested_raster_configs(adev, data,
1111 adev->gfx.config.backend_enable_mask, 1136 adev->gfx.config.backend_enable_mask,
@@ -1124,11 +1149,11 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1124{ 1149{
1125 u32 data, mask; 1150 u32 data, mask;
1126 1151
1127 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 1152 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
1128 data &= INACTIVE_CUS_MASK; 1153 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1129 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); 1154 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1130 1155
1131 data >>= INACTIVE_CUS_SHIFT; 1156 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1132 1157
1133 mask = gfx_v6_0_create_bitmask(cu_per_sh); 1158 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1134 1159
@@ -1148,7 +1173,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1148 for (i = 0; i < se_num; i++) { 1173 for (i = 0; i < se_num; i++) {
1149 for (j = 0; j < sh_per_se; j++) { 1174 for (j = 0; j < sh_per_se; j++) {
1150 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1175 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1151 data = RREG32(SPI_STATIC_THREAD_MGMT_3); 1176 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1152 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh); 1177 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1153 1178
1154 mask = 1; 1179 mask = 1;
@@ -1156,7 +1181,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1156 mask <<= k; 1181 mask <<= k;
1157 if (active_cu & mask) { 1182 if (active_cu & mask) {
1158 data &= ~mask; 1183 data &= ~mask;
1159 WREG32(SPI_STATIC_THREAD_MGMT_3, data); 1184 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1160 break; 1185 break;
1161 } 1186 }
1162 } 1187 }
@@ -1209,7 +1234,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1209 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1234 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1210 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1235 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1211 break; 1236 break;
1212
1213 case CHIP_VERDE: 1237 case CHIP_VERDE:
1214 adev->gfx.config.max_shader_engines = 1; 1238 adev->gfx.config.max_shader_engines = 1;
1215 adev->gfx.config.max_tile_pipes = 4; 1239 adev->gfx.config.max_tile_pipes = 4;
@@ -1266,18 +1290,18 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1266 break; 1290 break;
1267 } 1291 }
1268 1292
1269 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1293 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1270 WREG32(SRBM_INT_CNTL, 1); 1294 WREG32(mmSRBM_INT_CNTL, 1);
1271 WREG32(SRBM_INT_ACK, 1); 1295 WREG32(mmSRBM_INT_ACK, 1);
1272 1296
1273 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1297 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1274 1298
1275 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1299 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1276 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1300 mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1277 1301
1278 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1302 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1279 adev->gfx.config.mem_max_burst_length_bytes = 256; 1303 adev->gfx.config.mem_max_burst_length_bytes = 256;
1280 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1304 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1281 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1305 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1282 if (adev->gfx.config.mem_row_size_in_kb > 4) 1306 if (adev->gfx.config.mem_row_size_in_kb > 4)
1283 adev->gfx.config.mem_row_size_in_kb = 4; 1307 adev->gfx.config.mem_row_size_in_kb = 4;
@@ -1285,32 +1309,33 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1285 adev->gfx.config.num_gpus = 1; 1309 adev->gfx.config.num_gpus = 1;
1286 adev->gfx.config.multi_gpu_tile_size = 64; 1310 adev->gfx.config.multi_gpu_tile_size = 64;
1287 1311
1288 gb_addr_config &= ~ROW_SIZE_MASK; 1312 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1289 switch (adev->gfx.config.mem_row_size_in_kb) { 1313 switch (adev->gfx.config.mem_row_size_in_kb) {
1290 case 1: 1314 case 1:
1291 default: 1315 default:
1292 gb_addr_config |= ROW_SIZE(0); 1316 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1293 break; 1317 break;
1294 case 2: 1318 case 2:
1295 gb_addr_config |= ROW_SIZE(1); 1319 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1296 break; 1320 break;
1297 case 4: 1321 case 4:
1298 gb_addr_config |= ROW_SIZE(2); 1322 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1299 break; 1323 break;
1300 } 1324 }
1301 adev->gfx.config.gb_addr_config = gb_addr_config; 1325 adev->gfx.config.gb_addr_config = gb_addr_config;
1302 1326
1303 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1327 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1304 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1328 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1305 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1329 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1306 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1330 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1307 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1331 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1308 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1332 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1333
1309#if 0 1334#if 0
1310 if (adev->has_uvd) { 1335 if (adev->has_uvd) {
1311 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 1336 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1312 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1337 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1313 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1338 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1314 } 1339 }
1315#endif 1340#endif
1316 gfx_v6_0_tiling_mode_table_init(adev); 1341 gfx_v6_0_tiling_mode_table_init(adev);
@@ -1325,45 +1350,48 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1325 1350
1326 gfx_v6_0_get_cu_info(adev); 1351 gfx_v6_0_get_cu_info(adev);
1327 1352
1328 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1353 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1329 ROQ_IB2_START(0x2b))); 1354 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1330 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1355 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1356 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1331 1357
1332 sx_debug_1 = RREG32(SX_DEBUG_1); 1358 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1333 WREG32(SX_DEBUG_1, sx_debug_1); 1359 WREG32(mmSX_DEBUG_1, sx_debug_1);
1334 1360
1335 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1361 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1336 1362
1337 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) | 1363 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1338 SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) | 1364 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1339 SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) | 1365 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1340 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size))); 1366 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1341 1367
1342 WREG32(VGT_NUM_INSTANCES, 1); 1368 WREG32(mmVGT_NUM_INSTANCES, 1);
1343 WREG32(CP_PERFMON_CNTL, 0); 1369 WREG32(mmCP_PERFMON_CNTL, 0);
1344 WREG32(SQ_CONFIG, 0); 1370 WREG32(mmSQ_CONFIG, 0);
1345 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1371 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1346 FORCE_EOV_MAX_REZ_CNT(255))); 1372 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1347 1373
1348 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1374 WREG32(mmVGT_CACHE_INVALIDATION,
1349 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1375 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1376 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1350 1377
1351 WREG32(VGT_GS_VERTEX_REUSE, 16); 1378 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1352 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1379 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1353 1380
1354 WREG32(CB_PERFCOUNTER0_SELECT0, 0); 1381 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1355 WREG32(CB_PERFCOUNTER0_SELECT1, 0); 1382 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1356 WREG32(CB_PERFCOUNTER1_SELECT0, 0); 1383 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1357 WREG32(CB_PERFCOUNTER1_SELECT1, 0); 1384 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1358 WREG32(CB_PERFCOUNTER2_SELECT0, 0); 1385 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1359 WREG32(CB_PERFCOUNTER2_SELECT1, 0); 1386 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1360 WREG32(CB_PERFCOUNTER3_SELECT0, 0); 1387 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1361 WREG32(CB_PERFCOUNTER3_SELECT1, 0); 1388 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1362 1389
1363 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1390 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1364 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1391 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1365 1392
1366 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1393 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1394 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1367 1395
1368 udelay(50); 1396 udelay(50);
1369} 1397}
@@ -1374,7 +1402,7 @@ static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1374 int i; 1402 int i;
1375 1403
1376 adev->gfx.scratch.num_reg = 7; 1404 adev->gfx.scratch.num_reg = 7;
1377 adev->gfx.scratch.reg_base = SCRATCH_REG0; 1405 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1378 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 1406 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1379 adev->gfx.scratch.free[i] = true; 1407 adev->gfx.scratch.free[i] = true;
1380 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 1408 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
@@ -1430,11 +1458,18 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1430 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1458 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1431 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1459 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1432 WRITE_DATA_DST_SEL(0))); 1460 WRITE_DATA_DST_SEL(0)));
1433 amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL); 1461 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1434 amdgpu_ring_write(ring, 0); 1462 amdgpu_ring_write(ring, 0);
1435 amdgpu_ring_write(ring, 0x1); 1463 amdgpu_ring_write(ring, 0x1);
1436} 1464}
1437 1465
1466static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1467{
1468 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1469 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1470 EVENT_INDEX(0));
1471}
1472
1438/** 1473/**
1439 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1474 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1440 * 1475 *
@@ -1448,7 +1483,7 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1448 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1483 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1449 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1484 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1450 WRITE_DATA_DST_SEL(0))); 1485 WRITE_DATA_DST_SEL(0)));
1451 amdgpu_ring_write(ring, HDP_DEBUG0); 1486 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1452 amdgpu_ring_write(ring, 0); 1487 amdgpu_ring_write(ring, 0);
1453 amdgpu_ring_write(ring, 0x1); 1488 amdgpu_ring_write(ring, 0x1);
1454} 1489}
@@ -1460,7 +1495,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1460 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1495 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1461 /* flush read cache over gart */ 1496 /* flush read cache over gart */
1462 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1497 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1463 amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1498 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1464 amdgpu_ring_write(ring, 0); 1499 amdgpu_ring_write(ring, 0);
1465 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1500 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1466 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1501 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
@@ -1475,7 +1510,8 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1475 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1510 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1476 amdgpu_ring_write(ring, addr & 0xfffffffc); 1511 amdgpu_ring_write(ring, addr & 0xfffffffc);
1477 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1512 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1478 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 1513 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1514 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1479 amdgpu_ring_write(ring, lower_32_bits(seq)); 1515 amdgpu_ring_write(ring, lower_32_bits(seq));
1480 amdgpu_ring_write(ring, upper_32_bits(seq)); 1516 amdgpu_ring_write(ring, upper_32_bits(seq));
1481} 1517}
@@ -1578,11 +1614,13 @@ err1:
1578static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1614static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1579{ 1615{
1580 int i; 1616 int i;
1581 if (enable) 1617 if (enable) {
1582 WREG32(CP_ME_CNTL, 0); 1618 WREG32(mmCP_ME_CNTL, 0);
1583 else { 1619 } else {
1584 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 1620 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1585 WREG32(SCRATCH_UMSK, 0); 1621 CP_ME_CNTL__PFP_HALT_MASK |
1622 CP_ME_CNTL__CE_HALT_MASK));
1623 WREG32(mmSCRATCH_UMSK, 0);
1586 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1624 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1587 adev->gfx.gfx_ring[i].ready = false; 1625 adev->gfx.gfx_ring[i].ready = false;
1588 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1626 for (i = 0; i < adev->gfx.num_compute_rings; i++)
@@ -1616,34 +1654,33 @@ static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1616 fw_data = (const __le32 *) 1654 fw_data = (const __le32 *)
1617 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1655 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1618 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1656 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1619 WREG32(CP_PFP_UCODE_ADDR, 0); 1657 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1620 for (i = 0; i < fw_size; i++) 1658 for (i = 0; i < fw_size; i++)
1621 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1659 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1622 WREG32(CP_PFP_UCODE_ADDR, 0); 1660 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1623 1661
1624 /* CE */ 1662 /* CE */
1625 fw_data = (const __le32 *) 1663 fw_data = (const __le32 *)
1626 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1664 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1627 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1665 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1628 WREG32(CP_CE_UCODE_ADDR, 0); 1666 WREG32(mmCP_CE_UCODE_ADDR, 0);
1629 for (i = 0; i < fw_size; i++) 1667 for (i = 0; i < fw_size; i++)
1630 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1668 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1631 WREG32(CP_CE_UCODE_ADDR, 0); 1669 WREG32(mmCP_CE_UCODE_ADDR, 0);
1632 1670
1633 /* ME */ 1671 /* ME */
1634 fw_data = (const __be32 *) 1672 fw_data = (const __be32 *)
1635 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1673 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1636 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1674 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1637 WREG32(CP_ME_RAM_WADDR, 0); 1675 WREG32(mmCP_ME_RAM_WADDR, 0);
1638 for (i = 0; i < fw_size; i++) 1676 for (i = 0; i < fw_size; i++)
1639 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1677 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1640 WREG32(CP_ME_RAM_WADDR, 0); 1678 WREG32(mmCP_ME_RAM_WADDR, 0);
1641
1642 1679
1643 WREG32(CP_PFP_UCODE_ADDR, 0); 1680 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1644 WREG32(CP_CE_UCODE_ADDR, 0); 1681 WREG32(mmCP_CE_UCODE_ADDR, 0);
1645 WREG32(CP_ME_RAM_WADDR, 0); 1682 WREG32(mmCP_ME_RAM_WADDR, 0);
1646 WREG32(CP_ME_RAM_RADDR, 0); 1683 WREG32(mmCP_ME_RAM_RADDR, 0);
1647 return 0; 1684 return 0;
1648} 1685}
1649 1686
@@ -1720,14 +1757,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1720 int r; 1757 int r;
1721 u64 rptr_addr; 1758 u64 rptr_addr;
1722 1759
1723 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1760 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
1724 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1761 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1725 1762
1726 /* Set the write pointer delay */ 1763 /* Set the write pointer delay */
1727 WREG32(CP_RB_WPTR_DELAY, 0); 1764 WREG32(mmCP_RB_WPTR_DELAY, 0);
1728 1765
1729 WREG32(CP_DEBUG, 0); 1766 WREG32(mmCP_DEBUG, 0);
1730 WREG32(SCRATCH_ADDR, 0); 1767 WREG32(mmSCRATCH_ADDR, 0);
1731 1768
1732 /* ring 0 - compute and gfx */ 1769 /* ring 0 - compute and gfx */
1733 /* Set ring buffer size */ 1770 /* Set ring buffer size */
@@ -1738,24 +1775,24 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1738#ifdef __BIG_ENDIAN 1775#ifdef __BIG_ENDIAN
1739 tmp |= BUF_SWAP_32BIT; 1776 tmp |= BUF_SWAP_32BIT;
1740#endif 1777#endif
1741 WREG32(CP_RB0_CNTL, tmp); 1778 WREG32(mmCP_RB0_CNTL, tmp);
1742 1779
1743 /* Initialize the ring buffer's read and write pointers */ 1780 /* Initialize the ring buffer's read and write pointers */
1744 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 1781 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
1745 ring->wptr = 0; 1782 ring->wptr = 0;
1746 WREG32(CP_RB0_WPTR, ring->wptr); 1783 WREG32(mmCP_RB0_WPTR, ring->wptr);
1747 1784
1748 /* set the wb address whether it's enabled or not */ 1785 /* set the wb address whether it's enabled or not */
1749 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1786 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1750 WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 1787 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1751 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1788 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1752 1789
1753 WREG32(SCRATCH_UMSK, 0); 1790 WREG32(mmSCRATCH_UMSK, 0);
1754 1791
1755 mdelay(1); 1792 mdelay(1);
1756 WREG32(CP_RB0_CNTL, tmp); 1793 WREG32(mmCP_RB0_CNTL, tmp);
1757 1794
1758 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 1795 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
1759 1796
1760 /* start the rings */ 1797 /* start the rings */
1761 gfx_v6_0_cp_gfx_start(adev); 1798 gfx_v6_0_cp_gfx_start(adev);
@@ -1779,11 +1816,11 @@ static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1779 struct amdgpu_device *adev = ring->adev; 1816 struct amdgpu_device *adev = ring->adev;
1780 1817
1781 if (ring == &adev->gfx.gfx_ring[0]) 1818 if (ring == &adev->gfx.gfx_ring[0])
1782 return RREG32(CP_RB0_WPTR); 1819 return RREG32(mmCP_RB0_WPTR);
1783 else if (ring == &adev->gfx.compute_ring[0]) 1820 else if (ring == &adev->gfx.compute_ring[0])
1784 return RREG32(CP_RB1_WPTR); 1821 return RREG32(mmCP_RB1_WPTR);
1785 else if (ring == &adev->gfx.compute_ring[1]) 1822 else if (ring == &adev->gfx.compute_ring[1])
1786 return RREG32(CP_RB2_WPTR); 1823 return RREG32(mmCP_RB2_WPTR);
1787 else 1824 else
1788 BUG(); 1825 BUG();
1789} 1826}
@@ -1792,8 +1829,8 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1792{ 1829{
1793 struct amdgpu_device *adev = ring->adev; 1830 struct amdgpu_device *adev = ring->adev;
1794 1831
1795 WREG32(CP_RB0_WPTR, ring->wptr); 1832 WREG32(mmCP_RB0_WPTR, ring->wptr);
1796 (void)RREG32(CP_RB0_WPTR); 1833 (void)RREG32(mmCP_RB0_WPTR);
1797} 1834}
1798 1835
1799static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 1836static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
@@ -1801,11 +1838,11 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1801 struct amdgpu_device *adev = ring->adev; 1838 struct amdgpu_device *adev = ring->adev;
1802 1839
1803 if (ring == &adev->gfx.compute_ring[0]) { 1840 if (ring == &adev->gfx.compute_ring[0]) {
1804 WREG32(CP_RB1_WPTR, ring->wptr); 1841 WREG32(mmCP_RB1_WPTR, ring->wptr);
1805 (void)RREG32(CP_RB1_WPTR); 1842 (void)RREG32(mmCP_RB1_WPTR);
1806 } else if (ring == &adev->gfx.compute_ring[1]) { 1843 } else if (ring == &adev->gfx.compute_ring[1]) {
1807 WREG32(CP_RB2_WPTR, ring->wptr); 1844 WREG32(mmCP_RB2_WPTR, ring->wptr);
1808 (void)RREG32(CP_RB2_WPTR); 1845 (void)RREG32(mmCP_RB2_WPTR);
1809 } else { 1846 } else {
1810 BUG(); 1847 BUG();
1811 } 1848 }
@@ -1817,7 +1854,7 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1817 struct amdgpu_ring *ring; 1854 struct amdgpu_ring *ring;
1818 u32 tmp; 1855 u32 tmp;
1819 u32 rb_bufsz; 1856 u32 rb_bufsz;
1820 int r; 1857 int i, r;
1821 u64 rptr_addr; 1858 u64 rptr_addr;
1822 1859
1823 /* ring1 - compute only */ 1860 /* ring1 - compute only */
@@ -1829,19 +1866,19 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1829#ifdef __BIG_ENDIAN 1866#ifdef __BIG_ENDIAN
1830 tmp |= BUF_SWAP_32BIT; 1867 tmp |= BUF_SWAP_32BIT;
1831#endif 1868#endif
1832 WREG32(CP_RB1_CNTL, tmp); 1869 WREG32(mmCP_RB1_CNTL, tmp);
1833 1870
1834 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 1871 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
1835 ring->wptr = 0; 1872 ring->wptr = 0;
1836 WREG32(CP_RB1_WPTR, ring->wptr); 1873 WREG32(mmCP_RB1_WPTR, ring->wptr);
1837 1874
1838 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1875 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1839 WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 1876 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1840 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1877 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1841 1878
1842 mdelay(1); 1879 mdelay(1);
1843 WREG32(CP_RB1_CNTL, tmp); 1880 WREG32(mmCP_RB1_CNTL, tmp);
1844 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 1881 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
1845 1882
1846 ring = &adev->gfx.compute_ring[1]; 1883 ring = &adev->gfx.compute_ring[1];
1847 rb_bufsz = order_base_2(ring->ring_size / 8); 1884 rb_bufsz = order_base_2(ring->ring_size / 8);
@@ -1849,32 +1886,27 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1849#ifdef __BIG_ENDIAN 1886#ifdef __BIG_ENDIAN
1850 tmp |= BUF_SWAP_32BIT; 1887 tmp |= BUF_SWAP_32BIT;
1851#endif 1888#endif
1852 WREG32(CP_RB2_CNTL, tmp); 1889 WREG32(mmCP_RB2_CNTL, tmp);
1853 1890
1854 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 1891 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
1855 ring->wptr = 0; 1892 ring->wptr = 0;
1856 WREG32(CP_RB2_WPTR, ring->wptr); 1893 WREG32(mmCP_RB2_WPTR, ring->wptr);
1857 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1894 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1858 WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 1895 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1859 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1896 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1860 1897
1861 mdelay(1); 1898 mdelay(1);
1862 WREG32(CP_RB2_CNTL, tmp); 1899 WREG32(mmCP_RB2_CNTL, tmp);
1863 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 1900 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
1864 1901
1865 adev->gfx.compute_ring[0].ready = true; 1902 adev->gfx.compute_ring[0].ready = false;
1866 adev->gfx.compute_ring[1].ready = true; 1903 adev->gfx.compute_ring[1].ready = false;
1867 1904
1868 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]); 1905 for (i = 0; i < 2; i++) {
1869 if (r) { 1906 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
1870 adev->gfx.compute_ring[0].ready = false; 1907 if (r)
1871 return r; 1908 return r;
1872 } 1909 adev->gfx.compute_ring[i].ready = true;
1873
1874 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1875 if (r) {
1876 adev->gfx.compute_ring[1].ready = false;
1877 return r;
1878 } 1910 }
1879 1911
1880 return 0; 1912 return 0;
@@ -1892,24 +1924,26 @@ static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1892 1924
1893static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1925static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1894 bool enable) 1926 bool enable)
1895{ 1927{
1896 u32 tmp = RREG32(CP_INT_CNTL_RING0); 1928 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
1897 u32 mask; 1929 u32 mask;
1898 int i; 1930 int i;
1899 1931
1900 if (enable) 1932 if (enable)
1901 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 1933 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
1934 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
1902 else 1935 else
1903 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 1936 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
1904 WREG32(CP_INT_CNTL_RING0, tmp); 1937 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
1938 WREG32(mmCP_INT_CNTL_RING0, tmp);
1905 1939
1906 if (!enable) { 1940 if (!enable) {
1907 /* read a gfx register */ 1941 /* read a gfx register */
1908 tmp = RREG32(DB_DEPTH_INFO); 1942 tmp = RREG32(mmDB_DEPTH_INFO);
1909 1943
1910 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 1944 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1911 for (i = 0; i < adev->usec_timeout; i++) { 1945 for (i = 0; i < adev->usec_timeout; i++) {
1912 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 1946 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1913 break; 1947 break;
1914 udelay(1); 1948 udelay(1);
1915 } 1949 }
@@ -1973,9 +2007,9 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1973 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2007 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1974 WRITE_DATA_DST_SEL(0))); 2008 WRITE_DATA_DST_SEL(0)));
1975 if (vm_id < 8) { 2009 if (vm_id < 8) {
1976 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2010 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1977 } else { 2011 } else {
1978 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2012 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1979 } 2013 }
1980 amdgpu_ring_write(ring, 0); 2014 amdgpu_ring_write(ring, 0);
1981 amdgpu_ring_write(ring, pd_addr >> 12); 2015 amdgpu_ring_write(ring, pd_addr >> 12);
@@ -1984,7 +2018,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1984 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2018 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1985 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2019 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1986 WRITE_DATA_DST_SEL(0))); 2020 WRITE_DATA_DST_SEL(0)));
1987 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 2021 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1988 amdgpu_ring_write(ring, 0); 2022 amdgpu_ring_write(ring, 0);
1989 amdgpu_ring_write(ring, 1 << vm_id); 2023 amdgpu_ring_write(ring, 1 << vm_id);
1990 2024
@@ -1992,7 +2026,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1992 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2026 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1993 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2027 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
1994 WAIT_REG_MEM_ENGINE(0))); /* me */ 2028 WAIT_REG_MEM_ENGINE(0))); /* me */
1995 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 2029 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1996 amdgpu_ring_write(ring, 0); 2030 amdgpu_ring_write(ring, 0);
1997 amdgpu_ring_write(ring, 0); /* ref */ 2031 amdgpu_ring_write(ring, 0); /* ref */
1998 amdgpu_ring_write(ring, 0); /* mask */ 2032 amdgpu_ring_write(ring, 0); /* mask */
@@ -2071,7 +2105,6 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2071 if (src_ptr) { 2105 if (src_ptr) {
2072 /* save restore block */ 2106 /* save restore block */
2073 if (adev->gfx.rlc.save_restore_obj == NULL) { 2107 if (adev->gfx.rlc.save_restore_obj == NULL) {
2074
2075 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 2108 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2076 AMDGPU_GEM_DOMAIN_VRAM, 2109 AMDGPU_GEM_DOMAIN_VRAM,
2077 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 2110 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
@@ -2166,20 +2199,12 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2166 2199
2167static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2200static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2168{ 2201{
2169 u32 tmp; 2202 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2170
2171 tmp = RREG32(RLC_LB_CNTL);
2172 if (enable)
2173 tmp |= LOAD_BALANCE_ENABLE;
2174 else
2175 tmp &= ~LOAD_BALANCE_ENABLE;
2176 WREG32(RLC_LB_CNTL, tmp);
2177 2203
2178 if (!enable) { 2204 if (!enable) {
2179 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2205 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2180 WREG32(SPI_LB_CU_MASK, 0x00ff); 2206 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2181 } 2207 }
2182
2183} 2208}
2184 2209
2185static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2210static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
@@ -2187,13 +2212,13 @@ static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2187 int i; 2212 int i;
2188 2213
2189 for (i = 0; i < adev->usec_timeout; i++) { 2214 for (i = 0; i < adev->usec_timeout; i++) {
2190 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) 2215 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2191 break; 2216 break;
2192 udelay(1); 2217 udelay(1);
2193 } 2218 }
2194 2219
2195 for (i = 0; i < adev->usec_timeout; i++) { 2220 for (i = 0; i < adev->usec_timeout; i++) {
2196 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) 2221 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2197 break; 2222 break;
2198 udelay(1); 2223 udelay(1);
2199 } 2224 }
@@ -2203,20 +2228,20 @@ static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2203{ 2228{
2204 u32 tmp; 2229 u32 tmp;
2205 2230
2206 tmp = RREG32(RLC_CNTL); 2231 tmp = RREG32(mmRLC_CNTL);
2207 if (tmp != rlc) 2232 if (tmp != rlc)
2208 WREG32(RLC_CNTL, rlc); 2233 WREG32(mmRLC_CNTL, rlc);
2209} 2234}
2210 2235
2211static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2236static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2212{ 2237{
2213 u32 data, orig; 2238 u32 data, orig;
2214 2239
2215 orig = data = RREG32(RLC_CNTL); 2240 orig = data = RREG32(mmRLC_CNTL);
2216 2241
2217 if (data & RLC_ENABLE) { 2242 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2218 data &= ~RLC_ENABLE; 2243 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2219 WREG32(RLC_CNTL, data); 2244 WREG32(mmRLC_CNTL, data);
2220 2245
2221 gfx_v6_0_wait_for_rlc_serdes(adev); 2246 gfx_v6_0_wait_for_rlc_serdes(adev);
2222 } 2247 }
@@ -2226,7 +2251,7 @@ static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2226 2251
2227static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2252static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2228{ 2253{
2229 WREG32(RLC_CNTL, 0); 2254 WREG32(mmRLC_CNTL, 0);
2230 2255
2231 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2256 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2232 gfx_v6_0_wait_for_rlc_serdes(adev); 2257 gfx_v6_0_wait_for_rlc_serdes(adev);
@@ -2234,7 +2259,7 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2234 2259
2235static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2260static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2236{ 2261{
2237 WREG32(RLC_CNTL, RLC_ENABLE); 2262 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2238 2263
2239 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2264 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2240 2265
@@ -2243,13 +2268,9 @@ static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2243 2268
2244static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2269static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2245{ 2270{
2246 u32 tmp = RREG32(GRBM_SOFT_RESET); 2271 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2247
2248 tmp |= SOFT_RESET_RLC;
2249 WREG32(GRBM_SOFT_RESET, tmp);
2250 udelay(50); 2272 udelay(50);
2251 tmp &= ~SOFT_RESET_RLC; 2273 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2252 WREG32(GRBM_SOFT_RESET, tmp);
2253 udelay(50); 2274 udelay(50);
2254} 2275}
2255 2276
@@ -2258,11 +2279,12 @@ static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2258 u32 tmp; 2279 u32 tmp;
2259 2280
2260 /* Enable LBPW only for DDR3 */ 2281 /* Enable LBPW only for DDR3 */
2261 tmp = RREG32(MC_SEQ_MISC0); 2282 tmp = RREG32(mmMC_SEQ_MISC0);
2262 if ((tmp & 0xF0000000) == 0xB0000000) 2283 if ((tmp & 0xF0000000) == 0xB0000000)
2263 return true; 2284 return true;
2264 return false; 2285 return false;
2265} 2286}
2287
2266static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2288static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2267{ 2289{
2268} 2290}
@@ -2283,15 +2305,15 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2283 gfx_v6_0_init_pg(adev); 2305 gfx_v6_0_init_pg(adev);
2284 gfx_v6_0_init_cg(adev); 2306 gfx_v6_0_init_cg(adev);
2285 2307
2286 WREG32(RLC_RL_BASE, 0); 2308 WREG32(mmRLC_RL_BASE, 0);
2287 WREG32(RLC_RL_SIZE, 0); 2309 WREG32(mmRLC_RL_SIZE, 0);
2288 WREG32(RLC_LB_CNTL, 0); 2310 WREG32(mmRLC_LB_CNTL, 0);
2289 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); 2311 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2290 WREG32(RLC_LB_CNTR_INIT, 0); 2312 WREG32(mmRLC_LB_CNTR_INIT, 0);
2291 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); 2313 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2292 2314
2293 WREG32(RLC_MC_CNTL, 0); 2315 WREG32(mmRLC_MC_CNTL, 0);
2294 WREG32(RLC_UCODE_CNTL, 0); 2316 WREG32(mmRLC_UCODE_CNTL, 0);
2295 2317
2296 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2318 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2297 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2319 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
@@ -2301,10 +2323,10 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2301 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2323 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2302 2324
2303 for (i = 0; i < fw_size; i++) { 2325 for (i = 0; i < fw_size; i++) {
2304 WREG32(RLC_UCODE_ADDR, i); 2326 WREG32(mmRLC_UCODE_ADDR, i);
2305 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2327 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2306 } 2328 }
2307 WREG32(RLC_UCODE_ADDR, 0); 2329 WREG32(mmRLC_UCODE_ADDR, 0);
2308 2330
2309 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2331 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2310 gfx_v6_0_rlc_start(adev); 2332 gfx_v6_0_rlc_start(adev);
@@ -2316,38 +2338,38 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2316{ 2338{
2317 u32 data, orig, tmp; 2339 u32 data, orig, tmp;
2318 2340
2319 orig = data = RREG32(RLC_CGCG_CGLS_CTRL); 2341 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2320 2342
2321 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2343 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2322 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2344 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2323 2345
2324 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); 2346 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2325 2347
2326 tmp = gfx_v6_0_halt_rlc(adev); 2348 tmp = gfx_v6_0_halt_rlc(adev);
2327 2349
2328 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2350 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2329 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2351 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2330 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); 2352 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2331 2353
2332 gfx_v6_0_wait_for_rlc_serdes(adev); 2354 gfx_v6_0_wait_for_rlc_serdes(adev);
2333 gfx_v6_0_update_rlc(adev, tmp); 2355 gfx_v6_0_update_rlc(adev, tmp);
2334 2356
2335 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); 2357 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2336 2358
2337 data |= CGCG_EN | CGLS_EN; 2359 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2338 } else { 2360 } else {
2339 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2361 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2340 2362
2341 RREG32(CB_CGTT_SCLK_CTRL); 2363 RREG32(mmCB_CGTT_SCLK_CTRL);
2342 RREG32(CB_CGTT_SCLK_CTRL); 2364 RREG32(mmCB_CGTT_SCLK_CTRL);
2343 RREG32(CB_CGTT_SCLK_CTRL); 2365 RREG32(mmCB_CGTT_SCLK_CTRL);
2344 RREG32(CB_CGTT_SCLK_CTRL); 2366 RREG32(mmCB_CGTT_SCLK_CTRL);
2345 2367
2346 data &= ~(CGCG_EN | CGLS_EN); 2368 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2347 } 2369 }
2348 2370
2349 if (orig != data) 2371 if (orig != data)
2350 WREG32(RLC_CGCG_CGLS_CTRL, data); 2372 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2351 2373
2352} 2374}
2353 2375
@@ -2357,51 +2379,51 @@ static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2357 u32 data, orig, tmp = 0; 2379 u32 data, orig, tmp = 0;
2358 2380
2359 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2381 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2360 orig = data = RREG32(CGTS_SM_CTRL_REG); 2382 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2361 data = 0x96940200; 2383 data = 0x96940200;
2362 if (orig != data) 2384 if (orig != data)
2363 WREG32(CGTS_SM_CTRL_REG, data); 2385 WREG32(mmCGTS_SM_CTRL_REG, data);
2364 2386
2365 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2366 orig = data = RREG32(CP_MEM_SLP_CNTL); 2388 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2367 data |= CP_MEM_LS_EN; 2389 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2368 if (orig != data) 2390 if (orig != data)
2369 WREG32(CP_MEM_SLP_CNTL, data); 2391 WREG32(mmCP_MEM_SLP_CNTL, data);
2370 } 2392 }
2371 2393
2372 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); 2394 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2373 data &= 0xffffffc0; 2395 data &= 0xffffffc0;
2374 if (orig != data) 2396 if (orig != data)
2375 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); 2397 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2376 2398
2377 tmp = gfx_v6_0_halt_rlc(adev); 2399 tmp = gfx_v6_0_halt_rlc(adev);
2378 2400
2379 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2401 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2380 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2402 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2381 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); 2403 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2382 2404
2383 gfx_v6_0_update_rlc(adev, tmp); 2405 gfx_v6_0_update_rlc(adev, tmp);
2384 } else { 2406 } else {
2385 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); 2407 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2386 data |= 0x00000003; 2408 data |= 0x00000003;
2387 if (orig != data) 2409 if (orig != data)
2388 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); 2410 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2389 2411
2390 data = RREG32(CP_MEM_SLP_CNTL); 2412 data = RREG32(mmCP_MEM_SLP_CNTL);
2391 if (data & CP_MEM_LS_EN) { 2413 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2392 data &= ~CP_MEM_LS_EN; 2414 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2393 WREG32(CP_MEM_SLP_CNTL, data); 2415 WREG32(mmCP_MEM_SLP_CNTL, data);
2394 } 2416 }
2395 orig = data = RREG32(CGTS_SM_CTRL_REG); 2417 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2396 data |= LS_OVERRIDE | OVERRIDE; 2418 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2397 if (orig != data) 2419 if (orig != data)
2398 WREG32(CGTS_SM_CTRL_REG, data); 2420 WREG32(mmCGTS_SM_CTRL_REG, data);
2399 2421
2400 tmp = gfx_v6_0_halt_rlc(adev); 2422 tmp = gfx_v6_0_halt_rlc(adev);
2401 2423
2402 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2424 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2403 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2425 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2404 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); 2426 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2405 2427
2406 gfx_v6_0_update_rlc(adev, tmp); 2428 gfx_v6_0_update_rlc(adev, tmp);
2407 } 2429 }
@@ -2421,6 +2443,7 @@ static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2421 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2443 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2422} 2444}
2423*/ 2445*/
2446
2424static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2447static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2425 bool enable) 2448 bool enable)
2426{ 2449{
@@ -2435,13 +2458,13 @@ static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2435{ 2458{
2436 u32 data, orig; 2459 u32 data, orig;
2437 2460
2438 orig = data = RREG32(RLC_PG_CNTL); 2461 orig = data = RREG32(mmRLC_PG_CNTL);
2439 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2462 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2440 data &= ~0x8000; 2463 data &= ~0x8000;
2441 else 2464 else
2442 data |= 0x8000; 2465 data |= 0x8000;
2443 if (orig != data) 2466 if (orig != data)
2444 WREG32(RLC_PG_CNTL, data); 2467 WREG32(mmRLC_PG_CNTL, data);
2445} 2468}
2446 2469
2447static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2470static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
@@ -2518,26 +2541,13 @@ static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2518static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2541static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2519 bool enable) 2542 bool enable)
2520{ 2543{
2521
2522 u32 tmp;
2523
2524 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2544 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2525 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); 2545 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2526 WREG32(RLC_TTOP_D, tmp); 2546 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2527 2547 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2528 tmp = RREG32(RLC_PG_CNTL);
2529 tmp |= GFX_PG_ENABLE;
2530 WREG32(RLC_PG_CNTL, tmp);
2531
2532 tmp = RREG32(RLC_AUTO_PG_CTRL);
2533 tmp |= AUTO_PG_EN;
2534 WREG32(RLC_AUTO_PG_CTRL, tmp);
2535 } else { 2548 } else {
2536 tmp = RREG32(RLC_AUTO_PG_CTRL); 2549 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2537 tmp &= ~AUTO_PG_EN; 2550 (void)RREG32(mmDB_RENDER_CONTROL);
2538 WREG32(RLC_AUTO_PG_CTRL, tmp);
2539
2540 tmp = RREG32(DB_RENDER_CONTROL);
2541 } 2551 }
2542} 2552}
2543 2553
@@ -2550,8 +2560,8 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2550 2560
2551 mutex_lock(&adev->grbm_idx_mutex); 2561 mutex_lock(&adev->grbm_idx_mutex);
2552 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff); 2562 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2553 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 2563 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
2554 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); 2564 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
2555 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2565 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2556 mutex_unlock(&adev->grbm_idx_mutex); 2566 mutex_unlock(&adev->grbm_idx_mutex);
2557 2567
@@ -2594,12 +2604,8 @@ static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2594 } 2604 }
2595 } 2605 }
2596 2606
2597 WREG32(RLC_PG_AO_CU_MASK, tmp); 2607 WREG32(mmRLC_PG_AO_CU_MASK, tmp);
2598 2608 WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number);
2599 tmp = RREG32(RLC_MAX_PG_CU);
2600 tmp &= ~MAX_PU_CU_MASK;
2601 tmp |= MAX_PU_CU(active_cu_number);
2602 WREG32(RLC_MAX_PG_CU, tmp);
2603} 2609}
2604 2610
2605static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2611static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
@@ -2607,13 +2613,13 @@ static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2607{ 2613{
2608 u32 data, orig; 2614 u32 data, orig;
2609 2615
2610 orig = data = RREG32(RLC_PG_CNTL); 2616 orig = data = RREG32(mmRLC_PG_CNTL);
2611 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2617 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2612 data |= STATIC_PER_CU_PG_ENABLE; 2618 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2613 else 2619 else
2614 data &= ~STATIC_PER_CU_PG_ENABLE; 2620 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2615 if (orig != data) 2621 if (orig != data)
2616 WREG32(RLC_PG_CNTL, data); 2622 WREG32(mmRLC_PG_CNTL, data);
2617} 2623}
2618 2624
2619static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2625static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
@@ -2621,33 +2627,28 @@ static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2621{ 2627{
2622 u32 data, orig; 2628 u32 data, orig;
2623 2629
2624 orig = data = RREG32(RLC_PG_CNTL); 2630 orig = data = RREG32(mmRLC_PG_CNTL);
2625 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2631 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2626 data |= DYN_PER_CU_PG_ENABLE; 2632 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2627 else 2633 else
2628 data &= ~DYN_PER_CU_PG_ENABLE; 2634 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2629 if (orig != data) 2635 if (orig != data)
2630 WREG32(RLC_PG_CNTL, data); 2636 WREG32(mmRLC_PG_CNTL, data);
2631} 2637}
2632 2638
2633static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2639static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2634{ 2640{
2635 u32 tmp; 2641 u32 tmp;
2636 2642
2637 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2643 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2638 2644 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2639 tmp = RREG32(RLC_PG_CNTL); 2645 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2640 tmp |= GFX_PG_SRC;
2641 WREG32(RLC_PG_CNTL, tmp);
2642
2643 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2644 2646
2645 tmp = RREG32(RLC_AUTO_PG_CTRL); 2647 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2646 2648 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2647 tmp &= ~GRBM_REG_SGIT_MASK; 2649 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2648 tmp |= GRBM_REG_SGIT(0x700); 2650 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2649 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK; 2651 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2650 WREG32(RLC_AUTO_PG_CTRL, tmp);
2651} 2652}
2652 2653
2653static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2654static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
@@ -2703,7 +2704,6 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2703 2704
2704 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2705 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2705 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2706 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2706
2707 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2707 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2708 buffer[count++] = cpu_to_le32(0x80000000); 2708 buffer[count++] = cpu_to_le32(0x80000000);
2709 buffer[count++] = cpu_to_le32(0x80000000); 2709 buffer[count++] = cpu_to_le32(0x80000000);
@@ -2723,7 +2723,7 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2723 } 2723 }
2724 2724
2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2726 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2726 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2727 2727
2728 switch (adev->asic_type) { 2728 switch (adev->asic_type) {
2729 case CHIP_TAHITI: 2729 case CHIP_TAHITI:
@@ -2766,16 +2766,16 @@ static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2766 gfx_v6_0_enable_cp_pg(adev, true); 2766 gfx_v6_0_enable_cp_pg(adev, true);
2767 gfx_v6_0_enable_gds_pg(adev, true); 2767 gfx_v6_0_enable_gds_pg(adev, true);
2768 } else { 2768 } else {
2769 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2769 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2770 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2770 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2771 2771
2772 } 2772 }
2773 gfx_v6_0_init_ao_cu_mask(adev); 2773 gfx_v6_0_init_ao_cu_mask(adev);
2774 gfx_v6_0_update_gfx_pg(adev, true); 2774 gfx_v6_0_update_gfx_pg(adev, true);
2775 } else { 2775 } else {
2776 2776
2777 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2777 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2778 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2778 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2779 } 2779 }
2780} 2780}
2781 2781
@@ -2800,23 +2800,61 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2800 uint64_t clock; 2800 uint64_t clock;
2801 2801
2802 mutex_lock(&adev->gfx.gpu_clock_mutex); 2802 mutex_lock(&adev->gfx.gpu_clock_mutex);
2803 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2803 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2804 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 2804 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2805 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2805 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2806 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2806 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2807 return clock; 2807 return clock;
2808} 2808}
2809 2809
2810static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2810static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2811{ 2811{
2812 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2813 gfx_v6_0_ring_emit_vgt_flush(ring);
2812 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2814 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2813 amdgpu_ring_write(ring, 0x80000000); 2815 amdgpu_ring_write(ring, 0x80000000);
2814 amdgpu_ring_write(ring, 0); 2816 amdgpu_ring_write(ring, 0);
2815} 2817}
2816 2818
2819
2820static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2821{
2822 WREG32(mmSQ_IND_INDEX,
2823 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2824 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2825 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2826 (SQ_IND_INDEX__FORCE_READ_MASK));
2827 return RREG32(mmSQ_IND_DATA);
2828}
2829
2830static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2831{
2832 /* type 0 wave data */
2833 dst[(*no_fields)++] = 0;
2834 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2835 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2836 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2837 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2838 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2839 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2840 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2841 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2842 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2843 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2844 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2845 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2846 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
2847 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
2848 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
2849 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
2850 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2851 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2852}
2853
2817static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 2854static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2818 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 2855 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2819 .select_se_sh = &gfx_v6_0_select_se_sh, 2856 .select_se_sh = &gfx_v6_0_select_se_sh,
2857 .read_wave_data = &gfx_v6_0_read_wave_data,
2820}; 2858};
2821 2859
2822static int gfx_v6_0_early_init(void *handle) 2860static int gfx_v6_0_early_init(void *handle)
@@ -2967,7 +3005,7 @@ static bool gfx_v6_0_is_idle(void *handle)
2967{ 3005{
2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969 3007
2970 if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3008 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2971 return false; 3009 return false;
2972 else 3010 else
2973 return true; 3011 return true;
@@ -2998,14 +3036,14 @@ static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2998 3036
2999 switch (state) { 3037 switch (state) {
3000 case AMDGPU_IRQ_STATE_DISABLE: 3038 case AMDGPU_IRQ_STATE_DISABLE:
3001 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3039 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3002 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3040 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3003 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3041 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3004 break; 3042 break;
3005 case AMDGPU_IRQ_STATE_ENABLE: 3043 case AMDGPU_IRQ_STATE_ENABLE:
3006 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3044 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3007 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3045 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3008 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3046 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3009 break; 3047 break;
3010 default: 3048 default:
3011 break; 3049 break;
@@ -3020,27 +3058,27 @@ static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3020 switch (state){ 3058 switch (state){
3021 case AMDGPU_IRQ_STATE_DISABLE: 3059 case AMDGPU_IRQ_STATE_DISABLE:
3022 if (ring == 0) { 3060 if (ring == 0) {
3023 cp_int_cntl = RREG32(CP_INT_CNTL_RING1); 3061 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3024 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3062 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3025 WREG32(CP_INT_CNTL_RING1, cp_int_cntl); 3063 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3026 break; 3064 break;
3027 } else { 3065 } else {
3028 cp_int_cntl = RREG32(CP_INT_CNTL_RING2); 3066 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3029 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3067 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3030 WREG32(CP_INT_CNTL_RING2, cp_int_cntl); 3068 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3031 break; 3069 break;
3032 3070
3033 } 3071 }
3034 case AMDGPU_IRQ_STATE_ENABLE: 3072 case AMDGPU_IRQ_STATE_ENABLE:
3035 if (ring == 0) { 3073 if (ring == 0) {
3036 cp_int_cntl = RREG32(CP_INT_CNTL_RING1); 3074 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3037 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3075 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3038 WREG32(CP_INT_CNTL_RING1, cp_int_cntl); 3076 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3039 break; 3077 break;
3040 } else { 3078 } else {
3041 cp_int_cntl = RREG32(CP_INT_CNTL_RING2); 3079 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3042 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3080 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3043 WREG32(CP_INT_CNTL_RING2, cp_int_cntl); 3081 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3044 break; 3082 break;
3045 3083
3046 } 3084 }
@@ -3061,14 +3099,14 @@ static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3061 3099
3062 switch (state) { 3100 switch (state) {
3063 case AMDGPU_IRQ_STATE_DISABLE: 3101 case AMDGPU_IRQ_STATE_DISABLE:
3064 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3102 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3065 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3103 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3066 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3104 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3067 break; 3105 break;
3068 case AMDGPU_IRQ_STATE_ENABLE: 3106 case AMDGPU_IRQ_STATE_ENABLE:
3069 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3107 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3070 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3108 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3071 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3109 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3072 break; 3110 break;
3073 default: 3111 default:
3074 break; 3112 break;
@@ -3086,14 +3124,14 @@ static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3086 3124
3087 switch (state) { 3125 switch (state) {
3088 case AMDGPU_IRQ_STATE_DISABLE: 3126 case AMDGPU_IRQ_STATE_DISABLE:
3089 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3127 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3090 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3128 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3091 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3129 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3092 break; 3130 break;
3093 case AMDGPU_IRQ_STATE_ENABLE: 3131 case AMDGPU_IRQ_STATE_ENABLE:
3094 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3132 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3095 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3133 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3096 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3134 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3097 break; 3135 break;
3098 default: 3136 default:
3099 break; 3137 break;
@@ -3133,7 +3171,7 @@ static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3133 break; 3171 break;
3134 case 1: 3172 case 1:
3135 case 2: 3173 case 2:
3136 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]); 3174 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3137 break; 3175 break;
3138 default: 3176 default:
3139 break; 3177 break;
@@ -3236,7 +3274,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3236 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3274 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3237 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3275 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3238 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3276 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3239 3, /* gfx_v6_ring_emit_cntxcntl */ 3277 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3240 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3278 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3241 .emit_ib = gfx_v6_0_ring_emit_ib, 3279 .emit_ib = gfx_v6_0_ring_emit_ib,
3242 .emit_fence = gfx_v6_0_ring_emit_fence, 3280 .emit_fence = gfx_v6_0_ring_emit_fence,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 5b631fd1a879..1a745cf93f47 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2105 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2105 amdgpu_ring_write(ring, 0x20); /* poll interval */
2106} 2106}
2107 2107
2108static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2109{
2110 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2111 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2112 EVENT_INDEX(4));
2113
2114 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2115 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2116 EVENT_INDEX(0));
2117}
2118
2119
2108/** 2120/**
2109 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 2121 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2110 * 2122 *
@@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2260 2272
2261 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2273 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2262 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2274 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2275 gfx_v7_0_ring_emit_vgt_flush(ring);
2263 /* set load_global_config & load_global_uconfig */ 2276 /* set load_global_config & load_global_uconfig */
2264 dw2 |= 0x8001; 2277 dw2 |= 0x8001;
2265 /* set load_cs_sh_regs */ 2278 /* set load_cs_sh_regs */
@@ -4359,7 +4372,11 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4359 4372
4360static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4373static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4361{ 4374{
4362 WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); 4375 WREG32(mmSQ_IND_INDEX,
4376 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4377 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4378 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4379 (SQ_IND_INDEX__FORCE_READ_MASK));
4363 return RREG32(mmSQ_IND_DATA); 4380 return RREG32(mmSQ_IND_DATA);
4364} 4381}
4365 4382
@@ -5149,7 +5166,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5149 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5166 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5150 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5167 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5151 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5168 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5152 3, /* gfx_v7_ring_emit_cntxcntl */ 5169 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5153 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5170 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5154 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5171 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5155 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5172 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 23f1bc94ad3e..a3684891c6e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3904,7 +3904,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3904 int list_size; 3904 int list_size;
3905 unsigned int *register_list_format = 3905 unsigned int *register_list_format =
3906 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 3906 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3907 if (register_list_format == NULL) 3907 if (!register_list_format)
3908 return -ENOMEM; 3908 return -ENOMEM;
3909 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 3909 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3910 adev->gfx.rlc.reg_list_format_size_bytes); 3910 adev->gfx.rlc.reg_list_format_size_bytes);
@@ -5442,7 +5442,11 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5442 5442
5443static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 5443static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5444{ 5444{
5445 WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); 5445 WREG32(mmSQ_IND_INDEX,
5446 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5447 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5448 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5449 (SQ_IND_INDEX__FORCE_READ_MASK));
5446 return RREG32(mmSQ_IND_DATA); 5450 return RREG32(mmSQ_IND_DATA);
5447} 5451}
5448 5452
@@ -6182,6 +6186,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6182 amdgpu_ring_write(ring, 0x20); /* poll interval */ 6186 amdgpu_ring_write(ring, 0x20); /* poll interval */
6183} 6187}
6184 6188
6189static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6190{
6191 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6192 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6193 EVENT_INDEX(4));
6194
6195 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6196 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6197 EVENT_INDEX(0));
6198}
6199
6200
6185static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 6201static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
6186{ 6202{
6187 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6203 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -6367,6 +6383,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6367 6383
6368 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6384 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6369 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6385 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6386 gfx_v8_0_ring_emit_vgt_flush(ring);
6370 /* set load_global_config & load_global_uconfig */ 6387 /* set load_global_config & load_global_uconfig */
6371 dw2 |= 0x8001; 6388 dw2 |= 0x8001;
6372 /* set load_cs_sh_regs */ 6389 /* set load_cs_sh_regs */
@@ -6570,7 +6587,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6570 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 6587 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6571 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ 6588 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
6572 2 + /* gfx_v8_ring_emit_sb */ 6589 2 + /* gfx_v8_ring_emit_sb */
6573 3, /* gfx_v8_ring_emit_cntxcntl */ 6590 3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */
6574 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ 6591 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6575 .emit_ib = gfx_v8_0_ring_emit_ib_gfx, 6592 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6576 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 6593 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 1940d36bc304..64d3c1e6014c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1,4 +1,3 @@
1
2/* 1/*
3 * Copyright 2014 Advanced Micro Devices, Inc. 2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * 3 *
@@ -26,7 +25,16 @@
26#include "amdgpu.h" 25#include "amdgpu.h"
27#include "gmc_v6_0.h" 26#include "gmc_v6_0.h"
28#include "amdgpu_ucode.h" 27#include "amdgpu_ucode.h"
29#include "si/sid.h" 28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
30 38
31static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); 39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
32static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -37,6 +45,16 @@ MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
37MODULE_FIRMWARE("radeon/verde_mc.bin"); 45MODULE_FIRMWARE("radeon/verde_mc.bin");
38MODULE_FIRMWARE("radeon/oland_mc.bin"); 46MODULE_FIRMWARE("radeon/oland_mc.bin");
39 47
48#define MC_SEQ_MISC0__MT__MASK 0xf0000000
49#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
50#define MC_SEQ_MISC0__MT__DDR2 0x20000000
51#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
52#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
53#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
54#define MC_SEQ_MISC0__MT__HBM 0x60000000
55#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
56
57
40static const u32 crtc_offsets[6] = 58static const u32 crtc_offsets[6] =
41{ 59{
42 SI_CRTC0_REGISTER_OFFSET, 60 SI_CRTC0_REGISTER_OFFSET,
@@ -57,14 +75,14 @@ static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
57 75
58 gmc_v6_0_wait_for_idle((void *)adev); 76 gmc_v6_0_wait_for_idle((void *)adev);
59 77
60 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 78 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
61 if (REG_GET_FIELD(blackout, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE) != 1) { 79 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
62 /* Block CPU access */ 80 /* Block CPU access */
63 WREG32(BIF_FB_EN, 0); 81 WREG32(mmBIF_FB_EN, 0);
64 /* blackout the MC */ 82 /* blackout the MC */
65 blackout = REG_SET_FIELD(blackout, 83 blackout = REG_SET_FIELD(blackout,
66 mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); 84 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
67 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 85 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
68 } 86 }
69 /* wait for the MC to settle */ 87 /* wait for the MC to settle */
70 udelay(100); 88 udelay(100);
@@ -77,13 +95,13 @@ static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
77 u32 tmp; 95 u32 tmp;
78 96
79 /* unblackout the MC */ 97 /* unblackout the MC */
80 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); 98 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
81 tmp = REG_SET_FIELD(tmp, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); 99 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
82 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); 100 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
83 /* allow CPU access */ 101 /* allow CPU access */
84 tmp = REG_SET_FIELD(0, mmBIF_FB_EN, xxFB_READ_EN, 1); 102 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
85 tmp = REG_SET_FIELD(tmp, mmBIF_FB_EN, xxFB_WRITE_EN, 1); 103 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
86 WREG32(BIF_FB_EN, tmp); 104 WREG32(mmBIF_FB_EN, tmp);
87 105
88 if (adev->mode_info.num_crtc) 106 if (adev->mode_info.num_crtc)
89 amdgpu_display_resume_mc_access(adev, save); 107 amdgpu_display_resume_mc_access(adev, save);
@@ -158,37 +176,37 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
158 new_fw_data = (const __le32 *) 176 new_fw_data = (const __le32 *)
159 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 177 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
160 178
161 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 179 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
162 180
163 if (running == 0) { 181 if (running == 0) {
164 182
165 /* reset the engine and set to writable */ 183 /* reset the engine and set to writable */
166 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 184 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
167 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
168 186
169 /* load mc io regs */ 187 /* load mc io regs */
170 for (i = 0; i < regs_size; i++) { 188 for (i = 0; i < regs_size; i++) {
171 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 189 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
172 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 190 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
173 } 191 }
174 /* load the MC ucode */ 192 /* load the MC ucode */
175 for (i = 0; i < ucode_size; i++) { 193 for (i = 0; i < ucode_size; i++) {
176 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 194 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
177 } 195 }
178 196
179 /* put the engine back into the active state */ 197 /* put the engine back into the active state */
180 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
181 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
182 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
183 201
184 /* wait for training to complete */ 202 /* wait for training to complete */
185 for (i = 0; i < adev->usec_timeout; i++) { 203 for (i = 0; i < adev->usec_timeout; i++) {
186 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) 204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
187 break; 205 break;
188 udelay(1); 206 udelay(1);
189 } 207 }
190 for (i = 0; i < adev->usec_timeout; i++) { 208 for (i = 0; i < adev->usec_timeout; i++) {
191 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) 209 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
192 break; 210 break;
193 udelay(1); 211 udelay(1);
194 } 212 }
@@ -225,7 +243,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
225 WREG32((0xb08 + j), 0x00000000); 243 WREG32((0xb08 + j), 0x00000000);
226 WREG32((0xb09 + j), 0x00000000); 244 WREG32((0xb09 + j), 0x00000000);
227 } 245 }
228 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 246 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
229 247
230 gmc_v6_0_mc_stop(adev, &save); 248 gmc_v6_0_mc_stop(adev, &save);
231 249
@@ -233,24 +251,24 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
233 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 251 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
234 } 252 }
235 253
236 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 254 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
237 /* Update configuration */ 255 /* Update configuration */
238 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 256 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
239 adev->mc.vram_start >> 12); 257 adev->mc.vram_start >> 12);
240 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 258 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
241 adev->mc.vram_end >> 12); 259 adev->mc.vram_end >> 12);
242 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 260 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
243 adev->vram_scratch.gpu_addr >> 12); 261 adev->vram_scratch.gpu_addr >> 12);
244 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 262 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
245 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 263 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
246 WREG32(MC_VM_FB_LOCATION, tmp); 264 WREG32(mmMC_VM_FB_LOCATION, tmp);
247 /* XXX double check these! */ 265 /* XXX double check these! */
248 WREG32(HDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 266 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
249 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 267 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
250 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 268 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
251 WREG32(MC_VM_AGP_BASE, 0); 269 WREG32(mmMC_VM_AGP_BASE, 0);
252 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 270 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
253 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 271 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
254 272
255 if (gmc_v6_0_wait_for_idle((void *)adev)) { 273 if (gmc_v6_0_wait_for_idle((void *)adev)) {
256 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 274 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
@@ -265,16 +283,16 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
265 u32 tmp; 283 u32 tmp;
266 int chansize, numchan; 284 int chansize, numchan;
267 285
268 tmp = RREG32(MC_ARB_RAMCFG); 286 tmp = RREG32(mmMC_ARB_RAMCFG);
269 if (tmp & CHANSIZE_OVERRIDE) { 287 if (tmp & (1 << 11)) {
270 chansize = 16; 288 chansize = 16;
271 } else if (tmp & CHANSIZE_MASK) { 289 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
272 chansize = 64; 290 chansize = 64;
273 } else { 291 } else {
274 chansize = 32; 292 chansize = 32;
275 } 293 }
276 tmp = RREG32(MC_SHARED_CHMAP); 294 tmp = RREG32(mmMC_SHARED_CHMAP);
277 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 295 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
278 case 0: 296 case 0:
279 default: 297 default:
280 numchan = 1; 298 numchan = 1;
@@ -309,8 +327,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
309 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 327 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
310 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 328 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
311 /* size in MB on si */ 329 /* size in MB on si */
312 adev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 330 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
313 adev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 331 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
314 adev->mc.visible_vram_size = adev->mc.aper_size; 332 adev->mc.visible_vram_size = adev->mc.aper_size;
315 333
316 /* unless the user had overridden it, set the gart 334 /* unless the user had overridden it, set the gart
@@ -329,9 +347,9 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
329static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 347static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
330 uint32_t vmid) 348 uint32_t vmid)
331{ 349{
332 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); 350 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
333 351
334 WREG32(VM_INVALIDATE_REQUEST, 1 << vmid); 352 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
335} 353}
336 354
337static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, 355static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
@@ -355,20 +373,20 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
355{ 373{
356 u32 tmp; 374 u32 tmp;
357 375
358 tmp = RREG32(VM_CONTEXT1_CNTL); 376 tmp = RREG32(mmVM_CONTEXT1_CNTL);
359 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 377 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
360 xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 378 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
361 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 379 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
362 xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 380 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
363 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 381 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
364 xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 382 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
365 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 383 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
366 xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 384 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
367 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 385 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
368 xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT, value); 386 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
369 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 387 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
370 xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 388 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
371 WREG32(VM_CONTEXT1_CNTL, tmp); 389 WREG32(mmVM_CONTEXT1_CNTL, tmp);
372} 390}
373 391
374static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 392static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
@@ -383,33 +401,39 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
383 if (r) 401 if (r)
384 return r; 402 return r;
385 /* Setup TLB control */ 403 /* Setup TLB control */
386 WREG32(MC_VM_MX_L1_TLB_CNTL, 404 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
387 (0xA << 7) | 405 (0xA << 7) |
388 ENABLE_L1_TLB | 406 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
389 ENABLE_L1_FRAGMENT_PROCESSING | 407 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
390 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 408 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
391 ENABLE_ADVANCED_DRIVER_MODEL | 409 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
392 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 410 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
393 /* Setup L2 cache */ 411 /* Setup L2 cache */
394 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 412 WREG32(mmVM_L2_CNTL,
395 ENABLE_L2_FRAGMENT_PROCESSING | 413 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
396 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 414 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
397 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 415 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
398 EFFECTIVE_L2_QUEUE_SIZE(7) | 416 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
399 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 417 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
400 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 418 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
401 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 419 WREG32(mmVM_L2_CNTL2,
402 BANK_SELECT(4) | 420 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
403 L2_CACHE_BIGK_FRAGMENT_SIZE(4)); 421 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
422 WREG32(mmVM_L2_CNTL3,
423 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
424 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
425 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
404 /* setup context0 */ 426 /* setup context0 */
405 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 427 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
406 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 428 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
407 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 429 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
408 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 430 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
409 (u32)(adev->dummy_page.addr >> 12)); 431 (u32)(adev->dummy_page.addr >> 12));
410 WREG32(VM_CONTEXT0_CNTL2, 0); 432 WREG32(mmVM_CONTEXT0_CNTL2, 0);
411 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 433 WREG32(mmVM_CONTEXT0_CNTL,
412 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); 434 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
435 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
436 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
413 437
414 WREG32(0x575, 0); 438 WREG32(0x575, 0);
415 WREG32(0x576, 0); 439 WREG32(0x576, 0);
@@ -417,39 +441,41 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
417 441
418 /* empty context1-15 */ 442 /* empty context1-15 */
419 /* set vm size, must be a multiple of 4 */ 443 /* set vm size, must be a multiple of 4 */
420 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 444 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
421 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 445 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
422 /* Assign the pt base to something valid for now; the pts used for 446 /* Assign the pt base to something valid for now; the pts used for
423 * the VMs are determined by the application and setup and assigned 447 * the VMs are determined by the application and setup and assigned
424 * on the fly in the vm part of radeon_gart.c 448 * on the fly in the vm part of radeon_gart.c
425 */ 449 */
426 for (i = 1; i < 16; i++) { 450 for (i = 1; i < 16; i++) {
427 if (i < 8) 451 if (i < 8)
428 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 452 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
429 adev->gart.table_addr >> 12); 453 adev->gart.table_addr >> 12);
430 else 454 else
431 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 455 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
432 adev->gart.table_addr >> 12); 456 adev->gart.table_addr >> 12);
433 } 457 }
434 458
435 /* enable context1-15 */ 459 /* enable context1-15 */
436 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 460 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
437 (u32)(adev->dummy_page.addr >> 12)); 461 (u32)(adev->dummy_page.addr >> 12));
438 WREG32(VM_CONTEXT1_CNTL2, 4); 462 WREG32(mmVM_CONTEXT1_CNTL2, 4);
439 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 463 WREG32(mmVM_CONTEXT1_CNTL,
440 PAGE_TABLE_BLOCK_SIZE(amdgpu_vm_block_size - 9) | 464 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
441 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 465 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
442 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 466 ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) |
443 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 467 VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
444 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 468 VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
445 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 469 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
446 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 470 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
447 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 471 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
448 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 472 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
449 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 473 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
450 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
451 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
452 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 476 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
477 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
453 479
454 gmc_v6_0_gart_flush_gpu_tlb(adev, 0); 480 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
455 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 481 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
@@ -488,19 +514,22 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
488 }*/ 514 }*/
489 515
490 /* Disable all tables */ 516 /* Disable all tables */
491 WREG32(VM_CONTEXT0_CNTL, 0); 517 WREG32(mmVM_CONTEXT0_CNTL, 0);
492 WREG32(VM_CONTEXT1_CNTL, 0); 518 WREG32(mmVM_CONTEXT1_CNTL, 0);
493 /* Setup TLB control */ 519 /* Setup TLB control */
494 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | 520 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
495 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 521 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
522 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
496 /* Setup L2 cache */ 523 /* Setup L2 cache */
497 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 524 WREG32(mmVM_L2_CNTL,
498 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 525 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
499 EFFECTIVE_L2_QUEUE_SIZE(7) | 526 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
500 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 527 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
501 WREG32(VM_L2_CNTL2, 0); 528 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
502 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 529 WREG32(mmVM_L2_CNTL2, 0);
503 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 530 WREG32(mmVM_L2_CNTL3,
531 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
532 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
504 amdgpu_gart_table_vram_unpin(adev); 533 amdgpu_gart_table_vram_unpin(adev);
505} 534}
506 535
@@ -523,7 +552,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
523 552
524 /* base offset of vram pages */ 553 /* base offset of vram pages */
525 if (adev->flags & AMD_IS_APU) { 554 if (adev->flags & AMD_IS_APU) {
526 u64 tmp = RREG32(MC_VM_FB_OFFSET); 555 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
527 tmp <<= 22; 556 tmp <<= 22;
528 adev->vm_manager.vram_base_offset = tmp; 557 adev->vm_manager.vram_base_offset = tmp;
529 } else 558 } else
@@ -540,19 +569,19 @@ static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
540 u32 status, u32 addr, u32 mc_client) 569 u32 status, u32 addr, u32 mc_client)
541{ 570{
542 u32 mc_id; 571 u32 mc_id;
543 u32 vmid = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, xxVMID); 572 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
544 u32 protections = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, 573 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
545 xxPROTECTIONS); 574 PROTECTIONS);
546 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 575 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
547 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 576 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
548 577
549 mc_id = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, 578 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
550 xxMEMORY_CLIENT_ID); 579 MEMORY_CLIENT_ID);
551 580
552 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 581 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
553 protections, vmid, addr, 582 protections, vmid, addr,
554 REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, 583 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
555 xxMEMORY_CLIENT_RW) ? 584 MEMORY_CLIENT_RW) ?
556 "write" : "read", block, mc_client, mc_id); 585 "write" : "read", block, mc_client, mc_id);
557} 586}
558 587
@@ -655,7 +684,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
655{ 684{
656 u32 orig, data; 685 u32 orig, data;
657 686
658 orig = data = RREG32(HDP_HOST_PATH_CNTL); 687 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
659 688
660 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 689 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
661 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 690 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
@@ -663,7 +692,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
663 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 692 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
664 693
665 if (orig != data) 694 if (orig != data)
666 WREG32(HDP_HOST_PATH_CNTL, data); 695 WREG32(mmHDP_HOST_PATH_CNTL, data);
667} 696}
668 697
669static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 698static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
@@ -671,7 +700,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
671{ 700{
672 u32 orig, data; 701 u32 orig, data;
673 702
674 orig = data = RREG32(HDP_MEM_POWER_LS); 703 orig = data = RREG32(mmHDP_MEM_POWER_LS);
675 704
676 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 705 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
677 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 706 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
@@ -679,7 +708,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
679 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 708 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
680 709
681 if (orig != data) 710 if (orig != data)
682 WREG32(HDP_MEM_POWER_LS, data); 711 WREG32(mmHDP_MEM_POWER_LS, data);
683} 712}
684*/ 713*/
685 714
@@ -713,7 +742,7 @@ static int gmc_v6_0_early_init(void *handle)
713 if (adev->flags & AMD_IS_APU) { 742 if (adev->flags & AMD_IS_APU) {
714 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 743 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
715 } else { 744 } else {
716 u32 tmp = RREG32(MC_SEQ_MISC0); 745 u32 tmp = RREG32(mmMC_SEQ_MISC0);
717 tmp &= MC_SEQ_MISC0__MT__MASK; 746 tmp &= MC_SEQ_MISC0__MT__MASK;
718 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); 747 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
719 } 748 }
@@ -879,7 +908,7 @@ static int gmc_v6_0_resume(void *handle)
879static bool gmc_v6_0_is_idle(void *handle) 908static bool gmc_v6_0_is_idle(void *handle)
880{ 909{
881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
882 u32 tmp = RREG32(SRBM_STATUS); 911 u32 tmp = RREG32(mmSRBM_STATUS);
883 912
884 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 913 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
885 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 914 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
@@ -895,7 +924,7 @@ static int gmc_v6_0_wait_for_idle(void *handle)
895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896 925
897 for (i = 0; i < adev->usec_timeout; i++) { 926 for (i = 0; i < adev->usec_timeout; i++) {
898 tmp = RREG32(SRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 927 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
899 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 928 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
900 SRBM_STATUS__MCC_BUSY_MASK | 929 SRBM_STATUS__MCC_BUSY_MASK |
901 SRBM_STATUS__MCD_BUSY_MASK | 930 SRBM_STATUS__MCD_BUSY_MASK |
@@ -913,17 +942,17 @@ static int gmc_v6_0_soft_reset(void *handle)
913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914 struct amdgpu_mode_mc_save save; 943 struct amdgpu_mode_mc_save save;
915 u32 srbm_soft_reset = 0; 944 u32 srbm_soft_reset = 0;
916 u32 tmp = RREG32(SRBM_STATUS); 945 u32 tmp = RREG32(mmSRBM_STATUS);
917 946
918 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 947 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
919 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 948 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
920 mmSRBM_SOFT_RESET, xxSOFT_RESET_VMC, 1); 949 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
921 950
922 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 951 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
923 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 952 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
924 if (!(adev->flags & AMD_IS_APU)) 953 if (!(adev->flags & AMD_IS_APU))
925 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 954 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
926 mmSRBM_SOFT_RESET, xxSOFT_RESET_MC, 1); 955 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
927 } 956 }
928 957
929 if (srbm_soft_reset) { 958 if (srbm_soft_reset) {
@@ -933,17 +962,17 @@ static int gmc_v6_0_soft_reset(void *handle)
933 } 962 }
934 963
935 964
936 tmp = RREG32(SRBM_SOFT_RESET); 965 tmp = RREG32(mmSRBM_SOFT_RESET);
937 tmp |= srbm_soft_reset; 966 tmp |= srbm_soft_reset;
938 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 967 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
939 WREG32(SRBM_SOFT_RESET, tmp); 968 WREG32(mmSRBM_SOFT_RESET, tmp);
940 tmp = RREG32(SRBM_SOFT_RESET); 969 tmp = RREG32(mmSRBM_SOFT_RESET);
941 970
942 udelay(50); 971 udelay(50);
943 972
944 tmp &= ~srbm_soft_reset; 973 tmp &= ~srbm_soft_reset;
945 WREG32(SRBM_SOFT_RESET, tmp); 974 WREG32(mmSRBM_SOFT_RESET, tmp);
946 tmp = RREG32(SRBM_SOFT_RESET); 975 tmp = RREG32(mmSRBM_SOFT_RESET);
947 976
948 udelay(50); 977 udelay(50);
949 978
@@ -969,20 +998,20 @@ static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
969 998
970 switch (state) { 999 switch (state) {
971 case AMDGPU_IRQ_STATE_DISABLE: 1000 case AMDGPU_IRQ_STATE_DISABLE:
972 tmp = RREG32(VM_CONTEXT0_CNTL); 1001 tmp = RREG32(mmVM_CONTEXT0_CNTL);
973 tmp &= ~bits; 1002 tmp &= ~bits;
974 WREG32(VM_CONTEXT0_CNTL, tmp); 1003 WREG32(mmVM_CONTEXT0_CNTL, tmp);
975 tmp = RREG32(VM_CONTEXT1_CNTL); 1004 tmp = RREG32(mmVM_CONTEXT1_CNTL);
976 tmp &= ~bits; 1005 tmp &= ~bits;
977 WREG32(VM_CONTEXT1_CNTL, tmp); 1006 WREG32(mmVM_CONTEXT1_CNTL, tmp);
978 break; 1007 break;
979 case AMDGPU_IRQ_STATE_ENABLE: 1008 case AMDGPU_IRQ_STATE_ENABLE:
980 tmp = RREG32(VM_CONTEXT0_CNTL); 1009 tmp = RREG32(mmVM_CONTEXT0_CNTL);
981 tmp |= bits; 1010 tmp |= bits;
982 WREG32(VM_CONTEXT0_CNTL, tmp); 1011 WREG32(mmVM_CONTEXT0_CNTL, tmp);
983 tmp = RREG32(VM_CONTEXT1_CNTL); 1012 tmp = RREG32(mmVM_CONTEXT1_CNTL);
984 tmp |= bits; 1013 tmp |= bits;
985 WREG32(VM_CONTEXT1_CNTL, tmp); 1014 WREG32(mmVM_CONTEXT1_CNTL, tmp);
986 break; 1015 break;
987 default: 1016 default:
988 break; 1017 break;
@@ -997,9 +1026,9 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
997{ 1026{
998 u32 addr, status; 1027 u32 addr, status;
999 1028
1000 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); 1029 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1001 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); 1030 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1002 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 1031 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1003 1032
1004 if (!addr && !status) 1033 if (!addr && !status)
1005 return 0; 1034 return 0;
@@ -1007,13 +1036,15 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1007 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1036 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1008 gmc_v6_0_set_fault_enable_default(adev, false); 1037 gmc_v6_0_set_fault_enable_default(adev, false);
1009 1038
1010 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1039 if (printk_ratelimit()) {
1011 entry->src_id, entry->src_data); 1040 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1012 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1041 entry->src_id, entry->src_data);
1013 addr); 1042 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1014 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1043 addr);
1015 status); 1044 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1016 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1045 status);
1046 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1047 }
1017 1048
1018 return 0; 1049 return 0;
1019} 1050}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 3a25f72980c1..fbe1d9ac500a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
711 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 711 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
712 MEMORY_CLIENT_ID); 712 MEMORY_CLIENT_ID);
713 713
714 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 714 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
715 protections, vmid, addr, 715 protections, vmid, addr,
716 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 716 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
717 MEMORY_CLIENT_RW) ? 717 MEMORY_CLIENT_RW) ?
@@ -1198,13 +1198,15 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1198 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1198 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1199 gmc_v7_0_set_fault_enable_default(adev, false); 1199 gmc_v7_0_set_fault_enable_default(adev, false);
1200 1200
1201 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1201 if (printk_ratelimit()) {
1202 entry->src_id, entry->src_data); 1202 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1203 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1203 entry->src_id, entry->src_data);
1204 addr); 1204 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1205 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1205 addr);
1206 status); 1206 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1207 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); 1207 status);
1208 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1209 }
1208 1210
1209 return 0; 1211 return 0;
1210} 1212}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f7372d32b8e7..12ea3404dd65 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
837 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 837 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
838 MEMORY_CLIENT_ID); 838 MEMORY_CLIENT_ID);
839 839
840 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 840 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
841 protections, vmid, addr, 841 protections, vmid, addr,
842 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 842 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
843 MEMORY_CLIENT_RW) ? 843 MEMORY_CLIENT_RW) ?
@@ -1242,13 +1242,15 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1242 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1242 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1243 gmc_v8_0_set_fault_enable_default(adev, false); 1243 gmc_v8_0_set_fault_enable_default(adev, false);
1244 1244
1245 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1245 if (printk_ratelimit()) {
1246 entry->src_id, entry->src_data); 1246 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1247 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1247 entry->src_id, entry->src_data);
1248 addr); 1248 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1249 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1249 addr);
1250 status); 1250 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1251 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1251 status);
1252 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1253 }
1252 1254
1253 return 0; 1255 return 0;
1254} 1256}
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 61172d4a0657..5a1bc358bcb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2845,7 +2845,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
2845 pi->caps_tcp_ramping = true; 2845 pi->caps_tcp_ramping = true;
2846 } 2846 }
2847 2847
2848 if (amdgpu_sclk_deep_sleep_en) 2848 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
2849 pi->caps_sclk_ds = true; 2849 pi->caps_sclk_ds = true;
2850 else 2850 else
2851 pi->caps_sclk_ds = false; 2851 pi->caps_sclk_ds = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index e81aa4682760..fbe74a33899c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -775,11 +775,11 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
775 unsigned ndw = count * 2; 775 unsigned ndw = count * 2;
776 776
777 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 777 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
778 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 778 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
779 ib->ptr[ib->length_dw++] = pe; 779 ib->ptr[ib->length_dw++] = pe;
780 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 780 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
781 ib->ptr[ib->length_dw++] = ndw; 781 ib->ptr[ib->length_dw++] = ndw;
782 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 782 for (; ndw > 0; ndw -= 2) {
783 ib->ptr[ib->length_dw++] = lower_32_bits(value); 783 ib->ptr[ib->length_dw++] = lower_32_bits(value);
784 ib->ptr[ib->length_dw++] = upper_32_bits(value); 784 ib->ptr[ib->length_dw++] = upper_32_bits(value);
785 value += incr; 785 value += incr;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 77f146587c60..1170a64a3184 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -977,11 +977,11 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
977 unsigned ndw = count * 2; 977 unsigned ndw = count * 2;
978 978
979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
981 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 981 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
982 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 982 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
983 ib->ptr[ib->length_dw++] = ndw; 983 ib->ptr[ib->length_dw++] = ndw;
984 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 984 for (; ndw > 0; ndw -= 2) {
985 ib->ptr[ib->length_dw++] = lower_32_bits(value); 985 ib->ptr[ib->length_dw++] = lower_32_bits(value);
986 ib->ptr[ib->length_dw++] = upper_32_bits(value); 986 ib->ptr[ib->length_dw++] = upper_32_bits(value);
987 value += incr; 987 value += incr;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
new file mode 100644
index 000000000000..fde2086246fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -0,0 +1,272 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef SI_ENUMS_H
24#define SI_ENUMS_H
25
26#define VBLANK_INT_MASK (1 << 0)
27#define DC_HPDx_INT_EN (1 << 16)
28#define VBLANK_ACK (1 << 4)
29#define VLINE_ACK (1 << 4)
30
31#define CURSOR_WIDTH 64
32#define CURSOR_HEIGHT 64
33
34#define VGA_VSTATUS_CNTL 0xFFFCFFFF
35#define PRIORITY_MARK_MASK 0x7fff
36#define PRIORITY_OFF (1 << 16)
37#define PRIORITY_ALWAYS_ON (1 << 20)
38#define INTERLEAVE_EN (1 << 0)
39
40#define LATENCY_WATERMARK_MASK(x) ((x) << 16)
41#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
42#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
43
44#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
45#define GRPH_ENDIAN_NONE 0
46#define GRPH_ENDIAN_8IN16 1
47#define GRPH_ENDIAN_8IN32 2
48#define GRPH_ENDIAN_8IN64 3
49
50#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
51#define GRPH_DEPTH_8BPP 0
52#define GRPH_DEPTH_16BPP 1
53#define GRPH_DEPTH_32BPP 2
54
55#define GRPH_FORMAT(x) (((x) & 0x7) << 8)
56#define GRPH_FORMAT_INDEXED 0
57#define GRPH_FORMAT_ARGB1555 0
58#define GRPH_FORMAT_ARGB565 1
59#define GRPH_FORMAT_ARGB4444 2
60#define GRPH_FORMAT_AI88 3
61#define GRPH_FORMAT_MONO16 4
62#define GRPH_FORMAT_BGRA5551 5
63#define GRPH_FORMAT_ARGB8888 0
64#define GRPH_FORMAT_ARGB2101010 1
65#define GRPH_FORMAT_32BPP_DIG 2
66#define GRPH_FORMAT_8B_ARGB2101010 3
67#define GRPH_FORMAT_BGRA1010102 4
68#define GRPH_FORMAT_8B_BGRA1010102 5
69#define GRPH_FORMAT_RGB111110 6
70#define GRPH_FORMAT_BGR101111 7
71
72#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
73#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
74#define GRPH_ARRAY_LINEAR_GENERAL 0
75#define GRPH_ARRAY_LINEAR_ALIGNED 1
76#define GRPH_ARRAY_1D_TILED_THIN1 2
77#define GRPH_ARRAY_2D_TILED_THIN1 4
78#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
79#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
80#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
81#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
82#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
83#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
84
85#define CURSOR_EN (1 << 0)
86#define CURSOR_MODE(x) (((x) & 0x3) << 8)
87#define CURSOR_MONO 0
88#define CURSOR_24_1 1
89#define CURSOR_24_8_PRE_MULT 2
90#define CURSOR_24_8_UNPRE_MULT 3
91#define CURSOR_2X_MAGNIFY (1 << 16)
92#define CURSOR_FORCE_MC_ON (1 << 20)
93#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
94#define CURSOR_URGENT_ALWAYS 0
95#define CURSOR_URGENT_1_8 1
96#define CURSOR_URGENT_1_4 2
97#define CURSOR_URGENT_3_8 3
98#define CURSOR_URGENT_1_2 4
99#define CURSOR_UPDATE_PENDING (1 << 0)
100#define CURSOR_UPDATE_TAKEN (1 << 1)
101#define CURSOR_UPDATE_LOCK (1 << 16)
102#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
103
104#define AMDGPU_NUM_OF_VMIDS 8
105#define SI_CRTC0_REGISTER_OFFSET 0
106#define SI_CRTC1_REGISTER_OFFSET 0x300
107#define SI_CRTC2_REGISTER_OFFSET 0x2600
108#define SI_CRTC3_REGISTER_OFFSET 0x2900
109#define SI_CRTC4_REGISTER_OFFSET 0x2c00
110#define SI_CRTC5_REGISTER_OFFSET 0x2f00
111
112#define DMA0_REGISTER_OFFSET 0x000
113#define DMA1_REGISTER_OFFSET 0x200
114#define ES_AND_GS_AUTO 3
115#define RADEON_PACKET_TYPE3 3
116#define CE_PARTITION_BASE 3
117#define BUF_SWAP_32BIT (2 << 16)
118
119#define GFX_POWER_STATUS (1 << 1)
120#define GFX_CLOCK_STATUS (1 << 2)
121#define GFX_LS_STATUS (1 << 3)
122#define RLC_BUSY_STATUS (1 << 0)
123
124#define RLC_PUD(x) ((x) << 0)
125#define RLC_PUD_MASK (0xff << 0)
126#define RLC_PDD(x) ((x) << 8)
127#define RLC_PDD_MASK (0xff << 8)
128#define RLC_TTPD(x) ((x) << 16)
129#define RLC_TTPD_MASK (0xff << 16)
130#define RLC_MSD(x) ((x) << 24)
131#define RLC_MSD_MASK (0xff << 24)
132#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
133#define WRITE_DATA_DST_SEL(x) ((x) << 8)
134#define EVENT_TYPE(x) ((x) << 0)
135#define EVENT_INDEX(x) ((x) << 8)
136#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
137#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
138#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
139
140#define GFX6_NUM_GFX_RINGS 1
141#define GFX6_NUM_COMPUTE_RINGS 2
142#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
143#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
144
145#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
146#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
147#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
148
149#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
150 (((op) & 0xFF) << 8) | \
151 ((n) & 0x3FFF) << 16)
152#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
153#define PACKET3_NOP 0x10
154#define PACKET3_SET_BASE 0x11
155#define PACKET3_BASE_INDEX(x) ((x) << 0)
156#define PACKET3_CLEAR_STATE 0x12
157#define PACKET3_INDEX_BUFFER_SIZE 0x13
158#define PACKET3_DISPATCH_DIRECT 0x15
159#define PACKET3_DISPATCH_INDIRECT 0x16
160#define PACKET3_ALLOC_GDS 0x1B
161#define PACKET3_WRITE_GDS_RAM 0x1C
162#define PACKET3_ATOMIC_GDS 0x1D
163#define PACKET3_ATOMIC 0x1E
164#define PACKET3_OCCLUSION_QUERY 0x1F
165#define PACKET3_SET_PREDICATION 0x20
166#define PACKET3_REG_RMW 0x21
167#define PACKET3_COND_EXEC 0x22
168#define PACKET3_PRED_EXEC 0x23
169#define PACKET3_DRAW_INDIRECT 0x24
170#define PACKET3_DRAW_INDEX_INDIRECT 0x25
171#define PACKET3_INDEX_BASE 0x26
172#define PACKET3_DRAW_INDEX_2 0x27
173#define PACKET3_CONTEXT_CONTROL 0x28
174#define PACKET3_INDEX_TYPE 0x2A
175#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
176#define PACKET3_DRAW_INDEX_AUTO 0x2D
177#define PACKET3_DRAW_INDEX_IMMD 0x2E
178#define PACKET3_NUM_INSTANCES 0x2F
179#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
180#define PACKET3_INDIRECT_BUFFER_CONST 0x31
181#define PACKET3_INDIRECT_BUFFER 0x3F
182#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
183#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
184#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
185#define PACKET3_WRITE_DATA 0x37
186#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
187#define PACKET3_MEM_SEMAPHORE 0x39
188#define PACKET3_MPEG_INDEX 0x3A
189#define PACKET3_COPY_DW 0x3B
190#define PACKET3_WAIT_REG_MEM 0x3C
191#define PACKET3_MEM_WRITE 0x3D
192#define PACKET3_COPY_DATA 0x40
193#define PACKET3_CP_DMA 0x41
194# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
195# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
196# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
197# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
198# define PACKET3_CP_DMA_DIS_WC (1 << 21)
199# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
200# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
201# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
202# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
203# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
204# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
205# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
206#define PACKET3_PFP_SYNC_ME 0x42
207#define PACKET3_SURFACE_SYNC 0x43
208# define PACKET3_DEST_BASE_0_ENA (1 << 0)
209# define PACKET3_DEST_BASE_1_ENA (1 << 1)
210# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
211# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
212# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
213# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
214# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
215# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
216# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
217# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
218# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
219# define PACKET3_DEST_BASE_2_ENA (1 << 19)
220# define PACKET3_DEST_BASE_3_ENA (1 << 21)
221# define PACKET3_TCL1_ACTION_ENA (1 << 22)
222# define PACKET3_TC_ACTION_ENA (1 << 23)
223# define PACKET3_CB_ACTION_ENA (1 << 25)
224# define PACKET3_DB_ACTION_ENA (1 << 26)
225# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
226# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
227#define PACKET3_ME_INITIALIZE 0x44
228#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
229#define PACKET3_COND_WRITE 0x45
230#define PACKET3_EVENT_WRITE 0x46
231#define PACKET3_EVENT_WRITE_EOP 0x47
232#define PACKET3_EVENT_WRITE_EOS 0x48
233#define PACKET3_PREAMBLE_CNTL 0x4A
234# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
235# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
236#define PACKET3_ONE_REG_WRITE 0x57
237#define PACKET3_LOAD_CONFIG_REG 0x5F
238#define PACKET3_LOAD_CONTEXT_REG 0x60
239#define PACKET3_LOAD_SH_REG 0x61
240#define PACKET3_SET_CONFIG_REG 0x68
241#define PACKET3_SET_CONFIG_REG_START 0x00002000
242#define PACKET3_SET_CONFIG_REG_END 0x00002c00
243#define PACKET3_SET_CONTEXT_REG 0x69
244#define PACKET3_SET_CONTEXT_REG_START 0x000a000
245#define PACKET3_SET_CONTEXT_REG_END 0x000a400
246#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
247#define PACKET3_SET_RESOURCE_INDIRECT 0x74
248#define PACKET3_SET_SH_REG 0x76
249#define PACKET3_SET_SH_REG_START 0x00002c00
250#define PACKET3_SET_SH_REG_END 0x00003000
251#define PACKET3_SET_SH_REG_OFFSET 0x77
252#define PACKET3_ME_WRITE 0x7A
253#define PACKET3_SCRATCH_RAM_WRITE 0x7D
254#define PACKET3_SCRATCH_RAM_READ 0x7E
255#define PACKET3_CE_WRITE 0x7F
256#define PACKET3_LOAD_CONST_RAM 0x80
257#define PACKET3_WRITE_CONST_RAM 0x81
258#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
259#define PACKET3_DUMP_CONST_RAM 0x83
260#define PACKET3_INCREMENT_CE_COUNTER 0x84
261#define PACKET3_INCREMENT_DE_COUNTER 0x85
262#define PACKET3_WAIT_ON_CE_COUNTER 0x86
263#define PACKET3_WAIT_ON_DE_COUNTER 0x87
264#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
265#define PACKET3_SET_CE_DE_COUNTERS 0x89
266#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
267#define PACKET3_SWITCH_BUFFER 0x8B
268#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
269#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
270#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
271
272#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 8f9c7d55ddda..96444e4d862a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -45,7 +45,8 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
45static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
46static int uvd_v4_2_start(struct amdgpu_device *adev); 46static int uvd_v4_2_start(struct amdgpu_device *adev);
47static void uvd_v4_2_stop(struct amdgpu_device *adev); 47static void uvd_v4_2_stop(struct amdgpu_device *adev);
48 48static int uvd_v4_2_set_clockgating_state(void *handle,
49 enum amd_clockgating_state state);
49/** 50/**
50 * uvd_v4_2_ring_get_rptr - get read pointer 51 * uvd_v4_2_ring_get_rptr - get read pointer
51 * 52 *
@@ -154,9 +155,9 @@ static int uvd_v4_2_hw_init(void *handle)
154 uint32_t tmp; 155 uint32_t tmp;
155 int r; 156 int r;
156 157
157 /* raise clocks while booting up the VCPU */ 158 uvd_v4_2_init_cg(adev);
158 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 159 uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE);
159 160 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
160 r = uvd_v4_2_start(adev); 161 r = uvd_v4_2_start(adev);
161 if (r) 162 if (r)
162 goto done; 163 goto done;
@@ -196,8 +197,6 @@ static int uvd_v4_2_hw_init(void *handle)
196 amdgpu_ring_commit(ring); 197 amdgpu_ring_commit(ring);
197 198
198done: 199done:
199 /* lower clocks again */
200 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
201 200
202 if (!r) 201 if (!r)
203 DRM_INFO("UVD initialized successfully.\n"); 202 DRM_INFO("UVD initialized successfully.\n");
@@ -274,9 +273,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
274 273
275 uvd_v4_2_mc_resume(adev); 274 uvd_v4_2_mc_resume(adev);
276 275
277 /* disable clock gating */
278 WREG32(mmUVD_CGC_GATE, 0);
279
280 /* disable interupt */ 276 /* disable interupt */
281 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 277 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
282 278
@@ -568,8 +564,6 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
568 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 564 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
569 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 565 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
570 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 566 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
571
572 uvd_v4_2_init_cg(adev);
573} 567}
574 568
575static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 569static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
@@ -579,7 +573,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
579 573
580 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 574 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
581 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 575 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
582 data = 0xfff; 576 data |= 0xfff;
583 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 577 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
584 578
585 orig = data = RREG32(mmUVD_CGC_CTRL); 579 orig = data = RREG32(mmUVD_CGC_CTRL);
@@ -603,6 +597,8 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
603{ 597{
604 u32 tmp, tmp2; 598 u32 tmp, tmp2;
605 599
600 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
601
606 tmp = RREG32(mmUVD_CGC_CTRL); 602 tmp = RREG32(mmUVD_CGC_CTRL);
607 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 603 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
608 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 604 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
@@ -686,34 +682,18 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
686 return 0; 682 return 0;
687} 683}
688 684
689static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
690{
691 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
692
693 if (enable)
694 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
695 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
696 else
697 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
698 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
699
700 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
701}
702
703static int uvd_v4_2_set_clockgating_state(void *handle, 685static int uvd_v4_2_set_clockgating_state(void *handle,
704 enum amd_clockgating_state state) 686 enum amd_clockgating_state state)
705{ 687{
706 bool gate = false; 688 bool gate = false;
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
708 690
709 if (state == AMD_CG_STATE_GATE)
710 gate = true;
711
712 uvd_v5_0_set_bypass_mode(adev, gate);
713
714 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 691 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
715 return 0; 692 return 0;
716 693
694 if (state == AMD_CG_STATE_GATE)
695 gate = true;
696
717 uvd_v4_2_enable_mgcg(adev, gate); 697 uvd_v4_2_enable_mgcg(adev, gate);
718 698
719 return 0; 699 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 95303e2d5f92..95cabeafc18e 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -40,7 +40,10 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
40static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 40static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
41static int uvd_v5_0_start(struct amdgpu_device *adev); 41static int uvd_v5_0_start(struct amdgpu_device *adev);
42static void uvd_v5_0_stop(struct amdgpu_device *adev); 42static void uvd_v5_0_stop(struct amdgpu_device *adev);
43 43static int uvd_v5_0_set_clockgating_state(void *handle,
44 enum amd_clockgating_state state);
45static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
46 bool enable);
44/** 47/**
45 * uvd_v5_0_ring_get_rptr - get read pointer 48 * uvd_v5_0_ring_get_rptr - get read pointer
46 * 49 *
@@ -149,9 +152,6 @@ static int uvd_v5_0_hw_init(void *handle)
149 uint32_t tmp; 152 uint32_t tmp;
150 int r; 153 int r;
151 154
152 /* raise clocks while booting up the VCPU */
153 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
154
155 r = uvd_v5_0_start(adev); 155 r = uvd_v5_0_start(adev);
156 if (r) 156 if (r)
157 goto done; 157 goto done;
@@ -189,11 +189,7 @@ static int uvd_v5_0_hw_init(void *handle)
189 amdgpu_ring_write(ring, 3); 189 amdgpu_ring_write(ring, 3);
190 190
191 amdgpu_ring_commit(ring); 191 amdgpu_ring_commit(ring);
192
193done: 192done:
194 /* lower clocks again */
195 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
196
197 if (!r) 193 if (!r)
198 DRM_INFO("UVD initialized successfully.\n"); 194 DRM_INFO("UVD initialized successfully.\n");
199 195
@@ -226,6 +222,7 @@ static int uvd_v5_0_suspend(void *handle)
226 r = uvd_v5_0_hw_fini(adev); 222 r = uvd_v5_0_hw_fini(adev);
227 if (r) 223 if (r)
228 return r; 224 return r;
225 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
229 226
230 r = amdgpu_uvd_suspend(adev); 227 r = amdgpu_uvd_suspend(adev);
231 if (r) 228 if (r)
@@ -313,8 +310,9 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
313 310
314 uvd_v5_0_mc_resume(adev); 311 uvd_v5_0_mc_resume(adev);
315 312
316 /* disable clock gating */ 313 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
317 WREG32(mmUVD_CGC_GATE, 0); 314 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
315 uvd_v5_0_enable_mgcg(adev, true);
318 316
319 /* disable interupt */ 317 /* disable interupt */
320 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 318 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
@@ -628,16 +626,12 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
628 return 0; 626 return 0;
629} 627}
630 628
631static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 629static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
632{ 630{
633 uint32_t data, data1, data2, suvd_flags; 631 uint32_t data1, data3, suvd_flags;
634 632
635 data = RREG32(mmUVD_CGC_CTRL);
636 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 633 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
637 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 634 data3 = RREG32(mmUVD_CGC_GATE);
638
639 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
640 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
641 635
642 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 636 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
643 UVD_SUVD_CGC_GATE__SIT_MASK | 637 UVD_SUVD_CGC_GATE__SIT_MASK |
@@ -645,6 +639,49 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
645 UVD_SUVD_CGC_GATE__SCM_MASK | 639 UVD_SUVD_CGC_GATE__SCM_MASK |
646 UVD_SUVD_CGC_GATE__SDB_MASK; 640 UVD_SUVD_CGC_GATE__SDB_MASK;
647 641
642 if (enable) {
643 data3 |= (UVD_CGC_GATE__SYS_MASK |
644 UVD_CGC_GATE__UDEC_MASK |
645 UVD_CGC_GATE__MPEG2_MASK |
646 UVD_CGC_GATE__RBC_MASK |
647 UVD_CGC_GATE__LMI_MC_MASK |
648 UVD_CGC_GATE__IDCT_MASK |
649 UVD_CGC_GATE__MPRD_MASK |
650 UVD_CGC_GATE__MPC_MASK |
651 UVD_CGC_GATE__LBSI_MASK |
652 UVD_CGC_GATE__LRBBM_MASK |
653 UVD_CGC_GATE__UDEC_RE_MASK |
654 UVD_CGC_GATE__UDEC_CM_MASK |
655 UVD_CGC_GATE__UDEC_IT_MASK |
656 UVD_CGC_GATE__UDEC_DB_MASK |
657 UVD_CGC_GATE__UDEC_MP_MASK |
658 UVD_CGC_GATE__WCB_MASK |
659 UVD_CGC_GATE__VCPU_MASK |
660 UVD_CGC_GATE__JPEG_MASK |
661 UVD_CGC_GATE__SCPU_MASK);
662 data3 &= ~UVD_CGC_GATE__REGS_MASK;
663 data1 |= suvd_flags;
664 } else {
665 data3 = 0;
666 data1 = 0;
667 }
668
669 WREG32(mmUVD_SUVD_CGC_GATE, data1);
670 WREG32(mmUVD_CGC_GATE, data3);
671}
672
673static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
674{
675 uint32_t data, data2;
676
677 data = RREG32(mmUVD_CGC_CTRL);
678 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
679
680
681 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
682 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
683
684
648 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 685 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
649 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 686 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
650 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 687 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
@@ -675,11 +712,8 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
675 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 712 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
676 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 713 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
677 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 714 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
678 data1 |= suvd_flags;
679 715
680 WREG32(mmUVD_CGC_CTRL, data); 716 WREG32(mmUVD_CGC_CTRL, data);
681 WREG32(mmUVD_CGC_GATE, 0);
682 WREG32(mmUVD_SUVD_CGC_GATE, data1);
683 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 717 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
684} 718}
685 719
@@ -724,18 +758,30 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
724} 758}
725#endif 759#endif
726 760
727static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 761static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
762 bool enable)
728{ 763{
729 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 764 u32 orig, data;
730 765
731 if (enable) 766 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
732 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 767 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
733 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 768 data |= 0xfff;
734 else 769 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
735 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
736 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
737 770
738 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 771 orig = data = RREG32(mmUVD_CGC_CTRL);
772 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
773 if (orig != data)
774 WREG32(mmUVD_CGC_CTRL, data);
775 } else {
776 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
777 data &= ~0xfff;
778 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
779
780 orig = data = RREG32(mmUVD_CGC_CTRL);
781 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
782 if (orig != data)
783 WREG32(mmUVD_CGC_CTRL, data);
784 }
739} 785}
740 786
741static int uvd_v5_0_set_clockgating_state(void *handle, 787static int uvd_v5_0_set_clockgating_state(void *handle,
@@ -745,8 +791,6 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
745 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 791 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
746 static int curstate = -1; 792 static int curstate = -1;
747 793
748 uvd_v5_0_set_bypass_mode(adev, enable);
749
750 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 794 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
751 return 0; 795 return 0;
752 796
@@ -755,17 +799,18 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
755 799
756 curstate = state; 800 curstate = state;
757 if (enable) { 801 if (enable) {
758 /* disable HW gating and enable Sw gating */
759 uvd_v5_0_set_sw_clock_gating(adev);
760 } else {
761 /* wait for STATUS to clear */ 802 /* wait for STATUS to clear */
762 if (uvd_v5_0_wait_for_idle(handle)) 803 if (uvd_v5_0_wait_for_idle(handle))
763 return -EBUSY; 804 return -EBUSY;
805 uvd_v5_0_enable_clock_gating(adev, true);
764 806
765 /* enable HW gates because UVD is idle */ 807 /* enable HW gates because UVD is idle */
766/* uvd_v5_0_set_hw_clock_gating(adev); */ 808/* uvd_v5_0_set_hw_clock_gating(adev); */
809 } else {
810 uvd_v5_0_enable_clock_gating(adev, false);
767 } 811 }
768 812
813 uvd_v5_0_set_sw_clock_gating(adev);
769 return 0; 814 return 0;
770} 815}
771 816
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a339b5ccb296..00fad6951d82 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -151,6 +151,8 @@ static int uvd_v6_0_hw_init(void *handle)
151 uint32_t tmp; 151 uint32_t tmp;
152 int r; 152 int r;
153 153
154 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
155
154 r = uvd_v6_0_start(adev); 156 r = uvd_v6_0_start(adev);
155 if (r) 157 if (r)
156 goto done; 158 goto done;
@@ -935,28 +937,12 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
935} 937}
936#endif 938#endif
937 939
938static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
939{
940 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
941
942 if (enable)
943 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
944 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
945 else
946 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
947 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
948
949 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
950}
951
952static int uvd_v6_0_set_clockgating_state(void *handle, 940static int uvd_v6_0_set_clockgating_state(void *handle,
953 enum amd_clockgating_state state) 941 enum amd_clockgating_state state)
954{ 942{
955 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
956 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 944 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
957 945
958 uvd_v6_0_set_bypass_mode(adev, enable);
959
960 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 946 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
961 return 0; 947 return 0;
962 948
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0b21e7beda91..243dcf7bae47 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -926,7 +926,8 @@ static int vi_common_early_init(void *handle)
926 AMD_CG_SUPPORT_HDP_LS | 926 AMD_CG_SUPPORT_HDP_LS |
927 AMD_CG_SUPPORT_ROM_MGCG | 927 AMD_CG_SUPPORT_ROM_MGCG |
928 AMD_CG_SUPPORT_MC_MGCG | 928 AMD_CG_SUPPORT_MC_MGCG |
929 AMD_CG_SUPPORT_MC_LS; 929 AMD_CG_SUPPORT_MC_LS |
930 AMD_CG_SUPPORT_UVD_MGCG;
930 adev->pg_flags = 0; 931 adev->pg_flags = 0;
931 adev->external_rev_id = adev->rev_id + 0x3c; 932 adev->external_rev_id = adev->rev_id + 0x3c;
932 break; 933 break;
@@ -936,12 +937,12 @@ static int vi_common_early_init(void *handle)
936 adev->external_rev_id = adev->rev_id + 0x14; 937 adev->external_rev_id = adev->rev_id + 0x14;
937 break; 938 break;
938 case CHIP_POLARIS11: 939 case CHIP_POLARIS11:
939 adev->cg_flags = 0; 940 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
940 adev->pg_flags = 0; 941 adev->pg_flags = 0;
941 adev->external_rev_id = adev->rev_id + 0x5A; 942 adev->external_rev_id = adev->rev_id + 0x5A;
942 break; 943 break;
943 case CHIP_POLARIS10: 944 case CHIP_POLARIS10:
944 adev->cg_flags = 0; 945 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
945 adev->pg_flags = 0; 946 adev->pg_flags = 0;
946 adev->external_rev_id = adev->rev_id + 0x50; 947 adev->external_rev_id = adev->rev_id + 0x50;
947 break; 948 break;
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-11 16:06:47 -0400