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authorDave Airlie <airlied@redhat.com>2016-12-05 20:01:33 -0500
committerDave Airlie <airlied@redhat.com>2016-12-05 20:01:33 -0500
commit17f1dfd01ca105f0d3609225c9e7079c7df483b2 (patch)
treea30e2b896d41f0bb5206825d07ffd49cff97ed64
parent770ac20413ce654f6e4efaaf24e954ebb907fc3b (diff)
parente7b8243d3e0ace9f5130c3b5c3c52a50039a7501 (diff)
Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next
- lots of code cleanup - lots of bug fixes - expose rpm based fan info via hwmon - lots of clock and powergating fixes - SI register header cleanup and conversion to common format used by newer asics * 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (54 commits) drm/amdgpu: drop is_display_hung from display funcs drm/amdgpu/uvd: reduce IB parsing overhead on UVD5+ (v2) drm/amdgpu/uvd: consolidate code for fetching addr from ctx drm/amdgpu: Disable DPM in virtualization drm/amdgpu: use AMDGPU_GEM_CREATE_VRAM_CLEARED for VM PD/PTs (v2) drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2) drm/amdgpu: fix error handling in amdgpu_bo_create_restricted drm/amdgpu: fix amdgpu_fill_buffer (v2) drm/amdgpu: remove amdgpu_irq_get_delayed amdgpu: Wrap dev_err() calls on vm faults with printk_ratelimit() amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault() drm/amd/amdgpu: port of DCE v6 to new headers (v3) drm/amdgpu: cleanup unused iterator members for sdma v2.4 drm/amdgpu: cleanup unused iterator members for sdma v3 drm/amdgpu:impl vgt_flush for VI(V5) drm/amdgpu: enable uvd mgcg for Fiji. drm/amdgpu: refine cz uvd clock gate logic. drm/amdgpu: change log level to KERN_INFO in ci_dpm.c drm/amdgpu: always un-gate UVD REGS path. drm/amdgpu/sdma: fix typo in packet setup ...
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c39
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c47
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c69
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c99
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c515
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_virtual.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c770
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c21
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c23
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c339
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_enums.h272
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c42
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c113
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c18
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c7
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h661
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h8127
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h4457
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h9836
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h1784
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h12821
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h1274
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h11895
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h275
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h1079
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h148
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h715
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h96
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h795
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h64
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h99
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c72
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c31
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c14
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c5
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h3
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hwmgr.h6
-rwxr-xr-xdrivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c3
66 files changed, 55685 insertions, 1205 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 121a034fe27d..f53e52f4d672 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -92,13 +92,13 @@ extern int amdgpu_vm_debug;
92extern int amdgpu_sched_jobs; 92extern int amdgpu_sched_jobs;
93extern int amdgpu_sched_hw_submission; 93extern int amdgpu_sched_hw_submission;
94extern int amdgpu_powerplay; 94extern int amdgpu_powerplay;
95extern int amdgpu_powercontainment; 95extern int amdgpu_no_evict;
96extern int amdgpu_direct_gma_size;
96extern unsigned amdgpu_pcie_gen_cap; 97extern unsigned amdgpu_pcie_gen_cap;
97extern unsigned amdgpu_pcie_lane_cap; 98extern unsigned amdgpu_pcie_lane_cap;
98extern unsigned amdgpu_cg_mask; 99extern unsigned amdgpu_cg_mask;
99extern unsigned amdgpu_pg_mask; 100extern unsigned amdgpu_pg_mask;
100extern char *amdgpu_disable_cu; 101extern char *amdgpu_disable_cu;
101extern int amdgpu_sclk_deep_sleep_en;
102extern char *amdgpu_virtual_display; 102extern char *amdgpu_virtual_display;
103extern unsigned amdgpu_pp_feature_mask; 103extern unsigned amdgpu_pp_feature_mask;
104extern int amdgpu_vram_page_split; 104extern int amdgpu_vram_page_split;
@@ -1633,7 +1633,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1633#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1633#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1634#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1634#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1635#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1635#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1636#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
1637#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1636#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1638#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1637#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1639#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1638#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 2b6afe123f3d..b7e2762fcdd2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -70,7 +70,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
70 return false; 70 return false;
71 } 71 }
72 adev->bios = kmalloc(size, GFP_KERNEL); 72 adev->bios = kmalloc(size, GFP_KERNEL);
73 if (adev->bios == NULL) { 73 if (!adev->bios) {
74 iounmap(bios); 74 iounmap(bios);
75 return false; 75 return false;
76 } 76 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 78da52f90099..5a277495d6a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -841,16 +841,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
841 return amdgpu_cs_sync_rings(p); 841 return amdgpu_cs_sync_rings(p);
842} 842}
843 843
844static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
845{
846 if (r == -EDEADLK) {
847 r = amdgpu_gpu_reset(adev);
848 if (!r)
849 r = -EAGAIN;
850 }
851 return r;
852}
853
854static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 844static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
855 struct amdgpu_cs_parser *parser) 845 struct amdgpu_cs_parser *parser)
856{ 846{
@@ -1054,29 +1044,29 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1054 r = amdgpu_cs_parser_init(&parser, data); 1044 r = amdgpu_cs_parser_init(&parser, data);
1055 if (r) { 1045 if (r) {
1056 DRM_ERROR("Failed to initialize parser !\n"); 1046 DRM_ERROR("Failed to initialize parser !\n");
1057 amdgpu_cs_parser_fini(&parser, r, false); 1047 goto out;
1058 r = amdgpu_cs_handle_lockup(adev, r);
1059 return r;
1060 }
1061 r = amdgpu_cs_parser_bos(&parser, data);
1062 if (r == -ENOMEM)
1063 DRM_ERROR("Not enough memory for command submission!\n");
1064 else if (r && r != -ERESTARTSYS)
1065 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1066 else if (!r) {
1067 reserved_buffers = true;
1068 r = amdgpu_cs_ib_fill(adev, &parser);
1069 } 1048 }
1070 1049
1071 if (!r) { 1050 r = amdgpu_cs_parser_bos(&parser, data);
1072 r = amdgpu_cs_dependencies(adev, &parser); 1051 if (r) {
1073 if (r) 1052 if (r == -ENOMEM)
1074 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 1053 DRM_ERROR("Not enough memory for command submission!\n");
1054 else if (r != -ERESTARTSYS)
1055 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1056 goto out;
1075 } 1057 }
1076 1058
1059 reserved_buffers = true;
1060 r = amdgpu_cs_ib_fill(adev, &parser);
1077 if (r) 1061 if (r)
1078 goto out; 1062 goto out;
1079 1063
1064 r = amdgpu_cs_dependencies(adev, &parser);
1065 if (r) {
1066 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1067 goto out;
1068 }
1069
1080 for (i = 0; i < parser.job->num_ibs; i++) 1070 for (i = 0; i < parser.job->num_ibs; i++)
1081 trace_amdgpu_cs(&parser, i); 1071 trace_amdgpu_cs(&parser, i);
1082 1072
@@ -1088,7 +1078,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1088 1078
1089out: 1079out:
1090 amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 1080 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1091 r = amdgpu_cs_handle_lockup(adev, r);
1092 return r; 1081 return r;
1093} 1082}
1094 1083
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index deee2db36fce..fc790e5c46fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1017,8 +1017,8 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
1017 amdgpu_vm_block_size = 9; 1017 amdgpu_vm_block_size = 9;
1018 } 1018 }
1019 1019
1020 if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) || 1020 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1021 !amdgpu_check_pot_argument(amdgpu_vram_page_split)) { 1021 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1022 dev_warn(adev->dev, "invalid VRAM page split (%d)\n", 1022 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1023 amdgpu_vram_page_split); 1023 amdgpu_vram_page_split);
1024 amdgpu_vram_page_split = 1024; 1024 amdgpu_vram_page_split = 1024;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index bd85e35998e7..955d6f21e2b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -52,6 +52,8 @@ enum amdgpu_dpm_event_src {
52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
53}; 53};
54 54
55#define SCLK_DEEP_SLEEP_MASK 0x8
56
55struct amdgpu_ps { 57struct amdgpu_ps {
56 u32 caps; /* vbios flags */ 58 u32 caps; /* vbios flags */
57 u32 class; /* vbios flags */ 59 u32 class; /* vbios flags */
@@ -317,6 +319,11 @@ struct amdgpu_dpm_funcs {
317 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 319 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
318 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 320 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
319 321
322#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
323 ((adev)->pp_enabled ? \
324 (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \
325 -EINVAL)
326
320#define amdgpu_dpm_get_sclk(adev, l) \ 327#define amdgpu_dpm_get_sclk(adev, l) \
321 ((adev)->pp_enabled ? \ 328 ((adev)->pp_enabled ? \
322 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 329 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 42da6163b893..7914f999b1bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -91,8 +91,8 @@ int amdgpu_exp_hw_support = 0;
91int amdgpu_sched_jobs = 32; 91int amdgpu_sched_jobs = 32;
92int amdgpu_sched_hw_submission = 2; 92int amdgpu_sched_hw_submission = 2;
93int amdgpu_powerplay = -1; 93int amdgpu_powerplay = -1;
94int amdgpu_powercontainment = 1; 94int amdgpu_no_evict = 0;
95int amdgpu_sclk_deep_sleep_en = 1; 95int amdgpu_direct_gma_size = 0;
96unsigned amdgpu_pcie_gen_cap = 0; 96unsigned amdgpu_pcie_gen_cap = 0;
97unsigned amdgpu_pcie_lane_cap = 0; 97unsigned amdgpu_pcie_lane_cap = 0;
98unsigned amdgpu_cg_mask = 0xffffffff; 98unsigned amdgpu_cg_mask = 0xffffffff;
@@ -182,14 +182,14 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
182MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 182MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
183module_param_named(powerplay, amdgpu_powerplay, int, 0444); 183module_param_named(powerplay, amdgpu_powerplay, int, 0444);
184 184
185MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)");
186module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
187
188MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 185MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
189module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); 186module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
190 187
191MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); 188MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
192module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); 189module_param_named(no_evict, amdgpu_no_evict, int, 0444);
190
191MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
192module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
193 193
194MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 194MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
195module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 195module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 97928d7281f6..7b60fb79c3a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
382 if (!ring->fence_drv.fences) 382 if (!ring->fence_drv.fences)
383 return -ENOMEM; 383 return -ENOMEM;
384 384
385 timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 385 /* No need to setup the GPU scheduler for KIQ ring */
386 if (timeout == 0) { 386 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
387 /* 387 timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
388 * FIXME: 388 if (timeout == 0) {
389 * Delayed workqueue cannot use it directly, 389 /*
390 * so the scheduler will not use delayed workqueue if 390 * FIXME:
391 * MAX_SCHEDULE_TIMEOUT is set. 391 * Delayed workqueue cannot use it directly,
392 * Currently keep it simple and silly. 392 * so the scheduler will not use delayed workqueue if
393 */ 393 * MAX_SCHEDULE_TIMEOUT is set.
394 timeout = MAX_SCHEDULE_TIMEOUT; 394 * Currently keep it simple and silly.
395 } 395 */
396 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 396 timeout = MAX_SCHEDULE_TIMEOUT;
397 num_hw_submission, 397 }
398 timeout, ring->name); 398 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
399 if (r) { 399 num_hw_submission,
400 DRM_ERROR("Failed to create scheduler on ring %s.\n", 400 timeout, ring->name);
401 ring->name); 401 if (r) {
402 return r; 402 DRM_ERROR("Failed to create scheduler on ring %s.\n",
403 ring->name);
404 return r;
405 }
403 } 406 }
404 407
405 return 0; 408 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 9fa809876339..fb902932f571 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -424,15 +424,6 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
424 return 0; 424 return 0;
425} 425}
426 426
427bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
428 struct amdgpu_irq_src *src,
429 unsigned type)
430{
431 if ((type >= src->num_types) || !src->enabled_types)
432 return false;
433 return atomic_inc_return(&src->enabled_types[type]) == 1;
434}
435
436/** 427/**
437 * amdgpu_irq_put - disable interrupt 428 * amdgpu_irq_put - disable interrupt
438 * 429 *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index f016464035b8..1642f4108297 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -88,9 +88,6 @@ int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
88 unsigned type); 88 unsigned type);
89int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 89int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
90 unsigned type); 90 unsigned type);
91bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
92 struct amdgpu_irq_src *src,
93 unsigned type);
94int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 91int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
95 unsigned type); 92 unsigned type);
96bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 93bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 1e23334b07fb..202b4176b74e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -271,8 +271,6 @@ struct amdgpu_display_funcs {
271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
272 /* wait for vblank */ 272 /* wait for vblank */
273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
274 /* is dce hung */
275 bool (*is_display_hung)(struct amdgpu_device *adev);
276 /* set backlight level */ 274 /* set backlight level */
277 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 275 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
278 u8 level); 276 u8 level);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1479d09bd4dd..bf79b73e1538 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -128,17 +128,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
128 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 128 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
129 lpfn = adev->mc.real_vram_size >> PAGE_SHIFT; 129 lpfn = adev->mc.real_vram_size >> PAGE_SHIFT;
130 130
131 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
132 !(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
133 adev->mc.visible_vram_size < adev->mc.real_vram_size) {
134 places[c].fpfn = visible_pfn;
135 places[c].lpfn = lpfn;
136 places[c].flags = TTM_PL_FLAG_WC |
137 TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |
138 TTM_PL_FLAG_TOPDOWN;
139 c++;
140 }
141
142 places[c].fpfn = 0; 131 places[c].fpfn = 0;
143 places[c].lpfn = lpfn; 132 places[c].lpfn = lpfn;
144 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 133 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
@@ -382,39 +371,36 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
382 371
383 amdgpu_fill_placement_to_bo(bo, placement); 372 amdgpu_fill_placement_to_bo(bo, placement);
384 /* Kernel allocation are uninterruptible */ 373 /* Kernel allocation are uninterruptible */
374
375 if (!resv) {
376 bool locked;
377
378 reservation_object_init(&bo->tbo.ttm_resv);
379 locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock);
380 WARN_ON(!locked);
381 }
385 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 382 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
386 &bo->placement, page_align, !kernel, NULL, 383 &bo->placement, page_align, !kernel, NULL,
387 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 384 acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
388 if (unlikely(r != 0)) { 385 &amdgpu_ttm_bo_destroy);
386 if (unlikely(r != 0))
389 return r; 387 return r;
390 }
391 388
392 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 389 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
393 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 390 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
394 struct dma_fence *fence; 391 struct dma_fence *fence;
395 392
396 if (adev->mman.buffer_funcs_ring == NULL || 393 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
397 !adev->mman.buffer_funcs_ring->ready) { 394 if (unlikely(r))
398 r = -EBUSY;
399 goto fail_free;
400 }
401
402 r = amdgpu_bo_reserve(bo, false);
403 if (unlikely(r != 0))
404 goto fail_free;
405
406 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
407 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
408 if (unlikely(r != 0))
409 goto fail_unreserve; 395 goto fail_unreserve;
410 396
411 amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
412 amdgpu_bo_fence(bo, fence, false); 397 amdgpu_bo_fence(bo, fence, false);
413 amdgpu_bo_unreserve(bo);
414 dma_fence_put(bo->tbo.moving); 398 dma_fence_put(bo->tbo.moving);
415 bo->tbo.moving = dma_fence_get(fence); 399 bo->tbo.moving = dma_fence_get(fence);
416 dma_fence_put(fence); 400 dma_fence_put(fence);
417 } 401 }
402 if (!resv)
403 ww_mutex_unlock(&bo->tbo.resv->lock);
418 *bo_ptr = bo; 404 *bo_ptr = bo;
419 405
420 trace_amdgpu_bo_create(bo); 406 trace_amdgpu_bo_create(bo);
@@ -422,8 +408,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
422 return 0; 408 return 0;
423 409
424fail_unreserve: 410fail_unreserve:
425 amdgpu_bo_unreserve(bo); 411 ww_mutex_unlock(&bo->tbo.resv->lock);
426fail_free:
427 amdgpu_bo_unref(&bo); 412 amdgpu_bo_unref(&bo);
428 return r; 413 return r;
429} 414}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 274f3309aec9..723ae682bf25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -737,6 +737,21 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
737 return sprintf(buf, "%i\n", speed); 737 return sprintf(buf, "%i\n", speed);
738} 738}
739 739
740static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
741 struct device_attribute *attr,
742 char *buf)
743{
744 struct amdgpu_device *adev = dev_get_drvdata(dev);
745 int err;
746 u32 speed;
747
748 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
749 if (err)
750 return err;
751
752 return sprintf(buf, "%i\n", speed);
753}
754
740static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); 755static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
741static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 756static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
742static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 757static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
@@ -744,6 +759,7 @@ static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu
744static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 759static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
745static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 760static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
746static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 761static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
762static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
747 763
748static struct attribute *hwmon_attributes[] = { 764static struct attribute *hwmon_attributes[] = {
749 &sensor_dev_attr_temp1_input.dev_attr.attr, 765 &sensor_dev_attr_temp1_input.dev_attr.attr,
@@ -753,6 +769,7 @@ static struct attribute *hwmon_attributes[] = {
753 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 769 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
754 &sensor_dev_attr_pwm1_min.dev_attr.attr, 770 &sensor_dev_attr_pwm1_min.dev_attr.attr,
755 &sensor_dev_attr_pwm1_max.dev_attr.attr, 771 &sensor_dev_attr_pwm1_max.dev_attr.attr,
772 &sensor_dev_attr_fan1_input.dev_attr.attr,
756 NULL 773 NULL
757}; 774};
758 775
@@ -804,6 +821,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
804 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 821 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
805 return 0; 822 return 0;
806 823
824 /* requires powerplay */
825 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
826 return 0;
827
807 return effective_mode; 828 return effective_mode;
808} 829}
809 830
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index fa6baf31a35d..fc592c2b0e16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle)
155 ret = adev->powerplay.ip_funcs->sw_init( 155 ret = adev->powerplay.ip_funcs->sw_init(
156 adev->powerplay.pp_handle); 156 adev->powerplay.pp_handle);
157 157
158 if (adev->pp_enabled)
159 adev->pm.dpm_enabled = true;
160
161 return ret; 158 return ret;
162} 159}
163 160
@@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle)
187 ret = adev->powerplay.ip_funcs->hw_init( 184 ret = adev->powerplay.ip_funcs->hw_init(
188 adev->powerplay.pp_handle); 185 adev->powerplay.pp_handle);
189 186
187 if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
188 adev->pm.dpm_enabled = true;
189
190 return ret; 190 return ret;
191} 191}
192 192
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f2ad49c8e85b..574f0b79c690 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -44,7 +44,8 @@ enum amdgpu_ring_type {
44 AMDGPU_RING_TYPE_COMPUTE, 44 AMDGPU_RING_TYPE_COMPUTE,
45 AMDGPU_RING_TYPE_SDMA, 45 AMDGPU_RING_TYPE_SDMA,
46 AMDGPU_RING_TYPE_UVD, 46 AMDGPU_RING_TYPE_UVD,
47 AMDGPU_RING_TYPE_VCE 47 AMDGPU_RING_TYPE_VCE,
48 AMDGPU_RING_TYPE_KIQ
48}; 49};
49 50
50struct amdgpu_device; 51struct amdgpu_device;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 34a795463988..de9f919ae336 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -327,9 +327,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
327 return -EINVAL; 327 return -EINVAL;
328 328
329 *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL); 329 *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
330 if ((*sa_bo) == NULL) { 330 if (!(*sa_bo))
331 return -ENOMEM; 331 return -ENOMEM;
332 }
333 (*sa_bo)->manager = sa_manager; 332 (*sa_bo)->manager = sa_manager;
334 (*sa_bo)->fence = NULL; 333 (*sa_bo)->fence = NULL;
335 INIT_LIST_HEAD(&(*sa_bo)->olist); 334 INIT_LIST_HEAD(&(*sa_bo)->olist);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 1821c05484d0..8f18b8ed2b3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1382,28 +1382,40 @@ error_free:
1382} 1382}
1383 1383
1384int amdgpu_fill_buffer(struct amdgpu_bo *bo, 1384int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1385 uint32_t src_data, 1385 uint32_t src_data,
1386 struct reservation_object *resv, 1386 struct reservation_object *resv,
1387 struct dma_fence **fence) 1387 struct dma_fence **fence)
1388{ 1388{
1389 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1389 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1390 struct amdgpu_job *job; 1390 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1391 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1391 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1392 1392
1393 uint32_t max_bytes, byte_count; 1393 struct drm_mm_node *mm_node;
1394 uint64_t dst_offset; 1394 unsigned long num_pages;
1395 unsigned int num_loops, num_dw; 1395 unsigned int num_loops, num_dw;
1396 unsigned int i; 1396
1397 struct amdgpu_job *job;
1397 int r; 1398 int r;
1398 1399
1399 byte_count = bo->tbo.num_pages << PAGE_SHIFT; 1400 if (!ring->ready) {
1400 max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1401 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1401 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1402 return -EINVAL;
1403 }
1404
1405 num_pages = bo->tbo.num_pages;
1406 mm_node = bo->tbo.mem.mm_node;
1407 num_loops = 0;
1408 while (num_pages) {
1409 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1410
1411 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1412 num_pages -= mm_node->size;
1413 ++mm_node;
1414 }
1402 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 1415 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1403 1416
1404 /* for IB padding */ 1417 /* for IB padding */
1405 while (num_dw & 0x7) 1418 num_dw += 64;
1406 num_dw++;
1407 1419
1408 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); 1420 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1409 if (r) 1421 if (r)
@@ -1411,28 +1423,43 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1411 1423
1412 if (resv) { 1424 if (resv) {
1413 r = amdgpu_sync_resv(adev, &job->sync, resv, 1425 r = amdgpu_sync_resv(adev, &job->sync, resv,
1414 AMDGPU_FENCE_OWNER_UNDEFINED); 1426 AMDGPU_FENCE_OWNER_UNDEFINED);
1415 if (r) { 1427 if (r) {
1416 DRM_ERROR("sync failed (%d).\n", r); 1428 DRM_ERROR("sync failed (%d).\n", r);
1417 goto error_free; 1429 goto error_free;
1418 } 1430 }
1419 } 1431 }
1420 1432
1421 dst_offset = bo->tbo.mem.start << PAGE_SHIFT; 1433 num_pages = bo->tbo.num_pages;
1422 for (i = 0; i < num_loops; i++) { 1434 mm_node = bo->tbo.mem.mm_node;
1423 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1424 1435
1425 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, 1436 while (num_pages) {
1426 dst_offset, cur_size_in_bytes); 1437 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1438 uint64_t dst_addr;
1427 1439
1428 dst_offset += cur_size_in_bytes; 1440 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1429 byte_count -= cur_size_in_bytes; 1441 &bo->tbo.mem, &dst_addr);
1442 if (r)
1443 return r;
1444
1445 while (byte_count) {
1446 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1447
1448 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1449 dst_addr, cur_size_in_bytes);
1450
1451 dst_addr += cur_size_in_bytes;
1452 byte_count -= cur_size_in_bytes;
1453 }
1454
1455 num_pages -= mm_node->size;
1456 ++mm_node;
1430 } 1457 }
1431 1458
1432 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1459 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1433 WARN_ON(job->ibs[0].length_dw > num_dw); 1460 WARN_ON(job->ibs[0].length_dw > num_dw);
1434 r = amdgpu_job_submit(job, ring, &adev->mman.entity, 1461 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1435 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1462 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1436 if (r) 1463 if (r)
1437 goto error_free; 1464 goto error_free;
1438 1465
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index fb270c7e7171..a81dfaeeb8c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -360,6 +360,18 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
360 } 360 }
361} 361}
362 362
363static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
364{
365 uint32_t lo, hi;
366 uint64_t addr;
367
368 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
369 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
370 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
371
372 return addr;
373}
374
363/** 375/**
364 * amdgpu_uvd_cs_pass1 - first parsing round 376 * amdgpu_uvd_cs_pass1 - first parsing round
365 * 377 *
@@ -372,14 +384,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
372{ 384{
373 struct amdgpu_bo_va_mapping *mapping; 385 struct amdgpu_bo_va_mapping *mapping;
374 struct amdgpu_bo *bo; 386 struct amdgpu_bo *bo;
375 uint32_t cmd, lo, hi; 387 uint32_t cmd;
376 uint64_t addr; 388 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
377 int r = 0; 389 int r = 0;
378 390
379 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
380 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
381 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
382
383 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 391 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
384 if (mapping == NULL) { 392 if (mapping == NULL) {
385 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 393 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
@@ -698,18 +706,16 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
698{ 706{
699 struct amdgpu_bo_va_mapping *mapping; 707 struct amdgpu_bo_va_mapping *mapping;
700 struct amdgpu_bo *bo; 708 struct amdgpu_bo *bo;
701 uint32_t cmd, lo, hi; 709 uint32_t cmd;
702 uint64_t start, end; 710 uint64_t start, end;
703 uint64_t addr; 711 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
704 int r; 712 int r;
705 713
706 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
707 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
708 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
709
710 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); 714 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
711 if (mapping == NULL) 715 if (mapping == NULL) {
716 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
712 return -EINVAL; 717 return -EINVAL;
718 }
713 719
714 start = amdgpu_bo_gpu_offset(bo); 720 start = amdgpu_bo_gpu_offset(bo);
715 721
@@ -893,10 +899,13 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
893 ctx.buf_sizes = buf_sizes; 899 ctx.buf_sizes = buf_sizes;
894 ctx.ib_idx = ib_idx; 900 ctx.ib_idx = ib_idx;
895 901
896 /* first round, make sure the buffers are actually in the UVD segment */ 902 /* first round only required on chips without UVD 64 bit address support */
897 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 903 if (!parser->adev->uvd.address_64_bit) {
898 if (r) 904 /* first round, make sure the buffers are actually in the UVD segment */
899 return r; 905 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
906 if (r)
907 return r;
908 }
900 909
901 /* second round, patch buffer addresses into the command stream */ 910 /* second round, patch buffer addresses into the command stream */
902 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 911 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 337c5b31d18d..1dda9321bd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -530,70 +530,6 @@ static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
530} 530}
531 531
532/** 532/**
533 * amdgpu_vm_clear_bo - initially clear the page dir/table
534 *
535 * @adev: amdgpu_device pointer
536 * @bo: bo to clear
537 *
538 * need to reserve bo first before calling it.
539 */
540static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
541 struct amdgpu_vm *vm,
542 struct amdgpu_bo *bo)
543{
544 struct amdgpu_ring *ring;
545 struct dma_fence *fence = NULL;
546 struct amdgpu_job *job;
547 struct amdgpu_pte_update_params params;
548 unsigned entries;
549 uint64_t addr;
550 int r;
551
552 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
553
554 r = reservation_object_reserve_shared(bo->tbo.resv);
555 if (r)
556 return r;
557
558 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
559 if (r)
560 goto error;
561
562 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
563 if (r)
564 goto error;
565
566 addr = amdgpu_bo_gpu_offset(bo);
567 entries = amdgpu_bo_size(bo) / 8;
568
569 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
570 if (r)
571 goto error;
572
573 memset(&params, 0, sizeof(params));
574 params.adev = adev;
575 params.ib = &job->ibs[0];
576 amdgpu_vm_do_set_ptes(&params, addr, 0, entries, 0, 0);
577 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
578
579 WARN_ON(job->ibs[0].length_dw > 64);
580 r = amdgpu_job_submit(job, ring, &vm->entity,
581 AMDGPU_FENCE_OWNER_VM, &fence);
582 if (r)
583 goto error_free;
584
585 amdgpu_bo_fence(bo, fence, true);
586 dma_fence_put(fence);
587 return 0;
588
589error_free:
590 amdgpu_job_free(job);
591
592error:
593 return r;
594}
595
596/**
597 * amdgpu_vm_map_gart - Resolve gart mapping of addr 533 * amdgpu_vm_map_gart - Resolve gart mapping of addr
598 * 534 *
599 * @pages_addr: optional DMA address to use for lookup 535 * @pages_addr: optional DMA address to use for lookup
@@ -1435,7 +1371,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1435 AMDGPU_GEM_DOMAIN_VRAM, 1371 AMDGPU_GEM_DOMAIN_VRAM,
1436 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 1372 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
1437 AMDGPU_GEM_CREATE_SHADOW | 1373 AMDGPU_GEM_CREATE_SHADOW |
1438 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1374 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1375 AMDGPU_GEM_CREATE_VRAM_CLEARED,
1439 NULL, resv, &pt); 1376 NULL, resv, &pt);
1440 if (r) 1377 if (r)
1441 goto error_free; 1378 goto error_free;
@@ -1445,22 +1382,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1445 */ 1382 */
1446 pt->parent = amdgpu_bo_ref(vm->page_directory); 1383 pt->parent = amdgpu_bo_ref(vm->page_directory);
1447 1384
1448 r = amdgpu_vm_clear_bo(adev, vm, pt);
1449 if (r) {
1450 amdgpu_bo_unref(&pt->shadow);
1451 amdgpu_bo_unref(&pt);
1452 goto error_free;
1453 }
1454
1455 if (pt->shadow) {
1456 r = amdgpu_vm_clear_bo(adev, vm, pt->shadow);
1457 if (r) {
1458 amdgpu_bo_unref(&pt->shadow);
1459 amdgpu_bo_unref(&pt);
1460 goto error_free;
1461 }
1462 }
1463
1464 vm->page_tables[pt_idx].bo = pt; 1385 vm->page_tables[pt_idx].bo = pt;
1465 vm->page_tables[pt_idx].addr = 0; 1386 vm->page_tables[pt_idx].addr = 0;
1466 } 1387 }
@@ -1642,7 +1563,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1642 AMDGPU_GEM_DOMAIN_VRAM, 1563 AMDGPU_GEM_DOMAIN_VRAM,
1643 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 1564 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
1644 AMDGPU_GEM_CREATE_SHADOW | 1565 AMDGPU_GEM_CREATE_SHADOW |
1645 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 1566 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1567 AMDGPU_GEM_CREATE_VRAM_CLEARED,
1646 NULL, NULL, &vm->page_directory); 1568 NULL, NULL, &vm->page_directory);
1647 if (r) 1569 if (r)
1648 goto error_free_sched_entity; 1570 goto error_free_sched_entity;
@@ -1651,24 +1573,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1651 if (r) 1573 if (r)
1652 goto error_free_page_directory; 1574 goto error_free_page_directory;
1653 1575
1654 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
1655 if (r)
1656 goto error_unreserve;
1657
1658 if (vm->page_directory->shadow) {
1659 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory->shadow);
1660 if (r)
1661 goto error_unreserve;
1662 }
1663
1664 vm->last_eviction_counter = atomic64_read(&adev->num_evictions); 1576 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
1665 amdgpu_bo_unreserve(vm->page_directory); 1577 amdgpu_bo_unreserve(vm->page_directory);
1666 1578
1667 return 0; 1579 return 0;
1668 1580
1669error_unreserve:
1670 amdgpu_bo_unreserve(vm->page_directory);
1671
1672error_free_page_directory: 1581error_free_page_directory:
1673 amdgpu_bo_unref(&vm->page_directory->shadow); 1582 amdgpu_bo_unref(&vm->page_directory->shadow);
1674 amdgpu_bo_unref(&vm->page_directory); 1583 amdgpu_bo_unref(&vm->page_directory);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 180eed7c8bca..d710226a0fff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -108,7 +108,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man,
108 lpfn = man->size; 108 lpfn = man->size;
109 109
110 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS || 110 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS ||
111 amdgpu_vram_page_split == -1) { 111 place->lpfn || amdgpu_vram_page_split == -1) {
112 pages_per_node = ~0ul; 112 pages_per_node = ~0ul;
113 num_nodes = 1; 113 num_nodes = 1;
114 } else { 114 } else {
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1caff75ab9fc..1027f92de32b 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4202 4202
4203 if (!gate) { 4203 if (!gate) {
4204 /* turn the clocks on when decoding */ 4204 /* turn the clocks on when decoding */
4205 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
4206 AMD_CG_STATE_UNGATE);
4207 if (ret)
4208 return ret;
4209
4210 if (pi->caps_uvd_dpm || 4205 if (pi->caps_uvd_dpm ||
4211 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) 4206 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4212 pi->smc_state_table.UvdBootLevel = 0; 4207 pi->smc_state_table.UvdBootLevel = 0;
@@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4223 ret = ci_enable_uvd_dpm(adev, false); 4218 ret = ci_enable_uvd_dpm(adev, false);
4224 if (ret) 4219 if (ret)
4225 return ret; 4220 return ret;
4226
4227 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
4228 AMD_CG_STATE_GATE);
4229 } 4221 }
4230 4222
4231 return ret; 4223 return ret;
@@ -5896,7 +5888,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
5896 pi->pcie_dpm_key_disabled = 0; 5888 pi->pcie_dpm_key_disabled = 0;
5897 pi->thermal_sclk_dpm_enabled = 0; 5889 pi->thermal_sclk_dpm_enabled = 0;
5898 5890
5899 if (amdgpu_sclk_deep_sleep_en) 5891 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
5900 pi->caps_sclk_ds = true; 5892 pi->caps_sclk_ds = true;
5901 else 5893 else
5902 pi->caps_sclk_ds = false; 5894 pi->caps_sclk_ds = false;
@@ -5999,7 +5991,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
5999 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK; 5991 tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
6000 break; 5992 break;
6001 default: 5993 default:
6002 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift); 5994 DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
6003 break; 5995 break;
6004 } 5996 }
6005 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp); 5997 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 352b5fad5a06..ba2b66be9022 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev)
438 pi->caps_td_ramping = true; 438 pi->caps_td_ramping = true;
439 pi->caps_tcp_ramping = true; 439 pi->caps_tcp_ramping = true;
440 } 440 }
441 if (amdgpu_sclk_deep_sleep_en) 441 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
442 pi->caps_sclk_ds = true; 442 pi->caps_sclk_ds = true;
443 else 443 else
444 pi->caps_sclk_ds = false; 444 pi->caps_sclk_ds = false;
@@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
2111 2111
2112 if (gate) { 2112 if (gate) {
2113 if (pi->caps_uvd_pg) { 2113 if (pi->caps_uvd_pg) {
2114 /* disable clockgating so we can properly shut down the block */
2115 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 2114 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2116 AMD_CG_STATE_UNGATE); 2115 AMD_CG_STATE_GATE);
2117 if (ret) { 2116 if (ret) {
2118 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n"); 2117 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
2119 return; 2118 return;
@@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
2159 return; 2158 return;
2160 } 2159 }
2161 2160
2162 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
2163 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 2161 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2164 AMD_CG_STATE_GATE); 2162 AMD_CG_STATE_UNGATE);
2165 if (ret) { 2163 if (ret) {
2166 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n"); 2164 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
2167 return; 2165 return;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 65a954cb69ed..075aa0b1b075 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3749,7 +3749,6 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3749 .bandwidth_update = &dce_v10_0_bandwidth_update, 3749 .bandwidth_update = &dce_v10_0_bandwidth_update,
3750 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3750 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3751 .vblank_wait = &dce_v10_0_vblank_wait, 3751 .vblank_wait = &dce_v10_0_vblank_wait,
3752 .is_display_hung = &dce_v10_0_is_display_hung,
3753 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3752 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3754 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3753 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3755 .hpd_sense = &dce_v10_0_hpd_sense, 3754 .hpd_sense = &dce_v10_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index d807e876366b..a6717487ac78 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3805,7 +3805,6 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3805 .bandwidth_update = &dce_v11_0_bandwidth_update, 3805 .bandwidth_update = &dce_v11_0_bandwidth_update,
3806 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3806 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3807 .vblank_wait = &dce_v11_0_vblank_wait, 3807 .vblank_wait = &dce_v11_0_vblank_wait,
3808 .is_display_hung = &dce_v11_0_is_display_hung,
3809 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3808 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3810 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3809 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3811 .hpd_sense = &dce_v11_0_hpd_sense, 3810 .hpd_sense = &dce_v11_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bc9f2f423270..15d98ef696a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -30,8 +30,19 @@
30#include "atombios_encoders.h" 30#include "atombios_encoders.h"
31#include "amdgpu_pll.h" 31#include "amdgpu_pll.h"
32#include "amdgpu_connectors.h" 32#include "amdgpu_connectors.h"
33#include "si/si_reg.h" 33
34#include "si/sid.h" 34#include "bif/bif_3_0_d.h"
35#include "bif/bif_3_0_sh_mask.h"
36#include "oss/oss_1_0_d.h"
37#include "oss/oss_1_0_sh_mask.h"
38#include "gca/gfx_6_0_d.h"
39#include "gca/gfx_6_0_sh_mask.h"
40#include "gmc/gmc_6_0_d.h"
41#include "gmc/gmc_6_0_sh_mask.h"
42#include "dce/dce_6_0_d.h"
43#include "dce/dce_6_0_sh_mask.h"
44#include "gca/gfx_7_2_enum.h"
45#include "si_enums.h"
35 46
36static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 47static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
37static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 48static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -48,12 +59,12 @@ static const u32 crtc_offsets[6] =
48 59
49static const u32 hpd_offsets[] = 60static const u32 hpd_offsets[] =
50{ 61{
51 DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS, 62 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
52 DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS, 63 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
53 DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS, 64 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
54 DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS, 65 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
55 DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS, 66 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
56 DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS, 67 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
57}; 68};
58 69
59static const uint32_t dig_offsets[] = { 70static const uint32_t dig_offsets[] = {
@@ -73,32 +84,32 @@ static const struct {
73 uint32_t hpd; 84 uint32_t hpd;
74 85
75} interrupt_status_offsets[6] = { { 86} interrupt_status_offsets[6] = { {
76 .reg = DISP_INTERRUPT_STATUS, 87 .reg = mmDISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
80}, { 91}, {
81 .reg = DISP_INTERRUPT_STATUS_CONTINUE, 92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
85}, { 96}, {
86 .reg = DISP_INTERRUPT_STATUS_CONTINUE2, 97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
90}, { 101}, {
91 .reg = DISP_INTERRUPT_STATUS_CONTINUE3, 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
95}, { 106}, {
96 .reg = DISP_INTERRUPT_STATUS_CONTINUE4, 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
100}, { 111}, {
101 .reg = DISP_INTERRUPT_STATUS_CONTINUE5, 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
@@ -119,7 +130,7 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
119 130
120static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 131static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
121{ 132{
122 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) 133 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
123 return true; 134 return true;
124 else 135 else
125 return false; 136 return false;
@@ -129,8 +140,8 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
129{ 140{
130 u32 pos1, pos2; 141 u32 pos1, pos2;
131 142
132 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 143 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
133 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 144 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
134 145
135 if (pos1 != pos2) 146 if (pos1 != pos2)
136 return true; 147 return true;
@@ -152,7 +163,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
152 if (crtc >= adev->mode_info.num_crtc) 163 if (crtc >= adev->mode_info.num_crtc)
153 return; 164 return;
154 165
155 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) 166 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
156 return; 167 return;
157 168
158 /* depending on when we hit vblank, we may be close to active; if so, 169 /* depending on when we hit vblank, we may be close to active; if so,
@@ -180,7 +191,7 @@ static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
180 if (crtc >= adev->mode_info.num_crtc) 191 if (crtc >= adev->mode_info.num_crtc)
181 return 0; 192 return 0;
182 else 193 else
183 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 194 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
184} 195}
185 196
186static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 197static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
@@ -220,16 +231,16 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
220 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 231 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
221 232
222 /* flip at hsync for async, default is vsync */ 233 /* flip at hsync for async, default is vsync */
223 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 234 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
224 EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); 235 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
225 /* update the scanout addresses */ 236 /* update the scanout addresses */
226 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 237 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
227 upper_32_bits(crtc_base)); 238 upper_32_bits(crtc_base));
228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 239 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
229 (u32)crtc_base); 240 (u32)crtc_base);
230 241
231 /* post the write */ 242 /* post the write */
232 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 243 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
233} 244}
234 245
235static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 246static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -237,8 +248,8 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
237{ 248{
238 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 249 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
239 return -EINVAL; 250 return -EINVAL;
240 *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]); 251 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
241 *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 252 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
242 253
243 return 0; 254 return 0;
244 255
@@ -261,7 +272,7 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
261 if (hpd >= adev->mode_info.num_hpd) 272 if (hpd >= adev->mode_info.num_hpd)
262 return connected; 273 return connected;
263 274
264 if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE) 275 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
265 connected = true; 276 connected = true;
266 277
267 return connected; 278 return connected;
@@ -284,12 +295,12 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
284 if (hpd >= adev->mode_info.num_hpd) 295 if (hpd >= adev->mode_info.num_hpd)
285 return; 296 return;
286 297
287 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 298 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
288 if (connected) 299 if (connected)
289 tmp &= ~DC_HPDx_INT_POLARITY; 300 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
290 else 301 else
291 tmp |= DC_HPDx_INT_POLARITY; 302 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
292 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 303 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
293} 304}
294 305
295/** 306/**
@@ -312,9 +323,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
312 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 323 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
313 continue; 324 continue;
314 325
315 tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 326 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
316 tmp |= DC_HPDx_EN; 327 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
317 WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 328 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
318 329
319 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 330 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
320 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 331 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
@@ -323,9 +334,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
323 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 334 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
324 * also avoid interrupt storms during dpms. 335 * also avoid interrupt storms during dpms.
325 */ 336 */
326 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 337 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
327 tmp &= ~DC_HPDx_INT_EN; 338 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
328 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 339 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
329 continue; 340 continue;
330 } 341 }
331 342
@@ -355,9 +366,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
355 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 366 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
356 continue; 367 continue;
357 368
358 tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 369 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
359 tmp &= ~DC_HPDx_EN; 370 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
360 WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 371 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
361 372
362 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 373 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
363 } 374 }
@@ -365,14 +376,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
365 376
366static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 377static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
367{ 378{
368 return SI_DC_GPIO_HPD_A; 379 return mmDC_GPIO_HPD_A;
369}
370
371static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
372{
373 DRM_INFO("xxxx: dce_v6_0_is_display_hung ----no imp!!!!!\n");
374
375 return true;
376} 380}
377 381
378static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) 382static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
@@ -380,7 +384,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
380 if (crtc >= adev->mode_info.num_crtc) 384 if (crtc >= adev->mode_info.num_crtc)
381 return 0; 385 return 0;
382 else 386 else
383 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 387 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
384} 388}
385 389
386static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, 390static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
@@ -389,25 +393,25 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
389 u32 crtc_enabled, tmp, frame_count; 393 u32 crtc_enabled, tmp, frame_count;
390 int i, j; 394 int i, j;
391 395
392 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 396 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
393 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 397 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
394 398
395 /* disable VGA render */ 399 /* disable VGA render */
396 WREG32(VGA_RENDER_CONTROL, 0); 400 WREG32(mmVGA_RENDER_CONTROL, 0);
397 401
398 /* blank the display controllers */ 402 /* blank the display controllers */
399 for (i = 0; i < adev->mode_info.num_crtc; i++) { 403 for (i = 0; i < adev->mode_info.num_crtc; i++) {
400 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; 404 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
401 if (crtc_enabled) { 405 if (crtc_enabled) {
402 save->crtc_enabled[i] = true; 406 save->crtc_enabled[i] = true;
403 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 407 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
404 408
405 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { 409 if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
406 dce_v6_0_vblank_wait(adev, i); 410 dce_v6_0_vblank_wait(adev, i);
407 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 411 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
408 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 412 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
409 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 413 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
410 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
411 } 415 }
412 /* wait for the next frame */ 416 /* wait for the next frame */
413 frame_count = evergreen_get_vblank_counter(adev, i); 417 frame_count = evergreen_get_vblank_counter(adev, i);
@@ -418,11 +422,11 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
418 } 422 }
419 423
420 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 424 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
421 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 425 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
422 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 426 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
423 tmp &= ~EVERGREEN_CRTC_MASTER_EN; 427 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
424 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 428 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
425 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 429 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
426 save->crtc_enabled[i] = false; 430 save->crtc_enabled[i] = false;
427 /* ***** */ 431 /* ***** */
428 } else { 432 } else {
@@ -439,41 +443,41 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
439 443
440 /* update crtc base addresses */ 444 /* update crtc base addresses */
441 for (i = 0; i < adev->mode_info.num_crtc; i++) { 445 for (i = 0; i < adev->mode_info.num_crtc; i++) {
442 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 446 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
443 upper_32_bits(adev->mc.vram_start)); 447 upper_32_bits(adev->mc.vram_start));
444 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 448 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
445 upper_32_bits(adev->mc.vram_start)); 449 upper_32_bits(adev->mc.vram_start));
446 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 450 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
447 (u32)adev->mc.vram_start); 451 (u32)adev->mc.vram_start);
448 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 452 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
449 (u32)adev->mc.vram_start); 453 (u32)adev->mc.vram_start);
450 } 454 }
451 455
452 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 456 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
453 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); 457 WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
454 458
455 /* unlock regs and wait for update */ 459 /* unlock regs and wait for update */
456 for (i = 0; i < adev->mode_info.num_crtc; i++) { 460 for (i = 0; i < adev->mode_info.num_crtc; i++) {
457 if (save->crtc_enabled[i]) { 461 if (save->crtc_enabled[i]) {
458 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); 462 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
459 if ((tmp & 0x7) != 3) { 463 if ((tmp & 0x7) != 3) {
460 tmp &= ~0x7; 464 tmp &= ~0x7;
461 tmp |= 0x3; 465 tmp |= 0x3;
462 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 466 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
463 } 467 }
464 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 468 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
465 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { 469 if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
466 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 470 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
467 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); 471 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
468 } 472 }
469 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); 473 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
470 if (tmp & 1) { 474 if (tmp & 1) {
471 tmp &= ~1; 475 tmp &= ~1;
472 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 476 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
473 } 477 }
474 for (j = 0; j < adev->usec_timeout; j++) { 478 for (j = 0; j < adev->usec_timeout; j++) {
475 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 479 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
476 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) 480 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
477 break; 481 break;
478 udelay(1); 482 udelay(1);
479 } 483 }
@@ -481,9 +485,9 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
481 } 485 }
482 486
483 /* Unlock vga access */ 487 /* Unlock vga access */
484 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 488 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
485 mdelay(1); 489 mdelay(1);
486 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 490 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
487 491
488} 492}
489 493
@@ -491,8 +495,8 @@ static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
491 bool render) 495 bool render)
492{ 496{
493 if (!render) 497 if (!render)
494 WREG32(R_000300_VGA_RENDER_CONTROL, 498 WREG32(mmVGA_RENDER_CONTROL,
495 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 499 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
496 500
497} 501}
498 502
@@ -526,14 +530,14 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev)
526 530
527 /*Disable crtc*/ 531 /*Disable crtc*/
528 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 532 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
529 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & 533 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
530 EVERGREEN_CRTC_MASTER_EN; 534 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
531 if (crtc_enabled) { 535 if (crtc_enabled) {
532 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 537 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
534 tmp &= ~EVERGREEN_CRTC_MASTER_EN; 538 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
535 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 539 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 540 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 } 541 }
538 } 542 }
539 } 543 }
@@ -569,19 +573,23 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
569 case 6: 573 case 6:
570 if (dither == AMDGPU_FMT_DITHER_ENABLE) 574 if (dither == AMDGPU_FMT_DITHER_ENABLE)
571 /* XXX sort out optimal dither settings */ 575 /* XXX sort out optimal dither settings */
572 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | 576 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
573 FMT_SPATIAL_DITHER_EN); 577 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
578 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
574 else 579 else
575 tmp |= FMT_TRUNCATE_EN; 580 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
576 break; 581 break;
577 case 8: 582 case 8:
578 if (dither == AMDGPU_FMT_DITHER_ENABLE) 583 if (dither == AMDGPU_FMT_DITHER_ENABLE)
579 /* XXX sort out optimal dither settings */ 584 /* XXX sort out optimal dither settings */
580 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | 585 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
581 FMT_RGB_RANDOM_ENABLE | 586 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
582 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); 587 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
588 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
589 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
583 else 590 else
584 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); 591 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
592 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
585 break; 593 break;
586 case 10: 594 case 10:
587 default: 595 default:
@@ -589,7 +597,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
589 break; 597 break;
590 } 598 }
591 599
592 WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 600 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
593} 601}
594 602
595/** 603/**
@@ -603,7 +611,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
603 */ 611 */
604static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 612static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
605{ 613{
606 u32 tmp = RREG32(MC_SHARED_CHMAP); 614 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
607 615
608 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 616 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
609 case 0: 617 case 0:
@@ -1100,28 +1108,28 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
1100 } 1108 }
1101 1109
1102 /* select wm A */ 1110 /* select wm A */
1103 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1111 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1104 tmp = arb_control3; 1112 tmp = arb_control3;
1105 tmp &= ~LATENCY_WATERMARK_MASK(3); 1113 tmp &= ~LATENCY_WATERMARK_MASK(3);
1106 tmp |= LATENCY_WATERMARK_MASK(1); 1114 tmp |= LATENCY_WATERMARK_MASK(1);
1107 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1115 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1108 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, 1116 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1109 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 1117 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1110 LATENCY_HIGH_WATERMARK(line_time))); 1118 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1111 /* select wm B */ 1119 /* select wm B */
1112 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1120 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1113 tmp &= ~LATENCY_WATERMARK_MASK(3); 1121 tmp &= ~LATENCY_WATERMARK_MASK(3);
1114 tmp |= LATENCY_WATERMARK_MASK(2); 1122 tmp |= LATENCY_WATERMARK_MASK(2);
1115 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1123 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1116 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, 1124 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1117 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 1125 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1118 LATENCY_HIGH_WATERMARK(line_time))); 1126 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1119 /* restore original selection */ 1127 /* restore original selection */
1120 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1128 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1121 1129
1122 /* write the priority marks */ 1130 /* write the priority marks */
1123 WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1131 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1124 WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1132 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1125 1133
1126 /* save values for DPM */ 1134 /* save values for DPM */
1127 amdgpu_crtc->line_time = line_time; 1135 amdgpu_crtc->line_time = line_time;
@@ -1139,7 +1147,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1139 /* 1147 /*
1140 * Line Buffer Setup 1148 * Line Buffer Setup
1141 * There are 3 line buffers, each one shared by 2 display controllers. 1149 * There are 3 line buffers, each one shared by 2 display controllers.
1142 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1150 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1143 * the display controllers. The paritioning is done via one of four 1151 * the display controllers. The paritioning is done via one of four
1144 * preset allocations specified in bits 21:20: 1152 * preset allocations specified in bits 21:20:
1145 * 0 - half lb 1153 * 0 - half lb
@@ -1162,14 +1170,14 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1162 buffer_alloc = 0; 1170 buffer_alloc = 0;
1163 } 1171 }
1164 1172
1165 WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1173 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1166 DC_LB_MEMORY_CONFIG(tmp)); 1174 DC_LB_MEMORY_CONFIG(tmp));
1167 1175
1168 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1176 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1169 DMIF_BUFFERS_ALLOCATED(buffer_alloc)); 1177 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1170 for (i = 0; i < adev->usec_timeout; i++) { 1178 for (i = 0; i < adev->usec_timeout; i++) {
1171 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1179 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1172 DMIF_BUFFERS_ALLOCATED_COMPLETED) 1180 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1173 break; 1181 break;
1174 udelay(1); 1182 udelay(1);
1175 } 1183 }
@@ -1411,12 +1419,12 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1411 1419
1412static const u32 vga_control_regs[6] = 1420static const u32 vga_control_regs[6] =
1413{ 1421{
1414 AVIVO_D1VGA_CONTROL, 1422 mmD1VGA_CONTROL,
1415 AVIVO_D2VGA_CONTROL, 1423 mmD2VGA_CONTROL,
1416 EVERGREEN_D3VGA_CONTROL, 1424 mmD3VGA_CONTROL,
1417 EVERGREEN_D4VGA_CONTROL, 1425 mmD4VGA_CONTROL,
1418 EVERGREEN_D5VGA_CONTROL, 1426 mmD5VGA_CONTROL,
1419 EVERGREEN_D6VGA_CONTROL, 1427 mmD6VGA_CONTROL,
1420}; 1428};
1421 1429
1422static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1430static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
@@ -1436,7 +1444,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1436 struct drm_device *dev = crtc->dev; 1444 struct drm_device *dev = crtc->dev;
1437 struct amdgpu_device *adev = dev->dev_private; 1445 struct amdgpu_device *adev = dev->dev_private;
1438 1446
1439 WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1447 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1440} 1448}
1441 1449
1442static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1450static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
@@ -1452,7 +1460,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1452 struct amdgpu_bo *abo; 1460 struct amdgpu_bo *abo;
1453 uint64_t fb_location, tiling_flags; 1461 uint64_t fb_location, tiling_flags;
1454 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1462 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1455 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1463 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1456 u32 viewport_w, viewport_h; 1464 u32 viewport_w, viewport_h;
1457 int r; 1465 int r;
1458 bool bypass_lut = false; 1466 bool bypass_lut = false;
@@ -1496,64 +1504,64 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1496 1504
1497 switch (target_fb->pixel_format) { 1505 switch (target_fb->pixel_format) {
1498 case DRM_FORMAT_C8: 1506 case DRM_FORMAT_C8:
1499 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1507 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1500 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1508 GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1501 break; 1509 break;
1502 case DRM_FORMAT_XRGB4444: 1510 case DRM_FORMAT_XRGB4444:
1503 case DRM_FORMAT_ARGB4444: 1511 case DRM_FORMAT_ARGB4444:
1504 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1512 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1505 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1513 GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1506#ifdef __BIG_ENDIAN 1514#ifdef __BIG_ENDIAN
1507 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1515 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1508#endif 1516#endif
1509 break; 1517 break;
1510 case DRM_FORMAT_XRGB1555: 1518 case DRM_FORMAT_XRGB1555:
1511 case DRM_FORMAT_ARGB1555: 1519 case DRM_FORMAT_ARGB1555:
1512 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1520 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1513 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1521 GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1514#ifdef __BIG_ENDIAN 1522#ifdef __BIG_ENDIAN
1515 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1523 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1516#endif 1524#endif
1517 break; 1525 break;
1518 case DRM_FORMAT_BGRX5551: 1526 case DRM_FORMAT_BGRX5551:
1519 case DRM_FORMAT_BGRA5551: 1527 case DRM_FORMAT_BGRA5551:
1520 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1528 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1521 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1529 GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1522#ifdef __BIG_ENDIAN 1530#ifdef __BIG_ENDIAN
1523 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1531 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1524#endif 1532#endif
1525 break; 1533 break;
1526 case DRM_FORMAT_RGB565: 1534 case DRM_FORMAT_RGB565:
1527 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1535 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1528 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1536 GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1529#ifdef __BIG_ENDIAN 1537#ifdef __BIG_ENDIAN
1530 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1538 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1531#endif 1539#endif
1532 break; 1540 break;
1533 case DRM_FORMAT_XRGB8888: 1541 case DRM_FORMAT_XRGB8888:
1534 case DRM_FORMAT_ARGB8888: 1542 case DRM_FORMAT_ARGB8888:
1535 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1543 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1536 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1544 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1537#ifdef __BIG_ENDIAN 1545#ifdef __BIG_ENDIAN
1538 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1546 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1539#endif 1547#endif
1540 break; 1548 break;
1541 case DRM_FORMAT_XRGB2101010: 1549 case DRM_FORMAT_XRGB2101010:
1542 case DRM_FORMAT_ARGB2101010: 1550 case DRM_FORMAT_ARGB2101010:
1543 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1551 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1544 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1552 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1545#ifdef __BIG_ENDIAN 1553#ifdef __BIG_ENDIAN
1546 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1554 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1547#endif 1555#endif
1548 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1556 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1549 bypass_lut = true; 1557 bypass_lut = true;
1550 break; 1558 break;
1551 case DRM_FORMAT_BGRX1010102: 1559 case DRM_FORMAT_BGRX1010102:
1552 case DRM_FORMAT_BGRA1010102: 1560 case DRM_FORMAT_BGRA1010102:
1553 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1561 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1554 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1562 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1555#ifdef __BIG_ENDIAN 1563#ifdef __BIG_ENDIAN
1556 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1564 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1557#endif 1565#endif
1558 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1566 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1559 bypass_lut = true; 1567 bypass_lut = true;
@@ -1573,75 +1581,75 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1573 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1581 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1574 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1582 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1575 1583
1576 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1584 fb_format |= GRPH_NUM_BANKS(num_banks);
1577 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1585 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1578 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1586 fb_format |= GRPH_TILE_SPLIT(tile_split);
1579 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1587 fb_format |= GRPH_BANK_WIDTH(bankw);
1580 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1588 fb_format |= GRPH_BANK_HEIGHT(bankh);
1581 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1589 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1582 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1590 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1583 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1591 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1584 } 1592 }
1585 1593
1586 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1594 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1587 fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config); 1595 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1588 1596
1589 dce_v6_0_vga_enable(crtc, false); 1597 dce_v6_0_vga_enable(crtc, false);
1590 1598
1591 /* Make sure surface address is updated at vertical blank rather than 1599 /* Make sure surface address is updated at vertical blank rather than
1592 * horizontal blank 1600 * horizontal blank
1593 */ 1601 */
1594 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 1602 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1595 1603
1596 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1604 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1597 upper_32_bits(fb_location)); 1605 upper_32_bits(fb_location));
1598 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1606 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1599 upper_32_bits(fb_location)); 1607 upper_32_bits(fb_location));
1600 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1608 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1601 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1609 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1602 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1610 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1603 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1611 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1604 WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1612 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1605 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap); 1613 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1606 1614
1607 /* 1615 /*
1608 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1616 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1609 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1617 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1610 * retain the full precision throughout the pipeline. 1618 * retain the full precision throughout the pipeline.
1611 */ 1619 */
1612 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, 1620 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1613 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1621 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1614 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1622 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1615 1623
1616 if (bypass_lut) 1624 if (bypass_lut)
1617 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1625 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1618 1626
1619 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 1627 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1620 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 1628 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1621 WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0); 1629 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1622 WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 1630 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1623 WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 1631 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1624 WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 1632 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1625 1633
1626 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1634 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1627 WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 1635 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1628 1636
1629 dce_v6_0_grph_enable(crtc, true); 1637 dce_v6_0_grph_enable(crtc, true);
1630 1638
1631 WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 1639 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1632 target_fb->height); 1640 target_fb->height);
1633 x &= ~3; 1641 x &= ~3;
1634 y &= ~1; 1642 y &= ~1;
1635 WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset, 1643 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1636 (x << 16) | y); 1644 (x << 16) | y);
1637 viewport_w = crtc->mode.hdisplay; 1645 viewport_w = crtc->mode.hdisplay;
1638 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1646 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1639 1647
1640 WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 1648 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1641 (viewport_w << 16) | viewport_h); 1649 (viewport_w << 16) | viewport_h);
1642 1650
1643 /* set pageflip to happen anywhere in vblank interval */ 1651 /* set pageflip to happen anywhere in vblank interval */
1644 WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 1652 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1645 1653
1646 if (!atomic && fb && fb != crtc->primary->fb) { 1654 if (!atomic && fb && fb != crtc->primary->fb) {
1647 amdgpu_fb = to_amdgpu_framebuffer(fb); 1655 amdgpu_fb = to_amdgpu_framebuffer(fb);
@@ -1668,10 +1676,10 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1668 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1676 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1669 1677
1670 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1678 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1671 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 1679 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
1672 EVERGREEN_INTERLEAVE_EN); 1680 INTERLEAVE_EN);
1673 else 1681 else
1674 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 1682 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1675} 1683}
1676 1684
1677static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 1685static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
@@ -1684,54 +1692,52 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
1684 1692
1685 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 1693 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
1686 1694
1687 WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 1695 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1688 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 1696 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
1689 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 1697 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
1690 WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 1698 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
1691 NI_GRPH_PRESCALE_BYPASS); 1699 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
1692 WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 1700 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
1693 NI_OVL_PRESCALE_BYPASS); 1701 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
1694 WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1702 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1695 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 1703 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
1696 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 1704 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
1697
1698
1699 1705
1700 WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 1706 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
1701 1707
1702 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 1708 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
1703 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 1709 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
1704 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 1710 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
1705 1711
1706 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 1712 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
1707 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 1713 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
1708 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 1714 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
1709 1715
1710 WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 1716 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
1711 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 1717 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
1712 1718
1713 WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 1719 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
1714 for (i = 0; i < 256; i++) { 1720 for (i = 0; i < 256; i++) {
1715 WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 1721 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
1716 (amdgpu_crtc->lut_r[i] << 20) | 1722 (amdgpu_crtc->lut_r[i] << 20) |
1717 (amdgpu_crtc->lut_g[i] << 10) | 1723 (amdgpu_crtc->lut_g[i] << 10) |
1718 (amdgpu_crtc->lut_b[i] << 0)); 1724 (amdgpu_crtc->lut_b[i] << 0));
1719 } 1725 }
1720 1726
1721 WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1727 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1722 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 1728 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
1723 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 1729 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
1724 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 1730 ICON_DEGAMMA_MODE(0) |
1725 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 1731 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
1726 WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 1732 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
1727 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 1733 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
1728 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 1734 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
1729 WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1735 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1730 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 1736 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
1731 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 1737 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
1732 WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 1738 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1733 (NI_OUTPUT_CSC_GRPH_MODE(0) | 1739 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
1734 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 1740 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
1735 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 1741 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
1736 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 1742 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
1737 1743
@@ -1810,12 +1816,12 @@ static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
1810 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1816 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1811 uint32_t cur_lock; 1817 uint32_t cur_lock;
1812 1818
1813 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset); 1819 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
1814 if (lock) 1820 if (lock)
1815 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 1821 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1816 else 1822 else
1817 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 1823 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1818 WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 1824 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
1819} 1825}
1820 1826
1821static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 1827static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
@@ -1823,9 +1829,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
1823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1829 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1824 struct amdgpu_device *adev = crtc->dev->dev_private; 1830 struct amdgpu_device *adev = crtc->dev->dev_private;
1825 1831
1826 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, 1832 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1827 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 1833 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1828 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 1834 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1829 1835
1830 1836
1831} 1837}
@@ -1835,15 +1841,15 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
1835 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1841 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1836 struct amdgpu_device *adev = crtc->dev->dev_private; 1842 struct amdgpu_device *adev = crtc->dev->dev_private;
1837 1843
1838 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1844 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1839 upper_32_bits(amdgpu_crtc->cursor_addr)); 1845 upper_32_bits(amdgpu_crtc->cursor_addr));
1840 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1846 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1841 lower_32_bits(amdgpu_crtc->cursor_addr)); 1847 lower_32_bits(amdgpu_crtc->cursor_addr));
1842 1848
1843 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, 1849 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1844 EVERGREEN_CURSOR_EN | 1850 CUR_CONTROL__CURSOR_EN_MASK |
1845 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 1851 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1846 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 1852 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1847 1853
1848} 1854}
1849 1855
@@ -1870,9 +1876,9 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1870 y = 0; 1876 y = 0;
1871 } 1877 }
1872 1878
1873 WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 1879 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1874 WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 1880 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1875 WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset, 1881 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
1876 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 1882 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1877 1883
1878 amdgpu_crtc->cursor_x = x; 1884 amdgpu_crtc->cursor_x = x;
@@ -2478,14 +2484,14 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2478 2484
2479 switch (state) { 2485 switch (state) {
2480 case AMDGPU_IRQ_STATE_DISABLE: 2486 case AMDGPU_IRQ_STATE_DISABLE:
2481 interrupt_mask = RREG32(INT_MASK + reg_block); 2487 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2482 interrupt_mask &= ~VBLANK_INT_MASK; 2488 interrupt_mask &= ~VBLANK_INT_MASK;
2483 WREG32(INT_MASK + reg_block, interrupt_mask); 2489 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2484 break; 2490 break;
2485 case AMDGPU_IRQ_STATE_ENABLE: 2491 case AMDGPU_IRQ_STATE_ENABLE:
2486 interrupt_mask = RREG32(INT_MASK + reg_block); 2492 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2487 interrupt_mask |= VBLANK_INT_MASK; 2493 interrupt_mask |= VBLANK_INT_MASK;
2488 WREG32(INT_MASK + reg_block, interrupt_mask); 2494 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2489 break; 2495 break;
2490 default: 2496 default:
2491 break; 2497 break;
@@ -2513,14 +2519,14 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2513 2519
2514 switch (state) { 2520 switch (state) {
2515 case AMDGPU_IRQ_STATE_DISABLE: 2521 case AMDGPU_IRQ_STATE_DISABLE:
2516 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); 2522 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2517 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 2523 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2518 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2524 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2519 break; 2525 break;
2520 case AMDGPU_IRQ_STATE_ENABLE: 2526 case AMDGPU_IRQ_STATE_ENABLE:
2521 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); 2527 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2522 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 2528 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2523 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2529 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2524 break; 2530 break;
2525 default: 2531 default:
2526 break; 2532 break;
@@ -2588,7 +2594,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2588 switch (entry->src_data) { 2594 switch (entry->src_data) {
2589 case 0: /* vblank */ 2595 case 0: /* vblank */
2590 if (disp_int & interrupt_status_offsets[crtc].vblank) 2596 if (disp_int & interrupt_status_offsets[crtc].vblank)
2591 WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 2597 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2592 else 2598 else
2593 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2599 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2594 2600
@@ -2599,7 +2605,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2599 break; 2605 break;
2600 case 1: /* vline */ 2606 case 1: /* vline */
2601 if (disp_int & interrupt_status_offsets[crtc].vline) 2607 if (disp_int & interrupt_status_offsets[crtc].vline)
2602 WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 2608 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2603 else 2609 else
2604 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2610 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2605 2611
@@ -2625,12 +2631,12 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2625 return -EINVAL; 2631 return -EINVAL;
2626 } 2632 }
2627 2633
2628 reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]); 2634 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
2629 if (state == AMDGPU_IRQ_STATE_DISABLE) 2635 if (state == AMDGPU_IRQ_STATE_DISABLE)
2630 WREG32(GRPH_INT_CONTROL + crtc_offsets[type], 2636 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2631 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2637 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2632 else 2638 else
2633 WREG32(GRPH_INT_CONTROL + crtc_offsets[type], 2639 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2634 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2640 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2635 2641
2636 return 0; 2642 return 0;
@@ -2653,9 +2659,9 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2653 return -EINVAL; 2659 return -EINVAL;
2654 } 2660 }
2655 2661
2656 if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) & 2662 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
2657 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 2663 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2658 WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id], 2664 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
2659 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 2665 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2660 2666
2661 /* IRQ could occur when in initial stage */ 2667 /* IRQ could occur when in initial stage */
@@ -2706,9 +2712,9 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
2706 mask = interrupt_status_offsets[hpd].hpd; 2712 mask = interrupt_status_offsets[hpd].hpd;
2707 2713
2708 if (disp_int & mask) { 2714 if (disp_int & mask) {
2709 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 2715 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
2710 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 2716 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
2711 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 2717 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
2712 schedule_work(&adev->hotplug_work); 2718 schedule_work(&adev->hotplug_work);
2713 DRM_INFO("IH: HPD%d\n", hpd + 1); 2719 DRM_INFO("IH: HPD%d\n", hpd + 1);
2714 } 2720 }
@@ -3024,7 +3030,6 @@ static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3024 .bandwidth_update = &dce_v6_0_bandwidth_update, 3030 .bandwidth_update = &dce_v6_0_bandwidth_update,
3025 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3031 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3026 .vblank_wait = &dce_v6_0_vblank_wait, 3032 .vblank_wait = &dce_v6_0_vblank_wait,
3027 .is_display_hung = &dce_v6_0_is_display_hung,
3028 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3033 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3029 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3034 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3030 .hpd_sense = &dce_v6_0_hpd_sense, 3035 .hpd_sense = &dce_v6_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 4ae59914bc32..a699896eeabc 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3586,7 +3586,6 @@ static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3586 .bandwidth_update = &dce_v8_0_bandwidth_update, 3586 .bandwidth_update = &dce_v8_0_bandwidth_update,
3587 .vblank_get_counter = &dce_v8_0_vblank_get_counter, 3587 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3588 .vblank_wait = &dce_v8_0_vblank_wait, 3588 .vblank_wait = &dce_v8_0_vblank_wait,
3589 .is_display_hung = &dce_v8_0_is_display_hung,
3590 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3589 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3591 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3590 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3592 .hpd_sense = &dce_v8_0_hpd_sense, 3591 .hpd_sense = &dce_v8_0_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 81cbf0b05dff..a2442534e17b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -95,11 +95,6 @@ static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
95 return 0; 95 return 0;
96} 96}
97 97
98static bool dce_virtual_is_display_hung(struct amdgpu_device *adev)
99{
100 return false;
101}
102
103static void dce_virtual_stop_mc_access(struct amdgpu_device *adev, 98static void dce_virtual_stop_mc_access(struct amdgpu_device *adev,
104 struct amdgpu_mode_mc_save *save) 99 struct amdgpu_mode_mc_save *save)
105{ 100{
@@ -691,7 +686,6 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
691 .bandwidth_update = &dce_virtual_bandwidth_update, 686 .bandwidth_update = &dce_virtual_bandwidth_update,
692 .vblank_get_counter = &dce_virtual_vblank_get_counter, 687 .vblank_get_counter = &dce_virtual_vblank_get_counter,
693 .vblank_wait = &dce_virtual_vblank_wait, 688 .vblank_wait = &dce_virtual_vblank_wait,
694 .is_display_hung = &dce_virtual_is_display_hung,
695 .backlight_set_level = NULL, 689 .backlight_set_level = NULL,
696 .backlight_get_level = NULL, 690 .backlight_get_level = NULL,
697 .hpd_sense = &dce_virtual_hpd_sense, 691 .hpd_sense = &dce_virtual_hpd_sense,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 21c086e02e7b..879a94bbfe12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -26,15 +26,18 @@
26#include "amdgpu_gfx.h" 26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h" 27#include "amdgpu_ucode.h"
28#include "si/clearstate_si.h" 28#include "si/clearstate_si.h"
29#include "si/sid.h" 29#include "bif/bif_3_0_d.h"
30 30#include "bif/bif_3_0_sh_mask.h"
31#define GFX6_NUM_GFX_RINGS 1 31#include "oss/oss_1_0_d.h"
32#define GFX6_NUM_COMPUTE_RINGS 2 32#include "oss/oss_1_0_sh_mask.h"
33#define STATIC_PER_CU_PG_ENABLE (1 << 3) 33#include "gca/gfx_6_0_d.h"
34#define DYN_PER_CU_PG_ENABLE (1 << 2) 34#include "gca/gfx_6_0_sh_mask.h"
35#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 35#include "gmc/gmc_6_0_d.h"
36#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 36#include "gmc/gmc_6_0_sh_mask.h"
37 37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
38 41
39static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 42static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
40static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 43static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -70,6 +73,15 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *bu
70//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 73//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
71static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 74static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
72 75
76#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79#define MICRO_TILE_MODE(x) ((x) << 0)
80#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81#define BANK_WIDTH(x) ((x) << 14)
82#define BANK_HEIGHT(x) ((x) << 16)
83#define MACRO_TILE_ASPECT(x) ((x) << 18)
84#define NUM_BANKS(x) ((x) << 20)
73 85
74static const u32 verde_rlc_save_restore_register_list[] = 86static const u32 verde_rlc_save_restore_register_list[] =
75{ 87{
@@ -400,8 +412,8 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
400 } 412 }
401 413
402 if (adev->asic_type == CHIP_VERDE || 414 if (adev->asic_type == CHIP_VERDE ||
403 adev->asic_type == CHIP_OLAND || 415 adev->asic_type == CHIP_OLAND ||
404 adev->asic_type == CHIP_HAINAN) { 416 adev->asic_type == CHIP_HAINAN) {
405 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 417 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
406 switch (reg_offset) { 418 switch (reg_offset) {
407 case 0: 419 case 0:
@@ -414,7 +426,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
416 break; 428 break;
417 case 1: 429 case 1:
418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 430 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 431 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 432 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -434,7 +446,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
436 break; 448 break;
437 case 3: 449 case 3:
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 450 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 451 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 452 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -444,7 +456,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
446 break; 458 break;
447 case 4: 459 case 4:
448 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 460 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
449 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 461 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -454,7 +466,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
456 break; 468 break;
457 case 5: 469 case 5:
458 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 470 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
459 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 471 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 472 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -464,7 +476,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
466 break; 478 break;
467 case 6: 479 case 6:
468 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 480 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 481 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -474,7 +486,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
476 break; 488 break;
477 case 7: 489 case 7:
478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 490 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
479 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 491 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
480 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 492 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -484,7 +496,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 496 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 497 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
486 break; 498 break;
487 case 8: 499 case 8:
488 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 500 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
489 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 501 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 502 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -494,7 +506,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
496 break; 508 break;
497 case 9: 509 case 9:
498 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 510 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
499 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 511 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
500 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 512 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -504,7 +516,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
506 break; 518 break;
507 case 10: 519 case 10:
508 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 520 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 521 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 522 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -514,7 +526,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
516 break; 528 break;
517 case 11: 529 case 11:
518 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 530 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
519 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 531 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -524,7 +536,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
526 break; 538 break;
527 case 12: 539 case 12:
528 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 540 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
529 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 541 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
530 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 542 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -534,7 +546,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
536 break; 548 break;
537 case 13: 549 case 13:
538 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 550 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
539 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 551 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 552 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -544,7 +556,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
546 break; 558 break;
547 case 14: 559 case 14:
548 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 560 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
549 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 561 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 562 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -554,7 +566,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
556 break; 568 break;
557 case 15: 569 case 15:
558 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 570 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 571 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 572 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -564,7 +576,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 576 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 577 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
566 break; 578 break;
567 case 16: 579 case 16:
568 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 580 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
569 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 581 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 582 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -574,7 +586,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
576 break; 588 break;
577 case 17: 589 case 17:
578 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 590 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 591 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 592 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
@@ -584,7 +596,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
586 break; 598 break;
587 case 21: 599 case 21:
588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 600 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
589 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 601 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 602 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -594,7 +606,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
596 break; 608 break;
597 case 22: 609 case 22:
598 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 610 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 611 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
600 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 612 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -604,7 +616,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
606 break; 618 break;
607 case 23: 619 case 23:
608 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 620 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
609 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 621 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 622 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -614,7 +626,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
616 break; 628 break;
617 case 24: 629 case 24:
618 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 630 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
619 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 631 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
620 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 632 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -624,7 +636,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
626 break; 638 break;
627 case 25: 639 case 25:
628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 640 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
629 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 641 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 642 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
@@ -639,7 +651,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
639 break; 651 break;
640 } 652 }
641 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 653 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
642 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); 654 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
643 } 655 }
644 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 656 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 657 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
@@ -879,7 +891,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
879 break; 891 break;
880 } 892 }
881 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 893 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
882 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); 894 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
883 } 895 }
884 } else{ 896 } else{
885 897
@@ -894,19 +906,23 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
894 u32 data; 906 u32 data;
895 907
896 if (instance == 0xffffffff) 908 if (instance == 0xffffffff)
897 data = INSTANCE_BROADCAST_WRITES; 909 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
898 else 910 else
899 data = INSTANCE_INDEX(instance); 911 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
900 912
901 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 913 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
902 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 914 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
915 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
903 else if (se_num == 0xffffffff) 916 else if (se_num == 0xffffffff)
904 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 917 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
918 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
905 else if (sh_num == 0xffffffff) 919 else if (sh_num == 0xffffffff)
906 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); 920 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
921 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
907 else 922 else
908 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); 923 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
909 WREG32(GRBM_GFX_INDEX, data); 924 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
925 WREG32(mmGRBM_GFX_INDEX, data);
910} 926}
911 927
912static u32 gfx_v6_0_create_bitmask(u32 bit_width) 928static u32 gfx_v6_0_create_bitmask(u32 bit_width)
@@ -920,11 +936,11 @@ static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
920{ 936{
921 u32 data, mask; 937 u32 data, mask;
922 938
923 data = RREG32(CC_RB_BACKEND_DISABLE); 939 data = RREG32(mmCC_RB_BACKEND_DISABLE);
924 data &= BACKEND_DISABLE_MASK; 940 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
925 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); 941 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
926 942
927 data >>= BACKEND_DISABLE_SHIFT; 943 data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
928 944
929 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se); 945 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
930 946
@@ -936,14 +952,23 @@ static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
936 switch (adev->asic_type) { 952 switch (adev->asic_type) {
937 case CHIP_TAHITI: 953 case CHIP_TAHITI:
938 case CHIP_PITCAIRN: 954 case CHIP_PITCAIRN:
939 *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) | 955 *rconf |=
940 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2); 956 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
957 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
958 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
959 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
960 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
961 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
962 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
941 break; 963 break;
942 case CHIP_VERDE: 964 case CHIP_VERDE:
943 *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1); 965 *rconf |=
966 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
967 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
968 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
944 break; 969 break;
945 case CHIP_OLAND: 970 case CHIP_OLAND:
946 *rconf |= RB_YSEL; 971 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
947 break; 972 break;
948 case CHIP_HAINAN: 973 case CHIP_HAINAN:
949 *rconf |= 0x0; 974 *rconf |= 0x0;
@@ -981,24 +1006,24 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
981 int idx = (se / 2) * 2; 1006 int idx = (se / 2) * 2;
982 1007
983 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1008 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
984 raster_config_se &= ~SE_MAP_MASK; 1009 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
985 1010
986 if (!se_mask[idx]) { 1011 if (!se_mask[idx]) {
987 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1012 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
988 } else { 1013 } else {
989 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1014 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
990 } 1015 }
991 } 1016 }
992 1017
993 pkr0_mask &= rb_mask; 1018 pkr0_mask &= rb_mask;
994 pkr1_mask &= rb_mask; 1019 pkr1_mask &= rb_mask;
995 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1020 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
996 raster_config_se &= ~PKR_MAP_MASK; 1021 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
997 1022
998 if (!pkr0_mask) { 1023 if (!pkr0_mask) {
999 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1024 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1000 } else { 1025 } else {
1001 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1026 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1002 } 1027 }
1003 } 1028 }
1004 1029
@@ -1009,14 +1034,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1009 rb0_mask &= rb_mask; 1034 rb0_mask &= rb_mask;
1010 rb1_mask &= rb_mask; 1035 rb1_mask &= rb_mask;
1011 if (!rb0_mask || !rb1_mask) { 1036 if (!rb0_mask || !rb1_mask) {
1012 raster_config_se &= ~RB_MAP_PKR0_MASK; 1037 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1013 1038
1014 if (!rb0_mask) { 1039 if (!rb0_mask) {
1015 raster_config_se |= 1040 raster_config_se |=
1016 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1041 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1017 } else { 1042 } else {
1018 raster_config_se |= 1043 raster_config_se |=
1019 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1044 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1020 } 1045 }
1021 } 1046 }
1022 1047
@@ -1026,14 +1051,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1026 rb0_mask &= rb_mask; 1051 rb0_mask &= rb_mask;
1027 rb1_mask &= rb_mask; 1052 rb1_mask &= rb_mask;
1028 if (!rb0_mask || !rb1_mask) { 1053 if (!rb0_mask || !rb1_mask) {
1029 raster_config_se &= ~RB_MAP_PKR1_MASK; 1054 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1030 1055
1031 if (!rb0_mask) { 1056 if (!rb0_mask) {
1032 raster_config_se |= 1057 raster_config_se |=
1033 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1058 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1034 } else { 1059 } else {
1035 raster_config_se |= 1060 raster_config_se |=
1036 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1061 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1037 } 1062 }
1038 } 1063 }
1039 } 1064 }
@@ -1041,7 +1066,7 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1041 1066
1042 /* GRBM_GFX_INDEX has a different offset on SI */ 1067 /* GRBM_GFX_INDEX has a different offset on SI */
1043 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1068 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1044 WREG32(PA_SC_RASTER_CONFIG, raster_config_se); 1069 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1045 } 1070 }
1046 1071
1047 /* GRBM_GFX_INDEX has a different offset on SI */ 1072 /* GRBM_GFX_INDEX has a different offset on SI */
@@ -1063,7 +1088,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1063 for (j = 0; j < sh_per_se; j++) { 1088 for (j = 0; j < sh_per_se; j++) {
1064 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1089 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1065 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); 1090 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1066 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 1091 disabled_rbs |= data << ((i * sh_per_se + j) * 2);
1067 } 1092 }
1068 } 1093 }
1069 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1094 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
@@ -1105,7 +1130,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1105 1130
1106 if (!adev->gfx.config.backend_enable_mask || 1131 if (!adev->gfx.config.backend_enable_mask ||
1107 adev->gfx.config.num_rbs >= num_rb_pipes) 1132 adev->gfx.config.num_rbs >= num_rb_pipes)
1108 WREG32(PA_SC_RASTER_CONFIG, data); 1133 WREG32(mmPA_SC_RASTER_CONFIG, data);
1109 else 1134 else
1110 gfx_v6_0_write_harvested_raster_configs(adev, data, 1135 gfx_v6_0_write_harvested_raster_configs(adev, data,
1111 adev->gfx.config.backend_enable_mask, 1136 adev->gfx.config.backend_enable_mask,
@@ -1124,11 +1149,11 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1124{ 1149{
1125 u32 data, mask; 1150 u32 data, mask;
1126 1151
1127 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 1152 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
1128 data &= INACTIVE_CUS_MASK; 1153 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1129 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); 1154 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1130 1155
1131 data >>= INACTIVE_CUS_SHIFT; 1156 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1132 1157
1133 mask = gfx_v6_0_create_bitmask(cu_per_sh); 1158 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1134 1159
@@ -1148,7 +1173,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1148 for (i = 0; i < se_num; i++) { 1173 for (i = 0; i < se_num; i++) {
1149 for (j = 0; j < sh_per_se; j++) { 1174 for (j = 0; j < sh_per_se; j++) {
1150 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1175 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1151 data = RREG32(SPI_STATIC_THREAD_MGMT_3); 1176 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1152 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh); 1177 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1153 1178
1154 mask = 1; 1179 mask = 1;
@@ -1156,7 +1181,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1156 mask <<= k; 1181 mask <<= k;
1157 if (active_cu & mask) { 1182 if (active_cu & mask) {
1158 data &= ~mask; 1183 data &= ~mask;
1159 WREG32(SPI_STATIC_THREAD_MGMT_3, data); 1184 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1160 break; 1185 break;
1161 } 1186 }
1162 } 1187 }
@@ -1209,7 +1234,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1209 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1234 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1210 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1235 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1211 break; 1236 break;
1212
1213 case CHIP_VERDE: 1237 case CHIP_VERDE:
1214 adev->gfx.config.max_shader_engines = 1; 1238 adev->gfx.config.max_shader_engines = 1;
1215 adev->gfx.config.max_tile_pipes = 4; 1239 adev->gfx.config.max_tile_pipes = 4;
@@ -1266,18 +1290,18 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1266 break; 1290 break;
1267 } 1291 }
1268 1292
1269 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1293 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1270 WREG32(SRBM_INT_CNTL, 1); 1294 WREG32(mmSRBM_INT_CNTL, 1);
1271 WREG32(SRBM_INT_ACK, 1); 1295 WREG32(mmSRBM_INT_ACK, 1);
1272 1296
1273 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1297 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1274 1298
1275 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1299 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1276 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1300 mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1277 1301
1278 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1302 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1279 adev->gfx.config.mem_max_burst_length_bytes = 256; 1303 adev->gfx.config.mem_max_burst_length_bytes = 256;
1280 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1304 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1281 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1305 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1282 if (adev->gfx.config.mem_row_size_in_kb > 4) 1306 if (adev->gfx.config.mem_row_size_in_kb > 4)
1283 adev->gfx.config.mem_row_size_in_kb = 4; 1307 adev->gfx.config.mem_row_size_in_kb = 4;
@@ -1285,32 +1309,33 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1285 adev->gfx.config.num_gpus = 1; 1309 adev->gfx.config.num_gpus = 1;
1286 adev->gfx.config.multi_gpu_tile_size = 64; 1310 adev->gfx.config.multi_gpu_tile_size = 64;
1287 1311
1288 gb_addr_config &= ~ROW_SIZE_MASK; 1312 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1289 switch (adev->gfx.config.mem_row_size_in_kb) { 1313 switch (adev->gfx.config.mem_row_size_in_kb) {
1290 case 1: 1314 case 1:
1291 default: 1315 default:
1292 gb_addr_config |= ROW_SIZE(0); 1316 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1293 break; 1317 break;
1294 case 2: 1318 case 2:
1295 gb_addr_config |= ROW_SIZE(1); 1319 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1296 break; 1320 break;
1297 case 4: 1321 case 4:
1298 gb_addr_config |= ROW_SIZE(2); 1322 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1299 break; 1323 break;
1300 } 1324 }
1301 adev->gfx.config.gb_addr_config = gb_addr_config; 1325 adev->gfx.config.gb_addr_config = gb_addr_config;
1302 1326
1303 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1327 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1304 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1328 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1305 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1329 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1306 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1330 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1307 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1331 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1308 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1332 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1333
1309#if 0 1334#if 0
1310 if (adev->has_uvd) { 1335 if (adev->has_uvd) {
1311 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 1336 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1312 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1337 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1313 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1338 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1314 } 1339 }
1315#endif 1340#endif
1316 gfx_v6_0_tiling_mode_table_init(adev); 1341 gfx_v6_0_tiling_mode_table_init(adev);
@@ -1325,45 +1350,48 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1325 1350
1326 gfx_v6_0_get_cu_info(adev); 1351 gfx_v6_0_get_cu_info(adev);
1327 1352
1328 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1353 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1329 ROQ_IB2_START(0x2b))); 1354 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1330 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1355 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1356 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1331 1357
1332 sx_debug_1 = RREG32(SX_DEBUG_1); 1358 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1333 WREG32(SX_DEBUG_1, sx_debug_1); 1359 WREG32(mmSX_DEBUG_1, sx_debug_1);
1334 1360
1335 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1361 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1336 1362
1337 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) | 1363 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1338 SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) | 1364 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1339 SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) | 1365 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1340 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size))); 1366 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1341 1367
1342 WREG32(VGT_NUM_INSTANCES, 1); 1368 WREG32(mmVGT_NUM_INSTANCES, 1);
1343 WREG32(CP_PERFMON_CNTL, 0); 1369 WREG32(mmCP_PERFMON_CNTL, 0);
1344 WREG32(SQ_CONFIG, 0); 1370 WREG32(mmSQ_CONFIG, 0);
1345 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1371 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1346 FORCE_EOV_MAX_REZ_CNT(255))); 1372 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1347 1373
1348 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1374 WREG32(mmVGT_CACHE_INVALIDATION,
1349 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1375 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1376 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1350 1377
1351 WREG32(VGT_GS_VERTEX_REUSE, 16); 1378 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1352 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1379 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1353 1380
1354 WREG32(CB_PERFCOUNTER0_SELECT0, 0); 1381 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1355 WREG32(CB_PERFCOUNTER0_SELECT1, 0); 1382 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1356 WREG32(CB_PERFCOUNTER1_SELECT0, 0); 1383 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1357 WREG32(CB_PERFCOUNTER1_SELECT1, 0); 1384 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1358 WREG32(CB_PERFCOUNTER2_SELECT0, 0); 1385 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1359 WREG32(CB_PERFCOUNTER2_SELECT1, 0); 1386 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1360 WREG32(CB_PERFCOUNTER3_SELECT0, 0); 1387 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1361 WREG32(CB_PERFCOUNTER3_SELECT1, 0); 1388 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1362 1389
1363 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1390 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1364 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1391 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1365 1392
1366 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1393 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1394 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1367 1395
1368 udelay(50); 1396 udelay(50);
1369} 1397}
@@ -1374,7 +1402,7 @@ static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1374 int i; 1402 int i;
1375 1403
1376 adev->gfx.scratch.num_reg = 7; 1404 adev->gfx.scratch.num_reg = 7;
1377 adev->gfx.scratch.reg_base = SCRATCH_REG0; 1405 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1378 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 1406 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1379 adev->gfx.scratch.free[i] = true; 1407 adev->gfx.scratch.free[i] = true;
1380 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 1408 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
@@ -1430,11 +1458,18 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1430 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1458 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1431 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1459 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1432 WRITE_DATA_DST_SEL(0))); 1460 WRITE_DATA_DST_SEL(0)));
1433 amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL); 1461 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1434 amdgpu_ring_write(ring, 0); 1462 amdgpu_ring_write(ring, 0);
1435 amdgpu_ring_write(ring, 0x1); 1463 amdgpu_ring_write(ring, 0x1);
1436} 1464}
1437 1465
1466static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1467{
1468 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1469 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1470 EVENT_INDEX(0));
1471}
1472
1438/** 1473/**
1439 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1474 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1440 * 1475 *
@@ -1448,7 +1483,7 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1448 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1483 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1449 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1484 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1450 WRITE_DATA_DST_SEL(0))); 1485 WRITE_DATA_DST_SEL(0)));
1451 amdgpu_ring_write(ring, HDP_DEBUG0); 1486 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1452 amdgpu_ring_write(ring, 0); 1487 amdgpu_ring_write(ring, 0);
1453 amdgpu_ring_write(ring, 0x1); 1488 amdgpu_ring_write(ring, 0x1);
1454} 1489}
@@ -1460,7 +1495,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1460 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1495 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1461 /* flush read cache over gart */ 1496 /* flush read cache over gart */
1462 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1497 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1463 amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1498 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1464 amdgpu_ring_write(ring, 0); 1499 amdgpu_ring_write(ring, 0);
1465 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1500 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1466 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1501 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
@@ -1475,7 +1510,8 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1475 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1510 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1476 amdgpu_ring_write(ring, addr & 0xfffffffc); 1511 amdgpu_ring_write(ring, addr & 0xfffffffc);
1477 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1512 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1478 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 1513 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1514 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1479 amdgpu_ring_write(ring, lower_32_bits(seq)); 1515 amdgpu_ring_write(ring, lower_32_bits(seq));
1480 amdgpu_ring_write(ring, upper_32_bits(seq)); 1516 amdgpu_ring_write(ring, upper_32_bits(seq));
1481} 1517}
@@ -1578,11 +1614,13 @@ err1:
1578static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1614static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1579{ 1615{
1580 int i; 1616 int i;
1581 if (enable) 1617 if (enable) {
1582 WREG32(CP_ME_CNTL, 0); 1618 WREG32(mmCP_ME_CNTL, 0);
1583 else { 1619 } else {
1584 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 1620 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1585 WREG32(SCRATCH_UMSK, 0); 1621 CP_ME_CNTL__PFP_HALT_MASK |
1622 CP_ME_CNTL__CE_HALT_MASK));
1623 WREG32(mmSCRATCH_UMSK, 0);
1586 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1624 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1587 adev->gfx.gfx_ring[i].ready = false; 1625 adev->gfx.gfx_ring[i].ready = false;
1588 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1626 for (i = 0; i < adev->gfx.num_compute_rings; i++)
@@ -1616,34 +1654,33 @@ static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1616 fw_data = (const __le32 *) 1654 fw_data = (const __le32 *)
1617 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1655 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1618 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1656 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1619 WREG32(CP_PFP_UCODE_ADDR, 0); 1657 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1620 for (i = 0; i < fw_size; i++) 1658 for (i = 0; i < fw_size; i++)
1621 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1659 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1622 WREG32(CP_PFP_UCODE_ADDR, 0); 1660 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1623 1661
1624 /* CE */ 1662 /* CE */
1625 fw_data = (const __le32 *) 1663 fw_data = (const __le32 *)
1626 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1664 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1627 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1665 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1628 WREG32(CP_CE_UCODE_ADDR, 0); 1666 WREG32(mmCP_CE_UCODE_ADDR, 0);
1629 for (i = 0; i < fw_size; i++) 1667 for (i = 0; i < fw_size; i++)
1630 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1668 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1631 WREG32(CP_CE_UCODE_ADDR, 0); 1669 WREG32(mmCP_CE_UCODE_ADDR, 0);
1632 1670
1633 /* ME */ 1671 /* ME */
1634 fw_data = (const __be32 *) 1672 fw_data = (const __be32 *)
1635 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1673 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1636 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1674 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1637 WREG32(CP_ME_RAM_WADDR, 0); 1675 WREG32(mmCP_ME_RAM_WADDR, 0);
1638 for (i = 0; i < fw_size; i++) 1676 for (i = 0; i < fw_size; i++)
1639 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1677 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1640 WREG32(CP_ME_RAM_WADDR, 0); 1678 WREG32(mmCP_ME_RAM_WADDR, 0);
1641
1642 1679
1643 WREG32(CP_PFP_UCODE_ADDR, 0); 1680 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1644 WREG32(CP_CE_UCODE_ADDR, 0); 1681 WREG32(mmCP_CE_UCODE_ADDR, 0);
1645 WREG32(CP_ME_RAM_WADDR, 0); 1682 WREG32(mmCP_ME_RAM_WADDR, 0);
1646 WREG32(CP_ME_RAM_RADDR, 0); 1683 WREG32(mmCP_ME_RAM_RADDR, 0);
1647 return 0; 1684 return 0;
1648} 1685}
1649 1686
@@ -1720,14 +1757,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1720 int r; 1757 int r;
1721 u64 rptr_addr; 1758 u64 rptr_addr;
1722 1759
1723 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1760 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
1724 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1761 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1725 1762
1726 /* Set the write pointer delay */ 1763 /* Set the write pointer delay */
1727 WREG32(CP_RB_WPTR_DELAY, 0); 1764 WREG32(mmCP_RB_WPTR_DELAY, 0);
1728 1765
1729 WREG32(CP_DEBUG, 0); 1766 WREG32(mmCP_DEBUG, 0);
1730 WREG32(SCRATCH_ADDR, 0); 1767 WREG32(mmSCRATCH_ADDR, 0);
1731 1768
1732 /* ring 0 - compute and gfx */ 1769 /* ring 0 - compute and gfx */
1733 /* Set ring buffer size */ 1770 /* Set ring buffer size */
@@ -1738,24 +1775,24 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1738#ifdef __BIG_ENDIAN 1775#ifdef __BIG_ENDIAN
1739 tmp |= BUF_SWAP_32BIT; 1776 tmp |= BUF_SWAP_32BIT;
1740#endif 1777#endif
1741 WREG32(CP_RB0_CNTL, tmp); 1778 WREG32(mmCP_RB0_CNTL, tmp);
1742 1779
1743 /* Initialize the ring buffer's read and write pointers */ 1780 /* Initialize the ring buffer's read and write pointers */
1744 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 1781 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
1745 ring->wptr = 0; 1782 ring->wptr = 0;
1746 WREG32(CP_RB0_WPTR, ring->wptr); 1783 WREG32(mmCP_RB0_WPTR, ring->wptr);
1747 1784
1748 /* set the wb address whether it's enabled or not */ 1785 /* set the wb address whether it's enabled or not */
1749 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1786 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1750 WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 1787 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1751 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1788 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1752 1789
1753 WREG32(SCRATCH_UMSK, 0); 1790 WREG32(mmSCRATCH_UMSK, 0);
1754 1791
1755 mdelay(1); 1792 mdelay(1);
1756 WREG32(CP_RB0_CNTL, tmp); 1793 WREG32(mmCP_RB0_CNTL, tmp);
1757 1794
1758 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 1795 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
1759 1796
1760 /* start the rings */ 1797 /* start the rings */
1761 gfx_v6_0_cp_gfx_start(adev); 1798 gfx_v6_0_cp_gfx_start(adev);
@@ -1779,11 +1816,11 @@ static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
1779 struct amdgpu_device *adev = ring->adev; 1816 struct amdgpu_device *adev = ring->adev;
1780 1817
1781 if (ring == &adev->gfx.gfx_ring[0]) 1818 if (ring == &adev->gfx.gfx_ring[0])
1782 return RREG32(CP_RB0_WPTR); 1819 return RREG32(mmCP_RB0_WPTR);
1783 else if (ring == &adev->gfx.compute_ring[0]) 1820 else if (ring == &adev->gfx.compute_ring[0])
1784 return RREG32(CP_RB1_WPTR); 1821 return RREG32(mmCP_RB1_WPTR);
1785 else if (ring == &adev->gfx.compute_ring[1]) 1822 else if (ring == &adev->gfx.compute_ring[1])
1786 return RREG32(CP_RB2_WPTR); 1823 return RREG32(mmCP_RB2_WPTR);
1787 else 1824 else
1788 BUG(); 1825 BUG();
1789} 1826}
@@ -1792,8 +1829,8 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1792{ 1829{
1793 struct amdgpu_device *adev = ring->adev; 1830 struct amdgpu_device *adev = ring->adev;
1794 1831
1795 WREG32(CP_RB0_WPTR, ring->wptr); 1832 WREG32(mmCP_RB0_WPTR, ring->wptr);
1796 (void)RREG32(CP_RB0_WPTR); 1833 (void)RREG32(mmCP_RB0_WPTR);
1797} 1834}
1798 1835
1799static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 1836static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
@@ -1801,11 +1838,11 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1801 struct amdgpu_device *adev = ring->adev; 1838 struct amdgpu_device *adev = ring->adev;
1802 1839
1803 if (ring == &adev->gfx.compute_ring[0]) { 1840 if (ring == &adev->gfx.compute_ring[0]) {
1804 WREG32(CP_RB1_WPTR, ring->wptr); 1841 WREG32(mmCP_RB1_WPTR, ring->wptr);
1805 (void)RREG32(CP_RB1_WPTR); 1842 (void)RREG32(mmCP_RB1_WPTR);
1806 } else if (ring == &adev->gfx.compute_ring[1]) { 1843 } else if (ring == &adev->gfx.compute_ring[1]) {
1807 WREG32(CP_RB2_WPTR, ring->wptr); 1844 WREG32(mmCP_RB2_WPTR, ring->wptr);
1808 (void)RREG32(CP_RB2_WPTR); 1845 (void)RREG32(mmCP_RB2_WPTR);
1809 } else { 1846 } else {
1810 BUG(); 1847 BUG();
1811 } 1848 }
@@ -1817,7 +1854,7 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1817 struct amdgpu_ring *ring; 1854 struct amdgpu_ring *ring;
1818 u32 tmp; 1855 u32 tmp;
1819 u32 rb_bufsz; 1856 u32 rb_bufsz;
1820 int r; 1857 int i, r;
1821 u64 rptr_addr; 1858 u64 rptr_addr;
1822 1859
1823 /* ring1 - compute only */ 1860 /* ring1 - compute only */
@@ -1829,19 +1866,19 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1829#ifdef __BIG_ENDIAN 1866#ifdef __BIG_ENDIAN
1830 tmp |= BUF_SWAP_32BIT; 1867 tmp |= BUF_SWAP_32BIT;
1831#endif 1868#endif
1832 WREG32(CP_RB1_CNTL, tmp); 1869 WREG32(mmCP_RB1_CNTL, tmp);
1833 1870
1834 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 1871 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
1835 ring->wptr = 0; 1872 ring->wptr = 0;
1836 WREG32(CP_RB1_WPTR, ring->wptr); 1873 WREG32(mmCP_RB1_WPTR, ring->wptr);
1837 1874
1838 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1875 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1839 WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 1876 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1840 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1877 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1841 1878
1842 mdelay(1); 1879 mdelay(1);
1843 WREG32(CP_RB1_CNTL, tmp); 1880 WREG32(mmCP_RB1_CNTL, tmp);
1844 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 1881 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
1845 1882
1846 ring = &adev->gfx.compute_ring[1]; 1883 ring = &adev->gfx.compute_ring[1];
1847 rb_bufsz = order_base_2(ring->ring_size / 8); 1884 rb_bufsz = order_base_2(ring->ring_size / 8);
@@ -1849,32 +1886,27 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1849#ifdef __BIG_ENDIAN 1886#ifdef __BIG_ENDIAN
1850 tmp |= BUF_SWAP_32BIT; 1887 tmp |= BUF_SWAP_32BIT;
1851#endif 1888#endif
1852 WREG32(CP_RB2_CNTL, tmp); 1889 WREG32(mmCP_RB2_CNTL, tmp);
1853 1890
1854 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 1891 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
1855 ring->wptr = 0; 1892 ring->wptr = 0;
1856 WREG32(CP_RB2_WPTR, ring->wptr); 1893 WREG32(mmCP_RB2_WPTR, ring->wptr);
1857 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1894 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1858 WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 1895 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1859 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1896 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1860 1897
1861 mdelay(1); 1898 mdelay(1);
1862 WREG32(CP_RB2_CNTL, tmp); 1899 WREG32(mmCP_RB2_CNTL, tmp);
1863 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 1900 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
1864 1901
1865 adev->gfx.compute_ring[0].ready = true; 1902 adev->gfx.compute_ring[0].ready = false;
1866 adev->gfx.compute_ring[1].ready = true; 1903 adev->gfx.compute_ring[1].ready = false;
1867 1904
1868 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]); 1905 for (i = 0; i < 2; i++) {
1869 if (r) { 1906 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
1870 adev->gfx.compute_ring[0].ready = false; 1907 if (r)
1871 return r; 1908 return r;
1872 } 1909 adev->gfx.compute_ring[i].ready = true;
1873
1874 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1875 if (r) {
1876 adev->gfx.compute_ring[1].ready = false;
1877 return r;
1878 } 1910 }
1879 1911
1880 return 0; 1912 return 0;
@@ -1892,24 +1924,26 @@ static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1892 1924
1893static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1925static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1894 bool enable) 1926 bool enable)
1895{ 1927{
1896 u32 tmp = RREG32(CP_INT_CNTL_RING0); 1928 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
1897 u32 mask; 1929 u32 mask;
1898 int i; 1930 int i;
1899 1931
1900 if (enable) 1932 if (enable)
1901 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 1933 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
1934 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
1902 else 1935 else
1903 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 1936 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
1904 WREG32(CP_INT_CNTL_RING0, tmp); 1937 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
1938 WREG32(mmCP_INT_CNTL_RING0, tmp);
1905 1939
1906 if (!enable) { 1940 if (!enable) {
1907 /* read a gfx register */ 1941 /* read a gfx register */
1908 tmp = RREG32(DB_DEPTH_INFO); 1942 tmp = RREG32(mmDB_DEPTH_INFO);
1909 1943
1910 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 1944 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1911 for (i = 0; i < adev->usec_timeout; i++) { 1945 for (i = 0; i < adev->usec_timeout; i++) {
1912 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 1946 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1913 break; 1947 break;
1914 udelay(1); 1948 udelay(1);
1915 } 1949 }
@@ -1973,9 +2007,9 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1973 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2007 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1974 WRITE_DATA_DST_SEL(0))); 2008 WRITE_DATA_DST_SEL(0)));
1975 if (vm_id < 8) { 2009 if (vm_id < 8) {
1976 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2010 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1977 } else { 2011 } else {
1978 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2012 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1979 } 2013 }
1980 amdgpu_ring_write(ring, 0); 2014 amdgpu_ring_write(ring, 0);
1981 amdgpu_ring_write(ring, pd_addr >> 12); 2015 amdgpu_ring_write(ring, pd_addr >> 12);
@@ -1984,7 +2018,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1984 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2018 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1985 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2019 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1986 WRITE_DATA_DST_SEL(0))); 2020 WRITE_DATA_DST_SEL(0)));
1987 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 2021 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1988 amdgpu_ring_write(ring, 0); 2022 amdgpu_ring_write(ring, 0);
1989 amdgpu_ring_write(ring, 1 << vm_id); 2023 amdgpu_ring_write(ring, 1 << vm_id);
1990 2024
@@ -1992,7 +2026,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1992 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2026 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1993 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2027 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
1994 WAIT_REG_MEM_ENGINE(0))); /* me */ 2028 WAIT_REG_MEM_ENGINE(0))); /* me */
1995 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 2029 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1996 amdgpu_ring_write(ring, 0); 2030 amdgpu_ring_write(ring, 0);
1997 amdgpu_ring_write(ring, 0); /* ref */ 2031 amdgpu_ring_write(ring, 0); /* ref */
1998 amdgpu_ring_write(ring, 0); /* mask */ 2032 amdgpu_ring_write(ring, 0); /* mask */
@@ -2071,7 +2105,6 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2071 if (src_ptr) { 2105 if (src_ptr) {
2072 /* save restore block */ 2106 /* save restore block */
2073 if (adev->gfx.rlc.save_restore_obj == NULL) { 2107 if (adev->gfx.rlc.save_restore_obj == NULL) {
2074
2075 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 2108 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2076 AMDGPU_GEM_DOMAIN_VRAM, 2109 AMDGPU_GEM_DOMAIN_VRAM,
2077 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 2110 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
@@ -2166,20 +2199,12 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2166 2199
2167static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2200static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2168{ 2201{
2169 u32 tmp; 2202 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2170
2171 tmp = RREG32(RLC_LB_CNTL);
2172 if (enable)
2173 tmp |= LOAD_BALANCE_ENABLE;
2174 else
2175 tmp &= ~LOAD_BALANCE_ENABLE;
2176 WREG32(RLC_LB_CNTL, tmp);
2177 2203
2178 if (!enable) { 2204 if (!enable) {
2179 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2205 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2180 WREG32(SPI_LB_CU_MASK, 0x00ff); 2206 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2181 } 2207 }
2182
2183} 2208}
2184 2209
2185static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2210static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
@@ -2187,13 +2212,13 @@ static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2187 int i; 2212 int i;
2188 2213
2189 for (i = 0; i < adev->usec_timeout; i++) { 2214 for (i = 0; i < adev->usec_timeout; i++) {
2190 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) 2215 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2191 break; 2216 break;
2192 udelay(1); 2217 udelay(1);
2193 } 2218 }
2194 2219
2195 for (i = 0; i < adev->usec_timeout; i++) { 2220 for (i = 0; i < adev->usec_timeout; i++) {
2196 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) 2221 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2197 break; 2222 break;
2198 udelay(1); 2223 udelay(1);
2199 } 2224 }
@@ -2203,20 +2228,20 @@ static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2203{ 2228{
2204 u32 tmp; 2229 u32 tmp;
2205 2230
2206 tmp = RREG32(RLC_CNTL); 2231 tmp = RREG32(mmRLC_CNTL);
2207 if (tmp != rlc) 2232 if (tmp != rlc)
2208 WREG32(RLC_CNTL, rlc); 2233 WREG32(mmRLC_CNTL, rlc);
2209} 2234}
2210 2235
2211static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2236static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2212{ 2237{
2213 u32 data, orig; 2238 u32 data, orig;
2214 2239
2215 orig = data = RREG32(RLC_CNTL); 2240 orig = data = RREG32(mmRLC_CNTL);
2216 2241
2217 if (data & RLC_ENABLE) { 2242 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2218 data &= ~RLC_ENABLE; 2243 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2219 WREG32(RLC_CNTL, data); 2244 WREG32(mmRLC_CNTL, data);
2220 2245
2221 gfx_v6_0_wait_for_rlc_serdes(adev); 2246 gfx_v6_0_wait_for_rlc_serdes(adev);
2222 } 2247 }
@@ -2226,7 +2251,7 @@ static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2226 2251
2227static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2252static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2228{ 2253{
2229 WREG32(RLC_CNTL, 0); 2254 WREG32(mmRLC_CNTL, 0);
2230 2255
2231 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2256 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2232 gfx_v6_0_wait_for_rlc_serdes(adev); 2257 gfx_v6_0_wait_for_rlc_serdes(adev);
@@ -2234,7 +2259,7 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2234 2259
2235static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2260static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2236{ 2261{
2237 WREG32(RLC_CNTL, RLC_ENABLE); 2262 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2238 2263
2239 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2264 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2240 2265
@@ -2243,13 +2268,9 @@ static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2243 2268
2244static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2269static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2245{ 2270{
2246 u32 tmp = RREG32(GRBM_SOFT_RESET); 2271 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2247
2248 tmp |= SOFT_RESET_RLC;
2249 WREG32(GRBM_SOFT_RESET, tmp);
2250 udelay(50); 2272 udelay(50);
2251 tmp &= ~SOFT_RESET_RLC; 2273 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2252 WREG32(GRBM_SOFT_RESET, tmp);
2253 udelay(50); 2274 udelay(50);
2254} 2275}
2255 2276
@@ -2258,11 +2279,12 @@ static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2258 u32 tmp; 2279 u32 tmp;
2259 2280
2260 /* Enable LBPW only for DDR3 */ 2281 /* Enable LBPW only for DDR3 */
2261 tmp = RREG32(MC_SEQ_MISC0); 2282 tmp = RREG32(mmMC_SEQ_MISC0);
2262 if ((tmp & 0xF0000000) == 0xB0000000) 2283 if ((tmp & 0xF0000000) == 0xB0000000)
2263 return true; 2284 return true;
2264 return false; 2285 return false;
2265} 2286}
2287
2266static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2288static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2267{ 2289{
2268} 2290}
@@ -2283,15 +2305,15 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2283 gfx_v6_0_init_pg(adev); 2305 gfx_v6_0_init_pg(adev);
2284 gfx_v6_0_init_cg(adev); 2306 gfx_v6_0_init_cg(adev);
2285 2307
2286 WREG32(RLC_RL_BASE, 0); 2308 WREG32(mmRLC_RL_BASE, 0);
2287 WREG32(RLC_RL_SIZE, 0); 2309 WREG32(mmRLC_RL_SIZE, 0);
2288 WREG32(RLC_LB_CNTL, 0); 2310 WREG32(mmRLC_LB_CNTL, 0);
2289 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); 2311 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2290 WREG32(RLC_LB_CNTR_INIT, 0); 2312 WREG32(mmRLC_LB_CNTR_INIT, 0);
2291 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); 2313 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2292 2314
2293 WREG32(RLC_MC_CNTL, 0); 2315 WREG32(mmRLC_MC_CNTL, 0);
2294 WREG32(RLC_UCODE_CNTL, 0); 2316 WREG32(mmRLC_UCODE_CNTL, 0);
2295 2317
2296 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2318 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2297 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2319 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
@@ -2301,10 +2323,10 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2301 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2323 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2302 2324
2303 for (i = 0; i < fw_size; i++) { 2325 for (i = 0; i < fw_size; i++) {
2304 WREG32(RLC_UCODE_ADDR, i); 2326 WREG32(mmRLC_UCODE_ADDR, i);
2305 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2327 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2306 } 2328 }
2307 WREG32(RLC_UCODE_ADDR, 0); 2329 WREG32(mmRLC_UCODE_ADDR, 0);
2308 2330
2309 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2331 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2310 gfx_v6_0_rlc_start(adev); 2332 gfx_v6_0_rlc_start(adev);
@@ -2316,38 +2338,38 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2316{ 2338{
2317 u32 data, orig, tmp; 2339 u32 data, orig, tmp;
2318 2340
2319 orig = data = RREG32(RLC_CGCG_CGLS_CTRL); 2341 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2320 2342
2321 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2343 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2322 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2344 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2323 2345
2324 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); 2346 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2325 2347
2326 tmp = gfx_v6_0_halt_rlc(adev); 2348 tmp = gfx_v6_0_halt_rlc(adev);
2327 2349
2328 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2350 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2329 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2351 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2330 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); 2352 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2331 2353
2332 gfx_v6_0_wait_for_rlc_serdes(adev); 2354 gfx_v6_0_wait_for_rlc_serdes(adev);
2333 gfx_v6_0_update_rlc(adev, tmp); 2355 gfx_v6_0_update_rlc(adev, tmp);
2334 2356
2335 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); 2357 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2336 2358
2337 data |= CGCG_EN | CGLS_EN; 2359 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2338 } else { 2360 } else {
2339 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2361 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2340 2362
2341 RREG32(CB_CGTT_SCLK_CTRL); 2363 RREG32(mmCB_CGTT_SCLK_CTRL);
2342 RREG32(CB_CGTT_SCLK_CTRL); 2364 RREG32(mmCB_CGTT_SCLK_CTRL);
2343 RREG32(CB_CGTT_SCLK_CTRL); 2365 RREG32(mmCB_CGTT_SCLK_CTRL);
2344 RREG32(CB_CGTT_SCLK_CTRL); 2366 RREG32(mmCB_CGTT_SCLK_CTRL);
2345 2367
2346 data &= ~(CGCG_EN | CGLS_EN); 2368 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2347 } 2369 }
2348 2370
2349 if (orig != data) 2371 if (orig != data)
2350 WREG32(RLC_CGCG_CGLS_CTRL, data); 2372 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2351 2373
2352} 2374}
2353 2375
@@ -2357,51 +2379,51 @@ static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2357 u32 data, orig, tmp = 0; 2379 u32 data, orig, tmp = 0;
2358 2380
2359 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2381 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2360 orig = data = RREG32(CGTS_SM_CTRL_REG); 2382 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2361 data = 0x96940200; 2383 data = 0x96940200;
2362 if (orig != data) 2384 if (orig != data)
2363 WREG32(CGTS_SM_CTRL_REG, data); 2385 WREG32(mmCGTS_SM_CTRL_REG, data);
2364 2386
2365 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2366 orig = data = RREG32(CP_MEM_SLP_CNTL); 2388 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2367 data |= CP_MEM_LS_EN; 2389 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2368 if (orig != data) 2390 if (orig != data)
2369 WREG32(CP_MEM_SLP_CNTL, data); 2391 WREG32(mmCP_MEM_SLP_CNTL, data);
2370 } 2392 }
2371 2393
2372 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); 2394 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2373 data &= 0xffffffc0; 2395 data &= 0xffffffc0;
2374 if (orig != data) 2396 if (orig != data)
2375 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); 2397 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2376 2398
2377 tmp = gfx_v6_0_halt_rlc(adev); 2399 tmp = gfx_v6_0_halt_rlc(adev);
2378 2400
2379 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2401 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2380 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2402 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2381 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); 2403 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2382 2404
2383 gfx_v6_0_update_rlc(adev, tmp); 2405 gfx_v6_0_update_rlc(adev, tmp);
2384 } else { 2406 } else {
2385 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); 2407 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2386 data |= 0x00000003; 2408 data |= 0x00000003;
2387 if (orig != data) 2409 if (orig != data)
2388 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); 2410 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2389 2411
2390 data = RREG32(CP_MEM_SLP_CNTL); 2412 data = RREG32(mmCP_MEM_SLP_CNTL);
2391 if (data & CP_MEM_LS_EN) { 2413 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2392 data &= ~CP_MEM_LS_EN; 2414 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2393 WREG32(CP_MEM_SLP_CNTL, data); 2415 WREG32(mmCP_MEM_SLP_CNTL, data);
2394 } 2416 }
2395 orig = data = RREG32(CGTS_SM_CTRL_REG); 2417 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2396 data |= LS_OVERRIDE | OVERRIDE; 2418 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2397 if (orig != data) 2419 if (orig != data)
2398 WREG32(CGTS_SM_CTRL_REG, data); 2420 WREG32(mmCGTS_SM_CTRL_REG, data);
2399 2421
2400 tmp = gfx_v6_0_halt_rlc(adev); 2422 tmp = gfx_v6_0_halt_rlc(adev);
2401 2423
2402 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2424 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2403 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2425 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2404 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); 2426 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2405 2427
2406 gfx_v6_0_update_rlc(adev, tmp); 2428 gfx_v6_0_update_rlc(adev, tmp);
2407 } 2429 }
@@ -2421,6 +2443,7 @@ static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2421 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2443 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2422} 2444}
2423*/ 2445*/
2446
2424static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2447static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2425 bool enable) 2448 bool enable)
2426{ 2449{
@@ -2435,13 +2458,13 @@ static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2435{ 2458{
2436 u32 data, orig; 2459 u32 data, orig;
2437 2460
2438 orig = data = RREG32(RLC_PG_CNTL); 2461 orig = data = RREG32(mmRLC_PG_CNTL);
2439 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2462 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2440 data &= ~0x8000; 2463 data &= ~0x8000;
2441 else 2464 else
2442 data |= 0x8000; 2465 data |= 0x8000;
2443 if (orig != data) 2466 if (orig != data)
2444 WREG32(RLC_PG_CNTL, data); 2467 WREG32(mmRLC_PG_CNTL, data);
2445} 2468}
2446 2469
2447static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2470static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
@@ -2518,26 +2541,13 @@ static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2518static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2541static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2519 bool enable) 2542 bool enable)
2520{ 2543{
2521
2522 u32 tmp;
2523
2524 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2544 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2525 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); 2545 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2526 WREG32(RLC_TTOP_D, tmp); 2546 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2527 2547 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2528 tmp = RREG32(RLC_PG_CNTL);
2529 tmp |= GFX_PG_ENABLE;
2530 WREG32(RLC_PG_CNTL, tmp);
2531
2532 tmp = RREG32(RLC_AUTO_PG_CTRL);
2533 tmp |= AUTO_PG_EN;
2534 WREG32(RLC_AUTO_PG_CTRL, tmp);
2535 } else { 2548 } else {
2536 tmp = RREG32(RLC_AUTO_PG_CTRL); 2549 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2537 tmp &= ~AUTO_PG_EN; 2550 (void)RREG32(mmDB_RENDER_CONTROL);
2538 WREG32(RLC_AUTO_PG_CTRL, tmp);
2539
2540 tmp = RREG32(DB_RENDER_CONTROL);
2541 } 2551 }
2542} 2552}
2543 2553
@@ -2550,8 +2560,8 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2550 2560
2551 mutex_lock(&adev->grbm_idx_mutex); 2561 mutex_lock(&adev->grbm_idx_mutex);
2552 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff); 2562 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2553 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 2563 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
2554 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); 2564 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
2555 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2565 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2556 mutex_unlock(&adev->grbm_idx_mutex); 2566 mutex_unlock(&adev->grbm_idx_mutex);
2557 2567
@@ -2594,12 +2604,8 @@ static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2594 } 2604 }
2595 } 2605 }
2596 2606
2597 WREG32(RLC_PG_AO_CU_MASK, tmp); 2607 WREG32(mmRLC_PG_AO_CU_MASK, tmp);
2598 2608 WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number);
2599 tmp = RREG32(RLC_MAX_PG_CU);
2600 tmp &= ~MAX_PU_CU_MASK;
2601 tmp |= MAX_PU_CU(active_cu_number);
2602 WREG32(RLC_MAX_PG_CU, tmp);
2603} 2609}
2604 2610
2605static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2611static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
@@ -2607,13 +2613,13 @@ static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2607{ 2613{
2608 u32 data, orig; 2614 u32 data, orig;
2609 2615
2610 orig = data = RREG32(RLC_PG_CNTL); 2616 orig = data = RREG32(mmRLC_PG_CNTL);
2611 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2617 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2612 data |= STATIC_PER_CU_PG_ENABLE; 2618 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2613 else 2619 else
2614 data &= ~STATIC_PER_CU_PG_ENABLE; 2620 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2615 if (orig != data) 2621 if (orig != data)
2616 WREG32(RLC_PG_CNTL, data); 2622 WREG32(mmRLC_PG_CNTL, data);
2617} 2623}
2618 2624
2619static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2625static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
@@ -2621,33 +2627,28 @@ static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2621{ 2627{
2622 u32 data, orig; 2628 u32 data, orig;
2623 2629
2624 orig = data = RREG32(RLC_PG_CNTL); 2630 orig = data = RREG32(mmRLC_PG_CNTL);
2625 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2631 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2626 data |= DYN_PER_CU_PG_ENABLE; 2632 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2627 else 2633 else
2628 data &= ~DYN_PER_CU_PG_ENABLE; 2634 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2629 if (orig != data) 2635 if (orig != data)
2630 WREG32(RLC_PG_CNTL, data); 2636 WREG32(mmRLC_PG_CNTL, data);
2631} 2637}
2632 2638
2633static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2639static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2634{ 2640{
2635 u32 tmp; 2641 u32 tmp;
2636 2642
2637 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2643 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2638 2644 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2639 tmp = RREG32(RLC_PG_CNTL); 2645 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2640 tmp |= GFX_PG_SRC;
2641 WREG32(RLC_PG_CNTL, tmp);
2642
2643 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2644 2646
2645 tmp = RREG32(RLC_AUTO_PG_CTRL); 2647 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2646 2648 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2647 tmp &= ~GRBM_REG_SGIT_MASK; 2649 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2648 tmp |= GRBM_REG_SGIT(0x700); 2650 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2649 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK; 2651 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2650 WREG32(RLC_AUTO_PG_CTRL, tmp);
2651} 2652}
2652 2653
2653static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2654static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
@@ -2703,7 +2704,6 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2703 2704
2704 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2705 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2705 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2706 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2706
2707 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2707 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2708 buffer[count++] = cpu_to_le32(0x80000000); 2708 buffer[count++] = cpu_to_le32(0x80000000);
2709 buffer[count++] = cpu_to_le32(0x80000000); 2709 buffer[count++] = cpu_to_le32(0x80000000);
@@ -2723,7 +2723,7 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2723 } 2723 }
2724 2724
2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2726 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2726 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2727 2727
2728 switch (adev->asic_type) { 2728 switch (adev->asic_type) {
2729 case CHIP_TAHITI: 2729 case CHIP_TAHITI:
@@ -2766,16 +2766,16 @@ static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2766 gfx_v6_0_enable_cp_pg(adev, true); 2766 gfx_v6_0_enable_cp_pg(adev, true);
2767 gfx_v6_0_enable_gds_pg(adev, true); 2767 gfx_v6_0_enable_gds_pg(adev, true);
2768 } else { 2768 } else {
2769 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2769 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2770 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2770 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2771 2771
2772 } 2772 }
2773 gfx_v6_0_init_ao_cu_mask(adev); 2773 gfx_v6_0_init_ao_cu_mask(adev);
2774 gfx_v6_0_update_gfx_pg(adev, true); 2774 gfx_v6_0_update_gfx_pg(adev, true);
2775 } else { 2775 } else {
2776 2776
2777 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2777 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2778 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2778 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2779 } 2779 }
2780} 2780}
2781 2781
@@ -2800,23 +2800,61 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2800 uint64_t clock; 2800 uint64_t clock;
2801 2801
2802 mutex_lock(&adev->gfx.gpu_clock_mutex); 2802 mutex_lock(&adev->gfx.gpu_clock_mutex);
2803 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2803 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2804 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 2804 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2805 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2805 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2806 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2806 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2807 return clock; 2807 return clock;
2808} 2808}
2809 2809
2810static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2810static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2811{ 2811{
2812 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2813 gfx_v6_0_ring_emit_vgt_flush(ring);
2812 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2814 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2813 amdgpu_ring_write(ring, 0x80000000); 2815 amdgpu_ring_write(ring, 0x80000000);
2814 amdgpu_ring_write(ring, 0); 2816 amdgpu_ring_write(ring, 0);
2815} 2817}
2816 2818
2819
2820static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2821{
2822 WREG32(mmSQ_IND_INDEX,
2823 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2824 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2825 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2826 (SQ_IND_INDEX__FORCE_READ_MASK));
2827 return RREG32(mmSQ_IND_DATA);
2828}
2829
2830static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2831{
2832 /* type 0 wave data */
2833 dst[(*no_fields)++] = 0;
2834 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2835 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2836 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2837 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2838 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2839 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2840 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2841 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2842 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2843 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2844 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2845 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2846 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
2847 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
2848 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
2849 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
2850 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2851 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2852}
2853
2817static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 2854static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2818 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 2855 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2819 .select_se_sh = &gfx_v6_0_select_se_sh, 2856 .select_se_sh = &gfx_v6_0_select_se_sh,
2857 .read_wave_data = &gfx_v6_0_read_wave_data,
2820}; 2858};
2821 2859
2822static int gfx_v6_0_early_init(void *handle) 2860static int gfx_v6_0_early_init(void *handle)
@@ -2967,7 +3005,7 @@ static bool gfx_v6_0_is_idle(void *handle)
2967{ 3005{
2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969 3007
2970 if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3008 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2971 return false; 3009 return false;
2972 else 3010 else
2973 return true; 3011 return true;
@@ -2998,14 +3036,14 @@ static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2998 3036
2999 switch (state) { 3037 switch (state) {
3000 case AMDGPU_IRQ_STATE_DISABLE: 3038 case AMDGPU_IRQ_STATE_DISABLE:
3001 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3039 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3002 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3040 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3003 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3041 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3004 break; 3042 break;
3005 case AMDGPU_IRQ_STATE_ENABLE: 3043 case AMDGPU_IRQ_STATE_ENABLE:
3006 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3044 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3007 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3045 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3008 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3046 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3009 break; 3047 break;
3010 default: 3048 default:
3011 break; 3049 break;
@@ -3020,27 +3058,27 @@ static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3020 switch (state){ 3058 switch (state){
3021 case AMDGPU_IRQ_STATE_DISABLE: 3059 case AMDGPU_IRQ_STATE_DISABLE:
3022 if (ring == 0) { 3060 if (ring == 0) {
3023 cp_int_cntl = RREG32(CP_INT_CNTL_RING1); 3061 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3024 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3062 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3025 WREG32(CP_INT_CNTL_RING1, cp_int_cntl); 3063 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3026 break; 3064 break;
3027 } else { 3065 } else {
3028 cp_int_cntl = RREG32(CP_INT_CNTL_RING2); 3066 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3029 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3067 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3030 WREG32(CP_INT_CNTL_RING2, cp_int_cntl); 3068 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3031 break; 3069 break;
3032 3070
3033 } 3071 }
3034 case AMDGPU_IRQ_STATE_ENABLE: 3072 case AMDGPU_IRQ_STATE_ENABLE:
3035 if (ring == 0) { 3073 if (ring == 0) {
3036 cp_int_cntl = RREG32(CP_INT_CNTL_RING1); 3074 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3037 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3075 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3038 WREG32(CP_INT_CNTL_RING1, cp_int_cntl); 3076 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3039 break; 3077 break;
3040 } else { 3078 } else {
3041 cp_int_cntl = RREG32(CP_INT_CNTL_RING2); 3079 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3042 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; 3080 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3043 WREG32(CP_INT_CNTL_RING2, cp_int_cntl); 3081 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3044 break; 3082 break;
3045 3083
3046 } 3084 }
@@ -3061,14 +3099,14 @@ static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3061 3099
3062 switch (state) { 3100 switch (state) {
3063 case AMDGPU_IRQ_STATE_DISABLE: 3101 case AMDGPU_IRQ_STATE_DISABLE:
3064 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3102 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3065 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3103 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3066 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3104 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3067 break; 3105 break;
3068 case AMDGPU_IRQ_STATE_ENABLE: 3106 case AMDGPU_IRQ_STATE_ENABLE:
3069 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3107 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3070 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3108 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3071 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3109 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3072 break; 3110 break;
3073 default: 3111 default:
3074 break; 3112 break;
@@ -3086,14 +3124,14 @@ static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3086 3124
3087 switch (state) { 3125 switch (state) {
3088 case AMDGPU_IRQ_STATE_DISABLE: 3126 case AMDGPU_IRQ_STATE_DISABLE:
3089 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3127 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3090 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3128 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3091 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3129 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3092 break; 3130 break;
3093 case AMDGPU_IRQ_STATE_ENABLE: 3131 case AMDGPU_IRQ_STATE_ENABLE:
3094 cp_int_cntl = RREG32(CP_INT_CNTL_RING0); 3132 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3095 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3133 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3096 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3134 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3097 break; 3135 break;
3098 default: 3136 default:
3099 break; 3137 break;
@@ -3133,7 +3171,7 @@ static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3133 break; 3171 break;
3134 case 1: 3172 case 1:
3135 case 2: 3173 case 2:
3136 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]); 3174 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3137 break; 3175 break;
3138 default: 3176 default:
3139 break; 3177 break;
@@ -3236,7 +3274,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3236 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3274 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3237 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3275 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3238 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3276 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3239 3, /* gfx_v6_ring_emit_cntxcntl */ 3277 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3240 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3278 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3241 .emit_ib = gfx_v6_0_ring_emit_ib, 3279 .emit_ib = gfx_v6_0_ring_emit_ib,
3242 .emit_fence = gfx_v6_0_ring_emit_fence, 3280 .emit_fence = gfx_v6_0_ring_emit_fence,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 5b631fd1a879..1a745cf93f47 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2105 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2105 amdgpu_ring_write(ring, 0x20); /* poll interval */
2106} 2106}
2107 2107
2108static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2109{
2110 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2111 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2112 EVENT_INDEX(4));
2113
2114 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2115 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2116 EVENT_INDEX(0));
2117}
2118
2119
2108/** 2120/**
2109 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 2121 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2110 * 2122 *
@@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2260 2272
2261 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2273 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2262 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2274 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2275 gfx_v7_0_ring_emit_vgt_flush(ring);
2263 /* set load_global_config & load_global_uconfig */ 2276 /* set load_global_config & load_global_uconfig */
2264 dw2 |= 0x8001; 2277 dw2 |= 0x8001;
2265 /* set load_cs_sh_regs */ 2278 /* set load_cs_sh_regs */
@@ -4359,7 +4372,11 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4359 4372
4360static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4373static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4361{ 4374{
4362 WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); 4375 WREG32(mmSQ_IND_INDEX,
4376 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4377 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4378 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4379 (SQ_IND_INDEX__FORCE_READ_MASK));
4363 return RREG32(mmSQ_IND_DATA); 4380 return RREG32(mmSQ_IND_DATA);
4364} 4381}
4365 4382
@@ -5149,7 +5166,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5149 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5166 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5150 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5167 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5151 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5168 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5152 3, /* gfx_v7_ring_emit_cntxcntl */ 5169 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5153 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5170 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5154 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5171 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5155 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5172 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 23f1bc94ad3e..a3684891c6e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3904,7 +3904,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3904 int list_size; 3904 int list_size;
3905 unsigned int *register_list_format = 3905 unsigned int *register_list_format =
3906 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 3906 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3907 if (register_list_format == NULL) 3907 if (!register_list_format)
3908 return -ENOMEM; 3908 return -ENOMEM;
3909 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 3909 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3910 adev->gfx.rlc.reg_list_format_size_bytes); 3910 adev->gfx.rlc.reg_list_format_size_bytes);
@@ -5442,7 +5442,11 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5442 5442
5443static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 5443static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5444{ 5444{
5445 WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); 5445 WREG32(mmSQ_IND_INDEX,
5446 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5447 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5448 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5449 (SQ_IND_INDEX__FORCE_READ_MASK));
5446 return RREG32(mmSQ_IND_DATA); 5450 return RREG32(mmSQ_IND_DATA);
5447} 5451}
5448 5452
@@ -6182,6 +6186,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6182 amdgpu_ring_write(ring, 0x20); /* poll interval */ 6186 amdgpu_ring_write(ring, 0x20); /* poll interval */
6183} 6187}
6184 6188
6189static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6190{
6191 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6192 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6193 EVENT_INDEX(4));
6194
6195 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6196 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6197 EVENT_INDEX(0));
6198}
6199
6200
6185static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 6201static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
6186{ 6202{
6187 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6203 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -6367,6 +6383,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6367 6383
6368 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6384 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6369 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6385 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6386 gfx_v8_0_ring_emit_vgt_flush(ring);
6370 /* set load_global_config & load_global_uconfig */ 6387 /* set load_global_config & load_global_uconfig */
6371 dw2 |= 0x8001; 6388 dw2 |= 0x8001;
6372 /* set load_cs_sh_regs */ 6389 /* set load_cs_sh_regs */
@@ -6570,7 +6587,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6570 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 6587 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6571 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ 6588 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
6572 2 + /* gfx_v8_ring_emit_sb */ 6589 2 + /* gfx_v8_ring_emit_sb */
6573 3, /* gfx_v8_ring_emit_cntxcntl */ 6590 3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */
6574 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ 6591 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6575 .emit_ib = gfx_v8_0_ring_emit_ib_gfx, 6592 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6576 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 6593 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 1940d36bc304..64d3c1e6014c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1,4 +1,3 @@
1
2/* 1/*
3 * Copyright 2014 Advanced Micro Devices, Inc. 2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * 3 *
@@ -26,7 +25,16 @@
26#include "amdgpu.h" 25#include "amdgpu.h"
27#include "gmc_v6_0.h" 26#include "gmc_v6_0.h"
28#include "amdgpu_ucode.h" 27#include "amdgpu_ucode.h"
29#include "si/sid.h" 28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
30 38
31static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); 39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
32static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -37,6 +45,16 @@ MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
37MODULE_FIRMWARE("radeon/verde_mc.bin"); 45MODULE_FIRMWARE("radeon/verde_mc.bin");
38MODULE_FIRMWARE("radeon/oland_mc.bin"); 46MODULE_FIRMWARE("radeon/oland_mc.bin");
39 47
48#define MC_SEQ_MISC0__MT__MASK 0xf0000000
49#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
50#define MC_SEQ_MISC0__MT__DDR2 0x20000000
51#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
52#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
53#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
54#define MC_SEQ_MISC0__MT__HBM 0x60000000
55#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
56
57
40static const u32 crtc_offsets[6] = 58static const u32 crtc_offsets[6] =
41{ 59{
42 SI_CRTC0_REGISTER_OFFSET, 60 SI_CRTC0_REGISTER_OFFSET,
@@ -57,14 +75,14 @@ static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
57 75
58 gmc_v6_0_wait_for_idle((void *)adev); 76 gmc_v6_0_wait_for_idle((void *)adev);
59 77
60 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 78 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
61 if (REG_GET_FIELD(blackout, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE) != 1) { 79 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
62 /* Block CPU access */ 80 /* Block CPU access */
63 WREG32(BIF_FB_EN, 0); 81 WREG32(mmBIF_FB_EN, 0);
64 /* blackout the MC */ 82 /* blackout the MC */
65 blackout = REG_SET_FIELD(blackout, 83 blackout = REG_SET_FIELD(blackout,
66 mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); 84 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
67 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 85 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
68 } 86 }
69 /* wait for the MC to settle */ 87 /* wait for the MC to settle */
70 udelay(100); 88 udelay(100);
@@ -77,13 +95,13 @@ static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
77 u32 tmp; 95 u32 tmp;
78 96
79 /* unblackout the MC */ 97 /* unblackout the MC */
80 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); 98 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
81 tmp = REG_SET_FIELD(tmp, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); 99 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
82 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); 100 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
83 /* allow CPU access */ 101 /* allow CPU access */
84 tmp = REG_SET_FIELD(0, mmBIF_FB_EN, xxFB_READ_EN, 1); 102 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
85 tmp = REG_SET_FIELD(tmp, mmBIF_FB_EN, xxFB_WRITE_EN, 1); 103 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
86 WREG32(BIF_FB_EN, tmp); 104 WREG32(mmBIF_FB_EN, tmp);
87 105
88 if (adev->mode_info.num_crtc) 106 if (adev->mode_info.num_crtc)
89 amdgpu_display_resume_mc_access(adev, save); 107 amdgpu_display_resume_mc_access(adev, save);
@@ -158,37 +176,37 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
158 new_fw_data = (const __le32 *) 176 new_fw_data = (const __le32 *)
159 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 177 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
160 178
161 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 179 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
162 180
163 if (running == 0) { 181 if (running == 0) {
164 182
165 /* reset the engine and set to writable */ 183 /* reset the engine and set to writable */
166 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 184 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
167 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
168 186
169 /* load mc io regs */ 187 /* load mc io regs */
170 for (i = 0; i < regs_size; i++) { 188 for (i = 0; i < regs_size; i++) {
171 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 189 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
172 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 190 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
173 } 191 }
174 /* load the MC ucode */ 192 /* load the MC ucode */
175 for (i = 0; i < ucode_size; i++) { 193 for (i = 0; i < ucode_size; i++) {
176 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 194 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
177 } 195 }
178 196
179 /* put the engine back into the active state */ 197 /* put the engine back into the active state */
180 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
181 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
182 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
183 201
184 /* wait for training to complete */ 202 /* wait for training to complete */
185 for (i = 0; i < adev->usec_timeout; i++) { 203 for (i = 0; i < adev->usec_timeout; i++) {
186 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) 204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
187 break; 205 break;
188 udelay(1); 206 udelay(1);
189 } 207 }
190 for (i = 0; i < adev->usec_timeout; i++) { 208 for (i = 0; i < adev->usec_timeout; i++) {
191 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) 209 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
192 break; 210 break;
193 udelay(1); 211 udelay(1);
194 } 212 }
@@ -225,7 +243,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
225 WREG32((0xb08 + j), 0x00000000); 243 WREG32((0xb08 + j), 0x00000000);
226 WREG32((0xb09 + j), 0x00000000); 244 WREG32((0xb09 + j), 0x00000000);
227 } 245 }
228 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 246 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
229 247
230 gmc_v6_0_mc_stop(adev, &save); 248 gmc_v6_0_mc_stop(adev, &save);
231 249
@@ -233,24 +251,24 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
233 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 251 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
234 } 252 }
235 253
236 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 254 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
237 /* Update configuration */ 255 /* Update configuration */
238 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 256 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
239 adev->mc.vram_start >> 12); 257 adev->mc.vram_start >> 12);
240 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 258 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
241 adev->mc.vram_end >> 12); 259 adev->mc.vram_end >> 12);
242 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 260 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
243 adev->vram_scratch.gpu_addr >> 12); 261 adev->vram_scratch.gpu_addr >> 12);
244 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 262 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
245 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 263 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
246 WREG32(MC_VM_FB_LOCATION, tmp); 264 WREG32(mmMC_VM_FB_LOCATION, tmp);
247 /* XXX double check these! */ 265 /* XXX double check these! */
248 WREG32(HDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 266 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
249 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 267 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
250 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 268 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
251 WREG32(MC_VM_AGP_BASE, 0); 269 WREG32(mmMC_VM_AGP_BASE, 0);
252 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 270 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
253 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 271 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
254 272
255 if (gmc_v6_0_wait_for_idle((void *)adev)) { 273 if (gmc_v6_0_wait_for_idle((void *)adev)) {
256 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 274 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
@@ -265,16 +283,16 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
265 u32 tmp; 283 u32 tmp;
266 int chansize, numchan; 284 int chansize, numchan;
267 285
268 tmp = RREG32(MC_ARB_RAMCFG); 286 tmp = RREG32(mmMC_ARB_RAMCFG);
269 if (tmp & CHANSIZE_OVERRIDE) { 287 if (tmp & (1 << 11)) {
270 chansize = 16; 288 chansize = 16;
271 } else if (tmp & CHANSIZE_MASK) { 289 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
272 chansize = 64; 290 chansize = 64;
273 } else { 291 } else {
274 chansize = 32; 292 chansize = 32;
275 } 293 }
276 tmp = RREG32(MC_SHARED_CHMAP); 294 tmp = RREG32(mmMC_SHARED_CHMAP);
277 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 295 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
278 case 0: 296 case 0:
279 default: 297 default:
280 numchan = 1; 298 numchan = 1;
@@ -309,8 +327,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
309 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 327 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
310 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 328 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
311 /* size in MB on si */ 329 /* size in MB on si */
312 adev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 330 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
313 adev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 331 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
314 adev->mc.visible_vram_size = adev->mc.aper_size; 332 adev->mc.visible_vram_size = adev->mc.aper_size;
315 333
316 /* unless the user had overridden it, set the gart 334 /* unless the user had overridden it, set the gart
@@ -329,9 +347,9 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
329static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 347static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
330 uint32_t vmid) 348 uint32_t vmid)
331{ 349{
332 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); 350 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
333 351
334 WREG32(VM_INVALIDATE_REQUEST, 1 << vmid); 352 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
335} 353}
336 354
337static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, 355static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
@@ -355,20 +373,20 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
355{ 373{
356 u32 tmp; 374 u32 tmp;
357 375
358 tmp = RREG32(VM_CONTEXT1_CNTL); 376 tmp = RREG32(mmVM_CONTEXT1_CNTL);
359 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 377 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
360 xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 378 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
361 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 379 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
362 xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 380 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
363 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 381 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
364 xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 382 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
365 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 383 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
366 xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 384 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
367 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 385 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
368 xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT, value); 386 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
369 tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, 387 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
370 xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 388 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
371 WREG32(VM_CONTEXT1_CNTL, tmp); 389 WREG32(mmVM_CONTEXT1_CNTL, tmp);
372} 390}
373 391
374static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 392static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
@@ -383,33 +401,39 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
383 if (r) 401 if (r)
384 return r; 402 return r;
385 /* Setup TLB control */ 403 /* Setup TLB control */
386 WREG32(MC_VM_MX_L1_TLB_CNTL, 404 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
387 (0xA << 7) | 405 (0xA << 7) |
388 ENABLE_L1_TLB | 406 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
389 ENABLE_L1_FRAGMENT_PROCESSING | 407 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
390 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 408 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
391 ENABLE_ADVANCED_DRIVER_MODEL | 409 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
392 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 410 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
393 /* Setup L2 cache */ 411 /* Setup L2 cache */
394 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 412 WREG32(mmVM_L2_CNTL,
395 ENABLE_L2_FRAGMENT_PROCESSING | 413 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
396 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 414 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
397 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 415 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
398 EFFECTIVE_L2_QUEUE_SIZE(7) | 416 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
399 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 417 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
400 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 418 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
401 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 419 WREG32(mmVM_L2_CNTL2,
402 BANK_SELECT(4) | 420 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
403 L2_CACHE_BIGK_FRAGMENT_SIZE(4)); 421 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
422 WREG32(mmVM_L2_CNTL3,
423 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
424 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
425 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
404 /* setup context0 */ 426 /* setup context0 */
405 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 427 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
406 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 428 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
407 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 429 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
408 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 430 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
409 (u32)(adev->dummy_page.addr >> 12)); 431 (u32)(adev->dummy_page.addr >> 12));
410 WREG32(VM_CONTEXT0_CNTL2, 0); 432 WREG32(mmVM_CONTEXT0_CNTL2, 0);
411 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 433 WREG32(mmVM_CONTEXT0_CNTL,
412 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); 434 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
435 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
436 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
413 437
414 WREG32(0x575, 0); 438 WREG32(0x575, 0);
415 WREG32(0x576, 0); 439 WREG32(0x576, 0);
@@ -417,39 +441,41 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
417 441
418 /* empty context1-15 */ 442 /* empty context1-15 */
419 /* set vm size, must be a multiple of 4 */ 443 /* set vm size, must be a multiple of 4 */
420 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 444 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
421 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 445 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
422 /* Assign the pt base to something valid for now; the pts used for 446 /* Assign the pt base to something valid for now; the pts used for
423 * the VMs are determined by the application and setup and assigned 447 * the VMs are determined by the application and setup and assigned
424 * on the fly in the vm part of radeon_gart.c 448 * on the fly in the vm part of radeon_gart.c
425 */ 449 */
426 for (i = 1; i < 16; i++) { 450 for (i = 1; i < 16; i++) {
427 if (i < 8) 451 if (i < 8)
428 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 452 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
429 adev->gart.table_addr >> 12); 453 adev->gart.table_addr >> 12);
430 else 454 else
431 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 455 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
432 adev->gart.table_addr >> 12); 456 adev->gart.table_addr >> 12);
433 } 457 }
434 458
435 /* enable context1-15 */ 459 /* enable context1-15 */
436 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 460 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
437 (u32)(adev->dummy_page.addr >> 12)); 461 (u32)(adev->dummy_page.addr >> 12));
438 WREG32(VM_CONTEXT1_CNTL2, 4); 462 WREG32(mmVM_CONTEXT1_CNTL2, 4);
439 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 463 WREG32(mmVM_CONTEXT1_CNTL,
440 PAGE_TABLE_BLOCK_SIZE(amdgpu_vm_block_size - 9) | 464 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
441 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 465 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
442 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 466 ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) |
443 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 467 VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
444 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 468 VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
445 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 469 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
446 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 470 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
447 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 471 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
448 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 472 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
449 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 473 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
450 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
451 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
452 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 476 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
477 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
453 479
454 gmc_v6_0_gart_flush_gpu_tlb(adev, 0); 480 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
455 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 481 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
@@ -488,19 +514,22 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
488 }*/ 514 }*/
489 515
490 /* Disable all tables */ 516 /* Disable all tables */
491 WREG32(VM_CONTEXT0_CNTL, 0); 517 WREG32(mmVM_CONTEXT0_CNTL, 0);
492 WREG32(VM_CONTEXT1_CNTL, 0); 518 WREG32(mmVM_CONTEXT1_CNTL, 0);
493 /* Setup TLB control */ 519 /* Setup TLB control */
494 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | 520 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
495 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 521 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
522 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
496 /* Setup L2 cache */ 523 /* Setup L2 cache */
497 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 524 WREG32(mmVM_L2_CNTL,
498 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 525 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
499 EFFECTIVE_L2_QUEUE_SIZE(7) | 526 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
500 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 527 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
501 WREG32(VM_L2_CNTL2, 0); 528 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
502 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 529 WREG32(mmVM_L2_CNTL2, 0);
503 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 530 WREG32(mmVM_L2_CNTL3,
531 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
532 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
504 amdgpu_gart_table_vram_unpin(adev); 533 amdgpu_gart_table_vram_unpin(adev);
505} 534}
506 535
@@ -523,7 +552,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
523 552
524 /* base offset of vram pages */ 553 /* base offset of vram pages */
525 if (adev->flags & AMD_IS_APU) { 554 if (adev->flags & AMD_IS_APU) {
526 u64 tmp = RREG32(MC_VM_FB_OFFSET); 555 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
527 tmp <<= 22; 556 tmp <<= 22;
528 adev->vm_manager.vram_base_offset = tmp; 557 adev->vm_manager.vram_base_offset = tmp;
529 } else 558 } else
@@ -540,19 +569,19 @@ static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
540 u32 status, u32 addr, u32 mc_client) 569 u32 status, u32 addr, u32 mc_client)
541{ 570{
542 u32 mc_id; 571 u32 mc_id;
543 u32 vmid = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, xxVMID); 572 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
544 u32 protections = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, 573 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
545 xxPROTECTIONS); 574 PROTECTIONS);
546 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 575 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
547 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 576 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
548 577
549 mc_id = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, 578 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
550 xxMEMORY_CLIENT_ID); 579 MEMORY_CLIENT_ID);
551 580
552 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 581 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
553 protections, vmid, addr, 582 protections, vmid, addr,
554 REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, 583 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
555 xxMEMORY_CLIENT_RW) ? 584 MEMORY_CLIENT_RW) ?
556 "write" : "read", block, mc_client, mc_id); 585 "write" : "read", block, mc_client, mc_id);
557} 586}
558 587
@@ -655,7 +684,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
655{ 684{
656 u32 orig, data; 685 u32 orig, data;
657 686
658 orig = data = RREG32(HDP_HOST_PATH_CNTL); 687 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
659 688
660 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 689 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
661 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 690 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
@@ -663,7 +692,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
663 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 692 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
664 693
665 if (orig != data) 694 if (orig != data)
666 WREG32(HDP_HOST_PATH_CNTL, data); 695 WREG32(mmHDP_HOST_PATH_CNTL, data);
667} 696}
668 697
669static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 698static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
@@ -671,7 +700,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
671{ 700{
672 u32 orig, data; 701 u32 orig, data;
673 702
674 orig = data = RREG32(HDP_MEM_POWER_LS); 703 orig = data = RREG32(mmHDP_MEM_POWER_LS);
675 704
676 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 705 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
677 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 706 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
@@ -679,7 +708,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
679 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 708 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
680 709
681 if (orig != data) 710 if (orig != data)
682 WREG32(HDP_MEM_POWER_LS, data); 711 WREG32(mmHDP_MEM_POWER_LS, data);
683} 712}
684*/ 713*/
685 714
@@ -713,7 +742,7 @@ static int gmc_v6_0_early_init(void *handle)
713 if (adev->flags & AMD_IS_APU) { 742 if (adev->flags & AMD_IS_APU) {
714 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 743 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
715 } else { 744 } else {
716 u32 tmp = RREG32(MC_SEQ_MISC0); 745 u32 tmp = RREG32(mmMC_SEQ_MISC0);
717 tmp &= MC_SEQ_MISC0__MT__MASK; 746 tmp &= MC_SEQ_MISC0__MT__MASK;
718 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); 747 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
719 } 748 }
@@ -879,7 +908,7 @@ static int gmc_v6_0_resume(void *handle)
879static bool gmc_v6_0_is_idle(void *handle) 908static bool gmc_v6_0_is_idle(void *handle)
880{ 909{
881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
882 u32 tmp = RREG32(SRBM_STATUS); 911 u32 tmp = RREG32(mmSRBM_STATUS);
883 912
884 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 913 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
885 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 914 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
@@ -895,7 +924,7 @@ static int gmc_v6_0_wait_for_idle(void *handle)
895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896 925
897 for (i = 0; i < adev->usec_timeout; i++) { 926 for (i = 0; i < adev->usec_timeout; i++) {
898 tmp = RREG32(SRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 927 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
899 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 928 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
900 SRBM_STATUS__MCC_BUSY_MASK | 929 SRBM_STATUS__MCC_BUSY_MASK |
901 SRBM_STATUS__MCD_BUSY_MASK | 930 SRBM_STATUS__MCD_BUSY_MASK |
@@ -913,17 +942,17 @@ static int gmc_v6_0_soft_reset(void *handle)
913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914 struct amdgpu_mode_mc_save save; 943 struct amdgpu_mode_mc_save save;
915 u32 srbm_soft_reset = 0; 944 u32 srbm_soft_reset = 0;
916 u32 tmp = RREG32(SRBM_STATUS); 945 u32 tmp = RREG32(mmSRBM_STATUS);
917 946
918 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 947 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
919 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 948 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
920 mmSRBM_SOFT_RESET, xxSOFT_RESET_VMC, 1); 949 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
921 950
922 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 951 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
923 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 952 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
924 if (!(adev->flags & AMD_IS_APU)) 953 if (!(adev->flags & AMD_IS_APU))
925 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 954 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
926 mmSRBM_SOFT_RESET, xxSOFT_RESET_MC, 1); 955 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
927 } 956 }
928 957
929 if (srbm_soft_reset) { 958 if (srbm_soft_reset) {
@@ -933,17 +962,17 @@ static int gmc_v6_0_soft_reset(void *handle)
933 } 962 }
934 963
935 964
936 tmp = RREG32(SRBM_SOFT_RESET); 965 tmp = RREG32(mmSRBM_SOFT_RESET);
937 tmp |= srbm_soft_reset; 966 tmp |= srbm_soft_reset;
938 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 967 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
939 WREG32(SRBM_SOFT_RESET, tmp); 968 WREG32(mmSRBM_SOFT_RESET, tmp);
940 tmp = RREG32(SRBM_SOFT_RESET); 969 tmp = RREG32(mmSRBM_SOFT_RESET);
941 970
942 udelay(50); 971 udelay(50);
943 972
944 tmp &= ~srbm_soft_reset; 973 tmp &= ~srbm_soft_reset;
945 WREG32(SRBM_SOFT_RESET, tmp); 974 WREG32(mmSRBM_SOFT_RESET, tmp);
946 tmp = RREG32(SRBM_SOFT_RESET); 975 tmp = RREG32(mmSRBM_SOFT_RESET);
947 976
948 udelay(50); 977 udelay(50);
949 978
@@ -969,20 +998,20 @@ static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
969 998
970 switch (state) { 999 switch (state) {
971 case AMDGPU_IRQ_STATE_DISABLE: 1000 case AMDGPU_IRQ_STATE_DISABLE:
972 tmp = RREG32(VM_CONTEXT0_CNTL); 1001 tmp = RREG32(mmVM_CONTEXT0_CNTL);
973 tmp &= ~bits; 1002 tmp &= ~bits;
974 WREG32(VM_CONTEXT0_CNTL, tmp); 1003 WREG32(mmVM_CONTEXT0_CNTL, tmp);
975 tmp = RREG32(VM_CONTEXT1_CNTL); 1004 tmp = RREG32(mmVM_CONTEXT1_CNTL);
976 tmp &= ~bits; 1005 tmp &= ~bits;
977 WREG32(VM_CONTEXT1_CNTL, tmp); 1006 WREG32(mmVM_CONTEXT1_CNTL, tmp);
978 break; 1007 break;
979 case AMDGPU_IRQ_STATE_ENABLE: 1008 case AMDGPU_IRQ_STATE_ENABLE:
980 tmp = RREG32(VM_CONTEXT0_CNTL); 1009 tmp = RREG32(mmVM_CONTEXT0_CNTL);
981 tmp |= bits; 1010 tmp |= bits;
982 WREG32(VM_CONTEXT0_CNTL, tmp); 1011 WREG32(mmVM_CONTEXT0_CNTL, tmp);
983 tmp = RREG32(VM_CONTEXT1_CNTL); 1012 tmp = RREG32(mmVM_CONTEXT1_CNTL);
984 tmp |= bits; 1013 tmp |= bits;
985 WREG32(VM_CONTEXT1_CNTL, tmp); 1014 WREG32(mmVM_CONTEXT1_CNTL, tmp);
986 break; 1015 break;
987 default: 1016 default:
988 break; 1017 break;
@@ -997,9 +1026,9 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
997{ 1026{
998 u32 addr, status; 1027 u32 addr, status;
999 1028
1000 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); 1029 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1001 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); 1030 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1002 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 1031 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1003 1032
1004 if (!addr && !status) 1033 if (!addr && !status)
1005 return 0; 1034 return 0;
@@ -1007,13 +1036,15 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1007 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1036 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1008 gmc_v6_0_set_fault_enable_default(adev, false); 1037 gmc_v6_0_set_fault_enable_default(adev, false);
1009 1038
1010 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1039 if (printk_ratelimit()) {
1011 entry->src_id, entry->src_data); 1040 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1012 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1041 entry->src_id, entry->src_data);
1013 addr); 1042 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1014 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1043 addr);
1015 status); 1044 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1016 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1045 status);
1046 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1047 }
1017 1048
1018 return 0; 1049 return 0;
1019} 1050}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 3a25f72980c1..fbe1d9ac500a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
711 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 711 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
712 MEMORY_CLIENT_ID); 712 MEMORY_CLIENT_ID);
713 713
714 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 714 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
715 protections, vmid, addr, 715 protections, vmid, addr,
716 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 716 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
717 MEMORY_CLIENT_RW) ? 717 MEMORY_CLIENT_RW) ?
@@ -1198,13 +1198,15 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1198 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1198 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1199 gmc_v7_0_set_fault_enable_default(adev, false); 1199 gmc_v7_0_set_fault_enable_default(adev, false);
1200 1200
1201 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1201 if (printk_ratelimit()) {
1202 entry->src_id, entry->src_data); 1202 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1203 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1203 entry->src_id, entry->src_data);
1204 addr); 1204 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1205 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1205 addr);
1206 status); 1206 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1207 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); 1207 status);
1208 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1209 }
1208 1210
1209 return 0; 1211 return 0;
1210} 1212}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f7372d32b8e7..12ea3404dd65 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
837 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 837 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
838 MEMORY_CLIENT_ID); 838 MEMORY_CLIENT_ID);
839 839
840 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 840 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
841 protections, vmid, addr, 841 protections, vmid, addr,
842 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 842 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
843 MEMORY_CLIENT_RW) ? 843 MEMORY_CLIENT_RW) ?
@@ -1242,13 +1242,15 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1242 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1242 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1243 gmc_v8_0_set_fault_enable_default(adev, false); 1243 gmc_v8_0_set_fault_enable_default(adev, false);
1244 1244
1245 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1245 if (printk_ratelimit()) {
1246 entry->src_id, entry->src_data); 1246 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1247 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1247 entry->src_id, entry->src_data);
1248 addr); 1248 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1249 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1249 addr);
1250 status); 1250 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1251 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1251 status);
1252 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1253 }
1252 1254
1253 return 0; 1255 return 0;
1254} 1256}
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 61172d4a0657..5a1bc358bcb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2845,7 +2845,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
2845 pi->caps_tcp_ramping = true; 2845 pi->caps_tcp_ramping = true;
2846 } 2846 }
2847 2847
2848 if (amdgpu_sclk_deep_sleep_en) 2848 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
2849 pi->caps_sclk_ds = true; 2849 pi->caps_sclk_ds = true;
2850 else 2850 else
2851 pi->caps_sclk_ds = false; 2851 pi->caps_sclk_ds = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index e81aa4682760..fbe74a33899c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -775,11 +775,11 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
775 unsigned ndw = count * 2; 775 unsigned ndw = count * 2;
776 776
777 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 777 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
778 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 778 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
779 ib->ptr[ib->length_dw++] = pe; 779 ib->ptr[ib->length_dw++] = pe;
780 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 780 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
781 ib->ptr[ib->length_dw++] = ndw; 781 ib->ptr[ib->length_dw++] = ndw;
782 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 782 for (; ndw > 0; ndw -= 2) {
783 ib->ptr[ib->length_dw++] = lower_32_bits(value); 783 ib->ptr[ib->length_dw++] = lower_32_bits(value);
784 ib->ptr[ib->length_dw++] = upper_32_bits(value); 784 ib->ptr[ib->length_dw++] = upper_32_bits(value);
785 value += incr; 785 value += incr;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 77f146587c60..1170a64a3184 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -977,11 +977,11 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
977 unsigned ndw = count * 2; 977 unsigned ndw = count * 2;
978 978
979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
981 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 981 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
982 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 982 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
983 ib->ptr[ib->length_dw++] = ndw; 983 ib->ptr[ib->length_dw++] = ndw;
984 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 984 for (; ndw > 0; ndw -= 2) {
985 ib->ptr[ib->length_dw++] = lower_32_bits(value); 985 ib->ptr[ib->length_dw++] = lower_32_bits(value);
986 ib->ptr[ib->length_dw++] = upper_32_bits(value); 986 ib->ptr[ib->length_dw++] = upper_32_bits(value);
987 value += incr; 987 value += incr;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
new file mode 100644
index 000000000000..fde2086246fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -0,0 +1,272 @@
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef SI_ENUMS_H
24#define SI_ENUMS_H
25
26#define VBLANK_INT_MASK (1 << 0)
27#define DC_HPDx_INT_EN (1 << 16)
28#define VBLANK_ACK (1 << 4)
29#define VLINE_ACK (1 << 4)
30
31#define CURSOR_WIDTH 64
32#define CURSOR_HEIGHT 64
33
34#define VGA_VSTATUS_CNTL 0xFFFCFFFF
35#define PRIORITY_MARK_MASK 0x7fff
36#define PRIORITY_OFF (1 << 16)
37#define PRIORITY_ALWAYS_ON (1 << 20)
38#define INTERLEAVE_EN (1 << 0)
39
40#define LATENCY_WATERMARK_MASK(x) ((x) << 16)
41#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
42#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
43
44#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
45#define GRPH_ENDIAN_NONE 0
46#define GRPH_ENDIAN_8IN16 1
47#define GRPH_ENDIAN_8IN32 2
48#define GRPH_ENDIAN_8IN64 3
49
50#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
51#define GRPH_DEPTH_8BPP 0
52#define GRPH_DEPTH_16BPP 1
53#define GRPH_DEPTH_32BPP 2
54
55#define GRPH_FORMAT(x) (((x) & 0x7) << 8)
56#define GRPH_FORMAT_INDEXED 0
57#define GRPH_FORMAT_ARGB1555 0
58#define GRPH_FORMAT_ARGB565 1
59#define GRPH_FORMAT_ARGB4444 2
60#define GRPH_FORMAT_AI88 3
61#define GRPH_FORMAT_MONO16 4
62#define GRPH_FORMAT_BGRA5551 5
63#define GRPH_FORMAT_ARGB8888 0
64#define GRPH_FORMAT_ARGB2101010 1
65#define GRPH_FORMAT_32BPP_DIG 2
66#define GRPH_FORMAT_8B_ARGB2101010 3
67#define GRPH_FORMAT_BGRA1010102 4
68#define GRPH_FORMAT_8B_BGRA1010102 5
69#define GRPH_FORMAT_RGB111110 6
70#define GRPH_FORMAT_BGR101111 7
71
72#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
73#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
74#define GRPH_ARRAY_LINEAR_GENERAL 0
75#define GRPH_ARRAY_LINEAR_ALIGNED 1
76#define GRPH_ARRAY_1D_TILED_THIN1 2
77#define GRPH_ARRAY_2D_TILED_THIN1 4
78#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
79#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
80#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
81#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
82#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
83#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
84
85#define CURSOR_EN (1 << 0)
86#define CURSOR_MODE(x) (((x) & 0x3) << 8)
87#define CURSOR_MONO 0
88#define CURSOR_24_1 1
89#define CURSOR_24_8_PRE_MULT 2
90#define CURSOR_24_8_UNPRE_MULT 3
91#define CURSOR_2X_MAGNIFY (1 << 16)
92#define CURSOR_FORCE_MC_ON (1 << 20)
93#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
94#define CURSOR_URGENT_ALWAYS 0
95#define CURSOR_URGENT_1_8 1
96#define CURSOR_URGENT_1_4 2
97#define CURSOR_URGENT_3_8 3
98#define CURSOR_URGENT_1_2 4
99#define CURSOR_UPDATE_PENDING (1 << 0)
100#define CURSOR_UPDATE_TAKEN (1 << 1)
101#define CURSOR_UPDATE_LOCK (1 << 16)
102#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
103
104#define AMDGPU_NUM_OF_VMIDS 8
105#define SI_CRTC0_REGISTER_OFFSET 0
106#define SI_CRTC1_REGISTER_OFFSET 0x300
107#define SI_CRTC2_REGISTER_OFFSET 0x2600
108#define SI_CRTC3_REGISTER_OFFSET 0x2900
109#define SI_CRTC4_REGISTER_OFFSET 0x2c00
110#define SI_CRTC5_REGISTER_OFFSET 0x2f00
111
112#define DMA0_REGISTER_OFFSET 0x000
113#define DMA1_REGISTER_OFFSET 0x200
114#define ES_AND_GS_AUTO 3
115#define RADEON_PACKET_TYPE3 3
116#define CE_PARTITION_BASE 3
117#define BUF_SWAP_32BIT (2 << 16)
118
119#define GFX_POWER_STATUS (1 << 1)
120#define GFX_CLOCK_STATUS (1 << 2)
121#define GFX_LS_STATUS (1 << 3)
122#define RLC_BUSY_STATUS (1 << 0)
123
124#define RLC_PUD(x) ((x) << 0)
125#define RLC_PUD_MASK (0xff << 0)
126#define RLC_PDD(x) ((x) << 8)
127#define RLC_PDD_MASK (0xff << 8)
128#define RLC_TTPD(x) ((x) << 16)
129#define RLC_TTPD_MASK (0xff << 16)
130#define RLC_MSD(x) ((x) << 24)
131#define RLC_MSD_MASK (0xff << 24)
132#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
133#define WRITE_DATA_DST_SEL(x) ((x) << 8)
134#define EVENT_TYPE(x) ((x) << 0)
135#define EVENT_INDEX(x) ((x) << 8)
136#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
137#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
138#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
139
140#define GFX6_NUM_GFX_RINGS 1
141#define GFX6_NUM_COMPUTE_RINGS 2
142#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
143#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
144
145#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
146#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
147#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
148
149#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
150 (((op) & 0xFF) << 8) | \
151 ((n) & 0x3FFF) << 16)
152#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
153#define PACKET3_NOP 0x10
154#define PACKET3_SET_BASE 0x11
155#define PACKET3_BASE_INDEX(x) ((x) << 0)
156#define PACKET3_CLEAR_STATE 0x12
157#define PACKET3_INDEX_BUFFER_SIZE 0x13
158#define PACKET3_DISPATCH_DIRECT 0x15
159#define PACKET3_DISPATCH_INDIRECT 0x16
160#define PACKET3_ALLOC_GDS 0x1B
161#define PACKET3_WRITE_GDS_RAM 0x1C
162#define PACKET3_ATOMIC_GDS 0x1D
163#define PACKET3_ATOMIC 0x1E
164#define PACKET3_OCCLUSION_QUERY 0x1F
165#define PACKET3_SET_PREDICATION 0x20
166#define PACKET3_REG_RMW 0x21
167#define PACKET3_COND_EXEC 0x22
168#define PACKET3_PRED_EXEC 0x23
169#define PACKET3_DRAW_INDIRECT 0x24
170#define PACKET3_DRAW_INDEX_INDIRECT 0x25
171#define PACKET3_INDEX_BASE 0x26
172#define PACKET3_DRAW_INDEX_2 0x27
173#define PACKET3_CONTEXT_CONTROL 0x28
174#define PACKET3_INDEX_TYPE 0x2A
175#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
176#define PACKET3_DRAW_INDEX_AUTO 0x2D
177#define PACKET3_DRAW_INDEX_IMMD 0x2E
178#define PACKET3_NUM_INSTANCES 0x2F
179#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
180#define PACKET3_INDIRECT_BUFFER_CONST 0x31
181#define PACKET3_INDIRECT_BUFFER 0x3F
182#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
183#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
184#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
185#define PACKET3_WRITE_DATA 0x37
186#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
187#define PACKET3_MEM_SEMAPHORE 0x39
188#define PACKET3_MPEG_INDEX 0x3A
189#define PACKET3_COPY_DW 0x3B
190#define PACKET3_WAIT_REG_MEM 0x3C
191#define PACKET3_MEM_WRITE 0x3D
192#define PACKET3_COPY_DATA 0x40
193#define PACKET3_CP_DMA 0x41
194# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
195# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
196# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
197# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
198# define PACKET3_CP_DMA_DIS_WC (1 << 21)
199# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
200# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
201# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
202# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
203# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
204# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
205# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
206#define PACKET3_PFP_SYNC_ME 0x42
207#define PACKET3_SURFACE_SYNC 0x43
208# define PACKET3_DEST_BASE_0_ENA (1 << 0)
209# define PACKET3_DEST_BASE_1_ENA (1 << 1)
210# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
211# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
212# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
213# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
214# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
215# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
216# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
217# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
218# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
219# define PACKET3_DEST_BASE_2_ENA (1 << 19)
220# define PACKET3_DEST_BASE_3_ENA (1 << 21)
221# define PACKET3_TCL1_ACTION_ENA (1 << 22)
222# define PACKET3_TC_ACTION_ENA (1 << 23)
223# define PACKET3_CB_ACTION_ENA (1 << 25)
224# define PACKET3_DB_ACTION_ENA (1 << 26)
225# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
226# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
227#define PACKET3_ME_INITIALIZE 0x44
228#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
229#define PACKET3_COND_WRITE 0x45
230#define PACKET3_EVENT_WRITE 0x46
231#define PACKET3_EVENT_WRITE_EOP 0x47
232#define PACKET3_EVENT_WRITE_EOS 0x48
233#define PACKET3_PREAMBLE_CNTL 0x4A
234# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
235# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
236#define PACKET3_ONE_REG_WRITE 0x57
237#define PACKET3_LOAD_CONFIG_REG 0x5F
238#define PACKET3_LOAD_CONTEXT_REG 0x60
239#define PACKET3_LOAD_SH_REG 0x61
240#define PACKET3_SET_CONFIG_REG 0x68
241#define PACKET3_SET_CONFIG_REG_START 0x00002000
242#define PACKET3_SET_CONFIG_REG_END 0x00002c00
243#define PACKET3_SET_CONTEXT_REG 0x69
244#define PACKET3_SET_CONTEXT_REG_START 0x000a000
245#define PACKET3_SET_CONTEXT_REG_END 0x000a400
246#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
247#define PACKET3_SET_RESOURCE_INDIRECT 0x74
248#define PACKET3_SET_SH_REG 0x76
249#define PACKET3_SET_SH_REG_START 0x00002c00
250#define PACKET3_SET_SH_REG_END 0x00003000
251#define PACKET3_SET_SH_REG_OFFSET 0x77
252#define PACKET3_ME_WRITE 0x7A
253#define PACKET3_SCRATCH_RAM_WRITE 0x7D
254#define PACKET3_SCRATCH_RAM_READ 0x7E
255#define PACKET3_CE_WRITE 0x7F
256#define PACKET3_LOAD_CONST_RAM 0x80
257#define PACKET3_WRITE_CONST_RAM 0x81
258#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
259#define PACKET3_DUMP_CONST_RAM 0x83
260#define PACKET3_INCREMENT_CE_COUNTER 0x84
261#define PACKET3_INCREMENT_DE_COUNTER 0x85
262#define PACKET3_WAIT_ON_CE_COUNTER 0x86
263#define PACKET3_WAIT_ON_DE_COUNTER 0x87
264#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
265#define PACKET3_SET_CE_DE_COUNTERS 0x89
266#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
267#define PACKET3_SWITCH_BUFFER 0x8B
268#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
269#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
270#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
271
272#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 8f9c7d55ddda..96444e4d862a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -45,7 +45,8 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
45static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 45static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
46static int uvd_v4_2_start(struct amdgpu_device *adev); 46static int uvd_v4_2_start(struct amdgpu_device *adev);
47static void uvd_v4_2_stop(struct amdgpu_device *adev); 47static void uvd_v4_2_stop(struct amdgpu_device *adev);
48 48static int uvd_v4_2_set_clockgating_state(void *handle,
49 enum amd_clockgating_state state);
49/** 50/**
50 * uvd_v4_2_ring_get_rptr - get read pointer 51 * uvd_v4_2_ring_get_rptr - get read pointer
51 * 52 *
@@ -154,9 +155,9 @@ static int uvd_v4_2_hw_init(void *handle)
154 uint32_t tmp; 155 uint32_t tmp;
155 int r; 156 int r;
156 157
157 /* raise clocks while booting up the VCPU */ 158 uvd_v4_2_init_cg(adev);
158 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 159 uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE);
159 160 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
160 r = uvd_v4_2_start(adev); 161 r = uvd_v4_2_start(adev);
161 if (r) 162 if (r)
162 goto done; 163 goto done;
@@ -196,8 +197,6 @@ static int uvd_v4_2_hw_init(void *handle)
196 amdgpu_ring_commit(ring); 197 amdgpu_ring_commit(ring);
197 198
198done: 199done:
199 /* lower clocks again */
200 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
201 200
202 if (!r) 201 if (!r)
203 DRM_INFO("UVD initialized successfully.\n"); 202 DRM_INFO("UVD initialized successfully.\n");
@@ -274,9 +273,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
274 273
275 uvd_v4_2_mc_resume(adev); 274 uvd_v4_2_mc_resume(adev);
276 275
277 /* disable clock gating */
278 WREG32(mmUVD_CGC_GATE, 0);
279
280 /* disable interupt */ 276 /* disable interupt */
281 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 277 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
282 278
@@ -568,8 +564,6 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
568 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 564 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
569 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 565 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
570 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 566 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
571
572 uvd_v4_2_init_cg(adev);
573} 567}
574 568
575static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 569static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
@@ -579,7 +573,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
579 573
580 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 574 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
581 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 575 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
582 data = 0xfff; 576 data |= 0xfff;
583 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 577 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
584 578
585 orig = data = RREG32(mmUVD_CGC_CTRL); 579 orig = data = RREG32(mmUVD_CGC_CTRL);
@@ -603,6 +597,8 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
603{ 597{
604 u32 tmp, tmp2; 598 u32 tmp, tmp2;
605 599
600 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
601
606 tmp = RREG32(mmUVD_CGC_CTRL); 602 tmp = RREG32(mmUVD_CGC_CTRL);
607 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 603 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
608 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 604 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
@@ -686,34 +682,18 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
686 return 0; 682 return 0;
687} 683}
688 684
689static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
690{
691 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
692
693 if (enable)
694 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
695 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
696 else
697 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
698 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
699
700 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
701}
702
703static int uvd_v4_2_set_clockgating_state(void *handle, 685static int uvd_v4_2_set_clockgating_state(void *handle,
704 enum amd_clockgating_state state) 686 enum amd_clockgating_state state)
705{ 687{
706 bool gate = false; 688 bool gate = false;
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
708 690
709 if (state == AMD_CG_STATE_GATE)
710 gate = true;
711
712 uvd_v5_0_set_bypass_mode(adev, gate);
713
714 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 691 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
715 return 0; 692 return 0;
716 693
694 if (state == AMD_CG_STATE_GATE)
695 gate = true;
696
717 uvd_v4_2_enable_mgcg(adev, gate); 697 uvd_v4_2_enable_mgcg(adev, gate);
718 698
719 return 0; 699 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 95303e2d5f92..95cabeafc18e 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -40,7 +40,10 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
40static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 40static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
41static int uvd_v5_0_start(struct amdgpu_device *adev); 41static int uvd_v5_0_start(struct amdgpu_device *adev);
42static void uvd_v5_0_stop(struct amdgpu_device *adev); 42static void uvd_v5_0_stop(struct amdgpu_device *adev);
43 43static int uvd_v5_0_set_clockgating_state(void *handle,
44 enum amd_clockgating_state state);
45static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
46 bool enable);
44/** 47/**
45 * uvd_v5_0_ring_get_rptr - get read pointer 48 * uvd_v5_0_ring_get_rptr - get read pointer
46 * 49 *
@@ -149,9 +152,6 @@ static int uvd_v5_0_hw_init(void *handle)
149 uint32_t tmp; 152 uint32_t tmp;
150 int r; 153 int r;
151 154
152 /* raise clocks while booting up the VCPU */
153 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
154
155 r = uvd_v5_0_start(adev); 155 r = uvd_v5_0_start(adev);
156 if (r) 156 if (r)
157 goto done; 157 goto done;
@@ -189,11 +189,7 @@ static int uvd_v5_0_hw_init(void *handle)
189 amdgpu_ring_write(ring, 3); 189 amdgpu_ring_write(ring, 3);
190 190
191 amdgpu_ring_commit(ring); 191 amdgpu_ring_commit(ring);
192
193done: 192done:
194 /* lower clocks again */
195 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
196
197 if (!r) 193 if (!r)
198 DRM_INFO("UVD initialized successfully.\n"); 194 DRM_INFO("UVD initialized successfully.\n");
199 195
@@ -226,6 +222,7 @@ static int uvd_v5_0_suspend(void *handle)
226 r = uvd_v5_0_hw_fini(adev); 222 r = uvd_v5_0_hw_fini(adev);
227 if (r) 223 if (r)
228 return r; 224 return r;
225 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
229 226
230 r = amdgpu_uvd_suspend(adev); 227 r = amdgpu_uvd_suspend(adev);
231 if (r) 228 if (r)
@@ -313,8 +310,9 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
313 310
314 uvd_v5_0_mc_resume(adev); 311 uvd_v5_0_mc_resume(adev);
315 312
316 /* disable clock gating */ 313 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
317 WREG32(mmUVD_CGC_GATE, 0); 314 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
315 uvd_v5_0_enable_mgcg(adev, true);
318 316
319 /* disable interupt */ 317 /* disable interupt */
320 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 318 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
@@ -628,16 +626,12 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
628 return 0; 626 return 0;
629} 627}
630 628
631static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 629static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
632{ 630{
633 uint32_t data, data1, data2, suvd_flags; 631 uint32_t data1, data3, suvd_flags;
634 632
635 data = RREG32(mmUVD_CGC_CTRL);
636 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 633 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
637 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 634 data3 = RREG32(mmUVD_CGC_GATE);
638
639 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
640 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
641 635
642 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 636 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
643 UVD_SUVD_CGC_GATE__SIT_MASK | 637 UVD_SUVD_CGC_GATE__SIT_MASK |
@@ -645,6 +639,49 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
645 UVD_SUVD_CGC_GATE__SCM_MASK | 639 UVD_SUVD_CGC_GATE__SCM_MASK |
646 UVD_SUVD_CGC_GATE__SDB_MASK; 640 UVD_SUVD_CGC_GATE__SDB_MASK;
647 641
642 if (enable) {
643 data3 |= (UVD_CGC_GATE__SYS_MASK |
644 UVD_CGC_GATE__UDEC_MASK |
645 UVD_CGC_GATE__MPEG2_MASK |
646 UVD_CGC_GATE__RBC_MASK |
647 UVD_CGC_GATE__LMI_MC_MASK |
648 UVD_CGC_GATE__IDCT_MASK |
649 UVD_CGC_GATE__MPRD_MASK |
650 UVD_CGC_GATE__MPC_MASK |
651 UVD_CGC_GATE__LBSI_MASK |
652 UVD_CGC_GATE__LRBBM_MASK |
653 UVD_CGC_GATE__UDEC_RE_MASK |
654 UVD_CGC_GATE__UDEC_CM_MASK |
655 UVD_CGC_GATE__UDEC_IT_MASK |
656 UVD_CGC_GATE__UDEC_DB_MASK |
657 UVD_CGC_GATE__UDEC_MP_MASK |
658 UVD_CGC_GATE__WCB_MASK |
659 UVD_CGC_GATE__VCPU_MASK |
660 UVD_CGC_GATE__JPEG_MASK |
661 UVD_CGC_GATE__SCPU_MASK);
662 data3 &= ~UVD_CGC_GATE__REGS_MASK;
663 data1 |= suvd_flags;
664 } else {
665 data3 = 0;
666 data1 = 0;
667 }
668
669 WREG32(mmUVD_SUVD_CGC_GATE, data1);
670 WREG32(mmUVD_CGC_GATE, data3);
671}
672
673static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
674{
675 uint32_t data, data2;
676
677 data = RREG32(mmUVD_CGC_CTRL);
678 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
679
680
681 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
682 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
683
684
648 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 685 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
649 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 686 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
650 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 687 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
@@ -675,11 +712,8 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
675 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 712 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
676 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 713 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
677 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 714 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
678 data1 |= suvd_flags;
679 715
680 WREG32(mmUVD_CGC_CTRL, data); 716 WREG32(mmUVD_CGC_CTRL, data);
681 WREG32(mmUVD_CGC_GATE, 0);
682 WREG32(mmUVD_SUVD_CGC_GATE, data1);
683 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 717 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
684} 718}
685 719
@@ -724,18 +758,30 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
724} 758}
725#endif 759#endif
726 760
727static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 761static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
762 bool enable)
728{ 763{
729 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 764 u32 orig, data;
730 765
731 if (enable) 766 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
732 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 767 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
733 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 768 data |= 0xfff;
734 else 769 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
735 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
736 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
737 770
738 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 771 orig = data = RREG32(mmUVD_CGC_CTRL);
772 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
773 if (orig != data)
774 WREG32(mmUVD_CGC_CTRL, data);
775 } else {
776 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
777 data &= ~0xfff;
778 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
779
780 orig = data = RREG32(mmUVD_CGC_CTRL);
781 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
782 if (orig != data)
783 WREG32(mmUVD_CGC_CTRL, data);
784 }
739} 785}
740 786
741static int uvd_v5_0_set_clockgating_state(void *handle, 787static int uvd_v5_0_set_clockgating_state(void *handle,
@@ -745,8 +791,6 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
745 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 791 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
746 static int curstate = -1; 792 static int curstate = -1;
747 793
748 uvd_v5_0_set_bypass_mode(adev, enable);
749
750 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 794 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
751 return 0; 795 return 0;
752 796
@@ -755,17 +799,18 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
755 799
756 curstate = state; 800 curstate = state;
757 if (enable) { 801 if (enable) {
758 /* disable HW gating and enable Sw gating */
759 uvd_v5_0_set_sw_clock_gating(adev);
760 } else {
761 /* wait for STATUS to clear */ 802 /* wait for STATUS to clear */
762 if (uvd_v5_0_wait_for_idle(handle)) 803 if (uvd_v5_0_wait_for_idle(handle))
763 return -EBUSY; 804 return -EBUSY;
805 uvd_v5_0_enable_clock_gating(adev, true);
764 806
765 /* enable HW gates because UVD is idle */ 807 /* enable HW gates because UVD is idle */
766/* uvd_v5_0_set_hw_clock_gating(adev); */ 808/* uvd_v5_0_set_hw_clock_gating(adev); */
809 } else {
810 uvd_v5_0_enable_clock_gating(adev, false);
767 } 811 }
768 812
813 uvd_v5_0_set_sw_clock_gating(adev);
769 return 0; 814 return 0;
770} 815}
771 816
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a339b5ccb296..00fad6951d82 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -151,6 +151,8 @@ static int uvd_v6_0_hw_init(void *handle)
151 uint32_t tmp; 151 uint32_t tmp;
152 int r; 152 int r;
153 153
154 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
155
154 r = uvd_v6_0_start(adev); 156 r = uvd_v6_0_start(adev);
155 if (r) 157 if (r)
156 goto done; 158 goto done;
@@ -935,28 +937,12 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
935} 937}
936#endif 938#endif
937 939
938static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
939{
940 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
941
942 if (enable)
943 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
944 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
945 else
946 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
947 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
948
949 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
950}
951
952static int uvd_v6_0_set_clockgating_state(void *handle, 940static int uvd_v6_0_set_clockgating_state(void *handle,
953 enum amd_clockgating_state state) 941 enum amd_clockgating_state state)
954{ 942{
955 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
956 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 944 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
957 945
958 uvd_v6_0_set_bypass_mode(adev, enable);
959
960 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 946 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
961 return 0; 947 return 0;
962 948
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0b21e7beda91..243dcf7bae47 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -926,7 +926,8 @@ static int vi_common_early_init(void *handle)
926 AMD_CG_SUPPORT_HDP_LS | 926 AMD_CG_SUPPORT_HDP_LS |
927 AMD_CG_SUPPORT_ROM_MGCG | 927 AMD_CG_SUPPORT_ROM_MGCG |
928 AMD_CG_SUPPORT_MC_MGCG | 928 AMD_CG_SUPPORT_MC_MGCG |
929 AMD_CG_SUPPORT_MC_LS; 929 AMD_CG_SUPPORT_MC_LS |
930 AMD_CG_SUPPORT_UVD_MGCG;
930 adev->pg_flags = 0; 931 adev->pg_flags = 0;
931 adev->external_rev_id = adev->rev_id + 0x3c; 932 adev->external_rev_id = adev->rev_id + 0x3c;
932 break; 933 break;
@@ -936,12 +937,12 @@ static int vi_common_early_init(void *handle)
936 adev->external_rev_id = adev->rev_id + 0x14; 937 adev->external_rev_id = adev->rev_id + 0x14;
937 break; 938 break;
938 case CHIP_POLARIS11: 939 case CHIP_POLARIS11:
939 adev->cg_flags = 0; 940 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
940 adev->pg_flags = 0; 941 adev->pg_flags = 0;
941 adev->external_rev_id = adev->rev_id + 0x5A; 942 adev->external_rev_id = adev->rev_id + 0x5A;
942 break; 943 break;
943 case CHIP_POLARIS10: 944 case CHIP_POLARIS10:
944 adev->cg_flags = 0; 945 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
945 adev->pg_flags = 0; 946 adev->pg_flags = 0;
946 adev->external_rev_id = adev->rev_id + 0x50; 947 adev->external_rev_id = adev->rev_id + 0x50;
947 break; 948 break;
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h
new file mode 100644
index 000000000000..7138fbf7256a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h
@@ -0,0 +1,661 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef BIF_3_0_D_H
24#define BIF_3_0_D_H
25
26#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C
27#define ixPB0_DFT_JIT_INJ_REG0 0x13000
28#define ixPB0_DFT_JIT_INJ_REG1 0x13004
29#define ixPB0_DFT_JIT_INJ_REG2 0x13008
30#define ixPB0_GLB_CTRL_REG0 0x10004
31#define ixPB0_GLB_CTRL_REG1 0x10008
32#define ixPB0_GLB_CTRL_REG2 0x1000C
33#define ixPB0_GLB_CTRL_REG3 0x10010
34#define ixPB0_GLB_CTRL_REG4 0x10014
35#define ixPB0_GLB_CTRL_REG5 0x10018
36#define ixPB0_GLB_OVRD_REG0 0x10030
37#define ixPB0_GLB_OVRD_REG1 0x10034
38#define ixPB0_GLB_OVRD_REG2 0x10038
39#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C
40#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020
41#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024
42#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028
43#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C
44#define ixPB0_HW_DEBUG 0x12004
45#define ixPB0_PIF_CNTL 0x0010
46#define ixPB0_PIF_CNTL2 0x0014
47#define ixPB0_PIF_HW_DEBUG 0x0002
48#define ixPB0_PIF_PAIRING 0x0011
49#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020
50#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032
51#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021
52#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033
53#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034
54#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035
55#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036
56#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037
57#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022
58#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023
59#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024
60#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025
61#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026
62#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027
63#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030
64#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031
65#define ixPB0_PIF_PWRDOWN_0 0x0012
66#define ixPB0_PIF_PWRDOWN_1 0x0013
67#define ixPB0_PIF_PWRDOWN_2 0x0017
68#define ixPB0_PIF_PWRDOWN_3 0x0018
69#define ixPB0_PIF_SC_CTL 0x0016
70#define ixPB0_PIF_SCRATCH 0x0001
71#define ixPB0_PIF_SEQ_STATUS_0 0x0028
72#define ixPB0_PIF_SEQ_STATUS_10 0x003A
73#define ixPB0_PIF_SEQ_STATUS_1 0x0029
74#define ixPB0_PIF_SEQ_STATUS_11 0x003B
75#define ixPB0_PIF_SEQ_STATUS_12 0x003C
76#define ixPB0_PIF_SEQ_STATUS_13 0x003D
77#define ixPB0_PIF_SEQ_STATUS_14 0x003E
78#define ixPB0_PIF_SEQ_STATUS_15 0x003F
79#define ixPB0_PIF_SEQ_STATUS_2 0x002A
80#define ixPB0_PIF_SEQ_STATUS_3 0x002B
81#define ixPB0_PIF_SEQ_STATUS_4 0x002C
82#define ixPB0_PIF_SEQ_STATUS_5 0x002D
83#define ixPB0_PIF_SEQ_STATUS_6 0x002E
84#define ixPB0_PIF_SEQ_STATUS_7 0x002F
85#define ixPB0_PIF_SEQ_STATUS_8 0x0038
86#define ixPB0_PIF_SEQ_STATUS_9 0x0039
87#define ixPB0_PIF_TXPHYSTATUS 0x0015
88#define ixPB0_PLL_LC0_CTRL_REG0 0x14480
89#define ixPB0_PLL_LC0_OVRD_REG0 0x14490
90#define ixPB0_PLL_LC0_OVRD_REG1 0x14494
91#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
92#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
93#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
94#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
95#define ixPB0_PLL_RO0_CTRL_REG0 0x14440
96#define ixPB0_PLL_RO0_OVRD_REG0 0x14450
97#define ixPB0_PLL_RO0_OVRD_REG1 0x14454
98#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
99#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
100#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
101#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
102#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000
103#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010
104#define ixPB0_RX_GLB_CTRL_REG0 0x16000
105#define ixPB0_RX_GLB_CTRL_REG1 0x16004
106#define ixPB0_RX_GLB_CTRL_REG2 0x16008
107#define ixPB0_RX_GLB_CTRL_REG3 0x1600C
108#define ixPB0_RX_GLB_CTRL_REG4 0x16010
109#define ixPB0_RX_GLB_CTRL_REG5 0x16014
110#define ixPB0_RX_GLB_CTRL_REG6 0x16018
111#define ixPB0_RX_GLB_CTRL_REG7 0x1601C
112#define ixPB0_RX_GLB_CTRL_REG8 0x16020
113#define ixPB0_RX_GLB_OVRD_REG0 0x16030
114#define ixPB0_RX_GLB_OVRD_REG1 0x16034
115#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028
116#define ixPB0_RX_LANE0_CTRL_REG0 0x16440
117#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448
118#define ixPB0_RX_LANE10_CTRL_REG0 0x17500
119#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508
120#define ixPB0_RX_LANE11_CTRL_REG0 0x17600
121#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608
122#define ixPB0_RX_LANE12_CTRL_REG0 0x17840
123#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848
124#define ixPB0_RX_LANE13_CTRL_REG0 0x17880
125#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888
126#define ixPB0_RX_LANE14_CTRL_REG0 0x17900
127#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908
128#define ixPB0_RX_LANE15_CTRL_REG0 0x17A00
129#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08
130#define ixPB0_RX_LANE1_CTRL_REG0 0x16480
131#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488
132#define ixPB0_RX_LANE2_CTRL_REG0 0x16500
133#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508
134#define ixPB0_RX_LANE3_CTRL_REG0 0x16600
135#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608
136#define ixPB0_RX_LANE4_CTRL_REG0 0x16800
137#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848
138#define ixPB0_RX_LANE5_CTRL_REG0 0x16880
139#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888
140#define ixPB0_RX_LANE6_CTRL_REG0 0x16900
141#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908
142#define ixPB0_RX_LANE7_CTRL_REG0 0x16A00
143#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08
144#define ixPB0_RX_LANE8_CTRL_REG0 0x17440
145#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448
146#define ixPB0_RX_LANE9_CTRL_REG0 0x17480
147#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488
148#define ixPB0_STRAP_GLB_REG0 0x12020
149#define ixPB0_STRAP_PLL_REG0 0x12030
150#define ixPB0_STRAP_RX_REG0 0x12028
151#define ixPB0_STRAP_RX_REG1 0x1202C
152#define ixPB0_STRAP_TX_REG0 0x12024
153#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014
154#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018
155#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C
156#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020
157#define ixPB0_TX_GLB_CTRL_REG0 0x18000
158#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004
159#define ixPB0_TX_GLB_OVRD_REG0 0x18030
160#define ixPB0_TX_GLB_OVRD_REG1 0x18034
161#define ixPB0_TX_GLB_OVRD_REG2 0x18038
162#define ixPB0_TX_GLB_OVRD_REG3 0x1803C
163#define ixPB0_TX_GLB_OVRD_REG4 0x18040
164#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010
165#define ixPB0_TX_LANE0_CTRL_REG0 0x18440
166#define ixPB0_TX_LANE0_OVRD_REG0 0x18444
167#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448
168#define ixPB0_TX_LANE10_CTRL_REG0 0x19500
169#define ixPB0_TX_LANE10_OVRD_REG0 0x19504
170#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508
171#define ixPB0_TX_LANE11_CTRL_REG0 0x19600
172#define ixPB0_TX_LANE11_OVRD_REG0 0x19604
173#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608
174#define ixPB0_TX_LANE12_CTRL_REG0 0x19840
175#define ixPB0_TX_LANE12_OVRD_REG0 0x19844
176#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848
177#define ixPB0_TX_LANE13_CTRL_REG0 0x19880
178#define ixPB0_TX_LANE13_OVRD_REG0 0x19884
179#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888
180#define ixPB0_TX_LANE14_CTRL_REG0 0x19900
181#define ixPB0_TX_LANE14_OVRD_REG0 0x19904
182#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908
183#define ixPB0_TX_LANE15_CTRL_REG0 0x19A00
184#define ixPB0_TX_LANE15_OVRD_REG0 0x19A04
185#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08
186#define ixPB0_TX_LANE1_CTRL_REG0 0x18480
187#define ixPB0_TX_LANE1_OVRD_REG0 0x18484
188#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488
189#define ixPB0_TX_LANE2_CTRL_REG0 0x18500
190#define ixPB0_TX_LANE2_OVRD_REG0 0x18504
191#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508
192#define ixPB0_TX_LANE3_CTRL_REG0 0x18600
193#define ixPB0_TX_LANE3_OVRD_REG0 0x18604
194#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608
195#define ixPB0_TX_LANE4_CTRL_REG0 0x18840
196#define ixPB0_TX_LANE4_OVRD_REG0 0x18844
197#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848
198#define ixPB0_TX_LANE5_CTRL_REG0 0x18880
199#define ixPB0_TX_LANE5_OVRD_REG0 0x18884
200#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888
201#define ixPB0_TX_LANE6_CTRL_REG0 0x18900
202#define ixPB0_TX_LANE6_OVRD_REG0 0x18904
203#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908
204#define ixPB0_TX_LANE7_CTRL_REG0 0x18A00
205#define ixPB0_TX_LANE7_OVRD_REG0 0x18A04
206#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08
207#define ixPB0_TX_LANE8_CTRL_REG0 0x19440
208#define ixPB0_TX_LANE8_OVRD_REG0 0x19444
209#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448
210#define ixPB0_TX_LANE9_CTRL_REG0 0x19480
211#define ixPB0_TX_LANE9_OVRD_REG0 0x19484
212#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488
213#define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C
214#define ixPB1_DFT_JIT_INJ_REG0 0x13000
215#define ixPB1_DFT_JIT_INJ_REG1 0x13004
216#define ixPB1_DFT_JIT_INJ_REG2 0x13008
217#define ixPB1_GLB_CTRL_REG0 0x10004
218#define ixPB1_GLB_CTRL_REG1 0x10008
219#define ixPB1_GLB_CTRL_REG2 0x1000C
220#define ixPB1_GLB_CTRL_REG3 0x10010
221#define ixPB1_GLB_CTRL_REG4 0x10014
222#define ixPB1_GLB_CTRL_REG5 0x10018
223#define ixPB1_GLB_OVRD_REG0 0x10030
224#define ixPB1_GLB_OVRD_REG1 0x10034
225#define ixPB1_GLB_OVRD_REG2 0x10038
226#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C
227#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020
228#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024
229#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028
230#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C
231#define ixPB1_HW_DEBUG 0x12004
232#define ixPB1_PIF_CNTL 0x0010
233#define ixPB1_PIF_CNTL2 0x0014
234#define ixPB1_PIF_HW_DEBUG 0x0002
235#define ixPB1_PIF_PAIRING 0x0011
236#define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020
237#define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032
238#define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021
239#define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033
240#define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034
241#define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035
242#define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036
243#define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037
244#define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022
245#define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023
246#define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024
247#define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025
248#define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026
249#define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027
250#define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030
251#define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031
252#define ixPB1_PIF_PWRDOWN_0 0x0012
253#define ixPB1_PIF_PWRDOWN_1 0x0013
254#define ixPB1_PIF_PWRDOWN_2 0x0017
255#define ixPB1_PIF_PWRDOWN_3 0x0018
256#define ixPB1_PIF_SC_CTL 0x0016
257#define ixPB1_PIF_SCRATCH 0x0001
258#define ixPB1_PIF_SEQ_STATUS_0 0x0028
259#define ixPB1_PIF_SEQ_STATUS_10 0x003A
260#define ixPB1_PIF_SEQ_STATUS_1 0x0029
261#define ixPB1_PIF_SEQ_STATUS_11 0x003B
262#define ixPB1_PIF_SEQ_STATUS_12 0x003C
263#define ixPB1_PIF_SEQ_STATUS_13 0x003D
264#define ixPB1_PIF_SEQ_STATUS_14 0x003E
265#define ixPB1_PIF_SEQ_STATUS_15 0x003F
266#define ixPB1_PIF_SEQ_STATUS_2 0x002A
267#define ixPB1_PIF_SEQ_STATUS_3 0x002B
268#define ixPB1_PIF_SEQ_STATUS_4 0x002C
269#define ixPB1_PIF_SEQ_STATUS_5 0x002D
270#define ixPB1_PIF_SEQ_STATUS_6 0x002E
271#define ixPB1_PIF_SEQ_STATUS_7 0x002F
272#define ixPB1_PIF_SEQ_STATUS_8 0x0038
273#define ixPB1_PIF_SEQ_STATUS_9 0x0039
274#define ixPB1_PIF_TXPHYSTATUS 0x0015
275#define ixPB1_PLL_LC0_CTRL_REG0 0x14480
276#define ixPB1_PLL_LC0_OVRD_REG0 0x14490
277#define ixPB1_PLL_LC0_OVRD_REG1 0x14494
278#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
279#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
280#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
281#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
282#define ixPB1_PLL_RO0_CTRL_REG0 0x14440
283#define ixPB1_PLL_RO0_OVRD_REG0 0x14450
284#define ixPB1_PLL_RO0_OVRD_REG1 0x14454
285#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
286#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
287#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
288#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
289#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000
290#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010
291#define ixPB1_RX_GLB_CTRL_REG0 0x16000
292#define ixPB1_RX_GLB_CTRL_REG1 0x16004
293#define ixPB1_RX_GLB_CTRL_REG2 0x16008
294#define ixPB1_RX_GLB_CTRL_REG3 0x1600C
295#define ixPB1_RX_GLB_CTRL_REG4 0x16010
296#define ixPB1_RX_GLB_CTRL_REG5 0x16014
297#define ixPB1_RX_GLB_CTRL_REG6 0x16018
298#define ixPB1_RX_GLB_CTRL_REG7 0x1601C
299#define ixPB1_RX_GLB_CTRL_REG8 0x16020
300#define ixPB1_RX_GLB_OVRD_REG0 0x16030
301#define ixPB1_RX_GLB_OVRD_REG1 0x16034
302#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028
303#define ixPB1_RX_LANE0_CTRL_REG0 0x16440
304#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448
305#define ixPB1_RX_LANE10_CTRL_REG0 0x17500
306#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508
307#define ixPB1_RX_LANE11_CTRL_REG0 0x17600
308#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608
309#define ixPB1_RX_LANE12_CTRL_REG0 0x17840
310#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848
311#define ixPB1_RX_LANE13_CTRL_REG0 0x17880
312#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888
313#define ixPB1_RX_LANE14_CTRL_REG0 0x17900
314#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908
315#define ixPB1_RX_LANE15_CTRL_REG0 0x17A00
316#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08
317#define ixPB1_RX_LANE1_CTRL_REG0 0x16480
318#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488
319#define ixPB1_RX_LANE2_CTRL_REG0 0x16500
320#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508
321#define ixPB1_RX_LANE3_CTRL_REG0 0x16600
322#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608
323#define ixPB1_RX_LANE4_CTRL_REG0 0x16800
324#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848
325#define ixPB1_RX_LANE5_CTRL_REG0 0x16880
326#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888
327#define ixPB1_RX_LANE6_CTRL_REG0 0x16900
328#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908
329#define ixPB1_RX_LANE7_CTRL_REG0 0x16A00
330#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08
331#define ixPB1_RX_LANE8_CTRL_REG0 0x17440
332#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448
333#define ixPB1_RX_LANE9_CTRL_REG0 0x17480
334#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488
335#define ixPB1_STRAP_GLB_REG0 0x12020
336#define ixPB1_STRAP_PLL_REG0 0x12030
337#define ixPB1_STRAP_RX_REG0 0x12028
338#define ixPB1_STRAP_RX_REG1 0x1202C
339#define ixPB1_STRAP_TX_REG0 0x12024
340#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014
341#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018
342#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C
343#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020
344#define ixPB1_TX_GLB_CTRL_REG0 0x18000
345#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004
346#define ixPB1_TX_GLB_OVRD_REG0 0x18030
347#define ixPB1_TX_GLB_OVRD_REG1 0x18034
348#define ixPB1_TX_GLB_OVRD_REG2 0x18038
349#define ixPB1_TX_GLB_OVRD_REG3 0x1803C
350#define ixPB1_TX_GLB_OVRD_REG4 0x18040
351#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010
352#define ixPB1_TX_LANE0_CTRL_REG0 0x18440
353#define ixPB1_TX_LANE0_OVRD_REG0 0x18444
354#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448
355#define ixPB1_TX_LANE10_CTRL_REG0 0x19500
356#define ixPB1_TX_LANE10_OVRD_REG0 0x19504
357#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508
358#define ixPB1_TX_LANE11_CTRL_REG0 0x19600
359#define ixPB1_TX_LANE11_OVRD_REG0 0x19604
360#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608
361#define ixPB1_TX_LANE12_CTRL_REG0 0x19840
362#define ixPB1_TX_LANE12_OVRD_REG0 0x19844
363#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848
364#define ixPB1_TX_LANE13_CTRL_REG0 0x19880
365#define ixPB1_TX_LANE13_OVRD_REG0 0x19884
366#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888
367#define ixPB1_TX_LANE14_CTRL_REG0 0x19900
368#define ixPB1_TX_LANE14_OVRD_REG0 0x19904
369#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908
370#define ixPB1_TX_LANE15_CTRL_REG0 0x19A00
371#define ixPB1_TX_LANE15_OVRD_REG0 0x19A04
372#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08
373#define ixPB1_TX_LANE1_CTRL_REG0 0x18480
374#define ixPB1_TX_LANE1_OVRD_REG0 0x18484
375#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488
376#define ixPB1_TX_LANE2_CTRL_REG0 0x18500
377#define ixPB1_TX_LANE2_OVRD_REG0 0x18504
378#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508
379#define ixPB1_TX_LANE3_CTRL_REG0 0x18600
380#define ixPB1_TX_LANE3_OVRD_REG0 0x18604
381#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608
382#define ixPB1_TX_LANE4_CTRL_REG0 0x18840
383#define ixPB1_TX_LANE4_OVRD_REG0 0x18844
384#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848
385#define ixPB1_TX_LANE5_CTRL_REG0 0x18880
386#define ixPB1_TX_LANE5_OVRD_REG0 0x18884
387#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888
388#define ixPB1_TX_LANE6_CTRL_REG0 0x18900
389#define ixPB1_TX_LANE6_OVRD_REG0 0x18904
390#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908
391#define ixPB1_TX_LANE7_CTRL_REG0 0x18A00
392#define ixPB1_TX_LANE7_OVRD_REG0 0x18A04
393#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08
394#define ixPB1_TX_LANE8_CTRL_REG0 0x19440
395#define ixPB1_TX_LANE8_OVRD_REG0 0x19444
396#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448
397#define ixPB1_TX_LANE9_CTRL_REG0 0x19480
398#define ixPB1_TX_LANE9_OVRD_REG0 0x19484
399#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488
400#define ixPCIE_BUS_CNTL 0x0021
401#define ixPCIE_CFG_CNTL 0x003C
402#define ixPCIE_CI_CNTL 0x0020
403#define ixPCIE_CNTL 0x0010
404#define ixPCIE_CNTL2 0x001C
405#define ixPCIE_CONFIG_CNTL 0x0011
406#define ixPCIE_DEBUG_CNTL 0x0012
407#define ixPCIE_ERR_CNTL 0x006A
408#define ixPCIE_F0_DPA_CAP 0x00E0
409#define ixPCIE_F0_DPA_CNTL 0x00E5
410#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4
411#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7
412#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8
413#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9
414#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA
415#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB
416#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC
417#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED
418#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE
419#define ixPCIE_FC_CPL 0x0062
420#define ixPCIE_FC_NP 0x0061
421#define ixPCIE_FC_P 0x0060
422#define ixPCIE_HW_DEBUG 0x0002
423#define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A
424#define ixPCIE_I2C_REG_DATA 0x003B
425#define ixPCIE_INT_CNTL 0x001A
426#define ixPCIE_INT_STATUS 0x001B
427#define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9
428#define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2
429#define ixPCIE_LC_CDR_CNTL 0x00B3
430#define ixPCIE_LC_CNTL 0x00A0
431#define ixPCIE_LC_CNTL2 0x00B1
432#define ixPCIE_LC_CNTL3 0x00B5
433#define ixPCIE_LC_CNTL4 0x00B6
434#define ixPCIE_LC_CNTL5 0x00B7
435#define ixPCIE_LC_FORCE_COEFF 0x00B8
436#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA
437#define ixPCIE_LC_LANE_CNTL 0x00B4
438#define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2
439#define ixPCIE_LC_N_FTS_CNTL 0x00A3
440#define ixPCIE_LC_SPEED_CNTL 0x00A4
441#define ixPCIE_LC_STATE0 0x00A5
442#define ixPCIE_LC_STATE10 0x0026
443#define ixPCIE_LC_STATE1 0x00A6
444#define ixPCIE_LC_STATE11 0x0027
445#define ixPCIE_LC_STATE2 0x00A7
446#define ixPCIE_LC_STATE3 0x00A8
447#define ixPCIE_LC_STATE4 0x00A9
448#define ixPCIE_LC_STATE5 0x00AA
449#define ixPCIE_LC_STATE6 0x0022
450#define ixPCIE_LC_STATE7 0x0023
451#define ixPCIE_LC_STATE8 0x0024
452#define ixPCIE_LC_STATE9 0x0025
453#define ixPCIE_LC_STATUS1 0x0028
454#define ixPCIE_LC_STATUS2 0x0029
455#define ixPCIE_LC_TRAINING_CNTL 0x00A1
456#define ixPCIE_P_BUF_STATUS 0x0041
457#define ixPCIE_P_CNTL 0x0040
458#define ixPCIE_P_DECODER_STATUS 0x0042
459#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093
460#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094
461#define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087
462#define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084
463#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090
464#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A
465#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D
466#define ixPCIE_PERF_CNTL_TXCLK 0x0081
467#define ixPCIE_PERF_CNTL_TXCLK2 0x0095
468#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088
469#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085
470#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091
471#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B
472#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E
473#define ixPCIE_PERF_COUNT0_TXCLK 0x0082
474#define ixPCIE_PERF_COUNT0_TXCLK2 0x0096
475#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089
476#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086
477#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092
478#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C
479#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F
480#define ixPCIE_PERF_COUNT1_TXCLK 0x0083
481#define ixPCIE_PERF_COUNT1_TXCLK2 0x0097
482#define ixPCIE_PERF_COUNT_CNTL 0x0080
483#define ixPCIEP_HW_DEBUG 0x0002
484#define ixPCIE_P_MISC_STATUS 0x0043
485#define ixPCIEP_PORT_CNTL 0x0010
486#define ixPCIE_P_PORT_LANE_STATUS 0x0050
487#define ixPCIE_PRBS_CLR 0x00C8
488#define ixPCIE_PRBS_ERRCNT_0 0x00D0
489#define ixPCIE_PRBS_ERRCNT_10 0x00DA
490#define ixPCIE_PRBS_ERRCNT_1 0x00D1
491#define ixPCIE_PRBS_ERRCNT_11 0x00DB
492#define ixPCIE_PRBS_ERRCNT_12 0x00DC
493#define ixPCIE_PRBS_ERRCNT_13 0x00DD
494#define ixPCIE_PRBS_ERRCNT_14 0x00DE
495#define ixPCIE_PRBS_ERRCNT_15 0x00DF
496#define ixPCIE_PRBS_ERRCNT_2 0x00D2
497#define ixPCIE_PRBS_ERRCNT_3 0x00D3
498#define ixPCIE_PRBS_ERRCNT_4 0x00D4
499#define ixPCIE_PRBS_ERRCNT_5 0x00D5
500#define ixPCIE_PRBS_ERRCNT_6 0x00D6
501#define ixPCIE_PRBS_ERRCNT_7 0x00D7
502#define ixPCIE_PRBS_ERRCNT_8 0x00D8
503#define ixPCIE_PRBS_ERRCNT_9 0x00D9
504#define ixPCIE_PRBS_FREERUN 0x00CB
505#define ixPCIE_PRBS_HI_BITCNT 0x00CF
506#define ixPCIE_PRBS_LO_BITCNT 0x00CE
507#define ixPCIE_PRBS_MISC 0x00CC
508#define ixPCIE_PRBS_STATUS1 0x00C9
509#define ixPCIE_PRBS_STATUS2 0x00CA
510#define ixPCIE_PRBS_USER_PATTERN 0x00CD
511#define ixPCIE_P_RCV_L0S_FTS_DET 0x0050
512#define ixPCIEP_RESERVED 0x0000
513#define ixPCIEP_SCRATCH 0x0001
514#define ixPCIEP_STRAP_LC 0x00C0
515#define ixPCIEP_STRAP_MISC 0x00C1
516#define ixPCIE_RESERVED 0x0000
517#define ixPCIE_RX_CNTL 0x0070
518#define ixPCIE_RX_CNTL2 0x001D
519#define ixPCIE_RX_CNTL3 0x0074
520#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082
521#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081
522#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080
523#define ixPCIE_RX_EXPECTED_SEQNUM 0x0071
524#define ixPCIE_RX_LAST_TLP0 0x0031
525#define ixPCIE_RX_LAST_TLP1 0x0032
526#define ixPCIE_RX_LAST_TLP2 0x0033
527#define ixPCIE_RX_LAST_TLP3 0x0034
528#define ixPCIE_RX_NUM_NAK 0x000E
529#define ixPCIE_RX_NUM_NAK_GENERATED 0x000F
530#define ixPCIE_RX_VENDOR_SPECIFIC 0x0072
531#define ixPCIE_SCRATCH 0x0001
532#define ixPCIE_STRAP_F0 0x00B0
533#define ixPCIE_STRAP_F1 0x00B1
534#define ixPCIE_STRAP_F2 0x00B2
535#define ixPCIE_STRAP_F3 0x00B3
536#define ixPCIE_STRAP_F4 0x00B4
537#define ixPCIE_STRAP_F5 0x00B5
538#define ixPCIE_STRAP_F6 0x00B6
539#define ixPCIE_STRAP_F7 0x00B7
540#define ixPCIE_STRAP_I2C_BD 0x00C4
541#define ixPCIE_STRAP_MISC 0x00C0
542#define ixPCIE_STRAP_MISC2 0x00C1
543#define ixPCIE_STRAP_PI 0x00C2
544#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026
545#define ixPCIE_TX_CNTL 0x0020
546#define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032
547#define ixPCIE_TX_CREDITS_ADVT_NP 0x0031
548#define ixPCIE_TX_CREDITS_ADVT_P 0x0030
549#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037
550#define ixPCIE_TX_CREDITS_INIT_CPL 0x0035
551#define ixPCIE_TX_CREDITS_INIT_NP 0x0034
552#define ixPCIE_TX_CREDITS_INIT_P 0x0033
553#define ixPCIE_TX_CREDITS_STATUS 0x0036
554#define ixPCIE_TX_LAST_TLP0 0x0035
555#define ixPCIE_TX_LAST_TLP1 0x0036
556#define ixPCIE_TX_LAST_TLP2 0x0037
557#define ixPCIE_TX_LAST_TLP3 0x0038
558#define ixPCIE_TX_REPLAY 0x0025
559#define ixPCIE_TX_REQUESTER_ID 0x0021
560#define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023
561#define ixPCIE_TX_SEQ 0x0024
562#define ixPCIE_TX_VENDOR_SPECIFIC 0x0022
563#define ixPCIE_WPR_CNTL 0x0030
564#define mmBACO_CNTL 0x14E5
565#define mmBF_ANA_ISO_CNTL 0x14C7
566#define mmBIF_BACO_DEBUG 0x14DF
567#define mmBIF_BACO_DEBUG_LATCH 0x14DC
568#define mmBIF_BACO_MSIC 0x14DE
569#define mmBIF_BUSNUM_CNTL1 0x1525
570#define mmBIF_BUSNUM_CNTL2 0x152B
571#define mmBIF_BUSNUM_LIST0 0x1526
572#define mmBIF_BUSNUM_LIST1 0x1527
573#define mmBIF_BUSY_DELAY_CNTR 0x1529
574#define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F
575#define mmBIF_DEBUG_CNTL 0x151C
576#define mmBIF_DEBUG_MUX 0x151D
577#define mmBIF_DEBUG_OUT 0x151E
578#define mmBIF_DEVFUNCNUM_LIST0 0x14E8
579#define mmBIF_DEVFUNCNUM_LIST1 0x14E7
580#define mmBIF_FB_EN 0x1524
581#define mmBIF_FEATURES_CONTROL_MISC 0x14C2
582#define mmBIF_PERFCOUNTER0_RESULT 0x152D
583#define mmBIF_PERFCOUNTER1_RESULT 0x152E
584#define mmBIF_PERFMON_CNTL 0x152C
585#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F
586#define mmBIF_RESET_EN 0x1511
587#define mmBIF_SCRATCH0 0x150E
588#define mmBIF_SCRATCH1 0x150F
589#define mmBIF_SSA_DISP_LOWER 0x14D2
590#define mmBIF_SSA_DISP_UPPER 0x14D3
591#define mmBIF_SSA_GFX0_LOWER 0x14CA
592#define mmBIF_SSA_GFX0_UPPER 0x14CB
593#define mmBIF_SSA_GFX1_LOWER 0x14CC
594#define mmBIF_SSA_GFX1_UPPER 0x14CD
595#define mmBIF_SSA_GFX2_LOWER 0x14CE
596#define mmBIF_SSA_GFX2_UPPER 0x14CF
597#define mmBIF_SSA_GFX3_LOWER 0x14D0
598#define mmBIF_SSA_GFX3_UPPER 0x14D1
599#define mmBIF_SSA_MC_LOWER 0x14D4
600#define mmBIF_SSA_MC_UPPER 0x14D5
601#define mmBIF_SSA_PWR_STATUS 0x14C8
602#define mmBIF_XDMA_HI 0x14C1
603#define mmBIF_XDMA_LO 0x14C0
604#define mmBIOS_SCRATCH_0 0x05C9
605#define mmBIOS_SCRATCH_10 0x05D3
606#define mmBIOS_SCRATCH_1 0x05CA
607#define mmBIOS_SCRATCH_11 0x05D4
608#define mmBIOS_SCRATCH_12 0x05D5
609#define mmBIOS_SCRATCH_13 0x05D6
610#define mmBIOS_SCRATCH_14 0x05D7
611#define mmBIOS_SCRATCH_15 0x05D8
612#define mmBIOS_SCRATCH_2 0x05CB
613#define mmBIOS_SCRATCH_3 0x05CC
614#define mmBIOS_SCRATCH_4 0x05CD
615#define mmBIOS_SCRATCH_5 0x05CE
616#define mmBIOS_SCRATCH_6 0x05CF
617#define mmBIOS_SCRATCH_7 0x05D0
618#define mmBIOS_SCRATCH_8 0x05D1
619#define mmBIOS_SCRATCH_9 0x05D2
620#define mmBUS_CNTL 0x1508
621#define mmCAPTURE_HOST_BUSNUM 0x153C
622#define mmCLKREQB_PAD_CNTL 0x1521
623#define mmCONFIG_APER_SIZE 0x150C
624#define mmCONFIG_CNTL 0x1509
625#define mmCONFIG_F0_BASE 0x150B
626#define mmCONFIG_MEMSIZE 0x150A
627#define mmCONFIG_REG_APER_SIZE 0x150D
628#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
629#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
630#define mmHOST_BUSNUM 0x153D
631#define mmHW_DEBUG 0x1515
632#define mmIMPCTL_RESET 0x14F5
633#define mmINTERRUPT_CNTL 0x151A
634#define mmINTERRUPT_CNTL2 0x151B
635#define mmMASTER_CREDIT_CNTL 0x1516
636#define mmMM_CFGREGS_CNTL 0x1513
637#define mmMM_DATA 0x0001
638#define mmMM_INDEX 0x0000
639#define mmMM_INDEX_HI 0x0006
640#define mmNEW_REFCLKB_TIMER 0x14EA
641#define mmNEW_REFCLKB_TIMER_1 0x14E9
642#define mmPCIE_DATA 0x000D
643#define mmPCIE_INDEX 0x000C
644#define mmPEER0_FB_OFFSET_HI 0x14F3
645#define mmPEER0_FB_OFFSET_LO 0x14F2
646#define mmPEER1_FB_OFFSET_HI 0x14F1
647#define mmPEER1_FB_OFFSET_LO 0x14F0
648#define mmPEER2_FB_OFFSET_HI 0x14EF
649#define mmPEER2_FB_OFFSET_LO 0x14EE
650#define mmPEER3_FB_OFFSET_HI 0x14ED
651#define mmPEER3_FB_OFFSET_LO 0x14EC
652#define mmPEER_REG_RANGE0 0x153E
653#define mmPEER_REG_RANGE1 0x153F
654#define mmSLAVE_HANG_ERROR 0x153B
655#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
656#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
657#define mmSMBCLK_PAD_CNTL 0x1523
658#define mmSMBDAT_PAD_CNTL 0x1522
659#define mmSMBUS_BACO_DUMMY 0x14C6
660
661#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h
new file mode 100644
index 000000000000..e94445acf3c6
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h
@@ -0,0 +1,8127 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef BIF_3_0_SH_MASK_H
24#define BIF_3_0_SH_MASK_H
25
26#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30#define BACO_CNTL__BACO_EN_MASK 0x00000001L
31#define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34#define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
36#define BACO_CNTL__BACO_MODE_MASK 0x00000040L
37#define BACO_CNTL__BACO_MODE__SHIFT 0x00000006
38#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
39#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x00000003
40#define BACO_CNTL__BACO_RESET_EN_MASK 0x00000010L
41#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x00000004
42#define BACO_CNTL__PWRGOOD_BF_MASK 0x00000200L
43#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x00000009
44#define BACO_CNTL__PWRGOOD_DVO_MASK 0x00001000L
45#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0x0000000c
46#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x00000400L
47#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0x0000000a
48#define BACO_CNTL__PWRGOOD_MEM_MASK 0x00000800L
49#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0x0000000b
50#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000100L
51#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x00000008
52#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x00000001L
53#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x00000000
54#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x00000002L
55#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x00000001
56#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x00000001L
57#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x00000000
58#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x00000001L
59#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x00000000
60#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x00000001L
61#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x00000000
62#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL
63#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000
64#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
65#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008
66#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL
67#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000
68#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
69#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011
70#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
71#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010
72#define BIF_BUSNUM_LIST0__ID0_MASK 0x000000ffL
73#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x00000000
74#define BIF_BUSNUM_LIST0__ID1_MASK 0x0000ff00L
75#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x00000008
76#define BIF_BUSNUM_LIST0__ID2_MASK 0x00ff0000L
77#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x00000010
78#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000L
79#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x00000018
80#define BIF_BUSNUM_LIST1__ID4_MASK 0x000000ffL
81#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x00000000
82#define BIF_BUSNUM_LIST1__ID5_MASK 0x0000ff00L
83#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x00000008
84#define BIF_BUSNUM_LIST1__ID6_MASK 0x00ff0000L
85#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x00000010
86#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000L
87#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x00000018
88#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL
89#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000
90#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x000003ffL
91#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x00000000
92#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x00000010L
93#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x00000004
94#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x00000020L
95#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x00000005
96#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x00000001L
97#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x00000000
98#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x00001f00L
99#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x00000008
100#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x001f0000L
101#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x00000010
102#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x01000000L
103#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x00000018
104#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x00000002L
105#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x00000001
106#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x00000004L
107#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x00000002
108#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x00000008L
109#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x00000003
110#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x00000080L
111#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x00000007
112#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000L
113#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x0000001e
114#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x00000040L
115#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x00000006
116#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x0000003fL
117#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x00000000
118#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x00003f00L
119#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x00000008
120#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x0001ffffL
121#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x00000000
122#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000ffL
123#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x00000000
124#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000ff00L
125#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x00000008
126#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00ff0000L
127#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x00000010
128#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000L
129#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x00000018
130#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000ffL
131#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x00000000
132#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000ff00L
133#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x00000008
134#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00ff0000L
135#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x00000010
136#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000L
137#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x00000018
138#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
139#define BIF_FB_EN__FB_READ_EN__SHIFT 0x00000000
140#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
141#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x00000001
142#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
143#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x00000003
144#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
145#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x00000002
146#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x00000100L
147#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x00000008
148#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
149#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x00000000
150#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x00000080L
151#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x00000007
152#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L
153#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x00000005
154#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L
155#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x00000006
156#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
157#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x00000001
158#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L
159#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x00000004
160#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL
161#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000
162#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL
163#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000
164#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x00000001L
165#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x00000000
166#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x00000002L
167#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x00000001
168#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x00000004L
169#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x00000002
170#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x00001f00L
171#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000008
172#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x0003e000L
173#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000d
174#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x00000007L
175#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x00000000
176#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x00000038L
177#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x00000003
178#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x000003c0L
179#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x00000006
180#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x00400000L
181#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x00000016
182#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x00000040L
183#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x00000006
184#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x0003f000L
185#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0x0000000c
186#define BIF_RESET_EN__COR_RESET_EN_MASK 0x00000008L
187#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x00000003
188#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0x000c0000L
189#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x00000012
190#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x00000080L
191#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x00000007
192#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x00800000L
193#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x00000017
194#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0x0c000000L
195#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x0000001a
196#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x01000000L
197#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x00000018
198#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000L
199#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x0000001c
200#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x02000000L
201#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x00000019
202#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000L
203#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x0000001e
204#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x00000200L
205#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x00000009
206#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x00000400L
207#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0x0000000a
208#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x00000800L
209#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0x0000000b
210#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x00000004L
211#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x00000002
212#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x00100000L
213#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x00000014
214#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x00200000L
215#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x00000015
216#define BIF_RESET_EN__REG_RESET_EN_MASK 0x00000010L
217#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x00000004
218#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x00000100L
219#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x00000008
220#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x00000002L
221#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x00000001
222#define BIF_RESET_EN__STY_RESET_EN_MASK 0x00000020L
223#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x00000005
224#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffffL
225#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x00000000
226#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffffL
227#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x00000000
228#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x0003fffcL
229#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x00000002
230#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000L
231#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x0000001e
232#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000L
233#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x0000001f
234#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x0003fffcL
235#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x00000002
236#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x0003fffcL
237#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x00000002
238#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000L
239#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x0000001e
240#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000L
241#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x0000001f
242#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x0003fffcL
243#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x00000002
244#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x0003fffcL
245#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x00000002
246#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000L
247#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x0000001e
248#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000L
249#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x0000001f
250#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x0003fffcL
251#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x00000002
252#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x0003fffcL
253#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x00000002
254#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000L
255#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x0000001e
256#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000L
257#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x0000001f
258#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x0003fffcL
259#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x00000002
260#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x0003fffcL
261#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x00000002
262#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000L
263#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x0000001e
264#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000L
265#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x0000001f
266#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x0003fffcL
267#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x00000002
268#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000L
269#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x0000001d
270#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x0003fffcL
271#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x00000002
272#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000L
273#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x0000001e
274#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000L
275#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x0000001f
276#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x0003fffcL
277#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x00000002
278#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x00000002L
279#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x00000001
280#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x00000001L
281#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x00000000
282#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x00000004L
283#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x00000002
284#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffffL
285#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x00000000
286#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
287#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x0000001f
288#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffffL
289#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x00000000
290#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffffL
291#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x00000000
292#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffffL
293#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x00000000
294#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffffL
295#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x00000000
296#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffffL
297#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x00000000
298#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffffL
299#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x00000000
300#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffffL
301#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x00000000
302#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffffL
303#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x00000000
304#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffffL
305#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x00000000
306#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffffL
307#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x00000000
308#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffffL
309#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x00000000
310#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffffL
311#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x00000000
312#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffffL
313#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x00000000
314#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffffL
315#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x00000000
316#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffffL
317#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x00000000
318#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffffL
319#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x00000000
320#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffffL
321#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x00000000
322#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x00000100L
323#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x00000008
324#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x00000002L
325#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x00000001
326#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x00000001L
327#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x00000000
328#define BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
329#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x00000004
330#define BUS_CNTL__PMI_INT_DIS_MASK 0x00000020L
331#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000005
332#define BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
333#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x00000002
334#define BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
335#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x00000003
336#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
337#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x00000012
338#define BUS_CNTL__SET_AZ_TC_MASK 0x00001c00L
339#define BUS_CNTL__SET_AZ_TC__SHIFT 0x0000000a
340#define BUS_CNTL__SET_MC_TC_MASK 0x0000e000L
341#define BUS_CNTL__SET_MC_TC__SHIFT 0x0000000d
342#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
343#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x00000007
344#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
345#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x00000006
346#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
347#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x00000011
348#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
349#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x00000010
350#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
351#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x00000000
352#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
353#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x00000000
354#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
355#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0x0000000c
356#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
357#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x00000002
358#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
359#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0x0000000b
360#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
361#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x00000001
362#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
363#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x00000009
364#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
365#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x00000005
366#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
367#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x00000006
368#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
369#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x00000007
370#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
371#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x00000008
372#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
373#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x00000003
374#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
375#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0x0000000a
376#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffffL
377#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x00000000
378#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
379#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x00000000
380#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
381#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x00000002
382#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
383#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x00000003
384#define CONFIG_CNTL__VGA_DIS_MASK 0x00000002L
385#define CONFIG_CNTL__VGA_DIS__SHIFT 0x00000001
386#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffffL
387#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x00000000
388#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffffL
389#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x00000000
390#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000fffffL
391#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x00000000
392#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
393#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x00000000
394#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
395#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x00000000
396#define HOST_BUSNUM__HOST_ID_MASK 0x0000ffffL
397#define HOST_BUSNUM__HOST_ID__SHIFT 0x00000000
398#define HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L
399#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000
400#define HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L
401#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001
402#define HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L
403#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002
404#define HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L
405#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003
406#define HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L
407#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004
408#define HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L
409#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005
410#define HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L
411#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006
412#define HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L
413#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007
414#define HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L
415#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008
416#define HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L
417#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009
418#define HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L
419#define HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a
420#define HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L
421#define HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b
422#define HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L
423#define HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c
424#define HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L
425#define HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d
426#define HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L
427#define HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e
428#define HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L
429#define HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f
430#define HW_DEBUG__HW_16_DEBUG_MASK 0x00010000L
431#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x00000010
432#define HW_DEBUG__HW_17_DEBUG_MASK 0x00020000L
433#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x00000011
434#define HW_DEBUG__HW_18_DEBUG_MASK 0x00040000L
435#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x00000012
436#define HW_DEBUG__HW_19_DEBUG_MASK 0x00080000L
437#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x00000013
438#define HW_DEBUG__HW_20_DEBUG_MASK 0x00100000L
439#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x00000014
440#define HW_DEBUG__HW_21_DEBUG_MASK 0x00200000L
441#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x00000015
442#define HW_DEBUG__HW_22_DEBUG_MASK 0x00400000L
443#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x00000016
444#define HW_DEBUG__HW_23_DEBUG_MASK 0x00800000L
445#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x00000017
446#define HW_DEBUG__HW_24_DEBUG_MASK 0x01000000L
447#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x00000018
448#define HW_DEBUG__HW_25_DEBUG_MASK 0x02000000L
449#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x00000019
450#define HW_DEBUG__HW_26_DEBUG_MASK 0x04000000L
451#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x0000001a
452#define HW_DEBUG__HW_27_DEBUG_MASK 0x08000000L
453#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x0000001b
454#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000L
455#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x0000001c
456#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000L
457#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x0000001d
458#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000L
459#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x0000001e
460#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000L
461#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x0000001f
462#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x00000001L
463#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x00000000
464#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffffL
465#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x00000000
466#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x00001e00L
467#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x00000009
468#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
469#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x00000008
470#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
471#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x00000001
472#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
473#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x00000000
474#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000f0L
475#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x00000004
476#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
477#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x00000003
478#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x00006000L
479#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0x0000000d
480#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x003f0000L
481#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x00000010
482#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x0000003fL
483#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x00000000
484#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
485#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x00000000
486#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x00000008L
487#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x00000003
488#define MM_DATA__MM_DATA_MASK 0xffffffffL
489#define MM_DATA__MM_DATA__SHIFT 0x00000000
490#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffffL
491#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x00000000
492#define MM_INDEX__MM_APER_MASK 0x80000000L
493#define MM_INDEX__MM_APER__SHIFT 0x0000001f
494#define MM_INDEX__MM_OFFSET_MASK 0x7fffffffL
495#define MM_INDEX__MM_OFFSET__SHIFT 0x00000000
496#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x000003ffL
497#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x00000000
498#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x00000400L
499#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0x0000000a
500#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x00200000L
501#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x00000015
502#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x00000001L
503#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x00000000
504#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x001ffffeL
505#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x00000001
506#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L
507#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000
508#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL
509#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001
510#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L
511#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008
512#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L
513#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017
514#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L
515#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016
516#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL
517#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000
518#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L
519#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018
520#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L
521#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010
522#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L
523#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008
524#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL
525#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000
526#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL
527#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000
528#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL
529#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000
530#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L
531#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010
532#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L
533#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014
534#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L
535#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017
536#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L
537#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018
538#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L
539#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019
540#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L
541#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a
542#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L
543#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e
544#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L
545#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f
546#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L
547#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000
548#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL
549#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001
550#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L
551#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007
552#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L
553#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008
554#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L
555#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e
556#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L
557#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f
558#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L
559#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016
560#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L
561#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017
562#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L
563#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e
564#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L
565#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000
566#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL
567#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001
568#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L
569#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008
570#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L
571#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009
572#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L
573#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010
574#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L
575#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011
576#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L
577#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018
578#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L
579#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019
580#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L
581#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005
582#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L
583#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007
584#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L
585#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009
586#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L
587#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e
588#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L
589#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c
590#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L
591#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b
592#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L
593#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012
594#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L
595#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f
596#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L
597#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016
598#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L
599#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017
600#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L
601#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b
602#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L
603#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c
604#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L
605#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015
606#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL
607#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000
608#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L
609#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016
610#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL
611#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000
612#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L
613#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012
614#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L
615#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010
616#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L
617#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a
618#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L
619#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c
620#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L
621#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b
622#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL
623#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000
624#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL
625#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000
626#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L
627#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010
628#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L
629#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f
630#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L
631#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010
632#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L
633#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002
634#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L
635#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003
636#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L
637#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000
638#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L
639#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001
640#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L
641#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000
642#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L
643#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001
644#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L
645#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000
646#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L
647#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003
648#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L
649#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001
650#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L
651#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002
652#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L
653#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004
654#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L
655#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014
656#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L
657#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010
658#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L
659#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008
660#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L
661#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c
662#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L
663#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c
664#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L
665#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d
666#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L
667#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e
668#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L
669#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f
670#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L
671#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012
672#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L
673#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016
674#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L
675#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a
676#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L
677#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e
678#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L
679#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002
680#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L
681#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001
682#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L
683#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000
684#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L
685#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010
686#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L
687#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014
688#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L
689#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018
690#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L
691#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c
692#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L
693#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c
694#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L
695#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d
696#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L
697#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e
698#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L
699#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f
700#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L
701#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012
702#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L
703#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016
704#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L
705#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a
706#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L
707#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e
708#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L
709#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002
710#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L
711#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001
712#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L
713#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000
714#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L
715#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010
716#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L
717#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014
718#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L
719#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018
720#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L
721#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c
722#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L
723#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e
724#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L
725#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f
726#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L
727#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c
728#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L
729#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d
730#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L
731#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a
732#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L
733#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e
734#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L
735#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012
736#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L
737#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016
738#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L
739#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002
740#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L
741#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001
742#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L
743#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000
744#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L
745#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018
746#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L
747#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c
748#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L
749#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010
750#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L
751#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014
752#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L
753#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c
754#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L
755#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d
756#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L
757#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e
758#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L
759#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f
760#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L
761#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012
762#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L
763#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016
764#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L
765#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a
766#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L
767#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e
768#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L
769#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002
770#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L
771#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001
772#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L
773#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000
774#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L
775#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010
776#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L
777#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014
778#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L
779#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018
780#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L
781#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c
782#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x00000001L
783#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x00000000
784#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x00000002L
785#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x00000001
786#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x00000004L
787#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x00000002
788#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x00000008L
789#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x00000003
790#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x00000010L
791#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x00000004
792#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x00000020L
793#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x00000005
794#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x00000040L
795#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x00000006
796#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x00000080L
797#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x00000007
798#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x00000100L
799#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x00000008
800#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x00000200L
801#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x00000009
802#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x00000400L
803#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0x0000000a
804#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x00000800L
805#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0x0000000b
806#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x00001000L
807#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0x0000000c
808#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x00002000L
809#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0x0000000d
810#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x00004000L
811#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0x0000000e
812#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x00008000L
813#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0x0000000f
814#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x00010000L
815#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x00000010
816#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x00020000L
817#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x00000011
818#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x00040000L
819#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x00000012
820#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x00080000L
821#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x00000013
822#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x00100000L
823#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x00000014
824#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x00200000L
825#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x00000015
826#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x00400000L
827#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x00000016
828#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x00800000L
829#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x00000017
830#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x01000000L
831#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x00000018
832#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x02000000L
833#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x00000019
834#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x04000000L
835#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x0000001a
836#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x08000000L
837#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x0000001b
838#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000L
839#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x0000001c
840#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000L
841#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x0000001d
842#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000L
843#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x0000001e
844#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000L
845#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x0000001f
846#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L
847#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007
848#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L
849#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008
850#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L
851#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012
852#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L
853#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013
854#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L
855#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014
856#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L
857#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015
858#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L
859#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016
860#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L
861#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017
862#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L
863#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009
864#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L
865#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a
866#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L
867#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b
868#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L
869#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c
870#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L
871#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d
872#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L
873#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e
874#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L
875#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f
876#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L
877#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010
878#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L
879#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011
880#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L
881#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001
882#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L
883#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018
884#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L
885#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001
886#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L
887#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005
888#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L
889#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009
890#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L
891#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d
892#define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L
893#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008
894#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L
895#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014
896#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L
897#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004
898#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L
899#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017
900#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L
901#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c
902#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L
903#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d
904#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L
905#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011
906#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L
907#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003
908#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L
909#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002
910#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L
911#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a
912#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L
913#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006
914#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L
915#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007
916#define PB0_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L
917#define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018
918#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L
919#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b
920#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L
921#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000
922#define PB0_PIF_CNTL__TXGND_TIME_MASK 0x00010000L
923#define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010
924#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x00000001L
925#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x00000000
926#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x00000002L
927#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x00000001
928#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x00000004L
929#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x00000002
930#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x00000008L
931#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x00000003
932#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x00000010L
933#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x00000004
934#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x00000020L
935#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x00000005
936#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x00000040L
937#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x00000006
938#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x00000080L
939#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x00000007
940#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x00000100L
941#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x00000008
942#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x00000200L
943#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x00000009
944#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x00000400L
945#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0x0000000a
946#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x00000800L
947#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0x0000000b
948#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x00001000L
949#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0x0000000c
950#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x00002000L
951#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0x0000000d
952#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x00004000L
953#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0x0000000e
954#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x00008000L
955#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0x0000000f
956#define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L
957#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019
958#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L
959#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014
960#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L
961#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000
962#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L
963#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005
964#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L
965#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006
966#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L
967#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007
968#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L
969#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001
970#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L
971#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002
972#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L
973#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003
974#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L
975#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004
976#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L
977#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a
978#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L
979#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b
980#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L
981#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008
982#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L
983#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009
984#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L
985#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011
986#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L
987#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010
988#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L
989#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008
990#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L
991#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009
992#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L
993#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004
994#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L
995#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005
996#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L
997#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e
998#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L
999#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f
1000#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L
1001#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000
1002#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL
1003#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001
1004#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L
1005#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a
1006#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L
1007#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b
1008#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L
1009#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008
1010#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L
1011#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009
1012#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L
1013#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004
1014#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L
1015#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005
1016#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L
1017#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e
1018#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L
1019#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f
1020#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L
1021#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000
1022#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL
1023#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001
1024#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L
1025#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a
1026#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L
1027#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b
1028#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L
1029#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008
1030#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L
1031#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009
1032#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L
1033#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004
1034#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L
1035#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005
1036#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L
1037#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e
1038#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L
1039#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f
1040#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L
1041#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000
1042#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL
1043#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001
1044#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L
1045#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a
1046#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L
1047#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b
1048#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L
1049#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008
1050#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L
1051#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009
1052#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L
1053#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004
1054#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L
1055#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005
1056#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L
1057#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e
1058#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L
1059#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f
1060#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L
1061#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000
1062#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL
1063#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001
1064#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L
1065#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a
1066#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L
1067#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b
1068#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L
1069#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008
1070#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L
1071#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009
1072#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L
1073#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004
1074#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L
1075#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005
1076#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L
1077#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e
1078#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L
1079#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f
1080#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L
1081#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000
1082#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL
1083#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001
1084#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L
1085#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a
1086#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L
1087#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b
1088#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L
1089#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008
1090#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L
1091#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009
1092#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L
1093#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004
1094#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L
1095#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005
1096#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L
1097#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e
1098#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L
1099#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f
1100#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L
1101#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000
1102#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL
1103#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001
1104#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L
1105#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a
1106#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L
1107#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b
1108#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L
1109#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008
1110#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L
1111#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009
1112#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L
1113#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004
1114#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L
1115#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005
1116#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L
1117#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e
1118#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L
1119#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f
1120#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L
1121#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000
1122#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL
1123#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001
1124#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L
1125#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a
1126#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L
1127#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b
1128#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L
1129#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008
1130#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L
1131#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009
1132#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L
1133#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004
1134#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L
1135#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005
1136#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L
1137#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e
1138#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L
1139#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f
1140#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L
1141#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000
1142#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL
1143#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001
1144#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L
1145#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a
1146#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L
1147#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b
1148#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L
1149#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008
1150#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L
1151#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009
1152#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L
1153#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004
1154#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L
1155#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005
1156#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L
1157#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e
1158#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L
1159#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f
1160#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L
1161#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000
1162#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL
1163#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001
1164#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L
1165#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a
1166#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L
1167#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b
1168#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L
1169#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008
1170#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L
1171#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009
1172#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L
1173#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004
1174#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L
1175#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005
1176#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L
1177#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e
1178#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L
1179#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f
1180#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L
1181#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000
1182#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL
1183#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001
1184#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L
1185#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a
1186#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L
1187#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b
1188#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L
1189#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008
1190#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L
1191#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009
1192#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L
1193#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004
1194#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L
1195#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005
1196#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L
1197#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e
1198#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L
1199#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f
1200#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L
1201#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000
1202#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL
1203#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001
1204#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L
1205#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a
1206#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L
1207#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b
1208#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L
1209#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008
1210#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L
1211#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009
1212#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L
1213#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004
1214#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L
1215#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005
1216#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L
1217#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e
1218#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L
1219#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f
1220#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L
1221#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000
1222#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL
1223#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001
1224#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L
1225#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a
1226#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L
1227#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b
1228#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L
1229#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008
1230#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L
1231#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009
1232#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L
1233#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004
1234#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L
1235#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005
1236#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L
1237#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e
1238#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L
1239#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f
1240#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L
1241#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000
1242#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL
1243#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001
1244#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L
1245#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a
1246#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L
1247#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b
1248#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L
1249#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008
1250#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L
1251#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009
1252#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L
1253#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004
1254#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L
1255#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005
1256#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L
1257#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e
1258#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L
1259#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f
1260#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L
1261#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000
1262#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL
1263#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001
1264#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L
1265#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a
1266#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L
1267#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b
1268#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L
1269#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008
1270#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L
1271#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009
1272#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L
1273#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004
1274#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L
1275#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005
1276#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L
1277#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e
1278#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L
1279#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f
1280#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L
1281#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000
1282#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL
1283#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001
1284#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L
1285#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a
1286#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L
1287#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b
1288#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L
1289#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008
1290#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L
1291#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009
1292#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L
1293#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004
1294#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L
1295#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005
1296#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L
1297#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e
1298#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L
1299#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f
1300#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L
1301#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000
1302#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL
1303#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001
1304#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L
1305#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a
1306#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L
1307#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b
1308#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L
1309#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003
1310#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L
1311#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a
1312#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L
1313#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007
1314#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L
1315#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c
1316#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L
1317#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d
1318#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L
1319#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018
1320#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L
1321#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004
1322#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L
1323#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010
1324#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L
1325#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000
1326#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L
1327#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003
1328#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L
1329#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a
1330#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L
1331#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007
1332#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L
1333#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c
1334#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L
1335#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d
1336#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L
1337#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018
1338#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L
1339#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004
1340#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L
1341#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010
1342#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L
1343#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000
1344#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L
1345#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003
1346#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L
1347#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a
1348#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L
1349#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007
1350#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L
1351#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c
1352#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L
1353#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d
1354#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L
1355#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018
1356#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L
1357#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004
1358#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L
1359#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010
1360#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L
1361#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000
1362#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L
1363#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003
1364#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L
1365#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a
1366#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L
1367#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007
1368#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L
1369#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c
1370#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L
1371#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d
1372#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L
1373#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018
1374#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L
1375#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004
1376#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L
1377#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010
1378#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L
1379#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000
1380#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L
1381#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000
1382#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L
1383#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005
1384#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L
1385#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004
1386#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L
1387#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003
1388#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L
1389#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002
1390#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L
1391#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010
1392#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L
1393#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a
1394#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L
1395#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b
1396#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L
1397#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c
1398#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L
1399#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d
1400#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L
1401#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e
1402#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L
1403#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f
1404#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L
1405#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011
1406#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L
1407#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012
1408#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L
1409#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013
1410#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L
1411#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014
1412#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L
1413#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015
1414#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L
1415#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016
1416#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L
1417#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017
1418#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L
1419#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018
1420#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L
1421#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019
1422#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L
1423#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008
1424#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L
1425#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009
1426#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L
1427#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a
1428#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L
1429#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b
1430#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L
1431#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c
1432#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L
1433#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d
1434#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L
1435#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e
1436#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L
1437#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f
1438#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L
1439#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001
1440#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L
1441#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006
1442#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL
1443#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000
1444#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L
1445#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000
1446#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L
1447#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005
1448#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L
1449#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004
1450#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L
1451#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003
1452#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L
1453#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002
1454#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L
1455#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008
1456#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L
1457#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001
1458#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L
1459#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006
1460#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L
1461#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000
1462#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L
1463#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005
1464#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L
1465#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004
1466#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L
1467#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003
1468#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L
1469#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002
1470#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L
1471#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008
1472#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L
1473#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001
1474#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L
1475#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006
1476#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L
1477#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000
1478#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L
1479#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005
1480#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L
1481#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004
1482#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L
1483#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003
1484#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L
1485#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002
1486#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L
1487#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008
1488#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L
1489#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001
1490#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L
1491#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006
1492#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L
1493#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000
1494#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L
1495#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005
1496#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L
1497#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004
1498#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L
1499#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003
1500#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L
1501#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002
1502#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L
1503#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008
1504#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L
1505#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001
1506#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L
1507#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006
1508#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L
1509#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000
1510#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L
1511#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005
1512#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L
1513#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004
1514#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L
1515#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003
1516#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L
1517#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002
1518#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L
1519#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008
1520#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L
1521#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001
1522#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L
1523#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006
1524#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L
1525#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000
1526#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L
1527#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005
1528#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L
1529#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004
1530#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L
1531#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003
1532#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L
1533#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002
1534#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L
1535#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008
1536#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L
1537#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001
1538#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L
1539#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006
1540#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L
1541#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000
1542#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L
1543#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005
1544#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L
1545#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004
1546#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L
1547#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003
1548#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L
1549#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002
1550#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L
1551#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008
1552#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L
1553#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001
1554#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L
1555#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006
1556#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L
1557#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000
1558#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L
1559#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005
1560#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L
1561#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004
1562#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L
1563#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003
1564#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L
1565#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002
1566#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L
1567#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008
1568#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L
1569#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001
1570#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L
1571#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006
1572#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L
1573#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000
1574#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L
1575#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005
1576#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L
1577#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004
1578#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L
1579#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003
1580#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L
1581#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002
1582#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L
1583#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008
1584#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L
1585#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001
1586#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L
1587#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006
1588#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L
1589#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000
1590#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L
1591#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005
1592#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L
1593#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004
1594#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L
1595#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003
1596#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L
1597#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002
1598#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L
1599#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008
1600#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L
1601#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001
1602#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L
1603#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006
1604#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L
1605#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000
1606#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L
1607#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005
1608#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L
1609#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004
1610#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L
1611#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003
1612#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L
1613#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002
1614#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L
1615#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008
1616#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L
1617#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001
1618#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L
1619#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006
1620#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L
1621#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000
1622#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L
1623#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005
1624#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L
1625#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004
1626#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L
1627#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003
1628#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L
1629#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002
1630#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L
1631#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008
1632#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L
1633#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001
1634#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L
1635#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006
1636#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L
1637#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000
1638#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L
1639#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005
1640#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L
1641#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004
1642#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L
1643#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003
1644#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L
1645#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002
1646#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L
1647#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008
1648#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L
1649#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001
1650#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L
1651#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006
1652#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L
1653#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000
1654#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L
1655#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005
1656#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L
1657#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004
1658#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L
1659#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003
1660#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L
1661#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002
1662#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L
1663#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008
1664#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L
1665#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001
1666#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L
1667#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006
1668#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L
1669#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000
1670#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L
1671#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005
1672#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L
1673#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004
1674#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L
1675#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003
1676#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L
1677#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002
1678#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L
1679#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008
1680#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L
1681#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001
1682#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L
1683#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006
1684#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L
1685#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000
1686#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L
1687#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005
1688#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L
1689#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004
1690#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L
1691#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003
1692#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L
1693#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002
1694#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L
1695#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008
1696#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L
1697#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001
1698#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L
1699#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006
1700#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L
1701#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000
1702#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L
1703#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a
1704#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L
1705#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b
1706#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L
1707#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c
1708#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L
1709#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d
1710#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L
1711#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e
1712#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L
1713#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f
1714#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L
1715#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001
1716#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L
1717#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002
1718#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L
1719#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003
1720#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L
1721#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004
1722#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L
1723#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005
1724#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L
1725#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006
1726#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L
1727#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007
1728#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L
1729#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008
1730#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L
1731#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009
1732#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L
1733#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000
1734#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L
1735#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002
1736#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L
1737#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003
1738#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L
1739#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004
1740#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L
1741#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003
1742#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L
1743#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000
1744#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L
1745#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007
1746#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L
1747#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004
1748#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L
1749#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009
1750#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L
1751#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008
1752#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L
1753#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012
1754#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L
1755#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a
1756#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L
1757#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c
1758#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L
1759#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013
1760#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L
1761#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f
1762#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L
1763#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d
1764#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L
1765#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003
1766#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L
1767#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000
1768#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L
1769#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012
1770#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L
1771#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e
1772#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L
1773#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005
1774#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L
1775#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004
1776#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L
1777#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007
1778#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L
1779#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006
1780#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L
1781#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009
1782#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L
1783#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008
1784#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L
1785#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008
1786#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1787#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1788#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1789#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1790#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L
1791#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004
1792#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L
1793#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008
1794#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1795#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1796#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1797#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1798#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L
1799#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004
1800#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L
1801#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008
1802#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1803#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1804#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1805#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1806#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L
1807#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004
1808#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L
1809#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008
1810#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1811#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1812#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1813#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1814#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L
1815#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004
1816#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L
1817#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000
1818#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L
1819#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002
1820#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L
1821#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004
1822#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L
1823#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003
1824#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L
1825#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b
1826#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L
1827#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008
1828#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL
1829#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000
1830#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L
1831#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c
1832#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L
1833#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009
1834#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L
1835#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e
1836#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L
1837#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d
1838#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L
1839#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c
1840#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L
1841#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f
1842#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L
1843#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f
1844#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L
1845#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e
1846#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L
1847#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016
1848#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L
1849#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013
1850#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L
1851#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005
1852#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL
1853#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000
1854#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L
1855#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008
1856#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L
1857#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006
1858#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L
1859#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a
1860#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L
1861#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009
1862#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L
1863#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c
1864#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L
1865#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b
1866#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L
1867#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e
1868#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L
1869#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d
1870#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L
1871#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008
1872#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1873#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1874#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1875#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1876#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L
1877#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004
1878#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L
1879#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008
1880#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1881#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1882#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1883#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1884#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L
1885#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004
1886#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L
1887#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008
1888#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1889#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1890#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1891#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1892#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L
1893#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004
1894#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L
1895#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008
1896#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
1897#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
1898#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
1899#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
1900#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L
1901#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004
1902#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L
1903#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009
1904#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L
1905#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a
1906#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L
1907#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b
1908#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L
1909#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014
1910#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L
1911#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015
1912#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L
1913#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c
1914#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L
1915#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d
1916#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L
1917#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e
1918#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L
1919#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016
1920#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L
1921#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017
1922#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L
1923#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008
1924#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L
1925#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001
1926#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L
1927#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002
1928#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L
1929#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003
1930#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L
1931#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010
1932#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L
1933#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011
1934#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L
1935#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004
1936#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L
1937#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005
1938#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L
1939#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006
1940#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L
1941#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012
1942#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L
1943#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013
1944#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L
1945#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007
1946#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L
1947#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000
1948#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL
1949#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000
1950#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L
1951#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a
1952#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L
1953#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014
1954#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L
1955#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e
1956#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L
1957#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e
1958#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL
1959#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000
1960#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L
1961#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004
1962#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L
1963#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008
1964#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L
1965#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c
1966#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L
1967#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010
1968#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L
1969#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014
1970#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L
1971#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018
1972#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L
1973#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019
1974#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L
1975#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a
1976#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L
1977#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b
1978#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L
1979#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c
1980#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L
1981#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d
1982#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L
1983#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c
1984#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L
1985#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010
1986#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L
1987#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014
1988#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L
1989#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018
1990#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L
1991#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a
1992#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L
1993#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c
1994#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L
1995#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e
1996#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L
1997#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000
1998#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L
1999#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001
2000#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L
2001#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002
2002#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L
2003#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014
2004#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L
2005#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018
2006#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L
2007#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c
2008#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L
2009#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000
2010#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L
2011#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003
2012#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L
2013#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006
2014#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L
2015#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014
2016#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L
2017#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018
2018#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L
2019#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c
2020#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L
2021#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009
2022#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L
2023#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c
2024#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L
2025#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f
2026#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL
2027#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000
2028#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L
2029#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005
2030#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L
2031#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a
2032#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L
2033#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f
2034#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L
2035#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010
2036#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L
2037#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011
2038#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L
2039#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012
2040#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L
2041#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013
2042#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L
2043#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014
2044#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L
2045#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b
2046#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L
2047#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c
2048#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L
2049#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d
2050#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L
2051#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e
2052#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L
2053#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b
2054#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL
2055#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000
2056#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L
2057#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004
2058#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L
2059#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008
2060#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L
2061#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c
2062#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L
2063#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010
2064#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L
2065#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014
2066#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L
2067#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018
2068#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L
2069#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a
2070#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L
2071#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012
2072#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L
2073#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015
2074#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L
2075#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018
2076#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L
2077#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b
2078#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L
2079#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c
2080#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L
2081#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d
2082#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL
2083#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000
2084#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L
2085#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004
2086#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L
2087#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008
2088#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L
2089#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c
2090#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L
2091#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d
2092#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L
2093#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011
2094#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L
2095#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f
2096#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L
2097#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e
2098#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L
2099#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001
2100#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L
2101#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000
2102#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L
2103#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003
2104#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L
2105#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002
2106#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L
2107#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d
2108#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L
2109#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c
2110#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L
2111#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008
2112#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L
2113#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006
2114#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L
2115#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a
2116#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L
2117#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009
2118#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L
2119#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c
2120#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L
2121#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b
2122#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L
2123#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e
2124#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L
2125#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d
2126#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L
2127#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010
2128#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L
2129#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f
2130#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L
2131#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012
2132#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L
2133#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011
2134#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L
2135#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014
2136#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L
2137#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013
2138#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L
2139#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016
2140#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L
2141#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015
2142#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L
2143#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018
2144#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L
2145#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017
2146#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L
2147#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001
2148#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L
2149#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000
2150#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L
2151#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004
2152#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L
2153#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007
2154#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L
2155#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005
2156#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L
2157#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006
2158#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L
2159#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c
2160#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L
2161#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f
2162#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L
2163#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d
2164#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L
2165#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e
2166#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L
2167#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010
2168#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L
2169#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013
2170#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L
2171#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011
2172#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L
2173#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012
2174#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L
2175#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014
2176#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L
2177#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017
2178#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L
2179#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015
2180#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L
2181#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016
2182#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L
2183#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008
2184#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L
2185#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b
2186#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L
2187#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009
2188#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L
2189#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a
2190#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L
2191#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000
2192#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L
2193#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003
2194#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L
2195#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001
2196#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L
2197#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002
2198#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL
2199#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000
2200#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L
2201#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d
2202#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L
2203#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a
2204#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L
2205#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c
2206#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L
2207#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003
2208#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L
2209#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007
2210#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L
2211#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008
2212#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L
2213#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009
2214#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L
2215#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004
2216#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L
2217#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000
2218#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL
2219#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000
2220#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L
2221#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d
2222#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L
2223#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a
2224#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L
2225#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c
2226#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L
2227#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003
2228#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L
2229#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007
2230#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L
2231#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008
2232#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L
2233#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009
2234#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L
2235#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004
2236#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L
2237#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000
2238#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL
2239#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000
2240#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L
2241#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d
2242#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L
2243#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a
2244#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L
2245#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c
2246#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L
2247#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003
2248#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L
2249#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007
2250#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L
2251#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008
2252#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L
2253#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009
2254#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L
2255#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004
2256#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L
2257#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000
2258#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL
2259#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000
2260#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L
2261#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d
2262#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L
2263#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a
2264#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L
2265#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c
2266#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L
2267#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003
2268#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L
2269#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007
2270#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L
2271#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008
2272#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L
2273#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009
2274#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L
2275#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004
2276#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L
2277#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000
2278#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL
2279#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000
2280#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L
2281#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d
2282#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L
2283#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a
2284#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L
2285#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c
2286#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L
2287#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003
2288#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L
2289#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007
2290#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L
2291#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008
2292#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L
2293#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009
2294#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L
2295#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004
2296#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L
2297#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000
2298#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL
2299#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000
2300#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L
2301#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d
2302#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L
2303#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a
2304#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L
2305#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c
2306#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L
2307#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003
2308#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L
2309#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007
2310#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L
2311#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008
2312#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L
2313#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009
2314#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L
2315#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004
2316#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L
2317#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000
2318#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL
2319#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000
2320#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L
2321#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d
2322#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L
2323#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a
2324#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L
2325#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c
2326#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L
2327#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003
2328#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L
2329#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007
2330#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L
2331#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008
2332#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L
2333#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009
2334#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L
2335#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004
2336#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L
2337#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000
2338#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL
2339#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000
2340#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L
2341#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d
2342#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L
2343#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a
2344#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L
2345#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c
2346#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L
2347#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003
2348#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L
2349#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007
2350#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L
2351#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008
2352#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L
2353#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009
2354#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L
2355#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004
2356#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L
2357#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000
2358#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL
2359#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000
2360#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L
2361#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d
2362#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L
2363#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a
2364#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L
2365#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c
2366#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L
2367#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003
2368#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L
2369#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007
2370#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L
2371#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008
2372#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L
2373#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009
2374#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L
2375#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004
2376#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L
2377#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000
2378#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL
2379#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000
2380#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L
2381#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d
2382#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L
2383#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a
2384#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L
2385#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c
2386#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L
2387#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003
2388#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L
2389#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007
2390#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L
2391#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008
2392#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L
2393#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009
2394#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L
2395#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004
2396#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L
2397#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000
2398#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL
2399#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000
2400#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L
2401#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d
2402#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L
2403#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a
2404#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L
2405#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c
2406#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L
2407#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003
2408#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L
2409#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007
2410#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L
2411#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008
2412#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L
2413#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009
2414#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L
2415#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004
2416#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L
2417#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000
2418#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL
2419#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000
2420#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L
2421#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d
2422#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L
2423#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a
2424#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L
2425#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c
2426#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L
2427#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003
2428#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L
2429#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007
2430#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L
2431#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008
2432#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L
2433#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009
2434#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L
2435#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004
2436#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L
2437#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000
2438#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL
2439#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000
2440#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L
2441#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d
2442#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L
2443#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a
2444#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L
2445#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c
2446#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L
2447#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003
2448#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L
2449#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007
2450#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L
2451#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008
2452#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L
2453#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009
2454#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L
2455#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004
2456#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L
2457#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000
2458#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL
2459#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000
2460#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L
2461#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d
2462#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L
2463#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a
2464#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L
2465#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c
2466#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L
2467#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003
2468#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L
2469#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007
2470#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L
2471#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008
2472#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L
2473#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009
2474#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L
2475#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004
2476#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L
2477#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000
2478#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL
2479#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000
2480#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L
2481#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d
2482#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L
2483#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a
2484#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L
2485#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c
2486#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L
2487#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003
2488#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L
2489#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007
2490#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L
2491#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008
2492#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L
2493#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009
2494#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L
2495#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004
2496#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L
2497#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000
2498#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL
2499#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000
2500#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L
2501#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d
2502#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L
2503#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a
2504#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L
2505#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c
2506#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L
2507#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003
2508#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L
2509#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007
2510#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L
2511#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008
2512#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L
2513#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009
2514#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L
2515#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004
2516#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L
2517#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000
2518#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L
2519#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f
2520#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L
2521#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000
2522#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L
2523#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a
2524#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L
2525#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b
2526#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L
2527#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c
2528#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L
2529#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d
2530#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L
2531#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e
2532#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L
2533#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f
2534#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L
2535#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010
2536#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L
2537#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011
2538#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L
2539#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012
2540#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L
2541#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013
2542#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L
2543#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001
2544#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L
2545#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014
2546#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L
2547#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015
2548#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L
2549#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016
2550#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L
2551#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017
2552#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L
2553#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018
2554#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L
2555#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019
2556#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L
2557#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a
2558#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L
2559#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b
2560#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L
2561#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c
2562#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L
2563#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d
2564#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L
2565#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002
2566#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L
2567#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e
2568#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L
2569#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f
2570#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L
2571#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003
2572#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L
2573#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004
2574#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L
2575#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005
2576#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L
2577#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006
2578#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L
2579#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007
2580#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L
2581#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008
2582#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L
2583#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009
2584#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L
2585#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000
2586#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L
2587#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001
2588#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L
2589#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002
2590#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L
2591#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003
2592#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L
2593#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004
2594#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L
2595#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005
2596#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L
2597#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006
2598#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L
2599#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007
2600#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L
2601#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008
2602#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L
2603#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009
2604#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L
2605#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a
2606#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L
2607#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b
2608#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L
2609#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c
2610#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L
2611#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d
2612#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L
2613#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e
2614#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L
2615#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f
2616#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L
2617#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010
2618#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L
2619#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011
2620#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L
2621#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012
2622#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L
2623#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013
2624#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L
2625#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014
2626#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L
2627#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015
2628#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L
2629#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016
2630#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L
2631#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017
2632#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L
2633#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018
2634#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L
2635#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019
2636#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L
2637#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a
2638#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L
2639#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b
2640#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L
2641#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c
2642#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L
2643#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d
2644#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L
2645#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e
2646#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L
2647#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f
2648#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L
2649#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000
2650#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L
2651#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001
2652#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L
2653#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002
2654#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L
2655#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003
2656#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L
2657#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004
2658#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L
2659#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005
2660#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L
2661#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006
2662#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L
2663#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007
2664#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L
2665#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008
2666#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L
2667#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009
2668#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L
2669#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a
2670#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L
2671#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b
2672#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L
2673#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c
2674#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L
2675#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d
2676#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L
2677#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e
2678#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L
2679#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f
2680#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L
2681#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010
2682#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L
2683#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011
2684#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L
2685#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012
2686#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L
2687#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013
2688#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L
2689#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014
2690#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L
2691#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015
2692#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L
2693#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016
2694#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L
2695#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017
2696#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L
2697#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018
2698#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L
2699#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019
2700#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L
2701#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a
2702#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L
2703#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b
2704#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L
2705#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c
2706#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L
2707#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d
2708#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L
2709#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e
2710#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L
2711#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f
2712#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L
2713#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004
2714#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L
2715#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005
2716#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L
2717#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006
2718#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L
2719#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007
2720#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L
2721#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008
2722#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L
2723#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009
2724#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L
2725#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a
2726#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L
2727#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b
2728#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L
2729#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c
2730#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L
2731#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d
2732#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L
2733#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000
2734#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L
2735#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001
2736#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L
2737#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002
2738#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L
2739#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003
2740#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L
2741#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008
2742#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L
2743#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b
2744#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L
2745#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e
2746#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L
2747#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016
2748#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L
2749#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015
2750#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L
2751#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013
2752#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L
2753#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017
2754#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L
2755#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000
2756#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L
2757#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003
2758#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L
2759#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018
2760#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L
2761#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014
2762#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L
2763#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011
2764#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L
2765#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e
2766#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L
2767#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000
2768#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L
2769#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a
2770#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L
2771#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b
2772#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L
2773#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c
2774#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L
2775#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d
2776#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L
2777#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e
2778#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L
2779#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f
2780#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L
2781#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001
2782#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L
2783#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002
2784#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L
2785#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003
2786#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L
2787#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004
2788#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L
2789#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005
2790#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L
2791#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006
2792#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L
2793#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007
2794#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L
2795#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008
2796#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L
2797#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009
2798#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L
2799#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010
2800#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L
2801#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015
2802#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L
2803#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016
2804#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L
2805#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017
2806#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L
2807#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011
2808#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L
2809#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012
2810#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L
2811#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013
2812#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L
2813#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014
2814#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L
2815#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018
2816#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L
2817#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b
2818#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L
2819#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019
2820#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L
2821#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a
2822#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L
2823#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c
2824#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L
2825#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d
2826#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L
2827#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003
2828#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L
2829#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000
2830#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L
2831#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004
2832#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L
2833#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008
2834#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L
2835#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009
2836#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L
2837#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d
2838#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L
2839#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e
2840#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L
2841#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013
2842#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L
2843#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014
2844#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L
2845#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019
2846#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L
2847#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a
2848#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L
2849#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e
2850#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL
2851#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000
2852#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L
2853#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004
2854#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L
2855#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005
2856#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L
2857#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006
2858#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L
2859#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007
2860#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L
2861#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008
2862#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L
2863#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a
2864#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L
2865#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009
2866#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L
2867#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c
2868#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L
2869#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b
2870#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L
2871#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e
2872#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L
2873#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d
2874#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L
2875#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019
2876#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L
2877#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f
2878#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L
2879#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b
2880#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L
2881#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a
2882#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L
2883#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d
2884#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L
2885#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c
2886#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L
2887#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f
2888#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L
2889#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e
2890#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L
2891#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c
2892#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L
2893#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010
2894#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L
2895#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014
2896#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L
2897#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019
2898#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L
2899#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b
2900#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L
2901#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a
2902#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L
2903#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003
2904#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L
2905#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002
2906#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L
2907#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005
2908#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L
2909#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004
2910#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L
2911#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007
2912#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L
2913#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006
2914#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L
2915#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009
2916#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L
2917#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008
2918#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L
2919#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001
2920#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L
2921#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000
2922#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L
2923#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a
2924#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L
2925#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e
2926#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L
2927#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012
2928#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L
2929#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017
2930#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL
2931#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000
2932#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L
2933#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c
2934#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L
2935#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004
2936#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L
2937#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008
2938#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L
2939#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009
2940#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL
2941#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000
2942#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L
2943#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004
2944#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L
2945#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005
2946#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L
2947#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008
2948#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L
2949#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b
2950#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L
2951#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009
2952#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L
2953#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a
2954#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L
2955#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c
2956#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L
2957#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f
2958#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L
2959#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d
2960#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L
2961#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e
2962#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L
2963#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004
2964#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L
2965#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007
2966#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L
2967#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005
2968#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L
2969#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006
2970#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L
2971#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000
2972#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L
2973#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003
2974#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L
2975#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001
2976#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L
2977#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002
2978#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L
2979#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000
2980#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L
2981#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001
2982#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L
2983#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002
2984#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L
2985#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003
2986#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L
2987#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001
2988#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L
2989#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000
2990#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L
2991#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003
2992#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L
2993#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002
2994#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L
2995#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005
2996#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L
2997#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004
2998#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L
2999#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007
3000#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L
3001#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006
3002#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L
3003#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a
3004#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L
3005#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008
3006#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L
3007#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007
3008#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L
3009#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003
3010#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L
3011#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004
3012#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L
3013#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000
3014#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L
3015#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000
3016#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L
3017#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001
3018#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L
3019#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002
3020#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L
3021#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003
3022#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L
3023#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001
3024#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L
3025#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000
3026#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L
3027#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003
3028#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L
3029#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002
3030#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L
3031#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005
3032#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L
3033#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004
3034#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L
3035#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007
3036#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L
3037#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006
3038#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L
3039#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a
3040#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L
3041#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008
3042#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L
3043#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007
3044#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L
3045#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003
3046#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L
3047#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004
3048#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L
3049#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000
3050#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L
3051#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000
3052#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L
3053#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001
3054#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L
3055#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002
3056#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L
3057#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003
3058#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L
3059#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001
3060#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L
3061#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000
3062#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L
3063#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003
3064#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L
3065#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002
3066#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L
3067#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005
3068#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L
3069#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004
3070#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L
3071#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007
3072#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L
3073#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006
3074#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L
3075#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a
3076#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L
3077#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008
3078#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L
3079#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007
3080#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L
3081#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003
3082#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L
3083#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004
3084#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L
3085#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000
3086#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L
3087#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000
3088#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L
3089#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001
3090#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L
3091#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002
3092#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L
3093#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003
3094#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L
3095#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001
3096#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L
3097#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000
3098#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L
3099#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003
3100#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L
3101#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002
3102#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L
3103#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005
3104#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L
3105#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004
3106#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L
3107#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007
3108#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L
3109#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006
3110#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L
3111#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a
3112#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L
3113#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008
3114#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L
3115#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007
3116#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L
3117#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003
3118#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L
3119#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004
3120#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L
3121#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000
3122#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L
3123#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000
3124#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L
3125#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001
3126#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L
3127#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002
3128#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L
3129#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003
3130#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L
3131#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001
3132#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L
3133#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000
3134#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L
3135#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003
3136#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L
3137#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002
3138#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L
3139#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005
3140#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L
3141#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004
3142#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L
3143#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007
3144#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L
3145#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006
3146#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L
3147#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a
3148#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L
3149#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008
3150#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L
3151#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007
3152#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L
3153#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003
3154#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L
3155#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004
3156#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L
3157#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000
3158#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L
3159#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000
3160#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L
3161#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001
3162#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L
3163#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002
3164#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L
3165#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003
3166#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L
3167#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001
3168#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L
3169#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000
3170#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L
3171#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003
3172#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L
3173#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002
3174#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L
3175#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005
3176#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L
3177#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004
3178#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L
3179#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007
3180#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L
3181#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006
3182#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L
3183#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a
3184#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L
3185#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008
3186#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L
3187#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007
3188#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L
3189#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003
3190#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L
3191#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004
3192#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L
3193#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000
3194#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L
3195#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000
3196#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L
3197#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001
3198#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L
3199#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002
3200#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L
3201#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003
3202#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L
3203#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001
3204#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L
3205#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000
3206#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L
3207#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003
3208#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L
3209#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002
3210#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L
3211#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005
3212#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L
3213#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004
3214#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L
3215#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007
3216#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L
3217#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006
3218#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L
3219#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a
3220#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L
3221#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008
3222#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L
3223#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007
3224#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L
3225#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003
3226#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L
3227#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004
3228#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L
3229#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000
3230#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L
3231#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000
3232#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L
3233#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001
3234#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L
3235#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002
3236#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L
3237#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003
3238#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L
3239#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001
3240#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L
3241#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000
3242#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L
3243#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003
3244#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L
3245#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002
3246#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L
3247#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005
3248#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L
3249#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004
3250#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L
3251#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007
3252#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L
3253#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006
3254#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L
3255#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a
3256#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L
3257#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008
3258#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L
3259#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007
3260#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L
3261#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003
3262#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L
3263#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004
3264#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L
3265#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000
3266#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L
3267#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000
3268#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L
3269#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001
3270#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L
3271#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002
3272#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L
3273#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003
3274#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L
3275#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001
3276#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L
3277#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000
3278#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L
3279#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003
3280#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L
3281#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002
3282#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L
3283#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005
3284#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L
3285#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004
3286#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L
3287#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007
3288#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L
3289#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006
3290#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L
3291#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a
3292#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L
3293#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008
3294#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L
3295#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007
3296#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L
3297#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003
3298#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L
3299#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004
3300#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L
3301#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000
3302#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L
3303#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000
3304#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L
3305#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001
3306#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L
3307#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002
3308#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L
3309#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003
3310#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L
3311#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001
3312#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L
3313#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000
3314#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L
3315#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003
3316#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L
3317#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002
3318#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L
3319#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005
3320#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L
3321#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004
3322#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L
3323#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007
3324#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L
3325#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006
3326#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L
3327#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a
3328#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L
3329#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008
3330#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L
3331#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007
3332#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L
3333#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003
3334#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L
3335#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004
3336#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L
3337#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000
3338#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L
3339#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000
3340#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L
3341#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001
3342#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L
3343#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002
3344#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L
3345#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003
3346#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L
3347#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001
3348#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L
3349#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000
3350#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L
3351#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003
3352#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L
3353#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002
3354#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L
3355#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005
3356#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L
3357#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004
3358#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L
3359#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007
3360#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L
3361#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006
3362#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L
3363#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a
3364#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L
3365#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008
3366#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L
3367#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007
3368#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L
3369#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003
3370#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L
3371#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004
3372#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L
3373#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000
3374#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L
3375#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000
3376#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L
3377#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001
3378#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L
3379#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002
3380#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L
3381#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003
3382#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L
3383#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001
3384#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L
3385#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000
3386#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L
3387#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003
3388#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L
3389#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002
3390#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L
3391#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005
3392#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L
3393#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004
3394#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L
3395#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007
3396#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L
3397#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006
3398#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L
3399#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a
3400#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L
3401#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008
3402#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L
3403#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007
3404#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L
3405#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003
3406#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L
3407#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004
3408#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L
3409#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000
3410#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L
3411#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000
3412#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L
3413#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001
3414#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L
3415#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002
3416#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L
3417#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003
3418#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L
3419#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001
3420#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L
3421#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000
3422#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L
3423#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003
3424#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L
3425#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002
3426#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L
3427#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005
3428#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L
3429#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004
3430#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L
3431#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007
3432#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L
3433#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006
3434#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L
3435#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a
3436#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L
3437#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008
3438#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L
3439#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007
3440#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L
3441#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003
3442#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L
3443#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004
3444#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L
3445#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000
3446#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L
3447#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000
3448#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L
3449#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001
3450#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L
3451#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002
3452#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L
3453#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003
3454#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L
3455#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001
3456#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L
3457#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000
3458#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L
3459#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003
3460#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L
3461#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002
3462#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L
3463#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005
3464#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L
3465#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004
3466#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L
3467#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007
3468#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L
3469#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006
3470#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L
3471#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a
3472#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L
3473#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008
3474#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L
3475#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007
3476#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L
3477#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003
3478#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L
3479#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004
3480#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L
3481#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000
3482#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L
3483#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000
3484#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L
3485#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001
3486#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L
3487#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002
3488#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L
3489#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003
3490#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L
3491#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001
3492#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L
3493#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000
3494#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L
3495#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003
3496#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L
3497#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002
3498#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L
3499#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005
3500#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L
3501#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004
3502#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L
3503#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007
3504#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L
3505#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006
3506#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L
3507#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a
3508#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L
3509#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008
3510#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L
3511#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007
3512#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L
3513#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003
3514#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L
3515#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004
3516#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L
3517#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000
3518#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L
3519#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000
3520#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L
3521#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001
3522#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L
3523#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002
3524#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L
3525#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003
3526#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L
3527#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001
3528#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L
3529#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000
3530#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L
3531#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003
3532#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L
3533#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002
3534#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L
3535#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005
3536#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L
3537#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004
3538#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L
3539#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007
3540#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L
3541#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006
3542#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L
3543#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a
3544#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L
3545#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008
3546#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L
3547#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007
3548#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L
3549#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003
3550#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L
3551#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004
3552#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L
3553#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000
3554#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L
3555#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000
3556#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL
3557#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001
3558#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L
3559#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008
3560#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L
3561#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017
3562#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L
3563#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016
3564#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL
3565#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000
3566#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L
3567#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018
3568#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L
3569#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010
3570#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L
3571#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008
3572#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL
3573#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000
3574#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL
3575#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000
3576#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL
3577#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000
3578#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L
3579#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010
3580#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L
3581#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014
3582#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L
3583#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017
3584#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L
3585#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018
3586#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L
3587#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019
3588#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L
3589#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a
3590#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L
3591#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e
3592#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L
3593#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f
3594#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L
3595#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000
3596#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL
3597#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001
3598#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L
3599#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007
3600#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L
3601#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008
3602#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L
3603#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e
3604#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L
3605#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f
3606#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L
3607#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016
3608#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L
3609#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017
3610#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L
3611#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e
3612#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L
3613#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000
3614#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL
3615#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001
3616#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L
3617#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008
3618#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L
3619#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009
3620#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L
3621#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010
3622#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L
3623#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011
3624#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L
3625#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018
3626#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L
3627#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019
3628#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L
3629#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005
3630#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L
3631#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007
3632#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L
3633#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009
3634#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L
3635#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e
3636#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L
3637#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c
3638#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L
3639#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b
3640#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L
3641#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012
3642#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L
3643#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f
3644#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L
3645#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016
3646#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L
3647#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017
3648#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L
3649#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b
3650#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L
3651#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c
3652#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L
3653#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015
3654#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL
3655#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000
3656#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L
3657#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016
3658#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL
3659#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000
3660#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L
3661#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012
3662#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L
3663#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010
3664#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L
3665#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a
3666#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L
3667#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c
3668#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L
3669#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b
3670#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL
3671#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000
3672#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL
3673#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000
3674#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L
3675#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010
3676#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L
3677#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f
3678#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L
3679#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010
3680#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L
3681#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002
3682#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L
3683#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003
3684#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L
3685#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000
3686#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L
3687#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001
3688#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L
3689#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000
3690#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L
3691#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001
3692#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L
3693#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000
3694#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L
3695#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003
3696#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L
3697#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001
3698#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L
3699#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002
3700#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L
3701#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004
3702#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L
3703#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014
3704#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L
3705#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010
3706#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L
3707#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008
3708#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L
3709#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c
3710#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L
3711#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c
3712#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L
3713#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d
3714#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L
3715#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e
3716#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L
3717#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f
3718#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L
3719#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012
3720#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L
3721#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016
3722#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L
3723#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a
3724#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L
3725#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e
3726#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L
3727#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002
3728#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L
3729#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001
3730#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L
3731#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000
3732#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L
3733#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010
3734#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L
3735#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014
3736#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L
3737#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018
3738#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L
3739#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c
3740#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L
3741#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c
3742#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L
3743#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d
3744#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L
3745#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e
3746#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L
3747#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f
3748#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L
3749#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012
3750#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L
3751#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016
3752#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L
3753#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a
3754#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L
3755#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e
3756#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L
3757#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002
3758#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L
3759#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001
3760#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L
3761#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000
3762#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L
3763#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010
3764#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L
3765#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014
3766#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L
3767#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018
3768#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L
3769#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c
3770#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L
3771#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e
3772#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L
3773#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f
3774#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L
3775#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c
3776#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L
3777#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d
3778#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L
3779#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a
3780#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L
3781#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e
3782#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L
3783#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012
3784#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L
3785#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016
3786#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L
3787#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002
3788#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L
3789#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001
3790#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L
3791#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000
3792#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L
3793#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018
3794#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L
3795#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c
3796#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L
3797#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010
3798#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L
3799#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014
3800#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L
3801#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c
3802#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L
3803#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d
3804#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L
3805#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e
3806#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L
3807#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f
3808#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L
3809#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012
3810#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L
3811#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016
3812#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L
3813#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a
3814#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L
3815#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e
3816#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L
3817#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002
3818#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L
3819#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001
3820#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L
3821#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000
3822#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L
3823#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010
3824#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L
3825#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014
3826#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L
3827#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018
3828#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L
3829#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c
3830#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x00000001L
3831#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x00000000
3832#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x00000002L
3833#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x00000001
3834#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x00000004L
3835#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x00000002
3836#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x00000008L
3837#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x00000003
3838#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x00000010L
3839#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x00000004
3840#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x00000020L
3841#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x00000005
3842#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x00000040L
3843#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x00000006
3844#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x00000080L
3845#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x00000007
3846#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x00000100L
3847#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x00000008
3848#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x00000200L
3849#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x00000009
3850#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x00000400L
3851#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0x0000000a
3852#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x00000800L
3853#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0x0000000b
3854#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x00001000L
3855#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0x0000000c
3856#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x00002000L
3857#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0x0000000d
3858#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x00004000L
3859#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0x0000000e
3860#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x00008000L
3861#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0x0000000f
3862#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x00010000L
3863#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x00000010
3864#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x00020000L
3865#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x00000011
3866#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x00040000L
3867#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x00000012
3868#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x00080000L
3869#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x00000013
3870#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x00100000L
3871#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x00000014
3872#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x00200000L
3873#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x00000015
3874#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x00400000L
3875#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x00000016
3876#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x00800000L
3877#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x00000017
3878#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x01000000L
3879#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x00000018
3880#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x02000000L
3881#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x00000019
3882#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x04000000L
3883#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x0000001a
3884#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x08000000L
3885#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x0000001b
3886#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000L
3887#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x0000001c
3888#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000L
3889#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x0000001d
3890#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000L
3891#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x0000001e
3892#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000L
3893#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x0000001f
3894#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L
3895#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007
3896#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L
3897#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008
3898#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L
3899#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012
3900#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L
3901#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013
3902#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L
3903#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014
3904#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L
3905#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015
3906#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L
3907#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016
3908#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L
3909#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017
3910#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L
3911#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009
3912#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L
3913#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a
3914#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L
3915#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b
3916#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L
3917#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c
3918#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L
3919#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d
3920#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L
3921#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e
3922#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L
3923#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f
3924#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L
3925#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010
3926#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L
3927#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011
3928#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L
3929#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001
3930#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L
3931#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018
3932#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L
3933#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001
3934#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L
3935#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005
3936#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L
3937#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009
3938#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L
3939#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d
3940#define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L
3941#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008
3942#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L
3943#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014
3944#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L
3945#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004
3946#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L
3947#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017
3948#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L
3949#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c
3950#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L
3951#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d
3952#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L
3953#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011
3954#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L
3955#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003
3956#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L
3957#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002
3958#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L
3959#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a
3960#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L
3961#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006
3962#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L
3963#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007
3964#define PB1_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L
3965#define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018
3966#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L
3967#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b
3968#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L
3969#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000
3970#define PB1_PIF_CNTL__TXGND_TIME_MASK 0x00010000L
3971#define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010
3972#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x00000001L
3973#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x00000000
3974#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x00000002L
3975#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x00000001
3976#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x00000004L
3977#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x00000002
3978#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x00000008L
3979#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x00000003
3980#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x00000010L
3981#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x00000004
3982#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x00000020L
3983#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x00000005
3984#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x00000040L
3985#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x00000006
3986#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x00000080L
3987#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x00000007
3988#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x00000100L
3989#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x00000008
3990#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x00000200L
3991#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x00000009
3992#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x00000400L
3993#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0x0000000a
3994#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x00000800L
3995#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0x0000000b
3996#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x00001000L
3997#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0x0000000c
3998#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x00002000L
3999#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0x0000000d
4000#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x00004000L
4001#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0x0000000e
4002#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x00008000L
4003#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0x0000000f
4004#define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L
4005#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019
4006#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L
4007#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014
4008#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L
4009#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000
4010#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L
4011#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005
4012#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L
4013#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006
4014#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L
4015#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007
4016#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L
4017#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001
4018#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L
4019#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002
4020#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L
4021#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003
4022#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L
4023#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004
4024#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L
4025#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a
4026#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L
4027#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b
4028#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L
4029#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008
4030#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L
4031#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009
4032#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L
4033#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011
4034#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L
4035#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010
4036#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L
4037#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008
4038#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L
4039#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009
4040#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L
4041#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004
4042#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L
4043#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005
4044#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L
4045#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e
4046#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L
4047#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f
4048#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L
4049#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000
4050#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL
4051#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001
4052#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L
4053#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a
4054#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L
4055#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b
4056#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L
4057#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008
4058#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L
4059#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009
4060#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L
4061#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004
4062#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L
4063#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005
4064#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L
4065#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e
4066#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L
4067#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f
4068#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L
4069#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000
4070#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL
4071#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001
4072#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L
4073#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a
4074#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L
4075#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b
4076#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L
4077#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008
4078#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L
4079#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009
4080#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L
4081#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004
4082#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L
4083#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005
4084#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L
4085#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e
4086#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L
4087#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f
4088#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L
4089#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000
4090#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL
4091#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001
4092#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L
4093#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a
4094#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L
4095#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b
4096#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L
4097#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008
4098#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L
4099#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009
4100#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L
4101#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004
4102#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L
4103#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005
4104#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L
4105#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e
4106#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L
4107#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f
4108#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L
4109#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000
4110#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL
4111#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001
4112#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L
4113#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a
4114#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L
4115#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b
4116#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L
4117#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008
4118#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L
4119#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009
4120#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L
4121#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004
4122#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L
4123#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005
4124#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L
4125#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e
4126#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L
4127#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f
4128#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L
4129#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000
4130#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL
4131#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001
4132#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L
4133#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a
4134#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L
4135#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b
4136#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L
4137#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008
4138#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L
4139#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009
4140#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L
4141#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004
4142#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L
4143#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005
4144#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L
4145#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e
4146#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L
4147#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f
4148#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L
4149#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000
4150#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL
4151#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001
4152#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L
4153#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a
4154#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L
4155#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b
4156#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L
4157#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008
4158#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L
4159#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009
4160#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L
4161#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004
4162#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L
4163#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005
4164#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L
4165#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e
4166#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L
4167#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f
4168#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L
4169#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000
4170#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL
4171#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001
4172#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L
4173#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a
4174#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L
4175#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b
4176#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L
4177#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008
4178#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L
4179#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009
4180#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L
4181#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004
4182#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L
4183#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005
4184#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L
4185#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e
4186#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L
4187#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f
4188#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L
4189#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000
4190#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL
4191#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001
4192#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L
4193#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a
4194#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L
4195#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b
4196#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L
4197#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008
4198#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L
4199#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009
4200#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L
4201#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004
4202#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L
4203#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005
4204#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L
4205#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e
4206#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L
4207#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f
4208#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L
4209#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000
4210#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL
4211#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001
4212#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L
4213#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a
4214#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L
4215#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b
4216#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L
4217#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008
4218#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L
4219#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009
4220#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L
4221#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004
4222#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L
4223#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005
4224#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L
4225#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e
4226#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L
4227#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f
4228#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L
4229#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000
4230#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL
4231#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001
4232#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L
4233#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a
4234#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L
4235#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b
4236#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L
4237#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008
4238#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L
4239#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009
4240#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L
4241#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004
4242#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L
4243#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005
4244#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L
4245#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e
4246#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L
4247#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f
4248#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L
4249#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000
4250#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL
4251#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001
4252#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L
4253#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a
4254#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L
4255#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b
4256#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L
4257#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008
4258#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L
4259#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009
4260#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L
4261#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004
4262#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L
4263#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005
4264#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L
4265#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e
4266#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L
4267#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f
4268#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L
4269#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000
4270#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL
4271#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001
4272#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L
4273#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a
4274#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L
4275#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b
4276#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L
4277#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008
4278#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L
4279#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009
4280#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L
4281#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004
4282#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L
4283#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005
4284#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L
4285#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e
4286#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L
4287#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f
4288#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L
4289#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000
4290#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL
4291#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001
4292#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L
4293#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a
4294#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L
4295#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b
4296#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L
4297#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008
4298#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L
4299#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009
4300#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L
4301#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004
4302#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L
4303#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005
4304#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L
4305#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e
4306#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L
4307#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f
4308#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L
4309#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000
4310#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL
4311#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001
4312#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L
4313#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a
4314#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L
4315#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b
4316#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L
4317#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008
4318#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L
4319#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009
4320#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L
4321#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004
4322#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L
4323#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005
4324#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L
4325#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e
4326#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L
4327#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f
4328#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L
4329#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000
4330#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL
4331#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001
4332#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L
4333#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a
4334#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L
4335#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b
4336#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L
4337#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008
4338#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L
4339#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009
4340#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L
4341#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004
4342#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L
4343#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005
4344#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L
4345#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e
4346#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L
4347#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f
4348#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L
4349#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000
4350#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL
4351#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001
4352#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L
4353#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a
4354#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L
4355#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b
4356#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L
4357#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003
4358#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L
4359#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a
4360#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L
4361#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007
4362#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L
4363#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c
4364#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L
4365#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d
4366#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L
4367#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018
4368#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L
4369#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004
4370#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L
4371#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010
4372#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L
4373#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000
4374#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L
4375#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003
4376#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L
4377#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a
4378#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L
4379#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007
4380#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L
4381#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c
4382#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L
4383#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d
4384#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L
4385#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018
4386#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L
4387#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004
4388#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L
4389#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010
4390#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L
4391#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000
4392#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L
4393#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003
4394#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L
4395#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a
4396#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L
4397#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007
4398#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L
4399#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c
4400#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L
4401#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d
4402#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L
4403#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018
4404#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L
4405#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004
4406#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L
4407#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010
4408#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L
4409#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000
4410#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L
4411#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003
4412#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L
4413#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a
4414#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L
4415#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007
4416#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L
4417#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c
4418#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L
4419#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d
4420#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L
4421#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018
4422#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L
4423#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004
4424#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L
4425#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010
4426#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L
4427#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000
4428#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L
4429#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000
4430#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L
4431#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005
4432#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L
4433#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004
4434#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L
4435#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003
4436#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L
4437#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002
4438#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L
4439#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010
4440#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L
4441#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a
4442#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L
4443#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b
4444#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L
4445#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c
4446#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L
4447#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d
4448#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L
4449#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e
4450#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L
4451#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f
4452#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L
4453#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011
4454#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L
4455#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012
4456#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L
4457#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013
4458#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L
4459#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014
4460#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L
4461#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015
4462#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L
4463#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016
4464#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L
4465#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017
4466#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L
4467#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018
4468#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L
4469#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019
4470#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L
4471#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008
4472#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L
4473#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009
4474#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L
4475#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a
4476#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L
4477#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b
4478#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L
4479#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c
4480#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L
4481#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d
4482#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L
4483#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e
4484#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L
4485#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f
4486#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L
4487#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001
4488#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L
4489#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006
4490#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL
4491#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000
4492#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L
4493#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000
4494#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L
4495#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005
4496#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L
4497#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004
4498#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L
4499#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003
4500#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L
4501#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002
4502#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L
4503#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008
4504#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L
4505#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001
4506#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L
4507#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006
4508#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L
4509#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000
4510#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L
4511#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005
4512#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L
4513#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004
4514#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L
4515#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003
4516#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L
4517#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002
4518#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L
4519#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008
4520#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L
4521#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001
4522#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L
4523#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006
4524#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L
4525#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000
4526#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L
4527#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005
4528#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L
4529#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004
4530#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L
4531#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003
4532#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L
4533#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002
4534#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L
4535#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008
4536#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L
4537#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001
4538#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L
4539#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006
4540#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L
4541#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000
4542#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L
4543#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005
4544#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L
4545#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004
4546#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L
4547#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003
4548#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L
4549#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002
4550#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L
4551#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008
4552#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L
4553#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001
4554#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L
4555#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006
4556#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L
4557#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000
4558#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L
4559#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005
4560#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L
4561#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004
4562#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L
4563#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003
4564#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L
4565#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002
4566#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L
4567#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008
4568#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L
4569#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001
4570#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L
4571#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006
4572#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L
4573#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000
4574#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L
4575#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005
4576#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L
4577#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004
4578#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L
4579#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003
4580#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L
4581#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002
4582#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L
4583#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008
4584#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L
4585#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001
4586#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L
4587#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006
4588#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L
4589#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000
4590#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L
4591#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005
4592#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L
4593#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004
4594#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L
4595#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003
4596#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L
4597#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002
4598#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L
4599#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008
4600#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L
4601#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001
4602#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L
4603#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006
4604#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L
4605#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000
4606#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L
4607#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005
4608#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L
4609#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004
4610#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L
4611#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003
4612#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L
4613#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002
4614#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L
4615#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008
4616#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L
4617#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001
4618#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L
4619#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006
4620#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L
4621#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000
4622#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L
4623#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005
4624#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L
4625#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004
4626#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L
4627#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003
4628#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L
4629#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002
4630#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L
4631#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008
4632#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L
4633#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001
4634#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L
4635#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006
4636#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L
4637#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000
4638#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L
4639#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005
4640#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L
4641#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004
4642#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L
4643#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003
4644#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L
4645#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002
4646#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L
4647#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008
4648#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L
4649#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001
4650#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L
4651#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006
4652#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L
4653#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000
4654#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L
4655#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005
4656#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L
4657#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004
4658#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L
4659#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003
4660#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L
4661#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002
4662#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L
4663#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008
4664#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L
4665#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001
4666#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L
4667#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006
4668#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L
4669#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000
4670#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L
4671#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005
4672#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L
4673#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004
4674#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L
4675#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003
4676#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L
4677#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002
4678#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L
4679#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008
4680#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L
4681#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001
4682#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L
4683#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006
4684#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L
4685#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000
4686#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L
4687#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005
4688#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L
4689#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004
4690#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L
4691#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003
4692#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L
4693#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002
4694#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L
4695#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008
4696#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L
4697#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001
4698#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L
4699#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006
4700#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L
4701#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000
4702#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L
4703#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005
4704#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L
4705#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004
4706#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L
4707#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003
4708#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L
4709#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002
4710#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L
4711#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008
4712#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L
4713#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001
4714#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L
4715#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006
4716#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L
4717#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000
4718#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L
4719#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005
4720#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L
4721#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004
4722#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L
4723#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003
4724#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L
4725#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002
4726#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L
4727#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008
4728#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L
4729#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001
4730#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L
4731#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006
4732#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L
4733#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000
4734#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L
4735#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005
4736#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L
4737#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004
4738#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L
4739#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003
4740#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L
4741#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002
4742#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L
4743#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008
4744#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L
4745#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001
4746#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L
4747#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006
4748#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L
4749#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000
4750#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L
4751#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a
4752#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L
4753#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b
4754#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L
4755#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c
4756#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L
4757#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d
4758#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L
4759#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e
4760#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L
4761#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f
4762#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L
4763#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001
4764#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L
4765#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002
4766#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L
4767#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003
4768#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L
4769#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004
4770#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L
4771#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005
4772#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L
4773#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006
4774#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L
4775#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007
4776#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L
4777#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008
4778#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L
4779#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009
4780#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L
4781#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000
4782#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L
4783#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002
4784#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L
4785#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003
4786#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L
4787#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004
4788#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L
4789#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003
4790#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L
4791#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000
4792#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L
4793#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007
4794#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L
4795#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004
4796#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L
4797#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009
4798#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L
4799#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008
4800#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L
4801#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012
4802#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L
4803#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a
4804#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L
4805#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c
4806#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L
4807#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013
4808#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L
4809#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f
4810#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L
4811#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d
4812#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L
4813#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003
4814#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L
4815#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000
4816#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L
4817#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012
4818#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L
4819#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e
4820#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L
4821#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005
4822#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L
4823#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004
4824#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L
4825#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007
4826#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L
4827#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006
4828#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L
4829#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009
4830#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L
4831#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008
4832#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L
4833#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008
4834#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4835#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4836#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4837#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4838#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L
4839#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004
4840#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L
4841#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008
4842#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4843#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4844#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4845#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4846#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L
4847#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004
4848#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L
4849#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008
4850#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4851#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4852#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4853#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4854#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L
4855#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004
4856#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L
4857#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008
4858#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4859#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4860#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4861#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4862#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L
4863#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004
4864#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L
4865#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000
4866#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L
4867#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002
4868#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L
4869#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004
4870#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L
4871#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003
4872#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L
4873#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b
4874#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L
4875#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008
4876#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL
4877#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000
4878#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L
4879#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c
4880#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L
4881#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009
4882#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L
4883#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e
4884#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L
4885#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d
4886#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L
4887#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c
4888#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L
4889#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f
4890#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L
4891#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f
4892#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L
4893#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e
4894#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L
4895#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016
4896#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L
4897#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013
4898#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L
4899#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005
4900#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL
4901#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000
4902#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L
4903#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008
4904#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L
4905#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006
4906#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L
4907#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a
4908#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L
4909#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009
4910#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L
4911#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c
4912#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L
4913#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b
4914#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L
4915#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e
4916#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L
4917#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d
4918#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L
4919#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008
4920#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4921#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4922#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4923#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4924#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L
4925#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004
4926#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L
4927#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008
4928#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4929#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4930#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4931#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4932#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L
4933#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004
4934#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L
4935#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008
4936#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4937#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4938#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4939#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4940#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L
4941#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004
4942#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L
4943#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008
4944#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L
4945#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001
4946#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L
4947#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000
4948#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L
4949#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004
4950#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L
4951#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009
4952#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L
4953#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a
4954#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L
4955#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b
4956#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L
4957#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014
4958#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L
4959#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015
4960#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L
4961#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c
4962#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L
4963#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d
4964#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L
4965#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e
4966#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L
4967#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016
4968#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L
4969#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017
4970#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L
4971#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008
4972#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L
4973#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001
4974#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L
4975#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002
4976#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L
4977#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003
4978#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L
4979#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010
4980#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L
4981#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011
4982#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L
4983#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004
4984#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L
4985#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005
4986#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L
4987#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006
4988#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L
4989#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012
4990#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L
4991#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013
4992#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L
4993#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007
4994#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L
4995#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000
4996#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL
4997#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000
4998#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L
4999#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a
5000#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L
5001#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014
5002#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L
5003#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e
5004#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L
5005#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e
5006#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL
5007#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000
5008#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L
5009#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004
5010#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L
5011#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008
5012#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L
5013#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c
5014#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L
5015#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010
5016#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L
5017#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014
5018#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L
5019#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018
5020#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L
5021#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019
5022#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L
5023#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a
5024#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L
5025#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b
5026#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L
5027#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c
5028#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L
5029#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d
5030#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L
5031#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c
5032#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L
5033#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010
5034#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L
5035#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014
5036#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L
5037#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018
5038#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L
5039#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a
5040#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L
5041#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c
5042#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L
5043#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e
5044#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L
5045#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000
5046#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L
5047#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001
5048#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L
5049#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002
5050#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L
5051#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014
5052#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L
5053#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018
5054#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L
5055#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c
5056#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L
5057#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000
5058#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L
5059#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003
5060#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L
5061#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006
5062#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L
5063#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014
5064#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L
5065#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018
5066#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L
5067#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c
5068#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L
5069#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009
5070#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L
5071#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c
5072#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L
5073#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f
5074#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL
5075#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000
5076#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L
5077#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005
5078#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L
5079#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a
5080#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L
5081#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f
5082#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L
5083#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010
5084#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L
5085#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011
5086#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L
5087#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012
5088#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L
5089#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013
5090#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L
5091#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014
5092#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L
5093#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b
5094#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L
5095#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c
5096#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L
5097#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d
5098#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L
5099#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e
5100#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L
5101#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b
5102#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL
5103#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000
5104#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L
5105#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004
5106#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L
5107#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008
5108#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L
5109#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c
5110#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L
5111#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010
5112#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L
5113#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014
5114#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L
5115#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018
5116#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L
5117#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a
5118#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L
5119#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012
5120#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L
5121#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015
5122#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L
5123#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018
5124#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L
5125#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b
5126#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L
5127#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c
5128#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L
5129#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d
5130#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL
5131#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000
5132#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L
5133#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004
5134#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L
5135#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008
5136#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L
5137#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c
5138#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L
5139#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d
5140#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L
5141#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011
5142#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L
5143#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f
5144#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L
5145#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e
5146#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L
5147#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001
5148#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L
5149#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000
5150#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L
5151#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003
5152#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L
5153#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002
5154#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L
5155#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d
5156#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L
5157#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c
5158#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L
5159#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008
5160#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L
5161#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006
5162#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L
5163#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a
5164#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L
5165#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009
5166#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L
5167#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c
5168#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L
5169#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b
5170#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L
5171#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e
5172#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L
5173#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d
5174#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L
5175#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010
5176#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L
5177#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f
5178#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L
5179#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012
5180#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L
5181#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011
5182#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L
5183#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014
5184#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L
5185#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013
5186#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L
5187#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016
5188#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L
5189#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015
5190#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L
5191#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018
5192#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L
5193#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017
5194#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L
5195#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001
5196#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L
5197#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000
5198#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L
5199#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004
5200#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L
5201#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007
5202#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L
5203#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005
5204#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L
5205#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006
5206#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L
5207#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c
5208#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L
5209#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f
5210#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L
5211#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d
5212#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L
5213#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e
5214#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L
5215#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010
5216#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L
5217#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013
5218#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L
5219#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011
5220#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L
5221#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012
5222#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L
5223#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014
5224#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L
5225#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017
5226#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L
5227#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015
5228#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L
5229#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016
5230#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L
5231#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008
5232#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L
5233#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b
5234#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L
5235#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009
5236#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L
5237#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a
5238#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L
5239#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000
5240#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L
5241#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003
5242#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L
5243#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001
5244#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L
5245#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002
5246#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL
5247#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000
5248#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L
5249#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d
5250#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L
5251#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a
5252#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L
5253#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c
5254#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L
5255#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003
5256#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L
5257#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007
5258#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L
5259#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008
5260#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L
5261#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009
5262#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L
5263#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004
5264#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L
5265#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000
5266#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL
5267#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000
5268#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L
5269#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d
5270#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L
5271#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a
5272#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L
5273#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c
5274#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L
5275#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003
5276#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L
5277#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007
5278#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L
5279#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008
5280#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L
5281#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009
5282#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L
5283#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004
5284#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L
5285#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000
5286#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL
5287#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000
5288#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L
5289#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d
5290#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L
5291#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a
5292#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L
5293#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c
5294#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L
5295#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003
5296#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L
5297#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007
5298#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L
5299#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008
5300#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L
5301#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009
5302#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L
5303#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004
5304#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L
5305#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000
5306#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL
5307#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000
5308#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L
5309#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d
5310#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L
5311#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a
5312#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L
5313#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c
5314#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L
5315#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003
5316#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L
5317#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007
5318#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L
5319#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008
5320#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L
5321#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009
5322#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L
5323#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004
5324#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L
5325#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000
5326#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL
5327#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000
5328#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L
5329#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d
5330#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L
5331#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a
5332#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L
5333#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c
5334#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L
5335#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003
5336#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L
5337#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007
5338#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L
5339#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008
5340#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L
5341#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009
5342#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L
5343#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004
5344#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L
5345#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000
5346#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL
5347#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000
5348#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L
5349#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d
5350#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L
5351#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a
5352#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L
5353#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c
5354#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L
5355#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003
5356#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L
5357#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007
5358#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L
5359#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008
5360#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L
5361#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009
5362#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L
5363#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004
5364#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L
5365#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000
5366#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL
5367#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000
5368#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L
5369#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d
5370#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L
5371#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a
5372#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L
5373#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c
5374#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L
5375#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003
5376#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L
5377#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007
5378#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L
5379#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008
5380#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L
5381#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009
5382#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L
5383#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004
5384#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L
5385#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000
5386#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL
5387#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000
5388#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L
5389#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d
5390#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L
5391#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a
5392#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L
5393#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c
5394#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L
5395#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003
5396#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L
5397#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007
5398#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L
5399#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008
5400#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L
5401#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009
5402#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L
5403#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004
5404#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L
5405#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000
5406#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL
5407#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000
5408#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L
5409#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d
5410#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L
5411#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a
5412#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L
5413#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c
5414#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L
5415#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003
5416#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L
5417#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007
5418#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L
5419#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008
5420#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L
5421#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009
5422#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L
5423#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004
5424#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L
5425#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000
5426#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL
5427#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000
5428#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L
5429#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d
5430#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L
5431#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a
5432#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L
5433#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c
5434#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L
5435#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003
5436#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L
5437#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007
5438#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L
5439#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008
5440#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L
5441#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009
5442#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L
5443#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004
5444#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L
5445#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000
5446#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL
5447#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000
5448#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L
5449#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d
5450#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L
5451#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a
5452#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L
5453#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c
5454#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L
5455#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003
5456#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L
5457#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007
5458#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L
5459#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008
5460#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L
5461#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009
5462#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L
5463#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004
5464#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L
5465#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000
5466#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL
5467#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000
5468#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L
5469#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d
5470#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L
5471#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a
5472#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L
5473#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c
5474#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L
5475#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003
5476#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L
5477#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007
5478#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L
5479#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008
5480#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L
5481#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009
5482#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L
5483#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004
5484#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L
5485#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000
5486#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL
5487#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000
5488#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L
5489#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d
5490#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L
5491#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a
5492#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L
5493#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c
5494#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L
5495#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003
5496#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L
5497#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007
5498#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L
5499#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008
5500#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L
5501#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009
5502#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L
5503#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004
5504#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L
5505#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000
5506#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL
5507#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000
5508#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L
5509#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d
5510#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L
5511#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a
5512#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L
5513#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c
5514#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L
5515#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003
5516#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L
5517#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007
5518#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L
5519#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008
5520#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L
5521#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009
5522#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L
5523#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004
5524#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L
5525#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000
5526#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL
5527#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000
5528#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L
5529#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d
5530#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L
5531#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a
5532#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L
5533#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c
5534#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L
5535#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003
5536#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L
5537#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007
5538#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L
5539#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008
5540#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L
5541#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009
5542#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L
5543#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004
5544#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L
5545#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000
5546#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL
5547#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000
5548#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L
5549#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d
5550#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L
5551#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a
5552#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L
5553#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c
5554#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L
5555#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003
5556#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L
5557#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007
5558#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L
5559#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008
5560#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L
5561#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009
5562#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L
5563#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004
5564#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L
5565#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000
5566#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L
5567#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f
5568#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L
5569#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000
5570#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L
5571#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a
5572#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L
5573#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b
5574#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L
5575#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c
5576#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L
5577#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d
5578#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L
5579#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e
5580#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L
5581#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f
5582#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L
5583#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010
5584#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L
5585#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011
5586#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L
5587#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012
5588#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L
5589#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013
5590#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L
5591#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001
5592#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L
5593#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014
5594#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L
5595#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015
5596#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L
5597#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016
5598#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L
5599#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017
5600#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L
5601#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018
5602#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L
5603#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019
5604#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L
5605#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a
5606#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L
5607#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b
5608#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L
5609#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c
5610#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L
5611#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d
5612#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L
5613#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002
5614#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L
5615#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e
5616#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L
5617#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f
5618#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L
5619#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003
5620#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L
5621#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004
5622#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L
5623#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005
5624#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L
5625#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006
5626#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L
5627#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007
5628#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L
5629#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008
5630#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L
5631#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009
5632#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L
5633#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000
5634#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L
5635#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001
5636#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L
5637#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002
5638#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L
5639#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003
5640#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L
5641#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004
5642#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L
5643#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005
5644#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L
5645#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006
5646#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L
5647#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007
5648#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L
5649#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008
5650#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L
5651#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009
5652#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L
5653#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a
5654#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L
5655#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b
5656#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L
5657#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c
5658#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L
5659#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d
5660#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L
5661#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e
5662#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L
5663#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f
5664#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L
5665#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010
5666#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L
5667#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011
5668#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L
5669#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012
5670#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L
5671#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013
5672#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L
5673#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014
5674#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L
5675#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015
5676#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L
5677#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016
5678#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L
5679#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017
5680#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L
5681#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018
5682#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L
5683#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019
5684#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L
5685#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a
5686#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L
5687#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b
5688#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L
5689#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c
5690#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L
5691#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d
5692#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L
5693#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e
5694#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L
5695#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f
5696#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L
5697#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000
5698#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L
5699#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001
5700#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L
5701#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002
5702#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L
5703#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003
5704#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L
5705#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004
5706#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L
5707#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005
5708#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L
5709#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006
5710#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L
5711#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007
5712#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L
5713#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008
5714#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L
5715#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009
5716#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L
5717#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a
5718#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L
5719#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b
5720#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L
5721#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c
5722#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L
5723#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d
5724#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L
5725#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e
5726#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L
5727#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f
5728#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L
5729#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010
5730#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L
5731#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011
5732#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L
5733#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012
5734#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L
5735#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013
5736#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L
5737#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014
5738#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L
5739#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015
5740#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L
5741#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016
5742#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L
5743#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017
5744#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L
5745#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018
5746#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L
5747#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019
5748#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L
5749#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a
5750#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L
5751#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b
5752#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L
5753#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c
5754#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L
5755#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d
5756#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L
5757#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e
5758#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L
5759#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f
5760#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L
5761#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004
5762#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L
5763#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005
5764#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L
5765#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006
5766#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L
5767#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007
5768#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L
5769#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008
5770#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L
5771#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009
5772#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L
5773#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a
5774#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L
5775#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b
5776#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L
5777#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c
5778#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L
5779#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d
5780#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L
5781#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000
5782#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L
5783#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001
5784#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L
5785#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002
5786#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L
5787#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003
5788#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L
5789#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008
5790#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L
5791#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b
5792#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L
5793#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e
5794#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L
5795#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016
5796#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L
5797#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015
5798#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L
5799#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013
5800#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L
5801#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017
5802#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L
5803#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000
5804#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L
5805#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003
5806#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L
5807#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018
5808#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L
5809#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014
5810#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L
5811#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011
5812#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L
5813#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e
5814#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L
5815#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000
5816#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L
5817#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a
5818#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L
5819#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b
5820#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L
5821#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c
5822#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L
5823#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d
5824#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L
5825#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e
5826#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L
5827#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f
5828#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L
5829#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001
5830#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L
5831#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002
5832#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L
5833#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003
5834#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L
5835#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004
5836#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L
5837#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005
5838#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L
5839#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006
5840#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L
5841#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007
5842#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L
5843#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008
5844#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L
5845#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009
5846#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L
5847#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010
5848#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L
5849#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015
5850#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L
5851#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016
5852#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L
5853#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017
5854#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L
5855#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011
5856#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L
5857#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012
5858#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L
5859#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013
5860#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L
5861#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014
5862#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L
5863#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018
5864#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L
5865#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b
5866#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L
5867#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019
5868#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L
5869#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a
5870#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L
5871#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c
5872#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L
5873#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d
5874#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L
5875#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003
5876#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L
5877#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000
5878#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L
5879#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004
5880#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L
5881#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008
5882#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L
5883#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009
5884#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L
5885#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d
5886#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L
5887#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e
5888#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L
5889#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013
5890#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L
5891#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014
5892#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L
5893#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019
5894#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L
5895#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a
5896#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L
5897#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e
5898#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL
5899#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000
5900#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L
5901#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004
5902#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L
5903#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005
5904#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L
5905#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006
5906#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L
5907#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007
5908#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L
5909#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008
5910#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L
5911#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a
5912#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L
5913#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009
5914#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L
5915#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c
5916#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L
5917#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b
5918#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L
5919#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e
5920#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L
5921#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d
5922#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L
5923#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019
5924#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L
5925#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f
5926#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L
5927#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b
5928#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L
5929#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a
5930#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L
5931#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d
5932#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L
5933#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c
5934#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L
5935#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f
5936#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L
5937#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e
5938#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L
5939#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c
5940#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L
5941#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010
5942#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L
5943#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014
5944#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L
5945#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019
5946#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L
5947#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b
5948#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L
5949#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a
5950#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L
5951#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003
5952#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L
5953#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002
5954#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L
5955#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005
5956#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L
5957#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004
5958#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L
5959#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007
5960#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L
5961#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006
5962#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L
5963#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009
5964#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L
5965#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008
5966#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L
5967#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001
5968#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L
5969#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000
5970#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L
5971#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a
5972#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L
5973#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e
5974#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L
5975#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012
5976#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L
5977#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017
5978#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL
5979#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000
5980#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L
5981#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c
5982#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L
5983#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004
5984#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L
5985#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008
5986#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L
5987#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009
5988#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL
5989#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000
5990#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L
5991#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004
5992#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L
5993#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005
5994#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L
5995#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008
5996#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L
5997#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b
5998#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L
5999#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009
6000#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L
6001#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a
6002#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L
6003#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c
6004#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L
6005#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f
6006#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L
6007#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d
6008#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L
6009#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e
6010#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L
6011#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004
6012#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L
6013#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007
6014#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L
6015#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005
6016#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L
6017#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006
6018#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L
6019#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000
6020#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L
6021#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003
6022#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L
6023#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001
6024#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L
6025#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002
6026#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L
6027#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000
6028#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L
6029#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001
6030#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L
6031#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002
6032#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L
6033#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003
6034#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L
6035#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001
6036#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L
6037#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000
6038#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L
6039#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003
6040#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L
6041#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002
6042#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L
6043#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005
6044#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L
6045#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004
6046#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L
6047#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007
6048#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L
6049#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006
6050#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L
6051#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a
6052#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L
6053#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008
6054#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L
6055#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007
6056#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L
6057#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003
6058#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L
6059#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004
6060#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L
6061#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000
6062#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L
6063#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000
6064#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L
6065#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001
6066#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L
6067#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002
6068#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L
6069#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003
6070#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L
6071#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001
6072#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L
6073#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000
6074#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L
6075#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003
6076#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L
6077#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002
6078#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L
6079#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005
6080#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L
6081#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004
6082#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L
6083#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007
6084#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L
6085#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006
6086#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L
6087#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a
6088#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L
6089#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008
6090#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L
6091#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007
6092#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L
6093#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003
6094#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L
6095#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004
6096#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L
6097#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000
6098#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L
6099#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000
6100#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L
6101#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001
6102#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L
6103#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002
6104#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L
6105#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003
6106#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L
6107#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001
6108#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L
6109#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000
6110#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L
6111#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003
6112#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L
6113#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002
6114#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L
6115#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005
6116#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L
6117#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004
6118#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L
6119#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007
6120#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L
6121#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006
6122#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L
6123#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a
6124#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L
6125#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008
6126#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L
6127#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007
6128#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L
6129#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003
6130#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L
6131#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004
6132#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L
6133#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000
6134#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L
6135#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000
6136#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L
6137#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001
6138#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L
6139#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002
6140#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L
6141#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003
6142#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L
6143#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001
6144#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L
6145#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000
6146#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L
6147#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003
6148#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L
6149#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002
6150#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L
6151#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005
6152#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L
6153#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004
6154#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L
6155#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007
6156#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L
6157#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006
6158#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L
6159#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a
6160#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L
6161#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008
6162#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L
6163#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007
6164#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L
6165#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003
6166#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L
6167#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004
6168#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L
6169#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000
6170#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L
6171#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000
6172#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L
6173#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001
6174#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L
6175#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002
6176#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L
6177#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003
6178#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L
6179#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001
6180#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L
6181#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000
6182#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L
6183#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003
6184#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L
6185#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002
6186#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L
6187#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005
6188#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L
6189#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004
6190#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L
6191#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007
6192#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L
6193#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006
6194#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L
6195#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a
6196#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L
6197#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008
6198#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L
6199#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007
6200#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L
6201#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003
6202#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L
6203#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004
6204#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L
6205#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000
6206#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L
6207#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000
6208#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L
6209#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001
6210#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L
6211#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002
6212#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L
6213#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003
6214#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L
6215#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001
6216#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L
6217#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000
6218#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L
6219#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003
6220#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L
6221#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002
6222#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L
6223#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005
6224#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L
6225#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004
6226#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L
6227#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007
6228#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L
6229#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006
6230#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L
6231#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a
6232#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L
6233#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008
6234#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L
6235#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007
6236#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L
6237#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003
6238#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L
6239#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004
6240#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L
6241#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000
6242#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L
6243#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000
6244#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L
6245#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001
6246#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L
6247#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002
6248#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L
6249#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003
6250#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L
6251#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001
6252#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L
6253#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000
6254#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L
6255#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003
6256#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L
6257#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002
6258#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L
6259#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005
6260#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L
6261#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004
6262#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L
6263#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007
6264#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L
6265#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006
6266#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L
6267#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a
6268#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L
6269#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008
6270#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L
6271#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007
6272#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L
6273#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003
6274#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L
6275#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004
6276#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L
6277#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000
6278#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L
6279#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000
6280#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L
6281#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001
6282#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L
6283#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002
6284#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L
6285#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003
6286#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L
6287#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001
6288#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L
6289#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000
6290#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L
6291#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003
6292#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L
6293#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002
6294#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L
6295#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005
6296#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L
6297#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004
6298#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L
6299#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007
6300#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L
6301#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006
6302#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L
6303#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a
6304#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L
6305#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008
6306#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L
6307#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007
6308#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L
6309#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003
6310#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L
6311#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004
6312#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L
6313#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000
6314#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L
6315#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000
6316#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L
6317#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001
6318#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L
6319#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002
6320#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L
6321#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003
6322#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L
6323#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001
6324#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L
6325#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000
6326#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L
6327#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003
6328#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L
6329#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002
6330#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L
6331#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005
6332#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L
6333#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004
6334#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L
6335#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007
6336#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L
6337#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006
6338#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L
6339#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a
6340#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L
6341#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008
6342#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L
6343#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007
6344#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L
6345#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003
6346#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L
6347#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004
6348#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L
6349#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000
6350#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L
6351#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000
6352#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L
6353#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001
6354#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L
6355#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002
6356#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L
6357#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003
6358#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L
6359#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001
6360#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L
6361#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000
6362#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L
6363#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003
6364#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L
6365#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002
6366#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L
6367#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005
6368#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L
6369#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004
6370#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L
6371#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007
6372#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L
6373#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006
6374#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L
6375#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a
6376#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L
6377#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008
6378#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L
6379#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007
6380#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L
6381#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003
6382#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L
6383#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004
6384#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L
6385#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000
6386#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L
6387#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000
6388#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L
6389#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001
6390#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L
6391#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002
6392#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L
6393#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003
6394#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L
6395#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001
6396#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L
6397#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000
6398#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L
6399#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003
6400#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L
6401#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002
6402#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L
6403#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005
6404#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L
6405#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004
6406#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L
6407#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007
6408#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L
6409#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006
6410#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L
6411#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a
6412#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L
6413#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008
6414#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L
6415#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007
6416#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L
6417#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003
6418#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L
6419#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004
6420#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L
6421#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000
6422#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L
6423#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000
6424#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L
6425#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001
6426#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L
6427#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002
6428#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L
6429#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003
6430#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L
6431#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001
6432#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L
6433#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000
6434#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L
6435#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003
6436#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L
6437#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002
6438#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L
6439#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005
6440#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L
6441#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004
6442#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L
6443#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007
6444#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L
6445#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006
6446#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L
6447#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a
6448#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L
6449#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008
6450#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L
6451#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007
6452#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L
6453#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003
6454#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L
6455#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004
6456#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L
6457#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000
6458#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L
6459#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000
6460#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L
6461#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001
6462#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L
6463#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002
6464#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L
6465#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003
6466#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L
6467#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001
6468#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L
6469#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000
6470#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L
6471#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003
6472#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L
6473#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002
6474#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L
6475#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005
6476#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L
6477#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004
6478#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L
6479#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007
6480#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L
6481#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006
6482#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L
6483#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a
6484#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L
6485#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008
6486#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L
6487#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007
6488#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L
6489#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003
6490#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L
6491#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004
6492#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L
6493#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000
6494#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L
6495#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000
6496#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L
6497#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001
6498#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L
6499#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002
6500#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L
6501#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003
6502#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L
6503#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001
6504#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L
6505#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000
6506#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L
6507#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003
6508#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L
6509#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002
6510#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L
6511#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005
6512#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L
6513#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004
6514#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L
6515#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007
6516#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L
6517#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006
6518#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L
6519#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a
6520#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L
6521#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008
6522#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L
6523#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007
6524#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L
6525#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003
6526#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L
6527#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004
6528#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L
6529#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000
6530#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L
6531#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000
6532#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L
6533#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001
6534#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L
6535#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002
6536#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L
6537#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003
6538#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L
6539#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001
6540#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L
6541#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000
6542#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L
6543#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003
6544#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L
6545#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002
6546#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L
6547#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005
6548#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L
6549#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004
6550#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L
6551#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007
6552#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L
6553#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006
6554#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L
6555#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a
6556#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L
6557#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008
6558#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L
6559#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007
6560#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L
6561#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003
6562#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L
6563#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004
6564#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L
6565#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000
6566#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L
6567#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000
6568#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L
6569#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001
6570#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L
6571#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002
6572#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L
6573#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003
6574#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L
6575#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001
6576#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L
6577#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000
6578#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L
6579#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003
6580#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L
6581#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002
6582#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L
6583#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005
6584#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L
6585#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004
6586#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L
6587#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007
6588#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L
6589#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006
6590#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L
6591#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a
6592#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L
6593#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008
6594#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L
6595#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007
6596#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L
6597#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003
6598#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L
6599#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004
6600#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L
6601#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000
6602#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
6603#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x00000007
6604#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L
6605#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000006
6606#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000001L
6607#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x00000000
6608#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
6609#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x00000002
6610#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000002L
6611#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x00000001
6612#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L
6613#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x00000004
6614#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x00002000L
6615#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0x0000000d
6616#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L
6617#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x00000009
6618#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L
6619#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x00000003
6620#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L
6621#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x00000002
6622#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L
6623#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0x0000000a
6624#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L
6625#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0x0000000b
6626#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L
6627#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0x0000000c
6628#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L
6629#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x00000008
6630#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000c0L
6631#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x00000006
6632#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L
6633#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x00000012
6634#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L
6635#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x00000016
6636#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L
6637#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x00000013
6638#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L
6639#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x00000017
6640#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000L
6641#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x00000018
6642#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L
6643#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x00000011
6644#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L
6645#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x00000015
6646#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
6647#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x00000010
6648#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L
6649#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x00000014
6650#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007c0L
6651#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x00000006
6652#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L
6653#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x00000000
6654#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003eL
6655#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x00000001
6656#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
6657#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x00000000
6658#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000eL
6659#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x00000001
6660#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L
6661#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x00000009
6662#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
6663#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x00000008
6664#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L
6665#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x00000017
6666#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L
6667#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x0000001f
6668#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L
6669#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0x0000000f
6670#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x00100000L
6671#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x00000014
6672#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L
6673#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x00000013
6674#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L
6675#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x00000011
6676#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L
6677#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x00000010
6678#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L
6679#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x00000012
6680#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L
6681#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x00000015
6682#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L
6683#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x00000016
6684#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001c00L
6685#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0x0000000a
6686#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000L
6687#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x00000018
6688#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
6689#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x00000007
6690#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x02000000L
6691#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x00000019
6692#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
6693#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x00000010
6694#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
6695#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x00000014
6696#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
6697#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x00000018
6698#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000e0000L
6699#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x00000011
6700#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00e00000L
6701#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x00000015
6702#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000fL
6703#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x00000000
6704#define PCIE_DATA__PCIE_DATA_MASK 0xffffffffL
6705#define PCIE_DATA__PCIE_DATA__SHIFT 0x00000000
6706#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000L
6707#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x00000010
6708#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0x000000ffL
6709#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x00000000
6710#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x00000100L
6711#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x00000008
6712#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
6713#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x0000000b
6714#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L
6715#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x0000000c
6716#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L
6717#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x0000000d
6718#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
6719#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x00000008
6720#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
6721#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0x0000000f
6722#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
6723#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0x0000000e
6724#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
6725#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x00000010
6726#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
6727#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x00000000
6728#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
6729#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x00000007
6730#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
6731#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x00000005
6732#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
6733#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x00000001
6734#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
6735#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x00000006
6736#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
6737#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x00000004
6738#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
6739#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0x0000000c
6740#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
6741#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x00000008
6742#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00ff0000L
6743#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x00000010
6744#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000L
6745#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x00000018
6746#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x0000001fL
6747#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x00000000
6748#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000ffL
6749#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x00000000
6750#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6751#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6752#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6753#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6754#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6755#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6756#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6757#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6758#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6759#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6760#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6761#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6762#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6763#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6764#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL
6765#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000
6766#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000ffL
6767#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x00000000
6768#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000ff00L
6769#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x00000008
6770#define PCIE_FC_NP__NPD_CREDITS_MASK 0x000000ffL
6771#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x00000000
6772#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0000ff00L
6773#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x00000008
6774#define PCIE_FC_P__PD_CREDITS_MASK 0x000000ffL
6775#define PCIE_FC_P__PD_CREDITS__SHIFT 0x00000000
6776#define PCIE_FC_P__PH_CREDITS_MASK 0x0000ff00L
6777#define PCIE_FC_P__PH_CREDITS__SHIFT 0x00000008
6778#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L
6779#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000
6780#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L
6781#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001
6782#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L
6783#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002
6784#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L
6785#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003
6786#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L
6787#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004
6788#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L
6789#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005
6790#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L
6791#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006
6792#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L
6793#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007
6794#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L
6795#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008
6796#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L
6797#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009
6798#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L
6799#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a
6800#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L
6801#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b
6802#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L
6803#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c
6804#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L
6805#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d
6806#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L
6807#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e
6808#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L
6809#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f
6810#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001ffffL
6811#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x00000000
6812#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffffL
6813#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x00000000
6814#define PCIE_INDEX__PCIE_INDEX_MASK 0x000000ffL
6815#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x00000000
6816#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
6817#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x00000000
6818#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
6819#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x00000002
6820#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x00000080L
6821#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x00000007
6822#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
6823#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x00000004
6824#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
6825#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x00000001
6826#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
6827#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x00000006
6828#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x00000100L
6829#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x00000008
6830#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
6831#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x00000003
6832#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
6833#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x00000000
6834#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
6835#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x00000002
6836#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x00000080L
6837#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x00000007
6838#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
6839#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x00000004
6840#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
6841#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x00000001
6842#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
6843#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x00000006
6844#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x00000100L
6845#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x00000008
6846#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
6847#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x00000003
6848#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000fc00L
6849#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0x0000000a
6850#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000L
6851#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x00000016
6852#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003f0000L
6853#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x00000010
6854#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003f0L
6855#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x00000004
6856#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000fL
6857#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x00000000
6858#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
6859#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x00000000
6860#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
6861#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x00000005
6862#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
6863#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x00000001
6864#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
6865#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0x0000000a
6866#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
6867#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x00000006
6868#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
6869#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x00000009
6870#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
6871#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x00000008
6872#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
6873#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x00000003
6874#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
6875#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x00000004
6876#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
6877#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x00000007
6878#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
6879#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x00000002
6880#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
6881#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x00000018
6882#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000fffL
6883#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x00000000
6884#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00fff000L
6885#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0x0000000c
6886#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
6887#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x00000011
6888#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
6889#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x00000012
6890#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
6891#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x00000016
6892#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
6893#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x00000014
6894#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L
6895#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x00000013
6896#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
6897#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x00000010
6898#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
6899#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x0000001a
6900#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000c000L
6901#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0x0000000e
6902#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
6903#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x0000001f
6904#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
6905#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
6906#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0x0000000c
6907#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0x0000000b
6908#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
6909#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x0000001b
6910#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
6911#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0x0000000a
6912#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
6913#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x00000007
6914#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
6915#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x00000008
6916#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
6917#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x0000001c
6918#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
6919#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x00000019
6920#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
6921#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x00000015
6922#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
6923#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x00000006
6924#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
6925#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x0000001d
6926#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003fL
6927#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x00000000
6928#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
6929#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x00000017
6930#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
6931#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0x0000000d
6932#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
6933#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x00000009
6934#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
6935#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x00000012
6936#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
6937#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x00000013
6938#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
6939#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x00000008
6940#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000c0L
6941#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x00000006
6942#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L
6943#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x00000010
6944#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
6945#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x00000009
6946#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
6947#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x00000004
6948#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
6949#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x00000017
6950#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L
6951#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0x0000000c
6952#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000c000L
6953#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0x0000000e
6954#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
6955#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x0000000a
6956#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
6957#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x00000015
6958#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
6959#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x0000001e
6960#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
6961#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x00000018
6962#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
6963#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x00000011
6964#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L
6965#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x0000001f
6966#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
6967#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x00000003
6968#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
6969#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0x0000000b
6970#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
6971#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x00000005
6972#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L
6973#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x00000016
6974#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
6975#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x00000001
6976#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
6977#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x00000000
6978#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000L
6979#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x0000001a
6980#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
6981#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x00000019
6982#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L
6983#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L
6984#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x00000010
6985#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x00000004
6986#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
6987#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0x0000000a
6988#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L
6989#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x00000008
6990#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
6991#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x00000018
6992#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
6993#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x00000006
6994#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L
6995#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x00000011
6996#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003c0000L
6997#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x00000012
6998#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
6999#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x00000007
7000#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x00800000L
7001#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x00000017
7002#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
7003#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0x0000000e
7004#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L
7005#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x00000005
7006#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
7007#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0x0000000d
7008#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
7009#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x00000000
7010#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L
7011#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0x0000000f
7012#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
7013#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x00000016
7014#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L
7015#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0x0000000b
7016#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L
7017#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0x0000000c
7018#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000L
7019#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x0000001a
7020#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003fL
7021#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x00000000
7022#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000fc0L
7023#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x00000006
7024#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003f000L
7025#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0x0000000c
7026#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00fc0000L
7027#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x00000012
7028#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000f0L
7029#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x00000004
7030#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
7031#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x00000018
7032#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
7033#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x00000019
7034#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
7035#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x0000001b
7036#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
7037#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x0000001c
7038#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
7039#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x00000001
7040#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
7041#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x0000001e
7042#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
7043#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x0000001d
7044#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
7045#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x00000014
7046#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
7047#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x0000001f
7048#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
7049#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x00000011
7050#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000f00L
7051#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x00000008
7052#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
7053#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x00000017
7054#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000f000L
7055#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0x0000000c
7056#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000c0000L
7057#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x00000012
7058#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
7059#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x00000010
7060#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
7061#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x00000002
7062#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
7063#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x00000003
7064#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
7065#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x00000015
7066#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
7067#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x00000016
7068#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L
7069#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x00000013
7070#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L
7071#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x00000000
7072#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001f80L
7073#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x00000007
7074#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007e000L
7075#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0x0000000d
7076#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007eL
7077#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x00000001
7078#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L
7079#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x00000000
7080#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001f80L
7081#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x00000007
7082#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007e000L
7083#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0x0000000d
7084#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007eL
7085#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x00000001
7086#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01f80000L
7087#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x00000013
7088#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000L
7089#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x00000019
7090#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000ffffL
7091#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x00000000
7092#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000L
7093#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x00000010
7094#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L
7095#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x00000010
7096#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
7097#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x00000013
7098#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
7099#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x00000015
7100#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
7101#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x00000012
7102#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
7103#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x00000017
7104#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
7105#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x00000011
7106#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
7107#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
7108#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x00000004
7109#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x00000000
7110#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
7111#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x00000007
7112#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
7113#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x00000008
7114#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
7115#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0x0000000a
7116#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
7117#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x00000009
7118#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
7119#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0x0000000b
7120#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
7121#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0x0000000f
7122#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
7123#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0x0000000e
7124#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
7125#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x00000014
7126#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
7127#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0x0000000d
7128#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
7129#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0x0000000c
7130#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000L
7131#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x00000018
7132#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
7133#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x00000009
7134#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00ff0000L
7135#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x00000010
7136#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000ffL
7137#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
7138#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x00000008
7139#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x00000000
7140#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L
7141#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x00000011
7142#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L
7143#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x00000016
7144#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L
7145#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x0000001a
7146#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L
7147#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x00000010
7148#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L
7149#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x0000000d
7150#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L
7151#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x00000018
7152#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L
7153#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x0000001f
7154#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L
7155#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x0000001e
7156#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L
7157#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x0000000f
7158#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L
7159#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x00000008
7160#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L
7161#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x00000006
7162#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L
7163#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x00000007
7164#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L
7165#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x00000005
7166#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
7167#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x00000000
7168#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
7169#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x00000001
7170#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L
7171#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x00000009
7172#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L
7173#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x0000001c
7174#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L
7175#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x0000001d
7176#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L
7177#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x0000001b
7178#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L
7179#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x00000012
7180#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L
7181#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x00000014
7182#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L
7183#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x00000013
7184#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L
7185#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x00000015
7186#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L
7187#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x0000000c
7188#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000c00L
7189#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x0000000a
7190#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L
7191#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x00000017
7192#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L
7193#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x00000002
7194#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L
7195#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x00000003
7196#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003fL
7197#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x00000000
7198#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003f00L
7199#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x00000008
7200#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003f0000L
7201#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x00000010
7202#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000L
7203#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x00000018
7204#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003fL
7205#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x00000000
7206#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003f00L
7207#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x00000008
7208#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003f0000L
7209#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x00000010
7210#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000L
7211#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x00000018
7212#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003fL
7213#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x00000000
7214#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003f00L
7215#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x00000008
7216#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003f0000L
7217#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x00000010
7218#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000L
7219#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x00000018
7220#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003fL
7221#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x00000000
7222#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003f00L
7223#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x00000008
7224#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003f0000L
7225#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x00000010
7226#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000L
7227#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x00000018
7228#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003f0000L
7229#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x00000010
7230#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000L
7231#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x00000018
7232#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003fL
7233#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x00000000
7234#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003f00L
7235#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x00000008
7236#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003fL
7237#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x00000000
7238#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003f00L
7239#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x00000008
7240#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003f0000L
7241#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x00000010
7242#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000L
7243#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x00000018
7244#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003fL
7245#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x00000000
7246#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003f00L
7247#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x00000008
7248#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003f0000L
7249#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x00000010
7250#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000L
7251#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x00000018
7252#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003fL
7253#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x00000000
7254#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003f00L
7255#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x00000008
7256#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003f0000L
7257#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x00000010
7258#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000L
7259#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x00000018
7260#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003fL
7261#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x00000000
7262#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003f00L
7263#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x00000008
7264#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003f0000L
7265#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x00000010
7266#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000L
7267#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x00000018
7268#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003fL
7269#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x00000000
7270#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003f00L
7271#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x00000008
7272#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003f0000L
7273#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x00000010
7274#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000L
7275#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x00000018
7276#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003fL
7277#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x00000000
7278#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003f00L
7279#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x00000008
7280#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003f0000L
7281#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x00000010
7282#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000L
7283#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x00000018
7284#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003fL
7285#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x00000000
7286#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003f00L
7287#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x00000008
7288#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003f0000L
7289#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x00000010
7290#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000L
7291#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x00000018
7292#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000e0L
7293#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x00000005
7294#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001cL
7295#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x00000002
7296#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L
7297#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x00000000
7298#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L
7299#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x00000001
7300#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000ffffL
7301#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x00000000
7302#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000L
7303#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x00000010
7304#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
7305#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x0000001c
7306#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00c00000L
7307#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x00000016
7308#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
7309#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x00000011
7310#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
7311#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x00000004
7312#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
7313#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0x0000000d
7314#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
7315#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x00000018
7316#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
7317#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x00000019
7318#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
7319#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0x0000000b
7320#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000L
7321#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x0000001e
7322#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
7323#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x00000010
7324#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
7325#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x00000013
7326#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
7327#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0x0000000c
7328#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
7329#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x00000006
7330#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
7331#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x00000007
7332#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
7333#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x00000014
7334#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
7335#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x00000005
7336#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
7337#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x00000008
7338#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
7339#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x0000001a
7340#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
7341#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x0000001b
7342#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
7343#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x00000015
7344#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000fL
7345#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x00000000
7346#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
7347#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x00000012
7348#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
7349#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x0000001d
7350#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000ffffL
7351#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x00000000
7352#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000L
7353#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x00000010
7354#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L
7355#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0x0000000d
7356#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L
7357#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0x0000000c
7358#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x00000008L
7359#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x00000003
7360#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000c000L
7361#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0x0000000e
7362#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L
7363#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x00000004
7364#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L
7365#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x00000006
7366#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L
7367#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x00000007
7368#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L
7369#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x00000005
7370#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L
7371#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x00000008
7372#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L
7373#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x00000000
7374#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x00000004L
7375#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x00000002
7376#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L
7377#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x00000001
7378#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000ffffL
7379#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x00000000
7380#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000f00L
7381#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x00000008
7382#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000f0L
7383#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x00000004
7384#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L
7385#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014
7386#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L
7387#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c
7388#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L
7389#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010
7390#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0f000000L
7391#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x00000018
7392#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000fL
7393#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x00000000
7394#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000f00L
7395#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x00000008
7396#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000f0L
7397#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x00000004
7398#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L
7399#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014
7400#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L
7401#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c
7402#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L
7403#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010
7404#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0f000000L
7405#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x00000018
7406#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000fL
7407#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x00000000
7408#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L
7409#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010
7410#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000L
7411#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018
7412#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000ffL
7413#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x00000000
7414#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000ff00L
7415#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x00000008
7416#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L
7417#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010
7418#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000L
7419#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018
7420#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000ffL
7421#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x00000000
7422#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000ff00L
7423#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x00000008
7424#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L
7425#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010
7426#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000L
7427#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018
7428#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000ffL
7429#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x00000000
7430#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000ff00L
7431#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x00000008
7432#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L
7433#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010
7434#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000L
7435#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018
7436#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000ffL
7437#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x00000000
7438#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000ff00L
7439#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x00000008
7440#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L
7441#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010
7442#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000L
7443#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018
7444#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000ffL
7445#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x00000000
7446#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000ff00L
7447#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x00000008
7448#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00ff0000L
7449#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x00000010
7450#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000L
7451#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x00000018
7452#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000ffL
7453#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x00000000
7454#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000ff00L
7455#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x00000008
7456#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00ff0000L
7457#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x00000010
7458#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000L
7459#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x00000018
7460#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000ffL
7461#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x00000000
7462#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000ff00L
7463#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x00000008
7464#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffffL
7465#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x00000000
7466#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffffL
7467#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x00000000
7468#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffffL
7469#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x00000000
7470#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffffL
7471#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x00000000
7472#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffffL
7473#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x00000000
7474#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffffL
7475#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x00000000
7476#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffffL
7477#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x00000000
7478#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffffL
7479#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x00000000
7480#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffffL
7481#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x00000000
7482#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffffL
7483#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x00000000
7484#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffffL
7485#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x00000000
7486#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffffL
7487#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x00000000
7488#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffffL
7489#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x00000000
7490#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffffL
7491#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x00000000
7492#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L
7493#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x00000000
7494#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L
7495#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x00000002
7496#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L
7497#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x00000001
7498#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L
7499#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000
7500#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L
7501#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001
7502#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L
7503#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002
7504#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L
7505#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003
7506#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L
7507#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004
7508#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L
7509#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005
7510#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L
7511#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006
7512#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L
7513#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007
7514#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L
7515#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008
7516#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L
7517#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009
7518#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L
7519#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a
7520#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L
7521#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b
7522#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L
7523#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c
7524#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L
7525#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d
7526#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L
7527#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e
7528#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L
7529#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f
7530#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000ffL
7531#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x00000000
7532#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000L
7533#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x00000010
7534#define PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffffL
7535#define PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x00000000
7536#define PCIE_PORT_INDEX__PCIE_INDEX_MASK 0x000000ffL
7537#define PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x00000000
7538#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007f00L
7539#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x00000008
7540#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
7541#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x00000001
7542#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
7543#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x00000002
7544#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
7545#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x00000003
7546#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
7547#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x00000005
7548#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
7549#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x00000004
7550#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x00000040L
7551#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x00000006
7552#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
7553#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x00000000
7554#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007eL
7555#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x00000001
7556#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
7557#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x00000000
7558#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0x000f0000L
7559#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x00000010
7560#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000ffffL
7561#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x00000000
7562#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffffL
7563#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x00000000
7564#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffffL
7565#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x00000000
7566#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffffL
7567#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x00000000
7568#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffffL
7569#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x00000000
7570#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffffL
7571#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x00000000
7572#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffffL
7573#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x00000000
7574#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffffL
7575#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x00000000
7576#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffffL
7577#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x00000000
7578#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffffL
7579#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x00000000
7580#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffffL
7581#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x00000000
7582#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffffL
7583#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x00000000
7584#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffffL
7585#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x00000000
7586#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffffL
7587#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x00000000
7588#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffffL
7589#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x00000000
7590#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffffL
7591#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x00000000
7592#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffffL
7593#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x00000000
7594#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000ffffL
7595#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x00000000
7596#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000ffL
7597#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x00000000
7598#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffffL
7599#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x00000000
7600#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000010L
7601#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x00000004
7602#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000L
7603#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x00000010
7604#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x00000060L
7605#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x00000005
7606#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000c000L
7607#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0x0000000e
7608#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L
7609#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x00000000
7610#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00000f80L
7611#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x00000007
7612#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x00000006L
7613#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x00000001
7614#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000008L
7615#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x00000003
7616#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000ffffL
7617#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x00000000
7618#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000L
7619#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x00000010
7620#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000ffffL
7621#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x00000000
7622#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffffL
7623#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x00000000
7624#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000ff00L
7625#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x00000008
7626#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000ffL
7627#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x00000000
7628#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffffL
7629#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x00000000
7630#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffffL
7631#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x00000000
7632#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
7633#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x0000000f
7634#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
7635#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0x0000000b
7636#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
7637#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0x0000000c
7638#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
7639#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0x0000000d
7640#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
7641#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x00000000
7642#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
7643#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x00000010
7644#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000cL
7645#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x00000002
7646#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
7647#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x00000004
7648#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
7649#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0x0000000e
7650#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000c0L
7651#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x00000006
7652#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
7653#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x00000008
7654#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
7655#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x00000001
7656#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
7657#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x00000002
7658#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
7659#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x00000003
7660#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
7661#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x00000000
7662#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffffL
7663#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x00000000
7664#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L
7665#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x00000003
7666#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
7667#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x00000000
7668#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L
7669#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x00000005
7670#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L
7671#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x00000004
7672#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L
7673#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x00000001
7674#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L
7675#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x00000002
7676#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
7677#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x00000004
7678#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
7679#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x00000003
7680#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
7681#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x00000002
7682#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
7683#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x00000000
7684#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
7685#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x00000001
7686#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
7687#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0x0000000f
7688#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L
7689#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0x0000000e
7690#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
7691#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0x0000000c
7692#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
7693#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x00000001
7694#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
7695#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x00000004
7696#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
7697#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0x0000000a
7698#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
7699#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x00000005
7700#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
7701#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x00000017
7702#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
7703#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x00000003
7704#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
7705#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x00000006
7706#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
7707#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x00000018
7708#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
7709#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x00000000
7710#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
7711#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0x0000000b
7712#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
7713#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x00000007
7714#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
7715#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x00000008
7716#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
7717#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x00000016
7718#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
7719#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x00000002
7720#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
7721#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x00000019
7722#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
7723#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x00000015
7724#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
7725#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x00000009
7726#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
7727#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0x0000000d
7728#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
7729#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x00000014
7730#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
7731#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
7732#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x00000013
7733#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x00000010
7734#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000fffL
7735#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x00000000
7736#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00ff0000L
7737#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x00000010
7738#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000fffL
7739#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x00000000
7740#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00ff0000L
7741#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x00000010
7742#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000fffL
7743#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x00000000
7744#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00ff0000L
7745#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x00000010
7746#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000fffL
7747#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x00000000
7748#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffffL
7749#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x00000000
7750#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffffL
7751#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x00000000
7752#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffffL
7753#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x00000000
7754#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffffL
7755#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x00000000
7756#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffffL
7757#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x00000000
7758#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffffL
7759#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x00000000
7760#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00ffffffL
7761#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x00000000
7762#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
7763#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x00000018
7764#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffffL
7765#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x00000000
7766#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L
7767#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x00000006
7768#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L
7769#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x00000005
7770#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L
7771#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0x0000000a
7772#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L
7773#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x00000007
7774#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L
7775#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x00000009
7776#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L
7777#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x00000004
7778#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
7779#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x00000000
7780#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L
7781#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001
7782#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L
7783#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x00000002
7784#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L
7785#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0x0000000b
7786#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L
7787#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0x0000000c
7788#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L
7789#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x00000008
7790#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L
7791#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x00000003
7792#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x00000040L
7793#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x00000006
7794#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x00000020L
7795#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x00000005
7796#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x00000400L
7797#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0x0000000a
7798#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x00000080L
7799#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x00000007
7800#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x00000200L
7801#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x00000009
7802#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x00000010L
7803#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x00000004
7804#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x00000001L
7805#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x00000000
7806#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L
7807#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001
7808#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x00000004L
7809#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x00000002
7810#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x00000800L
7811#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0x0000000b
7812#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x00001000L
7813#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0x0000000c
7814#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x00000100L
7815#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x00000008
7816#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x00000008L
7817#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x00000003
7818#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x00000040L
7819#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x00000006
7820#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x00000020L
7821#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x00000005
7822#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x00000400L
7823#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0x0000000a
7824#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x00000080L
7825#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x00000007
7826#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x00000200L
7827#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x00000009
7828#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x00000010L
7829#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x00000004
7830#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x00000001L
7831#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x00000000
7832#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L
7833#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001
7834#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x00000004L
7835#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x00000002
7836#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x00000800L
7837#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0x0000000b
7838#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x00001000L
7839#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0x0000000c
7840#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x00000100L
7841#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x00000008
7842#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x00000008L
7843#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x00000003
7844#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffffL
7845#define PCIE_STRAP_F3__RESERVED__SHIFT 0x00000000
7846#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffffL
7847#define PCIE_STRAP_F4__RESERVED__SHIFT 0x00000000
7848#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffffL
7849#define PCIE_STRAP_F5__RESERVED__SHIFT 0x00000000
7850#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffffL
7851#define PCIE_STRAP_F6__RESERVED__SHIFT 0x00000000
7852#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffffL
7853#define PCIE_STRAP_F7__RESERVED__SHIFT 0x00000000
7854#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x00000080L
7855#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x00000007
7856#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007fL
7857#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x00000000
7858#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L
7859#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x00000001
7860#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L
7861#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x00000003
7862#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
7863#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x00000002
7864#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
7865#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x00000018
7866#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x02000000L
7867#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x00000019
7868#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L
7869#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x0000001a
7870#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000L
7871#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x0000001e
7872#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0x0000000fL
7873#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x00000000
7874#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x00001f00L
7875#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x00000008
7876#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
7877#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x0000001d
7878#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x00002000L
7879#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x0000000d
7880#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x00008000L
7881#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x0000000f
7882#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x00004000L
7883#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0x0000000e
7884#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L
7885#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x0000001c
7886#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L
7887#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x00000000
7888#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L
7889#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x0000001d
7890#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L
7891#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x0000001c
7892#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000fffL
7893#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
7894#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0x0000000c
7895#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x00000000
7896#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
7897#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x00000016
7898#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
7899#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x00000014
7900#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
7901#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x00000017
7902#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
7903#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0x0000000f
7904#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
7905#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x00000015
7906#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
7907#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0x0000000e
7908#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
7909#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0x0000000c
7910#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000c00L
7911#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0x0000000a
7912#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000fffL
7913#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x00000000
7914#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00ff0000L
7915#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x00000010
7916#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000fffL
7917#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x00000000
7918#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00ff0000L
7919#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x00000010
7920#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000fffL
7921#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x00000000
7922#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00ff0000L
7923#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x00000010
7924#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
7925#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x00000008
7926#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
7927#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x00000018
7928#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
7929#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x00000004
7930#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
7931#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x00000014
7932#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
7933#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x00000000
7934#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
7935#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x00000010
7936#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000fffL
7937#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x00000000
7938#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00ff0000L
7939#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x00000010
7940#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000fffL
7941#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x00000000
7942#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00ff0000L
7943#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x00000010
7944#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000fffL
7945#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x00000000
7946#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00ff0000L
7947#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x00000010
7948#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
7949#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x00000014
7950#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
7951#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x00000015
7952#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
7953#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x00000012
7954#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
7955#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x00000013
7956#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
7957#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x00000010
7958#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
7959#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x00000011
7960#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
7961#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x00000004
7962#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
7963#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x00000005
7964#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
7965#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x00000002
7966#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
7967#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x00000003
7968#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
7969#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x00000000
7970#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
7971#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x00000001
7972#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffffL
7973#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x00000000
7974#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffffL
7975#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x00000000
7976#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffffL
7977#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x00000000
7978#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffffL
7979#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x00000000
7980#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
7981#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x00000000
7982#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000L
7983#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
7984#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0x0000000f
7985#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x00000010
7986#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000ff00L
7987#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x00000008
7988#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000f8L
7989#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x00000003
7990#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
7991#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x00000000
7992#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
7993#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x0000001f
7994#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000L
7995#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x00000018
7996#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
7997#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x0000001e
7998#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0fff0000L
7999#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x00000010
8000#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000fffL
8001#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x00000000
8002#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00ffffffL
8003#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x00000000
8004#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L
8005#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x00000003
8006#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L
8007#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x00000000
8008#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L
8009#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x00000002
8010#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L
8011#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x00000001
8012#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L
8013#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x00000006
8014#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L
8015#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x00000004
8016#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L
8017#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x00000005
8018#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000fffffL
8019#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x00000000
8020#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
8021#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x0000001f
8022#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000fffffL
8023#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x00000000
8024#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000fffffL
8025#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x00000000
8026#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
8027#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x0000001f
8028#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000fffffL
8029#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x00000000
8030#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000fffffL
8031#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x00000000
8032#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
8033#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x0000001f
8034#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000fffffL
8035#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x00000000
8036#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000fffffL
8037#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x00000000
8038#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
8039#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x0000001f
8040#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000fffffL
8041#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x00000000
8042#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000L
8043#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x00000010
8044#define PEER_REG_RANGE0__START_ADDR_MASK 0x0000ffffL
8045#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x00000000
8046#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000L
8047#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x00000010
8048#define PEER_REG_RANGE1__START_ADDR_MASK 0x0000ffffL
8049#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x00000000
8050#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x00000010L
8051#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x00000004
8052#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x00000020L
8053#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x00000005
8054#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x00000002L
8055#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x00000001
8056#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x00000008L
8057#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x00000003
8058#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x00000001L
8059#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x00000000
8060#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x00000004L
8061#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x00000002
8062#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0x0000000eL
8063#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x00000001
8064#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x00100000L
8065#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x00000014
8066#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x00007c00L
8067#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0x0000000a
8068#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x00008000L
8069#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0x0000000f
8070#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x0000001fL
8071#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x00000000
8072#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x000001e0L
8073#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x00000005
8074#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000L
8075#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x00000019
8076#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x00000001L
8077#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x00000000
8078#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x00001000L
8079#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0x0000000c
8080#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x00000004L
8081#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x00000002
8082#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x00000800L
8083#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0x0000000b
8084#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x00000002L
8085#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x00000001
8086#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x00000200L
8087#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x00000009
8088#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x00000020L
8089#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x00000005
8090#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x00000040L
8091#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x00000006
8092#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x00000080L
8093#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x00000007
8094#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x00000100L
8095#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x00000008
8096#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x00000018L
8097#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x00000003
8098#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x00000400L
8099#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0x0000000a
8100#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x00000001L
8101#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x00000000
8102#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x00001000L
8103#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0x0000000c
8104#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x00000004L
8105#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x00000002
8106#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x00000800L
8107#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0x0000000b
8108#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x00000002L
8109#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x00000001
8110#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x00000200L
8111#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x00000009
8112#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x00000020L
8113#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x00000005
8114#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x00000040L
8115#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x00000006
8116#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x00000080L
8117#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x00000007
8118#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x00000100L
8119#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x00000008
8120#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x00000018L
8121#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x00000003
8122#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x00000400L
8123#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0x0000000a
8124#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffffL
8125#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x00000000
8126
8127#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
new file mode 100644
index 000000000000..ae798f768853
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
@@ -0,0 +1,4457 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef DCE_6_0_D_H
24#define DCE_6_0_D_H
25
26#define ixATTR00 0x0000
27#define ixATTR01 0x0001
28#define ixATTR02 0x0002
29#define ixATTR03 0x0003
30#define ixATTR04 0x0004
31#define ixATTR05 0x0005
32#define ixATTR06 0x0006
33#define ixATTR07 0x0007
34#define ixATTR08 0x0008
35#define ixATTR09 0x0009
36#define ixATTR0A 0x000A
37#define ixATTR0B 0x000B
38#define ixATTR0C 0x000C
39#define ixATTR0D 0x000D
40#define ixATTR0E 0x000E
41#define ixATTR0F 0x000F
42#define ixATTR10 0x0010
43#define ixATTR11 0x0011
44#define ixATTR12 0x0012
45#define ixATTR13 0x0013
46#define ixATTR14 0x0014
47#define ixAUDIO_DESCRIPTOR0 0x0001
48#define ixAUDIO_DESCRIPTOR10 0x000B
49#define ixAUDIO_DESCRIPTOR1 0x0002
50#define ixAUDIO_DESCRIPTOR11 0x000C
51#define ixAUDIO_DESCRIPTOR12 0x000D
52#define ixAUDIO_DESCRIPTOR13 0x000E
53#define ixAUDIO_DESCRIPTOR2 0x0003
54#define ixAUDIO_DESCRIPTOR3 0x0004
55#define ixAUDIO_DESCRIPTOR4 0x0005
56#define ixAUDIO_DESCRIPTOR5 0x0006
57#define ixAUDIO_DESCRIPTOR6 0x0007
58#define ixAUDIO_DESCRIPTOR7 0x0008
59#define ixAUDIO_DESCRIPTOR8 0x0009
60#define ixAUDIO_DESCRIPTOR9 0x000A
61#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
62#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
63#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
64#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
65#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
66#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
67#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
68#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
69#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
70#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
71#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000
72#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
73#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
74#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
75#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
76#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
77#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
78#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
79#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
80#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A
81#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B
82#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C
83#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D
84#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E
85#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F
86#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
87#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
88#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
89#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
90#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
91#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
92#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
93#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
94#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
95#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
96#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
97#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A
98#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B
99#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C
100#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D
101#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E
102#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F
103#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
104#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
105#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
106#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
107#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
108#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
109#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
110#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
111#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
112#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A
113#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B
114#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C
115#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D
116#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E
117#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F
118#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
119#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
120#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
121#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
122#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D
123#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E
124#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E
125#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
126#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09
127#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B
128#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A
129#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
130#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
131#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
132#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF
133#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
134#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
135#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
136#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
137#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05
138#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F
139#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B
140#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04
141#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A
142#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
143#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
144#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
145#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
146#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
147#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
148#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
149#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C
150#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B
151#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
152#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
153#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
154#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
155#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
156#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
157#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
158#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A
159#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
160#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
161#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
162#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
163#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
164#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C
165#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D
166#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E
167#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F
168#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
169#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
170#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
171#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
172#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
173#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
174#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09
175#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C
176#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E
177#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02
178#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04
179#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00
180#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A
181#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B
182#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C
183#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D
184#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E
185#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F
186#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
187#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
188#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
189#define ixAZALIA_FIFO_SIZE_CONTROL 0x0000
190#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001
191#define ixAZALIA_STREAM_DEBUG 0x0005
192#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002
193#define ixCRT00 0x0000
194#define ixCRT01 0x0001
195#define ixCRT02 0x0002
196#define ixCRT03 0x0003
197#define ixCRT04 0x0004
198#define ixCRT05 0x0005
199#define ixCRT06 0x0006
200#define ixCRT07 0x0007
201#define ixCRT08 0x0008
202#define ixCRT09 0x0009
203#define ixCRT0A 0x000A
204#define ixCRT0B 0x000B
205#define ixCRT0C 0x000C
206#define ixCRT0D 0x000D
207#define ixCRT0E 0x000E
208#define ixCRT0F 0x000F
209#define ixCRT10 0x0010
210#define ixCRT11 0x0011
211#define ixCRT12 0x0012
212#define ixCRT13 0x0013
213#define ixCRT14 0x0014
214#define ixCRT15 0x0015
215#define ixCRT16 0x0016
216#define ixCRT17 0x0017
217#define ixCRT18 0x0018
218#define ixCRT1E 0x001E
219#define ixCRT1F 0x001F
220#define ixCRT22 0x0022
221#define ixDCIO_DEBUG10 0x0010
222#define ixDCIO_DEBUG1 0x0001
223#define ixDCIO_DEBUG11 0x0011
224#define ixDCIO_DEBUG12 0x0012
225#define ixDCIO_DEBUG13 0x0013
226#define ixDCIO_DEBUG2 0x0002
227#define ixDCIO_DEBUG3 0x0003
228#define ixDCIO_DEBUG4 0x0004
229#define ixDCIO_DEBUG5 0x0005
230#define ixDCIO_DEBUG6 0x0006
231#define ixDCIO_DEBUG7 0x0007
232#define ixDCIO_DEBUG8 0x0008
233#define ixDCIO_DEBUG9 0x0009
234#define ixDCIO_DEBUGA 0x000A
235#define ixDCIO_DEBUGB 0x000B
236#define ixDCIO_DEBUGC 0x000C
237#define ixDCIO_DEBUGD 0x000D
238#define ixDCIO_DEBUGE 0x000E
239#define ixDCIO_DEBUGF 0x000F
240#define ixDCIO_DEBUG_ID 0x0000
241#define ixDMIF_DEBUG02_CORE0 0x0002
242#define ixDMIF_DEBUG02_CORE1 0x000A
243#define ixDP_AUX1_DEBUG_A 0x0010
244#define ixDP_AUX1_DEBUG_B 0x0011
245#define ixDP_AUX1_DEBUG_C 0x0012
246#define ixDP_AUX1_DEBUG_D 0x0013
247#define ixDP_AUX1_DEBUG_E 0x0014
248#define ixDP_AUX1_DEBUG_F 0x0015
249#define ixDP_AUX1_DEBUG_G 0x0016
250#define ixDP_AUX1_DEBUG_H 0x0017
251#define ixDP_AUX1_DEBUG_I 0x0018
252#define ixDP_AUX2_DEBUG_A 0x0020
253#define ixDP_AUX2_DEBUG_B 0x0021
254#define ixDP_AUX2_DEBUG_C 0x0022
255#define ixDP_AUX2_DEBUG_D 0x0023
256#define ixDP_AUX2_DEBUG_E 0x0024
257#define ixDP_AUX2_DEBUG_F 0x0025
258#define ixDP_AUX2_DEBUG_G 0x0026
259#define ixDP_AUX2_DEBUG_H 0x0027
260#define ixDP_AUX2_DEBUG_I 0x0028
261#define ixDP_AUX3_DEBUG_A 0x0030
262#define ixDP_AUX3_DEBUG_B 0x0031
263#define ixDP_AUX3_DEBUG_C 0x0032
264#define ixDP_AUX3_DEBUG_D 0x0033
265#define ixDP_AUX3_DEBUG_E 0x0034
266#define ixDP_AUX3_DEBUG_F 0x0035
267#define ixDP_AUX3_DEBUG_G 0x0036
268#define ixDP_AUX3_DEBUG_H 0x0037
269#define ixDP_AUX3_DEBUG_I 0x0038
270#define ixDP_AUX4_DEBUG_A 0x0040
271#define ixDP_AUX4_DEBUG_B 0x0041
272#define ixDP_AUX4_DEBUG_C 0x0042
273#define ixDP_AUX4_DEBUG_D 0x0043
274#define ixDP_AUX4_DEBUG_E 0x0044
275#define ixDP_AUX4_DEBUG_F 0x0045
276#define ixDP_AUX4_DEBUG_G 0x0046
277#define ixDP_AUX4_DEBUG_H 0x0047
278#define ixDP_AUX4_DEBUG_I 0x0048
279#define ixDP_AUX5_DEBUG_A 0x0070
280#define ixDP_AUX5_DEBUG_B 0x0071
281#define ixDP_AUX5_DEBUG_C 0x0072
282#define ixDP_AUX5_DEBUG_D 0x0073
283#define ixDP_AUX5_DEBUG_E 0x0074
284#define ixDP_AUX5_DEBUG_F 0x0075
285#define ixDP_AUX5_DEBUG_G 0x0076
286#define ixDP_AUX5_DEBUG_H 0x0077
287#define ixDP_AUX5_DEBUG_I 0x0078
288#define ixDP_AUX6_DEBUG_A 0x0080
289#define ixDP_AUX6_DEBUG_B 0x0081
290#define ixDP_AUX6_DEBUG_C 0x0082
291#define ixDP_AUX6_DEBUG_D 0x0083
292#define ixDP_AUX6_DEBUG_E 0x0084
293#define ixDP_AUX6_DEBUG_F 0x0085
294#define ixDP_AUX6_DEBUG_G 0x0086
295#define ixDP_AUX6_DEBUG_H 0x0087
296#define ixDP_AUX6_DEBUG_I 0x0088
297#define ixFMT_DEBUG0 0x0001
298#define ixFMT_DEBUG1 0x0002
299#define ixFMT_DEBUG2 0x0003
300#define ixFMT_DEBUG_ID 0x0000
301#define ixGRA00 0x0000
302#define ixGRA01 0x0001
303#define ixGRA02 0x0002
304#define ixGRA03 0x0003
305#define ixGRA04 0x0004
306#define ixGRA05 0x0005
307#define ixGRA06 0x0006
308#define ixGRA07 0x0007
309#define ixGRA08 0x0008
310#define ixIDDCCIF02_DBG_DCCIF_C 0x0009
311#define ixIDDCCIF04_DBG_DCCIF_E 0x000B
312#define ixIDDCCIF05_DBG_DCCIF_F 0x000C
313#define ixMVP_DEBUG_12 0x000C
314#define ixMVP_DEBUG_13 0x000D
315#define ixMVP_DEBUG_14 0x000E
316#define ixMVP_DEBUG_15 0x000F
317#define ixMVP_DEBUG_16 0x0010
318#define ixMVP_DEBUG_17 0x0011
319#define ixSEQ00 0x0000
320#define ixSEQ01 0x0001
321#define ixSEQ02 0x0002
322#define ixSEQ03 0x0003
323#define ixSEQ04 0x0004
324#define ixSINK_DESCRIPTION0 0x0005
325#define ixSINK_DESCRIPTION10 0x000F
326#define ixSINK_DESCRIPTION1 0x0006
327#define ixSINK_DESCRIPTION11 0x0010
328#define ixSINK_DESCRIPTION12 0x0011
329#define ixSINK_DESCRIPTION13 0x0012
330#define ixSINK_DESCRIPTION14 0x0013
331#define ixSINK_DESCRIPTION15 0x0014
332#define ixSINK_DESCRIPTION16 0x0015
333#define ixSINK_DESCRIPTION17 0x0016
334#define ixSINK_DESCRIPTION2 0x0007
335#define ixSINK_DESCRIPTION3 0x0008
336#define ixSINK_DESCRIPTION4 0x0009
337#define ixSINK_DESCRIPTION5 0x000A
338#define ixSINK_DESCRIPTION6 0x000B
339#define ixSINK_DESCRIPTION7 0x000C
340#define ixSINK_DESCRIPTION8 0x000D
341#define ixSINK_DESCRIPTION9 0x000E
342#define ixVGADCC_DBG_DCCIF_C 0x007E
343#define mmABM_TEST_DEBUG_DATA 0x169F
344#define mmABM_TEST_DEBUG_INDEX 0x169E
345#define mmAFMT_60958_0 0x1C41
346#define mmAFMT_60958_1 0x1C42
347#define mmAFMT_60958_2 0x1C48
348#define mmAFMT_AUDIO_CRC_CONTROL 0x1C43
349#define mmAFMT_AUDIO_CRC_RESULT 0x1C49
350#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52
351#define mmAFMT_AUDIO_INFO0 0x1C3F
352#define mmAFMT_AUDIO_INFO1 0x1C40
353#define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B
354#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17
355#define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F
356#define mmAFMT_AVI_INFO0 0x1C21
357#define mmAFMT_AVI_INFO1 0x1C22
358#define mmAFMT_AVI_INFO2 0x1C23
359#define mmAFMT_AVI_INFO3 0x1C24
360#define mmAFMT_GENERIC_0 0x1C28
361#define mmAFMT_GENERIC_1 0x1C29
362#define mmAFMT_GENERIC_2 0x1C2A
363#define mmAFMT_GENERIC_3 0x1C2B
364#define mmAFMT_GENERIC_4 0x1C2C
365#define mmAFMT_GENERIC_5 0x1C2D
366#define mmAFMT_GENERIC_6 0x1C2E
367#define mmAFMT_GENERIC_7 0x1C2F
368#define mmAFMT_GENERIC_HDR 0x1C27
369#define mmAFMT_INFOFRAME_CONTROL0 0x1C4D
370#define mmAFMT_INTERRUPT_STATUS 0x1C14
371#define mmAFMT_ISRC1_0 0x1C18
372#define mmAFMT_ISRC1_1 0x1C19
373#define mmAFMT_ISRC1_2 0x1C1A
374#define mmAFMT_ISRC1_3 0x1C1B
375#define mmAFMT_ISRC1_4 0x1C1C
376#define mmAFMT_ISRC2_0 0x1C1D
377#define mmAFMT_ISRC2_1 0x1C1E
378#define mmAFMT_ISRC2_2 0x1C1F
379#define mmAFMT_ISRC2_3 0x1C20
380#define mmAFMT_MPEG_INFO0 0x1C25
381#define mmAFMT_MPEG_INFO1 0x1C26
382#define mmAFMT_RAMP_CONTROL0 0x1C44
383#define mmAFMT_RAMP_CONTROL1 0x1C45
384#define mmAFMT_RAMP_CONTROL2 0x1C46
385#define mmAFMT_RAMP_CONTROL3 0x1C47
386#define mmAFMT_STATUS 0x1C4A
387#define mmAFMT_VBI_PACKET_CONTROL 0x1C4C
388#define mmATTRDR 0x00F0
389#define mmATTRDW 0x00F0
390#define mmATTRX 0x00F0
391#define mmAUX_ARB_CONTROL 0x1882
392#define mmAUX_CONTROL 0x1880
393#define mmAUX_DPHY_RX_CONTROL0 0x188A
394#define mmAUX_DPHY_RX_CONTROL1 0x188B
395#define mmAUX_DPHY_RX_STATUS 0x188D
396#define mmAUX_DPHY_TX_CONTROL 0x1889
397#define mmAUX_DPHY_TX_REF_CONTROL 0x1888
398#define mmAUX_DPHY_TX_STATUS 0x188C
399#define mmAUX_GTC_SYNC_CONTROL 0x188E
400#define mmAUX_GTC_SYNC_DATA 0x1890
401#define mmAUX_INTERRUPT_CONTROL 0x1883
402#define mmAUX_LS_DATA 0x1887
403#define mmAUX_LS_STATUS 0x1885
404#define mmAUXN_IMPCAL 0x190C
405#define mmAUXP_IMPCAL 0x190B
406#define mmAUX_SW_CONTROL 0x1881
407#define mmAUX_SW_DATA 0x1886
408#define mmAUX_SW_STATUS 0x1884
409#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9
410#define mmAZALIA_AUDIO_DTO 0x17BA
411#define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB
412#define mmAZALIA_BDL_DMA_CONTROL 0x17BF
413#define mmAZALIA_CONTROLLER_DEBUG 0x17CF
414#define mmAZALIA_CORB_DMA_CONTROL 0x17C1
415#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA
416#define mmAZALIA_DATA_DMA_CONTROL 0x17BE
417#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5
418#define mmAZALIA_F0_CODEC_DEBUG 0x17DF
419#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
420#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
421#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE
422#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB
423#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC
424#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD
425#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7
426#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA
427#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9
428#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8
429#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6
430#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3
431#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2
432#define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB
433#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC
434#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD
435#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0
436#define mmAZALIA_SCLK_CONTROL 0x17BC
437#define mmAZALIA_STREAM_DATA 0x17E9
438#define mmAZALIA_STREAM_INDEX 0x17E8
439#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD
440#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
441#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
442#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787
443#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786
444#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D
445#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C
446#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793
447#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792
448#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799
449#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798
450#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F
451#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E
452#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9
453#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8
454#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED
455#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC
456#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1
457#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0
458#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5
459#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4
460#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9
461#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8
462#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD
463#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC
464#define mmAZ_TEST_DEBUG_DATA 0x17D1
465#define mmAZ_TEST_DEBUG_INDEX 0x17D0
466#define mmBL1_PWM_ABM_CNTL 0x162E
467#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
468#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F
469#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B
470#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C
471#define mmBL1_PWM_GRP2_REG_LOCK 0x1630
472#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D
473#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A
474#define mmBL1_PWM_USER_LEVEL 0x1629
475#define mmBL_PWM_CNTL 0x191E
476#define mmBL_PWM_CNTL2 0x191F
477#define mmBL_PWM_GRP1_REG_LOCK 0x1921
478#define mmBL_PWM_PERIOD_CNTL 0x1920
479#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE
480#define mmBPHYC_DAC_MACRO_CNTL 0x19FD
481#define mmCC_DC_PIPE_DIS 0x177F
482#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4
483#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43
484#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44
485#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45
486#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46
487#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47
488#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48
489#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49
490#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A
491#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B
492#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C
493#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D
494#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E
495#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78
496#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3
497#define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2
498#define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D
499#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1
500#define mmCRTC0_CRTC_CONTROL 0x1B9C
501#define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9
502#define mmCRTC0_CRTC_COUNT_RESET 0x1BAA
503#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C
504#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6
505#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92
506#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93
507#define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99
508#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98
509#define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B
510#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79
511#define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A
512#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D
513#define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81
514#define mmCRTC0_CRTC_H_SYNC_A 0x1B82
515#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83
516#define mmCRTC0_CRTC_H_SYNC_B 0x1B84
517#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85
518#define mmCRTC0_CRTC_H_TOTAL 0x1B80
519#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E
520#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F
521#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4
522#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB
523#define mmCRTC0_CRTC_MASTER_EN 0x1BC2
524#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF
525#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0
526#define mmCRTC0_CRTC_MVP_STATUS 0x1BC1
527#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5
528#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0
529#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0
530#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2
531#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1
532#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF
533#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3
534#define mmCRTC0_CRTC_STATUS 0x1BA3
535#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6
536#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8
537#define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4
538#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7
539#define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE
540#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B
541#define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD
542#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7
543#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6
544#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC
545#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA
546#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB
547#define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94
548#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95
549#define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96
550#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97
551#define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5
552#define mmCRTC0_CRTC_VBI_END 0x1B86
553#define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D
554#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC
555#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7
556#define mmCRTC0_CRTC_V_SYNC_A 0x1B8E
557#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F
558#define mmCRTC0_CRTC_V_SYNC_B 0x1B90
559#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91
560#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C
561#define mmCRTC0_CRTC_V_TOTAL 0x1B87
562#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A
563#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B
564#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89
565#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88
566#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4
567#define mmCRTC0_DCFE_DBG_SEL 0x1B7E
568#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F
569#define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD
570#define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE
571#define mmCRTC0_PIXEL_RATE_CNTL 0x0140
572#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78
573#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3
574#define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2
575#define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D
576#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1
577#define mmCRTC1_CRTC_CONTROL 0x1E9C
578#define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9
579#define mmCRTC1_CRTC_COUNT_RESET 0x1EAA
580#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C
581#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6
582#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92
583#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93
584#define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99
585#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98
586#define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B
587#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79
588#define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A
589#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D
590#define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81
591#define mmCRTC1_CRTC_H_SYNC_A 0x1E82
592#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83
593#define mmCRTC1_CRTC_H_SYNC_B 0x1E84
594#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85
595#define mmCRTC1_CRTC_H_TOTAL 0x1E80
596#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E
597#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F
598#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4
599#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB
600#define mmCRTC1_CRTC_MASTER_EN 0x1EC2
601#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF
602#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0
603#define mmCRTC1_CRTC_MVP_STATUS 0x1EC1
604#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5
605#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0
606#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0
607#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2
608#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1
609#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF
610#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3
611#define mmCRTC1_CRTC_STATUS 0x1EA3
612#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6
613#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8
614#define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4
615#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7
616#define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE
617#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B
618#define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD
619#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7
620#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6
621#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC
622#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA
623#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB
624#define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94
625#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95
626#define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96
627#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97
628#define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5
629#define mmCRTC1_CRTC_VBI_END 0x1E86
630#define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D
631#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC
632#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7
633#define mmCRTC1_CRTC_V_SYNC_A 0x1E8E
634#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F
635#define mmCRTC1_CRTC_V_SYNC_B 0x1E90
636#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91
637#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C
638#define mmCRTC1_CRTC_V_TOTAL 0x1E87
639#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A
640#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B
641#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89
642#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88
643#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4
644#define mmCRTC1_DCFE_DBG_SEL 0x1E7E
645#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F
646#define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD
647#define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE
648#define mmCRTC1_PIXEL_RATE_CNTL 0x0144
649#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178
650#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3
651#define mmCRTC2_CRTC_BLACK_COLOR 0x41A2
652#define mmCRTC2_CRTC_BLANK_CONTROL 0x419D
653#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1
654#define mmCRTC2_CRTC_CONTROL 0x419C
655#define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9
656#define mmCRTC2_CRTC_COUNT_RESET 0x41AA
657#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C
658#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6
659#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192
660#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193
661#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199
662#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
663#define mmCRTC2_CRTC_GSL_CONTROL 0x417B
664#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179
665#define mmCRTC2_CRTC_GSL_WINDOW 0x417A
666#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D
667#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181
668#define mmCRTC2_CRTC_H_SYNC_A 0x4182
669#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183
670#define mmCRTC2_CRTC_H_SYNC_B 0x4184
671#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185
672#define mmCRTC2_CRTC_H_TOTAL 0x4180
673#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E
674#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F
675#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4
676#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB
677#define mmCRTC2_CRTC_MASTER_EN 0x41C2
678#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF
679#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0
680#define mmCRTC2_CRTC_MVP_STATUS 0x41C1
681#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5
682#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0
683#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0
684#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2
685#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1
686#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF
687#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3
688#define mmCRTC2_CRTC_STATUS 0x41A3
689#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6
690#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8
691#define mmCRTC2_CRTC_STATUS_POSITION 0x41A4
692#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7
693#define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE
694#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B
695#define mmCRTC2_CRTC_STEREO_STATUS 0x41AD
696#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7
697#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6
698#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC
699#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA
700#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB
701#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194
702#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195
703#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196
704#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197
705#define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5
706#define mmCRTC2_CRTC_VBI_END 0x4186
707#define mmCRTC2_CRTC_V_BLANK_START_END 0x418D
708#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC
709#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7
710#define mmCRTC2_CRTC_V_SYNC_A 0x418E
711#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F
712#define mmCRTC2_CRTC_V_SYNC_B 0x4190
713#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191
714#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C
715#define mmCRTC2_CRTC_V_TOTAL 0x4187
716#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A
717#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B
718#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189
719#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188
720#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4
721#define mmCRTC2_DCFE_DBG_SEL 0x417E
722#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F
723#define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD
724#define mmCRTC2_MASTER_UPDATE_MODE 0x41BE
725#define mmCRTC2_PIXEL_RATE_CNTL 0x0148
726#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478
727#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3
728#define mmCRTC3_CRTC_BLACK_COLOR 0x44A2
729#define mmCRTC3_CRTC_BLANK_CONTROL 0x449D
730#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1
731#define mmCRTC3_CRTC_CONTROL 0x449C
732#define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9
733#define mmCRTC3_CRTC_COUNT_RESET 0x44AA
734#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C
735#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6
736#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492
737#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493
738#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499
739#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498
740#define mmCRTC3_CRTC_GSL_CONTROL 0x447B
741#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479
742#define mmCRTC3_CRTC_GSL_WINDOW 0x447A
743#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D
744#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481
745#define mmCRTC3_CRTC_H_SYNC_A 0x4482
746#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483
747#define mmCRTC3_CRTC_H_SYNC_B 0x4484
748#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485
749#define mmCRTC3_CRTC_H_TOTAL 0x4480
750#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E
751#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F
752#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4
753#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB
754#define mmCRTC3_CRTC_MASTER_EN 0x44C2
755#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF
756#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0
757#define mmCRTC3_CRTC_MVP_STATUS 0x44C1
758#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5
759#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0
760#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0
761#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2
762#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1
763#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF
764#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3
765#define mmCRTC3_CRTC_STATUS 0x44A3
766#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6
767#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8
768#define mmCRTC3_CRTC_STATUS_POSITION 0x44A4
769#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7
770#define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE
771#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B
772#define mmCRTC3_CRTC_STEREO_STATUS 0x44AD
773#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7
774#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6
775#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC
776#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA
777#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB
778#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494
779#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495
780#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496
781#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497
782#define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5
783#define mmCRTC3_CRTC_VBI_END 0x4486
784#define mmCRTC3_CRTC_V_BLANK_START_END 0x448D
785#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC
786#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7
787#define mmCRTC3_CRTC_V_SYNC_A 0x448E
788#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F
789#define mmCRTC3_CRTC_V_SYNC_B 0x4490
790#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491
791#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C
792#define mmCRTC3_CRTC_V_TOTAL 0x4487
793#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A
794#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B
795#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489
796#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488
797#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4
798#define mmCRTC3_DCFE_DBG_SEL 0x447E
799#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F
800#define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78
801#define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD
802#define mmCRTC3_MASTER_UPDATE_MODE 0x44BE
803#define mmCRTC3_PIXEL_RATE_CNTL 0x014C
804#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778
805#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3
806#define mmCRTC4_CRTC_BLACK_COLOR 0x47A2
807#define mmCRTC4_CRTC_BLANK_CONTROL 0x479D
808#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1
809#define mmCRTC4_CRTC_CONTROL 0x479C
810#define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9
811#define mmCRTC4_CRTC_COUNT_RESET 0x47AA
812#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C
813#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6
814#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792
815#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793
816#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799
817#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798
818#define mmCRTC4_CRTC_GSL_CONTROL 0x477B
819#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779
820#define mmCRTC4_CRTC_GSL_WINDOW 0x477A
821#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D
822#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781
823#define mmCRTC4_CRTC_H_SYNC_A 0x4782
824#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783
825#define mmCRTC4_CRTC_H_SYNC_B 0x4784
826#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785
827#define mmCRTC4_CRTC_H_TOTAL 0x4780
828#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E
829#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F
830#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4
831#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB
832#define mmCRTC4_CRTC_MASTER_EN 0x47C2
833#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF
834#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0
835#define mmCRTC4_CRTC_MVP_STATUS 0x47C1
836#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5
837#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0
838#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0
839#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2
840#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1
841#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF
842#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3
843#define mmCRTC4_CRTC_STATUS 0x47A3
844#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6
845#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8
846#define mmCRTC4_CRTC_STATUS_POSITION 0x47A4
847#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7
848#define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE
849#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B
850#define mmCRTC4_CRTC_STEREO_STATUS 0x47AD
851#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7
852#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6
853#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC
854#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA
855#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB
856#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794
857#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795
858#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796
859#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797
860#define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5
861#define mmCRTC4_CRTC_VBI_END 0x4786
862#define mmCRTC4_CRTC_V_BLANK_START_END 0x478D
863#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC
864#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7
865#define mmCRTC4_CRTC_V_SYNC_A 0x478E
866#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F
867#define mmCRTC4_CRTC_V_SYNC_B 0x4790
868#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791
869#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C
870#define mmCRTC4_CRTC_V_TOTAL 0x4787
871#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A
872#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B
873#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789
874#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788
875#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4
876#define mmCRTC4_DCFE_DBG_SEL 0x477E
877#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F
878#define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD
879#define mmCRTC4_MASTER_UPDATE_MODE 0x47BE
880#define mmCRTC4_PIXEL_RATE_CNTL 0x0150
881#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78
882#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3
883#define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2
884#define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D
885#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1
886#define mmCRTC5_CRTC_CONTROL 0x4A9C
887#define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9
888#define mmCRTC5_CRTC_COUNT_RESET 0x4AAA
889#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C
890#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6
891#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92
892#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93
893#define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99
894#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98
895#define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B
896#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79
897#define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A
898#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D
899#define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81
900#define mmCRTC5_CRTC_H_SYNC_A 0x4A82
901#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83
902#define mmCRTC5_CRTC_H_SYNC_B 0x4A84
903#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85
904#define mmCRTC5_CRTC_H_TOTAL 0x4A80
905#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E
906#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F
907#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4
908#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB
909#define mmCRTC5_CRTC_MASTER_EN 0x4AC2
910#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF
911#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0
912#define mmCRTC5_CRTC_MVP_STATUS 0x4AC1
913#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5
914#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0
915#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0
916#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2
917#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1
918#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF
919#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3
920#define mmCRTC5_CRTC_STATUS 0x4AA3
921#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6
922#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8
923#define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4
924#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7
925#define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE
926#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B
927#define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD
928#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7
929#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6
930#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC
931#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA
932#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB
933#define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94
934#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95
935#define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96
936#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97
937#define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5
938#define mmCRTC5_CRTC_VBI_END 0x4A86
939#define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D
940#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC
941#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7
942#define mmCRTC5_CRTC_V_SYNC_A 0x4A8E
943#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F
944#define mmCRTC5_CRTC_V_SYNC_B 0x4A90
945#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91
946#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C
947#define mmCRTC5_CRTC_V_TOTAL 0x4A87
948#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A
949#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B
950#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89
951#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88
952#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4
953#define mmCRTC5_DCFE_DBG_SEL 0x4A7E
954#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F
955#define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD
956#define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE
957#define mmCRTC5_PIXEL_RATE_CNTL 0x0154
958#define mmCRTC8_DATA 0x00ED
959#define mmCRTC8_IDX 0x00ED
960#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3
961#define mmCRTC_BLACK_COLOR 0x1BA2
962#define mmCRTC_BLANK_CONTROL 0x1B9D
963#define mmCRTC_BLANK_DATA_COLOR 0x1BA1
964#define mmCRTC_CONTROL 0x1B9C
965#define mmCRTC_COUNT_CONTROL 0x1BA9
966#define mmCRTC_COUNT_RESET 0x1BAA
967#define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C
968#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6
969#define mmCRTC_DTMTEST_CNTL 0x1B92
970#define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93
971#define mmCRTC_FLOW_CONTROL 0x1B99
972#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98
973#define mmCRTC_GSL_CONTROL 0x1B7B
974#define mmCRTC_GSL_VSYNC_GAP 0x1B79
975#define mmCRTC_GSL_WINDOW 0x1B7A
976#define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D
977#define mmCRTC_H_BLANK_START_END 0x1B81
978#define mmCRTC_H_SYNC_A 0x1B82
979#define mmCRTC_H_SYNC_A_CNTL 0x1B83
980#define mmCRTC_H_SYNC_B 0x1B84
981#define mmCRTC_H_SYNC_B_CNTL 0x1B85
982#define mmCRTC_H_TOTAL 0x1B80
983#define mmCRTC_INTERLACE_CONTROL 0x1B9E
984#define mmCRTC_INTERLACE_STATUS 0x1B9F
985#define mmCRTC_INTERRUPT_CONTROL 0x1BB4
986#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB
987#define mmCRTC_MASTER_EN 0x1BC2
988#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF
989#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0
990#define mmCRTC_MVP_STATUS 0x1BC1
991#define mmCRTC_NOM_VERT_POSITION 0x1BA5
992#define mmCRTC_OVERSCAN_COLOR 0x1BA0
993#define mmCRTC_SNAPSHOT_CONTROL 0x1BB0
994#define mmCRTC_SNAPSHOT_FRAME 0x1BB2
995#define mmCRTC_SNAPSHOT_POSITION 0x1BB1
996#define mmCRTC_SNAPSHOT_STATUS 0x1BAF
997#define mmCRTC_START_LINE_CONTROL 0x1BB3
998#define mmCRTC_STATUS 0x1BA3
999#define mmCRTC_STATUS_FRAME_COUNT 0x1BA6
1000#define mmCRTC_STATUS_HV_COUNT 0x1BA8
1001#define mmCRTC_STATUS_POSITION 0x1BA4
1002#define mmCRTC_STATUS_VF_COUNT 0x1BA7
1003#define mmCRTC_STEREO_CONTROL 0x1BAE
1004#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B
1005#define mmCRTC_STEREO_STATUS 0x1BAD
1006#define mmCRTC_TEST_DEBUG_DATA 0x1BC7
1007#define mmCRTC_TEST_DEBUG_INDEX 0x1BC6
1008#define mmCRTC_TEST_PATTERN_COLOR 0x1BBC
1009#define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA
1010#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB
1011#define mmCRTC_TRIGA_CNTL 0x1B94
1012#define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95
1013#define mmCRTC_TRIGB_CNTL 0x1B96
1014#define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97
1015#define mmCRTC_UPDATE_LOCK 0x1BB5
1016#define mmCRTC_VBI_END 0x1B86
1017#define mmCRTC_V_BLANK_START_END 0x1B8D
1018#define mmCRTC_VERT_SYNC_CONTROL 0x1BAC
1019#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7
1020#define mmCRTC_V_SYNC_A 0x1B8E
1021#define mmCRTC_V_SYNC_A_CNTL 0x1B8F
1022#define mmCRTC_V_SYNC_B 0x1B90
1023#define mmCRTC_V_SYNC_B_CNTL 0x1B91
1024#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C
1025#define mmCRTC_V_TOTAL 0x1B87
1026#define mmCRTC_V_TOTAL_CONTROL 0x1B8A
1027#define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B
1028#define mmCRTC_V_TOTAL_MAX 0x1B89
1029#define mmCRTC_V_TOTAL_MIN 0x1B88
1030#define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4
1031#define mmCUR_COLOR1 0x1A6C
1032#define mmCUR_COLOR2 0x1A6D
1033#define mmCUR_CONTROL 0x1A66
1034#define mmCUR_HOT_SPOT 0x1A6B
1035#define mmCUR_POSITION 0x1A6A
1036#define mmCUR_REQUEST_FILTER_CNTL 0x1A99
1037#define mmCUR_SIZE 0x1A68
1038#define mmCUR_SURFACE_ADDRESS 0x1A67
1039#define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69
1040#define mmCUR_UPDATE 0x1A6E
1041#define mmD1VGA_CONTROL 0x00CC
1042#define mmD2VGA_CONTROL 0x00CE
1043#define mmD3VGA_CONTROL 0x00F8
1044#define mmD4VGA_CONTROL 0x00F9
1045#define mmD5VGA_CONTROL 0x00FA
1046#define mmD6VGA_CONTROL 0x00FB
1047#define mmDAC_AUTODETECT_CONTROL 0x19EE
1048#define mmDAC_AUTODETECT_CONTROL2 0x19EF
1049#define mmDAC_AUTODETECT_CONTROL3 0x19F0
1050#define mmDAC_AUTODETECT_INT_CONTROL 0x19F2
1051#define mmDAC_AUTODETECT_STATUS 0x19F1
1052#define mmDAC_CLK_ENABLE 0x0128
1053#define mmDAC_COMPARATOR_ENABLE 0x19F7
1054#define mmDAC_COMPARATOR_OUTPUT 0x19F8
1055#define mmDAC_CONTROL 0x19F6
1056#define mmDAC_CRC_CONTROL 0x19E7
1057#define mmDAC_CRC_EN 0x19E6
1058#define mmDAC_CRC_SIG_CONTROL 0x19EB
1059#define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9
1060#define mmDAC_CRC_SIG_RGB 0x19EA
1061#define mmDAC_CRC_SIG_RGB_MASK 0x19E8
1062#define mmDAC_DATA 0x00F2
1063#define mmDAC_DFT_CONFIG 0x19FA
1064#define mmDAC_ENABLE 0x19E4
1065#define mmDAC_FIFO_STATUS 0x19FB
1066#define mmDAC_FORCE_DATA 0x19F4
1067#define mmDAC_FORCE_OUTPUT_CNTL 0x19F3
1068#define mmDAC_MACRO_CNTL_RESERVED0 0x19FC
1069#define mmDAC_MACRO_CNTL_RESERVED1 0x19FD
1070#define mmDAC_MACRO_CNTL_RESERVED2 0x19FE
1071#define mmDAC_MACRO_CNTL_RESERVED3 0x19FF
1072#define mmDAC_MASK 0x00F1
1073#define mmDAC_POWERDOWN 0x19F5
1074#define mmDAC_PWR_CNTL 0x19F9
1075#define mmDAC_R_INDEX 0x00F1
1076#define mmDAC_SOURCE_SELECT 0x19E5
1077#define mmDAC_STEREOSYNC_SELECT 0x19ED
1078#define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC
1079#define mmDAC_W_INDEX 0x00F2
1080#define mmDC_ABM1_ACE_CNTL_MISC 0x1641
1081#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A
1082#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B
1083#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C
1084#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D
1085#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E
1086#define mmDC_ABM1_ACE_THRES_12 0x163F
1087#define mmDC_ABM1_ACE_THRES_34 0x1640
1088#define mmDC_ABM1_BL_MASTER_LOCK 0x169C
1089#define mmDC_ABM1_CNTL 0x1638
1090#define mmDC_ABM1_DEBUG_MISC 0x1649
1091#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
1092#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
1093#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
1094#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A
1095#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
1096#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A
1097#define mmDC_ABM1_HG_MISC_CTRL 0x164B
1098#define mmDC_ABM1_HG_RESULT_10 0x1664
1099#define mmDC_ABM1_HG_RESULT_1 0x165B
1100#define mmDC_ABM1_HG_RESULT_11 0x1665
1101#define mmDC_ABM1_HG_RESULT_12 0x1666
1102#define mmDC_ABM1_HG_RESULT_13 0x1667
1103#define mmDC_ABM1_HG_RESULT_14 0x1668
1104#define mmDC_ABM1_HG_RESULT_15 0x1669
1105#define mmDC_ABM1_HG_RESULT_16 0x166A
1106#define mmDC_ABM1_HG_RESULT_17 0x166B
1107#define mmDC_ABM1_HG_RESULT_18 0x166C
1108#define mmDC_ABM1_HG_RESULT_19 0x166D
1109#define mmDC_ABM1_HG_RESULT_20 0x166E
1110#define mmDC_ABM1_HG_RESULT_2 0x165C
1111#define mmDC_ABM1_HG_RESULT_21 0x166F
1112#define mmDC_ABM1_HG_RESULT_22 0x1670
1113#define mmDC_ABM1_HG_RESULT_23 0x1671
1114#define mmDC_ABM1_HG_RESULT_24 0x1672
1115#define mmDC_ABM1_HG_RESULT_3 0x165D
1116#define mmDC_ABM1_HG_RESULT_4 0x165E
1117#define mmDC_ABM1_HG_RESULT_5 0x165F
1118#define mmDC_ABM1_HG_RESULT_6 0x1660
1119#define mmDC_ABM1_HG_RESULT_7 0x1661
1120#define mmDC_ABM1_HG_RESULT_8 0x1662
1121#define mmDC_ABM1_HG_RESULT_9 0x1663
1122#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654
1123#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
1124#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E
1125#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
1126#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D
1127#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
1128#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
1129#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
1130#define mmDC_ABM1_LS_PIXEL_COUNT 0x164F
1131#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655
1132#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C
1133#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B
1134#define mmDCCG_AUDIO_DTO0_MODULE 0x016D
1135#define mmDCCG_AUDIO_DTO0_PHASE 0x016C
1136#define mmDCCG_AUDIO_DTO1_MODULE 0x0171
1137#define mmDCCG_AUDIO_DTO1_PHASE 0x0170
1138#define mmDCCG_AUDIO_DTO_SOURCE 0x016B
1139#define mmDCCG_CAC_STATUS 0x0137
1140#define mmDCCG_GATE_DISABLE_CNTL 0x0134
1141#define mmDCCG_GTC_CNTL 0x0120
1142#define mmDCCG_GTC_CURRENT 0x0123
1143#define mmDCCG_GTC_DTO_MODULO 0x0122
1144#define mmDCCG_PERFMON_CNTL 0x0133
1145#define mmDCCG_PLL0_PLL_ANALOG 0x1708
1146#define mmDCCG_PLL0_PLL_CNTL 0x1707
1147#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B
1148#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F
1149#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E
1150#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705
1151#define mmDCCG_PLL0_PLL_FB_DIV 0x1701
1152#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706
1153#define mmDCCG_PLL0_PLL_POST_DIV 0x1702
1154#define mmDCCG_PLL0_PLL_REF_DIV 0x1700
1155#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
1156#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704
1157#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A
1158#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D
1159#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C
1160#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709
1161#define mmDCCG_PLL1_PLL_ANALOG 0x1718
1162#define mmDCCG_PLL1_PLL_CNTL 0x1717
1163#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B
1164#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F
1165#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E
1166#define mmDCCG_PLL1_PLL_DS_CNTL 0x1715
1167#define mmDCCG_PLL1_PLL_FB_DIV 0x1711
1168#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716
1169#define mmDCCG_PLL1_PLL_POST_DIV 0x1712
1170#define mmDCCG_PLL1_PLL_REF_DIV 0x1710
1171#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713
1172#define mmDCCG_PLL1_PLL_SS_CNTL 0x1714
1173#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A
1174#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D
1175#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C
1176#define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719
1177#define mmDCCG_PLL2_PLL_ANALOG 0x1728
1178#define mmDCCG_PLL2_PLL_CNTL 0x1727
1179#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B
1180#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F
1181#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E
1182#define mmDCCG_PLL2_PLL_DS_CNTL 0x1725
1183#define mmDCCG_PLL2_PLL_FB_DIV 0x1721
1184#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726
1185#define mmDCCG_PLL2_PLL_POST_DIV 0x1722
1186#define mmDCCG_PLL2_PLL_REF_DIV 0x1720
1187#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723
1188#define mmDCCG_PLL2_PLL_SS_CNTL 0x1724
1189#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A
1190#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D
1191#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C
1192#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729
1193#define mmDCCG_SOFT_RESET 0x015F
1194#define mmDCCG_TEST_CLK_SEL 0x017E
1195#define mmDCCG_TEST_DEBUG_DATA 0x017D
1196#define mmDCCG_TEST_DEBUG_INDEX 0x017C
1197#define mmDCCG_VPCLK_CNTL 0x031F
1198#define mmDCDEBUG_BUS_CLK1_SEL 0x1860
1199#define mmDCDEBUG_BUS_CLK2_SEL 0x1861
1200#define mmDCDEBUG_BUS_CLK3_SEL 0x1862
1201#define mmDCDEBUG_BUS_CLK4_SEL 0x1863
1202#define mmDCDEBUG_OUT_CNTL 0x186B
1203#define mmDCDEBUG_OUT_DATA 0x186E
1204#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A
1205#define mmDC_DMCU_SCRATCH 0x1618
1206#define mmDC_DVODATA_CONFIG 0x1905
1207#define mmDCFE0_SOFT_RESET 0x0158
1208#define mmDCFE1_SOFT_RESET 0x0159
1209#define mmDCFE2_SOFT_RESET 0x015A
1210#define mmDCFE3_SOFT_RESET 0x015B
1211#define mmDCFE4_SOFT_RESET 0x015C
1212#define mmDCFE5_SOFT_RESET 0x015D
1213#define mmDCFE_DBG_SEL 0x1B7E
1214#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F
1215#define mmDC_GENERICA 0x1900
1216#define mmDC_GENERICB 0x1901
1217#define mmDC_GPIO_DDC1_A 0x194D
1218#define mmDC_GPIO_DDC1_EN 0x194E
1219#define mmDC_GPIO_DDC1_MASK 0x194C
1220#define mmDC_GPIO_DDC1_Y 0x194F
1221#define mmDC_GPIO_DDC2_A 0x1951
1222#define mmDC_GPIO_DDC2_EN 0x1952
1223#define mmDC_GPIO_DDC2_MASK 0x1950
1224#define mmDC_GPIO_DDC2_Y 0x1953
1225#define mmDC_GPIO_DDC3_A 0x1955
1226#define mmDC_GPIO_DDC3_EN 0x1956
1227#define mmDC_GPIO_DDC3_MASK 0x1954
1228#define mmDC_GPIO_DDC3_Y 0x1957
1229#define mmDC_GPIO_DDC4_A 0x1959
1230#define mmDC_GPIO_DDC4_EN 0x195A
1231#define mmDC_GPIO_DDC4_MASK 0x1958
1232#define mmDC_GPIO_DDC4_Y 0x195B
1233#define mmDC_GPIO_DDC5_A 0x195D
1234#define mmDC_GPIO_DDC5_EN 0x195E
1235#define mmDC_GPIO_DDC5_MASK 0x195C
1236#define mmDC_GPIO_DDC5_Y 0x195F
1237#define mmDC_GPIO_DDC6_A 0x1961
1238#define mmDC_GPIO_DDC6_EN 0x1962
1239#define mmDC_GPIO_DDC6_MASK 0x1960
1240#define mmDC_GPIO_DDC6_Y 0x1963
1241#define mmDC_GPIO_DDCVGA_A 0x1971
1242#define mmDC_GPIO_DDCVGA_EN 0x1972
1243#define mmDC_GPIO_DDCVGA_MASK 0x1970
1244#define mmDC_GPIO_DDCVGA_Y 0x1973
1245#define mmDC_GPIO_DEBUG 0x1904
1246#define mmDC_GPIO_DVODATA_A 0x1949
1247#define mmDC_GPIO_DVODATA_EN 0x194A
1248#define mmDC_GPIO_DVODATA_MASK 0x1948
1249#define mmDC_GPIO_DVODATA_Y 0x194B
1250#define mmDC_GPIO_GENERIC_A 0x1945
1251#define mmDC_GPIO_GENERIC_EN 0x1946
1252#define mmDC_GPIO_GENERIC_MASK 0x1944
1253#define mmDC_GPIO_GENERIC_Y 0x1947
1254#define mmDC_GPIO_GENLK_A 0x1969
1255#define mmDC_GPIO_GENLK_EN 0x196A
1256#define mmDC_GPIO_GENLK_MASK 0x1968
1257#define mmDC_GPIO_GENLK_Y 0x196B
1258#define mmDC_GPIO_HPD_A 0x196D
1259#define mmDC_GPIO_HPD_EN 0x196E
1260#define mmDC_GPIO_HPD_MASK 0x196C
1261#define mmDC_GPIO_HPD_Y 0x196F
1262#define mmDC_GPIO_I2CPAD_A 0x1975
1263#define mmDC_GPIO_I2CPAD_EN 0x1976
1264#define mmDC_GPIO_I2CPAD_MASK 0x1974
1265#define mmDC_GPIO_I2CPAD_STRENGTH 0x197A
1266#define mmDC_GPIO_I2CPAD_Y 0x1977
1267#define mmDC_GPIO_PAD_STRENGTH_1 0x1978
1268#define mmDC_GPIO_PAD_STRENGTH_2 0x1979
1269#define mmDC_GPIO_PWRSEQ_A 0x1941
1270#define mmDC_GPIO_PWRSEQ_EN 0x1942
1271#define mmDC_GPIO_PWRSEQ_MASK 0x1940
1272#define mmDC_GPIO_PWRSEQ_Y 0x1943
1273#define mmDC_GPIO_SYNCA_A 0x1965
1274#define mmDC_GPIO_SYNCA_EN 0x1966
1275#define mmDC_GPIO_SYNCA_MASK 0x1964
1276#define mmDC_GPIO_SYNCA_Y 0x1967
1277#define mmDC_GPU_TIMER_READ 0x1929
1278#define mmDC_GPU_TIMER_READ_CNTL 0x192A
1279#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928
1280#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927
1281#define mmDC_HPD1_CONTROL 0x1809
1282#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864
1283#define mmDC_HPD1_INT_CONTROL 0x1808
1284#define mmDC_HPD1_INT_STATUS 0x1807
1285#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC
1286#define mmDC_HPD2_CONTROL 0x180C
1287#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865
1288#define mmDC_HPD2_INT_CONTROL 0x180B
1289#define mmDC_HPD2_INT_STATUS 0x180A
1290#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD
1291#define mmDC_HPD3_CONTROL 0x180F
1292#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866
1293#define mmDC_HPD3_INT_CONTROL 0x180E
1294#define mmDC_HPD3_INT_STATUS 0x180D
1295#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE
1296#define mmDC_HPD4_CONTROL 0x1812
1297#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867
1298#define mmDC_HPD4_INT_CONTROL 0x1811
1299#define mmDC_HPD4_INT_STATUS 0x1810
1300#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC
1301#define mmDC_HPD5_CONTROL 0x1815
1302#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868
1303#define mmDC_HPD5_INT_CONTROL 0x1814
1304#define mmDC_HPD5_INT_STATUS 0x1813
1305#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD
1306#define mmDC_HPD6_CONTROL 0x1818
1307#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869
1308#define mmDC_HPD6_INT_CONTROL 0x1817
1309#define mmDC_HPD6_INT_STATUS 0x1816
1310#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE
1311#define mmDC_I2C_ARBITRATION 0x181A
1312#define mmDC_I2C_CONTROL 0x1819
1313#define mmDC_I2C_DATA 0x1833
1314#define mmDC_I2C_DDC1_HW_STATUS 0x181D
1315#define mmDC_I2C_DDC1_SETUP 0x1824
1316#define mmDC_I2C_DDC1_SPEED 0x1823
1317#define mmDC_I2C_DDC2_HW_STATUS 0x181E
1318#define mmDC_I2C_DDC2_SETUP 0x1826
1319#define mmDC_I2C_DDC2_SPEED 0x1825
1320#define mmDC_I2C_DDC3_HW_STATUS 0x181F
1321#define mmDC_I2C_DDC3_SETUP 0x1828
1322#define mmDC_I2C_DDC3_SPEED 0x1827
1323#define mmDC_I2C_DDC4_HW_STATUS 0x1820
1324#define mmDC_I2C_DDC4_SETUP 0x182A
1325#define mmDC_I2C_DDC4_SPEED 0x1829
1326#define mmDC_I2C_DDC5_HW_STATUS 0x1821
1327#define mmDC_I2C_DDC5_SETUP 0x182C
1328#define mmDC_I2C_DDC5_SPEED 0x182B
1329#define mmDC_I2C_DDC6_HW_STATUS 0x1822
1330#define mmDC_I2C_DDC6_SETUP 0x182E
1331#define mmDC_I2C_DDC6_SPEED 0x182D
1332#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855
1333#define mmDC_I2C_DDCVGA_SETUP 0x1857
1334#define mmDC_I2C_DDCVGA_SPEED 0x1856
1335#define mmDC_I2C_EDID_DETECT_CTRL 0x186F
1336#define mmDC_I2C_INTERRUPT_CONTROL 0x181B
1337#define mmDC_I2C_SW_STATUS 0x181C
1338#define mmDC_I2C_TRANSACTION0 0x182F
1339#define mmDC_I2C_TRANSACTION1 0x1830
1340#define mmDC_I2C_TRANSACTION2 0x1831
1341#define mmDC_I2C_TRANSACTION3 0x1832
1342#define mmDCI_CLK_CNTL 0x031E
1343#define mmDCI_CLK_RAMP_CNTL 0x0324
1344#define mmDCI_DEBUG_CONFIG 0x0323
1345#define mmDCI_MEM_PWR_CNTL 0x0326
1346#define mmDCI_MEM_PWR_STATE 0x031B
1347#define mmDCI_MEM_PWR_STATE2 0x0322
1348#define mmDCIO_DEBUG 0x192E
1349#define mmDCIO_GSL0_CNTL 0x1924
1350#define mmDCIO_GSL1_CNTL 0x1925
1351#define mmDCIO_GSL2_CNTL 0x1926
1352#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922
1353#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923
1354#define mmDCIO_IMPCAL_CNTL_AB 0x190D
1355#define mmDCIO_IMPCAL_CNTL_CD 0x1911
1356#define mmDCIO_IMPCAL_CNTL_EF 0x1915
1357#define mmDCIO_TEST_DEBUG_DATA 0x1930
1358#define mmDCIO_TEST_DEBUG_INDEX 0x192F
1359#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C
1360#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E
1361#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A
1362#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D
1363#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986
1364#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987
1365#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985
1366#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989
1367#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988
1368#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984
1369#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B
1370#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980
1371#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981
1372#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982
1373#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983
1374#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C
1375#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E
1376#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A
1377#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D
1378#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996
1379#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997
1380#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995
1381#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999
1382#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998
1383#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994
1384#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B
1385#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990
1386#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991
1387#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992
1388#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993
1389#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC
1390#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE
1391#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA
1392#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD
1393#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6
1394#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7
1395#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5
1396#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9
1397#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8
1398#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4
1399#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB
1400#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0
1401#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1
1402#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2
1403#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3
1404#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC
1405#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE
1406#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA
1407#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD
1408#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6
1409#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7
1410#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5
1411#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9
1412#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8
1413#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4
1414#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB
1415#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0
1416#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1
1417#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2
1418#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3
1419#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC
1420#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE
1421#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA
1422#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD
1423#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6
1424#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7
1425#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5
1426#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9
1427#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8
1428#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4
1429#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB
1430#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0
1431#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1
1432#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2
1433#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3
1434#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC
1435#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE
1436#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA
1437#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD
1438#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6
1439#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7
1440#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5
1441#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9
1442#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8
1443#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4
1444#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB
1445#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0
1446#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1
1447#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2
1448#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3
1449#define mmDCI_SOFT_RESET 0x015E
1450#define mmDCI_TEST_DEBUG_DATA 0x0321
1451#define mmDCI_TEST_DEBUG_INDEX 0x0320
1452#define mmDC_LUT_30_COLOR 0x1A7C
1453#define mmDC_LUT_AUTOFILL 0x1A7F
1454#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81
1455#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82
1456#define mmDC_LUT_BLACK_OFFSET_RED 0x1A83
1457#define mmDC_LUT_CONTROL 0x1A80
1458#define mmDC_LUT_PWL_DATA 0x1A7B
1459#define mmDC_LUT_RW_INDEX 0x1A79
1460#define mmDC_LUT_RW_MODE 0x1A78
1461#define mmDC_LUT_SEQ_COLOR 0x1A7A
1462#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D
1463#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84
1464#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85
1465#define mmDC_LUT_WHITE_OFFSET_RED 0x1A86
1466#define mmDC_LUT_WRITE_EN_MASK 0x1A7E
1467#define mmDC_MVP_LB_CONTROL 0x1ADB
1468#define mmDCO_CLK_CNTL 0x192B
1469#define mmDCO_CLK_RAMP_CNTL 0x192C
1470#define mmDCO_LIGHT_SLEEP_DIS 0x1907
1471#define mmDCO_MEM_POWER_STATE 0x1906
1472#define mmDCO_SOFT_RESET 0x0167
1473#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43
1474#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44
1475#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45
1476#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46
1477#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47
1478#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48
1479#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49
1480#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A
1481#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B
1482#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C
1483#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D
1484#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E
1485#define mmDCP0_CUR_COLOR1 0x1A6C
1486#define mmDCP0_CUR_COLOR2 0x1A6D
1487#define mmDCP0_CUR_CONTROL 0x1A66
1488#define mmDCP0_CUR_HOT_SPOT 0x1A6B
1489#define mmDCP0_CUR_POSITION 0x1A6A
1490#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99
1491#define mmDCP0_CUR_SIZE 0x1A68
1492#define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67
1493#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69
1494#define mmDCP0_CUR_UPDATE 0x1A6E
1495#define mmDCP0_DC_LUT_30_COLOR 0x1A7C
1496#define mmDCP0_DC_LUT_AUTOFILL 0x1A7F
1497#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81
1498#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82
1499#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83
1500#define mmDCP0_DC_LUT_CONTROL 0x1A80
1501#define mmDCP0_DC_LUT_PWL_DATA 0x1A7B
1502#define mmDCP0_DC_LUT_RW_INDEX 0x1A79
1503#define mmDCP0_DC_LUT_RW_MODE 0x1A78
1504#define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A
1505#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D
1506#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84
1507#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85
1508#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86
1509#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E
1510#define mmDCP0_DCP_CRC_CONTROL 0x1A87
1511#define mmDCP0_DCP_CRC_CURRENT 0x1A89
1512#define mmDCP0_DCP_CRC_LAST 0x1A8B
1513#define mmDCP0_DCP_CRC_MASK 0x1A88
1514#define mmDCP0_DCP_DEBUG 0x1A8D
1515#define mmDCP0_DCP_DEBUG2 0x1A98
1516#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65
1517#define mmDCP0_DCP_GSL_CONTROL 0x1A90
1518#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91
1519#define mmDCP0_DCP_RANDOM_SEEDS 0x1A61
1520#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60
1521#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96
1522#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95
1523#define mmDCP0_DEGAMMA_CONTROL 0x1A58
1524#define mmDCP0_DENORM_CONTROL 0x1A50
1525#define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A
1526#define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B
1527#define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C
1528#define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D
1529#define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E
1530#define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F
1531#define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59
1532#define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A
1533#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19
1534#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B
1535#define mmDCP0_GRPH_CONTROL 0x1A01
1536#define mmDCP0_GRPH_DFQ_CONTROL 0x1A14
1537#define mmDCP0_GRPH_DFQ_STATUS 0x1A15
1538#define mmDCP0_GRPH_ENABLE 0x1A00
1539#define mmDCP0_GRPH_FLIP_CONTROL 0x1A12
1540#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17
1541#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16
1542#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02
1543#define mmDCP0_GRPH_PITCH 0x1A06
1544#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04
1545#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07
1546#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05
1547#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08
1548#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97
1549#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18
1550#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13
1551#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09
1552#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A
1553#define mmDCP0_GRPH_SWAP_CNTL 0x1A03
1554#define mmDCP0_GRPH_UPDATE 0x1A11
1555#define mmDCP0_GRPH_X_END 0x1A0D
1556#define mmDCP0_GRPH_X_START 0x1A0B
1557#define mmDCP0_GRPH_Y_END 0x1A0E
1558#define mmDCP0_GRPH_Y_START 0x1A0C
1559#define mmDCP0_INPUT_CSC_C11_C12 0x1A36
1560#define mmDCP0_INPUT_CSC_C13_C14 0x1A37
1561#define mmDCP0_INPUT_CSC_C21_C22 0x1A38
1562#define mmDCP0_INPUT_CSC_C23_C24 0x1A39
1563#define mmDCP0_INPUT_CSC_C31_C32 0x1A3A
1564#define mmDCP0_INPUT_CSC_C33_C34 0x1A3B
1565#define mmDCP0_INPUT_CSC_CONTROL 0x1A35
1566#define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10
1567#define mmDCP0_KEY_CONTROL 0x1A53
1568#define mmDCP0_KEY_RANGE_ALPHA 0x1A54
1569#define mmDCP0_KEY_RANGE_BLUE 0x1A57
1570#define mmDCP0_KEY_RANGE_GREEN 0x1A56
1571#define mmDCP0_KEY_RANGE_RED 0x1A55
1572#define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D
1573#define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E
1574#define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F
1575#define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40
1576#define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41
1577#define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42
1578#define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C
1579#define mmDCP0_OUT_ROUND_CONTROL 0x1A51
1580#define mmDCP0_OVL_CONTROL1 0x1A1D
1581#define mmDCP0_OVL_CONTROL2 0x1A1E
1582#define mmDCP0_OVL_DFQ_CONTROL 0x1A29
1583#define mmDCP0_OVL_DFQ_STATUS 0x1A2A
1584#define mmDCP0_OVL_ENABLE 0x1A1C
1585#define mmDCP0_OVL_END 0x1A26
1586#define mmDCP0_OVL_PITCH 0x1A21
1587#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C
1588#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92
1589#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94
1590#define mmDCP0_OVL_START 0x1A25
1591#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93
1592#define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20
1593#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22
1594#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B
1595#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28
1596#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23
1597#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24
1598#define mmDCP0_OVL_SWAP_CNTL 0x1A1F
1599#define mmDCP0_OVL_UPDATE 0x1A27
1600#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D
1601#define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31
1602#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30
1603#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F
1604#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E
1605#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32
1606#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34
1607#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33
1608#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6
1609#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7
1610#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8
1611#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD
1612#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE
1613#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF
1614#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9
1615#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA
1616#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB
1617#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC
1618#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5
1619#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4
1620#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2
1621#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3
1622#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4
1623#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9
1624#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA
1625#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB
1626#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5
1627#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6
1628#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7
1629#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8
1630#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1
1631#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0
1632#define mmDCP0_REGAMMA_CONTROL 0x1AA0
1633#define mmDCP0_REGAMMA_LUT_DATA 0x1AA2
1634#define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1
1635#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3
1636#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43
1637#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44
1638#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45
1639#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46
1640#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47
1641#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48
1642#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49
1643#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A
1644#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B
1645#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C
1646#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D
1647#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E
1648#define mmDCP1_CUR_COLOR1 0x1D6C
1649#define mmDCP1_CUR_COLOR2 0x1D6D
1650#define mmDCP1_CUR_CONTROL 0x1D66
1651#define mmDCP1_CUR_HOT_SPOT 0x1D6B
1652#define mmDCP1_CUR_POSITION 0x1D6A
1653#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99
1654#define mmDCP1_CUR_SIZE 0x1D68
1655#define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67
1656#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69
1657#define mmDCP1_CUR_UPDATE 0x1D6E
1658#define mmDCP1_DC_LUT_30_COLOR 0x1D7C
1659#define mmDCP1_DC_LUT_AUTOFILL 0x1D7F
1660#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81
1661#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82
1662#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83
1663#define mmDCP1_DC_LUT_CONTROL 0x1D80
1664#define mmDCP1_DC_LUT_PWL_DATA 0x1D7B
1665#define mmDCP1_DC_LUT_RW_INDEX 0x1D79
1666#define mmDCP1_DC_LUT_RW_MODE 0x1D78
1667#define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A
1668#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D
1669#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84
1670#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85
1671#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86
1672#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E
1673#define mmDCP1_DCP_CRC_CONTROL 0x1D87
1674#define mmDCP1_DCP_CRC_CURRENT 0x1D89
1675#define mmDCP1_DCP_CRC_LAST 0x1D8B
1676#define mmDCP1_DCP_CRC_MASK 0x1D88
1677#define mmDCP1_DCP_DEBUG 0x1D8D
1678#define mmDCP1_DCP_DEBUG2 0x1D98
1679#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65
1680#define mmDCP1_DCP_GSL_CONTROL 0x1D90
1681#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91
1682#define mmDCP1_DCP_RANDOM_SEEDS 0x1D61
1683#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60
1684#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96
1685#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95
1686#define mmDCP1_DEGAMMA_CONTROL 0x1D58
1687#define mmDCP1_DENORM_CONTROL 0x1D50
1688#define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A
1689#define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B
1690#define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C
1691#define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D
1692#define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E
1693#define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F
1694#define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59
1695#define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A
1696#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19
1697#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B
1698#define mmDCP1_GRPH_CONTROL 0x1D01
1699#define mmDCP1_GRPH_DFQ_CONTROL 0x1D14
1700#define mmDCP1_GRPH_DFQ_STATUS 0x1D15
1701#define mmDCP1_GRPH_ENABLE 0x1D00
1702#define mmDCP1_GRPH_FLIP_CONTROL 0x1D12
1703#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17
1704#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16
1705#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02
1706#define mmDCP1_GRPH_PITCH 0x1D06
1707#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04
1708#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07
1709#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05
1710#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08
1711#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97
1712#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18
1713#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13
1714#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09
1715#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A
1716#define mmDCP1_GRPH_SWAP_CNTL 0x1D03
1717#define mmDCP1_GRPH_UPDATE 0x1D11
1718#define mmDCP1_GRPH_X_END 0x1D0D
1719#define mmDCP1_GRPH_X_START 0x1D0B
1720#define mmDCP1_GRPH_Y_END 0x1D0E
1721#define mmDCP1_GRPH_Y_START 0x1D0C
1722#define mmDCP1_INPUT_CSC_C11_C12 0x1D36
1723#define mmDCP1_INPUT_CSC_C13_C14 0x1D37
1724#define mmDCP1_INPUT_CSC_C21_C22 0x1D38
1725#define mmDCP1_INPUT_CSC_C23_C24 0x1D39
1726#define mmDCP1_INPUT_CSC_C31_C32 0x1D3A
1727#define mmDCP1_INPUT_CSC_C33_C34 0x1D3B
1728#define mmDCP1_INPUT_CSC_CONTROL 0x1D35
1729#define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10
1730#define mmDCP1_KEY_CONTROL 0x1D53
1731#define mmDCP1_KEY_RANGE_ALPHA 0x1D54
1732#define mmDCP1_KEY_RANGE_BLUE 0x1D57
1733#define mmDCP1_KEY_RANGE_GREEN 0x1D56
1734#define mmDCP1_KEY_RANGE_RED 0x1D55
1735#define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D
1736#define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E
1737#define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F
1738#define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40
1739#define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41
1740#define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42
1741#define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C
1742#define mmDCP1_OUT_ROUND_CONTROL 0x1D51
1743#define mmDCP1_OVL_CONTROL1 0x1D1D
1744#define mmDCP1_OVL_CONTROL2 0x1D1E
1745#define mmDCP1_OVL_DFQ_CONTROL 0x1D29
1746#define mmDCP1_OVL_DFQ_STATUS 0x1D2A
1747#define mmDCP1_OVL_ENABLE 0x1D1C
1748#define mmDCP1_OVL_END 0x1D26
1749#define mmDCP1_OVL_PITCH 0x1D21
1750#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C
1751#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92
1752#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94
1753#define mmDCP1_OVL_START 0x1D25
1754#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93
1755#define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20
1756#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22
1757#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B
1758#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28
1759#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23
1760#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24
1761#define mmDCP1_OVL_SWAP_CNTL 0x1D1F
1762#define mmDCP1_OVL_UPDATE 0x1D27
1763#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D
1764#define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31
1765#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30
1766#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F
1767#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E
1768#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32
1769#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34
1770#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33
1771#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6
1772#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7
1773#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8
1774#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD
1775#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE
1776#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF
1777#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9
1778#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA
1779#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB
1780#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC
1781#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5
1782#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4
1783#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2
1784#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3
1785#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4
1786#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9
1787#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA
1788#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB
1789#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5
1790#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6
1791#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7
1792#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8
1793#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1
1794#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0
1795#define mmDCP1_REGAMMA_CONTROL 0x1DA0
1796#define mmDCP1_REGAMMA_LUT_DATA 0x1DA2
1797#define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1
1798#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3
1799#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043
1800#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044
1801#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045
1802#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046
1803#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047
1804#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048
1805#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049
1806#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A
1807#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B
1808#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C
1809#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D
1810#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E
1811#define mmDCP2_CUR_COLOR1 0x406C
1812#define mmDCP2_CUR_COLOR2 0x406D
1813#define mmDCP2_CUR_CONTROL 0x4066
1814#define mmDCP2_CUR_HOT_SPOT 0x406B
1815#define mmDCP2_CUR_POSITION 0x406A
1816#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099
1817#define mmDCP2_CUR_SIZE 0x4068
1818#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067
1819#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069
1820#define mmDCP2_CUR_UPDATE 0x406E
1821#define mmDCP2_DC_LUT_30_COLOR 0x407C
1822#define mmDCP2_DC_LUT_AUTOFILL 0x407F
1823#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081
1824#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082
1825#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083
1826#define mmDCP2_DC_LUT_CONTROL 0x4080
1827#define mmDCP2_DC_LUT_PWL_DATA 0x407B
1828#define mmDCP2_DC_LUT_RW_INDEX 0x4079
1829#define mmDCP2_DC_LUT_RW_MODE 0x4078
1830#define mmDCP2_DC_LUT_SEQ_COLOR 0x407A
1831#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D
1832#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084
1833#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085
1834#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086
1835#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E
1836#define mmDCP2_DCP_CRC_CONTROL 0x4087
1837#define mmDCP2_DCP_CRC_CURRENT 0x4089
1838#define mmDCP2_DCP_CRC_LAST 0x408B
1839#define mmDCP2_DCP_CRC_MASK 0x4088
1840#define mmDCP2_DCP_DEBUG 0x408D
1841#define mmDCP2_DCP_DEBUG2 0x4098
1842#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065
1843#define mmDCP2_DCP_GSL_CONTROL 0x4090
1844#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
1845#define mmDCP2_DCP_RANDOM_SEEDS 0x4061
1846#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060
1847#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096
1848#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095
1849#define mmDCP2_DEGAMMA_CONTROL 0x4058
1850#define mmDCP2_DENORM_CONTROL 0x4050
1851#define mmDCP2_GAMUT_REMAP_C11_C12 0x405A
1852#define mmDCP2_GAMUT_REMAP_C13_C14 0x405B
1853#define mmDCP2_GAMUT_REMAP_C21_C22 0x405C
1854#define mmDCP2_GAMUT_REMAP_C23_C24 0x405D
1855#define mmDCP2_GAMUT_REMAP_C31_C32 0x405E
1856#define mmDCP2_GAMUT_REMAP_C33_C34 0x405F
1857#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059
1858#define mmDCP2_GRPH_COMPRESS_PITCH 0x401A
1859#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
1860#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B
1861#define mmDCP2_GRPH_CONTROL 0x4001
1862#define mmDCP2_GRPH_DFQ_CONTROL 0x4014
1863#define mmDCP2_GRPH_DFQ_STATUS 0x4015
1864#define mmDCP2_GRPH_ENABLE 0x4000
1865#define mmDCP2_GRPH_FLIP_CONTROL 0x4012
1866#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017
1867#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016
1868#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002
1869#define mmDCP2_GRPH_PITCH 0x4006
1870#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
1871#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
1872#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
1873#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
1874#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097
1875#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
1876#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013
1877#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009
1878#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A
1879#define mmDCP2_GRPH_SWAP_CNTL 0x4003
1880#define mmDCP2_GRPH_UPDATE 0x4011
1881#define mmDCP2_GRPH_X_END 0x400D
1882#define mmDCP2_GRPH_X_START 0x400B
1883#define mmDCP2_GRPH_Y_END 0x400E
1884#define mmDCP2_GRPH_Y_START 0x400C
1885#define mmDCP2_INPUT_CSC_C11_C12 0x4036
1886#define mmDCP2_INPUT_CSC_C13_C14 0x4037
1887#define mmDCP2_INPUT_CSC_C21_C22 0x4038
1888#define mmDCP2_INPUT_CSC_C23_C24 0x4039
1889#define mmDCP2_INPUT_CSC_C31_C32 0x403A
1890#define mmDCP2_INPUT_CSC_C33_C34 0x403B
1891#define mmDCP2_INPUT_CSC_CONTROL 0x4035
1892#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010
1893#define mmDCP2_KEY_CONTROL 0x4053
1894#define mmDCP2_KEY_RANGE_ALPHA 0x4054
1895#define mmDCP2_KEY_RANGE_BLUE 0x4057
1896#define mmDCP2_KEY_RANGE_GREEN 0x4056
1897#define mmDCP2_KEY_RANGE_RED 0x4055
1898#define mmDCP2_OUTPUT_CSC_C11_C12 0x403D
1899#define mmDCP2_OUTPUT_CSC_C13_C14 0x403E
1900#define mmDCP2_OUTPUT_CSC_C21_C22 0x403F
1901#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040
1902#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041
1903#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042
1904#define mmDCP2_OUTPUT_CSC_CONTROL 0x403C
1905#define mmDCP2_OUT_ROUND_CONTROL 0x4051
1906#define mmDCP2_OVL_CONTROL1 0x401D
1907#define mmDCP2_OVL_CONTROL2 0x401E
1908#define mmDCP2_OVL_DFQ_CONTROL 0x4029
1909#define mmDCP2_OVL_DFQ_STATUS 0x402A
1910#define mmDCP2_OVL_ENABLE 0x401C
1911#define mmDCP2_OVL_END 0x4026
1912#define mmDCP2_OVL_PITCH 0x4021
1913#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C
1914#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092
1915#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094
1916#define mmDCP2_OVL_START 0x4025
1917#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093
1918#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020
1919#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022
1920#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B
1921#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028
1922#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023
1923#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024
1924#define mmDCP2_OVL_SWAP_CNTL 0x401F
1925#define mmDCP2_OVL_UPDATE 0x4027
1926#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D
1927#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031
1928#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030
1929#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F
1930#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E
1931#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032
1932#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034
1933#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033
1934#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6
1935#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7
1936#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8
1937#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD
1938#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE
1939#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF
1940#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9
1941#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA
1942#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB
1943#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC
1944#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5
1945#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4
1946#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2
1947#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3
1948#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4
1949#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9
1950#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA
1951#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB
1952#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5
1953#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6
1954#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7
1955#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8
1956#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1
1957#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0
1958#define mmDCP2_REGAMMA_CONTROL 0x40A0
1959#define mmDCP2_REGAMMA_LUT_DATA 0x40A2
1960#define mmDCP2_REGAMMA_LUT_INDEX 0x40A1
1961#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3
1962#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343
1963#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344
1964#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345
1965#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346
1966#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347
1967#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348
1968#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349
1969#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A
1970#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B
1971#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C
1972#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D
1973#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E
1974#define mmDCP3_CUR_COLOR1 0x436C
1975#define mmDCP3_CUR_COLOR2 0x436D
1976#define mmDCP3_CUR_CONTROL 0x4366
1977#define mmDCP3_CUR_HOT_SPOT 0x436B
1978#define mmDCP3_CUR_POSITION 0x436A
1979#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399
1980#define mmDCP3_CUR_SIZE 0x4368
1981#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367
1982#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369
1983#define mmDCP3_CUR_UPDATE 0x436E
1984#define mmDCP3_DC_LUT_30_COLOR 0x437C
1985#define mmDCP3_DC_LUT_AUTOFILL 0x437F
1986#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381
1987#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382
1988#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383
1989#define mmDCP3_DC_LUT_CONTROL 0x4380
1990#define mmDCP3_DC_LUT_PWL_DATA 0x437B
1991#define mmDCP3_DC_LUT_RW_INDEX 0x4379
1992#define mmDCP3_DC_LUT_RW_MODE 0x4378
1993#define mmDCP3_DC_LUT_SEQ_COLOR 0x437A
1994#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D
1995#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384
1996#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385
1997#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386
1998#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E
1999#define mmDCP3_DCP_CRC_CONTROL 0x4387
2000#define mmDCP3_DCP_CRC_CURRENT 0x4389
2001#define mmDCP3_DCP_CRC_LAST 0x438B
2002#define mmDCP3_DCP_CRC_MASK 0x4388
2003#define mmDCP3_DCP_DEBUG 0x438D
2004#define mmDCP3_DCP_DEBUG2 0x4398
2005#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365
2006#define mmDCP3_DCP_GSL_CONTROL 0x4390
2007#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391
2008#define mmDCP3_DCP_RANDOM_SEEDS 0x4361
2009#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360
2010#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396
2011#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395
2012#define mmDCP3_DEGAMMA_CONTROL 0x4358
2013#define mmDCP3_DENORM_CONTROL 0x4350
2014#define mmDCP3_GAMUT_REMAP_C11_C12 0x435A
2015#define mmDCP3_GAMUT_REMAP_C13_C14 0x435B
2016#define mmDCP3_GAMUT_REMAP_C21_C22 0x435C
2017#define mmDCP3_GAMUT_REMAP_C23_C24 0x435D
2018#define mmDCP3_GAMUT_REMAP_C31_C32 0x435E
2019#define mmDCP3_GAMUT_REMAP_C33_C34 0x435F
2020#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359
2021#define mmDCP3_GRPH_COMPRESS_PITCH 0x431A
2022#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319
2023#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B
2024#define mmDCP3_GRPH_CONTROL 0x4301
2025#define mmDCP3_GRPH_DFQ_CONTROL 0x4314
2026#define mmDCP3_GRPH_DFQ_STATUS 0x4315
2027#define mmDCP3_GRPH_ENABLE 0x4300
2028#define mmDCP3_GRPH_FLIP_CONTROL 0x4312
2029#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317
2030#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316
2031#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302
2032#define mmDCP3_GRPH_PITCH 0x4306
2033#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304
2034#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307
2035#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305
2036#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308
2037#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397
2038#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318
2039#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313
2040#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309
2041#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A
2042#define mmDCP3_GRPH_SWAP_CNTL 0x4303
2043#define mmDCP3_GRPH_UPDATE 0x4311
2044#define mmDCP3_GRPH_X_END 0x430D
2045#define mmDCP3_GRPH_X_START 0x430B
2046#define mmDCP3_GRPH_Y_END 0x430E
2047#define mmDCP3_GRPH_Y_START 0x430C
2048#define mmDCP3_INPUT_CSC_C11_C12 0x4336
2049#define mmDCP3_INPUT_CSC_C13_C14 0x4337
2050#define mmDCP3_INPUT_CSC_C21_C22 0x4338
2051#define mmDCP3_INPUT_CSC_C23_C24 0x4339
2052#define mmDCP3_INPUT_CSC_C31_C32 0x433A
2053#define mmDCP3_INPUT_CSC_C33_C34 0x433B
2054#define mmDCP3_INPUT_CSC_CONTROL 0x4335
2055#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310
2056#define mmDCP3_KEY_CONTROL 0x4353
2057#define mmDCP3_KEY_RANGE_ALPHA 0x4354
2058#define mmDCP3_KEY_RANGE_BLUE 0x4357
2059#define mmDCP3_KEY_RANGE_GREEN 0x4356
2060#define mmDCP3_KEY_RANGE_RED 0x4355
2061#define mmDCP3_OUTPUT_CSC_C11_C12 0x433D
2062#define mmDCP3_OUTPUT_CSC_C13_C14 0x433E
2063#define mmDCP3_OUTPUT_CSC_C21_C22 0x433F
2064#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340
2065#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341
2066#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342
2067#define mmDCP3_OUTPUT_CSC_CONTROL 0x433C
2068#define mmDCP3_OUT_ROUND_CONTROL 0x4351
2069#define mmDCP3_OVL_CONTROL1 0x431D
2070#define mmDCP3_OVL_CONTROL2 0x431E
2071#define mmDCP3_OVL_DFQ_CONTROL 0x4329
2072#define mmDCP3_OVL_DFQ_STATUS 0x432A
2073#define mmDCP3_OVL_ENABLE 0x431C
2074#define mmDCP3_OVL_END 0x4326
2075#define mmDCP3_OVL_PITCH 0x4321
2076#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C
2077#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392
2078#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394
2079#define mmDCP3_OVL_START 0x4325
2080#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393
2081#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320
2082#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322
2083#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B
2084#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328
2085#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323
2086#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324
2087#define mmDCP3_OVL_SWAP_CNTL 0x431F
2088#define mmDCP3_OVL_UPDATE 0x4327
2089#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D
2090#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331
2091#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330
2092#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F
2093#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E
2094#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332
2095#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334
2096#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333
2097#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6
2098#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7
2099#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8
2100#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD
2101#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE
2102#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF
2103#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9
2104#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA
2105#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB
2106#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC
2107#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5
2108#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4
2109#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2
2110#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3
2111#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4
2112#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9
2113#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA
2114#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB
2115#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5
2116#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6
2117#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7
2118#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8
2119#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1
2120#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0
2121#define mmDCP3_REGAMMA_CONTROL 0x43A0
2122#define mmDCP3_REGAMMA_LUT_DATA 0x43A2
2123#define mmDCP3_REGAMMA_LUT_INDEX 0x43A1
2124#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3
2125#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643
2126#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644
2127#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645
2128#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646
2129#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647
2130#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648
2131#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649
2132#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A
2133#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B
2134#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C
2135#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D
2136#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E
2137#define mmDCP4_CUR_COLOR1 0x466C
2138#define mmDCP4_CUR_COLOR2 0x466D
2139#define mmDCP4_CUR_CONTROL 0x4666
2140#define mmDCP4_CUR_HOT_SPOT 0x466B
2141#define mmDCP4_CUR_POSITION 0x466A
2142#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699
2143#define mmDCP4_CUR_SIZE 0x4668
2144#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667
2145#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669
2146#define mmDCP4_CUR_UPDATE 0x466E
2147#define mmDCP4_DC_LUT_30_COLOR 0x467C
2148#define mmDCP4_DC_LUT_AUTOFILL 0x467F
2149#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681
2150#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682
2151#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683
2152#define mmDCP4_DC_LUT_CONTROL 0x4680
2153#define mmDCP4_DC_LUT_PWL_DATA 0x467B
2154#define mmDCP4_DC_LUT_RW_INDEX 0x4679
2155#define mmDCP4_DC_LUT_RW_MODE 0x4678
2156#define mmDCP4_DC_LUT_SEQ_COLOR 0x467A
2157#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D
2158#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684
2159#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685
2160#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686
2161#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E
2162#define mmDCP4_DCP_CRC_CONTROL 0x4687
2163#define mmDCP4_DCP_CRC_CURRENT 0x4689
2164#define mmDCP4_DCP_CRC_LAST 0x468B
2165#define mmDCP4_DCP_CRC_MASK 0x4688
2166#define mmDCP4_DCP_DEBUG 0x468D
2167#define mmDCP4_DCP_DEBUG2 0x4698
2168#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665
2169#define mmDCP4_DCP_GSL_CONTROL 0x4690
2170#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691
2171#define mmDCP4_DCP_RANDOM_SEEDS 0x4661
2172#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660
2173#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696
2174#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695
2175#define mmDCP4_DEGAMMA_CONTROL 0x4658
2176#define mmDCP4_DENORM_CONTROL 0x4650
2177#define mmDCP4_GAMUT_REMAP_C11_C12 0x465A
2178#define mmDCP4_GAMUT_REMAP_C13_C14 0x465B
2179#define mmDCP4_GAMUT_REMAP_C21_C22 0x465C
2180#define mmDCP4_GAMUT_REMAP_C23_C24 0x465D
2181#define mmDCP4_GAMUT_REMAP_C31_C32 0x465E
2182#define mmDCP4_GAMUT_REMAP_C33_C34 0x465F
2183#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659
2184#define mmDCP4_GRPH_COMPRESS_PITCH 0x461A
2185#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619
2186#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B
2187#define mmDCP4_GRPH_CONTROL 0x4601
2188#define mmDCP4_GRPH_DFQ_CONTROL 0x4614
2189#define mmDCP4_GRPH_DFQ_STATUS 0x4615
2190#define mmDCP4_GRPH_ENABLE 0x4600
2191#define mmDCP4_GRPH_FLIP_CONTROL 0x4612
2192#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617
2193#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616
2194#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602
2195#define mmDCP4_GRPH_PITCH 0x4606
2196#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604
2197#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607
2198#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605
2199#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608
2200#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697
2201#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618
2202#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613
2203#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609
2204#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A
2205#define mmDCP4_GRPH_SWAP_CNTL 0x4603
2206#define mmDCP4_GRPH_UPDATE 0x4611
2207#define mmDCP4_GRPH_X_END 0x460D
2208#define mmDCP4_GRPH_X_START 0x460B
2209#define mmDCP4_GRPH_Y_END 0x460E
2210#define mmDCP4_GRPH_Y_START 0x460C
2211#define mmDCP4_INPUT_CSC_C11_C12 0x4636
2212#define mmDCP4_INPUT_CSC_C13_C14 0x4637
2213#define mmDCP4_INPUT_CSC_C21_C22 0x4638
2214#define mmDCP4_INPUT_CSC_C23_C24 0x4639
2215#define mmDCP4_INPUT_CSC_C31_C32 0x463A
2216#define mmDCP4_INPUT_CSC_C33_C34 0x463B
2217#define mmDCP4_INPUT_CSC_CONTROL 0x4635
2218#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610
2219#define mmDCP4_KEY_CONTROL 0x4653
2220#define mmDCP4_KEY_RANGE_ALPHA 0x4654
2221#define mmDCP4_KEY_RANGE_BLUE 0x4657
2222#define mmDCP4_KEY_RANGE_GREEN 0x4656
2223#define mmDCP4_KEY_RANGE_RED 0x4655
2224#define mmDCP4_OUTPUT_CSC_C11_C12 0x463D
2225#define mmDCP4_OUTPUT_CSC_C13_C14 0x463E
2226#define mmDCP4_OUTPUT_CSC_C21_C22 0x463F
2227#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640
2228#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641
2229#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642
2230#define mmDCP4_OUTPUT_CSC_CONTROL 0x463C
2231#define mmDCP4_OUT_ROUND_CONTROL 0x4651
2232#define mmDCP4_OVL_CONTROL1 0x461D
2233#define mmDCP4_OVL_CONTROL2 0x461E
2234#define mmDCP4_OVL_DFQ_CONTROL 0x4629
2235#define mmDCP4_OVL_DFQ_STATUS 0x462A
2236#define mmDCP4_OVL_ENABLE 0x461C
2237#define mmDCP4_OVL_END 0x4626
2238#define mmDCP4_OVL_PITCH 0x4621
2239#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C
2240#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692
2241#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694
2242#define mmDCP4_OVL_START 0x4625
2243#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693
2244#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620
2245#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622
2246#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B
2247#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628
2248#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623
2249#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624
2250#define mmDCP4_OVL_SWAP_CNTL 0x461F
2251#define mmDCP4_OVL_UPDATE 0x4627
2252#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D
2253#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631
2254#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630
2255#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F
2256#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E
2257#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632
2258#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634
2259#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633
2260#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6
2261#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7
2262#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8
2263#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD
2264#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE
2265#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF
2266#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9
2267#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA
2268#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB
2269#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC
2270#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5
2271#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4
2272#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2
2273#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3
2274#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4
2275#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9
2276#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA
2277#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB
2278#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5
2279#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6
2280#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7
2281#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8
2282#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1
2283#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0
2284#define mmDCP4_REGAMMA_CONTROL 0x46A0
2285#define mmDCP4_REGAMMA_LUT_DATA 0x46A2
2286#define mmDCP4_REGAMMA_LUT_INDEX 0x46A1
2287#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3
2288#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943
2289#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944
2290#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945
2291#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946
2292#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947
2293#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948
2294#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949
2295#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A
2296#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B
2297#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C
2298#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D
2299#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E
2300#define mmDCP5_CUR_COLOR1 0x496C
2301#define mmDCP5_CUR_COLOR2 0x496D
2302#define mmDCP5_CUR_CONTROL 0x4966
2303#define mmDCP5_CUR_HOT_SPOT 0x496B
2304#define mmDCP5_CUR_POSITION 0x496A
2305#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999
2306#define mmDCP5_CUR_SIZE 0x4968
2307#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967
2308#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969
2309#define mmDCP5_CUR_UPDATE 0x496E
2310#define mmDCP5_DC_LUT_30_COLOR 0x497C
2311#define mmDCP5_DC_LUT_AUTOFILL 0x497F
2312#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981
2313#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982
2314#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983
2315#define mmDCP5_DC_LUT_CONTROL 0x4980
2316#define mmDCP5_DC_LUT_PWL_DATA 0x497B
2317#define mmDCP5_DC_LUT_RW_INDEX 0x4979
2318#define mmDCP5_DC_LUT_RW_MODE 0x4978
2319#define mmDCP5_DC_LUT_SEQ_COLOR 0x497A
2320#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D
2321#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984
2322#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985
2323#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986
2324#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E
2325#define mmDCP5_DCP_CRC_CONTROL 0x4987
2326#define mmDCP5_DCP_CRC_CURRENT 0x4989
2327#define mmDCP5_DCP_CRC_LAST 0x498B
2328#define mmDCP5_DCP_CRC_MASK 0x4988
2329#define mmDCP5_DCP_DEBUG 0x498D
2330#define mmDCP5_DCP_DEBUG2 0x4998
2331#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965
2332#define mmDCP5_DCP_GSL_CONTROL 0x4990
2333#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991
2334#define mmDCP5_DCP_RANDOM_SEEDS 0x4961
2335#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960
2336#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996
2337#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995
2338#define mmDCP5_DEGAMMA_CONTROL 0x4958
2339#define mmDCP5_DENORM_CONTROL 0x4950
2340#define mmDCP5_GAMUT_REMAP_C11_C12 0x495A
2341#define mmDCP5_GAMUT_REMAP_C13_C14 0x495B
2342#define mmDCP5_GAMUT_REMAP_C21_C22 0x495C
2343#define mmDCP5_GAMUT_REMAP_C23_C24 0x495D
2344#define mmDCP5_GAMUT_REMAP_C31_C32 0x495E
2345#define mmDCP5_GAMUT_REMAP_C33_C34 0x495F
2346#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959
2347#define mmDCP5_GRPH_COMPRESS_PITCH 0x491A
2348#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919
2349#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B
2350#define mmDCP5_GRPH_CONTROL 0x4901
2351#define mmDCP5_GRPH_DFQ_CONTROL 0x4914
2352#define mmDCP5_GRPH_DFQ_STATUS 0x4915
2353#define mmDCP5_GRPH_ENABLE 0x4900
2354#define mmDCP5_GRPH_FLIP_CONTROL 0x4912
2355#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917
2356#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916
2357#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902
2358#define mmDCP5_GRPH_PITCH 0x4906
2359#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904
2360#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907
2361#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905
2362#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908
2363#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997
2364#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918
2365#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913
2366#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909
2367#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A
2368#define mmDCP5_GRPH_SWAP_CNTL 0x4903
2369#define mmDCP5_GRPH_UPDATE 0x4911
2370#define mmDCP5_GRPH_X_END 0x490D
2371#define mmDCP5_GRPH_X_START 0x490B
2372#define mmDCP5_GRPH_Y_END 0x490E
2373#define mmDCP5_GRPH_Y_START 0x490C
2374#define mmDCP5_INPUT_CSC_C11_C12 0x4936
2375#define mmDCP5_INPUT_CSC_C13_C14 0x4937
2376#define mmDCP5_INPUT_CSC_C21_C22 0x4938
2377#define mmDCP5_INPUT_CSC_C23_C24 0x4939
2378#define mmDCP5_INPUT_CSC_C31_C32 0x493A
2379#define mmDCP5_INPUT_CSC_C33_C34 0x493B
2380#define mmDCP5_INPUT_CSC_CONTROL 0x4935
2381#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910
2382#define mmDCP5_KEY_CONTROL 0x4953
2383#define mmDCP5_KEY_RANGE_ALPHA 0x4954
2384#define mmDCP5_KEY_RANGE_BLUE 0x4957
2385#define mmDCP5_KEY_RANGE_GREEN 0x4956
2386#define mmDCP5_KEY_RANGE_RED 0x4955
2387#define mmDCP5_OUTPUT_CSC_C11_C12 0x493D
2388#define mmDCP5_OUTPUT_CSC_C13_C14 0x493E
2389#define mmDCP5_OUTPUT_CSC_C21_C22 0x493F
2390#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940
2391#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941
2392#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942
2393#define mmDCP5_OUTPUT_CSC_CONTROL 0x493C
2394#define mmDCP5_OUT_ROUND_CONTROL 0x4951
2395#define mmDCP5_OVL_CONTROL1 0x491D
2396#define mmDCP5_OVL_CONTROL2 0x491E
2397#define mmDCP5_OVL_DFQ_CONTROL 0x4929
2398#define mmDCP5_OVL_DFQ_STATUS 0x492A
2399#define mmDCP5_OVL_ENABLE 0x491C
2400#define mmDCP5_OVL_END 0x4926
2401#define mmDCP5_OVL_PITCH 0x4921
2402#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C
2403#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992
2404#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994
2405#define mmDCP5_OVL_START 0x4925
2406#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993
2407#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920
2408#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922
2409#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B
2410#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928
2411#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923
2412#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924
2413#define mmDCP5_OVL_SWAP_CNTL 0x491F
2414#define mmDCP5_OVL_UPDATE 0x4927
2415#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D
2416#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931
2417#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930
2418#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F
2419#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E
2420#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932
2421#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934
2422#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933
2423#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6
2424#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7
2425#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8
2426#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD
2427#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE
2428#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF
2429#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9
2430#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA
2431#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB
2432#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC
2433#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5
2434#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4
2435#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2
2436#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3
2437#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4
2438#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9
2439#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA
2440#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB
2441#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5
2442#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6
2443#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7
2444#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8
2445#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1
2446#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0
2447#define mmDCP5_REGAMMA_CONTROL 0x49A0
2448#define mmDCP5_REGAMMA_LUT_DATA 0x49A2
2449#define mmDCP5_REGAMMA_LUT_INDEX 0x49A1
2450#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3
2451#define mmDC_PAD_EXTERN_SIG 0x1902
2452#define mmDCP_CRC_CONTROL 0x1A87
2453#define mmDCP_CRC_CURRENT 0x1A89
2454#define mmDCP_CRC_LAST 0x1A8B
2455#define mmDCP_CRC_MASK 0x1A88
2456#define mmDCP_DEBUG 0x1A8D
2457#define mmDCP_DEBUG2 0x1A98
2458#define mmDCP_FP_CONVERTED_FIELD 0x1A65
2459#define mmDC_PGCNTL_STATUS_REG 0x177E
2460#define mmDC_PGFSM_CONFIG_REG 0x177C
2461#define mmDC_PGFSM_WRITE_REG 0x177D
2462#define mmDCP_GSL_CONTROL 0x1A90
2463#define mmDCPG_TEST_DEBUG_DATA 0x177B
2464#define mmDCPG_TEST_DEBUG_INDEX 0x1779
2465#define mmDC_PINSTRAPS 0x1917
2466#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91
2467#define mmDCP_RANDOM_SEEDS 0x1A61
2468#define mmDCP_SPATIAL_DITHER_CNTL 0x1A60
2469#define mmDCP_TEST_DEBUG_DATA 0x1A96
2470#define mmDCP_TEST_DEBUG_INDEX 0x1A95
2471#define mmDC_RBBMIF_RDWR_CNTL1 0x031A
2472#define mmDC_RBBMIF_RDWR_CNTL2 0x031D
2473#define mmDC_REF_CLK_CNTL 0x1903
2474#define mmDC_XDMA_INTERFACE_CNTL 0x0327
2475#define mmDEGAMMA_CONTROL 0x1A58
2476#define mmDENORM_CONTROL 0x1A50
2477#define mmDENTIST_DISPCLK_CNTL 0x0124
2478#define mmDIG0_AFMT_60958_0 0x1C41
2479#define mmDIG0_AFMT_60958_1 0x1C42
2480#define mmDIG0_AFMT_60958_2 0x1C48
2481#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43
2482#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49
2483#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52
2484#define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F
2485#define mmDIG0_AFMT_AUDIO_INFO1 0x1C40
2486#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B
2487#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17
2488#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F
2489#define mmDIG0_AFMT_AVI_INFO0 0x1C21
2490#define mmDIG0_AFMT_AVI_INFO1 0x1C22
2491#define mmDIG0_AFMT_AVI_INFO2 0x1C23
2492#define mmDIG0_AFMT_AVI_INFO3 0x1C24
2493#define mmDIG0_AFMT_GENERIC_0 0x1C28
2494#define mmDIG0_AFMT_GENERIC_1 0x1C29
2495#define mmDIG0_AFMT_GENERIC_2 0x1C2A
2496#define mmDIG0_AFMT_GENERIC_3 0x1C2B
2497#define mmDIG0_AFMT_GENERIC_4 0x1C2C
2498#define mmDIG0_AFMT_GENERIC_5 0x1C2D
2499#define mmDIG0_AFMT_GENERIC_6 0x1C2E
2500#define mmDIG0_AFMT_GENERIC_7 0x1C2F
2501#define mmDIG0_AFMT_GENERIC_HDR 0x1C27
2502#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D
2503#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14
2504#define mmDIG0_AFMT_ISRC1_0 0x1C18
2505#define mmDIG0_AFMT_ISRC1_1 0x1C19
2506#define mmDIG0_AFMT_ISRC1_2 0x1C1A
2507#define mmDIG0_AFMT_ISRC1_3 0x1C1B
2508#define mmDIG0_AFMT_ISRC1_4 0x1C1C
2509#define mmDIG0_AFMT_ISRC2_0 0x1C1D
2510#define mmDIG0_AFMT_ISRC2_1 0x1C1E
2511#define mmDIG0_AFMT_ISRC2_2 0x1C1F
2512#define mmDIG0_AFMT_ISRC2_3 0x1C20
2513#define mmDIG0_AFMT_MPEG_INFO0 0x1C25
2514#define mmDIG0_AFMT_MPEG_INFO1 0x1C26
2515#define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44
2516#define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45
2517#define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46
2518#define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47
2519#define mmDIG0_AFMT_STATUS 0x1C4A
2520#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C
2521#define mmDIG0_DIG_BE_CNTL 0x1C50
2522#define mmDIG0_DIG_BE_EN_CNTL 0x1C51
2523#define mmDIG0_DIG_CLOCK_PATTERN 0x1C03
2524#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08
2525#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09
2526#define mmDIG0_DIG_FE_CNTL 0x1C00
2527#define mmDIG0_DIG_FIFO_STATUS 0x1C0A
2528#define mmDIG0_DIG_LANE_ENABLE 0x1C8D
2529#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01
2530#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02
2531#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05
2532#define mmDIG0_DIG_TEST_PATTERN 0x1C04
2533#define mmDIG0_HDMI_ACR_32_0 0x1C37
2534#define mmDIG0_HDMI_ACR_32_1 0x1C38
2535#define mmDIG0_HDMI_ACR_44_0 0x1C39
2536#define mmDIG0_HDMI_ACR_44_1 0x1C3A
2537#define mmDIG0_HDMI_ACR_48_0 0x1C3B
2538#define mmDIG0_HDMI_ACR_48_1 0x1C3C
2539#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F
2540#define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D
2541#define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E
2542#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E
2543#define mmDIG0_HDMI_CONTROL 0x1C0C
2544#define mmDIG0_HDMI_GC 0x1C16
2545#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13
2546#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30
2547#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11
2548#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12
2549#define mmDIG0_HDMI_STATUS 0x1C0D
2550#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10
2551#define mmDIG0_LVDS_DATA_CNTL 0x1C8C
2552#define mmDIG0_TMDS_CNTL 0x1C7C
2553#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E
2554#define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D
2555#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86
2556#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87
2557#define mmDIG0_TMDS_CTL_BITS 0x1C83
2558#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84
2559#define mmDIG0_TMDS_DEBUG 0x1C82
2560#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F
2561#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80
2562#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81
2563#define mmDIG1_AFMT_60958_0 0x1F41
2564#define mmDIG1_AFMT_60958_1 0x1F42
2565#define mmDIG1_AFMT_60958_2 0x1F48
2566#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43
2567#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49
2568#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52
2569#define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F
2570#define mmDIG1_AFMT_AUDIO_INFO1 0x1F40
2571#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B
2572#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17
2573#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F
2574#define mmDIG1_AFMT_AVI_INFO0 0x1F21
2575#define mmDIG1_AFMT_AVI_INFO1 0x1F22
2576#define mmDIG1_AFMT_AVI_INFO2 0x1F23
2577#define mmDIG1_AFMT_AVI_INFO3 0x1F24
2578#define mmDIG1_AFMT_GENERIC_0 0x1F28
2579#define mmDIG1_AFMT_GENERIC_1 0x1F29
2580#define mmDIG1_AFMT_GENERIC_2 0x1F2A
2581#define mmDIG1_AFMT_GENERIC_3 0x1F2B
2582#define mmDIG1_AFMT_GENERIC_4 0x1F2C
2583#define mmDIG1_AFMT_GENERIC_5 0x1F2D
2584#define mmDIG1_AFMT_GENERIC_6 0x1F2E
2585#define mmDIG1_AFMT_GENERIC_7 0x1F2F
2586#define mmDIG1_AFMT_GENERIC_HDR 0x1F27
2587#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D
2588#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14
2589#define mmDIG1_AFMT_ISRC1_0 0x1F18
2590#define mmDIG1_AFMT_ISRC1_1 0x1F19
2591#define mmDIG1_AFMT_ISRC1_2 0x1F1A
2592#define mmDIG1_AFMT_ISRC1_3 0x1F1B
2593#define mmDIG1_AFMT_ISRC1_4 0x1F1C
2594#define mmDIG1_AFMT_ISRC2_0 0x1F1D
2595#define mmDIG1_AFMT_ISRC2_1 0x1F1E
2596#define mmDIG1_AFMT_ISRC2_2 0x1F1F
2597#define mmDIG1_AFMT_ISRC2_3 0x1F20
2598#define mmDIG1_AFMT_MPEG_INFO0 0x1F25
2599#define mmDIG1_AFMT_MPEG_INFO1 0x1F26
2600#define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44
2601#define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45
2602#define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46
2603#define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47
2604#define mmDIG1_AFMT_STATUS 0x1F4A
2605#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C
2606#define mmDIG1_DIG_BE_CNTL 0x1F50
2607#define mmDIG1_DIG_BE_EN_CNTL 0x1F51
2608#define mmDIG1_DIG_CLOCK_PATTERN 0x1F03
2609#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08
2610#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09
2611#define mmDIG1_DIG_FE_CNTL 0x1F00
2612#define mmDIG1_DIG_FIFO_STATUS 0x1F0A
2613#define mmDIG1_DIG_LANE_ENABLE 0x1F8D
2614#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01
2615#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02
2616#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05
2617#define mmDIG1_DIG_TEST_PATTERN 0x1F04
2618#define mmDIG1_HDMI_ACR_32_0 0x1F37
2619#define mmDIG1_HDMI_ACR_32_1 0x1F38
2620#define mmDIG1_HDMI_ACR_44_0 0x1F39
2621#define mmDIG1_HDMI_ACR_44_1 0x1F3A
2622#define mmDIG1_HDMI_ACR_48_0 0x1F3B
2623#define mmDIG1_HDMI_ACR_48_1 0x1F3C
2624#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F
2625#define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D
2626#define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E
2627#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E
2628#define mmDIG1_HDMI_CONTROL 0x1F0C
2629#define mmDIG1_HDMI_GC 0x1F16
2630#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13
2631#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30
2632#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11
2633#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12
2634#define mmDIG1_HDMI_STATUS 0x1F0D
2635#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10
2636#define mmDIG1_LVDS_DATA_CNTL 0x1F8C
2637#define mmDIG1_TMDS_CNTL 0x1F7C
2638#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E
2639#define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D
2640#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86
2641#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87
2642#define mmDIG1_TMDS_CTL_BITS 0x1F83
2643#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84
2644#define mmDIG1_TMDS_DEBUG 0x1F82
2645#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F
2646#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80
2647#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81
2648#define mmDIG2_AFMT_60958_0 0x4241
2649#define mmDIG2_AFMT_60958_1 0x4242
2650#define mmDIG2_AFMT_60958_2 0x4248
2651#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243
2652#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249
2653#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252
2654#define mmDIG2_AFMT_AUDIO_INFO0 0x423F
2655#define mmDIG2_AFMT_AUDIO_INFO1 0x4240
2656#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B
2657#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217
2658#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F
2659#define mmDIG2_AFMT_AVI_INFO0 0x4221
2660#define mmDIG2_AFMT_AVI_INFO1 0x4222
2661#define mmDIG2_AFMT_AVI_INFO2 0x4223
2662#define mmDIG2_AFMT_AVI_INFO3 0x4224
2663#define mmDIG2_AFMT_GENERIC_0 0x4228
2664#define mmDIG2_AFMT_GENERIC_1 0x4229
2665#define mmDIG2_AFMT_GENERIC_2 0x422A
2666#define mmDIG2_AFMT_GENERIC_3 0x422B
2667#define mmDIG2_AFMT_GENERIC_4 0x422C
2668#define mmDIG2_AFMT_GENERIC_5 0x422D
2669#define mmDIG2_AFMT_GENERIC_6 0x422E
2670#define mmDIG2_AFMT_GENERIC_7 0x422F
2671#define mmDIG2_AFMT_GENERIC_HDR 0x4227
2672#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D
2673#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214
2674#define mmDIG2_AFMT_ISRC1_0 0x4218
2675#define mmDIG2_AFMT_ISRC1_1 0x4219
2676#define mmDIG2_AFMT_ISRC1_2 0x421A
2677#define mmDIG2_AFMT_ISRC1_3 0x421B
2678#define mmDIG2_AFMT_ISRC1_4 0x421C
2679#define mmDIG2_AFMT_ISRC2_0 0x421D
2680#define mmDIG2_AFMT_ISRC2_1 0x421E
2681#define mmDIG2_AFMT_ISRC2_2 0x421F
2682#define mmDIG2_AFMT_ISRC2_3 0x4220
2683#define mmDIG2_AFMT_MPEG_INFO0 0x4225
2684#define mmDIG2_AFMT_MPEG_INFO1 0x4226
2685#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244
2686#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245
2687#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246
2688#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247
2689#define mmDIG2_AFMT_STATUS 0x424A
2690#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C
2691#define mmDIG2_DIG_BE_CNTL 0x4250
2692#define mmDIG2_DIG_BE_EN_CNTL 0x4251
2693#define mmDIG2_DIG_CLOCK_PATTERN 0x4203
2694#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208
2695#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209
2696#define mmDIG2_DIG_FE_CNTL 0x4200
2697#define mmDIG2_DIG_FIFO_STATUS 0x420A
2698#define mmDIG2_DIG_LANE_ENABLE 0x428D
2699#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201
2700#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202
2701#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205
2702#define mmDIG2_DIG_TEST_PATTERN 0x4204
2703#define mmDIG2_HDMI_ACR_32_0 0x4237
2704#define mmDIG2_HDMI_ACR_32_1 0x4238
2705#define mmDIG2_HDMI_ACR_44_0 0x4239
2706#define mmDIG2_HDMI_ACR_44_1 0x423A
2707#define mmDIG2_HDMI_ACR_48_0 0x423B
2708#define mmDIG2_HDMI_ACR_48_1 0x423C
2709#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F
2710#define mmDIG2_HDMI_ACR_STATUS_0 0x423D
2711#define mmDIG2_HDMI_ACR_STATUS_1 0x423E
2712#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E
2713#define mmDIG2_HDMI_CONTROL 0x420C
2714#define mmDIG2_HDMI_GC 0x4216
2715#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213
2716#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230
2717#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211
2718#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212
2719#define mmDIG2_HDMI_STATUS 0x420D
2720#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210
2721#define mmDIG2_LVDS_DATA_CNTL 0x428C
2722#define mmDIG2_TMDS_CNTL 0x427C
2723#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E
2724#define mmDIG2_TMDS_CONTROL_CHAR 0x427D
2725#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286
2726#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287
2727#define mmDIG2_TMDS_CTL_BITS 0x4283
2728#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284
2729#define mmDIG2_TMDS_DEBUG 0x4282
2730#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F
2731#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280
2732#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281
2733#define mmDIG3_AFMT_60958_0 0x4541
2734#define mmDIG3_AFMT_60958_1 0x4542
2735#define mmDIG3_AFMT_60958_2 0x4548
2736#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543
2737#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549
2738#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552
2739#define mmDIG3_AFMT_AUDIO_INFO0 0x453F
2740#define mmDIG3_AFMT_AUDIO_INFO1 0x4540
2741#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B
2742#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517
2743#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F
2744#define mmDIG3_AFMT_AVI_INFO0 0x4521
2745#define mmDIG3_AFMT_AVI_INFO1 0x4522
2746#define mmDIG3_AFMT_AVI_INFO2 0x4523
2747#define mmDIG3_AFMT_AVI_INFO3 0x4524
2748#define mmDIG3_AFMT_GENERIC_0 0x4528
2749#define mmDIG3_AFMT_GENERIC_1 0x4529
2750#define mmDIG3_AFMT_GENERIC_2 0x452A
2751#define mmDIG3_AFMT_GENERIC_3 0x452B
2752#define mmDIG3_AFMT_GENERIC_4 0x452C
2753#define mmDIG3_AFMT_GENERIC_5 0x452D
2754#define mmDIG3_AFMT_GENERIC_6 0x452E
2755#define mmDIG3_AFMT_GENERIC_7 0x452F
2756#define mmDIG3_AFMT_GENERIC_HDR 0x4527
2757#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D
2758#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514
2759#define mmDIG3_AFMT_ISRC1_0 0x4518
2760#define mmDIG3_AFMT_ISRC1_1 0x4519
2761#define mmDIG3_AFMT_ISRC1_2 0x451A
2762#define mmDIG3_AFMT_ISRC1_3 0x451B
2763#define mmDIG3_AFMT_ISRC1_4 0x451C
2764#define mmDIG3_AFMT_ISRC2_0 0x451D
2765#define mmDIG3_AFMT_ISRC2_1 0x451E
2766#define mmDIG3_AFMT_ISRC2_2 0x451F
2767#define mmDIG3_AFMT_ISRC2_3 0x4520
2768#define mmDIG3_AFMT_MPEG_INFO0 0x4525
2769#define mmDIG3_AFMT_MPEG_INFO1 0x4526
2770#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544
2771#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545
2772#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546
2773#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547
2774#define mmDIG3_AFMT_STATUS 0x454A
2775#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C
2776#define mmDIG3_DIG_BE_CNTL 0x4550
2777#define mmDIG3_DIG_BE_EN_CNTL 0x4551
2778#define mmDIG3_DIG_CLOCK_PATTERN 0x4503
2779#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508
2780#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509
2781#define mmDIG3_DIG_FE_CNTL 0x4500
2782#define mmDIG3_DIG_FIFO_STATUS 0x450A
2783#define mmDIG3_DIG_LANE_ENABLE 0x458D
2784#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501
2785#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502
2786#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505
2787#define mmDIG3_DIG_TEST_PATTERN 0x4504
2788#define mmDIG3_HDMI_ACR_32_0 0x4537
2789#define mmDIG3_HDMI_ACR_32_1 0x4538
2790#define mmDIG3_HDMI_ACR_44_0 0x4539
2791#define mmDIG3_HDMI_ACR_44_1 0x453A
2792#define mmDIG3_HDMI_ACR_48_0 0x453B
2793#define mmDIG3_HDMI_ACR_48_1 0x453C
2794#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F
2795#define mmDIG3_HDMI_ACR_STATUS_0 0x453D
2796#define mmDIG3_HDMI_ACR_STATUS_1 0x453E
2797#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E
2798#define mmDIG3_HDMI_CONTROL 0x450C
2799#define mmDIG3_HDMI_GC 0x4516
2800#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513
2801#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530
2802#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511
2803#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512
2804#define mmDIG3_HDMI_STATUS 0x450D
2805#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510
2806#define mmDIG3_LVDS_DATA_CNTL 0x458C
2807#define mmDIG3_TMDS_CNTL 0x457C
2808#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E
2809#define mmDIG3_TMDS_CONTROL_CHAR 0x457D
2810#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586
2811#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587
2812#define mmDIG3_TMDS_CTL_BITS 0x4583
2813#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584
2814#define mmDIG3_TMDS_DEBUG 0x4582
2815#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F
2816#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580
2817#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581
2818#define mmDIG4_AFMT_60958_0 0x4841
2819#define mmDIG4_AFMT_60958_1 0x4842
2820#define mmDIG4_AFMT_60958_2 0x4848
2821#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843
2822#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849
2823#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852
2824#define mmDIG4_AFMT_AUDIO_INFO0 0x483F
2825#define mmDIG4_AFMT_AUDIO_INFO1 0x4840
2826#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B
2827#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817
2828#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F
2829#define mmDIG4_AFMT_AVI_INFO0 0x4821
2830#define mmDIG4_AFMT_AVI_INFO1 0x4822
2831#define mmDIG4_AFMT_AVI_INFO2 0x4823
2832#define mmDIG4_AFMT_AVI_INFO3 0x4824
2833#define mmDIG4_AFMT_GENERIC_0 0x4828
2834#define mmDIG4_AFMT_GENERIC_1 0x4829
2835#define mmDIG4_AFMT_GENERIC_2 0x482A
2836#define mmDIG4_AFMT_GENERIC_3 0x482B
2837#define mmDIG4_AFMT_GENERIC_4 0x482C
2838#define mmDIG4_AFMT_GENERIC_5 0x482D
2839#define mmDIG4_AFMT_GENERIC_6 0x482E
2840#define mmDIG4_AFMT_GENERIC_7 0x482F
2841#define mmDIG4_AFMT_GENERIC_HDR 0x4827
2842#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D
2843#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814
2844#define mmDIG4_AFMT_ISRC1_0 0x4818
2845#define mmDIG4_AFMT_ISRC1_1 0x4819
2846#define mmDIG4_AFMT_ISRC1_2 0x481A
2847#define mmDIG4_AFMT_ISRC1_3 0x481B
2848#define mmDIG4_AFMT_ISRC1_4 0x481C
2849#define mmDIG4_AFMT_ISRC2_0 0x481D
2850#define mmDIG4_AFMT_ISRC2_1 0x481E
2851#define mmDIG4_AFMT_ISRC2_2 0x481F
2852#define mmDIG4_AFMT_ISRC2_3 0x4820
2853#define mmDIG4_AFMT_MPEG_INFO0 0x4825
2854#define mmDIG4_AFMT_MPEG_INFO1 0x4826
2855#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844
2856#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845
2857#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846
2858#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847
2859#define mmDIG4_AFMT_STATUS 0x484A
2860#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C
2861#define mmDIG4_DIG_BE_CNTL 0x4850
2862#define mmDIG4_DIG_BE_EN_CNTL 0x4851
2863#define mmDIG4_DIG_CLOCK_PATTERN 0x4803
2864#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808
2865#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809
2866#define mmDIG4_DIG_FE_CNTL 0x4800
2867#define mmDIG4_DIG_FIFO_STATUS 0x480A
2868#define mmDIG4_DIG_LANE_ENABLE 0x488D
2869#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801
2870#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802
2871#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805
2872#define mmDIG4_DIG_TEST_PATTERN 0x4804
2873#define mmDIG4_HDMI_ACR_32_0 0x4837
2874#define mmDIG4_HDMI_ACR_32_1 0x4838
2875#define mmDIG4_HDMI_ACR_44_0 0x4839
2876#define mmDIG4_HDMI_ACR_44_1 0x483A
2877#define mmDIG4_HDMI_ACR_48_0 0x483B
2878#define mmDIG4_HDMI_ACR_48_1 0x483C
2879#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F
2880#define mmDIG4_HDMI_ACR_STATUS_0 0x483D
2881#define mmDIG4_HDMI_ACR_STATUS_1 0x483E
2882#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E
2883#define mmDIG4_HDMI_CONTROL 0x480C
2884#define mmDIG4_HDMI_GC 0x4816
2885#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813
2886#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830
2887#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811
2888#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812
2889#define mmDIG4_HDMI_STATUS 0x480D
2890#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810
2891#define mmDIG4_LVDS_DATA_CNTL 0x488C
2892#define mmDIG4_TMDS_CNTL 0x487C
2893#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E
2894#define mmDIG4_TMDS_CONTROL_CHAR 0x487D
2895#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886
2896#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887
2897#define mmDIG4_TMDS_CTL_BITS 0x4883
2898#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884
2899#define mmDIG4_TMDS_DEBUG 0x4882
2900#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F
2901#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880
2902#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881
2903#define mmDIG5_AFMT_60958_0 0x4B41
2904#define mmDIG5_AFMT_60958_1 0x4B42
2905#define mmDIG5_AFMT_60958_2 0x4B48
2906#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43
2907#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49
2908#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52
2909#define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F
2910#define mmDIG5_AFMT_AUDIO_INFO1 0x4B40
2911#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B
2912#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17
2913#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F
2914#define mmDIG5_AFMT_AVI_INFO0 0x4B21
2915#define mmDIG5_AFMT_AVI_INFO1 0x4B22
2916#define mmDIG5_AFMT_AVI_INFO2 0x4B23
2917#define mmDIG5_AFMT_AVI_INFO3 0x4B24
2918#define mmDIG5_AFMT_GENERIC_0 0x4B28
2919#define mmDIG5_AFMT_GENERIC_1 0x4B29
2920#define mmDIG5_AFMT_GENERIC_2 0x4B2A
2921#define mmDIG5_AFMT_GENERIC_3 0x4B2B
2922#define mmDIG5_AFMT_GENERIC_4 0x4B2C
2923#define mmDIG5_AFMT_GENERIC_5 0x4B2D
2924#define mmDIG5_AFMT_GENERIC_6 0x4B2E
2925#define mmDIG5_AFMT_GENERIC_7 0x4B2F
2926#define mmDIG5_AFMT_GENERIC_HDR 0x4B27
2927#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D
2928#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14
2929#define mmDIG5_AFMT_ISRC1_0 0x4B18
2930#define mmDIG5_AFMT_ISRC1_1 0x4B19
2931#define mmDIG5_AFMT_ISRC1_2 0x4B1A
2932#define mmDIG5_AFMT_ISRC1_3 0x4B1B
2933#define mmDIG5_AFMT_ISRC1_4 0x4B1C
2934#define mmDIG5_AFMT_ISRC2_0 0x4B1D
2935#define mmDIG5_AFMT_ISRC2_1 0x4B1E
2936#define mmDIG5_AFMT_ISRC2_2 0x4B1F
2937#define mmDIG5_AFMT_ISRC2_3 0x4B20
2938#define mmDIG5_AFMT_MPEG_INFO0 0x4B25
2939#define mmDIG5_AFMT_MPEG_INFO1 0x4B26
2940#define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44
2941#define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45
2942#define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46
2943#define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47
2944#define mmDIG5_AFMT_STATUS 0x4B4A
2945#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C
2946#define mmDIG5_DIG_BE_CNTL 0x4B50
2947#define mmDIG5_DIG_BE_EN_CNTL 0x4B51
2948#define mmDIG5_DIG_CLOCK_PATTERN 0x4B03
2949#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08
2950#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09
2951#define mmDIG5_DIG_FE_CNTL 0x4B00
2952#define mmDIG5_DIG_FIFO_STATUS 0x4B0A
2953#define mmDIG5_DIG_LANE_ENABLE 0x4B8D
2954#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01
2955#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02
2956#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05
2957#define mmDIG5_DIG_TEST_PATTERN 0x4B04
2958#define mmDIG5_HDMI_ACR_32_0 0x4B37
2959#define mmDIG5_HDMI_ACR_32_1 0x4B38
2960#define mmDIG5_HDMI_ACR_44_0 0x4B39
2961#define mmDIG5_HDMI_ACR_44_1 0x4B3A
2962#define mmDIG5_HDMI_ACR_48_0 0x4B3B
2963#define mmDIG5_HDMI_ACR_48_1 0x4B3C
2964#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F
2965#define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D
2966#define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E
2967#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E
2968#define mmDIG5_HDMI_CONTROL 0x4B0C
2969#define mmDIG5_HDMI_GC 0x4B16
2970#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13
2971#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30
2972#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11
2973#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12
2974#define mmDIG5_HDMI_STATUS 0x4B0D
2975#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10
2976#define mmDIG5_LVDS_DATA_CNTL 0x4B8C
2977#define mmDIG5_TMDS_CNTL 0x4B7C
2978#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E
2979#define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D
2980#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86
2981#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87
2982#define mmDIG5_TMDS_CTL_BITS 0x4B83
2983#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84
2984#define mmDIG5_TMDS_DEBUG 0x4B82
2985#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F
2986#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80
2987#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81
2988#define mmDIG_BE_CNTL 0x1C50
2989#define mmDIG_BE_EN_CNTL 0x1C51
2990#define mmDIG_CLOCK_PATTERN 0x1C03
2991#define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08
2992#define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09
2993#define mmDIG_FE_CNTL 0x1C00
2994#define mmDIG_FIFO_STATUS 0x1C0A
2995#define mmDIG_LANE_ENABLE 0x1C8D
2996#define mmDIG_OUTPUT_CRC_CNTL 0x1C01
2997#define mmDIG_OUTPUT_CRC_RESULT 0x1C02
2998#define mmDIG_RANDOM_PATTERN_SEED 0x1C05
2999#define mmDIG_SOFT_RESET 0x013D
3000#define mmDIG_TEST_PATTERN 0x1C04
3001#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135
3002#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131
3003#define mmDISP_INTERRUPT_STATUS 0x183D
3004#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E
3005#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F
3006#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840
3007#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853
3008#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854
3009#define mmDISPOUT_STEREOSYNC_SEL 0x18BF
3010#define mmDISPPLL_BG_CNTL 0x013C
3011#define mmDISP_TIMER_CONTROL 0x1842
3012#define mmDMCU_CTRL 0x1600
3013#define mmDMCU_ERAM_RD_CTRL 0x160B
3014#define mmDMCU_ERAM_RD_DATA 0x160C
3015#define mmDMCU_ERAM_WR_CTRL 0x1609
3016#define mmDMCU_ERAM_WR_DATA 0x160A
3017#define mmDMCU_EVENT_TRIGGER 0x1611
3018#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A
3019#define mmDMCU_FW_CS_HI 0x1606
3020#define mmDMCU_FW_CS_LO 0x1607
3021#define mmDMCU_FW_END_ADDR 0x1604
3022#define mmDMCU_FW_ISR_START_ADDR 0x1605
3023#define mmDMCU_FW_START_ADDR 0x1603
3024#define mmDMCU_INT_CNT 0x1619
3025#define mmDMCU_INTERRUPT_STATUS 0x1614
3026#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
3027#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
3028#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
3029#define mmDMCU_IRAM_RD_CTRL 0x160F
3030#define mmDMCU_IRAM_RD_DATA 0x1610
3031#define mmDMCU_IRAM_WR_CTRL 0x160D
3032#define mmDMCU_IRAM_WR_DATA 0x160E
3033#define mmDMCU_PC_START_ADDR 0x1602
3034#define mmDMCU_RAM_ACCESS_CTRL 0x1608
3035#define mmDMCU_STATUS 0x1601
3036#define mmDMCU_TEST_DEBUG_DATA 0x1627
3037#define mmDMCU_TEST_DEBUG_INDEX 0x1626
3038#define mmDMCU_UC_CLK_GATING_CNTL 0x161B
3039#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
3040#define mmDMIF_ADDR_CALC 0x0300
3041#define mmDMIF_ADDR_CONFIG 0x02F5
3042#define mmDMIF_ARBITRATION_CONTROL 0x02F9
3043#define mmDMIF_CONTROL 0x02F6
3044#define mmDMIF_HW_DEBUG 0x02F8
3045#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30
3046#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31
3047#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34
3048#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36
3049#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35
3050#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37
3051#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33
3052#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39
3053#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38
3054#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30
3055#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31
3056#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34
3057#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36
3058#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35
3059#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37
3060#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33
3061#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39
3062#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38
3063#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
3064#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
3065#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134
3066#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
3067#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135
3068#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
3069#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133
3070#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139
3071#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138
3072#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430
3073#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431
3074#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434
3075#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436
3076#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435
3077#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437
3078#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433
3079#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439
3080#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438
3081#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730
3082#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731
3083#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734
3084#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
3085#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735
3086#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
3087#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733
3088#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739
3089#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738
3090#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30
3091#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31
3092#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34
3093#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36
3094#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35
3095#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37
3096#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33
3097#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39
3098#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38
3099#define mmDMIF_STATUS 0x02F7
3100#define mmDMIF_STATUS2 0x0301
3101#define mmDMIF_TEST_DEBUG_DATA 0x0313
3102#define mmDMIF_TEST_DEBUG_INDEX 0x0312
3103#define mmDOUT_DCE_VCE_CONTROL 0x18FF
3104#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841
3105#define mmDOUT_SCRATCH0 0x1844
3106#define mmDOUT_SCRATCH1 0x1845
3107#define mmDOUT_SCRATCH2 0x1846
3108#define mmDOUT_SCRATCH3 0x1847
3109#define mmDOUT_SCRATCH4 0x1848
3110#define mmDOUT_SCRATCH5 0x1849
3111#define mmDOUT_SCRATCH6 0x184A
3112#define mmDOUT_SCRATCH7 0x184B
3113#define mmDOUT_TEST_DEBUG_DATA 0x184E
3114#define mmDOUT_TEST_DEBUG_INDEX 0x184D
3115#define mmDP0_DP_CONFIG 0x1CC2
3116#define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3
3117#define mmDP0_DP_DPHY_CNTL 0x1CD0
3118#define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7
3119#define mmDP0_DP_DPHY_CRC_EN 0x1CD6
3120#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6
3121#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7
3122#define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8
3123#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
3124#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9
3125#define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4
3126#define mmDP0_DP_DPHY_SYM0 0x1CD2
3127#define mmDP0_DP_DPHY_SYM1 0x1CE0
3128#define mmDP0_DP_DPHY_SYM2 0x1CDF
3129#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1
3130#define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8
3131#define mmDP0_DP_LINK_CNTL 0x1CC0
3132#define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC
3133#define mmDP0_DP_MSA_COLORIMETRY 0x1CDA
3134#define mmDP0_DP_MSA_MISC 0x1CC5
3135#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA
3136#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB
3137#define mmDP0_DP_MSE_LINK_TIMING 0x1CE8
3138#define mmDP0_DP_MSE_MISC_CNTL 0x1CDB
3139#define mmDP0_DP_MSE_RATE_CNTL 0x1CE1
3140#define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3
3141#define mmDP0_DP_MSE_SAT0 0x1CE4
3142#define mmDP0_DP_MSE_SAT1 0x1CE5
3143#define mmDP0_DP_MSE_SAT2 0x1CE6
3144#define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7
3145#define mmDP0_DP_PIXEL_FORMAT 0x1CC1
3146#define mmDP0_DP_SEC_AUD_M 0x1CA7
3147#define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8
3148#define mmDP0_DP_SEC_AUD_N 0x1CA5
3149#define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6
3150#define mmDP0_DP_SEC_CNTL 0x1CA0
3151#define mmDP0_DP_SEC_CNTL1 0x1CAB
3152#define mmDP0_DP_SEC_FRAMING1 0x1CA1
3153#define mmDP0_DP_SEC_FRAMING2 0x1CA2
3154#define mmDP0_DP_SEC_FRAMING3 0x1CA3
3155#define mmDP0_DP_SEC_FRAMING4 0x1CA4
3156#define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA
3157#define mmDP0_DP_SEC_TIMESTAMP 0x1CA9
3158#define mmDP0_DP_STEER_FIFO 0x1CC4
3159#define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD
3160#define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC
3161#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF
3162#define mmDP0_DP_VID_M 0x1CCB
3163#define mmDP0_DP_VID_MSA_VBID 0x1CCD
3164#define mmDP0_DP_VID_N 0x1CCA
3165#define mmDP0_DP_VID_STREAM_CNTL 0x1CC3
3166#define mmDP0_DP_VID_TIMING 0x1CC9
3167#define mmDP1_DP_CONFIG 0x1FC2
3168#define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3
3169#define mmDP1_DP_DPHY_CNTL 0x1FD0
3170#define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7
3171#define mmDP1_DP_DPHY_CRC_EN 0x1FD6
3172#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6
3173#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7
3174#define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8
3175#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
3176#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9
3177#define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4
3178#define mmDP1_DP_DPHY_SYM0 0x1FD2
3179#define mmDP1_DP_DPHY_SYM1 0x1FE0
3180#define mmDP1_DP_DPHY_SYM2 0x1FDF
3181#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1
3182#define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8
3183#define mmDP1_DP_LINK_CNTL 0x1FC0
3184#define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC
3185#define mmDP1_DP_MSA_COLORIMETRY 0x1FDA
3186#define mmDP1_DP_MSA_MISC 0x1FC5
3187#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA
3188#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB
3189#define mmDP1_DP_MSE_LINK_TIMING 0x1FE8
3190#define mmDP1_DP_MSE_MISC_CNTL 0x1FDB
3191#define mmDP1_DP_MSE_RATE_CNTL 0x1FE1
3192#define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3
3193#define mmDP1_DP_MSE_SAT0 0x1FE4
3194#define mmDP1_DP_MSE_SAT1 0x1FE5
3195#define mmDP1_DP_MSE_SAT2 0x1FE6
3196#define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7
3197#define mmDP1_DP_PIXEL_FORMAT 0x1FC1
3198#define mmDP1_DP_SEC_AUD_M 0x1FA7
3199#define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8
3200#define mmDP1_DP_SEC_AUD_N 0x1FA5
3201#define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6
3202#define mmDP1_DP_SEC_CNTL 0x1FA0
3203#define mmDP1_DP_SEC_CNTL1 0x1FAB
3204#define mmDP1_DP_SEC_FRAMING1 0x1FA1
3205#define mmDP1_DP_SEC_FRAMING2 0x1FA2
3206#define mmDP1_DP_SEC_FRAMING3 0x1FA3
3207#define mmDP1_DP_SEC_FRAMING4 0x1FA4
3208#define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA
3209#define mmDP1_DP_SEC_TIMESTAMP 0x1FA9
3210#define mmDP1_DP_STEER_FIFO 0x1FC4
3211#define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD
3212#define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC
3213#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF
3214#define mmDP1_DP_VID_M 0x1FCB
3215#define mmDP1_DP_VID_MSA_VBID 0x1FCD
3216#define mmDP1_DP_VID_N 0x1FCA
3217#define mmDP1_DP_VID_STREAM_CNTL 0x1FC3
3218#define mmDP1_DP_VID_TIMING 0x1FC9
3219#define mmDP2_DP_CONFIG 0x42C2
3220#define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3
3221#define mmDP2_DP_DPHY_CNTL 0x42D0
3222#define mmDP2_DP_DPHY_CRC_CNTL 0x42D7
3223#define mmDP2_DP_DPHY_CRC_EN 0x42D6
3224#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6
3225#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7
3226#define mmDP2_DP_DPHY_CRC_RESULT 0x42D8
3227#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
3228#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9
3229#define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4
3230#define mmDP2_DP_DPHY_SYM0 0x42D2
3231#define mmDP2_DP_DPHY_SYM1 0x42E0
3232#define mmDP2_DP_DPHY_SYM2 0x42DF
3233#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1
3234#define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8
3235#define mmDP2_DP_LINK_CNTL 0x42C0
3236#define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC
3237#define mmDP2_DP_MSA_COLORIMETRY 0x42DA
3238#define mmDP2_DP_MSA_MISC 0x42C5
3239#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA
3240#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB
3241#define mmDP2_DP_MSE_LINK_TIMING 0x42E8
3242#define mmDP2_DP_MSE_MISC_CNTL 0x42DB
3243#define mmDP2_DP_MSE_RATE_CNTL 0x42E1
3244#define mmDP2_DP_MSE_RATE_UPDATE 0x42E3
3245#define mmDP2_DP_MSE_SAT0 0x42E4
3246#define mmDP2_DP_MSE_SAT1 0x42E5
3247#define mmDP2_DP_MSE_SAT2 0x42E6
3248#define mmDP2_DP_MSE_SAT_UPDATE 0x42E7
3249#define mmDP2_DP_PIXEL_FORMAT 0x42C1
3250#define mmDP2_DP_SEC_AUD_M 0x42A7
3251#define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8
3252#define mmDP2_DP_SEC_AUD_N 0x42A5
3253#define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6
3254#define mmDP2_DP_SEC_CNTL 0x42A0
3255#define mmDP2_DP_SEC_CNTL1 0x42AB
3256#define mmDP2_DP_SEC_FRAMING1 0x42A1
3257#define mmDP2_DP_SEC_FRAMING2 0x42A2
3258#define mmDP2_DP_SEC_FRAMING3 0x42A3
3259#define mmDP2_DP_SEC_FRAMING4 0x42A4
3260#define mmDP2_DP_SEC_PACKET_CNTL 0x42AA
3261#define mmDP2_DP_SEC_TIMESTAMP 0x42A9
3262#define mmDP2_DP_STEER_FIFO 0x42C4
3263#define mmDP2_DP_TEST_DEBUG_DATA 0x42FD
3264#define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC
3265#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF
3266#define mmDP2_DP_VID_M 0x42CB
3267#define mmDP2_DP_VID_MSA_VBID 0x42CD
3268#define mmDP2_DP_VID_N 0x42CA
3269#define mmDP2_DP_VID_STREAM_CNTL 0x42C3
3270#define mmDP2_DP_VID_TIMING 0x42C9
3271#define mmDP3_DP_CONFIG 0x45C2
3272#define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3
3273#define mmDP3_DP_DPHY_CNTL 0x45D0
3274#define mmDP3_DP_DPHY_CRC_CNTL 0x45D7
3275#define mmDP3_DP_DPHY_CRC_EN 0x45D6
3276#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6
3277#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7
3278#define mmDP3_DP_DPHY_CRC_RESULT 0x45D8
3279#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
3280#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9
3281#define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4
3282#define mmDP3_DP_DPHY_SYM0 0x45D2
3283#define mmDP3_DP_DPHY_SYM1 0x45E0
3284#define mmDP3_DP_DPHY_SYM2 0x45DF
3285#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1
3286#define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8
3287#define mmDP3_DP_LINK_CNTL 0x45C0
3288#define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC
3289#define mmDP3_DP_MSA_COLORIMETRY 0x45DA
3290#define mmDP3_DP_MSA_MISC 0x45C5
3291#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA
3292#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB
3293#define mmDP3_DP_MSE_LINK_TIMING 0x45E8
3294#define mmDP3_DP_MSE_MISC_CNTL 0x45DB
3295#define mmDP3_DP_MSE_RATE_CNTL 0x45E1
3296#define mmDP3_DP_MSE_RATE_UPDATE 0x45E3
3297#define mmDP3_DP_MSE_SAT0 0x45E4
3298#define mmDP3_DP_MSE_SAT1 0x45E5
3299#define mmDP3_DP_MSE_SAT2 0x45E6
3300#define mmDP3_DP_MSE_SAT_UPDATE 0x45E7
3301#define mmDP3_DP_PIXEL_FORMAT 0x45C1
3302#define mmDP3_DP_SEC_AUD_M 0x45A7
3303#define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8
3304#define mmDP3_DP_SEC_AUD_N 0x45A5
3305#define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6
3306#define mmDP3_DP_SEC_CNTL 0x45A0
3307#define mmDP3_DP_SEC_CNTL1 0x45AB
3308#define mmDP3_DP_SEC_FRAMING1 0x45A1
3309#define mmDP3_DP_SEC_FRAMING2 0x45A2
3310#define mmDP3_DP_SEC_FRAMING3 0x45A3
3311#define mmDP3_DP_SEC_FRAMING4 0x45A4
3312#define mmDP3_DP_SEC_PACKET_CNTL 0x45AA
3313#define mmDP3_DP_SEC_TIMESTAMP 0x45A9
3314#define mmDP3_DP_STEER_FIFO 0x45C4
3315#define mmDP3_DP_TEST_DEBUG_DATA 0x45FD
3316#define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC
3317#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF
3318#define mmDP3_DP_VID_M 0x45CB
3319#define mmDP3_DP_VID_MSA_VBID 0x45CD
3320#define mmDP3_DP_VID_N 0x45CA
3321#define mmDP3_DP_VID_STREAM_CNTL 0x45C3
3322#define mmDP3_DP_VID_TIMING 0x45C9
3323#define mmDP4_DP_CONFIG 0x48C2
3324#define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3
3325#define mmDP4_DP_DPHY_CNTL 0x48D0
3326#define mmDP4_DP_DPHY_CRC_CNTL 0x48D7
3327#define mmDP4_DP_DPHY_CRC_EN 0x48D6
3328#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6
3329#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7
3330#define mmDP4_DP_DPHY_CRC_RESULT 0x48D8
3331#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
3332#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9
3333#define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4
3334#define mmDP4_DP_DPHY_SYM0 0x48D2
3335#define mmDP4_DP_DPHY_SYM1 0x48E0
3336#define mmDP4_DP_DPHY_SYM2 0x48DF
3337#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1
3338#define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8
3339#define mmDP4_DP_LINK_CNTL 0x48C0
3340#define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC
3341#define mmDP4_DP_MSA_COLORIMETRY 0x48DA
3342#define mmDP4_DP_MSA_MISC 0x48C5
3343#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA
3344#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB
3345#define mmDP4_DP_MSE_LINK_TIMING 0x48E8
3346#define mmDP4_DP_MSE_MISC_CNTL 0x48DB
3347#define mmDP4_DP_MSE_RATE_CNTL 0x48E1
3348#define mmDP4_DP_MSE_RATE_UPDATE 0x48E3
3349#define mmDP4_DP_MSE_SAT0 0x48E4
3350#define mmDP4_DP_MSE_SAT1 0x48E5
3351#define mmDP4_DP_MSE_SAT2 0x48E6
3352#define mmDP4_DP_MSE_SAT_UPDATE 0x48E7
3353#define mmDP4_DP_PIXEL_FORMAT 0x48C1
3354#define mmDP4_DP_SEC_AUD_M 0x48A7
3355#define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8
3356#define mmDP4_DP_SEC_AUD_N 0x48A5
3357#define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6
3358#define mmDP4_DP_SEC_CNTL 0x48A0
3359#define mmDP4_DP_SEC_CNTL1 0x48AB
3360#define mmDP4_DP_SEC_FRAMING1 0x48A1
3361#define mmDP4_DP_SEC_FRAMING2 0x48A2
3362#define mmDP4_DP_SEC_FRAMING3 0x48A3
3363#define mmDP4_DP_SEC_FRAMING4 0x48A4
3364#define mmDP4_DP_SEC_PACKET_CNTL 0x48AA
3365#define mmDP4_DP_SEC_TIMESTAMP 0x48A9
3366#define mmDP4_DP_STEER_FIFO 0x48C4
3367#define mmDP4_DP_TEST_DEBUG_DATA 0x48FD
3368#define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC
3369#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF
3370#define mmDP4_DP_VID_M 0x48CB
3371#define mmDP4_DP_VID_MSA_VBID 0x48CD
3372#define mmDP4_DP_VID_N 0x48CA
3373#define mmDP4_DP_VID_STREAM_CNTL 0x48C3
3374#define mmDP4_DP_VID_TIMING 0x48C9
3375#define mmDP5_DP_CONFIG 0x4BC2
3376#define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3
3377#define mmDP5_DP_DPHY_CNTL 0x4BD0
3378#define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7
3379#define mmDP5_DP_DPHY_CRC_EN 0x4BD6
3380#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6
3381#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7
3382#define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8
3383#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
3384#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9
3385#define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4
3386#define mmDP5_DP_DPHY_SYM0 0x4BD2
3387#define mmDP5_DP_DPHY_SYM1 0x4BE0
3388#define mmDP5_DP_DPHY_SYM2 0x4BDF
3389#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1
3390#define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8
3391#define mmDP5_DP_LINK_CNTL 0x4BC0
3392#define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC
3393#define mmDP5_DP_MSA_COLORIMETRY 0x4BDA
3394#define mmDP5_DP_MSA_MISC 0x4BC5
3395#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA
3396#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB
3397#define mmDP5_DP_MSE_LINK_TIMING 0x4BE8
3398#define mmDP5_DP_MSE_MISC_CNTL 0x4BDB
3399#define mmDP5_DP_MSE_RATE_CNTL 0x4BE1
3400#define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3
3401#define mmDP5_DP_MSE_SAT0 0x4BE4
3402#define mmDP5_DP_MSE_SAT1 0x4BE5
3403#define mmDP5_DP_MSE_SAT2 0x4BE6
3404#define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7
3405#define mmDP5_DP_PIXEL_FORMAT 0x4BC1
3406#define mmDP5_DP_SEC_AUD_M 0x4BA7
3407#define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8
3408#define mmDP5_DP_SEC_AUD_N 0x4BA5
3409#define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6
3410#define mmDP5_DP_SEC_CNTL 0x4BA0
3411#define mmDP5_DP_SEC_CNTL1 0x4BAB
3412#define mmDP5_DP_SEC_FRAMING1 0x4BA1
3413#define mmDP5_DP_SEC_FRAMING2 0x4BA2
3414#define mmDP5_DP_SEC_FRAMING3 0x4BA3
3415#define mmDP5_DP_SEC_FRAMING4 0x4BA4
3416#define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA
3417#define mmDP5_DP_SEC_TIMESTAMP 0x4BA9
3418#define mmDP5_DP_STEER_FIFO 0x4BC4
3419#define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD
3420#define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC
3421#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF
3422#define mmDP5_DP_VID_M 0x4BCB
3423#define mmDP5_DP_VID_MSA_VBID 0x4BCD
3424#define mmDP5_DP_VID_N 0x4BCA
3425#define mmDP5_DP_VID_STREAM_CNTL 0x4BC3
3426#define mmDP5_DP_VID_TIMING 0x4BC9
3427#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882
3428#define mmDP_AUX0_AUX_CONTROL 0x1880
3429#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A
3430#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B
3431#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D
3432#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889
3433#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888
3434#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C
3435#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E
3436#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890
3437#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883
3438#define mmDP_AUX0_AUX_LS_DATA 0x1887
3439#define mmDP_AUX0_AUX_LS_STATUS 0x1885
3440#define mmDP_AUX0_AUX_SW_CONTROL 0x1881
3441#define mmDP_AUX0_AUX_SW_DATA 0x1886
3442#define mmDP_AUX0_AUX_SW_STATUS 0x1884
3443#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896
3444#define mmDP_AUX1_AUX_CONTROL 0x1894
3445#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E
3446#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F
3447#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1
3448#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D
3449#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C
3450#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0
3451#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2
3452#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4
3453#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897
3454#define mmDP_AUX1_AUX_LS_DATA 0x189B
3455#define mmDP_AUX1_AUX_LS_STATUS 0x1899
3456#define mmDP_AUX1_AUX_SW_CONTROL 0x1895
3457#define mmDP_AUX1_AUX_SW_DATA 0x189A
3458#define mmDP_AUX1_AUX_SW_STATUS 0x1898
3459#define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA
3460#define mmDP_AUX2_AUX_CONTROL 0x18A8
3461#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2
3462#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3
3463#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5
3464#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1
3465#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0
3466#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4
3467#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6
3468#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8
3469#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB
3470#define mmDP_AUX2_AUX_LS_DATA 0x18AF
3471#define mmDP_AUX2_AUX_LS_STATUS 0x18AD
3472#define mmDP_AUX2_AUX_SW_CONTROL 0x18A9
3473#define mmDP_AUX2_AUX_SW_DATA 0x18AE
3474#define mmDP_AUX2_AUX_SW_STATUS 0x18AC
3475#define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2
3476#define mmDP_AUX3_AUX_CONTROL 0x18C0
3477#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA
3478#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB
3479#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD
3480#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9
3481#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8
3482#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC
3483#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE
3484#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0
3485#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3
3486#define mmDP_AUX3_AUX_LS_DATA 0x18C7
3487#define mmDP_AUX3_AUX_LS_STATUS 0x18C5
3488#define mmDP_AUX3_AUX_SW_CONTROL 0x18C1
3489#define mmDP_AUX3_AUX_SW_DATA 0x18C6
3490#define mmDP_AUX3_AUX_SW_STATUS 0x18C4
3491#define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6
3492#define mmDP_AUX4_AUX_CONTROL 0x18D4
3493#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE
3494#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF
3495#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1
3496#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD
3497#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC
3498#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0
3499#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2
3500#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4
3501#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7
3502#define mmDP_AUX4_AUX_LS_DATA 0x18DB
3503#define mmDP_AUX4_AUX_LS_STATUS 0x18D9
3504#define mmDP_AUX4_AUX_SW_CONTROL 0x18D5
3505#define mmDP_AUX4_AUX_SW_DATA 0x18DA
3506#define mmDP_AUX4_AUX_SW_STATUS 0x18D8
3507#define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA
3508#define mmDP_AUX5_AUX_CONTROL 0x18E8
3509#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2
3510#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3
3511#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5
3512#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1
3513#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0
3514#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4
3515#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6
3516#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8
3517#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB
3518#define mmDP_AUX5_AUX_LS_DATA 0x18EF
3519#define mmDP_AUX5_AUX_LS_STATUS 0x18ED
3520#define mmDP_AUX5_AUX_SW_CONTROL 0x18E9
3521#define mmDP_AUX5_AUX_SW_DATA 0x18EE
3522#define mmDP_AUX5_AUX_SW_STATUS 0x18EC
3523#define mmDP_CONFIG 0x1CC2
3524#define mmDP_DPHY_8B10B_CNTL 0x1CD3
3525#define mmDP_DPHY_CNTL 0x1CD0
3526#define mmDP_DPHY_CRC_CNTL 0x1CD7
3527#define mmDP_DPHY_CRC_EN 0x1CD6
3528#define mmDP_DPHY_CRC_MST_CNTL 0x1CC6
3529#define mmDP_DPHY_CRC_MST_STATUS 0x1CC7
3530#define mmDP_DPHY_CRC_RESULT 0x1CD8
3531#define mmDP_DPHY_FAST_TRAINING 0x1CCE
3532#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9
3533#define mmDP_DPHY_PRBS_CNTL 0x1CD4
3534#define mmDP_DPHY_SYM0 0x1CD2
3535#define mmDP_DPHY_SYM1 0x1CE0
3536#define mmDP_DPHY_SYM2 0x1CDF
3537#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1
3538#define mmDP_DTO0_MODULO 0x0142
3539#define mmDP_DTO0_PHASE 0x0141
3540#define mmDP_DTO1_MODULO 0x0146
3541#define mmDP_DTO1_PHASE 0x0145
3542#define mmDP_DTO2_MODULO 0x014A
3543#define mmDP_DTO2_PHASE 0x0149
3544#define mmDP_DTO3_MODULO 0x014E
3545#define mmDP_DTO3_PHASE 0x014D
3546#define mmDP_DTO4_MODULO 0x0152
3547#define mmDP_DTO4_PHASE 0x0151
3548#define mmDP_DTO5_MODULO 0x0156
3549#define mmDP_DTO5_PHASE 0x0155
3550#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30
3551#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31
3552#define mmDPG_PIPE_DPM_CONTROL 0x1B34
3553#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36
3554#define mmDPG_PIPE_STUTTER_CONTROL 0x1B35
3555#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37
3556#define mmDPG_PIPE_URGENCY_CONTROL 0x1B33
3557#define mmDPG_TEST_DEBUG_DATA 0x1B39
3558#define mmDPG_TEST_DEBUG_INDEX 0x1B38
3559#define mmDP_HBR2_EYE_PATTERN 0x1CC8
3560#define mmDP_LINK_CNTL 0x1CC0
3561#define mmDP_LINK_FRAMING_CNTL 0x1CCC
3562#define mmDP_MSA_COLORIMETRY 0x1CDA
3563#define mmDP_MSA_MISC 0x1CC5
3564#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA
3565#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB
3566#define mmDP_MSE_LINK_TIMING 0x1CE8
3567#define mmDP_MSE_MISC_CNTL 0x1CDB
3568#define mmDP_MSE_RATE_CNTL 0x1CE1
3569#define mmDP_MSE_RATE_UPDATE 0x1CE3
3570#define mmDP_MSE_SAT0 0x1CE4
3571#define mmDP_MSE_SAT1 0x1CE5
3572#define mmDP_MSE_SAT2 0x1CE6
3573#define mmDP_MSE_SAT_UPDATE 0x1CE7
3574#define mmDP_PIXEL_FORMAT 0x1CC1
3575#define mmDP_SEC_AUD_M 0x1CA7
3576#define mmDP_SEC_AUD_M_READBACK 0x1CA8
3577#define mmDP_SEC_AUD_N 0x1CA5
3578#define mmDP_SEC_AUD_N_READBACK 0x1CA6
3579#define mmDP_SEC_CNTL 0x1CA0
3580#define mmDP_SEC_CNTL1 0x1CAB
3581#define mmDP_SEC_FRAMING1 0x1CA1
3582#define mmDP_SEC_FRAMING2 0x1CA2
3583#define mmDP_SEC_FRAMING3 0x1CA3
3584#define mmDP_SEC_FRAMING4 0x1CA4
3585#define mmDP_SEC_PACKET_CNTL 0x1CAA
3586#define mmDP_SEC_TIMESTAMP 0x1CA9
3587#define mmDP_STEER_FIFO 0x1CC4
3588#define mmDP_TEST_DEBUG_DATA 0x1CFD
3589#define mmDP_TEST_DEBUG_INDEX 0x1CFC
3590#define mmDP_VID_INTERRUPT_CNTL 0x1CCF
3591#define mmDP_VID_M 0x1CCB
3592#define mmDP_VID_MSA_VBID 0x1CCD
3593#define mmDP_VID_N 0x1CCA
3594#define mmDP_VID_STREAM_CNTL 0x1CC3
3595#define mmDP_VID_TIMING 0x1CC9
3596#define mmDVOACLKC_CNTL 0x016A
3597#define mmDVOACLKC_MVP_CNTL 0x0169
3598#define mmDVOACLKD_CNTL 0x0168
3599#define mmDVO_CLK_ENABLE 0x0129
3600#define mmDVO_CONTROL 0x185B
3601#define mmDVO_CRC2_SIG_MASK 0x185D
3602#define mmDVO_CRC2_SIG_RESULT 0x185E
3603#define mmDVO_CRC_EN 0x185C
3604#define mmDVO_ENABLE 0x1858
3605#define mmDVO_FIFO_ERROR_STATUS 0x185F
3606#define mmDVO_OUTPUT 0x185A
3607#define mmDVO_SKEW_ADJUST 0x197D
3608#define mmDVO_SOURCE_SELECT 0x1859
3609#define mmDVO_STRENGTH_CONTROL 0x197B
3610#define mmDVO_VREF_CONTROL 0x197C
3611#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E
3612#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F
3613#define mmFBC_CLIENT_REGION_MASK 0x16EB
3614#define mmFBC_CNTL 0x16D0
3615#define mmFBC_COMP_CNTL 0x16D4
3616#define mmFBC_COMP_MODE 0x16D5
3617#define mmFBC_CSM_REGION_OFFSET_01 0x16E9
3618#define mmFBC_CSM_REGION_OFFSET_23 0x16EA
3619#define mmFBC_DEBUG0 0x16D6
3620#define mmFBC_DEBUG1 0x16D7
3621#define mmFBC_DEBUG2 0x16D8
3622#define mmFBC_DEBUG_COMP 0x16EC
3623#define mmFBC_DEBUG_CSR 0x16ED
3624#define mmFBC_DEBUG_CSR_RDATA 0x16EE
3625#define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6
3626#define mmFBC_DEBUG_CSR_WDATA 0x16EF
3627#define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7
3628#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2
3629#define mmFBC_IDLE_MASK 0x16D1
3630#define mmFBC_IND_LUT0 0x16D9
3631#define mmFBC_IND_LUT10 0x16E3
3632#define mmFBC_IND_LUT1 0x16DA
3633#define mmFBC_IND_LUT11 0x16E4
3634#define mmFBC_IND_LUT12 0x16E5
3635#define mmFBC_IND_LUT13 0x16E6
3636#define mmFBC_IND_LUT14 0x16E7
3637#define mmFBC_IND_LUT15 0x16E8
3638#define mmFBC_IND_LUT2 0x16DB
3639#define mmFBC_IND_LUT3 0x16DC
3640#define mmFBC_IND_LUT4 0x16DD
3641#define mmFBC_IND_LUT5 0x16DE
3642#define mmFBC_IND_LUT6 0x16DF
3643#define mmFBC_IND_LUT7 0x16E0
3644#define mmFBC_IND_LUT8 0x16E1
3645#define mmFBC_IND_LUT9 0x16E2
3646#define mmFBC_MISC 0x16F0
3647#define mmFBC_START_STOP_DELAY 0x16D3
3648#define mmFBC_STATUS 0x16F1
3649#define mmFBC_TEST_DEBUG_DATA 0x16F5
3650#define mmFBC_TEST_DEBUG_INDEX 0x16F4
3651#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2
3652#define mmFMT0_FMT_CLAMP_CNTL 0x1BF9
3653#define mmFMT0_FMT_CONTROL 0x1BEE
3654#define mmFMT0_FMT_CRC_CNTL 0x1BFA
3655#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE
3656#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC
3657#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD
3658#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB
3659#define mmFMT0_FMT_DEBUG_CNTL 0x1BFF
3660#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5
3661#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4
3662#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3
3663#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED
3664#define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0
3665#define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1
3666#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF
3667#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6
3668#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7
3669#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8
3670#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC
3671#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB
3672#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2
3673#define mmFMT1_FMT_CLAMP_CNTL 0x1EF9
3674#define mmFMT1_FMT_CONTROL 0x1EEE
3675#define mmFMT1_FMT_CRC_CNTL 0x1EFA
3676#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE
3677#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC
3678#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD
3679#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB
3680#define mmFMT1_FMT_DEBUG_CNTL 0x1EFF
3681#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5
3682#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4
3683#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3
3684#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED
3685#define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0
3686#define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1
3687#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF
3688#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6
3689#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7
3690#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8
3691#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC
3692#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB
3693#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2
3694#define mmFMT2_FMT_CLAMP_CNTL 0x41F9
3695#define mmFMT2_FMT_CONTROL 0x41EE
3696#define mmFMT2_FMT_CRC_CNTL 0x41FA
3697#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE
3698#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC
3699#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD
3700#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB
3701#define mmFMT2_FMT_DEBUG_CNTL 0x41FF
3702#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5
3703#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4
3704#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3
3705#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED
3706#define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0
3707#define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1
3708#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF
3709#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6
3710#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7
3711#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8
3712#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC
3713#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB
3714#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2
3715#define mmFMT3_FMT_CLAMP_CNTL 0x44F9
3716#define mmFMT3_FMT_CONTROL 0x44EE
3717#define mmFMT3_FMT_CRC_CNTL 0x44FA
3718#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE
3719#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC
3720#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD
3721#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB
3722#define mmFMT3_FMT_DEBUG_CNTL 0x44FF
3723#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5
3724#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4
3725#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3
3726#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED
3727#define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0
3728#define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1
3729#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF
3730#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6
3731#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7
3732#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8
3733#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC
3734#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB
3735#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2
3736#define mmFMT4_FMT_CLAMP_CNTL 0x47F9
3737#define mmFMT4_FMT_CONTROL 0x47EE
3738#define mmFMT4_FMT_CRC_CNTL 0x47FA
3739#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE
3740#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC
3741#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD
3742#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB
3743#define mmFMT4_FMT_DEBUG_CNTL 0x47FF
3744#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5
3745#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4
3746#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3
3747#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED
3748#define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0
3749#define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1
3750#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF
3751#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6
3752#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7
3753#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8
3754#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC
3755#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB
3756#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2
3757#define mmFMT5_FMT_CLAMP_CNTL 0x4AF9
3758#define mmFMT5_FMT_CONTROL 0x4AEE
3759#define mmFMT5_FMT_CRC_CNTL 0x4AFA
3760#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE
3761#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC
3762#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD
3763#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB
3764#define mmFMT5_FMT_DEBUG_CNTL 0x4AFF
3765#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5
3766#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4
3767#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3
3768#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED
3769#define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0
3770#define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1
3771#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF
3772#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6
3773#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7
3774#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8
3775#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC
3776#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB
3777#define mmFMT_BIT_DEPTH_CONTROL 0x1BF2
3778#define mmFMT_CLAMP_CNTL 0x1BF9
3779#define mmFMT_CONTROL 0x1BEE
3780#define mmFMT_CRC_CNTL 0x1BFA
3781#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE
3782#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC
3783#define mmFMT_CRC_SIG_RED_GREEN 0x1BFD
3784#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB
3785#define mmFMT_DEBUG_CNTL 0x1BFF
3786#define mmFMT_DITHER_RAND_B_SEED 0x1BF5
3787#define mmFMT_DITHER_RAND_G_SEED 0x1BF4
3788#define mmFMT_DITHER_RAND_R_SEED 0x1BF3
3789#define mmFMT_DYNAMIC_EXP_CNTL 0x1BED
3790#define mmFMT_FORCE_DATA_0_1 0x1BF0
3791#define mmFMT_FORCE_DATA_2_3 0x1BF1
3792#define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF
3793#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6
3794#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7
3795#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8
3796#define mmFMT_TEST_DEBUG_DATA 0x1BEC
3797#define mmFMT_TEST_DEBUG_INDEX 0x1BEB
3798#define mmGAMUT_REMAP_C11_C12 0x1A5A
3799#define mmGAMUT_REMAP_C13_C14 0x1A5B
3800#define mmGAMUT_REMAP_C21_C22 0x1A5C
3801#define mmGAMUT_REMAP_C23_C24 0x1A5D
3802#define mmGAMUT_REMAP_C31_C32 0x1A5E
3803#define mmGAMUT_REMAP_C33_C34 0x1A5F
3804#define mmGAMUT_REMAP_CONTROL 0x1A59
3805#define mmGENENB 0x00F0
3806#define mmGENERIC_I2C_CONTROL 0x1834
3807#define mmGENERIC_I2C_DATA 0x183A
3808#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835
3809#define mmGENERIC_I2C_PIN_DEBUG 0x183C
3810#define mmGENERIC_I2C_PIN_SELECTION 0x183B
3811#define mmGENERIC_I2C_SETUP 0x1838
3812#define mmGENERIC_I2C_SPEED 0x1837
3813#define mmGENERIC_I2C_STATUS 0x1836
3814#define mmGENERIC_I2C_TRANSACTION 0x1839
3815#define mmGENFC_RD 0x00F2
3816#define mmGENFC_WT 0x00EE
3817#define mmGENMO_RD 0x00F3
3818#define mmGENMO_WT 0x00F0
3819#define mmGENS0 0x00F0
3820#define mmGENS1 0x00EE
3821#define mmGRPH8_DATA 0x00F3
3822#define mmGRPH8_IDX 0x00F3
3823#define mmGRPH_COMPRESS_PITCH 0x1A1A
3824#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19
3825#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B
3826#define mmGRPH_CONTROL 0x1A01
3827#define mmGRPH_DFQ_CONTROL 0x1A14
3828#define mmGRPH_DFQ_STATUS 0x1A15
3829#define mmGRPH_ENABLE 0x1A00
3830#define mmGRPH_FLIP_CONTROL 0x1A12
3831#define mmGRPH_INTERRUPT_CONTROL 0x1A17
3832#define mmGRPH_INTERRUPT_STATUS 0x1A16
3833#define mmGRPH_LUT_10BIT_BYPASS 0x1A02
3834#define mmGRPH_PITCH 0x1A06
3835#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04
3836#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07
3837#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05
3838#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08
3839#define mmGRPH_STEREOSYNC_FLIP 0x1A97
3840#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18
3841#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13
3842#define mmGRPH_SURFACE_OFFSET_X 0x1A09
3843#define mmGRPH_SURFACE_OFFSET_Y 0x1A0A
3844#define mmGRPH_SWAP_CNTL 0x1A03
3845#define mmGRPH_UPDATE 0x1A11
3846#define mmGRPH_X_END 0x1A0D
3847#define mmGRPH_X_START 0x1A0B
3848#define mmGRPH_Y_END 0x1A0E
3849#define mmGRPH_Y_START 0x1A0C
3850#define mmHDMI_ACR_32_0 0x1C37
3851#define mmHDMI_ACR_32_1 0x1C38
3852#define mmHDMI_ACR_44_0 0x1C39
3853#define mmHDMI_ACR_44_1 0x1C3A
3854#define mmHDMI_ACR_48_0 0x1C3B
3855#define mmHDMI_ACR_48_1 0x1C3C
3856#define mmHDMI_ACR_PACKET_CONTROL 0x1C0F
3857#define mmHDMI_ACR_STATUS_0 0x1C3D
3858#define mmHDMI_ACR_STATUS_1 0x1C3E
3859#define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E
3860#define mmHDMI_CONTROL 0x1C0C
3861#define mmHDMI_GC 0x1C16
3862#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13
3863#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30
3864#define mmHDMI_INFOFRAME_CONTROL0 0x1C11
3865#define mmHDMI_INFOFRAME_CONTROL1 0x1C12
3866#define mmHDMI_STATUS 0x1C0D
3867#define mmHDMI_VBI_PACKET_CONTROL 0x1C10
3868#define mmINPUT_CSC_C11_C12 0x1A36
3869#define mmINPUT_CSC_C13_C14 0x1A37
3870#define mmINPUT_CSC_C21_C22 0x1A38
3871#define mmINPUT_CSC_C23_C24 0x1A39
3872#define mmINPUT_CSC_C31_C32 0x1A3A
3873#define mmINPUT_CSC_C33_C34 0x1A3B
3874#define mmINPUT_CSC_CONTROL 0x1A35
3875#define mmINPUT_GAMMA_CONTROL 0x1A10
3876#define mmKEY_CONTROL 0x1A53
3877#define mmKEY_RANGE_ALPHA 0x1A54
3878#define mmKEY_RANGE_BLUE 0x1A57
3879#define mmKEY_RANGE_GREEN 0x1A56
3880#define mmKEY_RANGE_RED 0x1A55
3881#define mmLB0_DC_MVP_LB_CONTROL 0x1ADB
3882#define mmLB0_LB_DEBUG 0x1AFC
3883#define mmLB0_LB_DEBUG2 0x1AC9
3884#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
3885#define mmLB0_LB_SYNC_RESET_SEL 0x1ACA
3886#define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF
3887#define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE
3888#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9
3889#define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8
3890#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA
3891#define mmLB1_DC_MVP_LB_CONTROL 0x1DDB
3892#define mmLB1_LB_DEBUG 0x1DFC
3893#define mmLB1_LB_DEBUG2 0x1DC9
3894#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8
3895#define mmLB1_LB_SYNC_RESET_SEL 0x1DCA
3896#define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF
3897#define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE
3898#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9
3899#define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8
3900#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA
3901#define mmLB2_DC_MVP_LB_CONTROL 0x40DB
3902#define mmLB2_LB_DEBUG 0x40FC
3903#define mmLB2_LB_DEBUG2 0x40C9
3904#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8
3905#define mmLB2_LB_SYNC_RESET_SEL 0x40CA
3906#define mmLB2_LB_TEST_DEBUG_DATA 0x40FF
3907#define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE
3908#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9
3909#define mmLB2_MVP_AFR_FLIP_MODE 0x40D8
3910#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA
3911#define mmLB3_DC_MVP_LB_CONTROL 0x43DB
3912#define mmLB3_LB_DEBUG 0x43FC
3913#define mmLB3_LB_DEBUG2 0x43C9
3914#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8
3915#define mmLB3_LB_SYNC_RESET_SEL 0x43CA
3916#define mmLB3_LB_TEST_DEBUG_DATA 0x43FF
3917#define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE
3918#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9
3919#define mmLB3_MVP_AFR_FLIP_MODE 0x43D8
3920#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA
3921#define mmLB4_DC_MVP_LB_CONTROL 0x46DB
3922#define mmLB4_LB_DEBUG 0x46FC
3923#define mmLB4_LB_DEBUG2 0x46C9
3924#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8
3925#define mmLB4_LB_SYNC_RESET_SEL 0x46CA
3926#define mmLB4_LB_TEST_DEBUG_DATA 0x46FF
3927#define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE
3928#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9
3929#define mmLB4_MVP_AFR_FLIP_MODE 0x46D8
3930#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA
3931#define mmLB5_DC_MVP_LB_CONTROL 0x49DB
3932#define mmLB5_LB_DEBUG 0x49FC
3933#define mmLB5_LB_DEBUG2 0x49C9
3934#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8
3935#define mmLB5_LB_SYNC_RESET_SEL 0x49CA
3936#define mmLB5_LB_TEST_DEBUG_DATA 0x49FF
3937#define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE
3938#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9
3939#define mmLB5_MVP_AFR_FLIP_MODE 0x49D8
3940#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA
3941#define mmLB_DEBUG 0x1AFC
3942#define mmLB_DEBUG2 0x1AC9
3943#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
3944#define mmLB_SYNC_RESET_SEL 0x1ACA
3945#define mmLB_TEST_DEBUG_DATA 0x1AFF
3946#define mmLB_TEST_DEBUG_INDEX 0x1AFE
3947#define mmLIGHT_SLEEP_CNTL 0x0132
3948#define mmLOW_POWER_TILING_CONTROL 0x0325
3949#define mmLVDS_DATA_CNTL 0x1C8C
3950#define mmLVTMA_PWRSEQ_CNTL 0x1919
3951#define mmLVTMA_PWRSEQ_DELAY1 0x191C
3952#define mmLVTMA_PWRSEQ_DELAY2 0x191D
3953#define mmLVTMA_PWRSEQ_REF_DIV 0x191B
3954#define mmLVTMA_PWRSEQ_STATE 0x191A
3955#define mmMASTER_COMM_CMD_REG 0x161F
3956#define mmMASTER_COMM_CNTL_REG 0x1620
3957#define mmMASTER_COMM_DATA_REG1 0x161C
3958#define mmMASTER_COMM_DATA_REG2 0x161D
3959#define mmMASTER_COMM_DATA_REG3 0x161E
3960#define mmMASTER_UPDATE_LOCK 0x1BBD
3961#define mmMASTER_UPDATE_MODE 0x1BBE
3962#define mmMC_DC_INTERFACE_NACK_STATUS 0x031C
3963#define mmMCIF_CONTROL 0x0314
3964#define mmMCIF_MEM_CONTROL 0x0319
3965#define mmMCIF_TEST_DEBUG_DATA 0x0317
3966#define mmMCIF_TEST_DEBUG_INDEX 0x0316
3967#define mmMCIF_VMID 0x0318
3968#define mmMCIF_WRITE_COMBINE_CONTROL 0x0315
3969#define mmMICROSECOND_TIME_BASE_DIV 0x013B
3970#define mmMILLISECOND_TIME_BASE_DIV 0x0130
3971#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9
3972#define mmMVP_AFR_FLIP_MODE 0x1AD8
3973#define mmMVP_BLACK_KEYER 0x1686
3974#define mmMVP_CONTROL1 0x1680
3975#define mmMVP_CONTROL2 0x1681
3976#define mmMVP_CONTROL3 0x168A
3977#define mmMVP_CRC_CNTL 0x1687
3978#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688
3979#define mmMVP_CRC_RESULT_RED 0x1689
3980#define mmMVP_DEBUG 0x168F
3981#define mmMVP_FIFO_CONTROL 0x1682
3982#define mmMVP_FIFO_STATUS 0x1683
3983#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA
3984#define mmMVP_INBAND_CNTL_CAP 0x1685
3985#define mmMVP_RECEIVE_CNT_CNTL1 0x168B
3986#define mmMVP_RECEIVE_CNT_CNTL2 0x168C
3987#define mmMVP_SLAVE_STATUS 0x1684
3988#define mmMVP_TEST_DEBUG_DATA 0x168E
3989#define mmMVP_TEST_DEBUG_INDEX 0x168D
3990#define mmOUTPUT_CSC_C11_C12 0x1A3D
3991#define mmOUTPUT_CSC_C13_C14 0x1A3E
3992#define mmOUTPUT_CSC_C21_C22 0x1A3F
3993#define mmOUTPUT_CSC_C23_C24 0x1A40
3994#define mmOUTPUT_CSC_C31_C32 0x1A41
3995#define mmOUTPUT_CSC_C33_C34 0x1A42
3996#define mmOUTPUT_CSC_CONTROL 0x1A3C
3997#define mmOUT_ROUND_CONTROL 0x1A51
3998#define mmOVL_CONTROL1 0x1A1D
3999#define mmOVL_CONTROL2 0x1A1E
4000#define mmOVL_DFQ_CONTROL 0x1A29
4001#define mmOVL_DFQ_STATUS 0x1A2A
4002#define mmOVL_ENABLE 0x1A1C
4003#define mmOVL_END 0x1A26
4004#define mmOVL_PITCH 0x1A21
4005#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C
4006#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92
4007#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94
4008#define mmOVL_START 0x1A25
4009#define mmOVL_STEREOSYNC_FLIP 0x1A93
4010#define mmOVL_SURFACE_ADDRESS 0x1A20
4011#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22
4012#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B
4013#define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28
4014#define mmOVL_SURFACE_OFFSET_X 0x1A23
4015#define mmOVL_SURFACE_OFFSET_Y 0x1A24
4016#define mmOVL_SWAP_CNTL 0x1A1F
4017#define mmOVL_UPDATE 0x1A27
4018#define mmPHY_AUX_CNTL 0x197F
4019#define mmPIPE0_ARBITRATION_CONTROL3 0x02FA
4020#define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328
4021#define mmPIPE0_MAX_REQUESTS 0x0302
4022#define mmPIPE0_PG_CONFIG 0x1760
4023#define mmPIPE0_PG_ENABLE 0x1761
4024#define mmPIPE0_PG_STATUS 0x1762
4025#define mmPIPE1_ARBITRATION_CONTROL3 0x02FB
4026#define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330
4027#define mmPIPE1_MAX_REQUESTS 0x0303
4028#define mmPIPE1_PG_CONFIG 0x1764
4029#define mmPIPE1_PG_ENABLE 0x1765
4030#define mmPIPE1_PG_STATUS 0x1766
4031#define mmPIPE2_ARBITRATION_CONTROL3 0x02FC
4032#define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338
4033#define mmPIPE2_MAX_REQUESTS 0x0304
4034#define mmPIPE2_PG_CONFIG 0x1768
4035#define mmPIPE2_PG_ENABLE 0x1769
4036#define mmPIPE2_PG_STATUS 0x176A
4037#define mmPIPE3_ARBITRATION_CONTROL3 0x02FD
4038#define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340
4039#define mmPIPE3_MAX_REQUESTS 0x0305
4040#define mmPIPE3_PG_CONFIG 0x176C
4041#define mmPIPE3_PG_ENABLE 0x176D
4042#define mmPIPE3_PG_STATUS 0x176E
4043#define mmPIPE4_ARBITRATION_CONTROL3 0x02FE
4044#define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348
4045#define mmPIPE4_MAX_REQUESTS 0x0306
4046#define mmPIPE4_PG_CONFIG 0x1770
4047#define mmPIPE4_PG_ENABLE 0x1771
4048#define mmPIPE4_PG_STATUS 0x1772
4049#define mmPIPE5_ARBITRATION_CONTROL3 0x02FF
4050#define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350
4051#define mmPIPE5_MAX_REQUESTS 0x0307
4052#define mmPIPE5_PG_CONFIG 0x1774
4053#define mmPIPE5_PG_ENABLE 0x1775
4054#define mmPIPE5_PG_STATUS 0x1776
4055#define mmPIXCLK0_RESYNC_CNTL 0x013A
4056#define mmPIXCLK1_RESYNC_CNTL 0x0138
4057#define mmPIXCLK2_RESYNC_CNTL 0x0139
4058#define mmPLL_ANALOG 0x1708
4059#define mmPLL_CNTL 0x1707
4060#define mmPLL_DEBUG_CNTL 0x170B
4061#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F
4062#define mmPLL_DISPCLK_DTO_CNTL 0x170E
4063#define mmPLL_DS_CNTL 0x1705
4064#define mmPLL_FB_DIV 0x1701
4065#define mmPLL_IDCLK_CNTL 0x1706
4066#define mmPLL_POST_DIV 0x1702
4067#define mmPLL_REF_DIV 0x1700
4068#define mmPLL_SS_AMOUNT_DSFRAC 0x1703
4069#define mmPLL_SS_CNTL 0x1704
4070#define mmPLL_UNLOCK_DETECT_CNTL 0x170A
4071#define mmPLL_UPDATE_CNTL 0x170D
4072#define mmPLL_UPDATE_LOCK 0x170C
4073#define mmPLL_VREG_CNTL 0x1709
4074#define mmPRESCALE_GRPH_CONTROL 0x1A2D
4075#define mmPRESCALE_OVL_CONTROL 0x1A31
4076#define mmPRESCALE_VALUES_GRPH_B 0x1A30
4077#define mmPRESCALE_VALUES_GRPH_G 0x1A2F
4078#define mmPRESCALE_VALUES_GRPH_R 0x1A2E
4079#define mmPRESCALE_VALUES_OVL_CB 0x1A32
4080#define mmPRESCALE_VALUES_OVL_CR 0x1A34
4081#define mmPRESCALE_VALUES_OVL_Y 0x1A33
4082#define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6
4083#define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7
4084#define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8
4085#define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD
4086#define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE
4087#define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF
4088#define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9
4089#define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA
4090#define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB
4091#define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC
4092#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5
4093#define mmREGAMMA_CNTLA_START_CNTL 0x1AA4
4094#define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2
4095#define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3
4096#define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4
4097#define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9
4098#define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA
4099#define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB
4100#define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5
4101#define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6
4102#define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7
4103#define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8
4104#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1
4105#define mmREGAMMA_CNTLB_START_CNTL 0x1AB0
4106#define mmREGAMMA_CONTROL 0x1AA0
4107#define mmREGAMMA_LUT_DATA 0x1AA2
4108#define mmREGAMMA_LUT_INDEX 0x1AA1
4109#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3
4110#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E
4111#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F
4112#define mmSCL0_SCL_ALU_CONTROL 0x1B54
4113#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47
4114#define mmSCL0_SCL_BYPASS_CONTROL 0x1B45
4115#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55
4116#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40
4117#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41
4118#define mmSCL0_SCL_CONTROL 0x1B44
4119#define mmSCL0_SCL_DEBUG 0x1B6A
4120#define mmSCL0_SCL_DEBUG2 0x1B69
4121#define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53
4122#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A
4123#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B
4124#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46
4125#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60
4126#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61
4127#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62
4128#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63
4129#define mmSCL0_SCL_TAP_CONTROL 0x1B43
4130#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C
4131#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B
4132#define mmSCL0_SCL_UPDATE 0x1B51
4133#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E
4134#define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50
4135#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57
4136#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F
4137#define mmSCL0_VIEWPORT_SIZE 0x1B5D
4138#define mmSCL0_VIEWPORT_START 0x1B5C
4139#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E
4140#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F
4141#define mmSCL1_SCL_ALU_CONTROL 0x1E54
4142#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47
4143#define mmSCL1_SCL_BYPASS_CONTROL 0x1E45
4144#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55
4145#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40
4146#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41
4147#define mmSCL1_SCL_CONTROL 0x1E44
4148#define mmSCL1_SCL_DEBUG 0x1E6A
4149#define mmSCL1_SCL_DEBUG2 0x1E69
4150#define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53
4151#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A
4152#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B
4153#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46
4154#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60
4155#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61
4156#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62
4157#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63
4158#define mmSCL1_SCL_TAP_CONTROL 0x1E43
4159#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C
4160#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B
4161#define mmSCL1_SCL_UPDATE 0x1E51
4162#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E
4163#define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50
4164#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57
4165#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F
4166#define mmSCL1_VIEWPORT_SIZE 0x1E5D
4167#define mmSCL1_VIEWPORT_START 0x1E5C
4168#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E
4169#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F
4170#define mmSCL2_SCL_ALU_CONTROL 0x4154
4171#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147
4172#define mmSCL2_SCL_BYPASS_CONTROL 0x4145
4173#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
4174#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140
4175#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141
4176#define mmSCL2_SCL_CONTROL 0x4144
4177#define mmSCL2_SCL_DEBUG 0x416A
4178#define mmSCL2_SCL_DEBUG2 0x4169
4179#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153
4180#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A
4181#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B
4182#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146
4183#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160
4184#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161
4185#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162
4186#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163
4187#define mmSCL2_SCL_TAP_CONTROL 0x4143
4188#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C
4189#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B
4190#define mmSCL2_SCL_UPDATE 0x4151
4191#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E
4192#define mmSCL2_SCL_VERT_FILTER_INIT 0x4150
4193#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157
4194#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F
4195#define mmSCL2_VIEWPORT_SIZE 0x415D
4196#define mmSCL2_VIEWPORT_START 0x415C
4197#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E
4198#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F
4199#define mmSCL3_SCL_ALU_CONTROL 0x4454
4200#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447
4201#define mmSCL3_SCL_BYPASS_CONTROL 0x4445
4202#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455
4203#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440
4204#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441
4205#define mmSCL3_SCL_CONTROL 0x4444
4206#define mmSCL3_SCL_DEBUG 0x446A
4207#define mmSCL3_SCL_DEBUG2 0x4469
4208#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453
4209#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A
4210#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B
4211#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446
4212#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460
4213#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461
4214#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462
4215#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463
4216#define mmSCL3_SCL_TAP_CONTROL 0x4443
4217#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C
4218#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B
4219#define mmSCL3_SCL_UPDATE 0x4451
4220#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E
4221#define mmSCL3_SCL_VERT_FILTER_INIT 0x4450
4222#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457
4223#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F
4224#define mmSCL3_VIEWPORT_SIZE 0x445D
4225#define mmSCL3_VIEWPORT_START 0x445C
4226#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E
4227#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F
4228#define mmSCL4_SCL_ALU_CONTROL 0x4754
4229#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747
4230#define mmSCL4_SCL_BYPASS_CONTROL 0x4745
4231#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755
4232#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740
4233#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741
4234#define mmSCL4_SCL_CONTROL 0x4744
4235#define mmSCL4_SCL_DEBUG 0x476A
4236#define mmSCL4_SCL_DEBUG2 0x4769
4237#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753
4238#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A
4239#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B
4240#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746
4241#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760
4242#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761
4243#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762
4244#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763
4245#define mmSCL4_SCL_TAP_CONTROL 0x4743
4246#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C
4247#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B
4248#define mmSCL4_SCL_UPDATE 0x4751
4249#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E
4250#define mmSCL4_SCL_VERT_FILTER_INIT 0x4750
4251#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757
4252#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F
4253#define mmSCL4_VIEWPORT_SIZE 0x475D
4254#define mmSCL4_VIEWPORT_START 0x475C
4255#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E
4256#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F
4257#define mmSCL5_SCL_ALU_CONTROL 0x4A54
4258#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47
4259#define mmSCL5_SCL_BYPASS_CONTROL 0x4A45
4260#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55
4261#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40
4262#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41
4263#define mmSCL5_SCL_CONTROL 0x4A44
4264#define mmSCL5_SCL_DEBUG 0x4A6A
4265#define mmSCL5_SCL_DEBUG2 0x4A69
4266#define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53
4267#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A
4268#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B
4269#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46
4270#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60
4271#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61
4272#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62
4273#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63
4274#define mmSCL5_SCL_TAP_CONTROL 0x4A43
4275#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C
4276#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B
4277#define mmSCL5_SCL_UPDATE 0x4A51
4278#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E
4279#define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50
4280#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57
4281#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F
4282#define mmSCL5_VIEWPORT_SIZE 0x4A5D
4283#define mmSCL5_VIEWPORT_START 0x4A5C
4284#define mmSCL_ALU_CONTROL 0x1B54
4285#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47
4286#define mmSCL_BYPASS_CONTROL 0x1B45
4287#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55
4288#define mmSCL_COEF_RAM_SELECT 0x1B40
4289#define mmSCL_COEF_RAM_TAP_DATA 0x1B41
4290#define mmSCL_CONTROL 0x1B44
4291#define mmSCL_DEBUG 0x1B6A
4292#define mmSCL_DEBUG2 0x1B69
4293#define mmSCL_F_SHARP_CONTROL 0x1B53
4294#define mmSCL_HORZ_FILTER_CONTROL 0x1B4A
4295#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B
4296#define mmSCLK_CGTT_BLK_CTRL_REG 0x0136
4297#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46
4298#define mmSCL_MODE_CHANGE_DET1 0x1B60
4299#define mmSCL_MODE_CHANGE_DET2 0x1B61
4300#define mmSCL_MODE_CHANGE_DET3 0x1B62
4301#define mmSCL_MODE_CHANGE_MASK 0x1B63
4302#define mmSCL_TAP_CONTROL 0x1B43
4303#define mmSCL_TEST_DEBUG_DATA 0x1B6C
4304#define mmSCL_TEST_DEBUG_INDEX 0x1B6B
4305#define mmSCL_UPDATE 0x1B51
4306#define mmSCL_VERT_FILTER_CONTROL 0x1B4E
4307#define mmSCL_VERT_FILTER_INIT 0x1B50
4308#define mmSCL_VERT_FILTER_INIT_BOT 0x1B57
4309#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F
4310#define mmSEQ8_DATA 0x00F1
4311#define mmSEQ8_IDX 0x00F1
4312#define mmSLAVE_COMM_CMD_REG 0x1624
4313#define mmSLAVE_COMM_CNTL_REG 0x1625
4314#define mmSLAVE_COMM_DATA_REG1 0x1621
4315#define mmSLAVE_COMM_DATA_REG2 0x1622
4316#define mmSLAVE_COMM_DATA_REG3 0x1623
4317#define mmSYMCLKA_CLOCK_ENABLE 0x0160
4318#define mmSYMCLKB_CLOCK_ENABLE 0x0161
4319#define mmSYMCLKC_CLOCK_ENABLE 0x0162
4320#define mmSYMCLKD_CLOCK_ENABLE 0x0163
4321#define mmSYMCLKE_CLOCK_ENABLE 0x0164
4322#define mmSYMCLKF_CLOCK_ENABLE 0x0165
4323#define mmTMDS_CNTL 0x1C7C
4324#define mmTMDS_CONTROL0_FEEDBACK 0x1C7E
4325#define mmTMDS_CONTROL_CHAR 0x1C7D
4326#define mmTMDS_CTL0_1_GEN_CNTL 0x1C86
4327#define mmTMDS_CTL2_3_GEN_CNTL 0x1C87
4328#define mmTMDS_CTL_BITS 0x1C83
4329#define mmTMDS_DCBALANCER_CONTROL 0x1C84
4330#define mmTMDS_DEBUG 0x1C82
4331#define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F
4332#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80
4333#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81
4334#define mmUNIPHYAB_TPG_CONTROL 0x1931
4335#define mmUNIPHYAB_TPG_SEED 0x1932
4336#define mmUNIPHY_ANG_BIST_CNTL 0x198C
4337#define mmUNIPHYCD_TPG_CONTROL 0x1933
4338#define mmUNIPHYCD_TPG_SEED 0x1934
4339#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E
4340#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A
4341#define mmUNIPHYEF_TPG_CONTROL 0x1935
4342#define mmUNIPHYEF_TPG_SEED 0x1936
4343#define mmUNIPHY_IMPCAL_LINKA 0x1908
4344#define mmUNIPHY_IMPCAL_LINKB 0x1909
4345#define mmUNIPHY_IMPCAL_LINKC 0x190F
4346#define mmUNIPHY_IMPCAL_LINKD 0x1910
4347#define mmUNIPHY_IMPCAL_LINKE 0x1913
4348#define mmUNIPHY_IMPCAL_LINKF 0x1914
4349#define mmUNIPHY_IMPCAL_PERIOD 0x190A
4350#define mmUNIPHY_IMPCAL_PSW_AB 0x190E
4351#define mmUNIPHY_IMPCAL_PSW_CD 0x1912
4352#define mmUNIPHY_IMPCAL_PSW_EF 0x1916
4353#define mmUNIPHY_LINK_CNTL 0x198D
4354#define mmUNIPHY_PLL_CONTROL1 0x1986
4355#define mmUNIPHY_PLL_CONTROL2 0x1987
4356#define mmUNIPHY_PLL_FBDIV 0x1985
4357#define mmUNIPHY_PLL_SS_CNTL 0x1989
4358#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988
4359#define mmUNIPHY_POWER_CONTROL 0x1984
4360#define mmUNIPHY_REG_TEST_OUTPUT 0x198B
4361#define mmUNIPHY_SOFT_RESET 0x0166
4362#define mmUNIPHY_TX_CONTROL1 0x1980
4363#define mmUNIPHY_TX_CONTROL2 0x1981
4364#define mmUNIPHY_TX_CONTROL3 0x1982
4365#define mmUNIPHY_TX_CONTROL4 0x1983
4366#define mmVGA25_PPLL_ANALOG 0x00E4
4367#define mmVGA25_PPLL_FB_DIV 0x00DC
4368#define mmVGA25_PPLL_POST_DIV 0x00E0
4369#define mmVGA25_PPLL_REF_DIV 0x00D8
4370#define mmVGA28_PPLL_ANALOG 0x00E5
4371#define mmVGA28_PPLL_FB_DIV 0x00DD
4372#define mmVGA28_PPLL_POST_DIV 0x00E1
4373#define mmVGA28_PPLL_REF_DIV 0x00D9
4374#define mmVGA41_PPLL_ANALOG 0x00E6
4375#define mmVGA41_PPLL_FB_DIV 0x00DE
4376#define mmVGA41_PPLL_POST_DIV 0x00E2
4377#define mmVGA41_PPLL_REF_DIV 0x00DA
4378#define mmVGA_CACHE_CONTROL 0x00CB
4379#define mmVGA_DEBUG_READBACK_DATA 0x00D7
4380#define mmVGA_DEBUG_READBACK_INDEX 0x00D6
4381#define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6
4382#define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8
4383#define mmVGA_HDP_CONTROL 0x00CA
4384#define mmVGA_HW_DEBUG 0x00CF
4385#define mmVGA_INTERRUPT_CONTROL 0x00D1
4386#define mmVGA_INTERRUPT_STATUS 0x00D3
4387#define mmVGA_MAIN_CONTROL 0x00D4
4388#define mmVGA_MEMORY_BASE_ADDRESS 0x00C4
4389#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9
4390#define mmVGA_MEM_READ_PAGE_ADDR 0x0013
4391#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012
4392#define mmVGA_MODE_CONTROL 0x00C2
4393#define mmVGA_RENDER_CONTROL 0x00C0
4394#define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1
4395#define mmVGA_SOURCE_SELECT 0x00FC
4396#define mmVGA_STATUS 0x00D0
4397#define mmVGA_STATUS_CLEAR 0x00D2
4398#define mmVGA_SURFACE_PITCH_SELECT 0x00C3
4399#define mmVGA_TEST_CONTROL 0x00D5
4400#define mmVGA_TEST_DEBUG_DATA 0x00C7
4401#define mmVGA_TEST_DEBUG_INDEX 0x00C5
4402#define mmVIEWPORT_SIZE 0x1B5D
4403#define mmVIEWPORT_START 0x1B5C
4404#define mmXDMA_CLOCK_GATING_CNTL 0x0409
4405#define mmXDMA_IF_BIF_STATUS 0x0418
4406#define mmXDMA_INTERRUPT 0x0406
4407#define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4
4408#define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5
4409#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9
4410#define mmXDMA_MEM_POWER_CNTL 0x040B
4411#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6
4412#define mmXDMA_MSTR_CNTL 0x03E0
4413#define mmXDMA_MSTR_HEIGHT 0x03E3
4414#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1
4415#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2
4416#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3
4417#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA
4418#define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D
4419#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7
4420#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C
4421#define mmXDMA_MSTR_READ_COMMAND 0x03E1
4422#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6
4423#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7
4424#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4
4425#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5
4426#define mmXDMA_MSTR_STATUS 0x03E8
4427#define mmXDMA_RBBMIF_RDWR_CNTL 0x040A
4428#define mmXDMA_SLV_CNTL 0x03FB
4429#define mmXDMA_SLV_FLIP_PENDING 0x0407
4430#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD
4431#define mmXDMA_SLV_MEM_NACK_STATUS 0x040F
4432#define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E
4433#define mmXDMA_SLV_READ_LATENCY_AVE 0x0405
4434#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404
4435#define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412
4436#define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF
4437#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402
4438#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403
4439#define mmXDMA_SLV_SLS_PITCH 0x03FE
4440#define mmXDMA_SLV_WB_RATE_CNTL 0x0401
4441#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400
4442#define mmXDMA_TEST_DEBUG_DATA 0x041D
4443#define mmXDMA_TEST_DEBUG_INDEX 0x041C
4444
4445/* Registers that spilled out of sid.h */
4446#define mmDATA_FORMAT 0x1AC0
4447#define mmDESKTOP_HEIGHT 0x1AC1
4448#define mmDC_LB_MEMORY_SPLIT 0x1AC3
4449#define mmPRIORITY_A_CNT 0x1AC6
4450#define mmPRIORITY_B_CNT 0x1AC7
4451#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32
4452#define mmINT_MASK 0x1AD0
4453#define mmVLINE_STATUS 0x1AEE
4454#define mmVBLANK_STATUS 0x1AEF
4455
4456
4457#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
new file mode 100644
index 000000000000..9a4d4c299d5b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
@@ -0,0 +1,9836 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef DCE_6_0_SH_MASK_H
24#define DCE_6_0_SH_MASK_H
25
26#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
36#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L
37#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008
38#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L
39#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014
40#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L
41#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c
42#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L
43#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002
44#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L
45#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003
46#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L
47#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006
48#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L
49#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018
50#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L
51#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010
52#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L
53#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014
54#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L
55#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004
56#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL
57#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000
58#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L
59#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010
60#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L
61#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012
62#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL
63#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000
64#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L
65#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004
66#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L
67#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008
68#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L
69#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c
70#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L
71#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010
72#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L
73#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014
74#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L
75#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c
76#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L
77#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004
78#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L
79#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010
80#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L
81#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000
82#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L
83#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008
84#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L
85#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000
86#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L
87#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008
88#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L
89#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008
90#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L
91#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010
92#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L
93#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c
94#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L
95#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000
96#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L
97#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008
98#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL
99#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L
100#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010
101#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000
102#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L
103#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b
104#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L
105#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018
106#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL
107#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000
108#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L
109#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f
110#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L
111#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010
112#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L
113#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b
114#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L
115#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c
116#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L
117#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008
118#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L
119#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000
120#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L
121#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001
122#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L
123#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010
124#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L
125#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018
126#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L
127#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a
128#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L
129#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018
130#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L
131#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017
132#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L
133#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000
134#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L
135#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c
136#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L
137#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e
138#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L
139#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e
140#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L
141#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f
142#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L
143#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b
144#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L
145#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000
146#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L
147#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c
148#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L
149#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a
150#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL
151#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000
152#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L
153#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016
154#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L
155#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c
156#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L
157#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f
158#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L
159#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014
160#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L
161#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f
162#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L
163#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a
164#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L
165#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010
166#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L
167#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018
168#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L
169#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008
170#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L
171#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d
172#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L
173#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c
174#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L
175#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007
176#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L
177#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008
178#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L
179#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010
180#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL
181#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000
182#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L
183#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e
184#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL
185#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000
186#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L
187#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010
188#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL
189#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000
190#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L
191#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018
192#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL
193#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000
194#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L
195#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008
196#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L
197#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010
198#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L
199#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018
200#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL
201#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000
202#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L
203#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008
204#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L
205#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010
206#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L
207#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018
208#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L
209#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010
210#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L
211#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018
212#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL
213#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000
214#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L
215#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008
216#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL
217#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000
218#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L
219#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008
220#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L
221#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010
222#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L
223#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018
224#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL
225#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000
226#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L
227#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008
228#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L
229#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010
230#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L
231#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018
232#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL
233#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000
234#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L
235#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008
236#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L
237#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010
238#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L
239#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018
240#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL
241#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000
242#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L
243#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008
244#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L
245#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010
246#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L
247#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018
248#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL
249#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000
250#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L
251#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008
252#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L
253#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010
254#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L
255#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018
256#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL
257#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000
258#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L
259#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008
260#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L
261#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010
262#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L
263#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018
264#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L
265#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006
266#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L
267#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007
268#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L
269#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a
270#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L
271#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006
272#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L
273#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000
274#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L
275#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007
276#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL
277#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000
278#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L
279#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008
280#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L
281#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010
282#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L
283#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018
284#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL
285#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000
286#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L
287#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008
288#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L
289#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010
290#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L
291#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018
292#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L
293#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010
294#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L
295#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018
296#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL
297#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000
298#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L
299#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008
300#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL
301#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000
302#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L
303#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008
304#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L
305#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010
306#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L
307#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018
308#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL
309#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000
310#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L
311#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008
312#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L
313#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010
314#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L
315#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018
316#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL
317#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000
318#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L
319#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008
320#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L
321#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010
322#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L
323#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018
324#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL
325#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000
326#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L
327#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008
328#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L
329#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010
330#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L
331#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018
332#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL
333#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000
334#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L
335#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008
336#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L
337#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010
338#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L
339#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018
340#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL
341#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000
342#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L
343#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008
344#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L
345#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010
346#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L
347#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018
348#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L
349#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c
350#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL
351#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000
352#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L
353#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008
354#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L
355#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f
356#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL
357#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000
358#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L
359#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018
360#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL
361#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000
362#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL
363#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000
364#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL
365#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000
366#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L
367#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004
368#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L
369#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018
370#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L
371#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e
372#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L
373#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008
374#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L
375#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002
376#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L
377#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003
378#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L
379#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e
380#define ATTR00__ATTR_PAL_MASK 0x0000003fL
381#define ATTR00__ATTR_PAL__SHIFT 0x00000000
382#define ATTR01__ATTR_PAL_MASK 0x0000003fL
383#define ATTR01__ATTR_PAL__SHIFT 0x00000000
384#define ATTR02__ATTR_PAL_MASK 0x0000003fL
385#define ATTR02__ATTR_PAL__SHIFT 0x00000000
386#define ATTR03__ATTR_PAL_MASK 0x0000003fL
387#define ATTR03__ATTR_PAL__SHIFT 0x00000000
388#define ATTR04__ATTR_PAL_MASK 0x0000003fL
389#define ATTR04__ATTR_PAL__SHIFT 0x00000000
390#define ATTR05__ATTR_PAL_MASK 0x0000003fL
391#define ATTR05__ATTR_PAL__SHIFT 0x00000000
392#define ATTR06__ATTR_PAL_MASK 0x0000003fL
393#define ATTR06__ATTR_PAL__SHIFT 0x00000000
394#define ATTR07__ATTR_PAL_MASK 0x0000003fL
395#define ATTR07__ATTR_PAL__SHIFT 0x00000000
396#define ATTR08__ATTR_PAL_MASK 0x0000003fL
397#define ATTR08__ATTR_PAL__SHIFT 0x00000000
398#define ATTR09__ATTR_PAL_MASK 0x0000003fL
399#define ATTR09__ATTR_PAL__SHIFT 0x00000000
400#define ATTR0A__ATTR_PAL_MASK 0x0000003fL
401#define ATTR0A__ATTR_PAL__SHIFT 0x00000000
402#define ATTR0B__ATTR_PAL_MASK 0x0000003fL
403#define ATTR0B__ATTR_PAL__SHIFT 0x00000000
404#define ATTR0C__ATTR_PAL_MASK 0x0000003fL
405#define ATTR0C__ATTR_PAL__SHIFT 0x00000000
406#define ATTR0D__ATTR_PAL_MASK 0x0000003fL
407#define ATTR0D__ATTR_PAL__SHIFT 0x00000000
408#define ATTR0E__ATTR_PAL_MASK 0x0000003fL
409#define ATTR0E__ATTR_PAL__SHIFT 0x00000000
410#define ATTR0F__ATTR_PAL_MASK 0x0000003fL
411#define ATTR0F__ATTR_PAL__SHIFT 0x00000000
412#define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L
413#define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003
414#define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L
415#define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007
416#define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L
417#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000
418#define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L
419#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002
420#define ATTR10__ATTR_MONO_EN_MASK 0x00000002L
421#define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001
422#define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L
423#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005
424#define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L
425#define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006
426#define ATTR11__ATTR_OVSC_MASK 0x000000ffL
427#define ATTR11__ATTR_OVSC__SHIFT 0x00000000
428#define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL
429#define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000
430#define ATTR12__ATTR_VSMUX_MASK 0x00000030L
431#define ATTR12__ATTR_VSMUX__SHIFT 0x00000004
432#define ATTR13__ATTR_PPAN_MASK 0x0000000fL
433#define ATTR13__ATTR_PPAN__SHIFT 0x00000000
434#define ATTR14__ATTR_CSEL1_MASK 0x00000003L
435#define ATTR14__ATTR_CSEL1__SHIFT 0x00000000
436#define ATTR14__ATTR_CSEL2_MASK 0x0000000cL
437#define ATTR14__ATTR_CSEL2__SHIFT 0x00000002
438#define ATTRDR__ATTR_DATA_MASK 0x000000ffL
439#define ATTRDR__ATTR_DATA__SHIFT 0x00000000
440#define ATTRDW__ATTR_DATA_MASK 0x000000ffL
441#define ATTRDW__ATTR_DATA__SHIFT 0x00000000
442#define ATTRX__ATTR_IDX_MASK 0x0000001fL
443#define ATTRX__ATTR_IDX__SHIFT 0x00000000
444#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L
445#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005
446#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
447#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
448#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
449#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000
450#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
451#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
452#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
453#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
454#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
455#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
456#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
457#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000
458#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
459#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
460#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
461#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
462#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
463#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
464#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
465#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000
466#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
467#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
468#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
469#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
470#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
471#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
472#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
473#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000
474#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
475#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
476#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
477#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
478#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
479#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
480#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
481#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000
482#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
483#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
484#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
485#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
486#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
487#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
488#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
489#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000
490#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
491#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
492#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
493#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
494#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
495#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
496#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
497#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000
498#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
499#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
500#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
501#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
502#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
503#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
504#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
505#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000
506#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
507#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
508#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
509#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
510#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
511#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
512#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
513#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000
514#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
515#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
516#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
517#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
518#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
519#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
520#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
521#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000
522#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
523#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
524#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
525#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
526#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
527#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
528#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
529#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000
530#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
531#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
532#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
533#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
534#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
535#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
536#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
537#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000
538#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
539#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
540#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
541#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
542#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
543#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
544#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
545#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000
546#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
547#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
548#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
549#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
550#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
551#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
552#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
553#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000
554#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
555#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
556#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
557#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
558#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L
559#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000
560#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L
561#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019
562#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L
563#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018
564#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L
565#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018
566#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L
567#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a
568#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L
569#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008
570#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL
571#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002
572#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L
573#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011
574#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L
575#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010
576#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L
577#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010
578#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L
579#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d
580#define AUX_CONTROL__AUX_EN_MASK 0x00000001L
581#define AUX_CONTROL__AUX_EN__SHIFT 0x00000000
582#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L
583#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014
584#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L
585#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010
586#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L
587#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018
588#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L
589#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008
590#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L
591#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c
592#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L
593#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012
594#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L
595#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c
596#define AUX_CONTROL__SPARE_0_MASK 0x40000000L
597#define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e
598#define AUX_CONTROL__SPARE_1_MASK 0x80000000L
599#define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f
600#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L
601#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011
602#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L
603#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012
604#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L
605#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013
606#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L
607#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c
608#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L
609#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c
610#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L
611#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014
612#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L
613#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008
614#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L
615#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004
616#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L
617#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018
618#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L
619#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010
620#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL
621#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000
622#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L
623#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010
624#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L
625#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015
626#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L
627#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000
628#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L
629#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008
630#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L
631#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000
632#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L
633#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008
634#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L
635#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004
636#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L
637#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010
638#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L
639#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000
640#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L
641#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000
642#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L
643#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010
644#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L
645#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004
646#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L
647#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000
648#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L
649#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005
650#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L
651#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004
652#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L
653#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006
654#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L
655#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001
656#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L
657#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000
658#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L
659#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002
660#define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L
661#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008
662#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L
663#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010
664#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L
665#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d
666#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L
667#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000
668#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L
669#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009
670#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L
671#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b
672#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L
673#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018
674#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L
675#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001
676#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L
677#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013
678#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L
679#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e
680#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L
681#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c
682#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L
683#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008
684#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L
685#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a
686#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L
687#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016
688#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L
689#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017
690#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L
691#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014
692#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L
693#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012
694#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L
695#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011
696#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L
697#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007
698#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L
699#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004
700#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L
701#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f
702#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L
703#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e
704#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L
705#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a
706#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L
707#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009
708#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L
709#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008
710#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L
711#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000
712#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
713#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c
714#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L
715#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018
716#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L
717#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014
718#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L
719#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010
720#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L
721#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a
722#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L
723#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009
724#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L
725#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008
726#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L
727#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000
728#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L
729#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c
730#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L
731#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018
732#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L
733#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014
734#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L
735#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010
736#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L
737#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002
738#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L
739#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000
740#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L
741#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004
742#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L
743#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010
744#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
745#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f
746#define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L
747#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L
748#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000
749#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008
750#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L
751#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010
752#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L
753#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e
754#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L
755#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000
756#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L
757#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009
758#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L
759#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b
760#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L
761#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018
762#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L
763#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001
764#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L
765#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013
766#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L
767#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e
768#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L
769#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c
770#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L
771#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008
772#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L
773#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a
774#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L
775#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016
776#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L
777#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017
778#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L
779#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014
780#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L
781#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012
782#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L
783#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011
784#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L
785#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007
786#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L
787#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004
788#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL
789#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000
790#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L
791#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010
792#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL
793#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000
794#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L
795#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008
796#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L
797#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004
798#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L
799#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000
800#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL
801#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000
802#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L
803#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004
804#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L
805#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000
806#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL
807#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000
808#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL
809#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000
810#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L
811#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000
812#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L
813#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010
814#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L
815#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011
816#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L
817#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004
818#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L
819#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000
820#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L
821#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004
822#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L
823#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000
824#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL
825#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000
826#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L
827#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004
828#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
829#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004
830#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL
831#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000
832#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
833#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008
834#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
835#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b
836#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
837#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e
838#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
839#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f
840#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L
841#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008
842#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
843#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004
844#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
845#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000
846#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
847#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017
848#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
849#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007
850#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
851#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005
852#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
853#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003
854#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
855#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006
856#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
857#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002
858#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
859#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001
860#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L
861#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000
862#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL
863#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000
864#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
865#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003
866#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
867#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000
868#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L
869#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010
870#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
871#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008
872#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
873#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009
874#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
875#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004
876#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
877#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001
878#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
879#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b
880#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
881#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002
882#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
883#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a
884#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
885#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006
886#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
887#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005
888#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L
889#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014
890#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
891#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007
892#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL
893#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000
894#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L
895#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010
896#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL
897#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000
898#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000
899#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
900#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014
901#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
902#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000
903#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL
904#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000
905#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL
906#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000
907#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL
908#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000
909#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL
910#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000
911#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
912#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009
913#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L
914#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004
915#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL
916#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000
917#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
918#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a
919#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
920#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000
921#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL
922#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000
923#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L
924#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008
925#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L
926#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010
927#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L
928#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018
929#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL
930#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000
931#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL
932#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000
933#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
934#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e
935#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
936#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f
937#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL
938#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000
939#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L
940#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010
941#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL
942#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000
943#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL
944#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000
945#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
946#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
947#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L
948#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000
949#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
950#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
951#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
952#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
953#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
954#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
955#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L
956#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000
957#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
958#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
959#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
960#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
961#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L
962#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000
963#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
964#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
965#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
966#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
967#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L
968#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000
969#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
970#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
971#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
972#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
973#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L
974#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000
975#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
976#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
977#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
978#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
979#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L
980#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000
981#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
982#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
983#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
984#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
985#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L
986#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000
987#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
988#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
989#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
990#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
991#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L
992#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000
993#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
994#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
995#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
996#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
997#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L
998#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000
999#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1000#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1001#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
1002#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
1003#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L
1004#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000
1005#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1006#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1007#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
1008#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
1009#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L
1010#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000
1011#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1012#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1013#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
1014#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
1015#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L
1016#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000
1017#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1018#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1019#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
1020#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
1021#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L
1022#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000
1023#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1024#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1025#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
1026#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
1027#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L
1028#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000
1029#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1030#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1031#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L
1032#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008
1033#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L
1034#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f
1035#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L
1036#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011
1037#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L
1038#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012
1039#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L
1040#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010
1041#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L
1042#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b
1043#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL
1044#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000
1045#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L
1046#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f
1047#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L
1048#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004
1049#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L
1050#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000
1051#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L
1052#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001
1053#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L
1054#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c
1055#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L
1056#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008
1057#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L
1058#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009
1059#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L
1060#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014
1061#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L
1062#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010
1063#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L
1064#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011
1065#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L
1066#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c
1067#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L
1068#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018
1069#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L
1070#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019
1071#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L
1072#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004
1073#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
1074#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000
1075#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
1076#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001
1077#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L
1078#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c
1079#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L
1080#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008
1081#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L
1082#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009
1083#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L
1084#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014
1085#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L
1086#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010
1087#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L
1088#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011
1089#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L
1090#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c
1091#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L
1092#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018
1093#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L
1094#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019
1095#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
1096#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000
1097#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L
1098#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c
1099#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L
1100#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010
1101#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L
1102#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004
1103#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L
1104#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014
1105#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L
1106#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018
1107#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L
1108#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008
1109#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L
1110#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e
1111#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL
1112#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000
1113#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L
1114#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000
1115#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L
1116#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004
1117#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L
1118#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008
1119#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL
1120#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000
1121#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL
1122#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000
1123#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL
1124#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000
1125#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L
1126#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010
1127#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL
1128#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000
1129#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL
1130#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000
1131#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL
1132#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000
1133#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL
1134#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000
1135#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L
1136#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008
1137#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L
1138#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010
1139#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L
1140#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018
1141#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL
1142#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000
1143#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L
1144#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008
1145#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L
1146#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010
1147#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L
1148#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018
1149#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L
1150#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010
1151#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L
1152#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018
1153#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL
1154#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000
1155#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L
1156#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008
1157#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL
1158#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000
1159#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L
1160#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008
1161#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L
1162#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010
1163#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L
1164#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018
1165#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL
1166#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000
1167#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L
1168#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008
1169#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
1170#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007
1171#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L
1172#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c
1173#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL
1174#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000
1175#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL
1176#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000
1177#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
1178#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006
1179#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
1180#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003
1181#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
1182#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000
1183#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L
1184#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010
1185#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
1186#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008
1187#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
1188#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009
1189#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
1190#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001
1191#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
1192#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b
1193#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
1194#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002
1195#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
1196#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a
1197#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
1198#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006
1199#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
1200#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005
1201#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L
1202#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014
1203#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
1204#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007
1205#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
1206#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006
1207#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
1208#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018
1209#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
1210#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010
1211#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
1212#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007
1213#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
1214#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003
1215#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
1216#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000
1217#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
1218#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005
1219#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
1220#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002
1221#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
1222#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004
1223#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
1224#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001
1225#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L
1226#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008
1227#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL
1228#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000
1229#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL
1230#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000
1231#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL
1232#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000
1233#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
1234#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000
1235#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL
1236#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002
1237#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
1238#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
1239#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002
1240#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000
1241#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
1242#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
1243#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007
1244#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003
1245#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL
1246#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
1247#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006
1248#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000
1249#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL
1250#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
1251#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004
1252#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000
1253#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
1254#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005
1255#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
1256#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007
1257#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
1258#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004
1259#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL
1260#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000
1261#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL
1262#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000
1263#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L
1264#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004
1265#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL
1266#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000
1267#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L
1268#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004
1269#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL
1270#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000
1271#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L
1272#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004
1273#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL
1274#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000
1275#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L
1276#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004
1277#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL
1278#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000
1279#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L
1280#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004
1281#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L
1282#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004
1283#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL
1284#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000
1285#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L
1286#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008
1287#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L
1288#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b
1289#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L
1290#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e
1291#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L
1292#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L
1293#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f
1294#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f
1295#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL
1296#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000
1297#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L
1298#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007
1299#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L
1300#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008
1301#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L
1302#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004
1303#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L
1304#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000
1305#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L
1306#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017
1307#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L
1308#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007
1309#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L
1310#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005
1311#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L
1312#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003
1313#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L
1314#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006
1315#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L
1316#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002
1317#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L
1318#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001
1319#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL
1320#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000
1321#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
1322#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003
1323#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
1324#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000
1325#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L
1326#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010
1327#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
1328#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008
1329#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
1330#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009
1331#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L
1332#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004
1333#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
1334#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001
1335#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
1336#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b
1337#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
1338#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002
1339#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
1340#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a
1341#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
1342#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006
1343#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
1344#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005
1345#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L
1346#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014
1347#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
1348#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007
1349#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL
1350#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000
1351#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L
1352#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010
1353#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL
1354#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000
1355#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L
1356#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014
1357#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L
1358#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000
1359#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL
1360#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000
1361#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L
1362#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009
1363#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L
1364#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004
1365#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL
1366#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000
1367#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L
1368#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a
1369#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L
1370#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000
1371#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL
1372#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000
1373#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL
1374#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000
1375#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL
1376#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000
1377#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL
1378#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000
1379#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L
1380#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008
1381#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L
1382#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010
1383#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L
1384#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018
1385#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL
1386#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000
1387#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL
1388#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000
1389#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L
1390#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e
1391#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L
1392#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f
1393#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL
1394#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000
1395#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL
1396#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000
1397#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L
1398#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010
1399#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL
1400#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000
1401#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL
1402#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000
1403#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL
1404#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000
1405#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L
1406#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010
1407#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L
1408#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003
1409#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L
1410#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000
1411#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L
1412#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008
1413#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L
1414#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018
1415#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL
1416#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000
1417#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL
1418#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000
1419#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL
1420#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000
1421#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L
1422#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007
1423#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L
1424#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003
1425#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L
1426#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000
1427#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L
1428#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004
1429#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L
1430#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008
1431#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL
1432#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000
1433#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL
1434#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000
1435#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L
1436#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004
1437#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L
1438#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000
1439#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L
1440#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001
1441#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L
1442#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004
1443#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L
1444#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000
1445#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L
1446#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001
1447#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L
1448#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004
1449#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L
1450#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000
1451#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L
1452#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001
1453#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L
1454#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004
1455#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L
1456#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000
1457#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L
1458#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001
1459#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L
1460#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004
1461#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L
1462#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000
1463#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L
1464#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001
1465#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L
1466#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004
1467#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L
1468#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000
1469#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L
1470#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001
1471#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L
1472#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004
1473#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L
1474#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000
1475#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L
1476#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001
1477#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L
1478#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004
1479#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L
1480#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000
1481#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L
1482#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001
1483#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L
1484#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000
1485#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL
1486#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000
1487#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL
1488#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000
1489#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL
1490#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000
1491#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L
1492#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004
1493#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL
1494#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000
1495#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL
1496#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000
1497#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L
1498#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004
1499#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL
1500#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000
1501#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L
1502#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006
1503#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L
1504#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c
1505#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L
1506#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010
1507#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L
1508#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004
1509#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L
1510#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014
1511#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L
1512#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018
1513#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L
1514#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008
1515#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L
1516#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e
1517#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL
1518#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000
1519#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL
1520#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000
1521#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL
1522#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000
1523#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L
1524#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f
1525#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L
1526#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009
1527#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L
1528#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a
1529#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L
1530#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008
1531#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL
1532#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000
1533#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL
1534#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000
1535#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L
1536#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007
1537#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL
1538#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000
1539#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L
1540#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006
1541#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L
1542#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003
1543#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L
1544#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000
1545#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L
1546#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010
1547#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L
1548#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008
1549#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L
1550#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009
1551#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L
1552#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001
1553#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L
1554#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b
1555#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L
1556#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002
1557#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L
1558#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a
1559#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L
1560#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006
1561#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L
1562#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005
1563#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L
1564#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014
1565#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L
1566#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007
1567#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L
1568#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006
1569#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L
1570#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018
1571#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L
1572#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010
1573#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L
1574#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007
1575#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L
1576#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003
1577#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L
1578#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000
1579#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L
1580#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005
1581#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L
1582#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002
1583#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L
1584#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004
1585#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L
1586#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001
1587#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L
1588#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008
1589#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL
1590#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000
1591#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL
1592#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000
1593#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL
1594#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000
1595#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL
1596#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000
1597#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L
1598#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000
1599#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL
1600#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002
1601#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L
1602#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L
1603#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002
1604#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000
1605#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L
1606#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L
1607#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007
1608#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003
1609#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL
1610#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L
1611#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006
1612#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000
1613#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL
1614#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L
1615#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004
1616#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000
1617#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L
1618#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005
1619#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L
1620#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007
1621#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L
1622#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004
1623#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL
1624#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000
1625#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL
1626#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000
1627#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L
1628#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004
1629#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL
1630#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000
1631#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L
1632#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004
1633#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL
1634#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000
1635#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L
1636#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004
1637#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL
1638#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000
1639#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L
1640#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004
1641#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L
1642#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008
1643#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L
1644#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010
1645#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL
1646#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000
1647#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L
1648#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001
1649#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L
1650#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000
1651#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL
1652#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000
1653#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L
1654#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010
1655#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL
1656#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000
1657#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L
1658#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008
1659#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L
1660#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004
1661#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L
1662#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000
1663#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L
1664#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004
1665#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL
1666#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000
1667#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL
1668#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000
1669#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL
1670#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000
1671#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L
1672#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008
1673#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL
1674#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000
1675#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL
1676#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000
1677#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL
1678#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000
1679#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL
1680#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000
1681#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
1682#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
1683#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L
1684#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003
1685#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L
1686#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002
1687#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L
1688#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010
1689#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L
1690#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000
1691#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L
1692#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001
1693#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL
1694#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000
1695#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
1696#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f
1697#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L
1698#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010
1699#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
1700#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001
1701#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
1702#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000
1703#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L
1704#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008
1705#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL
1706#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000
1707#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL
1708#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000
1709#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L
1710#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011
1711#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
1712#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f
1713#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
1714#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018
1715#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L
1716#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000
1717#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L
1718#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008
1719#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L
1720#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010
1721#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL
1722#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000
1723#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL
1724#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000
1725#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL
1726#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000
1727#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L
1728#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e
1729#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L
1730#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f
1731#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL
1732#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000
1733#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L
1734#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c
1735#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL
1736#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000
1737#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L
1738#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f
1739#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L
1740#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e
1741#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L
1742#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011
1743#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L
1744#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f
1745#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L
1746#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018
1747#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L
1748#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000
1749#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L
1750#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008
1751#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L
1752#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010
1753#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L
1754#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010
1755#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL
1756#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000
1757#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L
1758#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c
1759#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L
1760#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002
1761#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L
1762#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001
1763#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L
1764#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000
1765#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L
1766#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014
1767#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L
1768#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004
1769#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L
1770#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018
1771#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L
1772#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010
1773#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L
1774#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c
1775#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L
1776#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008
1777#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L
1778#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000
1779#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL
1780#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001
1781#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L
1782#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L
1783#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004
1784#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000
1785#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL
1786#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000
1787#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L
1788#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010
1789#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL
1790#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000
1791#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L
1792#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010
1793#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL
1794#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000
1795#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L
1796#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010
1797#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL
1798#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000
1799#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L
1800#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010
1801#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL
1802#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000
1803#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L
1804#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010
1805#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL
1806#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000
1807#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L
1808#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010
1809#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL
1810#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000
1811#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L
1812#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010
1813#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL
1814#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000
1815#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L
1816#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010
1817#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL
1818#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000
1819#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L
1820#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010
1821#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL
1822#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000
1823#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L
1824#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010
1825#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL
1826#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000
1827#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L
1828#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010
1829#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL
1830#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000
1831#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L
1832#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010
1833#define CRT00__H_TOTAL_MASK 0x000000ffL
1834#define CRT00__H_TOTAL__SHIFT 0x00000000
1835#define CRT01__H_DISP_END_MASK 0x000000ffL
1836#define CRT01__H_DISP_END__SHIFT 0x00000000
1837#define CRT02__H_BLANK_START_MASK 0x000000ffL
1838#define CRT02__H_BLANK_START__SHIFT 0x00000000
1839#define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L
1840#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007
1841#define CRT03__H_BLANK_END_MASK 0x0000001fL
1842#define CRT03__H_BLANK_END__SHIFT 0x00000000
1843#define CRT03__H_DE_SKEW_MASK 0x00000060L
1844#define CRT03__H_DE_SKEW__SHIFT 0x00000005
1845#define CRT04__H_SYNC_START_MASK 0x000000ffL
1846#define CRT04__H_SYNC_START__SHIFT 0x00000000
1847#define CRT05__H_BLANK_END_B5_MASK 0x00000080L
1848#define CRT05__H_BLANK_END_B5__SHIFT 0x00000007
1849#define CRT05__H_SYNC_END_MASK 0x0000001fL
1850#define CRT05__H_SYNC_END__SHIFT 0x00000000
1851#define CRT05__H_SYNC_SKEW_MASK 0x00000060L
1852#define CRT05__H_SYNC_SKEW__SHIFT 0x00000005
1853#define CRT06__V_TOTAL_MASK 0x000000ffL
1854#define CRT06__V_TOTAL__SHIFT 0x00000000
1855#define CRT07__LINE_CMP_B8_MASK 0x00000010L
1856#define CRT07__LINE_CMP_B8__SHIFT 0x00000004
1857#define CRT07__V_BLANK_START_B8_MASK 0x00000008L
1858#define CRT07__V_BLANK_START_B8__SHIFT 0x00000003
1859#define CRT07__V_DISP_END_B8_MASK 0x00000002L
1860#define CRT07__V_DISP_END_B8__SHIFT 0x00000001
1861#define CRT07__V_DISP_END_B9_MASK 0x00000040L
1862#define CRT07__V_DISP_END_B9__SHIFT 0x00000006
1863#define CRT07__V_SYNC_START_B8_MASK 0x00000004L
1864#define CRT07__V_SYNC_START_B8__SHIFT 0x00000002
1865#define CRT07__V_SYNC_START_B9_MASK 0x00000080L
1866#define CRT07__V_SYNC_START_B9__SHIFT 0x00000007
1867#define CRT07__V_TOTAL_B8_MASK 0x00000001L
1868#define CRT07__V_TOTAL_B8__SHIFT 0x00000000
1869#define CRT07__V_TOTAL_B9_MASK 0x00000020L
1870#define CRT07__V_TOTAL_B9__SHIFT 0x00000005
1871#define CRT08__BYTE_PAN_MASK 0x00000060L
1872#define CRT08__BYTE_PAN__SHIFT 0x00000005
1873#define CRT08__ROW_SCAN_START_MASK 0x0000001fL
1874#define CRT08__ROW_SCAN_START__SHIFT 0x00000000
1875#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L
1876#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007
1877#define CRT09__LINE_CMP_B9_MASK 0x00000040L
1878#define CRT09__LINE_CMP_B9__SHIFT 0x00000006
1879#define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL
1880#define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000
1881#define CRT09__V_BLANK_START_B9_MASK 0x00000020L
1882#define CRT09__V_BLANK_START_B9__SHIFT 0x00000005
1883#define CRT0A__CURSOR_DISABLE_MASK 0x00000020L
1884#define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005
1885#define CRT0A__CURSOR_START_MASK 0x0000001fL
1886#define CRT0A__CURSOR_START__SHIFT 0x00000000
1887#define CRT0B__CURSOR_END_MASK 0x0000001fL
1888#define CRT0B__CURSOR_END__SHIFT 0x00000000
1889#define CRT0B__CURSOR_SKEW_MASK 0x00000060L
1890#define CRT0B__CURSOR_SKEW__SHIFT 0x00000005
1891#define CRT0C__DISP_START_MASK 0x000000ffL
1892#define CRT0C__DISP_START__SHIFT 0x00000000
1893#define CRT0D__DISP_START_MASK 0x000000ffL
1894#define CRT0D__DISP_START__SHIFT 0x00000000
1895#define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL
1896#define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000
1897#define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL
1898#define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000
1899#define CRT10__V_SYNC_START_MASK 0x000000ffL
1900#define CRT10__V_SYNC_START__SHIFT 0x00000000
1901#define CRT11__C0T7_WR_ONLY_MASK 0x00000080L
1902#define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007
1903#define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L
1904#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006
1905#define CRT11__V_INTR_CLR_MASK 0x00000010L
1906#define CRT11__V_INTR_CLR__SHIFT 0x00000004
1907#define CRT11__V_INTR_EN_MASK 0x00000020L
1908#define CRT11__V_INTR_EN__SHIFT 0x00000005
1909#define CRT11__V_SYNC_END_MASK 0x0000000fL
1910#define CRT11__V_SYNC_END__SHIFT 0x00000000
1911#define CRT12__V_DISP_END_MASK 0x000000ffL
1912#define CRT12__V_DISP_END__SHIFT 0x00000000
1913#define CRT13__DISP_PITCH_MASK 0x000000ffL
1914#define CRT13__DISP_PITCH__SHIFT 0x00000000
1915#define CRT14__ADDR_CNT_BY4_MASK 0x00000020L
1916#define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005
1917#define CRT14__DOUBLE_WORD_MASK 0x00000040L
1918#define CRT14__DOUBLE_WORD__SHIFT 0x00000006
1919#define CRT14__UNDRLN_LOC_MASK 0x0000001fL
1920#define CRT14__UNDRLN_LOC__SHIFT 0x00000000
1921#define CRT15__V_BLANK_START_MASK 0x000000ffL
1922#define CRT15__V_BLANK_START__SHIFT 0x00000000
1923#define CRT16__V_BLANK_END_MASK 0x000000ffL
1924#define CRT16__V_BLANK_END__SHIFT 0x00000000
1925#define CRT17__ADDR_CNT_BY2_MASK 0x00000008L
1926#define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003
1927#define CRT17__BYTE_MODE_MASK 0x00000040L
1928#define CRT17__BYTE_MODE__SHIFT 0x00000006
1929#define CRT17__CRTC_SYNC_EN_MASK 0x00000080L
1930#define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007
1931#define CRT17__RA0_AS_A13B_MASK 0x00000001L
1932#define CRT17__RA0_AS_A13B__SHIFT 0x00000000
1933#define CRT17__RA1_AS_A14B_MASK 0x00000002L
1934#define CRT17__RA1_AS_A14B__SHIFT 0x00000001
1935#define CRT17__VCOUNT_BY2_MASK 0x00000004L
1936#define CRT17__VCOUNT_BY2__SHIFT 0x00000002
1937#define CRT17__WRAP_A15TOA0_MASK 0x00000020L
1938#define CRT17__WRAP_A15TOA0__SHIFT 0x00000005
1939#define CRT18__LINE_CMP_MASK 0x000000ffL
1940#define CRT18__LINE_CMP__SHIFT 0x00000000
1941#define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L
1942#define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001
1943#define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL
1944#define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000
1945#define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL
1946#define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000
1947#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L
1948#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008
1949#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L
1950#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010
1951#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L
1952#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e
1953#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L
1954#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009
1955#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L
1956#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000
1957#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L
1958#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004
1959#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L
1960#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008
1961#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L
1962#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010
1963#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L
1964#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e
1965#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L
1966#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009
1967#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L
1968#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000
1969#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L
1970#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004
1971#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L
1972#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008
1973#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L
1974#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010
1975#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L
1976#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e
1977#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L
1978#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009
1979#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L
1980#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000
1981#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L
1982#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004
1983#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L
1984#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004
1985#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L
1986#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000
1987#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L
1988#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L
1989#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L
1990#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011
1991#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010
1992#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012
1993#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L
1994#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c
1995#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L
1996#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008
1997#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L
1998#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008
1999#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L
2000#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010
2001#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L
2002#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e
2003#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L
2004#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009
2005#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L
2006#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000
2007#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L
2008#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004
2009#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L
2010#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008
2011#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L
2012#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010
2013#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L
2014#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e
2015#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L
2016#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009
2017#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L
2018#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000
2019#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L
2020#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004
2021#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L
2022#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008
2023#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L
2024#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010
2025#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L
2026#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e
2027#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L
2028#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009
2029#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L
2030#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000
2031#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L
2032#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004
2033#define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL
2034#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000
2035#define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL
2036#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000
2037#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL
2038#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000
2039#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L
2040#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010
2041#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL
2042#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000
2043#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L
2044#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a
2045#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L
2046#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014
2047#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L
2048#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008
2049#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L
2050#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010
2051#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L
2052#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000
2053#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL
2054#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000
2055#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L
2056#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a
2057#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L
2058#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014
2059#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L
2060#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010
2061#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L
2062#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008
2063#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L
2064#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018
2065#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L
2066#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d
2067#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L
2068#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014
2069#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L
2070#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000
2071#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L
2072#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d
2073#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L
2074#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c
2075#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
2076#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004
2077#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
2078#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000
2079#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL
2080#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001
2081#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L
2082#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000
2083#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L
2084#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f
2085#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L
2086#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018
2087#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L
2088#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008
2089#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L
2090#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c
2091#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L
2092#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004
2093#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L
2094#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010
2095#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L
2096#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008
2097#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L
2098#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000
2099#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL
2100#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001
2101#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L
2102#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000
2103#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L
2104#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010
2105#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL
2106#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000
2107#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L
2108#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010
2109#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L
2110#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018
2111#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L
2112#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008
2113#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL
2114#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000
2115#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L
2116#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004
2117#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L
2118#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018
2119#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L
2120#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000
2121#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L
2122#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010
2123#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L
2124#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008
2125#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L
2126#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c
2127#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL
2128#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000
2129#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L
2130#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010
2131#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L
2132#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013
2133#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L
2134#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008
2135#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL
2136#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000
2137#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L
2138#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L
2139#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017
2140#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L
2141#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011
2142#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L
2143#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014
2144#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018
2145#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L
2146#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010
2147#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L
2148#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010
2149#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL
2150#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000
2151#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L
2152#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010
2153#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL
2154#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000
2155#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L
2156#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010
2157#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL
2158#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000
2159#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L
2160#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010
2161#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L
2162#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011
2163#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L
2164#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000
2165#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L
2166#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010
2167#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL
2168#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000
2169#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L
2170#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010
2171#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L
2172#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011
2173#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L
2174#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000
2175#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L
2176#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010
2177#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL
2178#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000
2179#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL
2180#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000
2181#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L
2182#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000
2183#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L
2184#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010
2185#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L
2186#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000
2187#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L
2188#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001
2189#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L
2190#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008
2191#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L
2192#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009
2193#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L
2194#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010
2195#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L
2196#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011
2197#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L
2198#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e
2199#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L
2200#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f
2201#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L
2202#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000
2203#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L
2204#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001
2205#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L
2206#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018
2207#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L
2208#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a
2209#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L
2210#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019
2211#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L
2212#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b
2213#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L
2214#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c
2215#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L
2216#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d
2217#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L
2218#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004
2219#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L
2220#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005
2221#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L
2222#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000
2223#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L
2224#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000
2225#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L
2226#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008
2227#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L
2228#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000
2229#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL
2230#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000
2231#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L
2232#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014
2233#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L
2234#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004
2235#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L
2236#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010
2237#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L
2238#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000
2239#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL
2240#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000
2241#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL
2242#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000
2243#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L
2244#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a
2245#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L
2246#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014
2247#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L
2248#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000
2249#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL
2250#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000
2251#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L
2252#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010
2253#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL
2254#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000
2255#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L
2256#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001
2257#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L
2258#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002
2259#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L
2260#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000
2261#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L
2262#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010
2263#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L
2264#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008
2265#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
2266#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000
2267#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
2268#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011
2269#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L
2270#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010
2271#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L
2272#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012
2273#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L
2274#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001
2275#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L
2276#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005
2277#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L
2278#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000
2279#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L
2280#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004
2281#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L
2282#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002
2283#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L
2284#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003
2285#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL
2286#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000
2287#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL
2288#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000
2289#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L
2290#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010
2291#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL
2292#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000
2293#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL
2294#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000
2295#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L
2296#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018
2297#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL
2298#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000
2299#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L
2300#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f
2301#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L
2302#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010
2303#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L
2304#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000
2305#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L
2306#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000
2307#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L
2308#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018
2309#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L
2310#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008
2311#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L
2312#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010
2313#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL
2314#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000
2315#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL
2316#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000
2317#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
2318#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
2319#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL
2320#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000
2321#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L
2322#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010
2323#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L
2324#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018
2325#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L
2326#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010
2327#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L
2328#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000
2329#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L
2330#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008
2331#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L
2332#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c
2333#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL
2334#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000
2335#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L
2336#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004
2337#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L
2338#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010
2339#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L
2340#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008
2341#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L
2342#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f
2343#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L
2344#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018
2345#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
2346#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010
2347#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L
2348#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014
2349#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L
2350#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009
2351#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L
2352#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b
2353#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L
2354#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005
2355#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L
2356#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a
2357#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L
2358#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008
2359#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
2360#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c
2361#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL
2362#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000
2363#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L
2364#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000
2365#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L
2366#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f
2367#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L
2368#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018
2369#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L
2370#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010
2371#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L
2372#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014
2373#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L
2374#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009
2375#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L
2376#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b
2377#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L
2378#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005
2379#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L
2380#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a
2381#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L
2382#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008
2383#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L
2384#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c
2385#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL
2386#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000
2387#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L
2388#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000
2389#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L
2390#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000
2391#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L
2392#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010
2393#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL
2394#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000
2395#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L
2396#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010
2397#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL
2398#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000
2399#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L
2400#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010
2401#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L
2402#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008
2403#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L
2404#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000
2405#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L
2406#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000
2407#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L
2408#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000
2409#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L
2410#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010
2411#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL
2412#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000
2413#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L
2414#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000
2415#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L
2416#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010
2417#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL
2418#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000
2419#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L
2420#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004
2421#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L
2422#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000
2423#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L
2424#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008
2425#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L
2426#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c
2427#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L
2428#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010
2429#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L
2430#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004
2431#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L
2432#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000
2433#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL
2434#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000
2435#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L
2436#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008
2437#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L
2438#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004
2439#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L
2440#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L
2441#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c
2442#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000
2443#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L
2444#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010
2445#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL
2446#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000
2447#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL
2448#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000
2449#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L
2450#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008
2451#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L
2452#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000
2453#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL
2454#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000
2455#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L
2456#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008
2457#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L
2458#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010
2459#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL
2460#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000
2461#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L
2462#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008
2463#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L
2464#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010
2465#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L
2466#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004
2467#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L
2468#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010
2469#define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L
2470#define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000
2471#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L
2472#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014
2473#define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L
2474#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008
2475#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L
2476#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018
2477#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L
2478#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010
2479#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL
2480#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000
2481#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L
2482#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010
2483#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL
2484#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000
2485#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L
2486#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000
2487#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL
2488#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000
2489#define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L
2490#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010
2491#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL
2492#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000
2493#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL
2494#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000
2495#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
2496#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018
2497#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L
2498#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010
2499#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L
2500#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000
2501#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L
2502#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001
2503#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L
2504#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000
2505#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
2506#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010
2507#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L
2508#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018
2509#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
2510#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009
2511#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L
2512#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008
2513#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L
2514#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000
2515#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
2516#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010
2517#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L
2518#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018
2519#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
2520#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009
2521#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L
2522#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008
2523#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L
2524#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000
2525#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
2526#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010
2527#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L
2528#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018
2529#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
2530#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009
2531#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L
2532#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008
2533#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L
2534#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000
2535#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
2536#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010
2537#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L
2538#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018
2539#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
2540#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009
2541#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L
2542#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008
2543#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L
2544#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000
2545#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
2546#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010
2547#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L
2548#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018
2549#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
2550#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009
2551#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L
2552#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008
2553#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L
2554#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000
2555#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L
2556#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010
2557#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L
2558#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018
2559#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L
2560#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009
2561#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L
2562#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008
2563#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL
2564#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000
2565#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L
2566#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008
2567#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL
2568#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000
2569#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L
2570#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008
2571#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L
2572#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010
2573#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L
2574#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008
2575#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L
2576#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000
2577#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L
2578#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000
2579#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L
2580#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010
2581#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L
2582#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018
2583#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L
2584#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004
2585#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L
2586#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010
2587#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L
2588#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008
2589#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L
2590#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000
2591#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L
2592#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000
2593#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L
2594#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004
2595#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L
2596#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012
2597#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L
2598#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000
2599#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L
2600#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008
2601#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L
2602#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011
2603#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L
2604#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010
2605#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L
2606#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001
2607#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L
2608#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002
2609#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L
2610#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L
2611#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003
2612#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000
2613#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L
2614#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000
2615#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L
2616#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008
2617#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L
2618#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010
2619#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L
2620#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000
2621#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L
2622#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008
2623#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L
2624#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010
2625#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L
2626#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000
2627#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL
2628#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000
2629#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL
2630#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000
2631#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL
2632#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000
2633#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L
2634#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a
2635#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L
2636#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014
2637#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL
2638#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000
2639#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L
2640#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a
2641#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L
2642#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014
2643#define DAC_DATA__DAC_DATA_MASK 0x0000003fL
2644#define DAC_DATA__DAC_DATA__SHIFT 0x00000000
2645#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL
2646#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000
2647#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L
2648#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000
2649#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L
2650#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001
2651#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L
2652#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005
2653#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L
2654#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004
2655#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL
2656#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002
2657#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L
2658#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008
2659#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L
2660#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a
2661#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L
2662#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d
2663#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
2664#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e
2665#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
2666#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f
2667#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L
2668#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010
2669#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L
2670#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016
2671#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL
2672#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002
2673#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
2674#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001
2675#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL
2676#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000
2677#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L
2678#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000
2679#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L
2680#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018
2681#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L
2682#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008
2683#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL
2684#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000
2685#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL
2686#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000
2687#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL
2688#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000
2689#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL
2690#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000
2691#define DAC_MASK__DAC_MASK_MASK 0x000000ffL
2692#define DAC_MASK__DAC_MASK__SHIFT 0x00000000
2693#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L
2694#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008
2695#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L
2696#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010
2697#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L
2698#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L
2699#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018
2700#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000
2701#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L
2702#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000
2703#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L
2704#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010
2705#define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL
2706#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000
2707#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L
2708#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000
2709#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L
2710#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003
2711#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L
2712#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000
2713#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L
2714#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000
2715#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L
2716#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010
2717#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L
2718#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008
2719#define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL
2720#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000
2721#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L
2722#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008
2723#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L
2724#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000
2725#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L
2726#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f
2727#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L
2728#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010
2729#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL
2730#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000
2731#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L
2732#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f
2733#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L
2734#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010
2735#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL
2736#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000
2737#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L
2738#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f
2739#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L
2740#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010
2741#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL
2742#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000
2743#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L
2744#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f
2745#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L
2746#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010
2747#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL
2748#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000
2749#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L
2750#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f
2751#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L
2752#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010
2753#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL
2754#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000
2755#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L
2756#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f
2757#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL
2758#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000
2759#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L
2760#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010
2761#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L
2762#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e
2763#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L
2764#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c
2765#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L
2766#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f
2767#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L
2768#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d
2769#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL
2770#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000
2771#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L
2772#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010
2773#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L
2774#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f
2775#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L
2776#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f
2777#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L
2778#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000
2779#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L
2780#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008
2781#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L
2782#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010
2783#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L
2784#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000
2785#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L
2786#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008
2787#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL
2788#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000
2789#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL
2790#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000
2791#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL
2792#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000
2793#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL
2794#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000
2795#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL
2796#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000
2797#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L
2798#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002
2799#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L
2800#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f
2801#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L
2802#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a
2803#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L
2804#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000
2805#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L
2806#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010
2807#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L
2808#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008
2809#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L
2810#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001
2811#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L
2812#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018
2813#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L
2814#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009
2815#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L
2816#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017
2817#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L
2818#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018
2819#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L
2820#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c
2821#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L
2822#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e
2823#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L
2824#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010
2825#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L
2826#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c
2827#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L
2828#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d
2829#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
2830#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f
2831#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L
2832#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000
2833#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L
2834#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008
2835#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L
2836#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014
2837#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL
2838#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000
2839#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL
2840#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000
2841#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL
2842#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000
2843#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL
2844#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000
2845#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL
2846#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000
2847#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL
2848#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000
2849#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL
2850#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000
2851#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL
2852#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000
2853#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL
2854#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000
2855#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL
2856#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000
2857#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL
2858#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000
2859#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL
2860#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000
2861#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL
2862#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000
2863#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL
2864#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000
2865#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL
2866#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000
2867#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL
2868#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000
2869#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL
2870#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000
2871#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL
2872#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000
2873#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL
2874#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000
2875#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL
2876#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000
2877#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL
2878#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000
2879#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL
2880#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000
2881#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL
2882#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000
2883#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL
2884#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000
2885#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L
2886#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010
2887#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
2888#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f
2889#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
2890#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001
2891#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
2892#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000
2893#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L
2894#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008
2895#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
2896#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f
2897#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL
2898#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000
2899#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L
2900#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008
2901#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L
2902#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010
2903#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L
2904#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010
2905#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL
2906#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000
2907#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL
2908#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000
2909#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L
2910#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010
2911#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL
2912#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000
2913#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
2914#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f
2915#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L
2916#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010
2917#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL
2918#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000
2919#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL
2920#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000
2921#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL
2922#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000
2923#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL
2924#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000
2925#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L
2926#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f
2927#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L
2928#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010
2929#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L
2930#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001
2931#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L
2932#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000
2933#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L
2934#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008
2935#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL
2936#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000
2937#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L
2938#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014
2939#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L
2940#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a
2941#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL
2942#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000
2943#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL
2944#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000
2945#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL
2946#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000
2947#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL
2948#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000
2949#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL
2950#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000
2951#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L
2952#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000
2953#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L
2954#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004
2955#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL
2956#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000
2957#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L
2958#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004
2959#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L
2960#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005
2961#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L
2962#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000
2963#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L
2964#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018
2965#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L
2966#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001
2967#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L
2968#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014
2969#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L
2970#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006
2971#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L
2972#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010
2973#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L
2974#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002
2975#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L
2976#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c
2977#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L
2978#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008
2979#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L
2980#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009
2981#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L
2982#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a
2983#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L
2984#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b
2985#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L
2986#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c
2987#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L
2988#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d
2989#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L
2990#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000
2991#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL
2992#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000
2993#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL
2994#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000
2995#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L
2996#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008
2997#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L
2998#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000
2999#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L
3000#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001
3001#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L
3002#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007
3003#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L
3004#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006
3005#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L
3006#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004
3007#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L
3008#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002
3009#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L
3010#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003
3011#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L
3012#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005
3013#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L
3014#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000
3015#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L
3016#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010
3017#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL
3018#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000
3019#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L
3020#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018
3021#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L
3022#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008
3023#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL
3024#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000
3025#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L
3026#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c
3027#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL
3028#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000
3029#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
3030#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
3031#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L
3032#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002
3033#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L
3034#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a
3035#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L
3036#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000
3037#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L
3038#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003
3039#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L
3040#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010
3041#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L
3042#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008
3043#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L
3044#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014
3045#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L
3046#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009
3047#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L
3048#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015
3049#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L
3050#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a
3051#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L
3052#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016
3053#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L
3054#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b
3055#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L
3056#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017
3057#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L
3058#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c
3059#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L
3060#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018
3061#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L
3062#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d
3063#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L
3064#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019
3065#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L
3066#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005
3067#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L
3068#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012
3069#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L
3070#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e
3071#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L
3072#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013
3073#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L
3074#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004
3075#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L
3076#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011
3077#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L
3078#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001
3079#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L
3080#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f
3081#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL
3082#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000
3083#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL
3084#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000
3085#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL
3086#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000
3087#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL
3088#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000
3089#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL
3090#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000
3091#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L
3092#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005
3093#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L
3094#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006
3095#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L
3096#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014
3097#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L
3098#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007
3099#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L
3100#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008
3101#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL
3102#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000
3103#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L
3104#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c
3105#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL
3106#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000
3107#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L
3108#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004
3109#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L
3110#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c
3111#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L
3112#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010
3113#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L
3114#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014
3115#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL
3116#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000
3117#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L
3118#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015
3119#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L
3120#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014
3121#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L
3122#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013
3123#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L
3124#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004
3125#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L
3126#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000
3127#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L
3128#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001
3129#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L
3130#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002
3131#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L
3132#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003
3133#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L
3134#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004
3135#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L
3136#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000
3137#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L
3138#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001
3139#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L
3140#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002
3141#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L
3142#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003
3143#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L
3144#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004
3145#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L
3146#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000
3147#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L
3148#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001
3149#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L
3150#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002
3151#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L
3152#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003
3153#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L
3154#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004
3155#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L
3156#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000
3157#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L
3158#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001
3159#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L
3160#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002
3161#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L
3162#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003
3163#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L
3164#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004
3165#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L
3166#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000
3167#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L
3168#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001
3169#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L
3170#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002
3171#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L
3172#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003
3173#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L
3174#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004
3175#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L
3176#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000
3177#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L
3178#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001
3179#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L
3180#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002
3181#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L
3182#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003
3183#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL
3184#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000
3185#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L
3186#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000
3187#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L
3188#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008
3189#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L
3190#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002
3191#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L
3192#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c
3193#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L
3194#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d
3195#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L
3196#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e
3197#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L
3198#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004
3199#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L
3200#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010
3201#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L
3202#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016
3203#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L
3204#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018
3205#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L
3206#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003
3207#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L
3208#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e
3209#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L
3210#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c
3211#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L
3212#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006
3213#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L
3214#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014
3215#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L
3216#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005
3217#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L
3218#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012
3219#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L
3220#define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000
3221#define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L
3222#define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008
3223#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L
3224#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018
3225#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L
3226#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010
3227#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L
3228#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014
3229#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L
3230#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c
3231#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L
3232#define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000
3233#define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L
3234#define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008
3235#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L
3236#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018
3237#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L
3238#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010
3239#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L
3240#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014
3241#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L
3242#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c
3243#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L
3244#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000
3245#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L
3246#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008
3247#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L
3248#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000
3249#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L
3250#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008
3251#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L
3252#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016
3253#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L
3254#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014
3255#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L
3256#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010
3257#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L
3258#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000
3259#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L
3260#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004
3261#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L
3262#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006
3263#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L
3264#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018
3265#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L
3266#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008
3267#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L
3268#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c
3269#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L
3270#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e
3271#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L
3272#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c
3273#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L
3274#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000
3275#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L
3276#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008
3277#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L
3278#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000
3279#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L
3280#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008
3281#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L
3282#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000
3283#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L
3284#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008
3285#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L
3286#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016
3287#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L
3288#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014
3289#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L
3290#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010
3291#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L
3292#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000
3293#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L
3294#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004
3295#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L
3296#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006
3297#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L
3298#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018
3299#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L
3300#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008
3301#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L
3302#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c
3303#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L
3304#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e
3305#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L
3306#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c
3307#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L
3308#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000
3309#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L
3310#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008
3311#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L
3312#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000
3313#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L
3314#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008
3315#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L
3316#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000
3317#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L
3318#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008
3319#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L
3320#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016
3321#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L
3322#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014
3323#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L
3324#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010
3325#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L
3326#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000
3327#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L
3328#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004
3329#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L
3330#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006
3331#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L
3332#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018
3333#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L
3334#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008
3335#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L
3336#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c
3337#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L
3338#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e
3339#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L
3340#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c
3341#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L
3342#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000
3343#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L
3344#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008
3345#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L
3346#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000
3347#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L
3348#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008
3349#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L
3350#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000
3351#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L
3352#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008
3353#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L
3354#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016
3355#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L
3356#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014
3357#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L
3358#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010
3359#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L
3360#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000
3361#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L
3362#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004
3363#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L
3364#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006
3365#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L
3366#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018
3367#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L
3368#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008
3369#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L
3370#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c
3371#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L
3372#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e
3373#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L
3374#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c
3375#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L
3376#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000
3377#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L
3378#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008
3379#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L
3380#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000
3381#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L
3382#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008
3383#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L
3384#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000
3385#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L
3386#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008
3387#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L
3388#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016
3389#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L
3390#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014
3391#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L
3392#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010
3393#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L
3394#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000
3395#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L
3396#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004
3397#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L
3398#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006
3399#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L
3400#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018
3401#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L
3402#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008
3403#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L
3404#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c
3405#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L
3406#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e
3407#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L
3408#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c
3409#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L
3410#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000
3411#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L
3412#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008
3413#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L
3414#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000
3415#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L
3416#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008
3417#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L
3418#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000
3419#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L
3420#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008
3421#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L
3422#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016
3423#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L
3424#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014
3425#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L
3426#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010
3427#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L
3428#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000
3429#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L
3430#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004
3431#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L
3432#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006
3433#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L
3434#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018
3435#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L
3436#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008
3437#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L
3438#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c
3439#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L
3440#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e
3441#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L
3442#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c
3443#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L
3444#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000
3445#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L
3446#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008
3447#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L
3448#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000
3449#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L
3450#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008
3451#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L
3452#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000
3453#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L
3454#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008
3455#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L
3456#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016
3457#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L
3458#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010
3459#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L
3460#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014
3461#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L
3462#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000
3463#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L
3464#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006
3465#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L
3466#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018
3467#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L
3468#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008
3469#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L
3470#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c
3471#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L
3472#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e
3473#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L
3474#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c
3475#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L
3476#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000
3477#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L
3478#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008
3479#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L
3480#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010
3481#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L
3482#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008
3483#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L
3484#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000
3485#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L
3486#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c
3487#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L
3488#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018
3489#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL
3490#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000
3491#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L
3492#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e
3493#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L
3494#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c
3495#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L
3496#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018
3497#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL
3498#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000
3499#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L
3500#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e
3501#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L
3502#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c
3503#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L
3504#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018
3505#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL
3506#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000
3507#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L
3508#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e
3509#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L
3510#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c
3511#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L
3512#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018
3513#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL
3514#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000
3515#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L
3516#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e
3517#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L
3518#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000
3519#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L
3520#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008
3521#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L
3522#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010
3523#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L
3524#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014
3525#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L
3526#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015
3527#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L
3528#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016
3529#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L
3530#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017
3531#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L
3532#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000
3533#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L
3534#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008
3535#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L
3536#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010
3537#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L
3538#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014
3539#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L
3540#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015
3541#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L
3542#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016
3543#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L
3544#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017
3545#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L
3546#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000
3547#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L
3548#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001
3549#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L
3550#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002
3551#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L
3552#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004
3553#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L
3554#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005
3555#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L
3556#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006
3557#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L
3558#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008
3559#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L
3560#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009
3561#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L
3562#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a
3563#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L
3564#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c
3565#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L
3566#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d
3567#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L
3568#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e
3569#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L
3570#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010
3571#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L
3572#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011
3573#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L
3574#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012
3575#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L
3576#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014
3577#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L
3578#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015
3579#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L
3580#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016
3581#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L
3582#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018
3583#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L
3584#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019
3585#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L
3586#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a
3587#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L
3588#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000
3589#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L
3590#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008
3591#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L
3592#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010
3593#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L
3594#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014
3595#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L
3596#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015
3597#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L
3598#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016
3599#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L
3600#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017
3601#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L
3602#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000
3603#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L
3604#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008
3605#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L
3606#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010
3607#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L
3608#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018
3609#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L
3610#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000
3611#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L
3612#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008
3613#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L
3614#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010
3615#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L
3616#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018
3617#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L
3618#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000
3619#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L
3620#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001
3621#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L
3622#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003
3623#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L
3624#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002
3625#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L
3626#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008
3627#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L
3628#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009
3629#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L
3630#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b
3631#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L
3632#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a
3633#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L
3634#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010
3635#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L
3636#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011
3637#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L
3638#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013
3639#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L
3640#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012
3641#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L
3642#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018
3643#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L
3644#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019
3645#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L
3646#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b
3647#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L
3648#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a
3649#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L
3650#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000
3651#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L
3652#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008
3653#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L
3654#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010
3655#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L
3656#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018
3657#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L
3658#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000
3659#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L
3660#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008
3661#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L
3662#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010
3663#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L
3664#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018
3665#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L
3666#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a
3667#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L
3668#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c
3669#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L
3670#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000
3671#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L
3672#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008
3673#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L
3674#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010
3675#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L
3676#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018
3677#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L
3678#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a
3679#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L
3680#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c
3681#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L
3682#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000
3683#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L
3684#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004
3685#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L
3686#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006
3687#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L
3688#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008
3689#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L
3690#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009
3691#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L
3692#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a
3693#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L
3694#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010
3695#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L
3696#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011
3697#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L
3698#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012
3699#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L
3700#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014
3701#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L
3702#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015
3703#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L
3704#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016
3705#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L
3706#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018
3707#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L
3708#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019
3709#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L
3710#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a
3711#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L
3712#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c
3713#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L
3714#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d
3715#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L
3716#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e
3717#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L
3718#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000
3719#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L
3720#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008
3721#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L
3722#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010
3723#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L
3724#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018
3725#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L
3726#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a
3727#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L
3728#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c
3729#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L
3730#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000
3731#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L
3732#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001
3733#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L
3734#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000
3735#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L
3736#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001
3737#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L
3738#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000
3739#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L
3740#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001
3741#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L
3742#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002
3743#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L
3744#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004
3745#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L
3746#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005
3747#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L
3748#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006
3749#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL
3750#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000
3751#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L
3752#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004
3753#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L
3754#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000
3755#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L
3756#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001
3757#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL
3758#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000
3759#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L
3760#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004
3761#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L
3762#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018
3763#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L
3764#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c
3765#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L
3766#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010
3767#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L
3768#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014
3769#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL
3770#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000
3771#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L
3772#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004
3773#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L
3774#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000
3775#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L
3776#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008
3777#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L
3778#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010
3779#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L
3780#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000
3781#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L
3782#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008
3783#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L
3784#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010
3785#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L
3786#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001
3787#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L
3788#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000
3789#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L
3790#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004
3791#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L
3792#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006
3793#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L
3794#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008
3795#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L
3796#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c
3797#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L
3798#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e
3799#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L
3800#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010
3801#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L
3802#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014
3803#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L
3804#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016
3805#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L
3806#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000
3807#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L
3808#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008
3809#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L
3810#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010
3811#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L
3812#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000
3813#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L
3814#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008
3815#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L
3816#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000
3817#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L
3818#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008
3819#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L
3820#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018
3821#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L
3822#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000
3823#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L
3824#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004
3825#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L
3826#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006
3827#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L
3828#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c
3829#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L
3830#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008
3831#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L
3832#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c
3833#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L
3834#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e
3835#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L
3836#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000
3837#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L
3838#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008
3839#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL
3840#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000
3841#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L
3842#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008
3843#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L
3844#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b
3845#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L
3846#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e
3847#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L
3848#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011
3849#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L
3850#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014
3851#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L
3852#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017
3853#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL
3854#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000
3855#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L
3856#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000
3857#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L
3858#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004
3859#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L
3860#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008
3861#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L
3862#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c
3863#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L
3864#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010
3865#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L
3866#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014
3867#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L
3868#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000
3869#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L
3870#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004
3871#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L
3872#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008
3873#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L
3874#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c
3875#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L
3876#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010
3877#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L
3878#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014
3879#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL
3880#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000
3881#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L
3882#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c
3883#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L
3884#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010
3885#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL
3886#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000
3887#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L
3888#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018
3889#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L
3890#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c
3891#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
3892#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c
3893#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L
3894#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000
3895#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L
3896#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010
3897#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L
3898#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008
3899#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L
3900#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014
3901#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L
3902#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018
3903#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L
3904#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000
3905#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L
3906#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008
3907#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L
3908#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004
3909#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L
3910#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001
3911#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L
3912#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c
3913#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L
3914#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018
3915#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL
3916#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000
3917#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L
3918#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014
3919#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL
3920#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000
3921#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L
3922#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c
3923#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L
3924#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010
3925#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL
3926#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000
3927#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L
3928#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018
3929#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L
3930#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c
3931#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
3932#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c
3933#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L
3934#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000
3935#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L
3936#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010
3937#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L
3938#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008
3939#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L
3940#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014
3941#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L
3942#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018
3943#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L
3944#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000
3945#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L
3946#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008
3947#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L
3948#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004
3949#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L
3950#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001
3951#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L
3952#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c
3953#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L
3954#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018
3955#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL
3956#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000
3957#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L
3958#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014
3959#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL
3960#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000
3961#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L
3962#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c
3963#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L
3964#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010
3965#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL
3966#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000
3967#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L
3968#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018
3969#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L
3970#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c
3971#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
3972#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c
3973#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L
3974#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000
3975#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L
3976#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010
3977#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L
3978#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008
3979#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L
3980#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014
3981#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L
3982#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018
3983#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L
3984#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000
3985#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L
3986#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008
3987#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L
3988#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004
3989#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L
3990#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001
3991#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L
3992#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c
3993#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L
3994#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018
3995#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL
3996#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000
3997#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L
3998#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014
3999#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL
4000#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000
4001#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L
4002#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c
4003#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L
4004#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010
4005#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL
4006#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000
4007#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L
4008#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018
4009#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L
4010#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c
4011#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
4012#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c
4013#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L
4014#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000
4015#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L
4016#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010
4017#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L
4018#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008
4019#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L
4020#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014
4021#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L
4022#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018
4023#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L
4024#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000
4025#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L
4026#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008
4027#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L
4028#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004
4029#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L
4030#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001
4031#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L
4032#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c
4033#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L
4034#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018
4035#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL
4036#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000
4037#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L
4038#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014
4039#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL
4040#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000
4041#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L
4042#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c
4043#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L
4044#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010
4045#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL
4046#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000
4047#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L
4048#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018
4049#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L
4050#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c
4051#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
4052#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c
4053#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L
4054#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000
4055#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L
4056#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010
4057#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L
4058#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008
4059#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L
4060#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014
4061#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L
4062#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018
4063#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L
4064#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000
4065#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L
4066#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008
4067#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L
4068#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004
4069#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L
4070#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001
4071#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L
4072#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c
4073#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L
4074#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018
4075#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL
4076#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000
4077#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L
4078#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014
4079#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL
4080#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000
4081#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L
4082#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c
4083#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L
4084#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010
4085#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL
4086#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000
4087#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L
4088#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018
4089#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L
4090#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c
4091#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L
4092#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c
4093#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L
4094#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000
4095#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L
4096#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010
4097#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L
4098#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008
4099#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L
4100#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014
4101#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L
4102#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018
4103#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L
4104#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000
4105#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L
4106#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008
4107#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L
4108#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004
4109#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L
4110#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001
4111#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L
4112#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c
4113#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L
4114#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018
4115#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL
4116#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000
4117#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L
4118#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014
4119#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L
4120#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008
4121#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L
4122#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c
4123#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L
4124#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019
4125#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L
4126#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018
4127#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L
4128#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004
4129#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL
4130#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002
4131#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L
4132#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015
4133#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L
4134#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000
4135#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L
4136#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014
4137#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L
4138#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f
4139#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L
4140#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008
4141#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L
4142#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000
4143#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L
4144#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002
4145#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L
4146#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001
4147#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L
4148#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003
4149#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L
4150#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014
4151#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L
4152#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L
4153#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000
4154#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008
4155#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L
4156#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010
4157#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L
4158#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f
4159#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4160#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4161#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L
4162#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c
4163#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L
4164#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014
4165#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L
4166#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003
4167#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L
4168#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010
4169#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L
4170#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000
4171#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L
4172#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011
4173#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L
4174#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007
4175#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L
4176#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000
4177#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L
4178#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001
4179#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L
4180#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004
4181#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L
4182#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005
4183#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L
4184#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006
4185#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4186#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008
4187#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4188#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4189#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L
4190#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018
4191#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4192#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4193#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L
4194#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010
4195#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L
4196#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000
4197#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4198#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4199#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L
4200#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c
4201#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L
4202#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014
4203#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L
4204#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003
4205#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L
4206#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010
4207#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L
4208#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000
4209#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L
4210#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011
4211#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L
4212#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007
4213#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L
4214#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000
4215#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L
4216#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001
4217#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L
4218#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004
4219#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L
4220#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005
4221#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L
4222#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006
4223#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4224#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008
4225#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4226#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4227#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L
4228#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018
4229#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4230#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4231#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L
4232#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010
4233#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L
4234#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000
4235#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4236#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4237#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L
4238#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c
4239#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L
4240#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014
4241#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L
4242#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003
4243#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L
4244#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010
4245#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L
4246#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000
4247#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L
4248#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011
4249#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L
4250#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007
4251#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L
4252#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000
4253#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L
4254#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001
4255#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L
4256#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004
4257#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L
4258#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005
4259#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L
4260#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006
4261#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4262#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008
4263#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4264#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4265#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L
4266#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018
4267#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4268#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4269#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L
4270#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010
4271#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L
4272#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000
4273#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4274#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4275#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L
4276#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c
4277#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L
4278#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014
4279#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L
4280#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003
4281#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L
4282#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010
4283#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L
4284#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000
4285#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L
4286#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011
4287#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L
4288#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007
4289#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L
4290#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000
4291#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L
4292#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001
4293#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L
4294#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004
4295#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L
4296#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005
4297#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L
4298#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006
4299#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4300#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008
4301#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4302#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4303#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L
4304#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018
4305#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4306#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4307#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L
4308#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010
4309#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L
4310#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000
4311#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4312#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4313#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L
4314#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c
4315#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L
4316#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014
4317#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L
4318#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003
4319#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L
4320#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010
4321#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L
4322#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000
4323#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L
4324#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011
4325#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L
4326#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007
4327#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L
4328#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000
4329#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L
4330#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001
4331#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L
4332#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004
4333#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L
4334#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005
4335#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L
4336#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006
4337#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4338#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008
4339#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4340#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4341#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L
4342#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018
4343#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4344#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4345#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L
4346#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010
4347#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L
4348#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000
4349#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4350#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4351#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L
4352#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c
4353#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L
4354#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014
4355#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L
4356#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003
4357#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L
4358#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010
4359#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L
4360#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000
4361#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L
4362#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011
4363#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L
4364#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007
4365#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L
4366#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000
4367#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L
4368#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001
4369#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L
4370#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004
4371#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L
4372#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005
4373#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L
4374#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006
4375#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4376#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008
4377#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4378#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4379#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L
4380#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018
4381#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4382#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4383#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L
4384#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010
4385#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L
4386#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000
4387#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L
4388#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018
4389#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L
4390#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c
4391#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L
4392#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014
4393#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L
4394#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003
4395#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L
4396#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010
4397#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L
4398#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000
4399#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L
4400#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011
4401#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L
4402#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007
4403#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L
4404#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000
4405#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L
4406#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001
4407#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L
4408#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004
4409#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L
4410#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005
4411#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L
4412#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006
4413#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L
4414#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008
4415#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L
4416#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010
4417#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L
4418#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018
4419#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
4420#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
4421#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L
4422#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010
4423#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L
4424#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000
4425#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L
4426#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014
4427#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L
4428#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c
4429#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL
4430#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000
4431#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L
4432#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005
4433#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L
4434#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004
4435#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L
4436#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006
4437#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L
4438#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009
4439#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L
4440#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008
4441#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L
4442#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a
4443#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L
4444#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d
4445#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L
4446#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c
4447#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L
4448#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e
4449#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L
4450#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011
4451#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L
4452#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010
4453#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L
4454#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012
4455#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L
4456#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015
4457#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L
4458#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014
4459#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L
4460#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016
4461#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L
4462#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019
4463#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L
4464#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018
4465#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L
4466#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a
4467#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L
4468#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c
4469#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L
4470#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b
4471#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L
4472#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d
4473#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L
4474#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001
4475#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L
4476#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000
4477#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L
4478#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002
4479#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L
4480#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004
4481#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L
4482#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007
4483#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L
4484#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002
4485#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L
4486#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006
4487#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L
4488#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c
4489#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L
4490#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d
4491#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L
4492#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e
4493#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L
4494#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f
4495#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L
4496#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012
4497#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L
4498#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000
4499#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L
4500#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008
4501#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L
4502#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005
4503#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L
4504#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010
4505#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L
4506#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000
4507#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L
4508#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c
4509#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L
4510#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d
4511#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L
4512#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008
4513#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L
4514#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010
4515#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L
4516#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000
4517#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L
4518#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c
4519#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L
4520#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d
4521#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L
4522#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008
4523#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L
4524#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010
4525#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L
4526#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000
4527#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L
4528#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c
4529#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L
4530#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d
4531#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L
4532#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008
4533#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L
4534#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010
4535#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L
4536#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000
4537#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L
4538#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c
4539#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L
4540#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d
4541#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L
4542#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008
4543#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L
4544#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b
4545#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL
4546#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000
4547#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L
4548#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f
4549#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L
4550#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010
4551#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L
4552#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011
4553#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L
4554#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012
4555#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L
4556#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013
4557#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L
4558#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014
4559#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L
4560#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015
4561#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L
4562#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009
4563#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L
4564#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b
4565#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L
4566#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d
4567#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L
4568#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006
4569#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L
4570#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005
4571#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L
4572#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e
4573#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L
4574#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a
4575#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L
4576#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c
4577#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L
4578#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016
4579#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L
4580#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017
4581#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L
4582#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008
4583#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL
4584#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000
4585#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L
4586#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000
4587#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L
4588#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c
4589#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L
4590#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006
4591#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L
4592#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001
4593#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L
4594#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e
4595#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L
4596#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007
4597#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L
4598#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002
4599#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L
4600#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010
4601#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L
4602#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008
4603#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L
4604#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003
4605#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L
4606#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012
4607#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L
4608#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009
4609#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L
4610#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004
4611#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L
4612#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014
4613#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L
4614#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a
4615#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L
4616#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005
4617#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L
4618#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016
4619#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L
4620#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b
4621#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L
4622#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000
4623#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL
4624#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002
4625#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L
4626#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004
4627#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L
4628#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016
4629#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L
4630#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c
4631#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L
4632#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000
4633#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL
4634#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002
4635#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L
4636#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004
4637#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L
4638#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006
4639#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L
4640#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008
4641#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L
4642#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a
4643#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L
4644#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c
4645#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L
4646#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a
4647#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L
4648#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018
4649#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L
4650#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010
4651#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L
4652#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012
4653#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L
4654#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e
4655#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L
4656#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014
4657#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL
4658#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000
4659#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL
4660#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000
4661#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL
4662#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000
4663#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL
4664#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000
4665#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L
4666#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012
4667#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L
4668#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L
4669#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e
4670#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L
4671#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d
4672#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f
4673#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L
4674#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L
4675#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013
4676#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L
4677#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010
4678#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014
4679#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L
4680#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016
4681#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L
4682#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015
4683#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L
4684#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L
4685#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a
4686#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b
4687#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L
4688#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017
4689#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L
4690#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011
4691#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L
4692#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019
4693#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L
4694#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018
4695#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L
4696#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c
4697#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L
4698#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L
4699#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000
4700#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006
4701#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L
4702#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L
4703#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004
4704#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a
4705#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL
4706#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002
4707#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L
4708#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008
4709#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL
4710#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000
4711#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL
4712#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000
4713#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL
4714#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000
4715#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL
4716#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000
4717#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL
4718#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000
4719#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL
4720#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000
4721#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL
4722#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000
4723#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL
4724#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000
4725#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL
4726#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000
4727#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL
4728#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000
4729#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL
4730#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000
4731#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL
4732#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000
4733#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL
4734#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000
4735#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL
4736#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000
4737#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL
4738#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000
4739#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL
4740#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000
4741#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
4742#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010
4743#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L
4744#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008
4745#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L
4746#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000
4747#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
4748#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010
4749#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L
4750#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008
4751#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L
4752#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000
4753#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L
4754#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010
4755#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L
4756#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008
4757#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L
4758#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000
4759#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
4760#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004
4761#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L
4762#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008
4763#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
4764#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000
4765#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
4766#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014
4767#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L
4768#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018
4769#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
4770#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010
4771#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L
4772#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004
4773#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L
4774#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008
4775#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L
4776#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000
4777#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L
4778#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014
4779#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L
4780#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018
4781#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L
4782#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010
4783#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL
4784#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000
4785#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L
4786#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c
4787#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L
4788#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005
4789#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L
4790#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008
4791#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL
4792#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000
4793#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L
4794#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c
4795#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L
4796#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005
4797#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L
4798#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008
4799#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL
4800#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000
4801#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L
4802#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c
4803#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L
4804#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005
4805#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L
4806#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008
4807#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL
4808#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000
4809#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL
4810#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000
4811#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
4812#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
4813#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L
4814#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004
4815#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L
4816#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005
4817#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L
4818#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006
4819#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L
4820#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007
4821#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L
4822#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008
4823#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L
4824#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009
4825#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L
4826#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c
4827#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L
4828#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003
4829#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L
4830#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002
4831#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L
4832#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000
4833#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L
4834#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001
4835#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL
4836#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000
4837#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL
4838#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000
4839#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
4840#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
4841#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL
4842#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000
4843#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L
4844#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a
4845#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L
4846#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014
4847#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L
4848#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001
4849#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L
4850#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000
4851#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL
4852#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000
4853#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL
4854#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000
4855#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL
4856#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000
4857#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L
4858#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005
4859#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L
4860#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006
4861#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L
4862#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004
4863#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L
4864#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d
4865#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L
4866#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e
4867#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L
4868#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c
4869#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L
4870#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015
4871#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L
4872#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016
4873#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L
4874#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014
4875#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL
4876#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000
4877#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L
4878#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008
4879#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L
4880#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010
4881#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL
4882#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000
4883#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L
4884#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010
4885#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL
4886#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000
4887#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L
4888#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000
4889#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL
4890#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000
4891#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L
4892#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000
4893#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL
4894#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000
4895#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL
4896#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000
4897#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL
4898#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000
4899#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L
4900#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000
4901#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L
4902#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f
4903#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L
4904#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c
4905#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L
4906#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c
4907#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L
4908#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010
4909#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L
4910#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008
4911#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L
4912#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014
4913#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L
4914#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000
4915#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL
4916#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000
4917#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L
4918#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006
4919#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L
4920#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008
4921#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L
4922#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009
4923#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L
4924#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018
4925#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L
4926#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019
4927#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L
4928#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a
4929#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L
4930#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b
4931#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L
4932#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c
4933#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L
4934#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d
4935#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L
4936#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007
4937#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L
4938#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010
4939#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L
4940#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011
4941#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L
4942#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012
4943#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L
4944#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013
4945#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L
4946#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014
4947#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L
4948#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015
4949#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L
4950#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c
4951#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L
4952#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005
4953#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L
4954#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006
4955#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L
4956#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008
4957#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L
4958#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009
4959#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L
4960#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018
4961#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L
4962#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019
4963#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L
4964#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a
4965#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L
4966#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b
4967#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L
4968#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c
4969#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L
4970#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d
4971#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L
4972#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007
4973#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L
4974#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010
4975#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L
4976#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011
4977#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L
4978#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012
4979#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L
4980#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013
4981#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L
4982#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014
4983#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L
4984#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015
4985#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L
4986#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c
4987#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L
4988#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005
4989#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L
4990#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003
4991#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L
4992#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011
4993#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L
4994#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004
4995#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L
4996#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012
4997#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L
4998#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005
4999#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L
5000#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013
5001#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L
5002#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006
5003#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L
5004#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014
5005#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L
5006#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007
5007#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L
5008#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015
5009#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L
5010#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008
5011#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L
5012#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016
5013#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L
5014#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009
5015#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L
5016#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a
5017#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L
5018#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b
5019#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L
5020#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c
5021#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L
5022#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d
5023#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L
5024#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e
5025#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L
5026#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001
5027#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L
5028#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002
5029#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L
5030#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010
5031#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L
5032#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000
5033#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L
5034#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006
5035#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L
5036#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008
5037#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L
5038#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a
5039#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L
5040#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c
5041#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L
5042#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e
5043#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L
5044#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010
5045#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L
5046#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012
5047#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L
5048#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014
5049#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L
5050#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016
5051#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L
5052#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018
5053#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L
5054#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a
5055#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L
5056#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c
5057#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL
5058#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002
5059#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L
5060#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004
5061#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L
5062#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000
5063#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L
5064#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019
5065#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L
5066#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d
5067#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L
5068#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000
5069#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L
5070#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001
5071#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L
5072#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003
5073#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L
5074#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b
5075#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L
5076#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010
5077#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L
5078#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011
5079#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L
5080#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012
5081#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L
5082#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013
5083#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L
5084#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014
5085#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L
5086#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015
5087#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L
5088#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018
5089#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L
5090#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002
5091#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L
5092#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c
5093#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L
5094#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a
5095#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL
5096#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000
5097#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L
5098#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004
5099#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L
5100#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000
5101#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L
5102#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008
5103#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL
5104#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002
5105#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL
5106#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000
5107#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL
5108#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000
5109#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL
5110#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000
5111#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL
5112#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000
5113#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL
5114#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000
5115#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL
5116#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000
5117#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L
5118#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014
5119#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L
5120#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010
5121#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L
5122#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002
5123#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L
5124#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000
5125#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L
5126#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001
5127#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL
5128#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000
5129#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL
5130#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000
5131#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L
5132#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000
5133#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L
5134#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001
5135#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L
5136#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002
5137#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L
5138#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b
5139#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L
5140#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c
5141#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L
5142#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c
5143#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L
5144#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010
5145#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L
5146#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008
5147#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L
5148#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018
5149#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL
5150#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000
5151#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL
5152#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000
5153#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
5154#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
5155#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L
5156#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e
5157#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L
5158#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a
5159#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L
5160#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010
5161#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L
5162#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d
5163#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L
5164#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b
5165#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL
5166#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000
5167#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L
5168#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004
5169#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L
5170#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010
5171#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L
5172#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008
5173#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL
5174#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000
5175#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L
5176#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008
5177#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L
5178#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a
5179#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L
5180#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009
5181#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L
5182#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006
5183#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L
5184#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000
5185#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L
5186#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004
5187#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL
5188#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000
5189#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL
5190#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000
5191#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
5192#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
5193#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L
5194#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000
5195#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L
5196#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003
5197#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L
5198#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004
5199#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L
5200#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007
5201#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L
5202#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008
5203#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L
5204#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b
5205#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L
5206#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c
5207#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L
5208#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f
5209#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L
5210#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010
5211#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L
5212#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013
5213#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L
5214#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000
5215#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L
5216#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003
5217#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L
5218#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004
5219#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L
5220#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007
5221#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L
5222#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008
5223#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L
5224#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000
5225#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L
5226#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016
5227#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L
5228#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010
5229#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L
5230#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014
5231#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL
5232#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000
5233#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L
5234#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008
5235#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L
5236#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015
5237#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L
5238#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c
5239#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L
5240#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000
5241#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L
5242#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004
5243#define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L
5244#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000
5245#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
5246#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013
5247#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L
5248#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f
5249#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L
5250#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011
5251#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L
5252#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012
5253#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L
5254#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008
5255#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL
5256#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000
5257#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L
5258#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014
5259#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L
5260#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015
5261#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L
5262#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016
5263#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L
5264#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018
5265#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L
5266#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008
5267#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L
5268#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c
5269#define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L
5270#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010
5271#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L
5272#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000
5273#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L
5274#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008
5275#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL
5276#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000
5277#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L
5278#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000
5279#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L
5280#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008
5281#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L
5282#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L
5283#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c
5284#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004
5285#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L
5286#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000
5287#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L
5288#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010
5289#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L
5290#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014
5291#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L
5292#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000
5293#define DIG_FE_CNTL__DIG_START_MASK 0x00000400L
5294#define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a
5295#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L
5296#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008
5297#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L
5298#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004
5299#define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L
5300#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012
5301#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L
5302#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018
5303#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L
5304#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a
5305#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L
5306#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d
5307#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L
5308#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008
5309#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
5310#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e
5311#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
5312#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f
5313#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L
5314#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000
5315#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L
5316#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010
5317#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L
5318#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016
5319#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL
5320#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002
5321#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
5322#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001
5323#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L
5324#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008
5325#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L
5326#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000
5327#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L
5328#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001
5329#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L
5330#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002
5331#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L
5332#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003
5333#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L
5334#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008
5335#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L
5336#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000
5337#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L
5338#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004
5339#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL
5340#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000
5341#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL
5342#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000
5343#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L
5344#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018
5345#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L
5346#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001
5347#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L
5348#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000
5349#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L
5350#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005
5351#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L
5352#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004
5353#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L
5354#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009
5355#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L
5356#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008
5357#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L
5358#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d
5359#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L
5360#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c
5361#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L
5362#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011
5363#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L
5364#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010
5365#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L
5366#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015
5367#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L
5368#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014
5369#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L
5370#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001
5371#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L
5372#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004
5373#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L
5374#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005
5375#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L
5376#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010
5377#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L
5378#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006
5379#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L
5380#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000
5381#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L
5382#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008
5383#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L
5384#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002
5385#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L
5386#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004
5387#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL
5388#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000
5389#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L
5390#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e
5391#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L
5392#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c
5393#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L
5394#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d
5395#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L
5396#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f
5397#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L
5398#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014
5399#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L
5400#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019
5401#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL
5402#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000
5403#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L
5404#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010
5405#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L
5406#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e
5407#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L
5408#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c
5409#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L
5410#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d
5411#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L
5412#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014
5413#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L
5414#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013
5415#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L
5416#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014
5417#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L
5418#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013
5419#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
5420#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006
5421#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
5422#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005
5423#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
5424#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a
5425#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L
5426#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004
5427#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L
5428#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007
5429#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L
5430#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008
5431#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
5432#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009
5433#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L
5434#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011
5435#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L
5436#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012
5437#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
5438#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f
5439#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
5440#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010
5441#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L
5442#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f
5443#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L
5444#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003
5445#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L
5446#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002
5447#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
5448#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000
5449#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L
5450#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014
5451#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L
5452#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013
5453#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
5454#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006
5455#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
5456#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005
5457#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
5458#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a
5459#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L
5460#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004
5461#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L
5462#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007
5463#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L
5464#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008
5465#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
5466#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009
5467#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L
5468#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011
5469#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L
5470#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012
5471#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
5472#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f
5473#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
5474#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010
5475#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L
5476#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f
5477#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L
5478#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003
5479#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L
5480#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002
5481#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
5482#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000
5483#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L
5484#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014
5485#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L
5486#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013
5487#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
5488#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006
5489#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
5490#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005
5491#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
5492#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a
5493#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L
5494#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004
5495#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L
5496#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007
5497#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L
5498#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008
5499#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
5500#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009
5501#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L
5502#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011
5503#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L
5504#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012
5505#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
5506#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f
5507#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
5508#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010
5509#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L
5510#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f
5511#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L
5512#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003
5513#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L
5514#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002
5515#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
5516#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000
5517#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L
5518#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014
5519#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L
5520#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013
5521#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
5522#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006
5523#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
5524#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005
5525#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
5526#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a
5527#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L
5528#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004
5529#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L
5530#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007
5531#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L
5532#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008
5533#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
5534#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009
5535#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L
5536#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011
5537#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L
5538#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012
5539#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
5540#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f
5541#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
5542#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010
5543#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L
5544#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003
5545#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L
5546#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002
5547#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
5548#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000
5549#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L
5550#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014
5551#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L
5552#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013
5553#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
5554#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006
5555#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
5556#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005
5557#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
5558#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a
5559#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L
5560#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004
5561#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L
5562#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007
5563#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L
5564#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008
5565#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
5566#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009
5567#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L
5568#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011
5569#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L
5570#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012
5571#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
5572#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f
5573#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
5574#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010
5575#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L
5576#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f
5577#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L
5578#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018
5579#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L
5580#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003
5581#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L
5582#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002
5583#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
5584#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000
5585#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L
5586#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006
5587#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L
5588#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005
5589#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L
5590#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a
5591#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L
5592#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004
5593#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L
5594#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007
5595#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L
5596#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008
5597#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L
5598#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009
5599#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L
5600#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016
5601#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L
5602#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017
5603#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L
5604#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011
5605#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L
5606#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012
5607#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L
5608#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019
5609#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L
5610#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018
5611#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L
5612#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015
5613#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L
5614#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f
5615#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L
5616#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010
5617#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L
5618#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f
5619#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L
5620#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b
5621#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L
5622#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a
5623#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L
5624#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003
5625#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L
5626#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002
5627#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L
5628#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000
5629#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L
5630#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000
5631#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L
5632#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010
5633#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L
5634#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004
5635#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L
5636#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000
5637#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL
5638#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000
5639#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
5640#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019
5641#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L
5642#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L
5643#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b
5644#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L
5645#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a
5646#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e
5647#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L
5648#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d
5649#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L
5650#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c
5651#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L
5652#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002
5653#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L
5654#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003
5655#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L
5656#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004
5657#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L
5658#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001
5659#define DMCU_CTRL__RESET_UC_MASK 0x00000001L
5660#define DMCU_CTRL__RESET_UC__SHIFT 0x00000000
5661#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L
5662#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016
5663#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL
5664#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000
5665#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L
5666#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010
5667#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L
5668#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014
5669#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL
5670#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000
5671#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL
5672#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000
5673#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L
5674#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010
5675#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L
5676#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014
5677#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL
5678#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000
5679#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L
5680#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000
5681#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L
5682#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017
5683#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L
5684#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010
5685#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL
5686#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002
5687#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L
5688#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000
5689#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL
5690#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000
5691#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL
5692#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000
5693#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL
5694#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000
5695#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L
5696#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008
5697#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL
5698#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000
5699#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L
5700#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008
5701#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL
5702#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000
5703#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L
5704#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008
5705#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L
5706#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010
5707#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL
5708#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000
5709#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L
5710#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008
5711#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L
5712#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002
5713#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L
5714#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002
5715#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L
5716#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000
5717#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L
5718#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000
5719#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L
5720#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001
5721#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L
5722#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001
5723#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L
5724#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012
5725#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L
5726#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012
5727#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L
5728#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c
5729#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L
5730#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c
5731#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L
5732#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013
5733#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L
5734#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013
5735#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L
5736#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d
5737#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L
5738#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d
5739#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L
5740#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014
5741#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L
5742#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014
5743#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L
5744#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e
5745#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L
5746#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e
5747#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L
5748#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015
5749#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L
5750#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015
5751#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L
5752#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f
5753#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L
5754#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f
5755#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L
5756#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016
5757#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L
5758#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016
5759#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L
5760#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010
5761#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L
5762#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010
5763#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L
5764#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017
5765#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L
5766#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017
5767#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L
5768#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011
5769#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L
5770#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011
5771#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L
5772#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008
5773#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L
5774#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008
5775#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L
5776#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003
5777#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L
5778#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009
5779#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L
5780#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a
5781#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L
5782#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a
5783#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L
5784#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b
5785#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L
5786#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b
5787#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L
5788#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018
5789#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L
5790#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018
5791#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L
5792#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019
5793#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L
5794#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019
5795#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L
5796#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a
5797#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L
5798#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a
5799#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L
5800#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b
5801#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L
5802#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b
5803#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L
5804#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c
5805#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L
5806#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c
5807#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L
5808#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d
5809#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L
5810#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d
5811#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L
5812#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002
5813#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L
5814#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000
5815#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L
5816#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001
5817#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L
5818#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012
5819#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L
5820#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c
5821#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L
5822#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013
5823#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L
5824#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d
5825#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L
5826#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014
5827#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L
5828#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e
5829#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L
5830#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015
5831#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L
5832#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f
5833#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L
5834#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016
5835#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L
5836#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010
5837#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L
5838#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017
5839#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L
5840#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011
5841#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L
5842#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009
5843#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L
5844#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a
5845#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L
5846#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b
5847#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L
5848#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002
5849#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L
5850#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000
5851#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L
5852#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001
5853#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L
5854#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012
5855#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L
5856#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c
5857#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L
5858#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013
5859#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L
5860#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d
5861#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L
5862#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014
5863#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L
5864#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e
5865#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L
5866#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015
5867#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L
5868#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f
5869#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L
5870#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016
5871#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L
5872#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010
5873#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L
5874#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017
5875#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L
5876#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011
5877#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L
5878#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008
5879#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L
5880#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003
5881#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L
5882#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018
5883#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L
5884#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019
5885#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L
5886#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a
5887#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L
5888#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b
5889#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L
5890#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c
5891#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L
5892#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d
5893#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L
5894#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002
5895#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L
5896#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000
5897#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L
5898#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001
5899#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L
5900#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012
5901#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L
5902#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c
5903#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L
5904#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013
5905#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L
5906#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d
5907#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L
5908#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014
5909#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L
5910#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e
5911#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L
5912#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015
5913#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L
5914#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f
5915#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L
5916#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016
5917#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L
5918#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010
5919#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L
5920#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017
5921#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L
5922#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011
5923#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L
5924#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008
5925#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L
5926#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003
5927#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L
5928#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018
5929#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L
5930#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019
5931#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L
5932#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a
5933#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L
5934#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b
5935#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L
5936#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c
5937#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L
5938#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d
5939#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL
5940#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000
5941#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL
5942#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000
5943#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL
5944#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000
5945#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL
5946#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000
5947#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL
5948#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000
5949#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L
5950#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008
5951#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L
5952#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004
5953#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L
5954#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001
5955#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L
5956#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000
5957#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L
5958#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005
5959#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L
5960#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003
5961#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L
5962#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002
5963#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L
5964#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008
5965#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L
5966#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000
5967#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L
5968#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002
5969#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L
5970#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001
5971#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL
5972#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000
5973#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL
5974#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000
5975#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
5976#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
5977#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L
5978#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008
5979#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L
5980#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000
5981#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L
5982#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010
5983#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L
5984#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003
5985#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L
5986#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000
5987#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L
5988#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e
5989#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L
5990#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f
5991#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L
5992#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009
5993#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L
5994#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002
5995#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L
5996#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d
5997#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L
5998#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c
5999#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L
6000#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b
6001#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L
6002#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a
6003#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L
6004#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007
6005#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L
6006#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006
6007#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L
6008#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005
6009#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L
6010#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004
6011#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L
6012#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008
6013#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L
6014#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001
6015#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
6016#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
6017#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L
6018#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c
6019#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
6020#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
6021#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
6022#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
6023#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
6024#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
6025#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
6026#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
6027#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
6028#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
6029#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
6030#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
6031#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
6032#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
6033#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL
6034#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000
6035#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L
6036#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010
6037#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L
6038#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000
6039#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L
6040#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d
6041#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L
6042#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018
6043#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L
6044#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004
6045#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L
6046#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c
6047#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L
6048#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002
6049#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L
6050#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010
6051#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L
6052#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008
6053#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL
6054#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000
6055#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L
6056#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010
6057#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L
6058#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011
6059#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL
6060#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000
6061#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L
6062#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010
6063#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L
6064#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011
6065#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL
6066#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000
6067#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L
6068#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008
6069#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L
6070#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009
6071#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L
6072#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000
6073#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L
6074#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001
6075#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L
6076#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002
6077#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L
6078#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003
6079#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L
6080#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004
6081#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L
6082#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005
6083#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L
6084#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008
6085#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L
6086#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010
6087#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L
6088#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014
6089#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L
6090#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011
6091#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL
6092#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000
6093#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L
6094#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018
6095#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L
6096#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c
6097#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL
6098#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000
6099#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL
6100#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000
6101#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
6102#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
6103#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L
6104#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004
6105#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L
6106#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000
6107#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L
6108#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008
6109#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L
6110#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000
6111#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL
6112#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000
6113#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL
6114#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000
6115#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL
6116#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000
6117#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL
6118#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000
6119#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL
6120#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000
6121#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL
6122#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000
6123#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL
6124#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000
6125#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL
6126#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000
6127#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL
6128#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000
6129#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL
6130#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000
6131#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
6132#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
6133#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL
6134#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000
6135#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL
6136#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000
6137#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL
6138#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000
6139#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL
6140#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000
6141#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL
6142#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000
6143#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL
6144#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000
6145#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL
6146#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000
6147#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL
6148#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000
6149#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL
6150#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000
6151#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL
6152#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000
6153#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL
6154#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000
6155#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL
6156#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000
6157#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL
6158#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000
6159#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL
6160#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000
6161#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL
6162#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000
6163#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL
6164#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000
6165#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL
6166#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000
6167#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL
6168#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000
6169#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL
6170#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000
6171#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL
6172#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000
6173#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL
6174#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000
6175#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL
6176#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000
6177#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL
6178#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000
6179#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL
6180#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000
6181#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL
6182#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000
6183#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL
6184#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000
6185#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL
6186#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000
6187#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL
6188#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000
6189#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL
6190#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000
6191#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL
6192#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000
6193#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL
6194#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000
6195#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL
6196#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000
6197#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL
6198#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000
6199#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL
6200#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000
6201#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL
6202#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000
6203#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL
6204#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000
6205#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL
6206#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000
6207#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL
6208#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000
6209#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL
6210#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000
6211#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL
6212#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000
6213#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL
6214#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000
6215#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL
6216#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000
6217#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL
6218#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000
6219#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL
6220#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000
6221#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL
6222#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000
6223#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL
6224#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000
6225#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL
6226#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000
6227#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL
6228#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000
6229#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL
6230#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000
6231#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL
6232#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000
6233#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL
6234#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000
6235#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL
6236#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000
6237#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL
6238#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000
6239#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL
6240#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000
6241#define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L
6242#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000
6243#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L
6244#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018
6245#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L
6246#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010
6247#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L
6248#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008
6249#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L
6250#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000
6251#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L
6252#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001
6253#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L
6254#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002
6255#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L
6256#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003
6257#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L
6258#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010
6259#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L
6260#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018
6261#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L
6262#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000
6263#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L
6264#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010
6265#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L
6266#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004
6267#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L
6268#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004
6269#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L
6270#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000
6271#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L
6272#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008
6273#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL
6274#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000
6275#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L
6276#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008
6277#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L
6278#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010
6279#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L
6280#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008
6281#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L
6282#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000
6283#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L
6284#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008
6285#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L
6286#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010
6287#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L
6288#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018
6289#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL
6290#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000
6291#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L
6292#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008
6293#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L
6294#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014
6295#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L
6296#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002
6297#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L
6298#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000
6299#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L
6300#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001
6301#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L
6302#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c
6303#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L
6304#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008
6305#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L
6306#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004
6307#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L
6308#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000
6309#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L
6310#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000
6311#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L
6312#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008
6313#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L
6314#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004
6315#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL
6316#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000
6317#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L
6318#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a
6319#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L
6320#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014
6321#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL
6322#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000
6323#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L
6324#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a
6325#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L
6326#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014
6327#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL
6328#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000
6329#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L
6330#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a
6331#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L
6332#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000
6333#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL
6334#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000
6335#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL
6336#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000
6337#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL
6338#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000
6339#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL
6340#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000
6341#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL
6342#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000
6343#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL
6344#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000
6345#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL
6346#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000
6347#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL
6348#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000
6349#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL
6350#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000
6351#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL
6352#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000
6353#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL
6354#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000
6355#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL
6356#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000
6357#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L
6358#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010
6359#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL
6360#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000
6361#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL
6362#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000
6363#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L
6364#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010
6365#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
6366#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000
6367#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L
6368#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004
6369#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L
6370#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008
6371#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L
6372#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L
6373#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c
6374#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010
6375#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L
6376#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a
6377#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L
6378#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000
6379#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L
6380#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009
6381#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L
6382#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008
6383#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
6384#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004
6385#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L
6386#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010
6387#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
6388#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000
6389#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L
6390#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004
6391#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L
6392#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007
6393#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L
6394#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005
6395#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L
6396#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006
6397#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L
6398#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b
6399#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L
6400#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a
6401#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L
6402#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009
6403#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L
6404#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008
6405#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
6406#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000
6407#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L
6408#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010
6409#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
6410#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004
6411#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L
6412#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007
6413#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L
6414#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005
6415#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L
6416#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006
6417#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L
6418#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b
6419#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L
6420#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a
6421#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L
6422#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009
6423#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L
6424#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008
6425#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L
6426#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010
6427#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL
6428#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000
6429#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL
6430#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000
6431#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL
6432#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000
6433#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
6434#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
6435#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L
6436#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000
6437#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L
6438#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011
6439#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L
6440#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008
6441#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L
6442#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004
6443#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL
6444#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000
6445#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L
6446#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018
6447#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L
6448#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c
6449#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L
6450#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008
6451#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL
6452#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000
6453#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L
6454#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003
6455#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L
6456#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008
6457#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L
6458#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010
6459#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L
6460#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018
6461#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L
6462#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000
6463#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L
6464#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004
6465#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L
6466#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010
6467#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL
6468#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000
6469#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL
6470#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000
6471#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L
6472#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010
6473#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L
6474#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000
6475#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L
6476#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004
6477#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L
6478#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008
6479#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L
6480#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a
6481#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL
6482#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000
6483#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L
6484#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000
6485#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L
6486#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008
6487#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L
6488#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018
6489#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L
6490#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000
6491#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L
6492#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010
6493#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L
6494#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008
6495#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L
6496#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018
6497#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L
6498#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000
6499#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L
6500#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010
6501#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L
6502#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008
6503#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L
6504#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018
6505#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L
6506#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000
6507#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L
6508#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010
6509#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L
6510#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008
6511#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L
6512#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000
6513#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L
6514#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018
6515#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L
6516#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008
6517#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L
6518#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000
6519#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L
6520#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010
6521#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL
6522#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000
6523#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL
6524#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000
6525#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL
6526#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000
6527#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL
6528#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000
6529#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L
6530#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000
6531#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L
6532#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010
6533#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L
6534#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c
6535#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L
6536#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004
6537#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L
6538#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008
6539#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L
6540#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018
6541#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L
6542#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014
6543#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L
6544#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015
6545#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L
6546#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016
6547#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L
6548#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017
6549#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L
6550#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c
6551#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L
6552#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000
6553#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL
6554#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000
6555#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L
6556#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010
6557#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L
6558#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010
6559#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL
6560#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000
6561#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL
6562#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000
6563#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L
6564#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010
6565#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L
6566#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c
6567#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L
6568#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d
6569#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L
6570#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018
6571#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L
6572#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014
6573#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L
6574#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010
6575#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL
6576#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001
6577#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L
6578#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004
6579#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L
6580#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008
6581#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L
6582#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000
6583#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L
6584#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000
6585#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L
6586#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006
6587#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L
6588#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004
6589#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L
6590#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005
6591#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L
6592#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007
6593#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L
6594#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c
6595#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L
6596#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008
6597#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL
6598#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000
6599#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL
6600#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000
6601#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
6602#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
6603#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L
6604#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001
6605#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L
6606#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000
6607#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L
6608#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002
6609#define DP_VID_M__DP_VID_M_MASK 0x00ffffffL
6610#define DP_VID_M__DP_VID_M__SHIFT 0x00000000
6611#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL
6612#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000
6613#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L
6614#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010
6615#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L
6616#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018
6617#define DP_VID_N__DP_VID_N_MASK 0x00ffffffL
6618#define DP_VID_N__DP_VID_N__SHIFT 0x00000000
6619#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L
6620#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014
6621#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L
6622#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008
6623#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L
6624#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000
6625#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L
6626#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010
6627#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L
6628#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008
6629#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L
6630#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018
6631#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L
6632#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000
6633#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L
6634#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011
6635#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L
6636#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008
6637#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L
6638#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010
6639#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L
6640#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000
6641#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L
6642#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012
6643#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L
6644#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011
6645#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L
6646#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008
6647#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L
6648#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010
6649#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L
6650#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000
6651#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L
6652#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012
6653#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L
6654#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014
6655#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L
6656#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018
6657#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L
6658#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c
6659#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L
6660#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011
6661#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L
6662#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008
6663#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L
6664#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010
6665#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L
6666#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000
6667#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L
6668#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012
6669#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L
6670#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000
6671#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L
6672#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018
6673#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L
6674#define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f
6675#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L
6676#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008
6677#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L
6678#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012
6679#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L
6680#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000
6681#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L
6682#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010
6683#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L
6684#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001
6685#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L
6686#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011
6687#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL
6688#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000
6689#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL
6690#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000
6691#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L
6692#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010
6693#define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L
6694#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000
6695#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L
6696#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a
6697#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L
6698#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d
6699#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L
6700#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008
6701#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L
6702#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e
6703#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L
6704#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f
6705#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L
6706#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000
6707#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L
6708#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010
6709#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L
6710#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016
6711#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL
6712#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002
6713#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L
6714#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001
6715#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L
6716#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008
6717#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L
6718#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000
6719#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL
6720#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000
6721#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L
6722#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000
6723#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L
6724#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010
6725#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L
6726#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c
6727#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L
6728#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008
6729#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L
6730#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c
6731#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L
6732#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d
6733#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L
6734#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004
6735#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL
6736#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000
6737#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L
6738#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004
6739#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L
6740#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000
6741#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L
6742#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001
6743#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L
6744#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010
6745#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL
6746#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000
6747#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL
6748#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000
6749#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L
6750#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010
6751#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L
6752#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010
6753#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L
6754#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010
6755#define FBC_CNTL__FBC_EN_MASK 0x80000000L
6756#define FBC_CNTL__FBC_EN__SHIFT 0x0000001f
6757#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L
6758#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000
6759#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L
6760#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019
6761#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL
6762#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001
6763#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L
6764#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010
6765#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L
6766#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011
6767#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L
6768#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012
6769#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L
6770#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013
6771#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L
6772#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014
6773#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL
6774#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000
6775#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L
6776#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008
6777#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L
6778#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a
6779#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L
6780#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009
6781#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L
6782#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b
6783#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L
6784#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010
6785#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L
6786#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000
6787#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL
6788#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000
6789#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L
6790#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010
6791#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL
6792#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000
6793#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L
6794#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010
6795#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L
6796#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010
6797#define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L
6798#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011
6799#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L
6800#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018
6801#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL
6802#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000
6803#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L
6804#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008
6805#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL
6806#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000
6807#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL
6808#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000
6809#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L
6810#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b
6811#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L
6812#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004
6813#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L
6814#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008
6815#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L
6816#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a
6817#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L
6818#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003
6819#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L
6820#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000
6821#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL
6822#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000
6823#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L
6824#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f
6825#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L
6826#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011
6827#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L
6828#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010
6829#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL
6830#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000
6831#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL
6832#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000
6833#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL
6834#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000
6835#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL
6836#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000
6837#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL
6838#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000
6839#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL
6840#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000
6841#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL
6842#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000
6843#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL
6844#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000
6845#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL
6846#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000
6847#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL
6848#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000
6849#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL
6850#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000
6851#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL
6852#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000
6853#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL
6854#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000
6855#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL
6856#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000
6857#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL
6858#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000
6859#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL
6860#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000
6861#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL
6862#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000
6863#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL
6864#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000
6865#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL
6866#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000
6867#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL
6868#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000
6869#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL
6870#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000
6871#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL
6872#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000
6873#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L
6874#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010
6875#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L
6876#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000
6877#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L
6878#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008
6879#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L
6880#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a
6881#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L
6882#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004
6883#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L
6884#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003
6885#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L
6886#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015
6887#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L
6888#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014
6889#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L
6890#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c
6891#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L
6892#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b
6893#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L
6894#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c
6895#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L
6896#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002
6897#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L
6898#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008
6899#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL
6900#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000
6901#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L
6902#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007
6903#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L
6904#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000
6905#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL
6906#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000
6907#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL
6908#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000
6909#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
6910#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
6911#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L
6912#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a
6913#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L
6914#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c
6915#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L
6916#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e
6917#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L
6918#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d
6919#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L
6920#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f
6921#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L
6922#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e
6923#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L
6924#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c
6925#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L
6926#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008
6927#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L
6928#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009
6929#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L
6930#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014
6931#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L
6932#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010
6933#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L
6934#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015
6935#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L
6936#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019
6937#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L
6938#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018
6939#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L
6940#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004
6941#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L
6942#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000
6943#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L
6944#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010
6945#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L
6946#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000
6947#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L
6948#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010
6949#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L
6950#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000
6951#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L
6952#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004
6953#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L
6954#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004
6955#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L
6956#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000
6957#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L
6958#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014
6959#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L
6960#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018
6961#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L
6962#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c
6963#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L
6964#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008
6965#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L
6966#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010
6967#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL
6968#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000
6969#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L
6970#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010
6971#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL
6972#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000
6973#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L
6974#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010
6975#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L
6976#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010
6977#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL
6978#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000
6979#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L
6980#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010
6981#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL
6982#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000
6983#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL
6984#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000
6985#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL
6986#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000
6987#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL
6988#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000
6989#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L
6990#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000
6991#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL
6992#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000
6993#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL
6994#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000
6995#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL
6996#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000
6997#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL
6998#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000
6999#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L
7000#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000
7001#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L
7002#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004
7003#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL
7004#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000
7005#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L
7006#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010
7007#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL
7008#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000
7009#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L
7010#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010
7011#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L
7012#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000
7013#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L
7014#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010
7015#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L
7016#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008
7017#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L
7018#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c
7019#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L
7020#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004
7021#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L
7022#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000
7023#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL
7024#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000
7025#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL
7026#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000
7027#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL
7028#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000
7029#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL
7030#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000
7031#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
7032#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
7033#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL
7034#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000
7035#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L
7036#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010
7037#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL
7038#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000
7039#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L
7040#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010
7041#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL
7042#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000
7043#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L
7044#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010
7045#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL
7046#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000
7047#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L
7048#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010
7049#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL
7050#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000
7051#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L
7052#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010
7053#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL
7054#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000
7055#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L
7056#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010
7057#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L
7058#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000
7059#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L
7060#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004
7061#define GENENB__BLK_IO_BASE_MASK 0x000000ffL
7062#define GENENB__BLK_IO_BASE__SHIFT 0x00000000
7063#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L
7064#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f
7065#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L
7066#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003
7067#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L
7068#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000
7069#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L
7070#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002
7071#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L
7072#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001
7073#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L
7074#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L
7075#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000
7076#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008
7077#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L
7078#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010
7079#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L
7080#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f
7081#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L
7082#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001
7083#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L
7084#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000
7085#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L
7086#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002
7087#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L
7088#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002
7089#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L
7090#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001
7091#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L
7092#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000
7093#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L
7094#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006
7095#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L
7096#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005
7097#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L
7098#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004
7099#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL
7100#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000
7101#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L
7102#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008
7103#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L
7104#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007
7105#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L
7106#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000
7107#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L
7108#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001
7109#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L
7110#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008
7111#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L
7112#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018
7113#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L
7114#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004
7115#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L
7116#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010
7117#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L
7118#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000
7119#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L
7120#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005
7121#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L
7122#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004
7123#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L
7124#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a
7125#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL
7126#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000
7127#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L
7128#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009
7129#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L
7130#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006
7131#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L
7132#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009
7133#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L
7134#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010
7135#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L
7136#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000
7137#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L
7138#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c
7139#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L
7140#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L
7141#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008
7142#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d
7143#define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L
7144#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003
7145#define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L
7146#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003
7147#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L
7148#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000
7149#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L
7150#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005
7151#define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL
7152#define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002
7153#define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L
7154#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006
7155#define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L
7156#define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001
7157#define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L
7158#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007
7159#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L
7160#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000
7161#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L
7162#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005
7163#define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL
7164#define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002
7165#define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L
7166#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006
7167#define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L
7168#define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001
7169#define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L
7170#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007
7171#define GENS0__CRT_INTR_MASK 0x00000080L
7172#define GENS0__CRT_INTR__SHIFT 0x00000007
7173#define GENS0__SENSE_SWITCH_MASK 0x00000010L
7174#define GENS0__SENSE_SWITCH__SHIFT 0x00000004
7175#define GENS1__NO_DISPLAY_MASK 0x00000001L
7176#define GENS1__NO_DISPLAY__SHIFT 0x00000000
7177#define GENS1__PIXEL_READ_BACK_MASK 0x00000030L
7178#define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004
7179#define GENS1__VGA_VSTATUS_MASK 0x00000008L
7180#define GENS1__VGA_VSTATUS__SHIFT 0x00000003
7181#define GRA00__GRPH_SET_RESET0_MASK 0x00000001L
7182#define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000
7183#define GRA00__GRPH_SET_RESET1_MASK 0x00000002L
7184#define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001
7185#define GRA00__GRPH_SET_RESET2_MASK 0x00000004L
7186#define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002
7187#define GRA00__GRPH_SET_RESET3_MASK 0x00000008L
7188#define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003
7189#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L
7190#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000
7191#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L
7192#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001
7193#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L
7194#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002
7195#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L
7196#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003
7197#define GRA02__GRPH_CCOMP_MASK 0x0000000fL
7198#define GRA02__GRPH_CCOMP__SHIFT 0x00000000
7199#define GRA03__GRPH_FN_SEL_MASK 0x00000018L
7200#define GRA03__GRPH_FN_SEL__SHIFT 0x00000003
7201#define GRA03__GRPH_ROTATE_MASK 0x00000007L
7202#define GRA03__GRPH_ROTATE__SHIFT 0x00000000
7203#define GRA04__GRPH_RMAP_MASK 0x00000003L
7204#define GRA04__GRPH_RMAP__SHIFT 0x00000000
7205#define GRA05__CGA_ODDEVEN_MASK 0x00000010L
7206#define GRA05__CGA_ODDEVEN__SHIFT 0x00000004
7207#define GRA05__GRPH_OES_MASK 0x00000020L
7208#define GRA05__GRPH_OES__SHIFT 0x00000005
7209#define GRA05__GRPH_PACK_MASK 0x00000040L
7210#define GRA05__GRPH_PACK__SHIFT 0x00000006
7211#define GRA05__GRPH_READ1_MASK 0x00000008L
7212#define GRA05__GRPH_READ1__SHIFT 0x00000003
7213#define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L
7214#define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000
7215#define GRA06__GRPH_ADRSEL_MASK 0x0000000cL
7216#define GRA06__GRPH_ADRSEL__SHIFT 0x00000002
7217#define GRA06__GRPH_GRAPHICS_MASK 0x00000001L
7218#define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000
7219#define GRA06__GRPH_ODDEVEN_MASK 0x00000002L
7220#define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001
7221#define GRA07__GRPH_XCARE0_MASK 0x00000001L
7222#define GRA07__GRPH_XCARE0__SHIFT 0x00000000
7223#define GRA07__GRPH_XCARE1_MASK 0x00000002L
7224#define GRA07__GRPH_XCARE1__SHIFT 0x00000001
7225#define GRA07__GRPH_XCARE2_MASK 0x00000004L
7226#define GRA07__GRPH_XCARE2__SHIFT 0x00000002
7227#define GRA07__GRPH_XCARE3_MASK 0x00000008L
7228#define GRA07__GRPH_XCARE3__SHIFT 0x00000003
7229#define GRA08__GRPH_BMSK_MASK 0x000000ffL
7230#define GRA08__GRPH_BMSK__SHIFT 0x00000000
7231#define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL
7232#define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000
7233#define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL
7234#define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000
7235#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L
7236#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006
7237#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L
7238#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008
7239#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL
7240#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000
7241#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
7242#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010
7243#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L
7244#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014
7245#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L
7246#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b
7247#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L
7248#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006
7249#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L
7250#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f
7251#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L
7252#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000
7253#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L
7254#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008
7255#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L
7256#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012
7257#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL
7258#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002
7259#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L
7260#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018
7261#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
7262#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011
7263#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L
7264#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d
7265#define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L
7266#define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004
7267#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
7268#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008
7269#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L
7270#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000
7271#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L
7272#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004
7273#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L
7274#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009
7275#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L
7276#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008
7277#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL
7278#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000
7279#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L
7280#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004
7281#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L
7282#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000
7283#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L
7284#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000
7285#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L
7286#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000
7287#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L
7288#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008
7289#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L
7290#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008
7291#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L
7292#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000
7293#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L
7294#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010
7295#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L
7296#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008
7297#define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL
7298#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000
7299#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L
7300#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000
7301#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L
7302#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008
7303#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL
7304#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000
7305#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
7306#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000
7307#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L
7308#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008
7309#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL
7310#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000
7311#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
7312#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010
7313#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
7314#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011
7315#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L
7316#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000
7317#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
7318#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008
7319#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
7320#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c
7321#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL
7322#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000
7323#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L
7324#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008
7325#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL
7326#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000
7327#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL
7328#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000
7329#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L
7330#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a
7331#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L
7332#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008
7333#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L
7334#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000
7335#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L
7336#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006
7337#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L
7338#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004
7339#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
7340#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018
7341#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L
7342#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000
7343#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L
7344#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001
7345#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L
7346#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c
7347#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L
7348#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002
7349#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L
7350#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003
7351#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L
7352#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008
7353#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L
7354#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010
7355#define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL
7356#define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000
7357#define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL
7358#define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000
7359#define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL
7360#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000
7361#define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL
7362#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000
7363#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L
7364#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c
7365#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL
7366#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000
7367#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L
7368#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c
7369#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL
7370#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000
7371#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L
7372#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c
7373#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL
7374#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000
7375#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L
7376#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f
7377#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L
7378#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c
7379#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L
7380#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001
7381#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L
7382#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010
7383#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L
7384#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004
7385#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L
7386#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000
7387#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L
7388#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008
7389#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L
7390#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c
7391#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL
7392#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000
7393#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L
7394#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004
7395#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L
7396#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010
7397#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L
7398#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008
7399#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L
7400#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c
7401#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L
7402#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018
7403#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L
7404#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008
7405#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L
7406#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009
7407#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L
7408#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000
7409#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L
7410#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004
7411#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L
7412#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004
7413#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L
7414#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002
7415#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L
7416#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000
7417#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L
7418#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L
7419#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c
7420#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008
7421#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L
7422#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001
7423#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L
7424#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010
7425#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L
7426#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000
7427#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L
7428#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005
7429#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L
7430#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018
7431#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L
7432#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004
7433#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L
7434#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001
7435#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L
7436#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010
7437#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L
7438#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000
7439#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L
7440#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005
7441#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L
7442#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018
7443#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L
7444#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004
7445#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L
7446#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005
7447#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L
7448#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004
7449#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L
7450#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001
7451#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L
7452#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000
7453#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L
7454#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009
7455#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L
7456#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008
7457#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L
7458#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008
7459#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL
7460#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000
7461#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L
7462#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010
7463#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L
7464#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000
7465#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L
7466#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010
7467#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L
7468#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b
7469#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L
7470#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014
7471#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L
7472#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005
7473#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L
7474#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004
7475#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L
7476#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009
7477#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L
7478#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010
7479#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L
7480#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008
7481#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L
7482#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000
7483#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL
7484#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000
7485#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL
7486#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000
7487#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL
7488#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000
7489#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL
7490#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000
7491#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L
7492#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010
7493#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL
7494#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000
7495#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L
7496#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010
7497#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL
7498#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000
7499#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L
7500#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010
7501#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL
7502#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000
7503#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L
7504#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010
7505#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL
7506#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000
7507#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L
7508#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010
7509#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL
7510#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000
7511#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L
7512#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010
7513#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L
7514#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000
7515#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L
7516#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004
7517#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L
7518#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000
7519#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L
7520#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004
7521#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L
7522#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c
7523#define KEY_CONTROL__KEY_MODE_MASK 0x00000006L
7524#define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001
7525#define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L
7526#define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000
7527#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L
7528#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010
7529#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL
7530#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000
7531#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L
7532#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010
7533#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL
7534#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000
7535#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L
7536#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010
7537#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL
7538#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000
7539#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L
7540#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010
7541#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL
7542#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000
7543#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL
7544#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000
7545#define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL
7546#define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000
7547#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L
7548#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000
7549#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L
7550#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004
7551#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L
7552#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000
7553#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL
7554#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000
7555#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL
7556#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000
7557#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
7558#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
7559#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L
7560#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000
7561#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L
7562#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008
7563#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L
7564#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000
7565#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L
7566#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003
7567#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L
7568#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008
7569#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L
7570#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005
7571#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L
7572#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b
7573#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L
7574#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c
7575#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L
7576#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010
7577#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L
7578#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000
7579#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L
7580#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004
7581#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L
7582#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008
7583#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L
7584#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a
7585#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L
7586#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009
7587#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L
7588#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c
7589#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L
7590#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012
7591#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L
7592#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010
7593#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L
7594#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011
7595#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L
7596#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L
7597#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019
7598#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L
7599#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a
7600#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018
7601#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L
7602#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L
7603#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011
7604#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L
7605#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012
7606#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010
7607#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L
7608#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001
7609#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L
7610#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000
7611#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L
7612#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004
7613#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L
7614#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L
7615#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009
7616#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L
7617#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a
7618#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008
7619#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L
7620#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010
7621#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L
7622#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018
7623#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL
7624#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000
7625#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L
7626#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008
7627#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L
7628#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010
7629#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL
7630#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000
7631#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L
7632#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008
7633#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L
7634#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018
7635#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L
7636#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010
7637#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL
7638#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000
7639#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L
7640#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003
7641#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L
7642#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001
7643#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L
7644#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004
7645#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L
7646#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008
7647#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L
7648#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002
7649#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L
7650#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000
7651#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL
7652#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000
7653#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L
7654#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008
7655#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L
7656#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010
7657#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L
7658#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018
7659#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
7660#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000
7661#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL
7662#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000
7663#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L
7664#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008
7665#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L
7666#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010
7667#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L
7668#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018
7669#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL
7670#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000
7671#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L
7672#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008
7673#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L
7674#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010
7675#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L
7676#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018
7677#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL
7678#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000
7679#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L
7680#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008
7681#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L
7682#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010
7683#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L
7684#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018
7685#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L
7686#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008
7687#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L
7688#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000
7689#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L
7690#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010
7691#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L
7692#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000
7693#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L
7694#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004
7695#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L
7696#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000
7697#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L
7698#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014
7699#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L
7700#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010
7701#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L
7702#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c
7703#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L
7704#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018
7705#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L
7706#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c
7707#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L
7708#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008
7709#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L
7710#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004
7711#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L
7712#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010
7713#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L
7714#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018
7715#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L
7716#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000
7717#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L
7718#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e
7719#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L
7720#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f
7721#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L
7722#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c
7723#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L
7724#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008
7725#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L
7726#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000
7727#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L
7728#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004
7729#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L
7730#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010
7731#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L
7732#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008
7733#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L
7734#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013
7735#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL
7736#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000
7737#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL
7738#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000
7739#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
7740#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
7741#define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL
7742#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000
7743#define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L
7744#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004
7745#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL
7746#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000
7747#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L
7748#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008
7749#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
7750#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014
7751#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL
7752#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000
7753#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L
7754#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011
7755#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L
7756#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008
7757#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L
7758#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010
7759#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L
7760#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014
7761#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL
7762#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000
7763#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL
7764#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000
7765#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L
7766#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c
7767#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L
7768#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008
7769#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L
7770#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004
7771#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L
7772#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000
7773#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L
7774#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014
7775#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L
7776#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a
7777#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL
7778#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000
7779#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L
7780#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c
7781#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L
7782#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a
7783#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L
7784#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010
7785#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L
7786#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018
7787#define MVP_CONTROL1__MVP_EN_MASK 0x00000001L
7788#define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000
7789#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L
7790#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014
7791#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L
7792#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004
7793#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L
7794#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009
7795#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L
7796#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008
7797#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L
7798#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c
7799#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L
7800#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e
7801#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L
7802#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f
7803#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L
7804#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010
7805#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L
7806#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014
7807#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L
7808#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008
7809#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L
7810#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c
7811#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L
7812#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000
7813#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L
7814#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004
7815#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L
7816#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c
7817#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L
7818#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018
7819#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L
7820#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004
7821#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L
7822#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008
7823#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L
7824#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014
7825#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L
7826#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c
7827#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L
7828#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c
7829#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L
7830#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010
7831#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L
7832#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000
7833#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L
7834#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018
7835#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL
7836#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000
7837#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L
7838#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d
7839#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L
7840#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c
7841#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L
7842#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008
7843#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L
7844#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010
7845#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L
7846#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e
7847#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL
7848#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000
7849#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L
7850#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010
7851#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL
7852#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000
7853#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L
7854#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001
7855#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L
7856#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001
7857#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L
7858#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000
7859#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL
7860#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001
7861#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L
7862#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000
7863#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL
7864#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001
7865#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L
7866#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a
7867#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L
7868#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019
7869#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L
7870#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b
7871#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L
7872#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014
7873#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L
7874#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013
7875#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L
7876#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000
7877#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L
7878#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011
7879#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L
7880#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010
7881#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L
7882#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012
7883#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L
7884#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f
7885#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L
7886#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e
7887#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L
7888#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b
7889#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L
7890#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c
7891#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L
7892#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a
7893#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L
7894#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009
7895#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L
7896#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d
7897#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L
7898#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003
7899#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L
7900#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006
7901#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L
7902#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004
7903#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L
7904#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000
7905#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L
7906#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003
7907#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L
7908#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002
7909#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L
7910#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001
7911#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L
7912#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004
7913#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L
7914#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c
7915#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L
7916#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000
7917#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L
7918#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d
7919#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L
7920#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010
7921#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L
7922#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018
7923#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L
7924#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001
7925#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL
7926#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002
7927#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L
7928#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000
7929#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L
7930#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008
7931#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L
7932#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005
7933#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L
7934#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004
7935#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L
7936#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007
7937#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L
7938#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006
7939#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L
7940#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001
7941#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L
7942#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003
7943#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L
7944#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000
7945#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L
7946#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002
7947#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L
7948#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010
7949#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L
7950#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008
7951#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL
7952#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000
7953#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L
7954#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f
7955#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L
7956#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e
7957#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL
7958#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000
7959#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L
7960#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010
7961#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L
7962#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L
7963#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c
7964#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008
7965#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L
7966#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c
7967#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L
7968#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L
7969#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018
7970#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014
7971#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L
7972#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e
7973#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L
7974#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L
7975#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000
7976#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008
7977#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L
7978#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018
7979#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L
7980#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000
7981#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L
7982#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008
7983#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L
7984#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004
7985#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L
7986#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f
7987#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L
7988#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010
7989#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL
7990#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000
7991#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL
7992#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L
7993#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f
7994#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000
7995#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L
7996#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010
7997#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL
7998#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000
7999#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL
8000#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000
8001#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL
8002#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000
8003#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
8004#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
8005#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL
8006#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000
8007#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L
8008#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010
8009#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL
8010#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000
8011#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L
8012#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010
8013#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL
8014#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000
8015#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L
8016#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010
8017#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL
8018#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000
8019#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L
8020#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010
8021#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL
8022#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000
8023#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L
8024#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010
8025#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL
8026#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000
8027#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L
8028#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010
8029#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L
8030#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000
8031#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L
8032#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004
8033#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL
8034#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000
8035#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L
8036#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010
8037#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L
8038#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014
8039#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L
8040#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b
8041#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L
8042#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006
8043#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L
8044#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018
8045#define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L
8046#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000
8047#define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L
8048#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008
8049#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L
8050#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012
8051#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL
8052#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002
8053#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L
8054#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019
8055#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L
8056#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011
8057#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L
8058#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d
8059#define OVL_CONTROL1__OVL_Z_MASK 0x00000030L
8060#define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004
8061#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L
8062#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000
8063#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L
8064#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008
8065#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L
8066#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000
8067#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L
8068#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004
8069#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL
8070#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000
8071#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L
8072#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009
8073#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L
8074#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008
8075#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L
8076#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004
8077#define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L
8078#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000
8079#define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L
8080#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008
8081#define OVL_END__OVL_X_END_MASK 0x7fff0000L
8082#define OVL_END__OVL_X_END__SHIFT 0x00000010
8083#define OVL_END__OVL_Y_END_MASK 0x00007fffL
8084#define OVL_END__OVL_Y_END__SHIFT 0x00000000
8085#define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL
8086#define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000
8087#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL
8088#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000
8089#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L
8090#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a
8091#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L
8092#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014
8093#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L
8094#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f
8095#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL
8096#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000
8097#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L
8098#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000
8099#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L
8100#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008
8101#define OVL_START__OVL_X_START_MASK 0x3fff0000L
8102#define OVL_START__OVL_X_START__SHIFT 0x00000010
8103#define OVL_START__OVL_Y_START_MASK 0x00003fffL
8104#define OVL_START__OVL_Y_START__SHIFT 0x00000000
8105#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L
8106#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010
8107#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L
8108#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011
8109#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L
8110#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000
8111#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L
8112#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008
8113#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L
8114#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c
8115#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL
8116#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000
8117#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL
8118#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000
8119#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L
8120#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008
8121#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L
8122#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000
8123#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L
8124#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008
8125#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL
8126#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000
8127#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL
8128#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000
8129#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L
8130#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a
8131#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L
8132#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008
8133#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L
8134#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000
8135#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L
8136#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006
8137#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L
8138#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004
8139#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L
8140#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018
8141#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L
8142#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010
8143#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L
8144#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000
8145#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L
8146#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001
8147#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L
8148#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010
8149#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L
8150#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c
8151#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L
8152#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e
8153#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL
8154#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000
8155#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
8156#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000
8157#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
8158#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004
8159#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL
8160#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000
8161#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L
8162#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000
8163#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L
8164#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000
8165#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L
8166#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c
8167#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L
8168#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e
8169#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL
8170#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000
8171#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L
8172#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d
8173#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL
8174#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000
8175#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
8176#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000
8177#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
8178#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004
8179#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL
8180#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000
8181#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L
8182#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000
8183#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L
8184#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000
8185#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L
8186#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c
8187#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L
8188#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e
8189#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL
8190#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000
8191#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L
8192#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d
8193#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL
8194#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000
8195#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
8196#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000
8197#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
8198#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004
8199#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL
8200#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000
8201#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L
8202#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000
8203#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L
8204#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000
8205#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L
8206#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c
8207#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L
8208#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e
8209#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL
8210#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000
8211#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L
8212#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d
8213#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL
8214#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000
8215#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
8216#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000
8217#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
8218#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004
8219#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL
8220#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000
8221#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L
8222#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000
8223#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L
8224#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000
8225#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L
8226#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c
8227#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L
8228#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e
8229#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL
8230#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000
8231#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L
8232#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d
8233#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL
8234#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000
8235#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
8236#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000
8237#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
8238#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004
8239#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL
8240#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000
8241#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L
8242#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000
8243#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L
8244#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000
8245#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L
8246#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c
8247#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L
8248#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e
8249#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL
8250#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000
8251#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L
8252#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d
8253#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL
8254#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000
8255#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L
8256#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000
8257#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L
8258#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004
8259#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL
8260#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000
8261#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L
8262#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000
8263#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L
8264#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000
8265#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L
8266#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c
8267#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L
8268#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e
8269#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL
8270#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000
8271#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L
8272#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d
8273#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L
8274#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004
8275#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L
8276#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000
8277#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L
8278#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004
8279#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L
8280#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000
8281#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L
8282#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004
8283#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L
8284#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000
8285#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL
8286#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000
8287#define PLL_ANALOG__PLL_CP_MASK 0x00000f00L
8288#define PLL_ANALOG__PLL_CP__SHIFT 0x00000008
8289#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L
8290#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018
8291#define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L
8292#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c
8293#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L
8294#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005
8295#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L
8296#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007
8297#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L
8298#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d
8299#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L
8300#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002
8301#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L
8302#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a
8303#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L
8304#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014
8305#define PLL_CNTL__PLL_CALREF_MASK 0x00000300L
8306#define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008
8307#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L
8308#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a
8309#define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L
8310#define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015
8311#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L
8312#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013
8313#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L
8314#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006
8315#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L
8316#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003
8317#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L
8318#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001
8319#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L
8320#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b
8321#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L
8322#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010
8323#define PLL_CNTL__PLL_RESET_MASK 0x00000001L
8324#define PLL_CNTL__PLL_RESET__SHIFT 0x00000000
8325#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L
8326#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018
8327#define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L
8328#define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004
8329#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L
8330#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008
8331#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L
8332#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004
8333#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L
8334#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000
8335#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL
8336#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000
8337#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L
8338#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018
8339#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L
8340#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010
8341#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL
8342#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000
8343#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L
8344#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016
8345#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L
8346#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011
8347#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L
8348#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014
8349#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L
8350#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015
8351#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL
8352#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000
8353#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L
8354#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012
8355#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L
8356#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010
8357#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L
8358#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013
8359#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L
8360#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004
8361#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL
8362#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000
8363#define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L
8364#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010
8365#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L
8366#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L
8367#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008
8368#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L
8369#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c
8370#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010
8371#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L
8372#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001
8373#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L
8374#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000
8375#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L
8376#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003
8377#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L
8378#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002
8379#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L
8380#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004
8381#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L
8382#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007
8383#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L
8384#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f
8385#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L
8386#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008
8387#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L
8388#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010
8389#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL
8390#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000
8391#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L
8392#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c
8393#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL
8394#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000
8395#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL
8396#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000
8397#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL
8398#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000
8399#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L
8400#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008
8401#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L
8402#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c
8403#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L
8404#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d
8405#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L
8406#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010
8407#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L
8408#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004
8409#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L
8410#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000
8411#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L
8412#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001
8413#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L
8414#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003
8415#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L
8416#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002
8417#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L
8418#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010
8419#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L
8420#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000
8421#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L
8422#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008
8423#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L
8424#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000
8425#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L
8426#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a
8427#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L
8428#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c
8429#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL
8430#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000
8431#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L
8432#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003
8433#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L
8434#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004
8435#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L
8436#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002
8437#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L
8438#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001
8439#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L
8440#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000
8441#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L
8442#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004
8443#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L
8444#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001
8445#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L
8446#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003
8447#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L
8448#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000
8449#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L
8450#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002
8451#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL
8452#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000
8453#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L
8454#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010
8455#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL
8456#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000
8457#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L
8458#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010
8459#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL
8460#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000
8461#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L
8462#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010
8463#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL
8464#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000
8465#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L
8466#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010
8467#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL
8468#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000
8469#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L
8470#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010
8471#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL
8472#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000
8473#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L
8474#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010
8475#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL
8476#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000
8477#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L
8478#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010
8479#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL
8480#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000
8481#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL
8482#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000
8483#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
8484#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c
8485#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L
8486#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010
8487#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
8488#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c
8489#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL
8490#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000
8491#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
8492#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c
8493#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L
8494#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010
8495#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
8496#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c
8497#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL
8498#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000
8499#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
8500#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c
8501#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L
8502#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010
8503#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
8504#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c
8505#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL
8506#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000
8507#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
8508#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c
8509#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L
8510#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010
8511#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
8512#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c
8513#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL
8514#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000
8515#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
8516#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c
8517#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L
8518#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010
8519#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
8520#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c
8521#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL
8522#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000
8523#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
8524#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c
8525#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L
8526#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010
8527#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
8528#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c
8529#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL
8530#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000
8531#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
8532#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c
8533#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L
8534#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010
8535#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
8536#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c
8537#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL
8538#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000
8539#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
8540#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c
8541#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L
8542#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010
8543#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
8544#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c
8545#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL
8546#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000
8547#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL
8548#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L
8549#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014
8550#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000
8551#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL
8552#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000
8553#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L
8554#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010
8555#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL
8556#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000
8557#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL
8558#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000
8559#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L
8560#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c
8561#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L
8562#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010
8563#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L
8564#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c
8565#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL
8566#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000
8567#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L
8568#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c
8569#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L
8570#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010
8571#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L
8572#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c
8573#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL
8574#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000
8575#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L
8576#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c
8577#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L
8578#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010
8579#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L
8580#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c
8581#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL
8582#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000
8583#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L
8584#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c
8585#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L
8586#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010
8587#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L
8588#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c
8589#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL
8590#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000
8591#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L
8592#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c
8593#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L
8594#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010
8595#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L
8596#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c
8597#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL
8598#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000
8599#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L
8600#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c
8601#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L
8602#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010
8603#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L
8604#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c
8605#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL
8606#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000
8607#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L
8608#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c
8609#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L
8610#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010
8611#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L
8612#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c
8613#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL
8614#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000
8615#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L
8616#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c
8617#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L
8618#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010
8619#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L
8620#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c
8621#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL
8622#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000
8623#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL
8624#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L
8625#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014
8626#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000
8627#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L
8628#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000
8629#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L
8630#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004
8631#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL
8632#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000
8633#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL
8634#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000
8635#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L
8636#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000
8637#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L
8638#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000
8639#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L
8640#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000
8641#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L
8642#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008
8643#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L
8644#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000
8645#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L
8646#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010
8647#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L
8648#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c
8649#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L
8650#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010
8651#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L
8652#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008
8653#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL
8654#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000
8655#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L
8656#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f
8657#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL
8658#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000
8659#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L
8660#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f
8661#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L
8662#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010
8663#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL
8664#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000
8665#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL
8666#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000
8667#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L
8668#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004
8669#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L
8670#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000
8671#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L
8672#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c
8673#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L
8674#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008
8675#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L
8676#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000
8677#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL
8678#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000
8679#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L
8680#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004
8681#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL
8682#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000
8683#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L
8684#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008
8685#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL
8686#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000
8687#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L
8688#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007
8689#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L
8690#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004
8691#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L
8692#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000
8693#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL
8694#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000
8695#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL
8696#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000
8697#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L
8698#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010
8699#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L
8700#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000
8701#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL
8702#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000
8703#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL
8704#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000
8705#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
8706#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
8707#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L
8708#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010
8709#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L
8710#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000
8711#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L
8712#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008
8713#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L
8714#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000
8715#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL
8716#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000
8717#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L
8718#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010
8719#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL
8720#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000
8721#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L
8722#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010
8723#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL
8724#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000
8725#define SEQ00__SEQ_RST0B_MASK 0x00000001L
8726#define SEQ00__SEQ_RST0B__SHIFT 0x00000000
8727#define SEQ00__SEQ_RST1B_MASK 0x00000002L
8728#define SEQ00__SEQ_RST1B__SHIFT 0x00000001
8729#define SEQ01__SEQ_DOT8_MASK 0x00000001L
8730#define SEQ01__SEQ_DOT8__SHIFT 0x00000000
8731#define SEQ01__SEQ_MAXBW_MASK 0x00000020L
8732#define SEQ01__SEQ_MAXBW__SHIFT 0x00000005
8733#define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L
8734#define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003
8735#define SEQ01__SEQ_SHIFT2_MASK 0x00000004L
8736#define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002
8737#define SEQ01__SEQ_SHIFT4_MASK 0x00000010L
8738#define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004
8739#define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L
8740#define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000
8741#define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L
8742#define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001
8743#define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L
8744#define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002
8745#define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L
8746#define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003
8747#define SEQ03__SEQ_FONT_A0_MASK 0x00000020L
8748#define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005
8749#define SEQ03__SEQ_FONT_A1_MASK 0x00000004L
8750#define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002
8751#define SEQ03__SEQ_FONT_A2_MASK 0x00000008L
8752#define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003
8753#define SEQ03__SEQ_FONT_B0_MASK 0x00000010L
8754#define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004
8755#define SEQ03__SEQ_FONT_B1_MASK 0x00000001L
8756#define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000
8757#define SEQ03__SEQ_FONT_B2_MASK 0x00000002L
8758#define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001
8759#define SEQ04__SEQ_256K_MASK 0x00000002L
8760#define SEQ04__SEQ_256K__SHIFT 0x00000001
8761#define SEQ04__SEQ_CHAIN_MASK 0x00000008L
8762#define SEQ04__SEQ_CHAIN__SHIFT 0x00000003
8763#define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L
8764#define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002
8765#define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL
8766#define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000
8767#define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L
8768#define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000
8769#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL
8770#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000
8771#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL
8772#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000
8773#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL
8774#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000
8775#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL
8776#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000
8777#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL
8778#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000
8779#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL
8780#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000
8781#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL
8782#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000
8783#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL
8784#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000
8785#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL
8786#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000
8787#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL
8788#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000
8789#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL
8790#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000
8791#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL
8792#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000
8793#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL
8794#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000
8795#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL
8796#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000
8797#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL
8798#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000
8799#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL
8800#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000
8801#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL
8802#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000
8803#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL
8804#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000
8805#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL
8806#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000
8807#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L
8808#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008
8809#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L
8810#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010
8811#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L
8812#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018
8813#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L
8814#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008
8815#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L
8816#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000
8817#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL
8818#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000
8819#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L
8820#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008
8821#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L
8822#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010
8823#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L
8824#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018
8825#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL
8826#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000
8827#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L
8828#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008
8829#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L
8830#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010
8831#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L
8832#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018
8833#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL
8834#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000
8835#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L
8836#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008
8837#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L
8838#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010
8839#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L
8840#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018
8841#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L
8842#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000
8843#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L
8844#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004
8845#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L
8846#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008
8847#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L
8848#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000
8849#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L
8850#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004
8851#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L
8852#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008
8853#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L
8854#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000
8855#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L
8856#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004
8857#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L
8858#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008
8859#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L
8860#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000
8861#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L
8862#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004
8863#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L
8864#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008
8865#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L
8866#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000
8867#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L
8868#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004
8869#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L
8870#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008
8871#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L
8872#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000
8873#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L
8874#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004
8875#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L
8876#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008
8877#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
8878#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
8879#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
8880#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
8881#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L
8882#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000
8883#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L
8884#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008
8885#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L
8886#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000
8887#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L
8888#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000
8889#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L
8890#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001
8891#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L
8892#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002
8893#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L
8894#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003
8895#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L
8896#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f
8897#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L
8898#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004
8899#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L
8900#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007
8901#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L
8902#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008
8903#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL
8904#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000
8905#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L
8906#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b
8907#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L
8908#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c
8909#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L
8910#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a
8911#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L
8912#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014
8913#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L
8914#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017
8915#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L
8916#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018
8917#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L
8918#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010
8919#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L
8920#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b
8921#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L
8922#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c
8923#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L
8924#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a
8925#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L
8926#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004
8927#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L
8928#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007
8929#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L
8930#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008
8931#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL
8932#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000
8933#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L
8934#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b
8935#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L
8936#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c
8937#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L
8938#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a
8939#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L
8940#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014
8941#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L
8942#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017
8943#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L
8944#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018
8945#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L
8946#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010
8947#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L
8948#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b
8949#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L
8950#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c
8951#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L
8952#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a
8953#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L
8954#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000
8955#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L
8956#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008
8957#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L
8958#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010
8959#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L
8960#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018
8961#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L
8962#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000
8963#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L
8964#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018
8965#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L
8966#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008
8967#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L
8968#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010
8969#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L
8970#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004
8971#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L
8972#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019
8973#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L
8974#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018
8975#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L
8976#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000
8977#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L
8978#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009
8979#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L
8980#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008
8981#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L
8982#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011
8983#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L
8984#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010
8985#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L
8986#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000
8987#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL
8988#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000
8989#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L
8990#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010
8991#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL
8992#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000
8993#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L
8994#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010
8995#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL
8996#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000
8997#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L
8998#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010
8999#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L
9000#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011
9001#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL
9002#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000
9003#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L
9004#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010
9005#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L
9006#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001
9007#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L
9008#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018
9009#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L
9010#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008
9011#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L
9012#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000
9013#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL
9014#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000
9015#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L
9016#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010
9017#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L
9018#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011
9019#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL
9020#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000
9021#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L
9022#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000
9023#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L
9024#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008
9025#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L
9026#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010
9027#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L
9028#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018
9029#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L
9030#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006
9031#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L
9032#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004
9033#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L
9034#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000
9035#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L
9036#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010
9037#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L
9038#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c
9039#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L
9040#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008
9041#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL
9042#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000
9043#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L
9044#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010
9045#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L
9046#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011
9047#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL
9048#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000
9049#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L
9050#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a
9051#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L
9052#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009
9053#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L
9054#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008
9055#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L
9056#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000
9057#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L
9058#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c
9059#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L
9060#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018
9061#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L
9062#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e
9063#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L
9064#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014
9065#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L
9066#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010
9067#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L
9068#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a
9069#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L
9070#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009
9071#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L
9072#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008
9073#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L
9074#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000
9075#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L
9076#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c
9077#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L
9078#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018
9079#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L
9080#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e
9081#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L
9082#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014
9083#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L
9084#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010
9085#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L
9086#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a
9087#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L
9088#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009
9089#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L
9090#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008
9091#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L
9092#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000
9093#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L
9094#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c
9095#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L
9096#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018
9097#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L
9098#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e
9099#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L
9100#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014
9101#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L
9102#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010
9103#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L
9104#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a
9105#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L
9106#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009
9107#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L
9108#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008
9109#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L
9110#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000
9111#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L
9112#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c
9113#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L
9114#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018
9115#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L
9116#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e
9117#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L
9118#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014
9119#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L
9120#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010
9121#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L
9122#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a
9123#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L
9124#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009
9125#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L
9126#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008
9127#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L
9128#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000
9129#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L
9130#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c
9131#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L
9132#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018
9133#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L
9134#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e
9135#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L
9136#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014
9137#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L
9138#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010
9139#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L
9140#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a
9141#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L
9142#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009
9143#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L
9144#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008
9145#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L
9146#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000
9147#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L
9148#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c
9149#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L
9150#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018
9151#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L
9152#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e
9153#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L
9154#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014
9155#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L
9156#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010
9157#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL
9158#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000
9159#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL
9160#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000
9161#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L
9162#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010
9163#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL
9164#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000
9165#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L
9166#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010
9167#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL
9168#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000
9169#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L
9170#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010
9171#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L
9172#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c
9173#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L
9174#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d
9175#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L
9176#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e
9177#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L
9178#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f
9179#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L
9180#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014
9181#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L
9182#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010
9183#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L
9184#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008
9185#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L
9186#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000
9187#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L
9188#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004
9189#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L
9190#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010
9191#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L
9192#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003
9193#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L
9194#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004
9195#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L
9196#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000
9197#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L
9198#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002
9199#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L
9200#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008
9201#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L
9202#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001
9203#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L
9204#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019
9205#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L
9206#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018
9207#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L
9208#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a
9209#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L
9210#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c
9211#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L
9212#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d
9213#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL
9214#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002
9215#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L
9216#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c
9217#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L
9218#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004
9219#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L
9220#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005
9221#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L
9222#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006
9223#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L
9224#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b
9225#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L
9226#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014
9227#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L
9228#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d
9229#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L
9230#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000
9231#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L
9232#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008
9233#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L
9234#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018
9235#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L
9236#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013
9237#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L
9238#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010
9239#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL
9240#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002
9241#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L
9242#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010
9243#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L
9244#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c
9245#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L
9246#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d
9247#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL
9248#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000
9249#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL
9250#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000
9251#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L
9252#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010
9253#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L
9254#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008
9255#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L
9256#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c
9257#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L
9258#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000
9259#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L
9260#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002
9261#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L
9262#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001
9263#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L
9264#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014
9265#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L
9266#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f
9267#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L
9268#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010
9269#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L
9270#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d
9271#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L
9272#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c
9273#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L
9274#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019
9275#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL
9276#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000
9277#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L
9278#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011
9279#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L
9280#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000
9281#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L
9282#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001
9283#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L
9284#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002
9285#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L
9286#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003
9287#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L
9288#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004
9289#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L
9290#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005
9291#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L
9292#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000
9293#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L
9294#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004
9295#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L
9296#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008
9297#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L
9298#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c
9299#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L
9300#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010
9301#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L
9302#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014
9303#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L
9304#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016
9305#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L
9306#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018
9307#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L
9308#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a
9309#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L
9310#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c
9311#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L
9312#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000
9313#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L
9314#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004
9315#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L
9316#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008
9317#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L
9318#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c
9319#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L
9320#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010
9321#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L
9322#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014
9323#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L
9324#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015
9325#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L
9326#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017
9327#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L
9328#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019
9329#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L
9330#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b
9331#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L
9332#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d
9333#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L
9334#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f
9335#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L
9336#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014
9337#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L
9338#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015
9339#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L
9340#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016
9341#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L
9342#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017
9343#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L
9344#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004
9345#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L
9346#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008
9347#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L
9348#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000
9349#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL
9350#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002
9351#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L
9352#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c
9353#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L
9354#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010
9355#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L
9356#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018
9357#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL
9358#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000
9359#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L
9360#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005
9361#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L
9362#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018
9363#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L
9364#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c
9365#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L
9366#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c
9367#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L
9368#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011
9369#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL
9370#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000
9371#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L
9372#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008
9373#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L
9374#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018
9375#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L
9376#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c
9377#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L
9378#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005
9379#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L
9380#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004
9381#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL
9382#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000
9383#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L
9384#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010
9385#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L
9386#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008
9387#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L
9388#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010
9389#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL
9390#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000
9391#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL
9392#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000
9393#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL
9394#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000
9395#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L
9396#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008
9397#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L
9398#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018
9399#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L
9400#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c
9401#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L
9402#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005
9403#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L
9404#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004
9405#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL
9406#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000
9407#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L
9408#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010
9409#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L
9410#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008
9411#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L
9412#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010
9413#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL
9414#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000
9415#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL
9416#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000
9417#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL
9418#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000
9419#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L
9420#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008
9421#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L
9422#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018
9423#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L
9424#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c
9425#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L
9426#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005
9427#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L
9428#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004
9429#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL
9430#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000
9431#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L
9432#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010
9433#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L
9434#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008
9435#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L
9436#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010
9437#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL
9438#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000
9439#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL
9440#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000
9441#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L
9442#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014
9443#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L
9444#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018
9445#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L
9446#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010
9447#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L
9448#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008
9449#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L
9450#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000
9451#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL
9452#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000
9453#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL
9454#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000
9455#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL
9456#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000
9457#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL
9458#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000
9459#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL
9460#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000
9461#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L
9462#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004
9463#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L
9464#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000
9465#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L
9466#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008
9467#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L
9468#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010
9469#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L
9470#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018
9471#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL
9472#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000
9473#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L
9474#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010
9475#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L
9476#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000
9477#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L
9478#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018
9479#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L
9480#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008
9481#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L
9482#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002
9483#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L
9484#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000
9485#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L
9486#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003
9487#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L
9488#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001
9489#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L
9490#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000
9491#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L
9492#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d
9493#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L
9494#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f
9495#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L
9496#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018
9497#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L
9498#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010
9499#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L
9500#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a
9501#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L
9502#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008
9503#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L
9504#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b
9505#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L
9506#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003
9507#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L
9508#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005
9509#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L
9510#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c
9511#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL
9512#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000
9513#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL
9514#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000
9515#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL
9516#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000
9517#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L
9518#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010
9519#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL
9520#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000
9521#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L
9522#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010
9523#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L
9524#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008
9525#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L
9526#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000
9527#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L
9528#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004
9529#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L
9530#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010
9531#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L
9532#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005
9533#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL
9534#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000
9535#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L
9536#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007
9537#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L
9538#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008
9539#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L
9540#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018
9541#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L
9542#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019
9543#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L
9544#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010
9545#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L
9546#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000
9547#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L
9548#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008
9549#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L
9550#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001
9551#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L
9552#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009
9553#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L
9554#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002
9555#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L
9556#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a
9557#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L
9558#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003
9559#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L
9560#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b
9561#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L
9562#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004
9563#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L
9564#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c
9565#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L
9566#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005
9567#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L
9568#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d
9569#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L
9570#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010
9571#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L
9572#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012
9573#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L
9574#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011
9575#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L
9576#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000
9577#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L
9578#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008
9579#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L
9580#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010
9581#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L
9582#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000
9583#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L
9584#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018
9585#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L
9586#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008
9587#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L
9588#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002
9589#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L
9590#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000
9591#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L
9592#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003
9593#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L
9594#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001
9595#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L
9596#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008
9597#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L
9598#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000
9599#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L
9600#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000
9601#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L
9602#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018
9603#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L
9604#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010
9605#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L
9606#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008
9607#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL
9608#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000
9609#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL
9610#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000
9611#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
9612#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
9613#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL
9614#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000
9615#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L
9616#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010
9617#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L
9618#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010
9619#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL
9620#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000
9621#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L
9622#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f
9623#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L
9624#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013
9625#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L
9626#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012
9627#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L
9628#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014
9629#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L
9630#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010
9631#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L
9632#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004
9633#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL
9634#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000
9635#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L
9636#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008
9637#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL
9638#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000
9639#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L
9640#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a
9641#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L
9642#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009
9643#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L
9644#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008
9645#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L
9646#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e
9647#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L
9648#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d
9649#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L
9650#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c
9651#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L
9652#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012
9653#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L
9654#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011
9655#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L
9656#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010
9657#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL
9658#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000
9659#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L
9660#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a
9661#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L
9662#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008
9663#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L
9664#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c
9665#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L
9666#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014
9667#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L
9668#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004
9669#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L
9670#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016
9671#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L
9672#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b
9673#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L
9674#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000
9675#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L
9676#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010
9677#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L
9678#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008
9679#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L
9680#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c
9681#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L
9682#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000
9683#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L
9684#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010
9685#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L
9686#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e
9687#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L
9688#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008
9689#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L
9690#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018
9691#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L
9692#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008
9693#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L
9694#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012
9695#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L
9696#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010
9697#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L
9698#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009
9699#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L
9700#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014
9701#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL
9702#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000
9703#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L
9704#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010
9705#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL
9706#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000
9707#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL
9708#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000
9709#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL
9710#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000
9711#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L
9712#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010
9713#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L
9714#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008
9715#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L
9716#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c
9717#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L
9718#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010
9719#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L
9720#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c
9721#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL
9722#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000
9723#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L
9724#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000
9725#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L
9726#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c
9727#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L
9728#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008
9729#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L
9730#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004
9731#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L
9732#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010
9733#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L
9734#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010
9735#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L
9736#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c
9737#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL
9738#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000
9739#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L
9740#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010
9741#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL
9742#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000
9743#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL
9744#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000
9745#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL
9746#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000
9747#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL
9748#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000
9749#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL
9750#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000
9751#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL
9752#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000
9753#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L
9754#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010
9755#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L
9756#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000
9757#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L
9758#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003
9759#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L
9760#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f
9761#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L
9762#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008
9763#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L
9764#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010
9765#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L
9766#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009
9767#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L
9768#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013
9769#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L
9770#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014
9771#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L
9772#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000
9773#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L
9774#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010
9775#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L
9776#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008
9777#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L
9778#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c
9779#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L
9780#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f
9781#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L
9782#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010
9783#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL
9784#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000
9785#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L
9786#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010
9787#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L
9788#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c
9789#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL
9790#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000
9791#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL
9792#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000
9793#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L
9794#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014
9795#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L
9796#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010
9797#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL
9798#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000
9799#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL
9800#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000
9801#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L
9802#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000
9803#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L
9804#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c
9805#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L
9806#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008
9807#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L
9808#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004
9809#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L
9810#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010
9811#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL
9812#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000
9813#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL
9814#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000
9815#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL
9816#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000
9817#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L
9818#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010
9819#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L
9820#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010
9821#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL
9822#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000
9823#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L
9824#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c
9825#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L
9826#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000
9827#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L
9828#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008
9829#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL
9830#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000
9831#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL
9832#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000
9833#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
9834#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
9835
9836#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h
new file mode 100644
index 000000000000..c75aee25619e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h
@@ -0,0 +1,1784 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef GFX_6_0_D_H
24#define GFX_6_0_D_H
25
26#define ixCLIPPER_DEBUG_REG00 0x0000
27#define ixCLIPPER_DEBUG_REG01 0x0001
28#define ixCLIPPER_DEBUG_REG02 0x0002
29#define ixCLIPPER_DEBUG_REG03 0x0003
30#define ixCLIPPER_DEBUG_REG04 0x0004
31#define ixCLIPPER_DEBUG_REG05 0x0005
32#define ixCLIPPER_DEBUG_REG06 0x0006
33#define ixCLIPPER_DEBUG_REG07 0x0007
34#define ixCLIPPER_DEBUG_REG08 0x0008
35#define ixCLIPPER_DEBUG_REG09 0x0009
36#define ixCLIPPER_DEBUG_REG10 0x000A
37#define ixCLIPPER_DEBUG_REG11 0x000B
38#define ixCLIPPER_DEBUG_REG12 0x000C
39#define ixCLIPPER_DEBUG_REG13 0x000D
40#define ixCLIPPER_DEBUG_REG14 0x000E
41#define ixCLIPPER_DEBUG_REG15 0x000F
42#define ixCLIPPER_DEBUG_REG16 0x0010
43#define ixCLIPPER_DEBUG_REG17 0x0011
44#define ixCLIPPER_DEBUG_REG18 0x0012
45#define ixCLIPPER_DEBUG_REG19 0x0013
46#define ixGDS_DEBUG_REG0 0x0000
47#define ixGDS_DEBUG_REG1 0x0001
48#define ixGDS_DEBUG_REG2 0x0002
49#define ixGDS_DEBUG_REG3 0x0003
50#define ixGDS_DEBUG_REG4 0x0004
51#define ixGDS_DEBUG_REG5 0x0005
52#define ixGDS_DEBUG_REG6 0x0006
53#define ixIA_DEBUG_REG0 0x0000
54#define ixIA_DEBUG_REG1 0x0001
55#define ixIA_DEBUG_REG2 0x0002
56#define ixIA_DEBUG_REG3 0x0003
57#define ixIA_DEBUG_REG4 0x0004
58#define ixIA_DEBUG_REG5 0x0005
59#define ixIA_DEBUG_REG6 0x0006
60#define ixIA_DEBUG_REG7 0x0007
61#define ixIA_DEBUG_REG8 0x0008
62#define ixIA_DEBUG_REG9 0x0009
63#define ixPA_SC_DEBUG_REG0 0x0000
64#define ixPA_SC_DEBUG_REG1 0x0001
65#define ixSETUP_DEBUG_REG0 0x0018
66#define ixSETUP_DEBUG_REG1 0x0019
67#define ixSETUP_DEBUG_REG2 0x001A
68#define ixSETUP_DEBUG_REG3 0x001B
69#define ixSETUP_DEBUG_REG4 0x001C
70#define ixSETUP_DEBUG_REG5 0x001D
71#define ixSQ_DEBUG_CTRL_LOCAL 0x0009
72#define ixSQ_DEBUG_STS_LOCAL 0x0008
73#define ixSQ_INTERRUPT_WORD_AUTO 0x20C0
74#define ixSQ_INTERRUPT_WORD_CMN 0x20C0
75#define ixSQ_INTERRUPT_WORD_WAVE 0x20C0
76#define ixSQ_WAVE_EXEC_HI 0x027F
77#define ixSQ_WAVE_EXEC_LO 0x027E
78#define ixSQ_WAVE_GPR_ALLOC 0x0015
79#define ixSQ_WAVE_HW_ID 0x0014
80#define ixSQ_WAVE_IB_DBG0 0x001C
81#define ixSQ_WAVE_IB_STS 0x0017
82#define ixSQ_WAVE_INST_DW0 0x001A
83#define ixSQ_WAVE_INST_DW1 0x001B
84#define ixSQ_WAVE_LDS_ALLOC 0x0016
85#define ixSQ_WAVE_M0 0x027C
86#define ixSQ_WAVE_MODE 0x0011
87#define ixSQ_WAVE_PC_HI 0x0019
88#define ixSQ_WAVE_PC_LO 0x0018
89#define ixSQ_WAVE_STATUS 0x0012
90#define ixSQ_WAVE_TBA_HI 0x026D
91#define ixSQ_WAVE_TBA_LO 0x026C
92#define ixSQ_WAVE_TMA_HI 0x026F
93#define ixSQ_WAVE_TMA_LO 0x026E
94#define ixSQ_WAVE_TRAPSTS 0x0013
95#define ixSQ_WAVE_TTMP0 0x0270
96#define ixSQ_WAVE_TTMP10 0x027A
97#define ixSQ_WAVE_TTMP1 0x0271
98#define ixSQ_WAVE_TTMP11 0x027B
99#define ixSQ_WAVE_TTMP2 0x0272
100#define ixSQ_WAVE_TTMP3 0x0273
101#define ixSQ_WAVE_TTMP4 0x0274
102#define ixSQ_WAVE_TTMP5 0x0275
103#define ixSQ_WAVE_TTMP6 0x0276
104#define ixSQ_WAVE_TTMP7 0x0277
105#define ixSQ_WAVE_TTMP8 0x0278
106#define ixSQ_WAVE_TTMP9 0x0279
107#define ixSXIFCCG_DEBUG_REG0 0x0014
108#define ixSXIFCCG_DEBUG_REG1 0x0015
109#define ixSXIFCCG_DEBUG_REG2 0x0016
110#define ixSXIFCCG_DEBUG_REG3 0x0017
111#define ixVGT_DEBUG_REG0 0x0000
112#define ixVGT_DEBUG_REG10 0x000A
113#define ixVGT_DEBUG_REG1 0x0001
114#define ixVGT_DEBUG_REG11 0x000B
115#define ixVGT_DEBUG_REG12 0x000C
116#define ixVGT_DEBUG_REG13 0x000D
117#define ixVGT_DEBUG_REG14 0x000E
118#define ixVGT_DEBUG_REG15 0x000F
119#define ixVGT_DEBUG_REG16 0x0010
120#define ixVGT_DEBUG_REG17 0x0011
121#define ixVGT_DEBUG_REG18 0x0012
122#define ixVGT_DEBUG_REG19 0x0013
123#define ixVGT_DEBUG_REG20 0x0014
124#define ixVGT_DEBUG_REG2 0x0002
125#define ixVGT_DEBUG_REG21 0x0015
126#define ixVGT_DEBUG_REG22 0x0016
127#define ixVGT_DEBUG_REG23 0x0017
128#define ixVGT_DEBUG_REG24 0x0018
129#define ixVGT_DEBUG_REG25 0x0019
130#define ixVGT_DEBUG_REG26 0x001A
131#define ixVGT_DEBUG_REG27 0x001B
132#define ixVGT_DEBUG_REG28 0x001C
133#define ixVGT_DEBUG_REG29 0x001D
134#define ixVGT_DEBUG_REG30 0x001E
135#define ixVGT_DEBUG_REG3 0x0003
136#define ixVGT_DEBUG_REG31 0x001F
137#define ixVGT_DEBUG_REG32 0x0020
138#define ixVGT_DEBUG_REG33 0x0021
139#define ixVGT_DEBUG_REG34 0x0022
140#define ixVGT_DEBUG_REG35 0x0023
141#define ixVGT_DEBUG_REG36 0x0024
142#define ixVGT_DEBUG_REG4 0x0004
143#define ixVGT_DEBUG_REG5 0x0005
144#define ixVGT_DEBUG_REG6 0x0006
145#define ixVGT_DEBUG_REG7 0x0007
146#define ixVGT_DEBUG_REG8 0x0008
147#define ixVGT_DEBUG_REG9 0x0009
148#define mmBCI_DEBUG_READ 0x24E3
149#define mmCB_BLEND0_CONTROL 0xA1E0
150#define mmCB_BLEND1_CONTROL 0xA1E1
151#define mmCB_BLEND2_CONTROL 0xA1E2
152#define mmCB_BLEND3_CONTROL 0xA1E3
153#define mmCB_BLEND4_CONTROL 0xA1E4
154#define mmCB_BLEND5_CONTROL 0xA1E5
155#define mmCB_BLEND6_CONTROL 0xA1E6
156#define mmCB_BLEND7_CONTROL 0xA1E7
157#define mmCB_BLEND_ALPHA 0xA108
158#define mmCB_BLEND_BLUE 0xA107
159#define mmCB_BLEND_GREEN 0xA106
160#define mmCB_BLEND_RED 0xA105
161#define mmCB_CGTT_SCLK_CTRL 0x2698
162#define mmCB_COLOR0_ATTRIB 0xA31D
163#define mmCB_COLOR0_BASE 0xA318
164#define mmCB_COLOR0_CLEAR_WORD0 0xA323
165#define mmCB_COLOR0_CLEAR_WORD1 0xA324
166#define mmCB_COLOR0_CMASK 0xA31F
167#define mmCB_COLOR0_CMASK_SLICE 0xA320
168#define mmCB_COLOR0_FMASK 0xA321
169#define mmCB_COLOR0_FMASK_SLICE 0xA322
170#define mmCB_COLOR0_INFO 0xA31C
171#define mmCB_COLOR0_PITCH 0xA319
172#define mmCB_COLOR0_SLICE 0xA31A
173#define mmCB_COLOR0_VIEW 0xA31B
174#define mmCB_COLOR1_ATTRIB 0xA32C
175#define mmCB_COLOR1_BASE 0xA327
176#define mmCB_COLOR1_CLEAR_WORD0 0xA332
177#define mmCB_COLOR1_CLEAR_WORD1 0xA333
178#define mmCB_COLOR1_CMASK 0xA32E
179#define mmCB_COLOR1_CMASK_SLICE 0xA32F
180#define mmCB_COLOR1_FMASK 0xA330
181#define mmCB_COLOR1_FMASK_SLICE 0xA331
182#define mmCB_COLOR1_INFO 0xA32B
183#define mmCB_COLOR1_PITCH 0xA328
184#define mmCB_COLOR1_SLICE 0xA329
185#define mmCB_COLOR1_VIEW 0xA32A
186#define mmCB_COLOR2_ATTRIB 0xA33B
187#define mmCB_COLOR2_BASE 0xA336
188#define mmCB_COLOR2_CLEAR_WORD0 0xA341
189#define mmCB_COLOR2_CLEAR_WORD1 0xA342
190#define mmCB_COLOR2_CMASK 0xA33D
191#define mmCB_COLOR2_CMASK_SLICE 0xA33E
192#define mmCB_COLOR2_FMASK 0xA33F
193#define mmCB_COLOR2_FMASK_SLICE 0xA340
194#define mmCB_COLOR2_INFO 0xA33A
195#define mmCB_COLOR2_PITCH 0xA337
196#define mmCB_COLOR2_SLICE 0xA338
197#define mmCB_COLOR2_VIEW 0xA339
198#define mmCB_COLOR3_ATTRIB 0xA34A
199#define mmCB_COLOR3_BASE 0xA345
200#define mmCB_COLOR3_CLEAR_WORD0 0xA350
201#define mmCB_COLOR3_CLEAR_WORD1 0xA351
202#define mmCB_COLOR3_CMASK 0xA34C
203#define mmCB_COLOR3_CMASK_SLICE 0xA34D
204#define mmCB_COLOR3_FMASK 0xA34E
205#define mmCB_COLOR3_FMASK_SLICE 0xA34F
206#define mmCB_COLOR3_INFO 0xA349
207#define mmCB_COLOR3_PITCH 0xA346
208#define mmCB_COLOR3_SLICE 0xA347
209#define mmCB_COLOR3_VIEW 0xA348
210#define mmCB_COLOR4_ATTRIB 0xA359
211#define mmCB_COLOR4_BASE 0xA354
212#define mmCB_COLOR4_CLEAR_WORD0 0xA35F
213#define mmCB_COLOR4_CLEAR_WORD1 0xA360
214#define mmCB_COLOR4_CMASK 0xA35B
215#define mmCB_COLOR4_CMASK_SLICE 0xA35C
216#define mmCB_COLOR4_FMASK 0xA35D
217#define mmCB_COLOR4_FMASK_SLICE 0xA35E
218#define mmCB_COLOR4_INFO 0xA358
219#define mmCB_COLOR4_PITCH 0xA355
220#define mmCB_COLOR4_SLICE 0xA356
221#define mmCB_COLOR4_VIEW 0xA357
222#define mmCB_COLOR5_ATTRIB 0xA368
223#define mmCB_COLOR5_BASE 0xA363
224#define mmCB_COLOR5_CLEAR_WORD0 0xA36E
225#define mmCB_COLOR5_CLEAR_WORD1 0xA36F
226#define mmCB_COLOR5_CMASK 0xA36A
227#define mmCB_COLOR5_CMASK_SLICE 0xA36B
228#define mmCB_COLOR5_FMASK 0xA36C
229#define mmCB_COLOR5_FMASK_SLICE 0xA36D
230#define mmCB_COLOR5_INFO 0xA367
231#define mmCB_COLOR5_PITCH 0xA364
232#define mmCB_COLOR5_SLICE 0xA365
233#define mmCB_COLOR5_VIEW 0xA366
234#define mmCB_COLOR6_ATTRIB 0xA377
235#define mmCB_COLOR6_BASE 0xA372
236#define mmCB_COLOR6_CLEAR_WORD0 0xA37D
237#define mmCB_COLOR6_CLEAR_WORD1 0xA37E
238#define mmCB_COLOR6_CMASK 0xA379
239#define mmCB_COLOR6_CMASK_SLICE 0xA37A
240#define mmCB_COLOR6_FMASK 0xA37B
241#define mmCB_COLOR6_FMASK_SLICE 0xA37C
242#define mmCB_COLOR6_INFO 0xA376
243#define mmCB_COLOR6_PITCH 0xA373
244#define mmCB_COLOR6_SLICE 0xA374
245#define mmCB_COLOR6_VIEW 0xA375
246#define mmCB_COLOR7_ATTRIB 0xA386
247#define mmCB_COLOR7_BASE 0xA381
248#define mmCB_COLOR7_CLEAR_WORD0 0xA38C
249#define mmCB_COLOR7_CLEAR_WORD1 0xA38D
250#define mmCB_COLOR7_CMASK 0xA388
251#define mmCB_COLOR7_CMASK_SLICE 0xA389
252#define mmCB_COLOR7_FMASK 0xA38A
253#define mmCB_COLOR7_FMASK_SLICE 0xA38B
254#define mmCB_COLOR7_INFO 0xA385
255#define mmCB_COLOR7_PITCH 0xA382
256#define mmCB_COLOR7_SLICE 0xA383
257#define mmCB_COLOR7_VIEW 0xA384
258#define mmCB_COLOR_CONTROL 0xA202
259#define mmCB_DEBUG_BUS_10 0x26A2
260#define mmCB_DEBUG_BUS_1 0x2699
261#define mmCB_DEBUG_BUS_11 0x26A3
262#define mmCB_DEBUG_BUS_12 0x26A4
263#define mmCB_DEBUG_BUS_13 0x26A5
264#define mmCB_DEBUG_BUS_14 0x26A6
265#define mmCB_DEBUG_BUS_15 0x26A7
266#define mmCB_DEBUG_BUS_16 0x26A8
267#define mmCB_DEBUG_BUS_17 0x26A9
268#define mmCB_DEBUG_BUS_18 0x26AA
269#define mmCB_DEBUG_BUS_2 0x269A
270#define mmCB_DEBUG_BUS_3 0x269B
271#define mmCB_DEBUG_BUS_4 0x269C
272#define mmCB_DEBUG_BUS_5 0x269D
273#define mmCB_DEBUG_BUS_6 0x269E
274#define mmCB_DEBUG_BUS_7 0x269F
275#define mmCB_DEBUG_BUS_8 0x26A0
276#define mmCB_DEBUG_BUS_9 0x26A1
277#define mmCB_HW_CONTROL 0x2684
278#define mmCB_HW_CONTROL_1 0x2685
279#define mmCB_HW_CONTROL_2 0x2686
280#define mmCB_PERFCOUNTER0_HI 0x2691
281#define mmCB_PERFCOUNTER0_LO 0x2690
282#define mmCB_PERFCOUNTER0_SELECT1 0x2689
283#define mmCB_PERFCOUNTER1_HI 0x2693
284#define mmCB_PERFCOUNTER1_LO 0x2692
285#define mmCB_PERFCOUNTER2_HI 0x2695
286#define mmCB_PERFCOUNTER2_LO 0x2694
287#define mmCB_PERFCOUNTER3_HI 0x2697
288#define mmCB_PERFCOUNTER3_LO 0x2696
289#define mmCB_SHADER_MASK 0xA08F
290#define mmCB_TARGET_MASK 0xA08E
291#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F
292#define mmCC_RB_BACKEND_DISABLE 0x263D
293#define mmCC_RB_DAISY_CHAIN 0x2641
294#define mmCC_RB_REDUNDANCY 0x263C
295#define mmCC_SQC_BANK_DISABLE 0x2307
296#define mmCGTS_RD_CTRL_REG 0x2455
297#define mmCGTS_RD_REG 0x2456
298#define mmCGTS_SM_CTRL_REG 0x2454
299#define mmCGTS_TCC_DISABLE 0x2452
300#define mmCGTS_USER_TCC_DISABLE 0x2453
301#define mmCGTT_BCI_CLK_CTRL 0x24A9
302#define mmCGTT_CP_CLK_CTRL 0x3059
303#define mmCGTT_GDS_CLK_CTRL 0x25DD
304#define mmCGTT_IA_CLK_CTRL 0x2261
305#define mmCGTT_PA_CLK_CTRL 0x2286
306#define mmCGTT_PC_CLK_CTRL 0x24A8
307#define mmCGTT_RLC_CLK_CTRL 0x30E0
308#define mmCGTT_SC_CLK_CTRL 0x22CA
309#define mmCGTT_SPI_CLK_CTRL 0x2451
310#define mmCGTT_SQ_CLK_CTRL 0x2362
311#define mmCGTT_SQG_CLK_CTRL 0x2363
312#define mmCGTT_SX_CLK_CTRL0 0x240C
313#define mmCGTT_SX_CLK_CTRL1 0x240D
314#define mmCGTT_SX_CLK_CTRL2 0x240E
315#define mmCGTT_SX_CLK_CTRL3 0x240F
316#define mmCGTT_SX_CLK_CTRL4 0x2410
317#define mmCGTT_TCI_CLK_CTRL 0x2B60
318#define mmCGTT_TCP_CLK_CTRL 0x2B15
319#define mmCGTT_VGT_CLK_CTRL 0x225F
320#define mmCOHER_DEST_BASE_0 0xA092
321#define mmCOHER_DEST_BASE_1 0xA093
322#define mmCOHER_DEST_BASE_2 0xA07E
323#define mmCOHER_DEST_BASE_3 0xA07F
324#define mmCOMPUTE_DIM_X 0x2E01
325#define mmCOMPUTE_DIM_Y 0x2E02
326#define mmCOMPUTE_DIM_Z 0x2E03
327#define mmCOMPUTE_DISPATCH_INITIATOR 0x2E00
328#define mmCOMPUTE_NUM_THREAD_X 0x2E07
329#define mmCOMPUTE_NUM_THREAD_Y 0x2E08
330#define mmCOMPUTE_NUM_THREAD_Z 0x2E09
331#define mmCOMPUTE_PGM_HI 0x2E0D
332#define mmCOMPUTE_PGM_LO 0x2E0C
333#define mmCOMPUTE_PGM_RSRC1 0x2E12
334#define mmCOMPUTE_PGM_RSRC2 0x2E13
335#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15
336#define mmCOMPUTE_START_X 0x2E04
337#define mmCOMPUTE_START_Y 0x2E05
338#define mmCOMPUTE_START_Z 0x2E06
339#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2E16
340#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2E17
341#define mmCOMPUTE_TBA_HI 0x2E0F
342#define mmCOMPUTE_TBA_LO 0x2E0E
343#define mmCOMPUTE_TMA_HI 0x2E11
344#define mmCOMPUTE_TMA_LO 0x2E10
345#define mmCOMPUTE_TMPRING_SIZE 0x2E18
346#define mmCOMPUTE_USER_DATA_0 0x2E40
347#define mmCOMPUTE_USER_DATA_10 0x2E4A
348#define mmCOMPUTE_USER_DATA_1 0x2E41
349#define mmCOMPUTE_USER_DATA_11 0x2E4B
350#define mmCOMPUTE_USER_DATA_12 0x2E4C
351#define mmCOMPUTE_USER_DATA_13 0x2E4D
352#define mmCOMPUTE_USER_DATA_14 0x2E4E
353#define mmCOMPUTE_USER_DATA_15 0x2E4F
354#define mmCOMPUTE_USER_DATA_2 0x2E42
355#define mmCOMPUTE_USER_DATA_3 0x2E43
356#define mmCOMPUTE_USER_DATA_4 0x2E44
357#define mmCOMPUTE_USER_DATA_5 0x2E45
358#define mmCOMPUTE_USER_DATA_6 0x2E46
359#define mmCOMPUTE_USER_DATA_7 0x2E47
360#define mmCOMPUTE_USER_DATA_8 0x2E48
361#define mmCOMPUTE_USER_DATA_9 0x2E49
362#define mmCOMPUTE_VMID 0x2E14
363#define mmCP_APPEND_ADDR_HI 0x2159
364#define mmCP_APPEND_ADDR_LO 0x2158
365#define mmCP_APPEND_DATA 0x215A
366#define mmCP_APPEND_LAST_CS_FENCE 0x215B
367#define mmCP_APPEND_LAST_PS_FENCE 0x215C
368#define mmCP_ATOMIC_PREOP_HI 0x215E
369#define mmCP_ATOMIC_PREOP_LO 0x215D
370#define mmCP_BUSY_STAT 0x219F
371#define mmCP_CE_HEADER_DUMP 0x21A4
372#define mmCP_CE_IB1_BASE_HI 0x21C7
373#define mmCP_CE_IB1_BASE_LO 0x21C6
374#define mmCP_CE_IB1_BUFSZ 0x21C8
375#define mmCP_CE_IB2_BASE_HI 0x21CA
376#define mmCP_CE_IB2_BASE_LO 0x21C9
377#define mmCP_CE_IB2_BUFSZ 0x21CB
378#define mmCP_CE_INIT_BASE_HI 0x21C4
379#define mmCP_CE_INIT_BASE_LO 0x21C3
380#define mmCP_CE_INIT_BUFSZ 0x21C5
381#define mmCP_CEQ1_AVAIL 0x21E6
382#define mmCP_CEQ2_AVAIL 0x21E7
383#define mmCP_CE_ROQ_IB1_STAT 0x21E9
384#define mmCP_CE_ROQ_IB2_STAT 0x21EA
385#define mmCP_CE_ROQ_RB_STAT 0x21E8
386#define mmCP_CE_UCODE_ADDR 0x305A
387#define mmCP_CE_UCODE_DATA 0x305B
388#define mmCP_CMD_DATA 0x21DF
389#define mmCP_CMD_INDEX 0x21DE
390#define mmCP_CNTX_STAT 0x21B8
391#define mmCP_COHER_BASE 0x217E
392#define mmCP_COHER_CNTL 0x217C
393#define mmCP_COHER_SIZE 0x217D
394#define mmCP_COHER_START_DELAY 0x217B
395#define mmCP_COHER_STATUS 0x217F
396#define mmCP_CSF_CNTL 0x21B5
397#define mmCP_CSF_STAT 0x21B4
398#define mmCP_DMA_CNTL 0x218A
399#define mmCP_DMA_ME_COMMAND 0x2184
400#define mmCP_DMA_ME_DST_ADDR 0x2182
401#define mmCP_DMA_ME_DST_ADDR_HI 0x2183
402#define mmCP_DMA_ME_SRC_ADDR 0x2180
403#define mmCP_DMA_ME_SRC_ADDR_HI 0x2181
404#define mmCP_DMA_PFP_COMMAND 0x2189
405#define mmCP_DMA_PFP_DST_ADDR 0x2187
406#define mmCP_DMA_PFP_DST_ADDR_HI 0x2188
407#define mmCP_DMA_PFP_SRC_ADDR 0x2185
408#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2186
409#define mmCP_DMA_READ_TAGS 0x218B
410#define mmCP_ECC_FIRSTOCCURRENCE 0x307A
411#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307B
412#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307C
413#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307D
414#define mmCP_EOP_DONE_ADDR_HI 0x2101
415#define mmCP_EOP_DONE_ADDR_LO 0x2100
416#define mmCP_EOP_DONE_DATA_HI 0x2103
417#define mmCP_EOP_DONE_DATA_LO 0x2102
418#define mmCP_EOP_LAST_FENCE_HI 0x2105
419#define mmCP_EOP_LAST_FENCE_LO 0x2104
420#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2160
421#define mmCP_GDS_ATOMIC0_PREOP_LO 0x215F
422#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2162
423#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2161
424#define mmCP_GRBM_FREE_COUNT 0x21A3
425#define mmCP_IB1_BASE_HI 0x21CD
426#define mmCP_IB1_BASE_LO 0x21CC
427#define mmCP_IB1_BUFSZ 0x21CE
428#define mmCP_IB1_OFFSET 0x2192
429#define mmCP_IB1_PREAMBLE_BEGIN 0x2194
430#define mmCP_IB1_PREAMBLE_END 0x2195
431#define mmCP_IB2_BASE_HI 0x21D0
432#define mmCP_IB2_BASE_LO 0x21CF
433#define mmCP_IB2_BUFSZ 0x21D1
434#define mmCP_IB2_OFFSET 0x2193
435#define mmCP_IB2_PREAMBLE_BEGIN 0x2196
436#define mmCP_IB2_PREAMBLE_END 0x2197
437#define mmCP_INT_CNTL 0x3049
438#define mmCP_INT_CNTL_RING0 0x306A
439#define mmCP_INT_CNTL_RING1 0x306B
440#define mmCP_INT_CNTL_RING2 0x306C
441#define mmCP_INT_STAT_DEBUG 0x21F7
442#define mmCP_INT_STATUS 0x304A
443#define mmCP_INT_STATUS_RING0 0x306D
444#define mmCP_INT_STATUS_RING1 0x306E
445#define mmCP_INT_STATUS_RING2 0x306F
446#define mmCP_MC_PACK_DELAY_CNT 0x21A7
447#define mmCP_ME_CNTL 0x21B6
448#define mmCP_ME_HEADER_DUMP 0x21A1
449#define mmCP_ME_MC_RADDR_HI 0x216E
450#define mmCP_ME_MC_RADDR_LO 0x216D
451#define mmCP_ME_MC_WADDR_HI 0x216A
452#define mmCP_ME_MC_WADDR_LO 0x2169
453#define mmCP_ME_MC_WDATA_HI 0x216C
454#define mmCP_ME_MC_WDATA_LO 0x216B
455#define mmCP_MEM_SLP_CNTL 0x3079
456#define mmCP_ME_PREEMPTION 0x21B9
457#define mmCP_MEQ_AVAIL 0x21DD
458#define mmCP_MEQ_STAT 0x21E5
459#define mmCP_MEQ_THRESHOLDS 0x21D9
460#define mmCP_ME_RAM_DATA 0x3058
461#define mmCP_ME_RAM_RADDR 0x3056
462#define mmCP_ME_RAM_WADDR 0x3057
463#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x210B
464#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x210A
465#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x210F
466#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x210E
467#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2113
468#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2112
469#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2117
470#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2116
471#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2109
472#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2108
473#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x210D
474#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x210C
475#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2111
476#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2110
477#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2115
478#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2114
479#define mmCP_PA_CINVOC_COUNT_HI 0x2129
480#define mmCP_PA_CINVOC_COUNT_LO 0x2128
481#define mmCP_PA_CPRIM_COUNT_HI 0x212B
482#define mmCP_PA_CPRIM_COUNT_LO 0x212A
483#define mmCP_PERFMON_CNTL 0x21FF
484#define mmCP_PERFMON_CNTX_CNTL 0xA0D8
485#define mmCP_PFP_HEADER_DUMP 0x21A2
486#define mmCP_PFP_IB_CONTROL 0x218D
487#define mmCP_PFP_LOAD_CONTROL 0x218E
488#define mmCP_PFP_UCODE_ADDR 0x3054
489#define mmCP_PFP_UCODE_DATA 0x3055
490#define mmCP_PIPE_STATS_ADDR_HI 0x2119
491#define mmCP_PIPE_STATS_ADDR_LO 0x2118
492#define mmCP_PWR_CNTL 0x3078
493#define mmCP_QUEUE_THRESHOLDS 0x21D8
494#define mmCP_RB0_BASE 0x3040
495#define mmCP_RB0_CNTL 0x3041
496#define mmCP_RB0_RPTR 0x21C0
497#define mmCP_RB0_RPTR_ADDR 0x3043
498#define mmCP_RB0_RPTR_ADDR_HI 0x3044
499#define mmCP_RB0_WPTR 0x3045
500#define mmCP_RB1_BASE 0x3060
501#define mmCP_RB1_CNTL 0x3061
502#define mmCP_RB1_RPTR 0x21BF
503#define mmCP_RB1_RPTR_ADDR 0x3062
504#define mmCP_RB1_RPTR_ADDR_HI 0x3063
505#define mmCP_RB1_WPTR 0x3064
506#define mmCP_RB2_BASE 0x3065
507#define mmCP_RB2_CNTL 0x3066
508#define mmCP_RB2_RPTR 0x21BE
509#define mmCP_RB2_RPTR_ADDR 0x3067
510#define mmCP_RB2_RPTR_ADDR_HI 0x3068
511#define mmCP_RB2_WPTR 0x3069
512#define mmCP_RB_BASE 0x3040
513#define mmCP_RB_CNTL 0x3041
514#define mmCP_RB_OFFSET 0x2191
515#define mmCP_RB_RPTR 0x21C0
516#define mmCP_RB_RPTR_ADDR 0x3043
517#define mmCP_RB_RPTR_ADDR_HI 0x3044
518#define mmCP_RB_RPTR_WR 0x3042
519#define mmCP_RB_VMID 0x3051
520#define mmCP_RB_WPTR 0x3045
521#define mmCP_RB_WPTR_DELAY 0x21C1
522#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047
523#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046
524#define mmCP_RB_WPTR_POLL_CNTL 0x21C2
525#define mmCP_RING0_PRIORITY 0x304D
526#define mmCP_RING1_PRIORITY 0x304E
527#define mmCP_RING2_PRIORITY 0x304F
528#define mmCP_RINGID 0xA0D9
529#define mmCP_RING_PRIORITY_CNTS 0x304C
530#define mmCP_ROQ1_THRESHOLDS 0x21D5
531#define mmCP_ROQ2_AVAIL 0x21DC
532#define mmCP_ROQ2_THRESHOLDS 0x21D6
533#define mmCP_ROQ_AVAIL 0x21DA
534#define mmCP_ROQ_IB1_STAT 0x21E1
535#define mmCP_ROQ_IB2_STAT 0x21E2
536#define mmCP_ROQ_RB_STAT 0x21E0
537#define mmCP_SC_PSINVOC_COUNT0_HI 0x212D
538#define mmCP_SC_PSINVOC_COUNT0_LO 0x212C
539#define mmCP_SC_PSINVOC_COUNT1_HI 0x212F
540#define mmCP_SC_PSINVOC_COUNT1_LO 0x212E
541#define mmCP_SCRATCH_DATA 0x2190
542#define mmCP_SCRATCH_INDEX 0x218F
543#define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0x2172
544#define mmCP_SEM_WAIT_TIMER 0x216F
545#define mmCP_SIG_SEM_ADDR_HI 0x2171
546#define mmCP_SIG_SEM_ADDR_LO 0x2170
547#define mmCP_STALLED_STAT1 0x219D
548#define mmCP_STALLED_STAT2 0x219E
549#define mmCP_STALLED_STAT3 0x219C
550#define mmCP_STAT 0x21A0
551#define mmCP_ST_BASE_HI 0x21D3
552#define mmCP_ST_BASE_LO 0x21D2
553#define mmCP_ST_BUFSZ 0x21D4
554#define mmCP_STQ_AVAIL 0x21DB
555#define mmCP_STQ_STAT 0x21E3
556#define mmCP_STQ_THRESHOLDS 0x21D7
557#define mmCP_STREAM_OUT_ADDR_HI 0x2107
558#define mmCP_STREAM_OUT_ADDR_LO 0x2106
559#define mmCP_STRMOUT_CNTL 0x213F
560#define mmCP_VGT_CSINVOC_COUNT_HI 0x2131
561#define mmCP_VGT_CSINVOC_COUNT_LO 0x2130
562#define mmCP_VGT_DSINVOC_COUNT_HI 0x2127
563#define mmCP_VGT_DSINVOC_COUNT_LO 0x2126
564#define mmCP_VGT_GSINVOC_COUNT_HI 0x2123
565#define mmCP_VGT_GSINVOC_COUNT_LO 0x2122
566#define mmCP_VGT_GSPRIM_COUNT_HI 0x211F
567#define mmCP_VGT_GSPRIM_COUNT_LO 0x211E
568#define mmCP_VGT_HSINVOC_COUNT_HI 0x2125
569#define mmCP_VGT_HSINVOC_COUNT_LO 0x2124
570#define mmCP_VGT_IAPRIM_COUNT_HI 0x211D
571#define mmCP_VGT_IAPRIM_COUNT_LO 0x211C
572#define mmCP_VGT_IAVERT_COUNT_HI 0x211B
573#define mmCP_VGT_IAVERT_COUNT_LO 0x211A
574#define mmCP_VGT_VSINVOC_COUNT_HI 0x2121
575#define mmCP_VGT_VSINVOC_COUNT_LO 0x2120
576#define mmCP_VMID 0xA0DA
577#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2174
578#define mmCP_WAIT_SEM_ADDR_HI 0x2176
579#define mmCP_WAIT_SEM_ADDR_LO 0x2175
580#define mmCS_COPY_STATE 0xA1F3
581#define mmDB_ALPHA_TO_MASK 0xA2DC
582#define mmDB_CGTT_CLK_CTRL_0 0x261A
583#define mmDB_COUNT_CONTROL 0xA001
584#define mmDB_CREDIT_LIMIT 0x2614
585#define mmDB_DEBUG 0x260C
586#define mmDB_DEBUG2 0x260D
587#define mmDB_DEBUG3 0x260E
588#define mmDB_DEBUG4 0x260F
589#define mmDB_DEPTH_BOUNDS_MAX 0xA009
590#define mmDB_DEPTH_BOUNDS_MIN 0xA008
591#define mmDB_DEPTH_CLEAR 0xA00B
592#define mmDB_DEPTH_CONTROL 0xA200
593#define mmDB_DEPTH_INFO 0xA00F
594#define mmDB_DEPTH_SIZE 0xA016
595#define mmDB_DEPTH_SLICE 0xA017
596#define mmDB_DEPTH_VIEW 0xA002
597#define mmDB_EQAA 0xA201
598#define mmDB_FIFO_DEPTH1 0x2618
599#define mmDB_FIFO_DEPTH2 0x2619
600#define mmDB_FREE_CACHELINES 0x2617
601#define mmDB_HTILE_DATA_BASE 0xA005
602#define mmDB_HTILE_SURFACE 0xA2AF
603#define mmDB_PERFCOUNTER0_HI 0x2602
604#define mmDB_PERFCOUNTER0_LO 0x2601
605#define mmDB_PERFCOUNTER0_SELECT 0x2600
606#define mmDB_PERFCOUNTER1_HI 0x2605
607#define mmDB_PERFCOUNTER1_LO 0x2604
608#define mmDB_PERFCOUNTER1_SELECT 0x2603
609#define mmDB_PERFCOUNTER2_HI 0x2608
610#define mmDB_PERFCOUNTER2_LO 0x2607
611#define mmDB_PERFCOUNTER2_SELECT 0x2606
612#define mmDB_PERFCOUNTER3_HI 0x260B
613#define mmDB_PERFCOUNTER3_LO 0x260A
614#define mmDB_PERFCOUNTER3_SELECT 0x2609
615#define mmDB_PRELOAD_CONTROL 0xA2B2
616#define mmDB_READ_DEBUG_0 0x2620
617#define mmDB_READ_DEBUG_1 0x2621
618#define mmDB_READ_DEBUG_2 0x2622
619#define mmDB_READ_DEBUG_3 0x2623
620#define mmDB_READ_DEBUG_4 0x2624
621#define mmDB_READ_DEBUG_5 0x2625
622#define mmDB_READ_DEBUG_6 0x2626
623#define mmDB_READ_DEBUG_7 0x2627
624#define mmDB_READ_DEBUG_8 0x2628
625#define mmDB_READ_DEBUG_9 0x2629
626#define mmDB_READ_DEBUG_A 0x262A
627#define mmDB_READ_DEBUG_B 0x262B
628#define mmDB_READ_DEBUG_C 0x262C
629#define mmDB_READ_DEBUG_D 0x262D
630#define mmDB_READ_DEBUG_E 0x262E
631#define mmDB_READ_DEBUG_F 0x262F
632#define mmDB_RENDER_CONTROL 0xA000
633#define mmDB_RENDER_OVERRIDE 0xA003
634#define mmDB_RENDER_OVERRIDE2 0xA004
635#define mmDB_SHADER_CONTROL 0xA203
636#define mmDB_SRESULTS_COMPARE_STATE0 0xA2B0
637#define mmDB_SRESULTS_COMPARE_STATE1 0xA2B1
638#define mmDB_STENCIL_CLEAR 0xA00A
639#define mmDB_STENCIL_CONTROL 0xA10B
640#define mmDB_STENCIL_INFO 0xA011
641#define mmDB_STENCIL_READ_BASE 0xA013
642#define mmDB_STENCILREFMASK 0xA10C
643#define mmDB_STENCILREFMASK_BF 0xA10D
644#define mmDB_STENCIL_WRITE_BASE 0xA015
645#define mmDB_SUBTILE_CONTROL 0x2616
646#define mmDB_WATERMARKS 0x2615
647#define mmDB_Z_INFO 0xA010
648#define mmDB_ZPASS_COUNT_HI 0x261D
649#define mmDB_ZPASS_COUNT_LOW 0x261C
650#define mmDB_Z_READ_BASE 0xA012
651#define mmDB_Z_WRITE_BASE 0xA014
652#define mmDEBUG_DATA 0x203D
653#define mmDEBUG_INDEX 0x203C
654#define mmGB_ADDR_CONFIG 0x263E
655#define mmGB_BACKEND_MAP 0x263F
656#define mmGB_EDC_MODE 0x307E
657#define mmGB_GPU_ID 0x2640
658#define mmGB_TILE_MODE0 0x2644
659#define mmGB_TILE_MODE10 0x264E
660#define mmGB_TILE_MODE1 0x2645
661#define mmGB_TILE_MODE11 0x264F
662#define mmGB_TILE_MODE12 0x2650
663#define mmGB_TILE_MODE13 0x2651
664#define mmGB_TILE_MODE14 0x2652
665#define mmGB_TILE_MODE15 0x2653
666#define mmGB_TILE_MODE16 0x2654
667#define mmGB_TILE_MODE17 0x2655
668#define mmGB_TILE_MODE18 0x2656
669#define mmGB_TILE_MODE19 0x2657
670#define mmGB_TILE_MODE20 0x2658
671#define mmGB_TILE_MODE2 0x2646
672#define mmGB_TILE_MODE21 0x2659
673#define mmGB_TILE_MODE22 0x265A
674#define mmGB_TILE_MODE23 0x265B
675#define mmGB_TILE_MODE24 0x265C
676#define mmGB_TILE_MODE25 0x265D
677#define mmGB_TILE_MODE26 0x265E
678#define mmGB_TILE_MODE27 0x265F
679#define mmGB_TILE_MODE28 0x2660
680#define mmGB_TILE_MODE29 0x2661
681#define mmGB_TILE_MODE30 0x2662
682#define mmGB_TILE_MODE3 0x2647
683#define mmGB_TILE_MODE31 0x2663
684#define mmGB_TILE_MODE4 0x2648
685#define mmGB_TILE_MODE5 0x2649
686#define mmGB_TILE_MODE6 0x264A
687#define mmGB_TILE_MODE7 0x264B
688#define mmGB_TILE_MODE8 0x264C
689#define mmGB_TILE_MODE9 0x264D
690#define mmGC_PRIV_MODE 0x3048
691#define mmGC_USER_RB_BACKEND_DISABLE 0x26DF
692#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270
693#define mmGDS_ATOM_BASE 0x25CE
694#define mmGDS_ATOM_CNTL 0x25CC
695#define mmGDS_ATOM_COMPLETE 0x25CD
696#define mmGDS_ATOM_DST 0x25D2
697#define mmGDS_ATOM_OFFSET0 0x25D0
698#define mmGDS_ATOM_OFFSET1 0x25D1
699#define mmGDS_ATOM_OP 0x25D3
700#define mmGDS_ATOM_READ0 0x25D8
701#define mmGDS_ATOM_READ0_U 0x25D9
702#define mmGDS_ATOM_READ1 0x25DA
703#define mmGDS_ATOM_READ1_U 0x25DB
704#define mmGDS_ATOM_SIZE 0x25CF
705#define mmGDS_ATOM_SRC0 0x25D4
706#define mmGDS_ATOM_SRC0_U 0x25D5
707#define mmGDS_ATOM_SRC1 0x25D6
708#define mmGDS_ATOM_SRC1_U 0x25D7
709#define mmGDS_CNTL_STATUS 0x25C1
710#define mmGDS_CONFIG 0x25C0
711#define mmGDS_DEBUG_CNTL 0x25DE
712#define mmGDS_DEBUG_DATA 0x25DF
713#define mmGDS_ENHANCE 0x25DC
714#define mmGDS_GRBM_SECDED_CNT 0x25E3
715#define mmGDS_GWS_RESOURCE 0x25E1
716#define mmGDS_GWS_RESOURCE_CNTL 0x25E0
717#define mmGDS_OA_DED 0x25E4
718#define mmGDS_PERFCOUNTER0_HI 0x25E7
719#define mmGDS_PERFCOUNTER0_LO 0x25E6
720#define mmGDS_PERFCOUNTER0_SELECT 0x25E5
721#define mmGDS_PERFCOUNTER1_HI 0x25EA
722#define mmGDS_PERFCOUNTER1_LO 0x25E9
723#define mmGDS_PERFCOUNTER1_SELECT 0x25E8
724#define mmGDS_PERFCOUNTER2_HI 0x25ED
725#define mmGDS_PERFCOUNTER2_LO 0x25EC
726#define mmGDS_PERFCOUNTER2_SELECT 0x25EB
727#define mmGDS_PERFCOUNTER3_HI 0x25F0
728#define mmGDS_PERFCOUNTER3_LO 0x25EF
729#define mmGDS_PERFCOUNTER3_SELECT 0x25EE
730#define mmGDS_RD_ADDR 0x25C2
731#define mmGDS_RD_BURST_ADDR 0x25C4
732#define mmGDS_RD_BURST_COUNT 0x25C5
733#define mmGDS_RD_BURST_DATA 0x25C6
734#define mmGDS_RD_DATA 0x25C3
735#define mmGDS_SECDED_CNT 0x25E2
736#define mmGDS_WR_ADDR 0x25C7
737#define mmGDS_WR_BURST_ADDR 0x25C9
738#define mmGDS_WR_BURST_DATA 0x25CA
739#define mmGDS_WR_DATA 0x25C8
740#define mmGDS_WRITE_COMPLETE 0x25CB
741#define mmGFX_COPY_STATE 0xA1F4
742#define mmGRBM_CAM_DATA 0x3001
743#define mmGRBM_CAM_INDEX 0x3000
744#define mmGRBM_CNTL 0x2000
745#define mmGRBM_DEBUG 0x2014
746#define mmGRBM_DEBUG_CNTL 0x2009
747#define mmGRBM_DEBUG_DATA 0x200A
748#define mmGRBM_DEBUG_SNAPSHOT 0x2015
749#define mmGRBM_GFX_CLKEN_CNTL 0x200C
750#define mmGRBM_GFX_INDEX 0x200B
751#define mmGRBM_INT_CNTL 0x2018
752#define mmGRBM_NOWHERE 0x203F
753#define mmGRBM_PERFCOUNTER0_HI 0x201F
754#define mmGRBM_PERFCOUNTER0_LO 0x201E
755#define mmGRBM_PERFCOUNTER0_SELECT 0x201C
756#define mmGRBM_PERFCOUNTER1_HI 0x2021
757#define mmGRBM_PERFCOUNTER1_LO 0x2020
758#define mmGRBM_PERFCOUNTER1_SELECT 0x201D
759#define mmGRBM_PWR_CNTL 0x2003
760#define mmGRBM_READ_ERROR 0x2016
761#define mmGRBM_SCRATCH_REG0 0x2040
762#define mmGRBM_SCRATCH_REG1 0x2041
763#define mmGRBM_SCRATCH_REG2 0x2042
764#define mmGRBM_SCRATCH_REG3 0x2043
765#define mmGRBM_SCRATCH_REG4 0x2044
766#define mmGRBM_SCRATCH_REG5 0x2045
767#define mmGRBM_SCRATCH_REG6 0x2046
768#define mmGRBM_SCRATCH_REG7 0x2047
769#define mmGRBM_SE0_PERFCOUNTER_HI 0x202B
770#define mmGRBM_SE0_PERFCOUNTER_LO 0x202A
771#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x2026
772#define mmGRBM_SE1_PERFCOUNTER_HI 0x202D
773#define mmGRBM_SE1_PERFCOUNTER_LO 0x202C
774#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x2027
775#define mmGRBM_SKEW_CNTL 0x2001
776#define mmGRBM_SOFT_RESET 0x2008
777#define mmGRBM_STATUS 0x2004
778#define mmGRBM_STATUS2 0x2002
779#define mmGRBM_STATUS_SE0 0x2005
780#define mmGRBM_STATUS_SE1 0x2006
781#define mmGRBM_WAIT_IDLE_CLOCKS 0x200D
782#define mmIA_CNTL_STATUS 0x2237
783#define mmIA_DEBUG_CNTL 0x223A
784#define mmIA_DEBUG_DATA 0x223B
785#define mmIA_ENHANCE 0xA29C
786#define mmIA_MULTI_VGT_PARAM 0xA2AA
787#define mmIA_PERFCOUNTER0_HI 0x2225
788#define mmIA_PERFCOUNTER0_LO 0x2224
789#define mmIA_PERFCOUNTER0_SELECT 0x2220
790#define mmIA_PERFCOUNTER1_HI 0x2227
791#define mmIA_PERFCOUNTER1_LO 0x2226
792#define mmIA_PERFCOUNTER1_SELECT 0x2221
793#define mmIA_PERFCOUNTER2_HI 0x2229
794#define mmIA_PERFCOUNTER2_LO 0x2228
795#define mmIA_PERFCOUNTER2_SELECT 0x2222
796#define mmIA_PERFCOUNTER3_HI 0x222B
797#define mmIA_PERFCOUNTER3_LO 0x222A
798#define mmIA_PERFCOUNTER3_SELECT 0x2223
799#define mmIA_VMID_OVERRIDE 0x2260
800#define mmPA_CL_CLIP_CNTL 0xA204
801#define mmPA_CL_CNTL_STATUS 0x2284
802#define mmPA_CL_ENHANCE 0x2285
803#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA2FC
804#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA2FD
805#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA2FA
806#define mmPA_CL_GB_VERT_DISC_ADJ 0xA2FB
807#define mmPA_CL_NANINF_CNTL 0xA208
808#define mmPA_CL_POINT_CULL_RAD 0xA1F8
809#define mmPA_CL_POINT_SIZE 0xA1F7
810#define mmPA_CL_POINT_X_RAD 0xA1F5
811#define mmPA_CL_POINT_Y_RAD 0xA1F6
812#define mmPA_CL_UCP_0_W 0xA172
813#define mmPA_CL_UCP_0_X 0xA16F
814#define mmPA_CL_UCP_0_Y 0xA170
815#define mmPA_CL_UCP_0_Z 0xA171
816#define mmPA_CL_UCP_1_W 0xA176
817#define mmPA_CL_UCP_1_X 0xA173
818#define mmPA_CL_UCP_1_Y 0xA174
819#define mmPA_CL_UCP_1_Z 0xA175
820#define mmPA_CL_UCP_2_W 0xA17A
821#define mmPA_CL_UCP_2_X 0xA177
822#define mmPA_CL_UCP_2_Y 0xA178
823#define mmPA_CL_UCP_2_Z 0xA179
824#define mmPA_CL_UCP_3_W 0xA17E
825#define mmPA_CL_UCP_3_X 0xA17B
826#define mmPA_CL_UCP_3_Y 0xA17C
827#define mmPA_CL_UCP_3_Z 0xA17D
828#define mmPA_CL_UCP_4_W 0xA182
829#define mmPA_CL_UCP_4_X 0xA17F
830#define mmPA_CL_UCP_4_Y 0xA180
831#define mmPA_CL_UCP_4_Z 0xA181
832#define mmPA_CL_UCP_5_W 0xA186
833#define mmPA_CL_UCP_5_X 0xA183
834#define mmPA_CL_UCP_5_Y 0xA184
835#define mmPA_CL_UCP_5_Z 0xA185
836#define mmPA_CL_VPORT_XOFFSET 0xA110
837#define mmPA_CL_VPORT_XOFFSET_10 0xA14C
838#define mmPA_CL_VPORT_XOFFSET_1 0xA116
839#define mmPA_CL_VPORT_XOFFSET_11 0xA152
840#define mmPA_CL_VPORT_XOFFSET_12 0xA158
841#define mmPA_CL_VPORT_XOFFSET_13 0xA15E
842#define mmPA_CL_VPORT_XOFFSET_14 0xA164
843#define mmPA_CL_VPORT_XOFFSET_15 0xA16A
844#define mmPA_CL_VPORT_XOFFSET_2 0xA11C
845#define mmPA_CL_VPORT_XOFFSET_3 0xA122
846#define mmPA_CL_VPORT_XOFFSET_4 0xA128
847#define mmPA_CL_VPORT_XOFFSET_5 0xA12E
848#define mmPA_CL_VPORT_XOFFSET_6 0xA134
849#define mmPA_CL_VPORT_XOFFSET_7 0xA13A
850#define mmPA_CL_VPORT_XOFFSET_8 0xA140
851#define mmPA_CL_VPORT_XOFFSET_9 0xA146
852#define mmPA_CL_VPORT_XSCALE 0xA10F
853#define mmPA_CL_VPORT_XSCALE_10 0xA14B
854#define mmPA_CL_VPORT_XSCALE_1 0xA115
855#define mmPA_CL_VPORT_XSCALE_11 0xA151
856#define mmPA_CL_VPORT_XSCALE_12 0xA157
857#define mmPA_CL_VPORT_XSCALE_13 0xA15D
858#define mmPA_CL_VPORT_XSCALE_14 0xA163
859#define mmPA_CL_VPORT_XSCALE_15 0xA169
860#define mmPA_CL_VPORT_XSCALE_2 0xA11B
861#define mmPA_CL_VPORT_XSCALE_3 0xA121
862#define mmPA_CL_VPORT_XSCALE_4 0xA127
863#define mmPA_CL_VPORT_XSCALE_5 0xA12D
864#define mmPA_CL_VPORT_XSCALE_6 0xA133
865#define mmPA_CL_VPORT_XSCALE_7 0xA139
866#define mmPA_CL_VPORT_XSCALE_8 0xA13F
867#define mmPA_CL_VPORT_XSCALE_9 0xA145
868#define mmPA_CL_VPORT_YOFFSET 0xA112
869#define mmPA_CL_VPORT_YOFFSET_10 0xA14E
870#define mmPA_CL_VPORT_YOFFSET_1 0xA118
871#define mmPA_CL_VPORT_YOFFSET_11 0xA154
872#define mmPA_CL_VPORT_YOFFSET_12 0xA15A
873#define mmPA_CL_VPORT_YOFFSET_13 0xA160
874#define mmPA_CL_VPORT_YOFFSET_14 0xA166
875#define mmPA_CL_VPORT_YOFFSET_15 0xA16C
876#define mmPA_CL_VPORT_YOFFSET_2 0xA11E
877#define mmPA_CL_VPORT_YOFFSET_3 0xA124
878#define mmPA_CL_VPORT_YOFFSET_4 0xA12A
879#define mmPA_CL_VPORT_YOFFSET_5 0xA130
880#define mmPA_CL_VPORT_YOFFSET_6 0xA136
881#define mmPA_CL_VPORT_YOFFSET_7 0xA13C
882#define mmPA_CL_VPORT_YOFFSET_8 0xA142
883#define mmPA_CL_VPORT_YOFFSET_9 0xA148
884#define mmPA_CL_VPORT_YSCALE 0xA111
885#define mmPA_CL_VPORT_YSCALE_10 0xA14D
886#define mmPA_CL_VPORT_YSCALE_1 0xA117
887#define mmPA_CL_VPORT_YSCALE_11 0xA153
888#define mmPA_CL_VPORT_YSCALE_12 0xA159
889#define mmPA_CL_VPORT_YSCALE_13 0xA15F
890#define mmPA_CL_VPORT_YSCALE_14 0xA165
891#define mmPA_CL_VPORT_YSCALE_15 0xA16B
892#define mmPA_CL_VPORT_YSCALE_2 0xA11D
893#define mmPA_CL_VPORT_YSCALE_3 0xA123
894#define mmPA_CL_VPORT_YSCALE_4 0xA129
895#define mmPA_CL_VPORT_YSCALE_5 0xA12F
896#define mmPA_CL_VPORT_YSCALE_6 0xA135
897#define mmPA_CL_VPORT_YSCALE_7 0xA13B
898#define mmPA_CL_VPORT_YSCALE_8 0xA141
899#define mmPA_CL_VPORT_YSCALE_9 0xA147
900#define mmPA_CL_VPORT_ZOFFSET 0xA114
901#define mmPA_CL_VPORT_ZOFFSET_10 0xA150
902#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A
903#define mmPA_CL_VPORT_ZOFFSET_11 0xA156
904#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C
905#define mmPA_CL_VPORT_ZOFFSET_13 0xA162
906#define mmPA_CL_VPORT_ZOFFSET_14 0xA168
907#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E
908#define mmPA_CL_VPORT_ZOFFSET_2 0xA120
909#define mmPA_CL_VPORT_ZOFFSET_3 0xA126
910#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C
911#define mmPA_CL_VPORT_ZOFFSET_5 0xA132
912#define mmPA_CL_VPORT_ZOFFSET_6 0xA138
913#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E
914#define mmPA_CL_VPORT_ZOFFSET_8 0xA144
915#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A
916#define mmPA_CL_VPORT_ZSCALE 0xA113
917#define mmPA_CL_VPORT_ZSCALE_10 0xA14F
918#define mmPA_CL_VPORT_ZSCALE_1 0xA119
919#define mmPA_CL_VPORT_ZSCALE_11 0xA155
920#define mmPA_CL_VPORT_ZSCALE_12 0xA15B
921#define mmPA_CL_VPORT_ZSCALE_13 0xA161
922#define mmPA_CL_VPORT_ZSCALE_14 0xA167
923#define mmPA_CL_VPORT_ZSCALE_15 0xA16D
924#define mmPA_CL_VPORT_ZSCALE_2 0xA11F
925#define mmPA_CL_VPORT_ZSCALE_3 0xA125
926#define mmPA_CL_VPORT_ZSCALE_4 0xA12B
927#define mmPA_CL_VPORT_ZSCALE_5 0xA131
928#define mmPA_CL_VPORT_ZSCALE_6 0xA137
929#define mmPA_CL_VPORT_ZSCALE_7 0xA13D
930#define mmPA_CL_VPORT_ZSCALE_8 0xA143
931#define mmPA_CL_VPORT_ZSCALE_9 0xA149
932#define mmPA_CL_VS_OUT_CNTL 0xA207
933#define mmPA_CL_VTE_CNTL 0xA206
934#define mmPA_SC_AA_CONFIG 0xA2F8
935#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xA30E
936#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xA30F
937#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xA2FE
938#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xA2FF
939#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xA300
940#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xA301
941#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xA306
942#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xA307
943#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xA308
944#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xA309
945#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xA302
946#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xA303
947#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xA304
948#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xA305
949#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xA30A
950#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xA30B
951#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xA30C
952#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xA30D
953#define mmPA_SC_CENTROID_PRIORITY_0 0xA2F5
954#define mmPA_SC_CENTROID_PRIORITY_1 0xA2F6
955#define mmPA_SC_CLIPRECT_0_BR 0xA085
956#define mmPA_SC_CLIPRECT_0_TL 0xA084
957#define mmPA_SC_CLIPRECT_1_BR 0xA087
958#define mmPA_SC_CLIPRECT_1_TL 0xA086
959#define mmPA_SC_CLIPRECT_2_BR 0xA089
960#define mmPA_SC_CLIPRECT_2_TL 0xA088
961#define mmPA_SC_CLIPRECT_3_BR 0xA08B
962#define mmPA_SC_CLIPRECT_3_TL 0xA08A
963#define mmPA_SC_CLIPRECT_RULE 0xA083
964#define mmPA_SC_DEBUG_CNTL 0x22F6
965#define mmPA_SC_DEBUG_DATA 0x22F7
966#define mmPA_SC_EDGERULE 0xA08C
967#define mmPA_SC_ENHANCE 0x22FC
968#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295
969#define mmPA_SC_FIFO_SIZE 0x22F3
970#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22C9
971#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091
972#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090
973#define mmPA_SC_IF_FIFO_SIZE 0x22F5
974#define mmPA_SC_LINE_CNTL 0xA2F7
975#define mmPA_SC_LINE_STIPPLE 0xA283
976#define mmPA_SC_LINE_STIPPLE_STATE 0x22C4
977#define mmPA_SC_MODE_CNTL_0 0xA292
978#define mmPA_SC_MODE_CNTL_1 0xA293
979#define mmPA_SC_PERFCOUNTER0_HI 0x22A9
980#define mmPA_SC_PERFCOUNTER0_LO 0x22A8
981#define mmPA_SC_PERFCOUNTER0_SELECT 0x22A0
982#define mmPA_SC_PERFCOUNTER1_HI 0x22AB
983#define mmPA_SC_PERFCOUNTER1_LO 0x22AA
984#define mmPA_SC_PERFCOUNTER1_SELECT 0x22A1
985#define mmPA_SC_PERFCOUNTER2_HI 0x22AD
986#define mmPA_SC_PERFCOUNTER2_LO 0x22AC
987#define mmPA_SC_PERFCOUNTER2_SELECT 0x22A2
988#define mmPA_SC_PERFCOUNTER3_HI 0x22AF
989#define mmPA_SC_PERFCOUNTER3_LO 0x22AE
990#define mmPA_SC_PERFCOUNTER3_SELECT 0x22A3
991#define mmPA_SC_PERFCOUNTER4_HI 0x22B1
992#define mmPA_SC_PERFCOUNTER4_LO 0x22B0
993#define mmPA_SC_PERFCOUNTER4_SELECT 0x22A4
994#define mmPA_SC_PERFCOUNTER5_HI 0x22B3
995#define mmPA_SC_PERFCOUNTER5_LO 0x22B2
996#define mmPA_SC_PERFCOUNTER5_SELECT 0x22A5
997#define mmPA_SC_PERFCOUNTER6_HI 0x22B5
998#define mmPA_SC_PERFCOUNTER6_LO 0x22B4
999#define mmPA_SC_PERFCOUNTER6_SELECT 0x22A6
1000#define mmPA_SC_PERFCOUNTER7_HI 0x22B7
1001#define mmPA_SC_PERFCOUNTER7_LO 0x22B6
1002#define mmPA_SC_PERFCOUNTER7_SELECT 0x22A7
1003#define mmPA_SC_RASTER_CONFIG 0xA0D4
1004#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D
1005#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C
1006#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095
1007#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094
1008#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9
1009#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8
1010#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB
1011#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA
1012#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD
1013#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC
1014#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF
1015#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE
1016#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1
1017#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0
1018#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3
1019#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2
1020#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097
1021#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096
1022#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099
1023#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098
1024#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B
1025#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A
1026#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D
1027#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C
1028#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F
1029#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E
1030#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1
1031#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0
1032#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3
1033#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2
1034#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5
1035#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4
1036#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7
1037#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6
1038#define mmPA_SC_VPORT_ZMAX_0 0xA0B5
1039#define mmPA_SC_VPORT_ZMAX_10 0xA0C9
1040#define mmPA_SC_VPORT_ZMAX_1 0xA0B7
1041#define mmPA_SC_VPORT_ZMAX_11 0xA0CB
1042#define mmPA_SC_VPORT_ZMAX_12 0xA0CD
1043#define mmPA_SC_VPORT_ZMAX_13 0xA0CF
1044#define mmPA_SC_VPORT_ZMAX_14 0xA0D1
1045#define mmPA_SC_VPORT_ZMAX_15 0xA0D3
1046#define mmPA_SC_VPORT_ZMAX_2 0xA0B9
1047#define mmPA_SC_VPORT_ZMAX_3 0xA0BB
1048#define mmPA_SC_VPORT_ZMAX_4 0xA0BD
1049#define mmPA_SC_VPORT_ZMAX_5 0xA0BF
1050#define mmPA_SC_VPORT_ZMAX_6 0xA0C1
1051#define mmPA_SC_VPORT_ZMAX_7 0xA0C3
1052#define mmPA_SC_VPORT_ZMAX_8 0xA0C5
1053#define mmPA_SC_VPORT_ZMAX_9 0xA0C7
1054#define mmPA_SC_VPORT_ZMIN_0 0xA0B4
1055#define mmPA_SC_VPORT_ZMIN_10 0xA0C8
1056#define mmPA_SC_VPORT_ZMIN_1 0xA0B6
1057#define mmPA_SC_VPORT_ZMIN_11 0xA0CA
1058#define mmPA_SC_VPORT_ZMIN_12 0xA0CC
1059#define mmPA_SC_VPORT_ZMIN_13 0xA0CE
1060#define mmPA_SC_VPORT_ZMIN_14 0xA0D0
1061#define mmPA_SC_VPORT_ZMIN_15 0xA0D2
1062#define mmPA_SC_VPORT_ZMIN_2 0xA0B8
1063#define mmPA_SC_VPORT_ZMIN_3 0xA0BA
1064#define mmPA_SC_VPORT_ZMIN_4 0xA0BC
1065#define mmPA_SC_VPORT_ZMIN_5 0xA0BE
1066#define mmPA_SC_VPORT_ZMIN_6 0xA0C0
1067#define mmPA_SC_VPORT_ZMIN_7 0xA0C2
1068#define mmPA_SC_VPORT_ZMIN_8 0xA0C4
1069#define mmPA_SC_VPORT_ZMIN_9 0xA0C6
1070#define mmPA_SC_WINDOW_OFFSET 0xA080
1071#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082
1072#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081
1073#define mmPA_SU_CNTL_STATUS 0x2294
1074#define mmPA_SU_DEBUG_CNTL 0x2280
1075#define mmPA_SU_DEBUG_DATA 0x2281
1076#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xA08D
1077#define mmPA_SU_LINE_CNTL 0xA282
1078#define mmPA_SU_LINE_STIPPLE_CNTL 0xA209
1079#define mmPA_SU_LINE_STIPPLE_SCALE 0xA20A
1080#define mmPA_SU_LINE_STIPPLE_VALUE 0x2298
1081#define mmPA_SU_PERFCOUNTER0_HI 0x228D
1082#define mmPA_SU_PERFCOUNTER0_LO 0x228C
1083#define mmPA_SU_PERFCOUNTER0_SELECT 0x2288
1084#define mmPA_SU_PERFCOUNTER1_HI 0x228F
1085#define mmPA_SU_PERFCOUNTER1_LO 0x228E
1086#define mmPA_SU_PERFCOUNTER1_SELECT 0x2289
1087#define mmPA_SU_PERFCOUNTER2_HI 0x2291
1088#define mmPA_SU_PERFCOUNTER2_LO 0x2290
1089#define mmPA_SU_PERFCOUNTER2_SELECT 0x228A
1090#define mmPA_SU_PERFCOUNTER3_HI 0x2293
1091#define mmPA_SU_PERFCOUNTER3_LO 0x2292
1092#define mmPA_SU_PERFCOUNTER3_SELECT 0x228B
1093#define mmPA_SU_POINT_MINMAX 0xA281
1094#define mmPA_SU_POINT_SIZE 0xA280
1095#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA2E3
1096#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA2E2
1097#define mmPA_SU_POLY_OFFSET_CLAMP 0xA2DF
1098#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA2DE
1099#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA2E1
1100#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA2E0
1101#define mmPA_SU_PRIM_FILTER_CNTL 0xA20B
1102#define mmPA_SU_SC_MODE_CNTL 0xA205
1103#define mmPA_SU_VTX_CNTL 0xA2F9
1104#define mmRAS_BCI_SIGNATURE0 0x339E
1105#define mmRAS_BCI_SIGNATURE1 0x339F
1106#define mmRAS_CB_SIGNATURE0 0x339D
1107#define mmRAS_DB_SIGNATURE0 0x338B
1108#define mmRAS_IA_SIGNATURE0 0x3397
1109#define mmRAS_IA_SIGNATURE1 0x3398
1110#define mmRAS_PA_SIGNATURE0 0x338C
1111#define mmRAS_SC_SIGNATURE0 0x338F
1112#define mmRAS_SC_SIGNATURE1 0x3390
1113#define mmRAS_SC_SIGNATURE2 0x3391
1114#define mmRAS_SC_SIGNATURE3 0x3392
1115#define mmRAS_SC_SIGNATURE4 0x3393
1116#define mmRAS_SC_SIGNATURE5 0x3394
1117#define mmRAS_SC_SIGNATURE6 0x3395
1118#define mmRAS_SC_SIGNATURE7 0x3396
1119#define mmRAS_SIGNATURE_CONTROL 0x3380
1120#define mmRAS_SIGNATURE_MASK 0x3381
1121#define mmRAS_SPI_SIGNATURE0 0x3399
1122#define mmRAS_SPI_SIGNATURE1 0x339A
1123#define mmRAS_SQ_SIGNATURE0 0x338E
1124#define mmRAS_SX_SIGNATURE0 0x3382
1125#define mmRAS_SX_SIGNATURE1 0x3383
1126#define mmRAS_SX_SIGNATURE2 0x3384
1127#define mmRAS_SX_SIGNATURE3 0x3385
1128#define mmRAS_TA_SIGNATURE0 0x339B
1129#define mmRAS_TD_SIGNATURE0 0x339C
1130#define mmRAS_VGT_SIGNATURE0 0x338D
1131#define mmRLC_AUTO_PG_CTRL 0x310D
1132#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0
1133#define mmRLC_CGCG_CGLS_CTRL 0x3101
1134#define mmRLC_CGCG_RAMP_CTRL 0x3102
1135#define mmRLC_CGTT_MGCG_OVERRIDE 0x3100
1136#define mmRLC_CNTL 0x30C0
1137#define mmRLC_CU_STATUS 0x3106
1138#define mmRLC_DEBUG 0x30CA
1139#define mmRLC_DEBUG_SELECT 0x30C9
1140#define mmRLC_DRIVER_CPDMA_STATUS 0x30C7
1141#define mmRLC_DYN_PG_REQUEST 0x3104
1142#define mmRLC_DYN_PG_STATUS 0x3103
1143#define mmRLC_GPU_CLOCK_32 0x30D5
1144#define mmRLC_GPU_CLOCK_32_RES_SEL 0x30D4
1145#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30CE
1146#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30CF
1147#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3108
1148#define mmRLC_LB_CNTL 0x30C3
1149#define mmRLC_LB_CNTR_INIT 0x30C6
1150#define mmRLC_LB_CNTR_MAX 0x30C5
1151#define mmRLC_LB_INIT_CU_MASK 0x3107
1152#define mmRLC_LB_PARAMS 0x3109
1153#define mmRLC_LOAD_BALANCE_CNTR 0x30F6
1154#define mmRLC_MAX_PG_CU 0x310C
1155#define mmRLC_MC_CNTL 0x30D1
1156#define mmRLC_MEM_SLP_CNTL 0x30D8
1157#define mmRLC_PERFCOUNTER0_HI 0x30DC
1158#define mmRLC_PERFCOUNTER0_LO 0x30DB
1159#define mmRLC_PERFCOUNTER0_SELECT 0x30DA
1160#define mmRLC_PERFCOUNTER1_HI 0x30DF
1161#define mmRLC_PERFCOUNTER1_LO 0x30DE
1162#define mmRLC_PERFCOUNTER1_SELECT 0x30DD
1163#define mmRLC_PERFMON_CNTL 0x30D9
1164#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x310B
1165#define mmRLC_PG_CNTL 0x30D7
1166#define mmRLC_SAVE_AND_RESTORE_BASE 0x30C4
1167#define mmRLC_SERDES_RD_DATA_0 0x3112
1168#define mmRLC_SERDES_RD_DATA_1 0x3113
1169#define mmRLC_SERDES_RD_DATA_2 0x3114
1170#define mmRLC_SERDES_RD_MASTER_INDEX 0x3111
1171#define mmRLC_SERDES_WR_CTRL 0x3117
1172#define mmRLC_SERDES_WR_DATA 0x3118
1173#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x310E
1174#define mmRLC_SMU_PG_CTRL 0x310F
1175#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3110
1176#define mmRLC_SOFT_RESET_GPU 0x30D6
1177#define mmRLC_STAT 0x30D3
1178#define mmRLC_THREAD1_DELAY 0x310A
1179#define mmRLC_UCODE_CNTL 0x30D2
1180#define mmSCRATCH_ADDR 0x2151
1181#define mmSCRATCH_REG0 0x2140
1182#define mmSCRATCH_REG1 0x2141
1183#define mmSCRATCH_REG2 0x2142
1184#define mmSCRATCH_REG3 0x2143
1185#define mmSCRATCH_REG4 0x2144
1186#define mmSCRATCH_REG5 0x2145
1187#define mmSCRATCH_REG6 0x2146
1188#define mmSCRATCH_REG7 0x2147
1189#define mmSCRATCH_UMSK 0x2150
1190#define mmSPI_ARB_CYCLES_0 0x243D
1191#define mmSPI_ARB_CYCLES_1 0x243E
1192#define mmSPI_ARB_PRIORITY 0x243C
1193#define mmSPI_BARYC_CNTL 0xA1B8
1194#define mmSPI_CONFIG_CNTL 0x2440
1195#define mmSPI_CONFIG_CNTL_1 0x244F
1196#define mmSPI_DEBUG_BUSY 0x2450
1197#define mmSPI_DEBUG_CNTL 0x2441
1198#define mmSPI_DEBUG_READ 0x2442
1199#define mmSPI_GDS_CREDITS 0x24D8
1200#define mmSPI_INTERP_CONTROL_0 0xA1B5
1201#define mmSPI_LB_CTR_CTRL 0x24D4
1202#define mmSPI_LB_CU_MASK 0x24D5
1203#define mmSPI_LB_DATA_REG 0x24D6
1204#define mmSPI_PERFCOUNTER0_HI 0x2447
1205#define mmSPI_PERFCOUNTER0_LO 0x2448
1206#define mmSPI_PERFCOUNTER0_SELECT 0x2443
1207#define mmSPI_PERFCOUNTER1_HI 0x2449
1208#define mmSPI_PERFCOUNTER1_LO 0x244A
1209#define mmSPI_PERFCOUNTER1_SELECT 0x2444
1210#define mmSPI_PERFCOUNTER2_HI 0x244B
1211#define mmSPI_PERFCOUNTER2_LO 0x244C
1212#define mmSPI_PERFCOUNTER2_SELECT 0x2445
1213#define mmSPI_PERFCOUNTER3_HI 0x244D
1214#define mmSPI_PERFCOUNTER3_LO 0x244E
1215#define mmSPI_PERFCOUNTER3_SELECT 0x2446
1216#define mmSPI_PERFCOUNTER_BINS 0x243F
1217#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24D7
1218#define mmSPI_PS_IN_CONTROL 0xA1B6
1219#define mmSPI_PS_INPUT_ADDR 0xA1B4
1220#define mmSPI_PS_INPUT_CNTL_0 0xA191
1221#define mmSPI_PS_INPUT_CNTL_10 0xA19B
1222#define mmSPI_PS_INPUT_CNTL_1 0xA192
1223#define mmSPI_PS_INPUT_CNTL_11 0xA19C
1224#define mmSPI_PS_INPUT_CNTL_12 0xA19D
1225#define mmSPI_PS_INPUT_CNTL_13 0xA19E
1226#define mmSPI_PS_INPUT_CNTL_14 0xA19F
1227#define mmSPI_PS_INPUT_CNTL_15 0xA1A0
1228#define mmSPI_PS_INPUT_CNTL_16 0xA1A1
1229#define mmSPI_PS_INPUT_CNTL_17 0xA1A2
1230#define mmSPI_PS_INPUT_CNTL_18 0xA1A3
1231#define mmSPI_PS_INPUT_CNTL_19 0xA1A4
1232#define mmSPI_PS_INPUT_CNTL_20 0xA1A5
1233#define mmSPI_PS_INPUT_CNTL_2 0xA193
1234#define mmSPI_PS_INPUT_CNTL_21 0xA1A6
1235#define mmSPI_PS_INPUT_CNTL_22 0xA1A7
1236#define mmSPI_PS_INPUT_CNTL_23 0xA1A8
1237#define mmSPI_PS_INPUT_CNTL_24 0xA1A9
1238#define mmSPI_PS_INPUT_CNTL_25 0xA1AA
1239#define mmSPI_PS_INPUT_CNTL_26 0xA1AB
1240#define mmSPI_PS_INPUT_CNTL_27 0xA1AC
1241#define mmSPI_PS_INPUT_CNTL_28 0xA1AD
1242#define mmSPI_PS_INPUT_CNTL_29 0xA1AE
1243#define mmSPI_PS_INPUT_CNTL_30 0xA1AF
1244#define mmSPI_PS_INPUT_CNTL_3 0xA194
1245#define mmSPI_PS_INPUT_CNTL_31 0xA1B0
1246#define mmSPI_PS_INPUT_CNTL_4 0xA195
1247#define mmSPI_PS_INPUT_CNTL_5 0xA196
1248#define mmSPI_PS_INPUT_CNTL_6 0xA197
1249#define mmSPI_PS_INPUT_CNTL_7 0xA198
1250#define mmSPI_PS_INPUT_CNTL_8 0xA199
1251#define mmSPI_PS_INPUT_CNTL_9 0xA19A
1252#define mmSPI_PS_INPUT_ENA 0xA1B3
1253#define mmSPI_PS_MAX_WAVE_ID 0x243B
1254#define mmSPI_SHADER_COL_FORMAT 0xA1C5
1255#define mmSPI_SHADER_PGM_HI_ES 0x2CC9
1256#define mmSPI_SHADER_PGM_HI_GS 0x2C89
1257#define mmSPI_SHADER_PGM_HI_HS 0x2D09
1258#define mmSPI_SHADER_PGM_HI_LS 0x2D49
1259#define mmSPI_SHADER_PGM_HI_PS 0x2C09
1260#define mmSPI_SHADER_PGM_HI_VS 0x2C49
1261#define mmSPI_SHADER_PGM_LO_ES 0x2CC8
1262#define mmSPI_SHADER_PGM_LO_GS 0x2C88
1263#define mmSPI_SHADER_PGM_LO_HS 0x2D08
1264#define mmSPI_SHADER_PGM_LO_LS 0x2D48
1265#define mmSPI_SHADER_PGM_LO_PS 0x2C08
1266#define mmSPI_SHADER_PGM_LO_VS 0x2C48
1267#define mmSPI_SHADER_PGM_RSRC1_ES 0x2CCA
1268#define mmSPI_SHADER_PGM_RSRC1_GS 0x2C8A
1269#define mmSPI_SHADER_PGM_RSRC1_HS 0x2D0A
1270#define mmSPI_SHADER_PGM_RSRC1_LS 0x2D4A
1271#define mmSPI_SHADER_PGM_RSRC1_PS 0x2C0A
1272#define mmSPI_SHADER_PGM_RSRC1_VS 0x2C4A
1273#define mmSPI_SHADER_PGM_RSRC2_ES 0x2CCB
1274#define mmSPI_SHADER_PGM_RSRC2_GS 0x2C8B
1275#define mmSPI_SHADER_PGM_RSRC2_HS 0x2D0B
1276#define mmSPI_SHADER_PGM_RSRC2_LS 0x2D4B
1277#define mmSPI_SHADER_PGM_RSRC2_PS 0x2C0B
1278#define mmSPI_SHADER_PGM_RSRC2_VS 0x2C4B
1279#define mmSPI_SHADER_POS_FORMAT 0xA1C3
1280#define mmSPI_SHADER_TBA_HI_ES 0x2CC1
1281#define mmSPI_SHADER_TBA_HI_GS 0x2C81
1282#define mmSPI_SHADER_TBA_HI_HS 0x2D01
1283#define mmSPI_SHADER_TBA_HI_LS 0x2D41
1284#define mmSPI_SHADER_TBA_HI_PS 0x2C01
1285#define mmSPI_SHADER_TBA_HI_VS 0x2C41
1286#define mmSPI_SHADER_TBA_LO_ES 0x2CC0
1287#define mmSPI_SHADER_TBA_LO_GS 0x2C80
1288#define mmSPI_SHADER_TBA_LO_HS 0x2D00
1289#define mmSPI_SHADER_TBA_LO_LS 0x2D40
1290#define mmSPI_SHADER_TBA_LO_PS 0x2C00
1291#define mmSPI_SHADER_TBA_LO_VS 0x2C40
1292#define mmSPI_SHADER_TMA_HI_ES 0x2CC3
1293#define mmSPI_SHADER_TMA_HI_GS 0x2C83
1294#define mmSPI_SHADER_TMA_HI_HS 0x2D03
1295#define mmSPI_SHADER_TMA_HI_LS 0x2D43
1296#define mmSPI_SHADER_TMA_HI_PS 0x2C03
1297#define mmSPI_SHADER_TMA_HI_VS 0x2C43
1298#define mmSPI_SHADER_TMA_LO_ES 0x2CC2
1299#define mmSPI_SHADER_TMA_LO_GS 0x2C82
1300#define mmSPI_SHADER_TMA_LO_HS 0x2D02
1301#define mmSPI_SHADER_TMA_LO_LS 0x2D42
1302#define mmSPI_SHADER_TMA_LO_PS 0x2C02
1303#define mmSPI_SHADER_TMA_LO_VS 0x2C42
1304#define mmSPI_SHADER_USER_DATA_ES_0 0x2CCC
1305#define mmSPI_SHADER_USER_DATA_ES_10 0x2CD6
1306#define mmSPI_SHADER_USER_DATA_ES_1 0x2CCD
1307#define mmSPI_SHADER_USER_DATA_ES_11 0x2CD7
1308#define mmSPI_SHADER_USER_DATA_ES_12 0x2CD8
1309#define mmSPI_SHADER_USER_DATA_ES_13 0x2CD9
1310#define mmSPI_SHADER_USER_DATA_ES_14 0x2CDA
1311#define mmSPI_SHADER_USER_DATA_ES_15 0x2CDB
1312#define mmSPI_SHADER_USER_DATA_ES_2 0x2CCE
1313#define mmSPI_SHADER_USER_DATA_ES_3 0x2CCF
1314#define mmSPI_SHADER_USER_DATA_ES_4 0x2CD0
1315#define mmSPI_SHADER_USER_DATA_ES_5 0x2CD1
1316#define mmSPI_SHADER_USER_DATA_ES_6 0x2CD2
1317#define mmSPI_SHADER_USER_DATA_ES_7 0x2CD3
1318#define mmSPI_SHADER_USER_DATA_ES_8 0x2CD4
1319#define mmSPI_SHADER_USER_DATA_ES_9 0x2CD5
1320#define mmSPI_SHADER_USER_DATA_GS_0 0x2C8C
1321#define mmSPI_SHADER_USER_DATA_GS_10 0x2C96
1322#define mmSPI_SHADER_USER_DATA_GS_1 0x2C8D
1323#define mmSPI_SHADER_USER_DATA_GS_11 0x2C97
1324#define mmSPI_SHADER_USER_DATA_GS_12 0x2C98
1325#define mmSPI_SHADER_USER_DATA_GS_13 0x2C99
1326#define mmSPI_SHADER_USER_DATA_GS_14 0x2C9A
1327#define mmSPI_SHADER_USER_DATA_GS_15 0x2C9B
1328#define mmSPI_SHADER_USER_DATA_GS_2 0x2C8E
1329#define mmSPI_SHADER_USER_DATA_GS_3 0x2C8F
1330#define mmSPI_SHADER_USER_DATA_GS_4 0x2C90
1331#define mmSPI_SHADER_USER_DATA_GS_5 0x2C91
1332#define mmSPI_SHADER_USER_DATA_GS_6 0x2C92
1333#define mmSPI_SHADER_USER_DATA_GS_7 0x2C93
1334#define mmSPI_SHADER_USER_DATA_GS_8 0x2C94
1335#define mmSPI_SHADER_USER_DATA_GS_9 0x2C95
1336#define mmSPI_SHADER_USER_DATA_HS_0 0x2D0C
1337#define mmSPI_SHADER_USER_DATA_HS_10 0x2D16
1338#define mmSPI_SHADER_USER_DATA_HS_1 0x2D0D
1339#define mmSPI_SHADER_USER_DATA_HS_11 0x2D17
1340#define mmSPI_SHADER_USER_DATA_HS_12 0x2D18
1341#define mmSPI_SHADER_USER_DATA_HS_13 0x2D19
1342#define mmSPI_SHADER_USER_DATA_HS_14 0x2D1A
1343#define mmSPI_SHADER_USER_DATA_HS_15 0x2D1B
1344#define mmSPI_SHADER_USER_DATA_HS_2 0x2D0E
1345#define mmSPI_SHADER_USER_DATA_HS_3 0x2D0F
1346#define mmSPI_SHADER_USER_DATA_HS_4 0x2D10
1347#define mmSPI_SHADER_USER_DATA_HS_5 0x2D11
1348#define mmSPI_SHADER_USER_DATA_HS_6 0x2D12
1349#define mmSPI_SHADER_USER_DATA_HS_7 0x2D13
1350#define mmSPI_SHADER_USER_DATA_HS_8 0x2D14
1351#define mmSPI_SHADER_USER_DATA_HS_9 0x2D15
1352#define mmSPI_SHADER_USER_DATA_LS_0 0x2D4C
1353#define mmSPI_SHADER_USER_DATA_LS_10 0x2D56
1354#define mmSPI_SHADER_USER_DATA_LS_1 0x2D4D
1355#define mmSPI_SHADER_USER_DATA_LS_11 0x2D57
1356#define mmSPI_SHADER_USER_DATA_LS_12 0x2D58
1357#define mmSPI_SHADER_USER_DATA_LS_13 0x2D59
1358#define mmSPI_SHADER_USER_DATA_LS_14 0x2D5A
1359#define mmSPI_SHADER_USER_DATA_LS_15 0x2D5B
1360#define mmSPI_SHADER_USER_DATA_LS_2 0x2D4E
1361#define mmSPI_SHADER_USER_DATA_LS_3 0x2D4F
1362#define mmSPI_SHADER_USER_DATA_LS_4 0x2D50
1363#define mmSPI_SHADER_USER_DATA_LS_5 0x2D51
1364#define mmSPI_SHADER_USER_DATA_LS_6 0x2D52
1365#define mmSPI_SHADER_USER_DATA_LS_7 0x2D53
1366#define mmSPI_SHADER_USER_DATA_LS_8 0x2D54
1367#define mmSPI_SHADER_USER_DATA_LS_9 0x2D55
1368#define mmSPI_SHADER_USER_DATA_PS_0 0x2C0C
1369#define mmSPI_SHADER_USER_DATA_PS_10 0x2C16
1370#define mmSPI_SHADER_USER_DATA_PS_1 0x2C0D
1371#define mmSPI_SHADER_USER_DATA_PS_11 0x2C17
1372#define mmSPI_SHADER_USER_DATA_PS_12 0x2C18
1373#define mmSPI_SHADER_USER_DATA_PS_13 0x2C19
1374#define mmSPI_SHADER_USER_DATA_PS_14 0x2C1A
1375#define mmSPI_SHADER_USER_DATA_PS_15 0x2C1B
1376#define mmSPI_SHADER_USER_DATA_PS_2 0x2C0E
1377#define mmSPI_SHADER_USER_DATA_PS_3 0x2C0F
1378#define mmSPI_SHADER_USER_DATA_PS_4 0x2C10
1379#define mmSPI_SHADER_USER_DATA_PS_5 0x2C11
1380#define mmSPI_SHADER_USER_DATA_PS_6 0x2C12
1381#define mmSPI_SHADER_USER_DATA_PS_7 0x2C13
1382#define mmSPI_SHADER_USER_DATA_PS_8 0x2C14
1383#define mmSPI_SHADER_USER_DATA_PS_9 0x2C15
1384#define mmSPI_SHADER_USER_DATA_VS_0 0x2C4C
1385#define mmSPI_SHADER_USER_DATA_VS_10 0x2C56
1386#define mmSPI_SHADER_USER_DATA_VS_1 0x2C4D
1387#define mmSPI_SHADER_USER_DATA_VS_11 0x2C57
1388#define mmSPI_SHADER_USER_DATA_VS_12 0x2C58
1389#define mmSPI_SHADER_USER_DATA_VS_13 0x2C59
1390#define mmSPI_SHADER_USER_DATA_VS_14 0x2C5A
1391#define mmSPI_SHADER_USER_DATA_VS_15 0x2C5B
1392#define mmSPI_SHADER_USER_DATA_VS_2 0x2C4E
1393#define mmSPI_SHADER_USER_DATA_VS_3 0x2C4F
1394#define mmSPI_SHADER_USER_DATA_VS_4 0x2C50
1395#define mmSPI_SHADER_USER_DATA_VS_5 0x2C51
1396#define mmSPI_SHADER_USER_DATA_VS_6 0x2C52
1397#define mmSPI_SHADER_USER_DATA_VS_7 0x2C53
1398#define mmSPI_SHADER_USER_DATA_VS_8 0x2C54
1399#define mmSPI_SHADER_USER_DATA_VS_9 0x2C55
1400#define mmSPI_SHADER_Z_FORMAT 0xA1C4
1401#define mmSPI_SLAVE_DEBUG_BUSY 0x24D3
1402#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24D9
1403#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24DA
1404#define mmSPI_TMPRING_SIZE 0xA1BA
1405#define mmSPI_VS_OUT_CONFIG 0xA1B1
1406#define mmSQ_ALU_CLK_CTRL 0x2360
1407#define mmSQ_BUF_RSRC_WORD0 0x23C0
1408#define mmSQ_BUF_RSRC_WORD1 0x23C1
1409#define mmSQ_BUF_RSRC_WORD2 0x23C2
1410#define mmSQ_BUF_RSRC_WORD3 0x23C3
1411#define mmSQC_CACHES 0x2302
1412#define mmSQC_CONFIG 0x2301
1413#define mmSQ_CONFIG 0x2300
1414#define mmSQC_SECDED_CNT 0x23A0
1415#define mmSQ_DEBUG_STS_GLOBAL 0x2309
1416#define mmSQ_DED_CNT 0x23A2
1417#define mmSQ_DED_INFO 0x23A3
1418#define mmSQ_DS_0 0x237F
1419#define mmSQ_DS_1 0x237F
1420#define mmSQ_EXP_0 0x237F
1421#define mmSQ_EXP_1 0x237F
1422#define mmSQ_FIFO_SIZES 0x2305
1423#define mmSQ_IMG_RSRC_WORD0 0x23C4
1424#define mmSQ_IMG_RSRC_WORD1 0x23C5
1425#define mmSQ_IMG_RSRC_WORD2 0x23C6
1426#define mmSQ_IMG_RSRC_WORD3 0x23C7
1427#define mmSQ_IMG_RSRC_WORD4 0x23C8
1428#define mmSQ_IMG_RSRC_WORD5 0x23C9
1429#define mmSQ_IMG_RSRC_WORD6 0x23CA
1430#define mmSQ_IMG_RSRC_WORD7 0x23CB
1431#define mmSQ_IMG_SAMP_WORD0 0x23CC
1432#define mmSQ_IMG_SAMP_WORD1 0x23CD
1433#define mmSQ_IMG_SAMP_WORD2 0x23CE
1434#define mmSQ_IMG_SAMP_WORD3 0x23CF
1435#define mmSQ_IND_CMD 0x237A
1436#define mmSQ_IND_DATA 0x2379
1437#define mmSQ_IND_INDEX 0x2378
1438#define mmSQ_INST 0x237F
1439#define mmSQ_LB_CTR_CTRL 0x2398
1440#define mmSQ_LB_DATA_ALU_CYCLES 0x2399
1441#define mmSQ_LB_DATA_ALU_STALLS 0x239B
1442#define mmSQ_LB_DATA_TEX_CYCLES 0x239A
1443#define mmSQ_LB_DATA_TEX_STALLS 0x239C
1444#define mmSQ_MIMG_0 0x237F
1445#define mmSQ_MIMG_1 0x237F
1446#define mmSQ_MTBUF_0 0x237F
1447#define mmSQ_MTBUF_1 0x237F
1448#define mmSQ_MUBUF_0 0x237F
1449#define mmSQ_MUBUF_1 0x237F
1450#define mmSQ_PERFCOUNTER0_HI 0x2321
1451#define mmSQ_PERFCOUNTER0_LO 0x2320
1452#define mmSQ_PERFCOUNTER0_SELECT 0x2340
1453#define mmSQ_PERFCOUNTER10_HI 0x2335
1454#define mmSQ_PERFCOUNTER10_LO 0x2334
1455#define mmSQ_PERFCOUNTER10_SELECT 0x234A
1456#define mmSQ_PERFCOUNTER11_HI 0x2337
1457#define mmSQ_PERFCOUNTER11_LO 0x2336
1458#define mmSQ_PERFCOUNTER11_SELECT 0x234B
1459#define mmSQ_PERFCOUNTER12_HI 0x2339
1460#define mmSQ_PERFCOUNTER12_LO 0x2338
1461#define mmSQ_PERFCOUNTER12_SELECT 0x234C
1462#define mmSQ_PERFCOUNTER13_HI 0x233B
1463#define mmSQ_PERFCOUNTER13_LO 0x233A
1464#define mmSQ_PERFCOUNTER13_SELECT 0x234D
1465#define mmSQ_PERFCOUNTER14_HI 0x233D
1466#define mmSQ_PERFCOUNTER14_LO 0x233C
1467#define mmSQ_PERFCOUNTER14_SELECT 0x234E
1468#define mmSQ_PERFCOUNTER15_HI 0x233F
1469#define mmSQ_PERFCOUNTER15_LO 0x233E
1470#define mmSQ_PERFCOUNTER15_SELECT 0x234F
1471#define mmSQ_PERFCOUNTER1_HI 0x2323
1472#define mmSQ_PERFCOUNTER1_LO 0x2322
1473#define mmSQ_PERFCOUNTER1_SELECT 0x2341
1474#define mmSQ_PERFCOUNTER2_HI 0x2325
1475#define mmSQ_PERFCOUNTER2_LO 0x2324
1476#define mmSQ_PERFCOUNTER2_SELECT 0x2342
1477#define mmSQ_PERFCOUNTER3_HI 0x2327
1478#define mmSQ_PERFCOUNTER3_LO 0x2326
1479#define mmSQ_PERFCOUNTER3_SELECT 0x2343
1480#define mmSQ_PERFCOUNTER4_HI 0x2329
1481#define mmSQ_PERFCOUNTER4_LO 0x2328
1482#define mmSQ_PERFCOUNTER4_SELECT 0x2344
1483#define mmSQ_PERFCOUNTER5_HI 0x232B
1484#define mmSQ_PERFCOUNTER5_LO 0x232A
1485#define mmSQ_PERFCOUNTER5_SELECT 0x2345
1486#define mmSQ_PERFCOUNTER6_HI 0x232D
1487#define mmSQ_PERFCOUNTER6_LO 0x232C
1488#define mmSQ_PERFCOUNTER6_SELECT 0x2346
1489#define mmSQ_PERFCOUNTER7_HI 0x232F
1490#define mmSQ_PERFCOUNTER7_LO 0x232E
1491#define mmSQ_PERFCOUNTER7_SELECT 0x2347
1492#define mmSQ_PERFCOUNTER8_HI 0x2331
1493#define mmSQ_PERFCOUNTER8_LO 0x2330
1494#define mmSQ_PERFCOUNTER8_SELECT 0x2348
1495#define mmSQ_PERFCOUNTER9_HI 0x2333
1496#define mmSQ_PERFCOUNTER9_LO 0x2332
1497#define mmSQ_PERFCOUNTER9_SELECT 0x2349
1498#define mmSQ_PERFCOUNTER_CTRL 0x2306
1499#define mmSQ_POWER_THROTTLE 0x2396
1500#define mmSQ_POWER_THROTTLE2 0x2397
1501#define mmSQ_RANDOM_WAVE_PRI 0x2303
1502#define mmSQ_REG_CREDITS 0x2304
1503#define mmSQ_SEC_CNT 0x23A1
1504#define mmSQ_SMRD 0x237F
1505#define mmSQ_SOP1 0x237F
1506#define mmSQ_SOP2 0x237F
1507#define mmSQ_SOPC 0x237F
1508#define mmSQ_SOPK 0x237F
1509#define mmSQ_SOPP 0x237F
1510#define mmSQ_TEX_CLK_CTRL 0x2361
1511#define mmSQ_THREAD_TRACE_BASE 0x2380
1512#define mmSQ_THREAD_TRACE_CNTR 0x2390
1513#define mmSQ_THREAD_TRACE_CTRL 0x238F
1514#define mmSQ_THREAD_TRACE_HIWATER 0x2392
1515#define mmSQ_THREAD_TRACE_MASK 0x2382
1516#define mmSQ_THREAD_TRACE_MODE 0x238E
1517#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384
1518#define mmSQ_THREAD_TRACE_SIZE 0x2381
1519#define mmSQ_THREAD_TRACE_STATUS 0x238D
1520#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383
1521#define mmSQ_THREAD_TRACE_USERDATA_0 0x2388
1522#define mmSQ_THREAD_TRACE_USERDATA_1 0x2389
1523#define mmSQ_THREAD_TRACE_USERDATA_2 0x238A
1524#define mmSQ_THREAD_TRACE_USERDATA_3 0x238B
1525#define mmSQ_THREAD_TRACE_WORD_CMN 0x23B0
1526#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23B0
1527#define mmSQ_THREAD_TRACE_WORD_INST 0x23B0
1528#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23B0
1529#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23B1
1530#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23B0
1531#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23B1
1532#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23B0
1533#define mmSQ_THREAD_TRACE_WORD_MISC 0x23B0
1534#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23B0
1535#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23B1
1536#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23B0
1537#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23B0
1538#define mmSQ_THREAD_TRACE_WORD_TIME 0x23B0
1539#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23B0
1540#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23B1
1541#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23B0
1542#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23B0
1543#define mmSQ_THREAD_TRACE_WPTR 0x238C
1544#define mmSQ_TIME_HI 0x237C
1545#define mmSQ_TIME_LO 0x237D
1546#define mmSQ_VINTRP 0x237F
1547#define mmSQ_VOP1 0x237F
1548#define mmSQ_VOP2 0x237F
1549#define mmSQ_VOP3_0 0x237F
1550#define mmSQ_VOP3_0_SDST_ENC 0x237F
1551#define mmSQ_VOP3_1 0x237F
1552#define mmSQ_VOPC 0x237F
1553#define mmSX_DEBUG_1 0x2418
1554#define mmSX_DEBUG_BUSY 0x2414
1555#define mmSX_DEBUG_BUSY_2 0x2415
1556#define mmSX_DEBUG_BUSY_3 0x2416
1557#define mmSX_DEBUG_BUSY_4 0x2417
1558#define mmSX_PERFCOUNTER0_HI 0x2421
1559#define mmSX_PERFCOUNTER0_LO 0x2420
1560#define mmSX_PERFCOUNTER0_SELECT 0x241C
1561#define mmSX_PERFCOUNTER1_HI 0x2423
1562#define mmSX_PERFCOUNTER1_LO 0x2422
1563#define mmSX_PERFCOUNTER1_SELECT 0x241D
1564#define mmSX_PERFCOUNTER2_HI 0x2425
1565#define mmSX_PERFCOUNTER2_LO 0x2424
1566#define mmSX_PERFCOUNTER2_SELECT 0x241E
1567#define mmSX_PERFCOUNTER3_HI 0x2427
1568#define mmSX_PERFCOUNTER3_LO 0x2426
1569#define mmSX_PERFCOUNTER3_SELECT 0x241F
1570#define mmTA_BC_BASE_ADDR 0xA020
1571#define mmTA_CGTT_CTRL 0x2544
1572#define mmTA_CNTL 0x2541
1573#define mmTA_CNTL_AUX 0x2542
1574#define mmTA_CS_BC_BASE_ADDR 0x2543
1575#define mmTA_DEBUG_DATA 0x254D
1576#define mmTA_DEBUG_INDEX 0x254C
1577#define mmTA_PERFCOUNTER0_HI 0x2556
1578#define mmTA_PERFCOUNTER0_LO 0x2555
1579#define mmTA_PERFCOUNTER0_SELECT 0x2554
1580#define mmTA_PERFCOUNTER1_HI 0x2562
1581#define mmTA_PERFCOUNTER1_LO 0x2561
1582#define mmTA_PERFCOUNTER1_SELECT 0x2560
1583#define mmTA_SCRATCH 0x2564
1584#define mmTA_STATUS 0x2548
1585#define mmTCA_CGTT_SCLK_CTRL 0x2BC1
1586#define mmTCA_CTRL 0x2BC0
1587#define mmTCA_PERFCOUNTER0_HI 0x2BD2
1588#define mmTCA_PERFCOUNTER0_LO 0x2BD1
1589#define mmTCA_PERFCOUNTER0_SELECT 0x2BD0
1590#define mmTCA_PERFCOUNTER1_HI 0x2BD5
1591#define mmTCA_PERFCOUNTER1_LO 0x2BD4
1592#define mmTCA_PERFCOUNTER1_SELECT 0x2BD3
1593#define mmTCA_PERFCOUNTER2_HI 0x2BD8
1594#define mmTCA_PERFCOUNTER2_LO 0x2BD7
1595#define mmTCA_PERFCOUNTER2_SELECT 0x2BD6
1596#define mmTCA_PERFCOUNTER3_HI 0x2BDB
1597#define mmTCA_PERFCOUNTER3_LO 0x2BDA
1598#define mmTCA_PERFCOUNTER3_SELECT 0x2BD9
1599#define mmTCC_CGTT_SCLK_CTRL 0x2B81
1600#define mmTCC_CTRL 0x2B80
1601#define mmTCC_EDC_COUNTER 0x2B82
1602#define mmTCC_PERFCOUNTER0_HI 0x2B92
1603#define mmTCC_PERFCOUNTER0_LO 0x2B91
1604#define mmTCC_PERFCOUNTER0_SELECT 0x2B90
1605#define mmTCC_PERFCOUNTER1_HI 0x2B95
1606#define mmTCC_PERFCOUNTER1_LO 0x2B94
1607#define mmTCC_PERFCOUNTER1_SELECT 0x2B93
1608#define mmTCC_PERFCOUNTER2_HI 0x2B98
1609#define mmTCC_PERFCOUNTER2_LO 0x2B97
1610#define mmTCC_PERFCOUNTER2_SELECT 0x2B96
1611#define mmTCC_PERFCOUNTER3_HI 0x2B9B
1612#define mmTCC_PERFCOUNTER3_LO 0x2B9A
1613#define mmTCC_PERFCOUNTER3_SELECT 0x2B99
1614#define mmTCI_CNTL_1 0x2B62
1615#define mmTCI_CNTL_2 0x2B63
1616#define mmTCI_STATUS 0x2B61
1617#define mmTCP_ADDR_CONFIG 0x2B05
1618#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2B16
1619#define mmTCP_CHAN_STEER_HI 0x2B04
1620#define mmTCP_CHAN_STEER_LO 0x2B03
1621#define mmTCP_CNTL 0x2B02
1622#define mmTCP_CREDIT 0x2B06
1623#define mmTCP_EDC_COUNTER 0x2B17
1624#define mmTCP_INVALIDATE 0x2B00
1625#define mmTCP_PERFCOUNTER0_HI 0x2B0A
1626#define mmTCP_PERFCOUNTER0_LO 0x2B0B
1627#define mmTCP_PERFCOUNTER0_SELECT 0x2B09
1628#define mmTCP_PERFCOUNTER1_HI 0x2B0D
1629#define mmTCP_PERFCOUNTER1_LO 0x2B0E
1630#define mmTCP_PERFCOUNTER1_SELECT 0x2B0C
1631#define mmTCP_PERFCOUNTER2_HI 0x2B10
1632#define mmTCP_PERFCOUNTER2_LO 0x2B11
1633#define mmTCP_PERFCOUNTER2_SELECT 0x2B0F
1634#define mmTCP_PERFCOUNTER3_HI 0x2B13
1635#define mmTCP_PERFCOUNTER3_LO 0x2B14
1636#define mmTCP_PERFCOUNTER3_SELECT 0x2B12
1637#define mmTCP_STATUS 0x2B01
1638#define mmTD_CGTT_CTRL 0x2527
1639#define mmTD_CNTL 0x2525
1640#define mmTD_DEBUG_DATA 0x2529
1641#define mmTD_DEBUG_INDEX 0x2528
1642#define mmTD_PERFCOUNTER0_HI 0x252E
1643#define mmTD_PERFCOUNTER0_LO 0x252D
1644#define mmTD_PERFCOUNTER0_SELECT 0x252C
1645#define mmTD_SCRATCH 0x2530
1646#define mmTD_STATUS 0x2526
1647#define mmUSER_SQC_BANK_DISABLE 0x2308
1648#define mmVGT_CACHE_INVALIDATION 0x2231
1649#define mmVGT_CNTL_STATUS 0x223C
1650#define mmVGT_DEBUG_CNTL 0x2238
1651#define mmVGT_DEBUG_DATA 0x2239
1652#define mmVGT_DMA_BASE 0xA1FA
1653#define mmVGT_DMA_BASE_HI 0xA1F9
1654#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222D
1655#define mmVGT_DMA_INDEX_TYPE 0xA29F
1656#define mmVGT_DMA_MAX_SIZE 0xA29E
1657#define mmVGT_DMA_NUM_INSTANCES 0xA2A2
1658#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222E
1659#define mmVGT_DMA_SIZE 0xA29D
1660#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222F
1661#define mmVGT_DRAW_INITIATOR 0xA1FC
1662#define mmVGT_ENHANCE 0xA294
1663#define mmVGT_ESGS_RING_ITEMSIZE 0xA2AB
1664#define mmVGT_ESGS_RING_SIZE 0x2232
1665#define mmVGT_ES_PER_GS 0xA296
1666#define mmVGT_EVENT_ADDRESS_REG 0xA1FE
1667#define mmVGT_EVENT_INITIATOR 0xA2A4
1668#define mmVGT_FIFO_DEPTHS 0x2234
1669#define mmVGT_GROUP_DECR 0xA28B
1670#define mmVGT_GROUP_FIRST_DECR 0xA28A
1671#define mmVGT_GROUP_PRIM_TYPE 0xA289
1672#define mmVGT_GROUP_VECT_0_CNTL 0xA28C
1673#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E
1674#define mmVGT_GROUP_VECT_1_CNTL 0xA28D
1675#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F
1676#define mmVGT_GS_INSTANCE_CNT 0xA2E4
1677#define mmVGT_GS_MAX_VERT_OUT 0xA2CE
1678#define mmVGT_GS_MODE 0xA290
1679#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B
1680#define mmVGT_GS_PER_ES 0xA295
1681#define mmVGT_GS_PER_VS 0xA297
1682#define mmVGT_GS_VERTEX_REUSE 0x2235
1683#define mmVGT_GS_VERT_ITEMSIZE 0xA2D7
1684#define mmVGT_GS_VERT_ITEMSIZE_1 0xA2D8
1685#define mmVGT_GS_VERT_ITEMSIZE_2 0xA2D9
1686#define mmVGT_GS_VERT_ITEMSIZE_3 0xA2DA
1687#define mmVGT_GSVS_RING_ITEMSIZE 0xA2AC
1688#define mmVGT_GSVS_RING_OFFSET_1 0xA298
1689#define mmVGT_GSVS_RING_OFFSET_2 0xA299
1690#define mmVGT_GSVS_RING_OFFSET_3 0xA29A
1691#define mmVGT_GSVS_RING_SIZE 0x2233
1692#define mmVGT_HOS_CNTL 0xA285
1693#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286
1694#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287
1695#define mmVGT_HOS_REUSE_DEPTH 0xA288
1696#define mmVGT_HS_OFFCHIP_PARAM 0x226C
1697#define mmVGT_IMMED_DATA 0xA1FD
1698#define mmVGT_INDEX_TYPE 0x2257
1699#define mmVGT_INDX_OFFSET 0xA102
1700#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8
1701#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9
1702#define mmVGT_LAST_COPY_STATE 0x2230
1703#define mmVGT_LS_HS_CONFIG 0xA2D6
1704#define mmVGT_MAX_VTX_INDX 0xA100
1705#define mmVGT_MC_LAT_CNTL 0x2236
1706#define mmVGT_MIN_VTX_INDX 0xA101
1707#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5
1708#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103
1709#define mmVGT_NUM_INDICES 0x225C
1710#define mmVGT_NUM_INSTANCES 0x225D
1711#define mmVGT_OUT_DEALLOC_CNTL 0xA317
1712#define mmVGT_OUTPUT_PATH_CNTL 0xA284
1713#define mmVGT_PERFCOUNTER0_HI 0x224D
1714#define mmVGT_PERFCOUNTER0_LO 0x224C
1715#define mmVGT_PERFCOUNTER0_SELECT 0x2248
1716#define mmVGT_PERFCOUNTER1_HI 0x224F
1717#define mmVGT_PERFCOUNTER1_LO 0x224E
1718#define mmVGT_PERFCOUNTER1_SELECT 0x2249
1719#define mmVGT_PERFCOUNTER2_HI 0x2251
1720#define mmVGT_PERFCOUNTER2_LO 0x2250
1721#define mmVGT_PERFCOUNTER2_SELECT 0x224A
1722#define mmVGT_PERFCOUNTER3_HI 0x2253
1723#define mmVGT_PERFCOUNTER3_LO 0x2252
1724#define mmVGT_PERFCOUNTER3_SELECT 0x224B
1725#define mmVGT_PERFCOUNTER_SEID_MASK 0x2247
1726#define mmVGT_PRIMITIVEID_EN 0xA2A1
1727#define mmVGT_PRIMITIVEID_RESET 0xA2A3
1728#define mmVGT_PRIMITIVE_TYPE 0x2256
1729#define mmVGT_REUSE_OFF 0xA2AD
1730#define mmVGT_SHADER_STAGES_EN 0xA2D5
1731#define mmVGT_STRMOUT_BUFFER_CONFIG 0xA2E6
1732#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2258
1733#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2259
1734#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x225A
1735#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x225B
1736#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7
1737#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB
1738#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF
1739#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3
1740#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4
1741#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8
1742#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC
1743#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0
1744#define mmVGT_STRMOUT_CONFIG 0xA2E5
1745#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB
1746#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA
1747#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC
1748#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5
1749#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9
1750#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD
1751#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1
1752#define mmVGT_SYS_CONFIG 0x2263
1753#define mmVGT_TF_MEMORY_BASE 0x226E
1754#define mmVGT_TF_PARAM 0xA2DB
1755#define mmVGT_TF_RING_SIZE 0x2262
1756#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316
1757#define mmVGT_VTX_CNT_EN 0xA2AE
1758#define mmVGT_VTX_VECT_EJECT_REG 0x222C
1759
1760/* manually added from old sid.h */
1761#define mmCB_PERFCOUNTER0_SELECT0 0x2688
1762#define mmCB_PERFCOUNTER1_SELECT0 0x268A
1763#define mmCB_PERFCOUNTER1_SELECT1 0x268B
1764#define mmCB_PERFCOUNTER2_SELECT0 0x268C
1765#define mmCB_PERFCOUNTER2_SELECT1 0x268D
1766#define mmCB_PERFCOUNTER3_SELECT0 0x268E
1767#define mmCB_PERFCOUNTER3_SELECT1 0x268F
1768#define mmCP_COHER_CNTL2 0x217A
1769#define mmCP_DEBUG 0x307F
1770#define mmRLC_SERDES_MASTER_BUSY_0 0x3119
1771#define mmRLC_SERDES_MASTER_BUSY_1 0x311A
1772#define mmRLC_RL_BASE 0x30C1
1773#define mmRLC_RL_SIZE 0x30C2
1774#define mmRLC_UCODE_ADDR 0x30CB
1775#define mmRLC_UCODE_DATA 0x30CC
1776#define mmRLC_GCPM_GENERAL_3 0x311E
1777#define mmRLC_SERDES_WR_MASTER_MASK_0 0x3115
1778#define mmRLC_SERDES_WR_MASTER_MASK_1 0x3116
1779#define mmRLC_TTOP_D 0x3105
1780#define mmRLC_CLEAR_STATE_RESTORE_BASE 0x30C8
1781#define mmRLC_PG_AO_CU_MASK 0x310B
1782#define mmSPI_STATIC_THREAD_MGMT_3 0x243A
1783
1784#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h
new file mode 100644
index 000000000000..b5e634749665
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h
@@ -0,0 +1,12821 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef GFX_6_0_SH_MASK_H
24#define GFX_6_0_SH_MASK_H
25
26#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
36#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
37#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
38#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
39#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
40#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
41#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
42#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
43#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e
44#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
45#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
46#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
47#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
48#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
49#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
50#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
51#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
52#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
53#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
54#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
55#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
56#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
57#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
58#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
59#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
60#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
61#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e
62#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
63#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
64#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
65#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
66#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
67#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
68#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
69#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
70#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
71#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
72#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
73#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
74#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
75#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
76#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
77#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
78#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
79#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e
80#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
81#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
82#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
83#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
84#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
85#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
86#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
87#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
88#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
89#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
90#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
91#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
92#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
93#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
94#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
95#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
96#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
97#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e
98#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
99#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
100#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
101#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
102#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
103#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
104#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
105#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
106#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
107#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
108#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
109#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
110#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
111#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
112#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
113#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
114#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
115#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e
116#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
117#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
118#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
119#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
120#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
121#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
122#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
123#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
124#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
125#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
126#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
127#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
128#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
129#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
130#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
131#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
132#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
133#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e
134#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
135#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
136#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
137#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
138#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
139#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
140#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
141#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
142#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
143#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
144#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
145#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
146#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
147#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
148#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
149#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
150#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
151#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e
152#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
153#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
154#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
155#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
156#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
157#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
158#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
159#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
160#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
161#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
162#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
163#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
164#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
165#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
166#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
167#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
168#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
169#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e
170#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
171#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
172#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL
173#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000
174#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL
175#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000
176#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL
177#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000
178#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL
179#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000
180#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
181#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
182#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL
183#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000
184#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
185#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
186#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
187#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
188#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
189#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
190#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
191#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
192#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
193#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
194#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
195#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
196#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
197#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
198#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
199#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
200#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
201#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
202#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
203#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
204#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
205#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
206#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
207#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
208#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
209#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
210#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
211#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
212#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL
213#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000
214#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
215#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
216#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
217#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
218#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL
219#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000
220#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
221#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
222#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL
223#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000
224#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
225#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
226#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
227#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010
228#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
229#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f
230#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
231#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
232#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
233#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
234#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
235#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
236#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
237#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e
238#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
239#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b
240#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
241#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000
242#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
243#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d
244#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
245#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
246#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL
247#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002
248#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L
249#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007
250#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
251#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008
252#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
253#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012
254#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
255#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
256#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
257#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
258#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL
259#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000
260#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL
261#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000
262#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L
263#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d
264#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL
265#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000
266#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
267#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
268#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
269#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
270#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
271#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
272#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
273#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
274#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
275#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
276#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
277#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
278#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL
279#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000
280#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
281#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
282#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
283#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
284#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL
285#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000
286#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
287#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
288#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL
289#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000
290#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
291#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
292#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
293#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010
294#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
295#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f
296#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
297#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
298#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
299#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
300#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
301#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
302#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
303#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e
304#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
305#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b
306#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
307#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000
308#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
309#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d
310#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
311#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
312#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL
313#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002
314#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L
315#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007
316#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
317#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008
318#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
319#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012
320#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
321#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
322#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
323#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
324#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL
325#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000
326#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL
327#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000
328#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L
329#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d
330#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL
331#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000
332#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
333#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
334#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
335#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
336#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
337#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
338#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
339#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
340#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
341#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
342#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
343#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
344#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL
345#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000
346#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
347#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
348#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
349#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
350#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL
351#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000
352#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
353#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
354#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL
355#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000
356#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
357#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
358#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
359#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010
360#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
361#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f
362#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
363#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
364#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
365#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
366#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
367#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
368#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
369#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e
370#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
371#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b
372#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
373#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000
374#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
375#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d
376#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
377#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
378#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL
379#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002
380#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L
381#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007
382#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
383#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008
384#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
385#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012
386#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
387#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
388#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
389#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
390#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL
391#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000
392#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL
393#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000
394#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L
395#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d
396#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL
397#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000
398#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
399#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
400#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
401#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
402#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
403#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
404#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
405#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
406#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
407#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
408#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
409#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
410#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL
411#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000
412#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
413#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
414#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
415#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
416#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL
417#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000
418#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
419#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
420#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL
421#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000
422#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
423#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
424#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
425#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010
426#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
427#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f
428#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
429#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
430#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
431#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
432#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
433#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
434#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
435#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e
436#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
437#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b
438#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
439#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000
440#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
441#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d
442#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
443#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
444#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL
445#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002
446#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L
447#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007
448#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
449#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008
450#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
451#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012
452#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
453#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
454#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
455#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
456#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL
457#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000
458#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL
459#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000
460#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L
461#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d
462#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL
463#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000
464#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
465#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
466#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
467#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
468#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
469#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
470#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
471#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
472#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
473#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
474#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
475#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
476#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL
477#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000
478#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
479#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
480#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
481#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
482#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL
483#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000
484#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
485#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
486#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL
487#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000
488#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
489#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
490#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
491#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010
492#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
493#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f
494#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
495#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
496#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
497#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
498#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
499#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
500#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
501#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e
502#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
503#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b
504#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
505#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000
506#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
507#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d
508#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
509#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
510#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL
511#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002
512#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L
513#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007
514#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
515#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008
516#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
517#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012
518#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
519#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
520#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
521#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
522#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL
523#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000
524#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL
525#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000
526#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L
527#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d
528#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL
529#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000
530#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
531#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
532#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
533#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
534#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
535#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
536#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
537#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
538#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
539#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
540#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
541#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
542#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL
543#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000
544#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
545#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
546#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
547#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
548#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL
549#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000
550#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
551#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
552#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL
553#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000
554#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
555#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
556#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
557#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010
558#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
559#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f
560#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
561#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
562#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
563#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
564#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
565#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
566#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
567#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e
568#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
569#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b
570#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
571#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000
572#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
573#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d
574#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
575#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
576#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL
577#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002
578#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L
579#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007
580#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
581#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008
582#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
583#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012
584#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
585#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
586#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
587#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
588#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL
589#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000
590#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL
591#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000
592#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L
593#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d
594#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL
595#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000
596#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
597#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
598#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
599#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
600#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
601#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
602#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
603#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
604#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
605#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
606#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
607#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
608#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL
609#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000
610#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
611#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
612#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
613#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
614#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL
615#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000
616#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
617#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
618#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL
619#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000
620#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
621#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
622#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
623#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010
624#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
625#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f
626#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
627#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
628#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
629#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
630#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
631#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
632#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
633#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e
634#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
635#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b
636#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
637#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000
638#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
639#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d
640#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
641#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
642#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL
643#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002
644#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L
645#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007
646#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
647#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008
648#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
649#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012
650#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
651#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
652#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
653#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
654#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL
655#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000
656#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL
657#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000
658#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L
659#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d
660#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL
661#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000
662#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
663#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
664#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
665#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
666#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
667#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
668#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
669#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
670#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
671#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
672#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
673#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
674#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL
675#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000
676#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
677#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
678#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
679#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
680#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL
681#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000
682#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
683#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
684#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL
685#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000
686#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
687#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
688#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
689#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010
690#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
691#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f
692#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
693#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
694#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
695#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
696#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
697#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
698#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
699#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e
700#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
701#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b
702#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
703#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000
704#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
705#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d
706#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
707#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
708#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL
709#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002
710#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L
711#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007
712#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
713#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008
714#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
715#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012
716#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
717#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
718#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
719#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
720#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL
721#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000
722#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL
723#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000
724#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L
725#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d
726#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL
727#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000
728#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
729#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003
730#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
731#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004
732#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L
733#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010
734#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x00000008L
735#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x00000003
736#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x00000020L
737#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x00000005
738#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x00000010L
739#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x00000004
740#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x00000200L
741#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x00000009
742#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x00000100L
743#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x00000008
744#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x00000080L
745#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x00000007
746#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x00000400L
747#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0x0000000a
748#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x00000040L
749#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x00000006
750#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x00000002L
751#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x00000001
752#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x0007f800L
753#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0x0000000b
754#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x00000001L
755#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x00000000
756#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x00000004L
757#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x00000002
758#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x00000010L
759#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x00000004
760#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x00000008L
761#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x00000003
762#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x00000100L
763#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x00000008
764#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x00000002L
765#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x00000001
766#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x00000004L
767#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x00000002
768#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x00000020L
769#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x00000005
770#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x00000040L
771#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x00000006
772#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x00000080L
773#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x00000007
774#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x00000001L
775#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x00000000
776#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x00000010L
777#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x00000004
778#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x00000040L
779#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x00000006
780#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x00000100L
781#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x00000008
782#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x00000020L
783#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x00000005
784#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x00000008L
785#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x00000003
786#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x00000004L
787#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x00000002
788#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x00000003L
789#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x00000000
790#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x00000080L
791#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x00000007
792#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L
793#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014
794#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L
795#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016
796#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L
797#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015
798#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x000003c0L
799#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x00000006
800#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0x000f0000L
801#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x00000010
802#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x0000003fL
803#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x00000000
804#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0x0000fc00L
805#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0x0000000a
806#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x00000008L
807#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x00000003
808#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x00000004L
809#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x00000002
810#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x00000001L
811#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x00000000
812#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x00000020L
813#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x00000005
814#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x00000002L
815#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x00000001
816#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x00000010L
817#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x00000004
818#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x00000080L
819#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x00000007
820#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x00000040L
821#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x00000006
822#define CB_DEBUG_BUS_18__NOT_USED_MASK 0x00ffffffL
823#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x00000000
824#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L
825#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b
826#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L
827#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a
828#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL
829#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000
830#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L
831#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011
832#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L
833#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005
834#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL
835#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000
836#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff800000L
837#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x00000017
838#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L
839#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f
840#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L
841#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008
842#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
843#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000
844#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
845#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010
846#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L
847#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c
848#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL
849#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000
850#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
851#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019
852#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
853#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a
854#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
855#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018
856#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
857#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015
858#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
859#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b
860#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
861#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e
862#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
863#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016
864#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
865#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012
866#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
867#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f
868#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
869#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017
870#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L
871#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006
872#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
873#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014
874#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
875#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013
876#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
877#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d
878#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
879#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c
880#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
881#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
882#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
883#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
884#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
885#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
886#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
887#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
888#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL
889#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
890#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L
891#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
892#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
893#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
894#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
895#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
896#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
897#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
898#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
899#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
900#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
901#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
902#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
903#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
904#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL
905#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000
906#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L
907#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004
908#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L
909#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008
910#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L
911#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c
912#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L
913#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010
914#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L
915#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014
916#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L
917#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018
918#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L
919#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c
920#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL
921#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000
922#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L
923#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004
924#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L
925#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008
926#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L
927#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c
928#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L
929#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010
930#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L
931#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014
932#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L
933#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018
934#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L
935#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c
936#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L
937#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001
938#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L
939#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004
940#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L
941#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010
942#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
943#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003
944#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
945#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
946#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL
947#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000
948#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L
949#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004
950#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L
951#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008
952#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L
953#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c
954#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L
955#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010
956#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L
957#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014
958#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L
959#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018
960#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L
961#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c
962#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
963#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c
964#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
965#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014
966#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L
967#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008
968#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L
969#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010
970#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L
971#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010
972#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L
973#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014
974#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L
975#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018
976#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L
977#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c
978#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L
979#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008
980#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL
981#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000
982#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL
983#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000
984#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
985#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010
986#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
987#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016
988#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
989#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c
990#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L
991#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004
992#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
993#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017
994#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L
995#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018
996#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL
997#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000
998#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
999#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015
1000#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
1001#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014
1002#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L
1003#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011
1004#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L
1005#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010
1006#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L
1007#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010
1008#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
1009#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e
1010#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
1011#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d
1012#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
1013#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c
1014#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
1015#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b
1016#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
1017#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a
1018#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
1019#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019
1020#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
1021#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018
1022#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1023#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1024#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1025#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1026#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1027#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1028#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L
1029#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c
1030#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1031#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1032#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1033#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1034#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
1035#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e
1036#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
1037#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f
1038#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1039#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1040#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1041#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1042#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1043#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1044#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1045#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1046#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1047#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1048#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1049#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1050#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1051#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1052#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1053#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1054#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1055#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1056#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1057#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1058#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
1059#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d
1060#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
1061#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a
1062#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1063#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1064#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1065#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1066#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
1067#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019
1068#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1069#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1070#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1071#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1072#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1073#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1074#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1075#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1076#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1077#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1078#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
1079#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e
1080#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1081#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1082#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1083#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1084#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
1085#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f
1086#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1087#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1088#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1089#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1090#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1091#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1092#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1093#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1094#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1095#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1096#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
1097#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d
1098#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L
1099#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019
1100#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
1101#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e
1102#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
1103#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d
1104#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
1105#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c
1106#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
1107#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b
1108#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L
1109#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a
1110#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L
1111#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012
1112#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
1113#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018
1114#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1115#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1116#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1117#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1118#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1119#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1120#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1121#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1122#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1123#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1124#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
1125#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e
1126#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
1127#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f
1128#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1129#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1130#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1131#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1132#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1133#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1134#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1135#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1136#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1137#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1138#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1139#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1140#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1141#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1142#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1143#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1144#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1145#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1146#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1147#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1148#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
1149#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a
1150#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
1151#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e
1152#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
1153#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d
1154#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
1155#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c
1156#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
1157#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b
1158#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L
1159#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012
1160#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
1161#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018
1162#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1163#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1164#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1165#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1166#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1167#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1168#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
1169#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
1170#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1171#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1172#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1173#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1174#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1175#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1176#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
1177#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
1178#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1179#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1180#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1181#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1182#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1183#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1184#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L
1185#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004
1186#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL
1187#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000
1188#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L
1189#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c
1190#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
1191#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f
1192#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
1193#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e
1194#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
1195#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d
1196#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
1197#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c
1198#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
1199#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b
1200#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
1201#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a
1202#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
1203#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019
1204#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
1205#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018
1206#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L
1207#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004
1208#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL
1209#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000
1210#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L
1211#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c
1212#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
1213#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f
1214#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
1215#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e
1216#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
1217#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d
1218#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
1219#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c
1220#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
1221#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b
1222#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
1223#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a
1224#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
1225#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019
1226#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L
1227#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x00000018
1228#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L
1229#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004
1230#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL
1231#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000
1232#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L
1233#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c
1234#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
1235#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f
1236#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
1237#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e
1238#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
1239#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d
1240#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
1241#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c
1242#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
1243#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b
1244#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
1245#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a
1246#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
1247#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019
1248#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L
1249#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x00000018
1250#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L
1251#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004
1252#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL
1253#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000
1254#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L
1255#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c
1256#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
1257#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f
1258#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
1259#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e
1260#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
1261#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d
1262#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
1263#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c
1264#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
1265#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b
1266#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
1267#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a
1268#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
1269#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019
1270#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L
1271#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x00000018
1272#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L
1273#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004
1274#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL
1275#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000
1276#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L
1277#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c
1278#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
1279#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f
1280#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
1281#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e
1282#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
1283#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d
1284#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
1285#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c
1286#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
1287#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b
1288#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
1289#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a
1290#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
1291#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019
1292#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x01000000L
1293#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x00000018
1294#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1295#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1296#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1297#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1298#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1299#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1300#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1301#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1302#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1303#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1304#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1305#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1306#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1307#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1308#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1309#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1310#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1311#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1312#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1313#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1314#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1315#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1316#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1317#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1318#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1319#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1320#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1321#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1322#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1323#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1324#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1325#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1326#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1327#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1328#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1329#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1330#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1331#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1332#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1333#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1334#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
1335#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
1336#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
1337#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a
1338#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
1339#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d
1340#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1341#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1342#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1343#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1344#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
1345#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019
1346#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1347#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1348#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1349#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1350#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1351#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1352#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1353#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1354#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL
1355#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000
1356#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L
1357#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b
1358#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L
1359#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c
1360#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L
1361#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015
1362#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L
1363#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016
1364#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L
1365#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008
1366#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L
1367#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c
1368#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L
1369#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b
1370#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L
1371#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f
1372#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L
1373#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010
1374#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L
1375#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d
1376#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L
1377#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d
1378#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L
1379#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e
1380#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L
1381#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009
1382#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L
1383#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011
1384#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L
1385#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012
1386#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L
1387#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f
1388#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L
1389#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013
1390#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L
1391#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014
1392#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L
1393#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017
1394#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L
1395#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018
1396#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L
1397#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019
1398#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L
1399#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a
1400#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L
1401#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e
1402#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL
1403#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000
1404#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L
1405#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008
1406#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L
1407#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c
1408#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L
1409#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d
1410#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L
1411#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011
1412#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L
1413#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014
1414#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L
1415#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e
1416#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L
1417#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b
1418#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L
1419#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e
1420#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L
1421#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f
1422#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L
1423#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018
1424#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L
1425#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a
1426#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L
1427#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019
1428#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L
1429#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017
1430#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L
1431#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016
1432#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L
1433#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015
1434#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L
1435#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000
1436#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L
1437#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a
1438#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L
1439#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c
1440#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L
1441#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014
1442#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L
1443#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015
1444#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L
1445#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b
1446#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L
1447#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d
1448#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L
1449#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018
1450#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L
1451#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006
1452#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L
1453#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016
1454#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L
1455#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e
1456#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L
1457#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f
1458#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L
1459#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017
1460#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L
1461#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019
1462#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L
1463#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010
1464#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L
1465#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c
1466#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L
1467#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008
1468#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L
1469#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003
1470#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1471#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1472#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L
1473#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1474#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1475#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1476#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L
1477#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1478#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L
1479#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e
1480#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L
1481#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d
1482#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1483#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1484#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L
1485#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1486#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1487#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1488#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L
1489#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1490#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L
1491#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d
1492#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L
1493#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1494#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1495#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1496#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1497#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1498#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1499#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1500#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1501#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1502#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1503#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1504#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1505#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1506#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L
1507#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1508#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1509#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1510#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L
1511#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1512#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L
1513#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e
1514#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L
1515#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d
1516#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1517#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1518#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L
1519#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1520#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L
1521#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1522#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L
1523#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1524#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L
1525#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d
1526#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L
1527#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1528#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1529#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1530#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L
1531#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1532#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1533#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1534#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1535#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1536#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1537#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1538#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1539#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1540#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L
1541#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1542#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1543#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1544#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L
1545#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1546#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L
1547#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e
1548#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L
1549#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d
1550#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1551#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1552#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L
1553#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1554#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L
1555#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1556#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L
1557#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1558#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L
1559#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d
1560#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L
1561#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1562#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1563#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1564#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L
1565#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1566#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1567#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1568#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1569#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1570#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1571#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1572#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1573#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1574#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L
1575#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1576#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1577#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1578#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L
1579#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1580#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L
1581#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e
1582#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L
1583#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d
1584#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1585#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1586#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L
1587#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1588#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L
1589#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1590#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L
1591#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1592#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L
1593#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d
1594#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L
1595#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1596#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1597#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1598#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L
1599#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1600#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1601#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1602#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1603#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1604#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1605#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1606#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L
1607#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007
1608#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L
1609#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014
1610#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L
1611#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003
1612#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L
1613#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b
1614#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L
1615#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f
1616#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L
1617#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006
1618#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L
1619#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010
1620#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L
1621#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002
1622#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L
1623#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a
1624#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L
1625#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e
1626#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L
1627#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005
1628#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L
1629#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c
1630#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L
1631#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001
1632#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L
1633#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019
1634#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L
1635#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d
1636#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L
1637#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004
1638#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L
1639#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008
1640#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L
1641#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000
1642#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L
1643#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018
1644#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L
1645#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c
1646#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL
1647#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000
1648#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L
1649#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d
1650#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L
1651#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008
1652#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L
1653#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016
1654#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L
1655#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012
1656#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L
1657#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014
1658#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L
1659#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e
1660#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1661#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1662#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L
1663#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c
1664#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L
1665#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d
1666#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L
1667#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a
1668#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L
1669#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b
1670#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L
1671#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018
1672#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L
1673#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019
1674#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L
1675#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010
1676#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L
1677#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c
1678#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L
1679#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f
1680#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L
1681#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011
1682#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L
1683#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005
1684#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L
1685#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006
1686#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L
1687#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000
1688#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L
1689#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e
1690#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L
1691#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018
1692#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L
1693#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d
1694#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L
1695#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f
1696#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L
1697#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017
1698#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L
1699#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015
1700#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L
1701#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003
1702#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L
1703#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007
1704#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L
1705#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004
1706#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L
1707#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008
1708#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L
1709#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e
1710#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L
1711#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015
1712#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L
1713#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013
1714#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L
1715#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018
1716#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L
1717#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e
1718#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L
1719#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014
1720#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L
1721#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c
1722#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L
1723#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006
1724#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL
1725#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000
1726#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L
1727#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012
1728#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L
1729#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f
1730#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L
1731#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a
1732#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L
1733#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015
1734#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L
1735#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010
1736#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L
1737#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f
1738#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL
1739#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
1740#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1741#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1742#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L
1743#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1744#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L
1745#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008
1746#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1747#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1748#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L
1749#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014
1750#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L
1751#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d
1752#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
1753#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
1754#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
1755#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
1756#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L
1757#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e
1758#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL
1759#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000
1760#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L
1761#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007
1762#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L
1763#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d
1764#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1765#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1766#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L
1767#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1768#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L
1769#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008
1770#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L
1771#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1772#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L
1773#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014
1774#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L
1775#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d
1776#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L
1777#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013
1778#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L
1779#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012
1780#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L
1781#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e
1782#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL
1783#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000
1784#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L
1785#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007
1786#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L
1787#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d
1788#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1789#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1790#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L
1791#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1792#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L
1793#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008
1794#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L
1795#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1796#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L
1797#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014
1798#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L
1799#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d
1800#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L
1801#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013
1802#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L
1803#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012
1804#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L
1805#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e
1806#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL
1807#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000
1808#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L
1809#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007
1810#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L
1811#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d
1812#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1813#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1814#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L
1815#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1816#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L
1817#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008
1818#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L
1819#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1820#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L
1821#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014
1822#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L
1823#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d
1824#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L
1825#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013
1826#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L
1827#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012
1828#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L
1829#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e
1830#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL
1831#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000
1832#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L
1833#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007
1834#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L
1835#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d
1836#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL
1837#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000
1838#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL
1839#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000
1840#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL
1841#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000
1842#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL
1843#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000
1844#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL
1845#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000
1846#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL
1847#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000
1848#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL
1849#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000
1850#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
1851#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000
1852#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x00001000L
1853#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0x0000000c
1854#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x00000380L
1855#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x00000007
1856#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
1857#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002
1858#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
1859#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003
1860#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
1861#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004
1862#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
1863#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006
1864#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
1865#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001
1866#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
1867#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e
1868#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
1869#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a
1870#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
1871#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005
1872#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
1873#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b
1874#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL
1875#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000
1876#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L
1877#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010
1878#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL
1879#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000
1880#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L
1881#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010
1882#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL
1883#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000
1884#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L
1885#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010
1886#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL
1887#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000
1888#define COMPUTE_PGM_HI__INST_ATC_MASK 0x00000100L
1889#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x00000008
1890#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL
1891#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000
1892#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
1893#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018
1894#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L
1895#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019
1896#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L
1897#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016
1898#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
1899#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015
1900#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L
1901#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c
1902#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
1903#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017
1904#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L
1905#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a
1906#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
1907#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014
1908#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L
1909#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006
1910#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL
1911#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000
1912#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L
1913#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
1914#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d
1915#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018
1916#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L
1917#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f
1918#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
1919#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000
1920#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
1921#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007
1922#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
1923#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008
1924#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
1925#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009
1926#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
1927#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a
1928#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
1929#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b
1930#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
1931#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006
1932#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL
1933#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001
1934#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
1935#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018
1936#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
1937#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017
1938#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L
1939#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010
1940#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
1941#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016
1942#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L
1943#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c
1944#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x0000003fL
1945#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000
1946#define COMPUTE_START_X__START_MASK 0xffffffffL
1947#define COMPUTE_START_X__START__SHIFT 0x00000000
1948#define COMPUTE_START_Y__START_MASK 0xffffffffL
1949#define COMPUTE_START_Y__START__SHIFT 0x00000000
1950#define COMPUTE_START_Z__START_MASK 0xffffffffL
1951#define COMPUTE_START_Z__START__SHIFT 0x00000000
1952#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL
1953#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000
1954#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L
1955#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010
1956#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL
1957#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000
1958#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L
1959#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010
1960#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL
1961#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000
1962#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL
1963#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000
1964#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL
1965#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000
1966#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL
1967#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000
1968#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L
1969#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c
1970#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL
1971#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000
1972#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL
1973#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000
1974#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL
1975#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000
1976#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL
1977#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000
1978#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL
1979#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000
1980#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL
1981#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000
1982#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL
1983#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000
1984#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL
1985#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000
1986#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL
1987#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000
1988#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL
1989#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000
1990#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL
1991#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000
1992#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL
1993#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000
1994#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL
1995#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000
1996#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL
1997#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000
1998#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL
1999#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000
2000#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL
2001#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000
2002#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL
2003#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000
2004#define COMPUTE_VMID__DATA_MASK 0x0000000fL
2005#define COMPUTE_VMID__DATA__SHIFT 0x00000000
2006#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L
2007#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d
2008#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L
2009#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010
2010#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x000000ffL
2011#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000
2012#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL
2013#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002
2014#define CP_APPEND_DATA__DATA_MASK 0xffffffffL
2015#define CP_APPEND_DATA__DATA__SHIFT 0x00000000
2016#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL
2017#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000
2018#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL
2019#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000
2020#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL
2021#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000
2022#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL
2023#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000
2024#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
2025#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016
2026#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
2027#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006
2028#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
2029#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012
2030#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
2031#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f
2032#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
2033#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011
2034#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
2035#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008
2036#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
2037#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007
2038#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
2039#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014
2040#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
2041#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015
2042#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
2043#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a
2044#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
2045#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009
2046#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
2047#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000
2048#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
2049#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c
2050#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
2051#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d
2052#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
2053#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e
2054#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
2055#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013
2056#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL
2057#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000
2058#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL
2059#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000
2060#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL
2061#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002
2062#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL
2063#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000
2064#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL
2065#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000
2066#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL
2067#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002
2068#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL
2069#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000
2070#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x000000ffL
2071#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000
2072#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L
2073#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005
2074#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL
2075#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000
2076#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L
2077#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010
2078#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL
2079#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000
2080#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL
2081#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000
2082#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL
2083#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000
2084#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L
2085#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010
2086#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL
2087#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000
2088#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L
2089#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010
2090#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL
2091#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000
2092#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L
2093#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010
2094#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL
2095#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000
2096#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL
2097#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000
2098#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL
2099#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000
2100#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL
2101#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000
2102#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
2103#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c
2104#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L
2105#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010
2106#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L
2107#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014
2108#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL
2109#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000
2110#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
2111#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c
2112#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
2113#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008
2114#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL
2115#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000
2116#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL
2117#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000
2118#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
2119#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006
2120#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
2121#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007
2122#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
2123#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008
2124#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
2125#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009
2126#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
2127#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a
2128#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
2129#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b
2130#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
2131#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c
2132#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
2133#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d
2134#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
2135#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019
2136#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
2137#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a
2138#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
2139#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e
2140#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
2141#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000
2142#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
2143#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001
2144#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
2145#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013
2146#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
2147#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015
2148#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
2149#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d
2150#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
2151#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b
2152#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
2153#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c
2154#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
2155#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017
2156#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
2157#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016
2158#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
2159#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f
2160#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x00010000L
2161#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x00000010
2162#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
2163#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012
2164#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL
2165#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000
2166#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL
2167#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000
2168#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL
2169#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000
2170#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL
2171#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000
2172#define CP_COHER_STATUS__MEID_MASK 0x03000000L
2173#define CP_COHER_STATUS__MEID__SHIFT 0x00000018
2174#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L
2175#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e
2176#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
2177#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f
2178#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL
2179#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000
2180#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x00003f00L
2181#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008
2182#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL
2183#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000
2184#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L
2185#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010
2186#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
2187#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004
2188#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L
2189#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e
2190#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
2191#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c
2192#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
2193#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d
2194#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL
2195#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000
2196#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
2197#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d
2198#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
2199#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b
2200#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L
2201#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015
2202#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L
2203#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018
2204#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
2205#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e
2206#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
2207#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c
2208#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
2209#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a
2210#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L
2211#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016
2212#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL
2213#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000
2214#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL
2215#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000
2216#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL
2217#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000
2218#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL
2219#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000
2220#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL
2221#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000
2222#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
2223#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d
2224#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
2225#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b
2226#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L
2227#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015
2228#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L
2229#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018
2230#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
2231#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e
2232#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
2233#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c
2234#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
2235#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a
2236#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L
2237#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016
2238#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL
2239#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000
2240#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL
2241#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000
2242#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL
2243#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000
2244#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL
2245#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000
2246#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL
2247#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000
2248#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
2249#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c
2250#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
2251#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000
2252#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0x000000f0L
2253#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x00000004
2254#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x00000003L
2255#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x00000000
2256#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0x000000f0L
2257#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x00000004
2258#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x00003c00L
2259#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0x0000000a
2260#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0x000f0000L
2261#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x00000010
2262#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x00000003L
2263#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x00000000
2264#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0x000000f0L
2265#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x00000004
2266#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x00003c00L
2267#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0x0000000a
2268#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0x000f0000L
2269#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x00000010
2270#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x00000003L
2271#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x00000000
2272#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0x000000f0L
2273#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x00000004
2274#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x00003c00L
2275#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0x0000000a
2276#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0x000f0000L
2277#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x00000010
2278#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x00003c00L
2279#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0x0000000a
2280#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L
2281#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010
2282#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL
2283#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000
2284#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL
2285#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002
2286#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x00000003L
2287#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x00000000
2288#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0x0000ffffL
2289#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x00000000
2290#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L
2291#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d
2292#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
2293#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010
2294#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
2295#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018
2296#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL
2297#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000
2298#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL
2299#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000
2300#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL
2301#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000
2302#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL
2303#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000
2304#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL
2305#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000
2306#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL
2307#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000
2308#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL
2309#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000
2310#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL
2311#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000
2312#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L
2313#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008
2314#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL
2315#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L
2316#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010
2317#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000
2318#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL
2319#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000
2320#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL
2321#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002
2322#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL
2323#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000
2324#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL
2325#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000
2326#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL
2327#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000
2328#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL
2329#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000
2330#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL
2331#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000
2332#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL
2333#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002
2334#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL
2335#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000
2336#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL
2337#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000
2338#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL
2339#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000
2340#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL
2341#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000
2342#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2343#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2344#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2345#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2346#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2347#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2348#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
2349#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2350#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
2351#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2352#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
2353#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2354#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2355#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2356#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2357#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2358#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2359#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2360#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2361#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2362#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2363#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2364#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2365#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2366#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2367#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2368#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
2369#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2370#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
2371#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2372#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
2373#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2374#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2375#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2376#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2377#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2378#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2379#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2380#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2381#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2382#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2383#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2384#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2385#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2386#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2387#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2388#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2389#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2390#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2391#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2392#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
2393#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2394#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
2395#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2396#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
2397#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2398#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2399#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2400#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2401#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2402#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2403#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2404#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2405#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2406#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2407#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2408#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2409#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2410#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2411#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2412#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2413#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2414#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2415#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2416#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
2417#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2418#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
2419#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2420#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
2421#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2422#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2423#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2424#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2425#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2426#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2427#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2428#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2429#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2430#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2431#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2432#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2433#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2434#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2435#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2436#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2437#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2438#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L
2439#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013
2440#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L
2441#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014
2442#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
2443#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e
2444#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
2445#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f
2446#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
2447#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e
2448#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
2449#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d
2450#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
2451#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018
2452#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
2453#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016
2454#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
2455#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017
2456#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
2457#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b
2458#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
2459#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a
2460#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
2461#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011
2462#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2463#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2464#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2465#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2466#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2467#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2468#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
2469#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f
2470#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
2471#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e
2472#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
2473#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d
2474#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2475#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2476#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2477#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2478#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
2479#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017
2480#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2481#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2482#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2483#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2484#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2485#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2486#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2487#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2488#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
2489#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f
2490#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
2491#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e
2492#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
2493#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d
2494#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2495#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2496#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2497#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2498#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
2499#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017
2500#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2501#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2502#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
2503#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2504#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2505#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2506#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2507#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2508#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2509#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2510#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2511#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2512#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
2513#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f
2514#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
2515#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e
2516#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
2517#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d
2518#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2519#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2520#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2521#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2522#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
2523#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017
2524#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2525#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2526#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
2527#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2528#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2529#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2530#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2531#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2532#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2533#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2534#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2535#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2536#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
2537#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f
2538#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
2539#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e
2540#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
2541#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d
2542#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2543#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2544#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2545#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2546#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
2547#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017
2548#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2549#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2550#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
2551#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2552#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2553#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2554#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
2555#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2556#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2557#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2558#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x0000001fL
2559#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x00000000
2560#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
2561#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018
2562#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
2563#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004
2564#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
2565#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019
2566#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
2567#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c
2568#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
2569#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008
2570#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
2571#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d
2572#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
2573#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a
2574#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
2575#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006
2576#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
2577#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b
2578#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL
2579#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000
2580#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x000000ffL
2581#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000
2582#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL
2583#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002
2584#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L
2585#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000
2586#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x000000ffL
2587#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000
2588#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL
2589#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002
2590#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L
2591#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000
2592#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL
2593#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000
2594#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL
2595#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000
2596#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
2597#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001
2598#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
2599#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000
2600#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L
2601#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010
2602#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L
2603#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008
2604#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L
2605#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018
2606#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL
2607#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002
2608#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x00000001L
2609#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x00000000
2610#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL
2611#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000
2612#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL
2613#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000
2614#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L
2615#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010
2616#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL
2617#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000
2618#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L
2619#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008
2620#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL
2621#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000
2622#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00000fffL
2623#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000
2624#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00000fffL
2625#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000
2626#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL
2627#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000
2628#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL
2629#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000
2630#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL
2631#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000
2632#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL
2633#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000
2634#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL
2635#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000
2636#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL
2637#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000
2638#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL
2639#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000
2640#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL
2641#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000
2642#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL
2643#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000
2644#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL
2645#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000
2646#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL
2647#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000
2648#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL
2649#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000
2650#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL
2651#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000
2652#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL
2653#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000
2654#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL
2655#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000
2656#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL
2657#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000
2658#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL
2659#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000
2660#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL
2661#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000
2662#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL
2663#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000
2664#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL
2665#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000
2666#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
2667#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008
2668#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
2669#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
2670#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL
2671#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
2672#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L
2673#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004
2674#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
2675#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f
2676#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL
2677#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000
2678#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x00000001L
2679#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000
2680#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
2681#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001
2682#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
2683#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000
2684#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
2685#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018
2686#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
2687#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010
2688#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L
2689#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0x0000000f
2690#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL
2691#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000
2692#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL
2693#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000
2694#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffffffffL
2695#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000
2696#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL
2697#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002
2698#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x00000003L
2699#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x00000000
2700#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x00000001L
2701#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x00000000
2702#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL
2703#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000
2704#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L
2705#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008
2706#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL
2707#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
2708#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL
2709#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000
2710#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L
2711#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000010
2712#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L
2713#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018
2714#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2715#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2716#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2717#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2718#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L
2719#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008
2720#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL
2721#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000
2722#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2723#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2724#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2725#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2726#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L
2727#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2728#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2729#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2730#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2731#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2732#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2733#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2734#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL
2735#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000
2736#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL
2737#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000
2738#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL
2739#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
2740#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL
2741#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000
2742#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L
2743#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018
2744#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2745#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2746#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2747#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2748#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L
2749#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008
2750#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL
2751#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000
2752#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2753#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2754#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2755#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2756#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L
2757#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2758#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2759#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2760#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2761#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2762#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2763#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2764#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL
2765#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000
2766#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL
2767#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000
2768#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL
2769#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000
2770#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L
2771#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018
2772#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2773#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2774#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2775#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2776#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L
2777#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008
2778#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL
2779#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000
2780#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2781#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2782#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2783#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2784#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L
2785#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2786#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2787#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2788#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2789#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2790#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2791#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2792#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL
2793#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000
2794#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL
2795#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000
2796#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL
2797#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000
2798#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L
2799#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010
2800#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L
2801#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018
2802#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2803#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2804#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2805#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2806#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L
2807#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
2808#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL
2809#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
2810#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2811#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2812#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2813#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2814#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L
2815#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2816#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL
2817#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000
2818#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2819#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2820#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2821#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2822#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2823#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2824#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL
2825#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000
2826#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL
2827#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000
2828#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL
2829#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000
2830#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L
2831#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008
2832#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L
2833#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010
2834#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L
2835#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c
2836#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL
2837#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000
2838#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0x000000ffL
2839#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x00000000
2840#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x000000ffL
2841#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000
2842#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffcL
2843#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x00000002
2844#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL
2845#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002
2846#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L
2847#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010
2848#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL
2849#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000
2850#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL
2851#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000
2852#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
2853#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000
2854#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
2855#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000
2856#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
2857#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000
2858#define CP_RINGID__RINGID_MASK 0x00000003L
2859#define CP_RINGID__RINGID__SHIFT 0x00000000
2860#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL
2861#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000
2862#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L
2863#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008
2864#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L
2865#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010
2866#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L
2867#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018
2868#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L
2869#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010
2870#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L
2871#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018
2872#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL
2873#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000
2874#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L
2875#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008
2876#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL
2877#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000
2878#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L
2879#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008
2880#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L
2881#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010
2882#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL
2883#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000
2884#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L
2885#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018
2886#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L
2887#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010
2888#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL
2889#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000
2890#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL
2891#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000
2892#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L
2893#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010
2894#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL
2895#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000
2896#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L
2897#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010
2898#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL
2899#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000
2900#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L
2901#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010
2902#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL
2903#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000
2904#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL
2905#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000
2906#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffffL
2907#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x00000000
2908#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffffL
2909#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x00000000
2910#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL
2911#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000
2912#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL
2913#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000
2914#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL
2915#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000
2916#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL
2917#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000
2918#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
2919#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018
2920#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L
2921#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d
2922#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
2923#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014
2924#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
2925#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010
2926#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L
2927#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003
2928#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
2929#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000
2930#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
2931#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a
2932#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
2933#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b
2934#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
2935#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d
2936#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
2937#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c
2938#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x00004000L
2939#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0x0000000e
2940#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
2941#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f
2942#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x00010000L
2943#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x00000010
2944#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x00020000L
2945#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x00000011
2946#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
2947#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000
2948#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
2949#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004
2950#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
2951#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002
2952#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x10000000L
2953#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x0000001c
2954#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
2955#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x0000001c
2956#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
2957#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b
2958#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
2959#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a
2960#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
2961#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017
2962#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
2963#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018
2964#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
2965#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019
2966#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
2967#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c
2968#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
2969#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019
2970#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
2971#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a
2972#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
2973#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d
2974#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
2975#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b
2976#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
2977#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015
2978#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
2979#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016
2980#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
2981#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b
2982#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
2983#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010
2984#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
2985#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c
2986#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
2987#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d
2988#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
2989#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e
2990#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
2991#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012
2992#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
2993#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f
2994#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
2995#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a
2996#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
2997#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009
2998#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x00000040L
2999#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x00000006
3000#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
3001#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005
3002#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
3003#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000014
3004#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
3005#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000013
3006#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
3007#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000
3008#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
3009#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001
3010#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000080L
3011#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000007
3012#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
3013#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002
3014#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
3015#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004
3016#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
3017#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008
3018#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
3019#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018
3020#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
3021#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011
3022#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
3023#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017
3024#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
3025#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f
3026#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
3027#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e
3028#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
3029#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000
3030#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
3031#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006
3032#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000100L
3033#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000008
3034#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
3035#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004
3036#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
3037#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001
3038#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
3039#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003
3040#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
3041#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005
3042#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
3043#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007
3044#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
3045#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a
3046#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
3047#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b
3048#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
3049#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002
3050#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
3051#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c
3052#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
3053#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d
3054#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
3055#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e
3056#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
3057#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f
3058#define CP_STAT__CE_BUSY_MASK 0x04000000L
3059#define CP_STAT__CE_BUSY__SHIFT 0x0000001a
3060#define CP_STAT__CP_BUSY_MASK 0x80000000L
3061#define CP_STAT__CP_BUSY__SHIFT 0x0000001f
3062#define CP_STAT__CPC_CPG_BUSY_MASK 0x02000000L
3063#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x00000019
3064#define CP_STAT__DC_BUSY_MASK 0x00002000L
3065#define CP_STAT__DC_BUSY__SHIFT 0x0000000d
3066#define CP_STAT__DMA_BUSY_MASK 0x00400000L
3067#define CP_STAT__DMA_BUSY__SHIFT 0x00000016
3068#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
3069#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014
3070#define CP_STAT__ME_BUSY_MASK 0x00020000L
3071#define CP_STAT__ME_BUSY__SHIFT 0x00000011
3072#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
3073#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010
3074#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x00000080L
3075#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x00000007
3076#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x00000100L
3077#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x00000008
3078#define CP_STAT__PFP_BUSY_MASK 0x00008000L
3079#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f
3080#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
3081#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012
3082#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
3083#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017
3084#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
3085#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d
3086#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
3087#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e
3088#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
3089#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c
3090#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
3091#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a
3092#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
3093#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b
3094#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
3095#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009
3096#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
3097#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c
3098#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
3099#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018
3100#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
3101#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013
3102#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
3103#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015
3104#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
3105#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b
3106#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x000000ffL
3107#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000
3108#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL
3109#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002
3110#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL
3111#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000
3112#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL
3113#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000
3114#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL
3115#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000
3116#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL
3117#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000
3118#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L
3119#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008
3120#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L
3121#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010
3122#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffffffffL
3123#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000
3124#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL
3125#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002
3126#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x00000003L
3127#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x00000000
3128#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
3129#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000
3130#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL
3131#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000
3132#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL
3133#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000
3134#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL
3135#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000
3136#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL
3137#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000
3138#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL
3139#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000
3140#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL
3141#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000
3142#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL
3143#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000
3144#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL
3145#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000
3146#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL
3147#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000
3148#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL
3149#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000
3150#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL
3151#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000
3152#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL
3153#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000
3154#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL
3155#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000
3156#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL
3157#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000
3158#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL
3159#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000
3160#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL
3161#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000
3162#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000ffffL
3163#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x00000000
3164#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000L
3165#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x00000010
3166#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000ffffL
3167#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x00000000
3168#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000L
3169#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x00000010
3170#define CP_VMID__VMID_MASK 0x0000000fL
3171#define CP_VMID__VMID__SHIFT 0x00000000
3172#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL
3173#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000
3174#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL
3175#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000
3176#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
3177#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018
3178#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L
3179#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d
3180#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
3181#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014
3182#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
3183#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010
3184#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L
3185#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003
3186#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
3187#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000
3188#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
3189#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000
3190#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
3191#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000
3192#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
3193#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008
3194#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L
3195#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a
3196#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
3197#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c
3198#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L
3199#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e
3200#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
3201#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010
3202#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L
3203#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004
3204#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL
3205#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000
3206#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x00fff000L
3207#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c
3208#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
3209#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f
3210#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
3211#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e
3212#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
3213#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d
3214#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
3215#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c
3216#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
3217#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b
3218#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
3219#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a
3220#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
3221#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019
3222#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
3223#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018
3224#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00f00000L
3225#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x00000014
3226#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
3227#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001
3228#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
3229#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004
3230#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L
3231#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x00000010
3232#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0f000000L
3233#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000018
3234#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000L
3235#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x0000001c
3236#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L
3237#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0x0000000c
3238#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000f00L
3239#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008
3240#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
3241#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000
3242#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L
3243#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a
3244#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L
3245#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018
3246#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L
3247#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005
3248#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL
3249#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000
3250#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
3251#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000
3252#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L
3253#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009
3254#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
3255#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012
3256#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L
3257#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x00000010
3258#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
3259#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011
3260#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x00000100L
3261#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x00000008
3262#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x00000020L
3263#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x00000080L
3264#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x00000007
3265#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x00000005
3266#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
3267#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d
3268#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
3269#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013
3270#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x80000000L
3271#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x0000001f
3272#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
3273#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002
3274#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
3275#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001
3276#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
3277#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e
3278#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
3279#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x0000001f
3280#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
3281#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004
3282#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
3283#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003
3284#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x00000040L
3285#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x00000006
3286#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
3287#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c
3288#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
3289#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f
3290#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00020000L
3291#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x00000011
3292#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xfc000000L
3293#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x0000001a
3294#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
3295#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x00000019
3296#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
3297#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x00000018
3298#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
3299#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004
3300#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00200000L
3301#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x00000015
3302#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00004000L
3303#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0x0000000e
3304#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00010000L
3305#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0x00000010
3306#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00008000L
3307#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0x0000000f
3308#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00080000L
3309#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x00000013
3310#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00002000L
3311#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0x0000000d
3312#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
3313#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x0000001b
3314#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
3315#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x00000017
3316#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000800L
3317#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0x0000000b
3318#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000400L
3319#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x0000000a
3320#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
3321#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007
3322#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00100000L
3323#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x00000014
3324#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
3325#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003
3326#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
3327#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008
3328#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
3329#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x0000001d
3330#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
3331#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x0000001c
3332#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
3333#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x0000001a
3334#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00001000L
3335#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0x0000000c
3336#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00400000L
3337#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x00000016
3338#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00800000L
3339#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x00000017
3340#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
3341#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005
3342#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
3343#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006
3344#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
3345#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002
3346#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00040000L
3347#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x00000012
3348#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffffc0L
3349#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x00000006
3350#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000020L
3351#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x00000005
3352#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
3353#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001
3354#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
3355#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000
3356#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
3357#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002
3358#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
3359#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001
3360#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
3361#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f
3362#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
3363#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e
3364#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
3365#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006
3366#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
3367#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013
3368#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L
3369#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a
3370#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
3371#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c
3372#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
3373#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008
3374#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
3375#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007
3376#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
3377#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010
3378#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
3379#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000
3380#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L
3381#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018
3382#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
3383#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012
3384#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
3385#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e
3386#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
3387#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f
3388#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
3389#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011
3390#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
3391#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017
3392#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
3393#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003
3394#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
3395#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002
3396#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
3397#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d
3398#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
3399#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004
3400#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
3401#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015
3402#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
3403#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c
3404#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
3405#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016
3406#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL
3407#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000
3408#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL
3409#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000
3410#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL
3411#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000
3412#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
3413#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007
3414#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
3415#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003
3416#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
3417#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f
3418#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
3419#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e
3420#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
3421#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000
3422#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
3423#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014
3424#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
3425#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008
3426#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
3427#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001
3428#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
3429#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004
3430#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
3431#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002
3432#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0x0000000fL
3433#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x00000000
3434#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0x000000f0L
3435#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x00000004
3436#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x00018000L
3437#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0x0000000f
3438#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x00006000L
3439#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0x0000000d
3440#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x00060000L
3441#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x00000011
3442#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x00180000L
3443#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x00000013
3444#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x00001f00L
3445#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x00000008
3446#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x003ff800L
3447#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0x0000000b
3448#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x000007ffL
3449#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x00000000
3450#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x003fffffL
3451#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x00000000
3452#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L
3453#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d
3454#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL
3455#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000
3456#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
3457#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019
3458#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
3459#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018
3460#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
3461#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015
3462#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
3463#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c
3464#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
3465#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b
3466#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
3467#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010
3468#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
3469#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011
3470#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
3471#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012
3472#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
3473#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013
3474#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
3475#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008
3476#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
3477#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000
3478#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
3479#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018
3480#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
3481#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004
3482#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
3483#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014
3484#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L
3485#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015
3486#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L
3487#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a
3488#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x0000001fL
3489#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x00000000
3490#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x000003e0L
3491#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x00000005
3492#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L
3493#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010
3494#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL
3495#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000
3496#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L
3497#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008
3498#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L
3499#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f
3500#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L
3501#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019
3502#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL
3503#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000
3504#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x01e00000L
3505#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000015
3506#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L
3507#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007
3508#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x001fc000L
3509#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e
3510#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000L
3511#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000019
3512#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL
3513#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000
3514#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
3515#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010
3516#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
3517#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001
3518#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
3519#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002
3520#define DB_HTILE_SURFACE__LINEAR_MASK 0x00000001L
3521#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x00000000
3522#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L
3523#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a
3524#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L
3525#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004
3526#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
3527#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003
3528#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3529#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3530#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3531#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3532#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
3533#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
3534#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
3535#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
3536#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
3537#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
3538#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
3539#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
3540#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
3541#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
3542#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
3543#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
3544#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
3545#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
3546#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
3547#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
3548#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
3549#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
3550#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3551#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3552#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3553#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3554#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L
3555#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c
3556#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L
3557#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018
3558#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
3559#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
3560#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
3561#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
3562#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
3563#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
3564#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
3565#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
3566#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
3567#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
3568#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
3569#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
3570#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
3571#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
3572#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3573#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3574#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3575#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3576#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
3577#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
3578#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L
3579#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018
3580#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
3581#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
3582#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L
3583#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a
3584#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
3585#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
3586#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3587#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3588#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3589#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3590#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
3591#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
3592#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L
3593#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018
3594#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
3595#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
3596#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L
3597#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a
3598#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
3599#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
3600#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L
3601#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010
3602#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L
3603#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018
3604#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL
3605#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000
3606#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L
3607#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008
3608#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL
3609#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000
3610#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL
3611#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000
3612#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL
3613#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000
3614#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL
3615#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000
3616#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL
3617#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000
3618#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL
3619#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000
3620#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL
3621#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000
3622#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL
3623#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000
3624#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL
3625#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000
3626#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL
3627#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000
3628#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL
3629#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000
3630#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL
3631#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000
3632#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL
3633#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000
3634#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL
3635#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000
3636#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL
3637#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000
3638#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL
3639#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000
3640#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
3641#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007
3642#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L
3643#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008
3644#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
3645#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000
3646#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
3647#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006
3648#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
3649#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002
3650#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
3651#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004
3652#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
3653#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001
3654#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
3655#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005
3656#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
3657#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003
3658#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
3659#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008
3660#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
3661#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a
3662#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
3663#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007
3664#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
3665#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x00000017
3666#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
3667#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009
3668#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
3669#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006
3670#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
3671#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005
3672#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001c0000L
3673#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x00000012
3674#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
3675#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0x0000000f
3676#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
3677#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0x0000000c
3678#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
3679#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000
3680#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL
3681#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002
3682#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
3683#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x00000016
3684#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
3685#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x00000015
3686#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
3687#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0x0000000b
3688#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
3689#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012
3690#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
3691#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a
3692#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
3693#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010
3694#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
3695#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008
3696#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
3697#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007
3698#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
3699#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a
3700#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
3701#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d
3702#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL
3703#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002
3704#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
3705#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004
3706#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
3707#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000
3708#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
3709#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f
3710#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
3711#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006
3712#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
3713#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c
3714#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
3715#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c
3716#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
3717#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e
3718#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
3719#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b
3720#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
3721#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013
3722#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
3723#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b
3724#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
3725#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d
3726#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
3727#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011
3728#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L
3729#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015
3730#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
3731#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009
3732#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
3733#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f
3734#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
3735#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b
3736#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
3737#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d
3738#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
3739#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007
3740#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
3741#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c
3742#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
3743#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009
3744#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
3745#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a
3746#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
3747#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006
3748#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
3749#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008
3750#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
3751#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002
3752#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
3753#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001
3754#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
3755#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000
3756#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
3757#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004
3758#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
3759#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000
3760#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L
3761#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c
3762#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L
3763#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004
3764#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
3765#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018
3766#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
3767#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000
3768#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L
3769#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c
3770#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L
3771#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004
3772#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
3773#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018
3774#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL
3775#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000
3776#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L
3777#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c
3778#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL
3779#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000
3780#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L
3781#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014
3782#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L
3783#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008
3784#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L
3785#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010
3786#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L
3787#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004
3788#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
3789#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b
3790#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
3791#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000
3792#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x00700000L
3793#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x00000014
3794#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0x0000e000L
3795#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0x0000000d
3796#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
3797#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d
3798#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL
3799#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000
3800#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L
3801#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008
3802#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L
3803#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018
3804#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL
3805#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000
3806#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L
3807#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010
3808#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L
3809#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008
3810#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L
3811#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018
3812#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL
3813#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000
3814#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L
3815#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010
3816#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL
3817#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000
3818#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
3819#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010
3820#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L
3821#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012
3822#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
3823#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000
3824#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL
3825#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002
3826#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
3827#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004
3828#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L
3829#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006
3830#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
3831#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008
3832#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L
3833#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a
3834#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
3835#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c
3836#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L
3837#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e
3838#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
3839#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e
3840#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
3841#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f
3842#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x07f00000L
3843#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014
3844#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L
3845#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005
3846#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL
3847#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000
3848#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L
3849#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f
3850#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x08000000L
3851#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x0000001b
3852#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
3853#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b
3854#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000L
3855#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x0000001c
3856#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000L
3857#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x0000001d
3858#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
3859#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b
3860#define DB_Z_INFO__FORMAT_MASK 0x00000003L
3861#define DB_Z_INFO__FORMAT__SHIFT 0x00000000
3862#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL
3863#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002
3864#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
3865#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c
3866#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x00700000L
3867#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x00000014
3868#define DB_Z_INFO__TILE_SPLIT_MASK 0x0000e000L
3869#define DB_Z_INFO__TILE_SPLIT__SHIFT 0x0000000d
3870#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
3871#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d
3872#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
3873#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f
3874#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL
3875#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000
3876#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL
3877#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000
3878#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL
3879#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000
3880#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL
3881#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000
3882#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL
3883#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000
3884#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL
3885#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000
3886#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
3887#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
3888#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
3889#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
3890#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
3891#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
3892#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
3893#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
3894#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
3895#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
3896#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
3897#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
3898#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
3899#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
3900#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
3901#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
3902#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
3903#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
3904#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL
3905#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000
3906#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
3907#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f
3908#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
3909#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014
3910#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00010000L
3911#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x00000010
3912#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
3913#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d
3914#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL
3915#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000
3916#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL
3917#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002
3918#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3919#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3920#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L
3921#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006
3922#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
3923#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x00000019
3924#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
3925#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b
3926#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL
3927#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002
3928#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3929#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3930#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L
3931#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006
3932#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
3933#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x00000019
3934#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
3935#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b
3936#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL
3937#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002
3938#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3939#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3940#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L
3941#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006
3942#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
3943#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x00000019
3944#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
3945#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b
3946#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL
3947#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002
3948#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3949#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3950#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L
3951#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006
3952#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
3953#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x00000019
3954#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
3955#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b
3956#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL
3957#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002
3958#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3959#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3960#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L
3961#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006
3962#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
3963#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x00000019
3964#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
3965#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b
3966#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL
3967#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002
3968#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3969#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3970#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L
3971#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006
3972#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
3973#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x00000019
3974#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
3975#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b
3976#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL
3977#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002
3978#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3979#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3980#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L
3981#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006
3982#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
3983#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x00000019
3984#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
3985#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b
3986#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL
3987#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002
3988#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3989#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3990#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L
3991#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006
3992#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
3993#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x00000019
3994#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
3995#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b
3996#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL
3997#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002
3998#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3999#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4000#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L
4001#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006
4002#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
4003#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x00000019
4004#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
4005#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b
4006#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL
4007#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002
4008#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4009#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4010#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L
4011#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006
4012#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
4013#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x00000019
4014#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
4015#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b
4016#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL
4017#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002
4018#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4019#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4020#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L
4021#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006
4022#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
4023#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x00000019
4024#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
4025#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b
4026#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL
4027#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002
4028#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4029#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4030#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L
4031#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006
4032#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
4033#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x00000019
4034#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
4035#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b
4036#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL
4037#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002
4038#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4039#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4040#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L
4041#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006
4042#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
4043#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x00000019
4044#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
4045#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b
4046#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL
4047#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002
4048#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4049#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4050#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L
4051#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006
4052#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
4053#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x00000019
4054#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
4055#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b
4056#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL
4057#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002
4058#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4059#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4060#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L
4061#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006
4062#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
4063#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x00000019
4064#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
4065#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b
4066#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL
4067#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002
4068#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4069#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4070#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L
4071#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006
4072#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
4073#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x00000019
4074#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
4075#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b
4076#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL
4077#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002
4078#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4079#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4080#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L
4081#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006
4082#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
4083#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x00000019
4084#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
4085#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b
4086#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL
4087#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002
4088#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4089#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4090#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L
4091#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006
4092#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
4093#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x00000019
4094#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
4095#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b
4096#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL
4097#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002
4098#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4099#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4100#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L
4101#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006
4102#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
4103#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x00000019
4104#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
4105#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b
4106#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL
4107#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002
4108#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4109#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4110#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L
4111#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006
4112#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
4113#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x00000019
4114#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
4115#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b
4116#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL
4117#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002
4118#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4119#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4120#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L
4121#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006
4122#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
4123#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x00000019
4124#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
4125#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b
4126#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL
4127#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002
4128#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4129#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4130#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L
4131#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006
4132#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
4133#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x00000019
4134#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
4135#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b
4136#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL
4137#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002
4138#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4139#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4140#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L
4141#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006
4142#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
4143#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x00000019
4144#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
4145#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b
4146#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL
4147#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002
4148#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4149#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4150#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L
4151#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006
4152#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
4153#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x00000019
4154#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
4155#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b
4156#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL
4157#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002
4158#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4159#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4160#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L
4161#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006
4162#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
4163#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x00000019
4164#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
4165#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b
4166#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL
4167#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002
4168#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4169#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4170#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L
4171#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006
4172#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
4173#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x00000019
4174#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
4175#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b
4176#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL
4177#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002
4178#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4179#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4180#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L
4181#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006
4182#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
4183#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x00000019
4184#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
4185#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b
4186#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL
4187#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002
4188#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4189#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4190#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L
4191#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006
4192#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
4193#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x00000019
4194#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
4195#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b
4196#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL
4197#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002
4198#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4199#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4200#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L
4201#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006
4202#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
4203#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x00000019
4204#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
4205#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b
4206#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL
4207#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002
4208#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4209#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4210#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L
4211#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006
4212#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
4213#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x00000019
4214#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
4215#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b
4216#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL
4217#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002
4218#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4219#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4220#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L
4221#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006
4222#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
4223#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x00000019
4224#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
4225#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b
4226#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL
4227#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002
4228#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4229#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4230#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L
4231#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006
4232#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
4233#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x00000019
4234#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
4235#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b
4236#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
4237#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
4238#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L
4239#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001
4240#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L
4241#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004
4242#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L
4243#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010
4244#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
4245#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003
4246#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL
4247#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000
4248#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L
4249#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010
4250#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL
4251#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000
4252#define GDS_ATOM_CNTL__DMODE_MASK 0x00000100L
4253#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008
4254#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L
4255#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006
4256#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00L
4257#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x00000009
4258#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
4259#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000
4260#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL
4261#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001
4262#define GDS_ATOM_DST__DST_MASK 0xffffffffL
4263#define GDS_ATOM_DST__DST__SHIFT 0x00000000
4264#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL
4265#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000
4266#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L
4267#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008
4268#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL
4269#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000
4270#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L
4271#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008
4272#define GDS_ATOM_OP__OP_MASK 0x000000ffL
4273#define GDS_ATOM_OP__OP__SHIFT 0x00000000
4274#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L
4275#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008
4276#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL
4277#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000
4278#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL
4279#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000
4280#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL
4281#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000
4282#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL
4283#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000
4284#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL
4285#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000
4286#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L
4287#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010
4288#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL
4289#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000
4290#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL
4291#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000
4292#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL
4293#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000
4294#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL
4295#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000
4296#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
4297#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004
4298#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
4299#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003
4300#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
4301#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006
4302#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
4303#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005
4304#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
4305#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000
4306#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
4307#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001
4308#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
4309#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002
4310#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
4311#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001
4312#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
4313#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003
4314#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
4315#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005
4316#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
4317#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007
4318#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL
4319#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000
4320#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L
4321#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005
4322#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL
4323#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000
4324#define GDS_DEBUG_REG0__buff_write_MASK 0x00020000L
4325#define GDS_DEBUG_REG0__buff_write__SHIFT 0x00000011
4326#define GDS_DEBUG_REG0__cstate_MASK 0x0001e000L
4327#define GDS_DEBUG_REG0__cstate__SHIFT 0x0000000d
4328#define GDS_DEBUG_REG0__flush_request_MASK 0x00040000L
4329#define GDS_DEBUG_REG0__flush_request__SHIFT 0x00000012
4330#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x00001000L
4331#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0x0000000c
4332#define GDS_DEBUG_REG0__spare1_MASK 0x00000001L
4333#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000
4334#define GDS_DEBUG_REG0__spare_MASK 0xff000000L
4335#define GDS_DEBUG_REG0__spare__SHIFT 0x00000018
4336#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x00100000L
4337#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x00000014
4338#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x00200000L
4339#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x00000015
4340#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x00080000L
4341#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x00000013
4342#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x00000040L
4343#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x00000006
4344#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0x00000f80L
4345#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x00000007
4346#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x00200000L
4347#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x00000015
4348#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x00100000L
4349#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x00000014
4350#define GDS_DEBUG_REG1__awaiting_data_MASK 0x00080000L
4351#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x00000013
4352#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x00800000L
4353#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x00000017
4354#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x00400000L
4355#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x00000016
4356#define GDS_DEBUG_REG1__data_ready_MASK 0x00040000L
4357#define GDS_DEBUG_REG1__data_ready__SHIFT 0x00000012
4358#define GDS_DEBUG_REG1__pixel_addr_MASK 0x0001fffcL
4359#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x00000002
4360#define GDS_DEBUG_REG1__pixel_vld_MASK 0x00020000L
4361#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x00000011
4362#define GDS_DEBUG_REG1__spare_MASK 0xff000000L
4363#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018
4364#define GDS_DEBUG_REG1__tag_hit_MASK 0x00000001L
4365#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x00000000
4366#define GDS_DEBUG_REG1__tag_miss_MASK 0x00000002L
4367#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x00000001
4368#define GDS_DEBUG_REG2__app_sel_MASK 0x000000f0L
4369#define GDS_DEBUG_REG2__app_sel__SHIFT 0x00000004
4370#define GDS_DEBUG_REG2__cmd_write_MASK 0x00000008L
4371#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x00000003
4372#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x00000002L
4373#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x00000001
4374#define GDS_DEBUG_REG2__ds_full_MASK 0x00000001L
4375#define GDS_DEBUG_REG2__ds_full__SHIFT 0x00000000
4376#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x00000004L
4377#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x00000002
4378#define GDS_DEBUG_REG2__req_MASK 0x007fff00L
4379#define GDS_DEBUG_REG2__req__SHIFT 0x00000008
4380#define GDS_DEBUG_REG2__spare_MASK 0xff000000L
4381#define GDS_DEBUG_REG2__spare__SHIFT 0x00000018
4382#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x00007800L
4383#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0x0000000b
4384#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x000007ffL
4385#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x00000000
4386#define GDS_DEBUG_REG3__spare_MASK 0xff000000L
4387#define GDS_DEBUG_REG3__spare__SHIFT 0x00000018
4388#define GDS_DEBUG_REG4__cmd_write_MASK 0x00020000L
4389#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x00000011
4390#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x00010000L
4391#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x00000010
4392#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x00002000L
4393#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0x0000000d
4394#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x00008000L
4395#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0x0000000f
4396#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x00001000L
4397#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0x0000000c
4398#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x00004000L
4399#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0x0000000e
4400#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x00000400L
4401#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0x0000000a
4402#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x00000800L
4403#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0x0000000b
4404#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x00000200L
4405#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x00000009
4406#define GDS_DEBUG_REG4__cur_reso_MASK 0x000001f8L
4407#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x00000003
4408#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x00080000L
4409#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x00000013
4410#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x00040000L
4411#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x00000012
4412#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x00200000L
4413#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x00000015
4414#define GDS_DEBUG_REG4__gws_busy_MASK 0x00000001L
4415#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x00000000
4416#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x00000004L
4417#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x00000002
4418#define GDS_DEBUG_REG4__gws_req_MASK 0x00000002L
4419#define GDS_DEBUG_REG4__gws_req__SHIFT 0x00000001
4420#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x00400000L
4421#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x00000016
4422#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x00800000L
4423#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x00000017
4424#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x00100000L
4425#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x00000014
4426#define GDS_DEBUG_REG4__spare_MASK 0xff000000L
4427#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018
4428#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x00000004L
4429#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x00000002
4430#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x00000008L
4431#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x00000003
4432#define GDS_DEBUG_REG5__dec_error_MASK 0x00000002L
4433#define GDS_DEBUG_REG5__dec_error__SHIFT 0x00000001
4434#define GDS_DEBUG_REG5__error_ds_address_MASK 0x003fff00L
4435#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x00000008
4436#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000L
4437#define GDS_DEBUG_REG5__spare1__SHIFT 0x00000016
4438#define GDS_DEBUG_REG5__spare_MASK 0xff000000L
4439#define GDS_DEBUG_REG5__spare__SHIFT 0x00000018
4440#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x00000010L
4441#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x00000004
4442#define GDS_DEBUG_REG5__write_dis_MASK 0x00000001L
4443#define GDS_DEBUG_REG5__write_dis__SHIFT 0x00000000
4444#define GDS_DEBUG_REG6__counters_busy_MASK 0x001fffe0L
4445#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x00000005
4446#define GDS_DEBUG_REG6__counters_enabled_MASK 0x0000001eL
4447#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x00000001
4448#define GDS_DEBUG_REG6__oa_busy_MASK 0x00000001L
4449#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x00000000
4450#define GDS_DEBUG_REG6__spare_MASK 0xff000000L
4451#define GDS_DEBUG_REG6__spare__SHIFT 0x00000018
4452#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
4453#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x00000010
4454#define GDS_ENHANCE__MISC_MASK 0x0000ffffL
4455#define GDS_ENHANCE__MISC__SHIFT 0x00000000
4456#define GDS_ENHANCE__UNUSED_MASK 0xffff0000L
4457#define GDS_ENHANCE__UNUSED__SHIFT 0x00000010
4458#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff0000L
4459#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x00000010
4460#define GDS_GRBM_SECDED_CNT__SEC_MASK 0x0000ffffL
4461#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x00000000
4462#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003fL
4463#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x00000000
4464#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0L
4465#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x00000006
4466#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000ffffL
4467#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x00000000
4468#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000L
4469#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x00000010
4470#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001ffeL
4471#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x00000001
4472#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
4473#define GDS_GWS_RESOURCE__DED__SHIFT 0x0000000e
4474#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
4475#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x00000000
4476#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L
4477#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x0000001c
4478#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07ff0000L
4479#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x00000010
4480#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L
4481#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x0000001b
4482#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
4483#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x0000000f
4484#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
4485#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x00000000
4486#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000ff00L
4487#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x00000008
4488#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
4489#define GDS_GWS_RESOURCE__TYPE__SHIFT 0x0000000d
4490#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000L
4491#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x0000001d
4492#define GDS_OA_DED__ME0_CS_DED_MASK 0x00000004L
4493#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x00000002
4494#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
4495#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x00000000
4496#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
4497#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x00000001
4498#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
4499#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x00000004
4500#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
4501#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x00000005
4502#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
4503#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x00000006
4504#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
4505#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x00000007
4506#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
4507#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x00000008
4508#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
4509#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x00000009
4510#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
4511#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0x0000000a
4512#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
4513#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0x0000000b
4514#define GDS_OA_DED__UNUSED0_MASK 0x00000008L
4515#define GDS_OA_DED__UNUSED0__SHIFT 0x00000003
4516#define GDS_OA_DED__UNUSED1_MASK 0xfffff000L
4517#define GDS_OA_DED__UNUSED1__SHIFT 0x0000000c
4518#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4519#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4520#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4521#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4522#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL
4523#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000
4524#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L
4525#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a
4526#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
4527#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
4528#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
4529#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
4530#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
4531#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
4532#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4533#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4534#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4535#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4536#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
4537#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
4538#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
4539#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
4540#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
4541#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
4542#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4543#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4544#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4545#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4546#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
4547#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
4548#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
4549#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
4550#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
4551#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
4552#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4553#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4554#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4555#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4556#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
4557#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
4558#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
4559#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
4560#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
4561#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
4562#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffffL
4563#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x00000000
4564#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffffL
4565#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x00000000
4566#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffffL
4567#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x00000000
4568#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffffL
4569#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x00000000
4570#define GDS_RD_DATA__READ_DATA_MASK 0xffffffffL
4571#define GDS_RD_DATA__READ_DATA__SHIFT 0x00000000
4572#define GDS_SECDED_CNT__DED_MASK 0xffff0000L
4573#define GDS_SECDED_CNT__DED__SHIFT 0x00000010
4574#define GDS_SECDED_CNT__SEC_MASK 0x0000ffffL
4575#define GDS_SECDED_CNT__SEC__SHIFT 0x00000000
4576#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffffL
4577#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x00000000
4578#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffffL
4579#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x00000000
4580#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffffL
4581#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x00000000
4582#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffffL
4583#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x00000000
4584#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffffL
4585#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x00000000
4586#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
4587#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000
4588#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL
4589#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000
4590#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L
4591#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010
4592#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
4593#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000
4594#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL
4595#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000
4596#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x0000003fL
4597#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x00000000
4598#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffffL
4599#define GRBM_DEBUG_DATA__DATA__SHIFT 0x00000000
4600#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000040L
4601#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000006
4602#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x00001000L
4603#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x0000000c
4604#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0x00000f00L
4605#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x00000008
4606#define GRBM_DEBUG__IGNORE_FAO_MASK 0x00000020L
4607#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x00000005
4608#define GRBM_DEBUG__IGNORE_RDY_MASK 0x00000002L
4609#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000001
4610#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x00000001L
4611#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x00000000
4612#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x00000002L
4613#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x00000001
4614#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000080L
4615#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000007
4616#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x00000200L
4617#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x00000009
4618#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x00000040L
4619#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x00000006
4620#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x00004000L
4621#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0x0000000e
4622#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x00000080L
4623#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x00000007
4624#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x00008000L
4625#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0x0000000f
4626#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x00000100L
4627#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x00000008
4628#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x00010000L
4629#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x00000010
4630#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x00000200L
4631#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x00000009
4632#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x00020000L
4633#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x00000011
4634#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x00000400L
4635#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0x0000000a
4636#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x00040000L
4637#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x00000012
4638#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x00000800L
4639#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0x0000000b
4640#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x00080000L
4641#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x00000013
4642#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x00001000L
4643#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0x0000000c
4644#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x00100000L
4645#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x00000014
4646#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x00002000L
4647#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0x0000000d
4648#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x00200000L
4649#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x00000015
4650#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x00000002L
4651#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x00000001
4652#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x00000008L
4653#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x00000003
4654#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x00000010L
4655#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x00000004
4656#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
4657#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
4658#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
4659#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
4660#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
4661#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e
4662#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000ffL
4663#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x00000000
4664#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
4665#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x0000001f
4666#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00ff0000L
4667#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010
4668#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
4669#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x0000001d
4670#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000ff00L
4671#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x00000008
4672#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
4673#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x00000013
4674#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
4675#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x00000000
4676#define GRBM_NOWHERE__DATA_MASK 0xffffffffL
4677#define GRBM_NOWHERE__DATA__SHIFT 0x00000000
4678#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4679#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4680#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4681#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4682#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
4683#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019
4684#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
4685#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015
4686#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
4687#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b
4688#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
4689#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016
4690#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
4691#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014
4692#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
4693#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a
4694#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
4695#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018
4696#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
4697#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013
4698#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
4699#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017
4700#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
4701#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012
4702#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL
4703#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
4704#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
4705#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a
4706#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
4707#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011
4708#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
4709#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010
4710#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
4711#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e
4712#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
4713#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d
4714#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
4715#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b
4716#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
4717#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c
4718#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
4719#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c
4720#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4721#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4722#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4723#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4724#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
4725#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019
4726#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
4727#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015
4728#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
4729#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b
4730#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
4731#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016
4732#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
4733#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014
4734#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
4735#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a
4736#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
4737#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018
4738#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
4739#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013
4740#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
4741#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017
4742#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
4743#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012
4744#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL
4745#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
4746#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
4747#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a
4748#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
4749#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011
4750#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
4751#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010
4752#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
4753#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e
4754#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
4755#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d
4756#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
4757#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b
4758#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
4759#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c
4760#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
4761#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c
4762#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0x0000000fL
4763#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x00000000
4764#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0x000000f0L
4765#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x00000004
4766#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
4767#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x00000013
4768#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
4769#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x00000014
4770#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
4771#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x00000015
4772#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
4773#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x00000016
4774#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
4775#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x00000017
4776#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
4777#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x00000018
4778#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
4779#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x00000019
4780#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
4781#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x0000001a
4782#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
4783#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x0000001b
4784#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
4785#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x0000001c
4786#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
4787#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x0000001d
4788#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
4789#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x0000001e
4790#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
4791#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x0000001f
4792#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
4793#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x00000012
4794#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x00020000L
4795#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x00000011
4796#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL
4797#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002
4798#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
4799#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f
4800#define GRBM_READ_ERROR__READ_MEID_MASK 0x00c00000L
4801#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x00000016
4802#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
4803#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x00000014
4804#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL
4805#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000
4806#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL
4807#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000
4808#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL
4809#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000
4810#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL
4811#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000
4812#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL
4813#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000
4814#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL
4815#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000
4816#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL
4817#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000
4818#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL
4819#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000
4820#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4821#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4822#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4823#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4824#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
4825#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015
4826#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
4827#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012
4828#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
4829#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b
4830#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
4831#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011
4832#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
4833#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a
4834#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
4835#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014
4836#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL
4837#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000
4838#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
4839#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010
4840#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
4841#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f
4842#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
4843#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d
4844#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
4845#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c
4846#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
4847#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013
4848#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL
4849#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000
4850#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL
4851#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000
4852#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
4853#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015
4854#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
4855#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012
4856#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
4857#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b
4858#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
4859#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011
4860#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
4861#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a
4862#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
4863#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014
4864#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL
4865#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000
4866#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
4867#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010
4868#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
4869#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f
4870#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
4871#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d
4872#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
4873#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c
4874#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
4875#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013
4876#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000fc0L
4877#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000006
4878#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003fL
4879#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000
4880#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
4881#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x00000012
4882#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
4883#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x00000011
4884#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
4885#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x00000013
4886#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
4887#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000
4888#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
4889#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x00000010
4890#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
4891#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x00000002
4892#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
4893#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x0000001d
4894#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
4895#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x0000001c
4896#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
4897#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x0000001e
4898#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
4899#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x00000004
4900#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000fL
4901#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x00000000
4902#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
4903#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x00000005
4904#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
4905#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x00000006
4906#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
4907#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x00000007
4908#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
4909#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x00000008
4910#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
4911#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x00000009
4912#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
4913#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0x0000000a
4914#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
4915#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0x0000000b
4916#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
4917#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0x0000000c
4918#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
4919#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0x0000000d
4920#define GRBM_STATUS2__RLC_BUSY_MASK 0x00000100L
4921#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x00000008
4922#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00000001L
4923#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0x00000000
4924#define GRBM_STATUS2__TC_BUSY_MASK 0x00000200L
4925#define GRBM_STATUS2__TC_BUSY__SHIFT 0x00000009
4926#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
4927#define GRBM_STATUS__BCI_BUSY__SHIFT 0x00000017
4928#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
4929#define GRBM_STATUS__CB_BUSY__SHIFT 0x0000001e
4930#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
4931#define GRBM_STATUS__CB_CLEAN__SHIFT 0x0000000d
4932#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
4933#define GRBM_STATUS__CP_BUSY__SHIFT 0x0000001d
4934#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
4935#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x0000001c
4936#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
4937#define GRBM_STATUS__DB_BUSY__SHIFT 0x0000001a
4938#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
4939#define GRBM_STATUS__DB_CLEAN__SHIFT 0x0000000c
4940#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
4941#define GRBM_STATUS__GDS_BUSY__SHIFT 0x0000000f
4942#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
4943#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x00000009
4944#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
4945#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f
4946#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
4947#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
4948#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x00000012
4949#define GRBM_STATUS__IA_BUSY__SHIFT 0x00000013
4950#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
4951#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x00000007
4952#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000fL
4953#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x00000000
4954#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
4955#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x00000008
4956#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
4957#define GRBM_STATUS__PA_BUSY__SHIFT 0x00000019
4958#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
4959#define GRBM_STATUS__SC_BUSY__SHIFT 0x00000018
4960#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
4961#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x00000016
4962#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
4963#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x0000001f
4964#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
4965#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x00000002
4966#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
4967#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x0000001e
4968#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
4969#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x00000001
4970#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
4971#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x00000018
4972#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
4973#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x0000001d
4974#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
4975#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x0000001b
4976#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
4977#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x0000001a
4978#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
4979#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x00000019
4980#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
4981#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x00000017
4982#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
4983#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x00000016
4984#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
4985#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x0000001f
4986#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
4987#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x00000002
4988#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
4989#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x0000001e
4990#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
4991#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x00000001
4992#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
4993#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x00000018
4994#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
4995#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x0000001d
4996#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
4997#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x0000001b
4998#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
4999#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x0000001a
5000#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
5001#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x00000019
5002#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
5003#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x00000017
5004#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
5005#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x00000016
5006#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
5007#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x0000001f
5008#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
5009#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x00000002
5010#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
5011#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x0000001e
5012#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
5013#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x00000001
5014#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
5015#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x00000018
5016#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
5017#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x0000001d
5018#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
5019#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x0000001b
5020#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
5021#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x0000001a
5022#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
5023#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x00000019
5024#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
5025#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x00000017
5026#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
5027#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x00000016
5028#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
5029#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x0000001f
5030#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
5031#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x00000002
5032#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
5033#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x0000001e
5034#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
5035#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x00000001
5036#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
5037#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x00000018
5038#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
5039#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x0000001d
5040#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
5041#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x0000001b
5042#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
5043#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x0000001a
5044#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
5045#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x00000019
5046#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
5047#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x00000017
5048#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
5049#define GRBM_STATUS__SPI_BUSY__SHIFT 0x00000016
5050#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x00000020L
5051#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x00000005
5052#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
5053#define GRBM_STATUS__SX_BUSY__SHIFT 0x00000014
5054#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
5055#define GRBM_STATUS__TA_BUSY__SHIFT 0x0000000e
5056#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
5057#define GRBM_STATUS__VGT_BUSY__SHIFT 0x00000011
5058#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
5059#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
5060#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x00000010
5061#define GRBM_STATUS__WD_BUSY__SHIFT 0x00000015
5062#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000ffL
5063#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x00000000
5064#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
5065#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x00000004
5066#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
5067#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x00000000
5068#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
5069#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x00000001
5070#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
5071#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x00000002
5072#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
5073#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x00000003
5074#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x0000003fL
5075#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x00000000
5076#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x00000040L
5077#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x00000006
5078#define IA_DEBUG_DATA__DATA_MASK 0xffffffffL
5079#define IA_DEBUG_DATA__DATA__SHIFT 0x00000000
5080#define IA_DEBUG_REG0__core_clk_busy_MASK 0x04000000L
5081#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a
5082#define IA_DEBUG_REG0__dma_busy_MASK 0x00000040L
5083#define IA_DEBUG_REG0__dma_busy__SHIFT 0x00000006
5084#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x00001000L
5085#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0x0000000c
5086#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x00000400L
5087#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0x0000000a
5088#define IA_DEBUG_REG0__dma_req_busy_MASK 0x00000020L
5089#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x00000005
5090#define IA_DEBUG_REG0__grp_busy_MASK 0x00000100L
5091#define IA_DEBUG_REG0__grp_busy__SHIFT 0x00000008
5092#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x00002000L
5093#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0x0000000d
5094#define IA_DEBUG_REG0__grp_dma_read_MASK 0x00000800L
5095#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0x0000000b
5096#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x00000001L
5097#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x00000000
5098#define IA_DEBUG_REG0__ia_busy_MASK 0x00000004L
5099#define IA_DEBUG_REG0__ia_busy__SHIFT 0x00000002
5100#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x00000002L
5101#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x00000001
5102#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x00000008L
5103#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x00000003
5104#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x00000080L
5105#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x00000007
5106#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L
5107#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018
5108#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L
5109#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d
5110#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L
5111#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c
5112#define IA_DEBUG_REG0__SPARE0_MASK 0x00000010L
5113#define IA_DEBUG_REG0__SPARE0__SHIFT 0x00000004
5114#define IA_DEBUG_REG0__SPARE1_MASK 0x00000200L
5115#define IA_DEBUG_REG0__SPARE1__SHIFT 0x00000009
5116#define IA_DEBUG_REG0__SPARE2_MASK 0x00ffc000L
5117#define IA_DEBUG_REG0__SPARE2__SHIFT 0x0000000e
5118#define IA_DEBUG_REG0__SPARE3_MASK 0x00100000L
5119#define IA_DEBUG_REG0__SPARE3__SHIFT 0x00000014
5120#define IA_DEBUG_REG0__SPARE4_MASK 0x08000000L
5121#define IA_DEBUG_REG0__SPARE4__SHIFT 0x0000001b
5122#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000L
5123#define IA_DEBUG_REG0__SPARE5__SHIFT 0x0000001e
5124#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000L
5125#define IA_DEBUG_REG0__SPARE6__SHIFT 0x0000001f
5126#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000L
5127#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x0000001c
5128#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x00000100L
5129#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x00000008
5130#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x00000200L
5131#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x00000009
5132#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x00000060L
5133#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x00000005
5134#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x00004000L
5135#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0x0000000e
5136#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x00008000L
5137#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0x0000000f
5138#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x04000000L
5139#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x0000001a
5140#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x00000001L
5141#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x00000000
5142#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x00000002L
5143#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x00000001
5144#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x00002000L
5145#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0x0000000d
5146#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000L
5147#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x0000001e
5148#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x00000008L
5149#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x00000003
5150#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x00010000L
5151#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x00000010
5152#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x00020000L
5153#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x00000011
5154#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x00000080L
5155#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x00000007
5156#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000L
5157#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x0000001f
5158#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x01000000L
5159#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x00000018
5160#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x02000000L
5161#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x00000019
5162#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x00000800L
5163#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0x0000000b
5164#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x00000010L
5165#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x00000004
5166#define IA_DEBUG_REG1__grp_dma_read_MASK 0x08000000L
5167#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x0000001b
5168#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x00001000L
5169#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0x0000000c
5170#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000L
5171#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x0000001d
5172#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x00000400L
5173#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0x0000000a
5174#define IA_DEBUG_REG1__stage2_dr_MASK 0x00040000L
5175#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x00000012
5176#define IA_DEBUG_REG1__stage2_rtr_MASK 0x00080000L
5177#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x00000013
5178#define IA_DEBUG_REG1__stage3_dr_MASK 0x00100000L
5179#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x00000014
5180#define IA_DEBUG_REG1__stage3_rtr_MASK 0x00200000L
5181#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x00000015
5182#define IA_DEBUG_REG1__stage4_dr_MASK 0x00400000L
5183#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x00000016
5184#define IA_DEBUG_REG1__stage4_rtr_MASK 0x00800000L
5185#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x00000017
5186#define IA_DEBUG_REG1__start_new_packet_MASK 0x00000004L
5187#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x00000002
5188#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000L
5189#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x0000001c
5190#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x00000100L
5191#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x00000008
5192#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x00000200L
5193#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x00000009
5194#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x00000060L
5195#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x00000005
5196#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x00004000L
5197#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0x0000000e
5198#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x00008000L
5199#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0x0000000f
5200#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x04000000L
5201#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x0000001a
5202#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x00000001L
5203#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x00000000
5204#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x00000002L
5205#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x00000001
5206#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x00002000L
5207#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0x0000000d
5208#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000L
5209#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x0000001e
5210#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x00000008L
5211#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x00000003
5212#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x00010000L
5213#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x00000010
5214#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x00020000L
5215#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x00000011
5216#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x00000080L
5217#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x00000007
5218#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000L
5219#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x0000001f
5220#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x01000000L
5221#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x00000018
5222#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x02000000L
5223#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x00000019
5224#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x00000800L
5225#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0x0000000b
5226#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x00000010L
5227#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x00000004
5228#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x08000000L
5229#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x0000001b
5230#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x00001000L
5231#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0x0000000c
5232#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000L
5233#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x0000001d
5234#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x00000400L
5235#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0x0000000a
5236#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x00040000L
5237#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x00000012
5238#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x00080000L
5239#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x00000013
5240#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x00100000L
5241#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x00000014
5242#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x00200000L
5243#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x00000015
5244#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x00400000L
5245#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x00000016
5246#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x00800000L
5247#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x00000017
5248#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x00000004L
5249#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x00000002
5250#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x04000000L
5251#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x0000001a
5252#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x08000000L
5253#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x0000001b
5254#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x00000008L
5255#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x00000003
5256#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x00000004L
5257#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x00000002
5258#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x00000002L
5259#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x00000001
5260#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x00000010L
5261#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x00000004
5262#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x00000001L
5263#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x00000000
5264#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x00000800L
5265#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0x0000000b
5266#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x00000400L
5267#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0x0000000a
5268#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x00000200L
5269#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x00000009
5270#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x00001000L
5271#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0x0000000c
5272#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x00000100L
5273#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x00000008
5274#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x00008000L
5275#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0x0000000f
5276#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x00000020L
5277#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x00000005
5278#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x00002000L
5279#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0x0000000d
5280#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x00040000L
5281#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x00000012
5282#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000L
5283#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x0000001d
5284#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000L
5285#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x0000001c
5286#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x00004000L
5287#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0x0000000e
5288#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x00000040L
5289#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x00000006
5290#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x00100000L
5291#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x00000014
5292#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x00200000L
5293#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x00000015
5294#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x00400000L
5295#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x00000016
5296#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x00800000L
5297#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x00000017
5298#define IA_DEBUG_REG3__pipe0_dr_MASK 0x00010000L
5299#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x00000010
5300#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x00020000L
5301#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x00000011
5302#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x00000080L
5303#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x00000007
5304#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000L
5305#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x0000001f
5306#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000L
5307#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x0000001e
5308#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x00080000L
5309#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x00000013
5310#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x03000000L
5311#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x00000018
5312#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000L
5313#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x0000001f
5314#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x00100000L
5315#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x00000014
5316#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000L
5317#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x0000001d
5318#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x00010000L
5319#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x00000010
5320#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0x0c000000L
5321#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x0000001a
5322#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00e00000L
5323#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000015
5324#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x02000000L
5325#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x00000019
5326#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x01000000L
5327#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x00000018
5328#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x00000040L
5329#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x00000006
5330#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x00000080L
5331#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x00000007
5332#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0x000e0000L
5333#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x00000011
5334#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x00008000L
5335#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0x0000000f
5336#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x00004000L
5337#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0x0000000e
5338#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000L
5339#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x0000001e
5340#define IA_DEBUG_REG4__pipe0_dr_MASK 0x00000001L
5341#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x00000000
5342#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x00000100L
5343#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000008
5344#define IA_DEBUG_REG4__pipe1_dr_MASK 0x00000002L
5345#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x00000001
5346#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x00000200L
5347#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000009
5348#define IA_DEBUG_REG4__pipe2_dr_MASK 0x00000004L
5349#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x00000002
5350#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x00000400L
5351#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0x0000000a
5352#define IA_DEBUG_REG4__pipe3_dr_MASK 0x00000008L
5353#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x00000003
5354#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L
5355#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b
5356#define IA_DEBUG_REG4__pipe4_dr_MASK 0x00000010L
5357#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x00000004
5358#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x00001000L
5359#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0x0000000c
5360#define IA_DEBUG_REG4__pipe5_dr_MASK 0x00000020L
5361#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x00000005
5362#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x00002000L
5363#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0x0000000d
5364#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000L
5365#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x0000001c
5366#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0x0000ffffL
5367#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x00000000
5368#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000L
5369#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x0000001f
5370#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000L
5371#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x0000001e
5372#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000L
5373#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x00000010
5374#define IA_DEBUG_REG6__after_group_partial_MASK 0x00400000L
5375#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x00000016
5376#define IA_DEBUG_REG6__current_shift_q_MASK 0x0000000fL
5377#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x00000000
5378#define IA_DEBUG_REG6__current_stride_pre_MASK 0x000000f0L
5379#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x00000004
5380#define IA_DEBUG_REG6__current_stride_q_MASK 0x00001f00L
5381#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x00000008
5382#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x00008000L
5383#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0x0000000f
5384#define IA_DEBUG_REG6__extract_group_MASK 0x00800000L
5385#define IA_DEBUG_REG6__extract_group__SHIFT 0x00000017
5386#define IA_DEBUG_REG6__first_group_partial_MASK 0x00002000L
5387#define IA_DEBUG_REG6__first_group_partial__SHIFT 0x0000000d
5388#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000L
5389#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x00000018
5390#define IA_DEBUG_REG6__next_group_partial_MASK 0x00200000L
5391#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x00000015
5392#define IA_DEBUG_REG6__next_stride_q_MASK 0x001f0000L
5393#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x00000010
5394#define IA_DEBUG_REG6__second_group_partial_MASK 0x00004000L
5395#define IA_DEBUG_REG6__second_group_partial__SHIFT 0x0000000e
5396#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x02000000L
5397#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x00000019
5398#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x04000000L
5399#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x0000001a
5400#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x08000000L
5401#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x0000001b
5402#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x00800000L
5403#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x00000017
5404#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x00700000L
5405#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x00000014
5406#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0x0000000fL
5407#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x00000000
5408#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x01000000L
5409#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x00000018
5410#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000L
5411#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x0000001f
5412#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000L
5413#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x0000001e
5414#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000L
5415#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x0000001d
5416#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000L
5417#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x0000001c
5418#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0x0000f000L
5419#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0x0000000c
5420#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0x000f0000L
5421#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x00000010
5422#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0x00000f00L
5423#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x00000008
5424#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0x000000f0L
5425#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x00000004
5426#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x0000001fL
5427#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x00000000
5428#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000L
5429#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x0000001c
5430#define IA_DEBUG_REG8__grp_continued_MASK 0x00000800L
5431#define IA_DEBUG_REG8__grp_continued__SHIFT 0x0000000b
5432#define IA_DEBUG_REG8__grp_eopg_MASK 0x04000000L
5433#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x0000001a
5434#define IA_DEBUG_REG8__grp_eop_MASK 0x02000000L
5435#define IA_DEBUG_REG8__grp_eop__SHIFT 0x00000019
5436#define IA_DEBUG_REG8__grp_event_flag_MASK 0x08000000L
5437#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x0000001b
5438#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x01000000L
5439#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x00000018
5440#define IA_DEBUG_REG8__grp_output_path_MASK 0x00e00000L
5441#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x00000015
5442#define IA_DEBUG_REG8__grp_state_sel_MASK 0x00007000L
5443#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0x0000000c
5444#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x001f8000L
5445#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0x0000000f
5446#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x00000100L
5447#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x00000008
5448#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x00000400L
5449#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0x0000000a
5450#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x00000200L
5451#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x00000009
5452#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x00000080L
5453#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x00000007
5454#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x00000020L
5455#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x00000005
5456#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x00000040L
5457#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x00000006
5458#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x00000400L
5459#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0x0000000a
5460#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x00000200L
5461#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x00000009
5462#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x00000002L
5463#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x00000001
5464#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x00040000L
5465#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x00000012
5466#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x00080000L
5467#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x00000013
5468#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x00000008L
5469#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x00000003
5470#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x00000004L
5471#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x00000002
5472#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x00000020L
5473#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x00000005
5474#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x00000080L
5475#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x00000007
5476#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x00000010L
5477#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x00000004
5478#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x00000100L
5479#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x00000008
5480#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x00000040L
5481#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x00000006
5482#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x00020000L
5483#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x00000011
5484#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x00000800L
5485#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0x0000000b
5486#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfffc0000L
5487#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x00000012
5488#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x00001000L
5489#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0x0000000c
5490#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x00000001L
5491#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x00000000
5492#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x00010000L
5493#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x00000010
5494#define IA_DEBUG_REG9__SPARE0_MASK 0x00004000L
5495#define IA_DEBUG_REG9__SPARE0__SHIFT 0x0000000e
5496#define IA_DEBUG_REG9__SPARE1_MASK 0x00008000L
5497#define IA_DEBUG_REG9__SPARE1__SHIFT 0x0000000f
5498#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x00002000L
5499#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0x0000000d
5500#define IA_ENHANCE__MISC_MASK 0xffffffffL
5501#define IA_ENHANCE__MISC__SHIFT 0x00000000
5502#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
5503#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x00000012
5504#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
5505#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x00000010
5506#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000ffffL
5507#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x00000000
5508#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
5509#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x00000013
5510#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
5511#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x00000011
5512#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
5513#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x00000014
5514#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
5515#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
5516#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
5517#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
5518#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
5519#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
5520#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
5521#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
5522#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
5523#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
5524#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
5525#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
5526#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
5527#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
5528#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
5529#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
5530#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
5531#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
5532#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
5533#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
5534#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
5535#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
5536#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
5537#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
5538#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
5539#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
5540#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
5541#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
5542#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
5543#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
5544#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
5545#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
5546#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
5547#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
5548#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
5549#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
5550#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
5551#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
5552#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
5553#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
5554#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
5555#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
5556#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
5557#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
5558#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
5559#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
5560#define IA_VMID_OVERRIDE__ENABLE_MASK 0x00000001L
5561#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x00000000
5562#define IA_VMID_OVERRIDE__VMID_MASK 0x0000001eL
5563#define IA_VMID_OVERRIDE__VMID__SHIFT 0x00000001
5564#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
5565#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012
5566#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
5567#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010
5568#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
5569#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014
5570#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
5571#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013
5572#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
5573#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x00000018
5574#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
5575#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x00000016
5576#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L
5577#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0x0000000e
5578#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
5579#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0x0000000d
5580#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
5581#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x00000011
5582#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
5583#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000
5584#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
5585#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001
5586#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
5587#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x00000002
5588#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
5589#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003
5590#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
5591#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004
5592#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
5593#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005
5594#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
5595#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x00000019
5596#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
5597#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015
5598#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
5599#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x0000001b
5600#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
5601#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x0000001a
5602#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L
5603#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f
5604#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
5605#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x00000003
5606#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
5607#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000
5608#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
5609#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f
5610#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
5611#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e
5612#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
5613#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d
5614#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
5615#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c
5616#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
5617#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001
5618#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
5619#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x00000004
5620#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L
5621#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005
5622#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL
5623#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000
5624#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL
5625#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000
5626#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL
5627#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000
5628#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL
5629#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000
5630#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
5631#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0x0000000e
5632#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
5633#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0x0000000d
5634#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
5635#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0x0000000c
5636#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
5637#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x00000009
5638#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
5639#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x00000008
5640#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
5641#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0x0000000b
5642#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
5643#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0x0000000a
5644#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
5645#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x00000003
5646#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
5647#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x00000014
5648#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
5649#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002
5650#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
5651#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x00000006
5652#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
5653#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x00000007
5654#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
5655#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000
5656#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
5657#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x00000004
5658#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
5659#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001
5660#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
5661#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x00000005
5662#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffffL
5663#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x00000000
5664#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffffL
5665#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x00000000
5666#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffffL
5667#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x00000000
5668#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffffL
5669#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x00000000
5670#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL
5671#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000
5672#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffffL
5673#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x00000000
5674#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffffL
5675#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000
5676#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffffL
5677#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000
5678#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffffL
5679#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000
5680#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL
5681#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x00000000
5682#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffffL
5683#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000
5684#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffffL
5685#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000
5686#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL
5687#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000
5688#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffffL
5689#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x00000000
5690#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffffL
5691#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x00000000
5692#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffffL
5693#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x00000000
5694#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL
5695#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x00000000
5696#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffffL
5697#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000
5698#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffffL
5699#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x00000000
5700#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffffL
5701#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000
5702#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffffL
5703#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x00000000
5704#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffffL
5705#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000
5706#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffffL
5707#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x00000000
5708#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffffL
5709#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000
5710#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffffL
5711#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x00000000
5712#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL
5713#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000
5714#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffffL
5715#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x00000000
5716#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffffL
5717#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x00000000
5718#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffffL
5719#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x00000000
5720#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffffL
5721#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x00000000
5722#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffffL
5723#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x00000000
5724#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffffL
5725#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x00000000
5726#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffffL
5727#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x00000000
5728#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffffL
5729#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x00000000
5730#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffffL
5731#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x00000000
5732#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffffL
5733#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x00000000
5734#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffffL
5735#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x00000000
5736#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffffL
5737#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x00000000
5738#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffffL
5739#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x00000000
5740#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffffL
5741#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x00000000
5742#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffffL
5743#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x00000000
5744#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffffL
5745#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x00000000
5746#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffffL
5747#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x00000000
5748#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL
5749#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000
5750#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffffL
5751#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x00000000
5752#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffffL
5753#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x00000000
5754#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffffL
5755#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x00000000
5756#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffffL
5757#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x00000000
5758#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffffL
5759#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x00000000
5760#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffffL
5761#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x00000000
5762#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffffL
5763#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x00000000
5764#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffffL
5765#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x00000000
5766#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffffL
5767#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x00000000
5768#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffffL
5769#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x00000000
5770#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffffL
5771#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x00000000
5772#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffffL
5773#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x00000000
5774#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffffL
5775#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x00000000
5776#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffffL
5777#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x00000000
5778#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffffL
5779#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x00000000
5780#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL
5781#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000
5782#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffffL
5783#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x00000000
5784#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffffL
5785#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x00000000
5786#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffffL
5787#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x00000000
5788#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffffL
5789#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x00000000
5790#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffffL
5791#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x00000000
5792#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffffL
5793#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x00000000
5794#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffffL
5795#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x00000000
5796#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffffL
5797#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x00000000
5798#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffffL
5799#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x00000000
5800#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffffL
5801#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x00000000
5802#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffffL
5803#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x00000000
5804#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffffL
5805#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x00000000
5806#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffffL
5807#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x00000000
5808#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffffL
5809#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x00000000
5810#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffffL
5811#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x00000000
5812#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL
5813#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000
5814#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffffL
5815#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x00000000
5816#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffffL
5817#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x00000000
5818#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffffL
5819#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x00000000
5820#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffffL
5821#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x00000000
5822#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffffL
5823#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x00000000
5824#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffffL
5825#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x00000000
5826#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffffL
5827#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x00000000
5828#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffffL
5829#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x00000000
5830#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffffL
5831#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x00000000
5832#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffffL
5833#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x00000000
5834#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffffL
5835#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x00000000
5836#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffffL
5837#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x00000000
5838#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffffL
5839#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x00000000
5840#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffffL
5841#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x00000000
5842#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffffL
5843#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x00000000
5844#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL
5845#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000
5846#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffffL
5847#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x00000000
5848#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffffL
5849#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x00000000
5850#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffffL
5851#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x00000000
5852#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffffL
5853#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x00000000
5854#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffffL
5855#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x00000000
5856#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffffL
5857#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x00000000
5858#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffffL
5859#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x00000000
5860#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffffL
5861#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x00000000
5862#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffffL
5863#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x00000000
5864#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffffL
5865#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x00000000
5866#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffffL
5867#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x00000000
5868#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffffL
5869#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x00000000
5870#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffffL
5871#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x00000000
5872#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffffL
5873#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x00000000
5874#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffffL
5875#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x00000000
5876#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL
5877#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000
5878#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffffL
5879#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x00000000
5880#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffffL
5881#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x00000000
5882#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffffL
5883#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x00000000
5884#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffffL
5885#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x00000000
5886#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffffL
5887#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x00000000
5888#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffffL
5889#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x00000000
5890#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffffL
5891#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x00000000
5892#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffffL
5893#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x00000000
5894#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffffL
5895#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x00000000
5896#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffffL
5897#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x00000000
5898#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffffL
5899#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x00000000
5900#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffffL
5901#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x00000000
5902#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffffL
5903#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x00000000
5904#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffffL
5905#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x00000000
5906#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffffL
5907#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x00000000
5908#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL
5909#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000
5910#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
5911#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x00000000
5912#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
5913#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x00000001
5914#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
5915#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x00000002
5916#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
5917#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x00000003
5918#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
5919#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x00000004
5920#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
5921#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x00000005
5922#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
5923#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x00000006
5924#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
5925#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x00000007
5926#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
5927#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x00000008
5928#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
5929#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x00000009
5930#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
5931#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0x0000000a
5932#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
5933#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0x0000000b
5934#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
5935#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0x0000000c
5936#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
5937#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0x0000000d
5938#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
5939#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0x0000000e
5940#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
5941#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0x0000000f
5942#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
5943#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x00000011
5944#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
5945#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x00000019
5946#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
5947#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x00000014
5948#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
5949#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x00000010
5950#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
5951#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x00000012
5952#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
5953#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x00000013
5954#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
5955#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x00000016
5956#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
5957#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x00000017
5958#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
5959#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x00000018
5960#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
5961#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x00000015
5962#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
5963#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b
5964#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
5965#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001
5966#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
5967#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000
5968#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
5969#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003
5970#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
5971#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002
5972#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
5973#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005
5974#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
5975#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004
5976#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
5977#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a
5978#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
5979#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008
5980#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
5981#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009
5982#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
5983#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x00000004
5984#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
5985#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x00000018
5986#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L
5987#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d
5988#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
5989#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x00000014
5990#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
5991#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000
5992#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000ffffL
5993#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x00000000
5994#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000L
5995#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x00000010
5996#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000ffffL
5997#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x00000000
5998#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000L
5999#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x00000010
6000#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000fL
6001#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x00000000
6002#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000f0L
6003#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x00000004
6004#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000f00L
6005#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x00000008
6006#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000f000L
6007#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0x0000000c
6008#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000f0000L
6009#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x00000010
6010#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00f00000L
6011#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x00000014
6012#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0f000000L
6013#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x00000018
6014#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000L
6015#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x0000001c
6016#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000fL
6017#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x00000000
6018#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000f0L
6019#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x00000004
6020#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000f00L
6021#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x00000008
6022#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000f000L
6023#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0x0000000c
6024#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000f0000L
6025#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x00000010
6026#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00f00000L
6027#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x00000014
6028#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0f000000L
6029#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x00000018
6030#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000L
6031#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x0000001c
6032#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000f0000L
6033#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x00000010
6034#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00f00000L
6035#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x00000014
6036#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0f000000L
6037#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x00000018
6038#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000L
6039#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x0000001c
6040#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000fL
6041#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x00000000
6042#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000f0L
6043#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x00000004
6044#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000f00L
6045#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x00000008
6046#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000f000L
6047#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0x0000000c
6048#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000fL
6049#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x00000000
6050#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000f0L
6051#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x00000004
6052#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000f00L
6053#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x00000008
6054#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000f000L
6055#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0x0000000c
6056#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000f0000L
6057#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x00000010
6058#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00f00000L
6059#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x00000014
6060#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0f000000L
6061#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x00000018
6062#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000L
6063#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x0000001c
6064#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000fL
6065#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x00000000
6066#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000f0L
6067#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x00000004
6068#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000f00L
6069#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x00000008
6070#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000f000L
6071#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0x0000000c
6072#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000f0000L
6073#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x00000010
6074#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00f00000L
6075#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x00000014
6076#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0f000000L
6077#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x00000018
6078#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000L
6079#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x0000001c
6080#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000fL
6081#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x00000000
6082#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000f0L
6083#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x00000004
6084#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000f00L
6085#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x00000008
6086#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000f000L
6087#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0x0000000c
6088#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000f0000L
6089#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x00000010
6090#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00f00000L
6091#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x00000014
6092#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0f000000L
6093#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x00000018
6094#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000L
6095#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x0000001c
6096#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000f0000L
6097#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x00000010
6098#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00f00000L
6099#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x00000014
6100#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0f000000L
6101#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x00000018
6102#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000L
6103#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x0000001c
6104#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000fL
6105#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x00000000
6106#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000f0L
6107#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x00000004
6108#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000f00L
6109#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x00000008
6110#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000f000L
6111#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0x0000000c
6112#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000fL
6113#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x00000000
6114#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000f0L
6115#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x00000004
6116#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000f00L
6117#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x00000008
6118#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000f000L
6119#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0x0000000c
6120#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000f0000L
6121#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x00000010
6122#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00f00000L
6123#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x00000014
6124#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0f000000L
6125#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x00000018
6126#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000L
6127#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x0000001c
6128#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000fL
6129#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x00000000
6130#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000f0L
6131#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x00000004
6132#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000f00L
6133#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x00000008
6134#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000f000L
6135#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0x0000000c
6136#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000f0000L
6137#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x00000010
6138#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00f00000L
6139#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x00000014
6140#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0f000000L
6141#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x00000018
6142#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000L
6143#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x0000001c
6144#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000fL
6145#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x00000000
6146#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000f0L
6147#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x00000004
6148#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000f00L
6149#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x00000008
6150#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000f000L
6151#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0x0000000c
6152#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000f0000L
6153#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x00000010
6154#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00f00000L
6155#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x00000014
6156#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0f000000L
6157#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x00000018
6158#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000L
6159#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x0000001c
6160#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000f0000L
6161#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x00000010
6162#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00f00000L
6163#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x00000014
6164#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0f000000L
6165#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x00000018
6166#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000L
6167#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x0000001c
6168#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000fL
6169#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x00000000
6170#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000f0L
6171#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x00000004
6172#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000f00L
6173#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x00000008
6174#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000f000L
6175#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0x0000000c
6176#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000fL
6177#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x00000000
6178#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000f0L
6179#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x00000004
6180#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000f00L
6181#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x00000008
6182#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000f000L
6183#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0x0000000c
6184#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000f0000L
6185#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x00000010
6186#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00f00000L
6187#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x00000014
6188#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0f000000L
6189#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x00000018
6190#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000L
6191#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x0000001c
6192#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000fL
6193#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x00000000
6194#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000f0L
6195#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x00000004
6196#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000f00L
6197#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x00000008
6198#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000f000L
6199#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0x0000000c
6200#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000f0000L
6201#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x00000010
6202#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00f00000L
6203#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x00000014
6204#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0f000000L
6205#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x00000018
6206#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000L
6207#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x0000001c
6208#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000fL
6209#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x00000000
6210#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000f0L
6211#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x00000004
6212#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000f00L
6213#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x00000008
6214#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000f000L
6215#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0x0000000c
6216#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000f0000L
6217#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x00000010
6218#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00f00000L
6219#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x00000014
6220#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0f000000L
6221#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x00000018
6222#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000L
6223#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x0000001c
6224#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000f0000L
6225#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x00000010
6226#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00f00000L
6227#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x00000014
6228#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0f000000L
6229#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x00000018
6230#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000L
6231#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x0000001c
6232#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000fL
6233#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x00000000
6234#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000f0L
6235#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x00000004
6236#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000f00L
6237#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x00000008
6238#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000f000L
6239#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0x0000000c
6240#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000fL
6241#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x00000000
6242#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000f0L
6243#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x00000004
6244#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000f00L
6245#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x00000008
6246#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000f000L
6247#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0x0000000c
6248#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000f0000L
6249#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x00000010
6250#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00f00000L
6251#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x00000014
6252#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0f000000L
6253#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x00000018
6254#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000L
6255#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x0000001c
6256#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000fL
6257#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x00000000
6258#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000f0L
6259#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x00000004
6260#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000f00L
6261#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x00000008
6262#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000f000L
6263#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0x0000000c
6264#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000f0000L
6265#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x00000010
6266#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00f00000L
6267#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x00000014
6268#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0f000000L
6269#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x00000018
6270#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000L
6271#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x0000001c
6272#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000f00L
6273#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x00000008
6274#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000f000L
6275#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0x0000000c
6276#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000f0000L
6277#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x00000010
6278#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00f00000L
6279#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x00000014
6280#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0f000000L
6281#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x00000018
6282#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000L
6283#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x0000001c
6284#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000fL
6285#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x00000000
6286#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000f0L
6287#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x00000004
6288#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007fffL
6289#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x00000000
6290#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000L
6291#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x00000010
6292#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007fffL
6293#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x00000000
6294#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000L
6295#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x00000010
6296#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007fffL
6297#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x00000000
6298#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000L
6299#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x00000010
6300#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007fffL
6301#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x00000000
6302#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000L
6303#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x00000010
6304#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007fffL
6305#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x00000000
6306#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000L
6307#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x00000010
6308#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007fffL
6309#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x00000000
6310#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000L
6311#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x00000010
6312#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007fffL
6313#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x00000000
6314#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000L
6315#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x00000010
6316#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007fffL
6317#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x00000000
6318#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000L
6319#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x00000010
6320#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000ffffL
6321#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x00000000
6322#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000003fL
6323#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000
6324#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL
6325#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000
6326#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x00000003L
6327#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x00000000
6328#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0x0000000cL
6329#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x00000002
6330#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x00000003L
6331#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x00000000
6332#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0x0000000cL
6333#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x00000002
6334#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000L
6335#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x0000001c
6336#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003f000L
6337#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0x0000000c
6338#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00fc0000L
6339#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x00000012
6340#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0f000000L
6341#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x00000018
6342#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000f0L
6343#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x00000004
6344#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000f00L
6345#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x00000008
6346#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000fL
6347#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x00000000
6348#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
6349#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x00000002
6350#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000200L
6351#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x00000009
6352#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00004000L
6353#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0x0000000e
6354#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00200000L
6355#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000015
6356#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00800000L
6357#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x00000017
6358#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00040000L
6359#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x00000012
6360#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00010000L
6361#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x00000010
6362#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00400000L
6363#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000016
6364#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00080000L
6365#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x00000013
6366#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00002000L
6367#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0x0000000d
6368#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0x000000c0L
6369#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x00000006
6370#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
6371#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x00000001
6372#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
6373#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x00000005
6374#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000400L
6375#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x0000000a
6376#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000800L
6377#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x0000000b
6378#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00001000L
6379#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0x0000000c
6380#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L
6381#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f
6382#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L
6383#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e
6384#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
6385#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x00000003
6386#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
6387#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x00000004
6388#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00008000L
6389#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0x0000000f
6390#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x01000000L
6391#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x00000018
6392#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00020000L
6393#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x00000011
6394#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00100000L
6395#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x00000014
6396#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
6397#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x00000000
6398#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000100L
6399#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x00000008
6400#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000000ffL
6401#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x00000000
6402#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007fc0L
6403#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006
6404#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000L
6405#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x00000017
6406#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003fL
6407#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x00000000
6408#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001f8000L
6409#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0x0000000f
6410#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000ffffL
6411#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x00000000
6412#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000L
6413#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x00000010
6414#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007fffL
6415#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x00000000
6416#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000L
6417#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x00000010
6418#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007fffL
6419#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x00000000
6420#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000L
6421#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x00000010
6422#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6423#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6424#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00fc0000L
6425#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x00000012
6426#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000fc0L
6427#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x00000006
6428#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003fL
6429#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x00000000
6430#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003f000L
6431#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0x0000000c
6432#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
6433#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0x0000000c
6434#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
6435#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009
6436#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
6437#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a
6438#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
6439#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0x0000000b
6440#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
6441#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d
6442#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL
6443#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000
6444#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
6445#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c
6446#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L
6447#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010
6448#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L
6449#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008
6450#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL
6451#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000
6452#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
6453#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x00000002
6454#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
6455#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x00000000
6456#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
6457#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x00000003
6458#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
6459#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x00000001
6460#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
6461#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x00000019
6462#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
6463#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x0000001a
6464#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
6465#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x00000013
6466#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00f00000L
6467#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x00000014
6468#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
6469#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0x0000000f
6470#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
6471#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0x0000000e
6472#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
6473#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x00000018
6474#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
6475#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x00000012
6476#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
6477#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x00000011
6478#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
6479#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x0000001b
6480#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
6481#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x0000001c
6482#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
6483#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x00000010
6484#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
6485#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x00000007
6486#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
6487#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x00000009
6488#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
6489#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0x0000000a
6490#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
6491#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x00000008
6492#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
6493#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x00000002
6494#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
6495#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x00000001
6496#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
6497#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x00000003
6498#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
6499#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x00000004
6500#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
6501#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x00000000
6502#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
6503#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0x0000000b
6504#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
6505#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0x0000000c
6506#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
6507#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0x0000000d
6508#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6509#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6510#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6511#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6512#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
6513#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
6514#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
6515#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
6516#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
6517#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
6518#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
6519#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
6520#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL
6521#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
6522#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6523#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6524#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6525#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6526#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL
6527#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
6528#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6529#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6530#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6531#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6532#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL
6533#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
6534#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6535#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6536#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6537#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6538#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL
6539#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
6540#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6541#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6542#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6543#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6544#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL
6545#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000
6546#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6547#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6548#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6549#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6550#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL
6551#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000
6552#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6553#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6554#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6555#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6556#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL
6557#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000
6558#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL
6559#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6560#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6561#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6562#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL
6563#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000
6564#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
6565#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x00000000
6566#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000cL
6567#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x00000002
6568#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L
6569#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x00000004
6570#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
6571#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x00000008
6572#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000c000L
6573#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0x0000000e
6574#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000c00L
6575#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0x0000000a
6576#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
6577#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0x0000000c
6578#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
6579#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x00000000
6580#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000cL
6581#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x00000002
6582#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
6583#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x00000004
6584#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
6585#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x00000006
6586#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
6587#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x00000007
6588#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
6589#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x00000010
6590#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000c0000L
6591#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x00000012
6592#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
6593#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x00000014
6594#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
6595#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x00000018
6596#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0c000000L
6597#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x0000001a
6598#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L
6599#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x0000001c
6600#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000ffffL
6601#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000
6602#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000L
6603#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010
6604#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000ffffL
6605#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000
6606#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000L
6607#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010
6608#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007fffL
6609#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x00000000
6610#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000L
6611#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x00000010
6612#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007fffL
6613#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x00000000
6614#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000L
6615#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x00000010
6616#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6617#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6618#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007fffL
6619#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x00000000
6620#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000L
6621#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x00000010
6622#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007fffL
6623#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x00000000
6624#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000L
6625#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x00000010
6626#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6627#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6628#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007fffL
6629#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x00000000
6630#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000L
6631#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x00000010
6632#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007fffL
6633#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x00000000
6634#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000L
6635#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x00000010
6636#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6637#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6638#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007fffL
6639#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x00000000
6640#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000L
6641#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x00000010
6642#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007fffL
6643#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x00000000
6644#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000L
6645#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x00000010
6646#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6647#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6648#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007fffL
6649#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x00000000
6650#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000L
6651#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x00000010
6652#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007fffL
6653#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x00000000
6654#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000L
6655#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x00000010
6656#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6657#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6658#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007fffL
6659#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x00000000
6660#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000L
6661#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x00000010
6662#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007fffL
6663#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x00000000
6664#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000L
6665#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x00000010
6666#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6667#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6668#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007fffL
6669#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x00000000
6670#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000L
6671#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x00000010
6672#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007fffL
6673#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x00000000
6674#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000L
6675#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x00000010
6676#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6677#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6678#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007fffL
6679#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x00000000
6680#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000L
6681#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x00000010
6682#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007fffL
6683#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x00000000
6684#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000L
6685#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x00000010
6686#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6687#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6688#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007fffL
6689#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x00000000
6690#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000L
6691#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x00000010
6692#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007fffL
6693#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x00000000
6694#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000L
6695#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x00000010
6696#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6697#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6698#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007fffL
6699#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x00000000
6700#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000L
6701#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x00000010
6702#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007fffL
6703#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x00000000
6704#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000L
6705#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x00000010
6706#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6707#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6708#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007fffL
6709#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x00000000
6710#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000L
6711#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x00000010
6712#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007fffL
6713#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x00000000
6714#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000L
6715#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x00000010
6716#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6717#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6718#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007fffL
6719#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x00000000
6720#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000L
6721#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x00000010
6722#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007fffL
6723#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x00000000
6724#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000L
6725#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x00000010
6726#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6727#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6728#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007fffL
6729#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x00000000
6730#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000L
6731#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x00000010
6732#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007fffL
6733#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x00000000
6734#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000L
6735#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x00000010
6736#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6737#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6738#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007fffL
6739#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x00000000
6740#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000L
6741#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x00000010
6742#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007fffL
6743#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x00000000
6744#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000L
6745#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x00000010
6746#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6747#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6748#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007fffL
6749#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x00000000
6750#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000L
6751#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x00000010
6752#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007fffL
6753#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x00000000
6754#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000L
6755#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x00000010
6756#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6757#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6758#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007fffL
6759#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x00000000
6760#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000L
6761#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x00000010
6762#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007fffL
6763#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x00000000
6764#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000L
6765#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x00000010
6766#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6767#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6768#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffffL
6769#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x00000000
6770#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffffL
6771#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x00000000
6772#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffffL
6773#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x00000000
6774#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffffL
6775#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x00000000
6776#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffffL
6777#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x00000000
6778#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffffL
6779#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x00000000
6780#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffffL
6781#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x00000000
6782#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffffL
6783#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x00000000
6784#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffffL
6785#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x00000000
6786#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffffL
6787#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x00000000
6788#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffffL
6789#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x00000000
6790#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffffL
6791#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x00000000
6792#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffffL
6793#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x00000000
6794#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffffL
6795#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x00000000
6796#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffffL
6797#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x00000000
6798#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffffL
6799#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x00000000
6800#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffffL
6801#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x00000000
6802#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffffL
6803#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x00000000
6804#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffffL
6805#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x00000000
6806#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffffL
6807#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x00000000
6808#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffffL
6809#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x00000000
6810#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffffL
6811#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x00000000
6812#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffffL
6813#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x00000000
6814#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffffL
6815#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x00000000
6816#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffffL
6817#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x00000000
6818#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffffL
6819#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x00000000
6820#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffffL
6821#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x00000000
6822#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffffL
6823#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x00000000
6824#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffffL
6825#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x00000000
6826#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffffL
6827#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x00000000
6828#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffffL
6829#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x00000000
6830#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffffL
6831#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x00000000
6832#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000ffffL
6833#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000
6834#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000L
6835#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010
6836#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007fffL
6837#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000
6838#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000L
6839#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010
6840#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007fffL
6841#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000
6842#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000L
6843#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010
6844#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
6845#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f
6846#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
6847#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f
6848#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL
6849#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000
6850#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL
6851#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000
6852#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001ffL
6853#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x00000000
6854#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01ff0000L
6855#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x00000010
6856#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL
6857#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000
6858#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
6859#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x00000004
6860#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
6861#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x00000002
6862#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
6863#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x00000003
6864#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
6865#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x00000000
6866#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffffL
6867#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x00000000
6868#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00ffffffL
6869#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x00000000
6870#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL
6871#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6872#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6873#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6874#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
6875#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
6876#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
6877#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
6878#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
6879#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
6880#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
6881#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
6882#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
6883#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
6884#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL
6885#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6886#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6887#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6888#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
6889#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
6890#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
6891#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
6892#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
6893#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
6894#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
6895#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
6896#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
6897#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
6898#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL
6899#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6900#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6901#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6902#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
6903#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
6904#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
6905#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
6906#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL
6907#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
6908#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
6909#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
6910#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
6911#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
6912#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
6913#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
6914#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L
6915#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010
6916#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL
6917#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000
6918#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL
6919#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000
6920#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L
6921#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010
6922#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL
6923#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000
6924#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL
6925#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000
6926#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffffL
6927#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x00000000
6928#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
6929#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x00000008
6930#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000ffL
6931#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x00000000
6932#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL
6933#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000
6934#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL
6935#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000
6936#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
6937#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x00000005
6938#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
6939#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000001
6940#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
6941#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x00000006
6942#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
6943#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000002
6944#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000ff00L
6945#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x00000008
6946#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
6947#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x00000007
6948#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
6949#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000003
6950#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
6951#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x00000004
6952#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
6953#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000000
6954#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
6955#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x0000001e
6956#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
6957#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x0000001f
6958#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
6959#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001
6960#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
6961#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000
6962#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
6963#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002
6964#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
6965#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015
6966#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
6967#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014
6968#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
6969#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008
6970#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L
6971#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005
6972#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
6973#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003
6974#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
6975#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c
6976#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
6977#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b
6978#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
6979#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d
6980#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
6981#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013
6982#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
6983#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010
6984#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
6985#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000
6986#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
6987#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003
6988#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
6989#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001
6990#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
6991#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
6992#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL
6993#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000
6994#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
6995#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
6996#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
6997#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
6998#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
6999#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7000#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL
7001#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000
7002#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7003#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7004#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7005#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7006#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffffL
7007#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x00000000
7008#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffffL
7009#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x00000000
7010#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffffL
7011#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x00000000
7012#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffffL
7013#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x00000000
7014#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffffL
7015#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x00000000
7016#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffffL
7017#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x00000000
7018#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffffL
7019#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x00000000
7020#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L
7021#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x00000000
7022#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffffL
7023#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x00000000
7024#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7025#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7026#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL
7027#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000
7028#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7029#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7030#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7031#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7032#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffffL
7033#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x00000000
7034#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffffL
7035#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x00000000
7036#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffffL
7037#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x00000000
7038#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7039#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7040#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7041#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7042#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffffL
7043#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x00000000
7044#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
7045#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x00000001
7046#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
7047#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x00000000
7048#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
7049#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x00000002
7050#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007fff8L
7051#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x00000003
7052#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L
7053#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x00000013
7054#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
7055#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x00000000
7056#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffeL
7057#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x00000001
7058#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
7059#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x0000001b
7060#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
7061#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000
7062#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x0000ff00L
7063#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008
7064#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
7065#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x0000001c
7066#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
7067#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001
7068#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL
7069#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002
7070#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
7071#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x0000001d
7072#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000L
7073#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x0000001f
7074#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000fL
7075#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x00000000
7076#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L
7077#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004
7078#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0fff0000L
7079#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x00000010
7080#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000L
7081#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x0000001c
7082#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000f00L
7083#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x00000008
7084#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000f000L
7085#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0x0000000c
7086#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffffL
7087#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x00000000
7088#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
7089#define RLC_CNTL__FORCE_RETRY__SHIFT 0x00000001
7090#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
7091#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x00000002
7092#define RLC_CNTL__RESERVED_MASK 0xffffff00L
7093#define RLC_CNTL__RESERVED__SHIFT 0x00000008
7094#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
7095#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x00000000
7096#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
7097#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x00000003
7098#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x00000010L
7099#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x00000004
7100#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffffL
7101#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x00000000
7102#define RLC_DEBUG__DATA_MASK 0xffffffffL
7103#define RLC_DEBUG__DATA__SHIFT 0x00000000
7104#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffff8000L
7105#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x0000000f
7106#define RLC_DEBUG_SELECT__SELECT_MASK 0x000000ffL
7107#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x00000000
7108#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x00000010L
7109#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x00000004
7110#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x00000001L
7111#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x00000000
7112#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0x0000000eL
7113#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x00000001
7114#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0L
7115#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x00000005
7116#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffffL
7117#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x00000000
7118#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL
7119#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000
7120#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001ffL
7121#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x00000000
7122#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00L
7123#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x00000009
7124#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffffL
7125#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x00000000
7126#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0L
7127#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x00000006
7128#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL
7129#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000
7130#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffffL
7131#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x00000000
7132#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffffL
7133#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x00000000
7134#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffffL
7135#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x00000000
7136#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000ff0L
7137#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x00000004
7138#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
7139#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x00000001
7140#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
7141#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x00000003
7142#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
7143#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x00000002
7144#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
7145#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x00000000
7146#define RLC_LB_CNTL__RESERVED_MASK 0xfffffff0L
7147#define RLC_LB_CNTL__RESERVED__SHIFT 0x00000004
7148#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffffL
7149#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x00000000
7150#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffffL
7151#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x00000000
7152#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffffL
7153#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x00000000
7154#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000feL
7155#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x00000001
7156#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000L
7157#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x00000010
7158#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000ff00L
7159#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x00000008
7160#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
7161#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x00000000
7162#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffffL
7163#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x00000000
7164#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000ffL
7165#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x00000000
7166#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00L
7167#define RLC_MAX_PG_CU__SPARE__SHIFT 0x00000008
7168#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000L
7169#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x0000001c
7170#define RLC_MC_CNTL__RDNFO_URG_MASK 0x00f00000L
7171#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x00000014
7172#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x08000000L
7173#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x0000001b
7174#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x03000000L
7175#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x00000018
7176#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x04000000L
7177#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x0000001a
7178#define RLC_MC_CNTL__RESERVED_B_MASK 0x000fe000L
7179#define RLC_MC_CNTL__RESERVED_B__SHIFT 0x0000000d
7180#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000L
7181#define RLC_MC_CNTL__RESERVED__SHIFT 0x0000001d
7182#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x00000010L
7183#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x00000004
7184#define RLC_MC_CNTL__WRNFO_URG_MASK 0x000001e0L
7185#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x00000005
7186#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x00001e00L
7187#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x00000009
7188#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x00000008L
7189#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x00000003
7190#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x00000003L
7191#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x00000000
7192#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x00000004L
7193#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x00000002
7194#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L
7195#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018
7196#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL
7197#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002
7198#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
7199#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x00000001
7200#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
7201#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x00000000
7202#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00ff0000L
7203#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x00000010
7204#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000ff00L
7205#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x00000008
7206#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
7207#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
7208#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
7209#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
7210#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
7211#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
7212#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
7213#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
7214#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
7215#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
7216#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
7217#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
7218#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
7219#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
7220#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
7221#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
7222#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffffL
7223#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x00000000
7224#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
7225#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x00000010
7226#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
7227#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x00000002
7228#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
7229#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x00000000
7230#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
7231#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x00000001
7232#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000L
7233#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x00000018
7234#define RLC_PG_CNTL__RESERVED1_MASK 0x00f80000L
7235#define RLC_PG_CNTL__RESERVED1__SHIFT 0x00000013
7236#define RLC_PG_CNTL__RESERVED_MASK 0xfffffff0L
7237#define RLC_PG_CNTL__RESERVED__SHIFT 0x00000004
7238#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
7239#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x00000012
7240#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
7241#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x00000011
7242#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
7243#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x00000003
7244#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffffL
7245#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x00000000
7246#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffffL
7247#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x00000000
7248#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffffL
7249#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x00000000
7250#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffffL
7251#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x00000000
7252#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000fL
7253#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x00000000
7254#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x0000c000L
7255#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x0000000e
7256#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x00003800L
7257#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0x0000000b
7258#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001c0L
7259#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x00000006
7260#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000200L
7261#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x00000009
7262#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00000400L
7263#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0x0000000a
7264#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
7265#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x00000004
7266#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffffc000L
7267#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x0000000e
7268#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000ffL
7269#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x00000000
7270#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x00100000L
7271#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x00000014
7272#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x00200000L
7273#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x00000015
7274#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x00020000L
7275#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x00000011
7276#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x00010000L
7277#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x00000010
7278#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x00080000L
7279#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x00000013
7280#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x00040000L
7281#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x00000012
7282#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x00400000L
7283#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x00000016
7284#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x00800000L
7285#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x00000017
7286#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
7287#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0x0000000a
7288#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
7289#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0x0000000b
7290#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
7291#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x00000008
7292#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
7293#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x00000009
7294#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
7295#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0x0000000d
7296#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000L
7297#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x0000001c
7298#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0x0000c000L
7299#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0x0000000e
7300#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0x0f000000L
7301#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x00000018
7302#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
7303#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0x0000000c
7304#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffffL
7305#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x00000000
7306#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffeL
7307#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x00000001
7308#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
7309#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x00000000
7310#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffeL
7311#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x00000001
7312#define RLC_SMU_PG_CTRL__START_PG_MASK 0x00000001L
7313#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x00000000
7314#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffeL
7315#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x00000001
7316#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x00000001L
7317#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x00000000
7318#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffeL
7319#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x00000001
7320#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x00000001L
7321#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x00000000
7322#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL
7323#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000
7324#define RLC_STAT__RESERVED_MASK 0xfffffff0L
7325#define RLC_STAT__RESERVED__SHIFT 0x00000004
7326#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
7327#define RLC_STAT__RLC_BUSY__SHIFT 0x00000000
7328#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L
7329#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x00000001
7330#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L
7331#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x00000002
7332#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000ffL
7333#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x00000000
7334#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000ff00L
7335#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x00000008
7336#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00ff0000L
7337#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x00000010
7338#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000L
7339#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x00000018
7340#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffffL
7341#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x00000000
7342#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffffL
7343#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x00000000
7344#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL
7345#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000
7346#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL
7347#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000
7348#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL
7349#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000
7350#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL
7351#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000
7352#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL
7353#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000
7354#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL
7355#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000
7356#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL
7357#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000
7358#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL
7359#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000
7360#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
7361#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x00000010
7362#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000ffL
7363#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x00000000
7364#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000L
7365#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x0000001f
7366#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000L
7367#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x0000001c
7368#define SETUP_DEBUG_REG0__event_id_gated_MASK 0x0fc00000L
7369#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x00000016
7370#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00200000L
7371#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000015
7372#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00008000L
7373#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000f
7374#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00004000L
7375#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000e
7376#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00080000L
7377#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x00000013
7378#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000L
7379#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x0000001d
7380#define SETUP_DEBUG_REG0__pmode_state_MASK 0x00003f00L
7381#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000008
7382#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x00000003L
7383#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x00000000
7384#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x00030000L
7385#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x00000010
7386#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00040000L
7387#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x00000012
7388#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00100000L
7389#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000014
7390#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000003cL
7391#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000002
7392#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000L
7393#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x0000001e
7394#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000L
7395#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x00000010
7396#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0x0000ffffL
7397#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x00000000
7398#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000L
7399#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x00000010
7400#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0x0000ffffL
7401#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x00000000
7402#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000L
7403#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x00000010
7404#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0x0000ffffL
7405#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x00000000
7406#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x00003fffL
7407#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000
7408#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00008000L
7409#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000f
7410#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00080000L
7411#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000013
7412#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x00700000L
7413#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000014
7414#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x03000000L
7415#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000018
7416#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000L
7417#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001f
7418#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000L
7419#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001d
7420#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00004000L
7421#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000e
7422#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x00070000L
7423#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x00000010
7424#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000L
7425#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x0000001a
7426#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00800000L
7427#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000017
7428#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x0fffc000L
7429#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000e
7430#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x00003fffL
7431#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000
7432#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000L
7433#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x0000001f
7434#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000L
7435#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x0000001c
7436#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000L
7437#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x0000001e
7438#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000ffffL
7439#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x00000000
7440#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000L
7441#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x00000010
7442#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000ffffL
7443#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x00000000
7444#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000L
7445#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x00000010
7446#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
7447#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x00000000
7448#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
7449#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x00000003
7450#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001c0L
7451#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x00000006
7452#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000e00L
7453#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x00000009
7454#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
7455#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0x0000000c
7456#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000c000L
7457#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0x0000000e
7458#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
7459#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x00000010
7460#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000c0000L
7461#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x00000012
7462#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
7463#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x00000018
7464#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
7465#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x00000008
7466#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
7467#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0x0000000c
7468#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
7469#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x00000000
7470#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
7471#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x00000004
7472#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
7473#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x00000010
7474#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
7475#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x00000014
7476#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
7477#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x00000008
7478#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
7479#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x00000004
7480#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003c00L
7481#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0x0000000a
7482#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
7483#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x00000009
7484#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
7485#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x00000006
7486#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000L
7487#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x00000010
7488#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
7489#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x00000007
7490#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000fL
7491#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x00000000
7492#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
7493#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x00000019
7494#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
7495#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x00000018
7496#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00e00000L
7497#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x00000015
7498#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001fffffL
7499#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x00000000
7500#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
7501#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x0000001a
7502#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
7503#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x0000001b
7504#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000080L
7505#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x00000007
7506#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000100L
7507#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x00000008
7508#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000200L
7509#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x00000009
7510#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L
7511#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x0000000b
7512#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L
7513#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0x0000000c
7514#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L
7515#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0x0000000d
7516#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L
7517#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0x0000000e
7518#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L
7519#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0x0000000f
7520#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L
7521#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x00000007
7522#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L
7523#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x00000002
7524#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00008000L
7525#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x0000000f
7526#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00010000L
7527#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x00000010
7528#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L
7529#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x00000003
7530#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L
7531#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x00000001
7532#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00000400L
7533#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x0000000a
7534#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00000800L
7535#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x0000000b
7536#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L
7537#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x00000000
7538#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L
7539#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x00000014
7540#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L
7541#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x00000005
7542#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L
7543#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x00000006
7544#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00001000L
7545#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x0000000c
7546#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00002000L
7547#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x0000000d
7548#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00020000L
7549#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x00000011
7550#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L
7551#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x00000004
7552#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x00000001L
7553#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x00000000
7554#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003e0L
7555#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x00000005
7556#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0e000000L
7557#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x00000019
7558#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L
7559#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x0000001f
7560#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L
7561#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x00000010
7562#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000fc00L
7563#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0x0000000a
7564#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000001eL
7565#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x00000001
7566#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L
7567#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x00000011
7568#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L
7569#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x00000012
7570#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x00080000L
7571#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x00000013
7572#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L
7573#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x00000014
7574#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x00200000L
7575#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x00000015
7576#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x00400000L
7577#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x00000016
7578#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x00800000L
7579#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x00000017
7580#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x01000000L
7581#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x00000018
7582#define SPI_DEBUG_READ__DATA_MASK 0x00ffffffL
7583#define SPI_DEBUG_READ__DATA__SHIFT 0x00000000
7584#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000ff00L
7585#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x00000008
7586#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000ffL
7587#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x00000000
7588#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000L
7589#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x00000010
7590#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
7591#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000
7592#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
7593#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x00000001
7594#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
7595#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0x0000000b
7596#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001cL
7597#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x00000002
7598#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000e0L
7599#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x00000005
7600#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
7601#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x00000008
7602#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
7603#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0x0000000e
7604#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
7605#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x00000000
7606#define SPI_LB_CU_MASK__CU_MASK_MASK 0x0000ffffL
7607#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x00000000
7608#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffffL
7609#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x00000000
7610#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
7611#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
7612#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
7613#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
7614#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
7615#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
7616#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
7617#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
7618#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
7619#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
7620#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
7621#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
7622#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
7623#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
7624#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
7625#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
7626#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
7627#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
7628#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
7629#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
7630#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
7631#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
7632#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
7633#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
7634#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
7635#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
7636#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
7637#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
7638#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
7639#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
7640#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
7641#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
7642#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003ffL
7643#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x00000000
7644#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000ffc00L
7645#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0x0000000a
7646#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
7647#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
7648#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L
7649#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a
7650#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
7651#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
7652#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
7653#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
7654#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
7655#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
7656#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003ffL
7657#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x00000000
7658#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000ffc00L
7659#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0x0000000a
7660#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
7661#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
7662#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L
7663#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a
7664#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
7665#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
7666#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L
7667#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x00000004
7668#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000fL
7669#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x00000000
7670#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L
7671#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0x0000000c
7672#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000f00L
7673#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x00000008
7674#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00f00000L
7675#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x00000014
7676#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000f0000L
7677#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x00000010
7678#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000L
7679#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x0000001c
7680#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L
7681#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x00000018
7682#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0x0000ffffL
7683#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x00000000
7684#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
7685#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0x0000000e
7686#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL
7687#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000
7688#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
7689#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x00000006
7690#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
7691#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0x0000000d
7692#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
7693#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0x0000000c
7694#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
7695#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x00000005
7696#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
7697#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x00000006
7698#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
7699#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x00000004
7700#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
7701#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007
7702#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
7703#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x00000001
7704#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
7705#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x00000002
7706#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
7707#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003
7708#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
7709#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x00000000
7710#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
7711#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0x0000000f
7712#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
7713#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0x0000000b
7714#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
7715#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x00000008
7716#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
7717#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x00000009
7718#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
7719#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0x0000000a
7720#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
7721#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e
7722#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001e000L
7723#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0x0000000d
7724#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
7725#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x00000008
7726#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
7727#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x00000012
7728#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
7729#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0x0000000a
7730#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003fL
7731#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x00000000
7732#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
7733#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x00000011
7734#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001e000L
7735#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0x0000000d
7736#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
7737#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x00000008
7738#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
7739#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x00000012
7740#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
7741#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0x0000000a
7742#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003fL
7743#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x00000000
7744#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
7745#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x00000011
7746#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001e000L
7747#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0x0000000d
7748#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
7749#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x00000008
7750#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
7751#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x00000012
7752#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
7753#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0x0000000a
7754#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003fL
7755#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x00000000
7756#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
7757#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x00000011
7758#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001e000L
7759#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0x0000000d
7760#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
7761#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x00000008
7762#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
7763#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x00000012
7764#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
7765#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0x0000000a
7766#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003fL
7767#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x00000000
7768#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
7769#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x00000011
7770#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001e000L
7771#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0x0000000d
7772#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
7773#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x00000008
7774#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
7775#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x00000012
7776#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
7777#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0x0000000a
7778#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003fL
7779#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x00000000
7780#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
7781#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x00000011
7782#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001e000L
7783#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0x0000000d
7784#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
7785#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x00000008
7786#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
7787#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x00000012
7788#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
7789#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0x0000000a
7790#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003fL
7791#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x00000000
7792#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
7793#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x00000011
7794#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001e000L
7795#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0x0000000d
7796#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
7797#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x00000008
7798#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
7799#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x00000012
7800#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
7801#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0x0000000a
7802#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003fL
7803#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x00000000
7804#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
7805#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x00000011
7806#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001e000L
7807#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0x0000000d
7808#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
7809#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x00000008
7810#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
7811#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x00000012
7812#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
7813#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0x0000000a
7814#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003fL
7815#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x00000000
7816#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
7817#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x00000011
7818#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001e000L
7819#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0x0000000d
7820#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
7821#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x00000008
7822#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
7823#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x00000012
7824#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
7825#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0x0000000a
7826#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003fL
7827#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x00000000
7828#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
7829#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x00000011
7830#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001e000L
7831#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0x0000000d
7832#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
7833#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x00000008
7834#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
7835#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x00000012
7836#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
7837#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0x0000000a
7838#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003fL
7839#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x00000000
7840#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
7841#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x00000011
7842#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001e000L
7843#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0x0000000d
7844#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
7845#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x00000008
7846#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
7847#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x00000012
7848#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
7849#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0x0000000a
7850#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003fL
7851#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x00000000
7852#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
7853#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x00000011
7854#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L
7855#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0x0000000d
7856#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
7857#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x00000008
7858#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
7859#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x00000012
7860#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
7861#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0x0000000a
7862#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003fL
7863#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x00000000
7864#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
7865#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x00000011
7866#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
7867#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x00000008
7868#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
7869#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x00000012
7870#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
7871#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0x0000000a
7872#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003fL
7873#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x00000000
7874#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
7875#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x00000008
7876#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
7877#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x00000012
7878#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
7879#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0x0000000a
7880#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003fL
7881#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x00000000
7882#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
7883#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x00000008
7884#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
7885#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x00000012
7886#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
7887#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0x0000000a
7888#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003fL
7889#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x00000000
7890#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
7891#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x00000008
7892#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
7893#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x00000012
7894#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
7895#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0x0000000a
7896#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003fL
7897#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x00000000
7898#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
7899#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x00000008
7900#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
7901#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x00000012
7902#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
7903#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0x0000000a
7904#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003fL
7905#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x00000000
7906#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
7907#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x00000008
7908#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
7909#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x00000012
7910#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
7911#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0x0000000a
7912#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003fL
7913#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x00000000
7914#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
7915#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x00000008
7916#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
7917#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x00000012
7918#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
7919#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0x0000000a
7920#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003fL
7921#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x00000000
7922#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
7923#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x00000008
7924#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
7925#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x00000012
7926#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
7927#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0x0000000a
7928#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003fL
7929#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x00000000
7930#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
7931#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x00000008
7932#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
7933#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x00000012
7934#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
7935#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0x0000000a
7936#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003fL
7937#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x00000000
7938#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
7939#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x00000008
7940#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
7941#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x00000012
7942#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
7943#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0x0000000a
7944#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003fL
7945#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x00000000
7946#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001e000L
7947#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0x0000000d
7948#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
7949#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x00000008
7950#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
7951#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x00000012
7952#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
7953#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0x0000000a
7954#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003fL
7955#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x00000000
7956#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
7957#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x00000011
7958#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
7959#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x00000008
7960#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
7961#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x00000012
7962#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
7963#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0x0000000a
7964#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003fL
7965#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x00000000
7966#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
7967#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x00000008
7968#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
7969#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x00000012
7970#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
7971#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0x0000000a
7972#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003fL
7973#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x00000000
7974#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001e000L
7975#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0x0000000d
7976#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
7977#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x00000008
7978#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
7979#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x00000012
7980#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
7981#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0x0000000a
7982#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003fL
7983#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x00000000
7984#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
7985#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x00000011
7986#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001e000L
7987#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0x0000000d
7988#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
7989#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x00000008
7990#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
7991#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x00000012
7992#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
7993#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0x0000000a
7994#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003fL
7995#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x00000000
7996#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
7997#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x00000011
7998#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001e000L
7999#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0x0000000d
8000#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
8001#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x00000008
8002#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
8003#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x00000012
8004#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
8005#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0x0000000a
8006#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003fL
8007#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x00000000
8008#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
8009#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x00000011
8010#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001e000L
8011#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0x0000000d
8012#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
8013#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x00000008
8014#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
8015#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x00000012
8016#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
8017#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0x0000000a
8018#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003fL
8019#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x00000000
8020#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
8021#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x00000011
8022#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001e000L
8023#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0x0000000d
8024#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
8025#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x00000008
8026#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
8027#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x00000012
8028#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
8029#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0x0000000a
8030#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003fL
8031#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x00000000
8032#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
8033#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x00000011
8034#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001e000L
8035#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0x0000000d
8036#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
8037#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x00000008
8038#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
8039#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x00000012
8040#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
8041#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0x0000000a
8042#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003fL
8043#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x00000000
8044#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
8045#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x00000011
8046#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001e000L
8047#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0x0000000d
8048#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
8049#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x00000008
8050#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
8051#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x00000012
8052#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
8053#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0x0000000a
8054#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003fL
8055#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x00000000
8056#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
8057#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x00000011
8058#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
8059#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0x0000000d
8060#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
8061#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0x0000000c
8062#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
8063#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x00000005
8064#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
8065#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x00000006
8066#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
8067#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x00000004
8068#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
8069#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007
8070#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
8071#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x00000001
8072#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
8073#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x00000002
8074#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
8075#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003
8076#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
8077#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x00000000
8078#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
8079#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0x0000000f
8080#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
8081#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0x0000000b
8082#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
8083#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x00000008
8084#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
8085#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x00000009
8086#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
8087#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0x0000000a
8088#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
8089#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e
8090#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL
8091#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000
8092#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000fL
8093#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x00000000
8094#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000f0L
8095#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x00000004
8096#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000f00L
8097#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x00000008
8098#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000f000L
8099#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0x0000000c
8100#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000f0000L
8101#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x00000010
8102#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00f00000L
8103#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x00000014
8104#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0f000000L
8105#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x00000018
8106#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000L
8107#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x0000001c
8108#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000ffL
8109#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x00000000
8110#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0x000000ffL
8111#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x00000000
8112#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0x000000ffL
8113#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x00000000
8114#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000ffL
8115#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x00000000
8116#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000ffL
8117#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x00000000
8118#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0x000000ffL
8119#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x00000000
8120#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffffL
8121#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x00000000
8122#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffffL
8123#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x00000000
8124#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffffL
8125#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x00000000
8126#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffffL
8127#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x00000000
8128#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffffL
8129#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x00000000
8130#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffffL
8131#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x00000000
8132#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000L
8133#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x0000001b
8134#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000L
8135#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x0000001e
8136#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L
8137#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x0000001a
8138#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x00400000L
8139#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x00000016
8140#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L
8141#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x00000015
8142#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000ff000L
8143#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0x0000000c
8144#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L
8145#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x00000017
8146#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000c00L
8147#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0x0000000a
8148#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L
8149#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x00000014
8150#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003c0L
8151#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x00000006
8152#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L
8153#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x00000018
8154#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003fL
8155#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x00000000
8156#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0x0e000000L
8157#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x00000019
8158#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L
8159#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x0000001c
8160#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
8161#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x00000018
8162#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L
8163#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x00000016
8164#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
8165#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x00000015
8166#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000ff000L
8167#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0x0000000c
8168#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
8169#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x00000017
8170#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000c00L
8171#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0x0000000a
8172#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
8173#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x00000014
8174#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003c0L
8175#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x00000006
8176#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003fL
8177#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x00000000
8178#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x07000000L
8179#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x00000018
8180#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L
8181#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x0000001b
8182#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L
8183#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x00000016
8184#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
8185#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x00000015
8186#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000ff000L
8187#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0x0000000c
8188#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
8189#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x00000017
8190#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000c00L
8191#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0x0000000a
8192#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
8193#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x00000014
8194#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003c0L
8195#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x00000006
8196#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003fL
8197#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x00000000
8198#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000L
8199#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x0000001a
8200#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000L
8201#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x0000001d
8202#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x00400000L
8203#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x00000016
8204#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L
8205#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x00000015
8206#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000ff000L
8207#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0x0000000c
8208#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L
8209#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x00000017
8210#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000c00L
8211#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0x0000000a
8212#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L
8213#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x00000014
8214#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003c0L
8215#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x00000006
8216#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L
8217#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x00000018
8218#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003fL
8219#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x00000000
8220#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0x0e000000L
8221#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x00000019
8222#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L
8223#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x0000001c
8224#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
8225#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x00000018
8226#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L
8227#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x00000016
8228#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
8229#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x00000015
8230#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000ff000L
8231#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0x0000000c
8232#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
8233#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x00000017
8234#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000c00L
8235#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0x0000000a
8236#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
8237#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x00000014
8238#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003c0L
8239#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x00000006
8240#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003fL
8241#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x00000000
8242#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000L
8243#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x0000001b
8244#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L
8245#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x0000001e
8246#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
8247#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x0000001a
8248#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L
8249#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x00000016
8250#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
8251#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x00000015
8252#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000ff000L
8253#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0x0000000c
8254#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
8255#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x00000017
8256#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000c00L
8257#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0x0000000a
8258#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
8259#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x00000014
8260#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003c0L
8261#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x00000006
8262#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
8263#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x00000018
8264#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003fL
8265#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x00000000
8266#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x00007f00L
8267#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x00000008
8268#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x0001ff00L
8269#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x00000008
8270#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000L
8271#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x00000014
8272#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x00000080L
8273#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x00000007
8274#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x00000001L
8275#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x00000000
8276#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x00000040L
8277#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x00000006
8278#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x0000003eL
8279#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x00000001
8280#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000L
8281#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x00000014
8282#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L
8283#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x00000007
8284#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L
8285#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x00000000
8286#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L
8287#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x00000006
8288#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003eL
8289#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x00000001
8290#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x0001ff00L
8291#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x00000008
8292#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000L
8293#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x00000014
8294#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x00000080L
8295#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x00000007
8296#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x00000001L
8297#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x00000000
8298#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x00000040L
8299#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x00000006
8300#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x0000003eL
8301#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x00000001
8302#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x00003f80L
8303#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x00000007
8304#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
8305#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x00000000
8306#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
8307#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x00000006
8308#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003eL
8309#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x00000001
8310#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000fe00L
8311#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x00000009
8312#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L
8313#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x00000007
8314#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
8315#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x00000000
8316#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L
8317#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x00000008
8318#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
8319#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x00000006
8320#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003eL
8321#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x00000001
8322#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x01ff0000L
8323#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x00000010
8324#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0x0000ff80L
8325#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x00000007
8326#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x00000001L
8327#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x00000000
8328#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x00000040L
8329#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x00000006
8330#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x0000003eL
8331#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x00000001
8332#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x007f0000L
8333#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x00000010
8334#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x01ff0000L
8335#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x00000010
8336#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0x0000ff80L
8337#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x00000007
8338#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x00000001L
8339#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x00000000
8340#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x00000040L
8341#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x00000006
8342#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x0000003eL
8343#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x00000001
8344#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000ff80L
8345#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x00000007
8346#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L
8347#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x00000000
8348#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L
8349#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x00000006
8350#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003eL
8351#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x00000001
8352#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x01ff0000L
8353#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x00000010
8354#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0x0000ff80L
8355#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x00000007
8356#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x00000001L
8357#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x00000000
8358#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x00000040L
8359#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x00000006
8360#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x0000003eL
8361#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x00000001
8362#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x007f0000L
8363#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x00000010
8364#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000ff00L
8365#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x00000008
8366#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
8367#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x00000000
8368#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
8369#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x00000006
8370#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003eL
8371#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x00000001
8372#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
8373#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x00000007
8374#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x000fe000L
8375#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0x0000000d
8376#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
8377#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x00000007
8378#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
8379#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x00000000
8380#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
8381#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x00000008
8382#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
8383#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x00000009
8384#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
8385#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0x0000000a
8386#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
8387#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0x0000000b
8388#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
8389#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0x0000000c
8390#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
8391#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x00000006
8392#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003eL
8393#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x00000001
8394#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000fL
8395#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x00000000
8396#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000f0L
8397#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x00000004
8398#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000f00L
8399#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x00000008
8400#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000f000L
8401#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0x0000000c
8402#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0x000000ffL
8403#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x00000000
8404#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0x000000ffL
8405#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x00000000
8406#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0x000000ffL
8407#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x00000000
8408#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0x000000ffL
8409#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x00000000
8410#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0x000000ffL
8411#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x00000000
8412#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0x000000ffL
8413#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x00000000
8414#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffffL
8415#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x00000000
8416#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffffL
8417#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x00000000
8418#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffffL
8419#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x00000000
8420#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffffL
8421#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x00000000
8422#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffffL
8423#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x00000000
8424#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffffL
8425#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x00000000
8426#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0x000000ffL
8427#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x00000000
8428#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0x000000ffL
8429#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x00000000
8430#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0x000000ffL
8431#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x00000000
8432#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0x000000ffL
8433#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x00000000
8434#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0x000000ffL
8435#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x00000000
8436#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0x000000ffL
8437#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x00000000
8438#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffffL
8439#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x00000000
8440#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffffL
8441#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x00000000
8442#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffffL
8443#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x00000000
8444#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffffL
8445#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x00000000
8446#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffffL
8447#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x00000000
8448#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffffL
8449#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x00000000
8450#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffffL
8451#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x00000000
8452#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffffL
8453#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x00000000
8454#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffffL
8455#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x00000000
8456#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffffL
8457#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x00000000
8458#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffffL
8459#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x00000000
8460#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffffL
8461#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x00000000
8462#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffffL
8463#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x00000000
8464#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffffL
8465#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x00000000
8466#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffffL
8467#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x00000000
8468#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffffL
8469#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x00000000
8470#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffffL
8471#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x00000000
8472#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffffL
8473#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x00000000
8474#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffffL
8475#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x00000000
8476#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffffL
8477#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x00000000
8478#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffffL
8479#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x00000000
8480#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffffL
8481#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x00000000
8482#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffffL
8483#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x00000000
8484#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffffL
8485#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x00000000
8486#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffffL
8487#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x00000000
8488#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffffL
8489#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x00000000
8490#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffffL
8491#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x00000000
8492#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffffL
8493#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x00000000
8494#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffffL
8495#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x00000000
8496#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffffL
8497#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x00000000
8498#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffffL
8499#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x00000000
8500#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffffL
8501#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x00000000
8502#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffffL
8503#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x00000000
8504#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffffL
8505#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x00000000
8506#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffffL
8507#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x00000000
8508#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffffL
8509#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x00000000
8510#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffffL
8511#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x00000000
8512#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffffL
8513#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x00000000
8514#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffffL
8515#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x00000000
8516#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffffL
8517#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x00000000
8518#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffffL
8519#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x00000000
8520#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffffL
8521#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x00000000
8522#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffffL
8523#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x00000000
8524#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffffL
8525#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x00000000
8526#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffffL
8527#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x00000000
8528#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffffL
8529#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x00000000
8530#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffffL
8531#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x00000000
8532#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffffL
8533#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x00000000
8534#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffffL
8535#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x00000000
8536#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffffL
8537#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x00000000
8538#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffffL
8539#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x00000000
8540#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffffL
8541#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x00000000
8542#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffffL
8543#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x00000000
8544#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffffL
8545#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x00000000
8546#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffffL
8547#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x00000000
8548#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffffL
8549#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x00000000
8550#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffffL
8551#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x00000000
8552#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffffL
8553#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x00000000
8554#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffffL
8555#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x00000000
8556#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffffL
8557#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x00000000
8558#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffffL
8559#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x00000000
8560#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffffL
8561#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x00000000
8562#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffffL
8563#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x00000000
8564#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffffL
8565#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x00000000
8566#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffffL
8567#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x00000000
8568#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffffL
8569#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x00000000
8570#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffffL
8571#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x00000000
8572#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffffL
8573#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x00000000
8574#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffffL
8575#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x00000000
8576#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffffL
8577#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x00000000
8578#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffffL
8579#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x00000000
8580#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffffL
8581#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x00000000
8582#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffffL
8583#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x00000000
8584#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffffL
8585#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x00000000
8586#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffffL
8587#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x00000000
8588#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffffL
8589#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x00000000
8590#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffffL
8591#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x00000000
8592#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffffL
8593#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x00000000
8594#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffffL
8595#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x00000000
8596#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffffL
8597#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x00000000
8598#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffffL
8599#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x00000000
8600#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffffL
8601#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x00000000
8602#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffffL
8603#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x00000000
8604#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffffL
8605#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x00000000
8606#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffffL
8607#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x00000000
8608#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffffL
8609#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x00000000
8610#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffffL
8611#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x00000000
8612#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffffL
8613#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x00000000
8614#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffffL
8615#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x00000000
8616#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffffL
8617#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x00000000
8618#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffffL
8619#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x00000000
8620#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffffL
8621#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x00000000
8622#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffffL
8623#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x00000000
8624#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffffL
8625#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x00000000
8626#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffffL
8627#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x00000000
8628#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffffL
8629#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x00000000
8630#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffffL
8631#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x00000000
8632#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffffL
8633#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x00000000
8634#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffffL
8635#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x00000000
8636#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffffL
8637#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x00000000
8638#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffffL
8639#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x00000000
8640#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffffL
8641#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x00000000
8642#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000fL
8643#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x00000000
8644#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L
8645#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x00000002
8646#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00200000L
8647#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x00000015
8648#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L
8649#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x00000003
8650#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L
8651#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x00000001
8652#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L
8653#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x00000000
8654#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000200L
8655#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x00000009
8656#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000400L
8657#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x0000000a
8658#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x00000800L
8659#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0x0000000b
8660#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x00001000L
8661#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0x0000000c
8662#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x00002000L
8663#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0x0000000d
8664#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x00004000L
8665#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0x0000000e
8666#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x00008000L
8667#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0x0000000f
8668#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x00010000L
8669#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x00000010
8670#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000020L
8671#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x00000005
8672#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000040L
8673#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x00000006
8674#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x00000080L
8675#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x00000007
8676#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x00000100L
8677#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x00000008
8678#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x00000010L
8679#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x00000004
8680#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x00020000L
8681#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x00000011
8682#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x00040000L
8683#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x00000012
8684#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x00080000L
8685#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x00000013
8686#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x00100000L
8687#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x00000014
8688#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000ffffL
8689#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x00000000
8690#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000L
8691#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x00000010
8692#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000ffffL
8693#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x00000000
8694#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000L
8695#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x00000010
8696#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L
8697#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c
8698#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000fffL
8699#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x00000000
8700#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003eL
8701#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x00000001
8702#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
8703#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x00000006
8704#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL
8705#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000
8706#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L
8707#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010
8708#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL
8709#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000
8710#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000ffffL
8711#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000
8712#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
8713#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x0000001e
8714#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000L
8715#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x00000010
8716#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
8717#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x0000001f
8718#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL
8719#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x00000000
8720#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
8721#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x00000017
8722#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x01000000L
8723#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x00000018
8724#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
8725#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0x0000000f
8726#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L
8727#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009
8728#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
8729#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000
8730#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
8731#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003
8732#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L
8733#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006
8734#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x00180000L
8735#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x00000013
8736#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x02000000L
8737#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x00000019
8738#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x04000000L
8739#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x0000001a
8740#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
8741#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x00000015
8742#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000L
8743#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x0000001b
8744#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
8745#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0x0000000c
8746#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000L
8747#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x0000001e
8748#define SQC_CACHES__DATA_INVALIDATE_MASK 0x00000002L
8749#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x00000001
8750#define SQC_CACHES__INST_INVALIDATE_MASK 0x00000001L
8751#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x00000000
8752#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x00000004L
8753#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x00000002
8754#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000cL
8755#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x00000002
8756#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
8757#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x00000007
8758#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
8759#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x00000008
8760#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
8761#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x00000006
8762#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
8763#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x00000009
8764#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
8765#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0x0000000a
8766#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
8767#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x00000000
8768#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
8769#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x00000004
8770#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
8771#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x0000000b
8772#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L
8773#define SQ_CONFIG__DEBUG_EN__SHIFT 0x00000008
8774#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x00000400L
8775#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0x0000000a
8776#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x00000200L
8777#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x00000009
8778#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
8779#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0x0000000f
8780#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
8781#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0x0000000d
8782#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
8783#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0x0000000e
8784#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
8785#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0x0000000c
8786#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x00000800L
8787#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0x0000000b
8788#define SQ_CONFIG__UNUSED_MASK 0x000000ffL
8789#define SQ_CONFIG__UNUSED__SHIFT 0x00000000
8790#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000L
8791#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x00000018
8792#define SQC_SECDED_CNT__DATA_SEC_MASK 0x00ff0000L
8793#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x00000010
8794#define SQC_SECDED_CNT__INST_DED_MASK 0x0000ff00L
8795#define SQC_SECDED_CNT__INST_DED__SHIFT 0x00000008
8796#define SQC_SECDED_CNT__INST_SEC_MASK 0x000000ffL
8797#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x00000000
8798#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000ffL
8799#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x00000000
8800#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
8801#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
8802#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
8803#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
8804#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L
8805#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018
8806#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L
8807#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010
8808#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL
8809#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000
8810#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L
8811#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004
8812#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
8813#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
8814#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
8815#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
8816#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L
8817#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004
8818#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L
8819#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010
8820#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
8821#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
8822#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
8823#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
8824#define SQ_DED_CNT__LDS_DED_MASK 0x0000003fL
8825#define SQ_DED_CNT__LDS_DED__SHIFT 0x00000000
8826#define SQ_DED_CNT__SGPR_DED_MASK 0x00001f00L
8827#define SQ_DED_CNT__SGPR_DED__SHIFT 0x00000008
8828#define SQ_DED_CNT__VGPR_DED_MASK 0x01ff0000L
8829#define SQ_DED_CNT__VGPR_DED__SHIFT 0x00000010
8830#define SQ_DED_INFO__SIMD_ID_MASK 0x00000030L
8831#define SQ_DED_INFO__SIMD_ID__SHIFT 0x00000004
8832#define SQ_DED_INFO__SOURCE_MASK 0x000001c0L
8833#define SQ_DED_INFO__SOURCE__SHIFT 0x00000006
8834#define SQ_DED_INFO__VM_ID_MASK 0x00001e00L
8835#define SQ_DED_INFO__VM_ID__SHIFT 0x00000009
8836#define SQ_DED_INFO__WAVE_ID_MASK 0x0000000fL
8837#define SQ_DED_INFO__WAVE_ID__SHIFT 0x00000000
8838#define SQ_DS_0__ENCODING_MASK 0xfc000000L
8839#define SQ_DS_0__ENCODING__SHIFT 0x0000001a
8840#define SQ_DS_0__GDS_MASK 0x00020000L
8841#define SQ_DS_0__GDS__SHIFT 0x00000011
8842#define SQ_DS_0__OFFSET0_MASK 0x000000ffL
8843#define SQ_DS_0__OFFSET0__SHIFT 0x00000000
8844#define SQ_DS_0__OFFSET1_MASK 0x0000ff00L
8845#define SQ_DS_0__OFFSET1__SHIFT 0x00000008
8846#define SQ_DS_0__OP_MASK 0x03fc0000L
8847#define SQ_DS_0__OP__SHIFT 0x00000012
8848#define SQ_DS_1__ADDR_MASK 0x000000ffL
8849#define SQ_DS_1__ADDR__SHIFT 0x00000000
8850#define SQ_DS_1__DATA0_MASK 0x0000ff00L
8851#define SQ_DS_1__DATA0__SHIFT 0x00000008
8852#define SQ_DS_1__DATA1_MASK 0x00ff0000L
8853#define SQ_DS_1__DATA1__SHIFT 0x00000010
8854#define SQ_DS_1__VDST_MASK 0xff000000L
8855#define SQ_DS_1__VDST__SHIFT 0x00000018
8856#define SQ_EXP_0__COMPR_MASK 0x00000400L
8857#define SQ_EXP_0__COMPR__SHIFT 0x0000000a
8858#define SQ_EXP_0__DONE_MASK 0x00000800L
8859#define SQ_EXP_0__DONE__SHIFT 0x0000000b
8860#define SQ_EXP_0__ENCODING_MASK 0xfc000000L
8861#define SQ_EXP_0__ENCODING__SHIFT 0x0000001a
8862#define SQ_EXP_0__EN_MASK 0x0000000fL
8863#define SQ_EXP_0__EN__SHIFT 0x00000000
8864#define SQ_EXP_0__TGT_MASK 0x000003f0L
8865#define SQ_EXP_0__TGT__SHIFT 0x00000004
8866#define SQ_EXP_0__VM_MASK 0x00001000L
8867#define SQ_EXP_0__VM__SHIFT 0x0000000c
8868#define SQ_EXP_1__VSRC0_MASK 0x000000ffL
8869#define SQ_EXP_1__VSRC0__SHIFT 0x00000000
8870#define SQ_EXP_1__VSRC1_MASK 0x0000ff00L
8871#define SQ_EXP_1__VSRC1__SHIFT 0x00000008
8872#define SQ_EXP_1__VSRC2_MASK 0x00ff0000L
8873#define SQ_EXP_1__VSRC2__SHIFT 0x00000010
8874#define SQ_EXP_1__VSRC3_MASK 0xff000000L
8875#define SQ_EXP_1__VSRC3__SHIFT 0x00000018
8876#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
8877#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x00000010
8878#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000fL
8879#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x00000000
8880#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000f00L
8881#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x00000008
8882#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000c0000L
8883#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x00000012
8884#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL
8885#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000
8886#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000ffL
8887#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000
8888#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03f00000L
8889#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x00000014
8890#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000fff00L
8891#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x00000008
8892#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000L
8893#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x0000001e
8894#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000L
8895#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x0000001a
8896#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0fffc000L
8897#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0x0000000e
8898#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000L
8899#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x0000001f
8900#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
8901#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x0000001c
8902#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003fffL
8903#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x00000000
8904#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x08000000L
8905#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x0000001b
8906#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000f000L
8907#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0x0000000c
8908#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L
8909#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009
8910#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
8911#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000
8912#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
8913#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003
8914#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L
8915#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006
8916#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000f0000L
8917#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x00000010
8918#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x04000000L
8919#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x0000001a
8920#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x02000000L
8921#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x00000019
8922#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x01f00000L
8923#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x00000014
8924#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000L
8925#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x0000001c
8926#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001fffL
8927#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x00000000
8928#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x07ffe000L
8929#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0x0000000d
8930#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001fffL
8931#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x00000000
8932#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x03ffe000L
8933#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0x0000000d
8934#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000ff000L
8935#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0x0000000c
8936#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
8937#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x00000014
8938#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000fffL
8939#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x00000000
8940#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000L
8941#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x00000015
8942#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffffL
8943#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x00000000
8944#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07e00000L
8945#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x00000015
8946#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
8947#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x00000010
8948#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
8949#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x00000000
8950#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
8951#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x00000003
8952#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001c0L
8953#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x00000006
8954#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
8955#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0x0000000c
8956#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
8957#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x0000001c
8958#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
8959#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x0000001d
8960#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
8961#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x00000014
8962#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
8963#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0x0000000f
8964#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000e00L
8965#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x00000009
8966#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
8967#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x00000013
8968#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
8969#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x0000001b
8970#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00fff000L
8971#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0x0000000c
8972#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000fffL
8973#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x00000000
8974#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0f000000L
8975#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x00000018
8976#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000L
8977#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x0000001c
8978#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000L
8979#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x0000001d
8980#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
8981#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x0000001e
8982#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003fffL
8983#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000fc000L
8984#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0x0000000e
8985#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x00000000
8986#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0c000000L
8987#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x0000001a
8988#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
8989#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x0000001c
8990#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
8991#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x00000014
8992#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00c00000L
8993#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x00000016
8994#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
8995#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x00000018
8996#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000fffL
8997#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x00000000
8998#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000L
8999#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x0000001e
9000#define SQ_IND_DATA__DATA_MASK 0xffffffffL
9001#define SQ_IND_DATA__DATA__SHIFT 0x00000000
9002#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
9003#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0x0000000c
9004#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
9005#define SQ_IND_INDEX__FORCE_READ__SHIFT 0x0000000d
9006#define SQ_IND_INDEX__INDEX_MASK 0xffff0000L
9007#define SQ_IND_INDEX__INDEX__SHIFT 0x00000010
9008#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
9009#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0x0000000e
9010#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
9011#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004
9012#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000fc0L
9013#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x00000006
9014#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
9015#define SQ_IND_INDEX__UNINDEXED__SHIFT 0x0000000f
9016#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000fL
9017#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x00000000
9018#define SQ_INST__ENCODING_MASK 0xffffffffL
9019#define SQ_INST__ENCODING__SHIFT 0x00000000
9020#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x00000010L
9021#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x00000004
9022#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0x0c000000L
9023#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x0000001a
9024#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x00000020L
9025#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x00000005
9026#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x00000040L
9027#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x00000006
9028#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x00000080L
9029#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x00000007
9030#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x00000008L
9031#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x00000003
9032#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x02000000L
9033#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x00000019
9034#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x00000004L
9035#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x00000002
9036#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x00000001L
9037#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x00000000
9038#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x00000002L
9039#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x00000001
9040#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0x0c000000L
9041#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x0000001a
9042#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x02000000L
9043#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x00000019
9044#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0x00f00000L
9045#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x00000014
9046#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x000000ffL
9047#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x00000000
9048#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0x0c000000L
9049#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x0000001a
9050#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x00000200L
9051#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x00000009
9052#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x02000000L
9053#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x00000019
9054#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x01000000L
9055#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x00000018
9056#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x000c0000L
9057#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x00000012
9058#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x00003c00L
9059#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0x0000000a
9060#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x0003c000L
9061#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x0000000e
9062#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
9063#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x00000002
9064#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
9065#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x00000001
9066#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
9067#define SQ_LB_CTR_CTRL__START__SHIFT 0x00000000
9068#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffffL
9069#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x00000000
9070#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffffL
9071#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x00000000
9072#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffffL
9073#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x00000000
9074#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffffL
9075#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x00000000
9076#define SQ_MIMG_0__DA_MASK 0x00004000L
9077#define SQ_MIMG_0__DA__SHIFT 0x0000000e
9078#define SQ_MIMG_0__DMASK_MASK 0x00000f00L
9079#define SQ_MIMG_0__DMASK__SHIFT 0x00000008
9080#define SQ_MIMG_0__ENCODING_MASK 0xfc000000L
9081#define SQ_MIMG_0__ENCODING__SHIFT 0x0000001a
9082#define SQ_MIMG_0__GLC_MASK 0x00002000L
9083#define SQ_MIMG_0__GLC__SHIFT 0x0000000d
9084#define SQ_MIMG_0__LWE_MASK 0x00020000L
9085#define SQ_MIMG_0__LWE__SHIFT 0x00000011
9086#define SQ_MIMG_0__OP_MASK 0x01fc0000L
9087#define SQ_MIMG_0__OP__SHIFT 0x00000012
9088#define SQ_MIMG_0__R128_MASK 0x00008000L
9089#define SQ_MIMG_0__R128__SHIFT 0x0000000f
9090#define SQ_MIMG_0__SLC_MASK 0x02000000L
9091#define SQ_MIMG_0__SLC__SHIFT 0x00000019
9092#define SQ_MIMG_0__TFE_MASK 0x00010000L
9093#define SQ_MIMG_0__TFE__SHIFT 0x00000010
9094#define SQ_MIMG_0__UNORM_MASK 0x00001000L
9095#define SQ_MIMG_0__UNORM__SHIFT 0x0000000c
9096#define SQ_MIMG_1__SRSRC_MASK 0x001f0000L
9097#define SQ_MIMG_1__SRSRC__SHIFT 0x00000010
9098#define SQ_MIMG_1__SSAMP_MASK 0x03e00000L
9099#define SQ_MIMG_1__SSAMP__SHIFT 0x00000015
9100#define SQ_MIMG_1__VADDR_MASK 0x000000ffL
9101#define SQ_MIMG_1__VADDR__SHIFT 0x00000000
9102#define SQ_MIMG_1__VDATA_MASK 0x0000ff00L
9103#define SQ_MIMG_1__VDATA__SHIFT 0x00000008
9104#define SQ_MTBUF_0__ADDR64_MASK 0x00008000L
9105#define SQ_MTBUF_0__ADDR64__SHIFT 0x0000000f
9106#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
9107#define SQ_MTBUF_0__DFMT__SHIFT 0x00000013
9108#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000L
9109#define SQ_MTBUF_0__ENCODING__SHIFT 0x0000001a
9110#define SQ_MTBUF_0__GLC_MASK 0x00004000L
9111#define SQ_MTBUF_0__GLC__SHIFT 0x0000000e
9112#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
9113#define SQ_MTBUF_0__IDXEN__SHIFT 0x0000000d
9114#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
9115#define SQ_MTBUF_0__NFMT__SHIFT 0x00000017
9116#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
9117#define SQ_MTBUF_0__OFFEN__SHIFT 0x0000000c
9118#define SQ_MTBUF_0__OFFSET_MASK 0x00000fffL
9119#define SQ_MTBUF_0__OFFSET__SHIFT 0x00000000
9120#define SQ_MTBUF_0__OP_MASK 0x00070000L
9121#define SQ_MTBUF_0__OP__SHIFT 0x00000010
9122#define SQ_MTBUF_1__SLC_MASK 0x00400000L
9123#define SQ_MTBUF_1__SLC__SHIFT 0x00000016
9124#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000L
9125#define SQ_MTBUF_1__SOFFSET__SHIFT 0x00000018
9126#define SQ_MTBUF_1__SRSRC_MASK 0x001f0000L
9127#define SQ_MTBUF_1__SRSRC__SHIFT 0x00000010
9128#define SQ_MTBUF_1__TFE_MASK 0x00800000L
9129#define SQ_MTBUF_1__TFE__SHIFT 0x00000017
9130#define SQ_MTBUF_1__VADDR_MASK 0x000000ffL
9131#define SQ_MTBUF_1__VADDR__SHIFT 0x00000000
9132#define SQ_MTBUF_1__VDATA_MASK 0x0000ff00L
9133#define SQ_MTBUF_1__VDATA__SHIFT 0x00000008
9134#define SQ_MUBUF_0__ADDR64_MASK 0x00008000L
9135#define SQ_MUBUF_0__ADDR64__SHIFT 0x0000000f
9136#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000L
9137#define SQ_MUBUF_0__ENCODING__SHIFT 0x0000001a
9138#define SQ_MUBUF_0__GLC_MASK 0x00004000L
9139#define SQ_MUBUF_0__GLC__SHIFT 0x0000000e
9140#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
9141#define SQ_MUBUF_0__IDXEN__SHIFT 0x0000000d
9142#define SQ_MUBUF_0__LDS_MASK 0x00010000L
9143#define SQ_MUBUF_0__LDS__SHIFT 0x00000010
9144#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
9145#define SQ_MUBUF_0__OFFEN__SHIFT 0x0000000c
9146#define SQ_MUBUF_0__OFFSET_MASK 0x00000fffL
9147#define SQ_MUBUF_0__OFFSET__SHIFT 0x00000000
9148#define SQ_MUBUF_0__OP_MASK 0x01fc0000L
9149#define SQ_MUBUF_0__OP__SHIFT 0x00000012
9150#define SQ_MUBUF_1__SLC_MASK 0x00400000L
9151#define SQ_MUBUF_1__SLC__SHIFT 0x00000016
9152#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000L
9153#define SQ_MUBUF_1__SOFFSET__SHIFT 0x00000018
9154#define SQ_MUBUF_1__SRSRC_MASK 0x001f0000L
9155#define SQ_MUBUF_1__SRSRC__SHIFT 0x00000010
9156#define SQ_MUBUF_1__TFE_MASK 0x00800000L
9157#define SQ_MUBUF_1__TFE__SHIFT 0x00000017
9158#define SQ_MUBUF_1__VADDR_MASK 0x000000ffL
9159#define SQ_MUBUF_1__VADDR__SHIFT 0x00000000
9160#define SQ_MUBUF_1__VDATA_MASK 0x0000ff00L
9161#define SQ_MUBUF_1__VDATA__SHIFT 0x00000008
9162#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9163#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9164#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9165#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9166#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
9167#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
9168#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL
9169#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
9170#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0f000000L
9171#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x00000018
9172#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L
9173#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014
9174#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9175#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9176#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9177#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9178#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9179#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9180#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9181#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9182#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000L
9183#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x0000001c
9184#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001ffL
9185#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x00000000
9186#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0f000000L
9187#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x00000018
9188#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00f00000L
9189#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x00000014
9190#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9191#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9192#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9193#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9194#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9195#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9196#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9197#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9198#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000L
9199#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x0000001c
9200#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001ffL
9201#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x00000000
9202#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0f000000L
9203#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x00000018
9204#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00f00000L
9205#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x00000014
9206#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9207#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9208#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9209#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9210#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9211#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9212#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9213#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9214#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000L
9215#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x0000001c
9216#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001ffL
9217#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x00000000
9218#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0f000000L
9219#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x00000018
9220#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00f00000L
9221#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x00000014
9222#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9223#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9224#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9225#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9226#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9227#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9228#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9229#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9230#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000L
9231#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x0000001c
9232#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001ffL
9233#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x00000000
9234#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0f000000L
9235#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x00000018
9236#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00f00000L
9237#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x00000014
9238#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9239#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9240#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9241#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9242#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9243#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9244#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9245#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9246#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000L
9247#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x0000001c
9248#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001ffL
9249#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x00000000
9250#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0f000000L
9251#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x00000018
9252#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00f00000L
9253#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x00000014
9254#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9255#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9256#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9257#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9258#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9259#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9260#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9261#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9262#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000L
9263#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x0000001c
9264#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001ffL
9265#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x00000000
9266#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0f000000L
9267#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x00000018
9268#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00f00000L
9269#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x00000014
9270#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9271#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9272#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9273#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9274#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9275#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9276#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9277#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9278#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
9279#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
9280#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL
9281#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
9282#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0f000000L
9283#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x00000018
9284#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L
9285#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014
9286#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9287#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9288#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9289#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9290#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9291#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9292#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9293#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9294#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
9295#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
9296#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL
9297#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
9298#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0f000000L
9299#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x00000018
9300#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00f00000L
9301#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x00000014
9302#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9303#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9304#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9305#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9306#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9307#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9308#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9309#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9310#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
9311#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
9312#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL
9313#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
9314#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0f000000L
9315#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x00000018
9316#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00f00000L
9317#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x00000014
9318#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9319#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9320#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9321#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9322#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9323#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9324#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9325#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9326#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000L
9327#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x0000001c
9328#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL
9329#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000
9330#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0f000000L
9331#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x00000018
9332#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00f00000L
9333#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x00000014
9334#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9335#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9336#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9337#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9338#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9339#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9340#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9341#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9342#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000L
9343#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x0000001c
9344#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL
9345#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000
9346#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0f000000L
9347#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x00000018
9348#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00f00000L
9349#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x00000014
9350#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9351#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9352#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9353#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9354#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9355#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9356#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9357#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9358#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000L
9359#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x0000001c
9360#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL
9361#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000
9362#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0f000000L
9363#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x00000018
9364#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00f00000L
9365#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x00000014
9366#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9367#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9368#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9369#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9370#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9371#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9372#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9373#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9374#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000L
9375#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x0000001c
9376#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL
9377#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000
9378#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0f000000L
9379#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x00000018
9380#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00f00000L
9381#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x00000014
9382#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9383#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9384#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9385#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9386#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9387#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9388#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9389#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9390#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000L
9391#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x0000001c
9392#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001ffL
9393#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x00000000
9394#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0f000000L
9395#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x00000018
9396#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00f00000L
9397#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x00000014
9398#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9399#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9400#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9401#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9402#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffffL
9403#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000
9404#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffffL
9405#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x00000000
9406#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000L
9407#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x0000001c
9408#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001ffL
9409#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x00000000
9410#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0f000000L
9411#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x00000018
9412#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00f00000L
9413#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x00000014
9414#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000f000L
9415#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c
9416#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L
9417#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010
9418#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
9419#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x00000000
9420#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001f00L
9421#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x00000008
9422#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
9423#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x00000006
9424#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
9425#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0x0000000d
9426#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
9427#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x00000003
9428#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
9429#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x00000002
9430#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
9431#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x00000004
9432#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
9433#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x00000005
9434#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
9435#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x00000000
9436#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
9437#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x00000001
9438#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
9439#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b
9440#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003fffL
9441#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x00000000
9442#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L
9443#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010
9444#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
9445#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x0000001f
9446#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000L
9447#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x00000010
9448#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003fffL
9449#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x00000000
9450#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000L
9451#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x0000001e
9452#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007fL
9453#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x00000000
9454#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x001ffc00L
9455#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0x0000000a
9456#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
9457#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x00000007
9458#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000f00L
9459#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x00000008
9460#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
9461#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x0000001f
9462#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
9463#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x0000001e
9464#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
9465#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x0000001c
9466#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003fL
9467#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x00000000
9468#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
9469#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x0000001d
9470#define SQ_SEC_CNT__LDS_SEC_MASK 0x0000003fL
9471#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x00000000
9472#define SQ_SEC_CNT__SGPR_SEC_MASK 0x00001f00L
9473#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x00000008
9474#define SQ_SEC_CNT__VGPR_SEC_MASK 0x01ff0000L
9475#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x00000010
9476#define SQ_SMRD__ENCODING_MASK 0xf8000000L
9477#define SQ_SMRD__ENCODING__SHIFT 0x0000001b
9478#define SQ_SMRD__IMM_MASK 0x00000100L
9479#define SQ_SMRD__IMM__SHIFT 0x00000008
9480#define SQ_SMRD__OFFSET_MASK 0x000000ffL
9481#define SQ_SMRD__OFFSET__SHIFT 0x00000000
9482#define SQ_SMRD__OP_MASK 0x07c00000L
9483#define SQ_SMRD__OP__SHIFT 0x00000016
9484#define SQ_SMRD__SBASE_MASK 0x00007e00L
9485#define SQ_SMRD__SBASE__SHIFT 0x00000009
9486#define SQ_SMRD__SDST_MASK 0x003f8000L
9487#define SQ_SMRD__SDST__SHIFT 0x0000000f
9488#define SQ_SOP1__ENCODING_MASK 0xff800000L
9489#define SQ_SOP1__ENCODING__SHIFT 0x00000017
9490#define SQ_SOP1__OP_MASK 0x0000ff00L
9491#define SQ_SOP1__OP__SHIFT 0x00000008
9492#define SQ_SOP1__SDST_MASK 0x007f0000L
9493#define SQ_SOP1__SDST__SHIFT 0x00000010
9494#define SQ_SOP1__SSRC0_MASK 0x000000ffL
9495#define SQ_SOP1__SSRC0__SHIFT 0x00000000
9496#define SQ_SOP2__ENCODING_MASK 0xc0000000L
9497#define SQ_SOP2__ENCODING__SHIFT 0x0000001e
9498#define SQ_SOP2__OP_MASK 0x3f800000L
9499#define SQ_SOP2__OP__SHIFT 0x00000017
9500#define SQ_SOP2__SDST_MASK 0x007f0000L
9501#define SQ_SOP2__SDST__SHIFT 0x00000010
9502#define SQ_SOP2__SSRC0_MASK 0x000000ffL
9503#define SQ_SOP2__SSRC0__SHIFT 0x00000000
9504#define SQ_SOP2__SSRC1_MASK 0x0000ff00L
9505#define SQ_SOP2__SSRC1__SHIFT 0x00000008
9506#define SQ_SOPC__ENCODING_MASK 0xff800000L
9507#define SQ_SOPC__ENCODING__SHIFT 0x00000017
9508#define SQ_SOPC__OP_MASK 0x007f0000L
9509#define SQ_SOPC__OP__SHIFT 0x00000010
9510#define SQ_SOPC__SSRC0_MASK 0x000000ffL
9511#define SQ_SOPC__SSRC0__SHIFT 0x00000000
9512#define SQ_SOPC__SSRC1_MASK 0x0000ff00L
9513#define SQ_SOPC__SSRC1__SHIFT 0x00000008
9514#define SQ_SOPK__ENCODING_MASK 0xf0000000L
9515#define SQ_SOPK__ENCODING__SHIFT 0x0000001c
9516#define SQ_SOPK__OP_MASK 0x0f800000L
9517#define SQ_SOPK__OP__SHIFT 0x00000017
9518#define SQ_SOPK__SDST_MASK 0x007f0000L
9519#define SQ_SOPK__SDST__SHIFT 0x00000010
9520#define SQ_SOPK__SIMM16_MASK 0x0000ffffL
9521#define SQ_SOPK__SIMM16__SHIFT 0x00000000
9522#define SQ_SOPP__ENCODING_MASK 0xff800000L
9523#define SQ_SOPP__ENCODING__SHIFT 0x00000017
9524#define SQ_SOPP__OP_MASK 0x007f0000L
9525#define SQ_SOPP__OP__SHIFT 0x00000010
9526#define SQ_SOPP__SIMM16_MASK 0x0000ffffL
9527#define SQ_SOPP__SIMM16__SHIFT 0x00000000
9528#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL
9529#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000
9530#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L
9531#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010
9532#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000fL
9533#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x00000000
9534#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x00000010L
9535#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x00000004
9536#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffffL
9537#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x00000000
9538#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffffL
9539#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x00000000
9540#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
9541#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x0000001f
9542#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
9543#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x00000000
9544#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001fL
9545#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x00000000
9546#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000L
9547#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x00000010
9548#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
9549#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x00000007
9550#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
9551#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x00000005
9552#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
9553#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0x0000000e
9554#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
9555#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0x0000000f
9556#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
9557#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0x0000000c
9558#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
9559#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x00000019
9560#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
9561#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x00000017
9562#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
9563#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x0000001e
9564#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
9565#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x0000001b
9566#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001c0000L
9567#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x00000012
9568#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000e00L
9569#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x00000009
9570#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001c0L
9571#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x00000006
9572#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
9573#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0x0000000c
9574#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
9575#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0x0000000f
9576#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
9577#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x00000000
9578#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
9579#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x00000003
9580#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
9581#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x00000015
9582#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x04000000L
9583#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x0000001a
9584#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
9585#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x0000001d
9586#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
9587#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x0000001f
9588#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000ffffL
9589#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x00000000
9590#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000L
9591#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x00000010
9592#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003fffffL
9593#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x00000000
9594#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
9595#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x0000001e
9596#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00070000L
9597#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x00000010
9598#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000007L
9599#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x00000000
9600#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
9601#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x0000001f
9602#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
9603#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x0000001d
9604#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0x0000ffffL
9605#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x00000000
9606#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
9607#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x00000018
9608#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00ff0000L
9609#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x00000010
9610#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000ffffL
9611#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x00000000
9612#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffffL
9613#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x00000000
9614#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffffL
9615#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x00000000
9616#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffffL
9617#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x00000000
9618#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffffL
9619#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x00000000
9620#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x00000010L
9621#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x00000004
9622#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x0000000fL
9623#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x00000000
9624#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0x0000fc00L
9625#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0x0000000a
9626#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x00000020L
9627#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x00000005
9628#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x000001c0L
9629#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x00000006
9630#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x00000010L
9631#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x00000004
9632#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x0000000fL
9633#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x00000000
9634#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0x0000f000L
9635#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0x0000000c
9636#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000L
9637#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x00000010
9638#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
9639#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x00000009
9640#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
9641#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x00000004
9642#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL
9643#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000
9644#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001e0L
9645#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x00000005
9646#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00ffffffL
9647#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x00000000
9648#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x00000600L
9649#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x00000009
9650#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x00000800L
9651#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0x0000000b
9652#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x00000010L
9653#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x00000004
9654#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x0000000fL
9655#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x00000000
9656#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003c0L
9657#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x00000006
9658#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000L
9659#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x00000010
9660#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
9661#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x00000005
9662#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000c000L
9663#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0x0000000e
9664#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
9665#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x00000004
9666#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL
9667#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000
9668#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003c00L
9669#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0x0000000a
9670#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0x0000ffffL
9671#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x00000000
9672#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x000001e0L
9673#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x00000005
9674#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
9675#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x00000008
9676#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000c00L
9677#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0x0000000a
9678#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
9679#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0x0000000c
9680#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000c000L
9681#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0x0000000e
9682#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
9683#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x00000010
9684#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000c0000L
9685#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x00000012
9686#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
9687#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x00000014
9688#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00c00000L
9689#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x00000016
9690#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
9691#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x00000018
9692#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0c000000L
9693#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x0000001a
9694#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
9695#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x00000005
9696#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
9697#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x00000004
9698#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000fL
9699#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x00000000
9700#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0x000000c0L
9701#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0x00000006
9702#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x00000020L
9703#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0x00000005
9704#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x00000010L
9705#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x00000004
9706#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x0000000fL
9707#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x00000000
9708#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01fff000L
9709#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0x0000000c
9710#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000L
9711#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x00000019
9712#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000c00L
9713#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0x0000000a
9714#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003c0L
9715#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x00000006
9716#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
9717#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x00000005
9718#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
9719#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x00000004
9720#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL
9721#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000
9722#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003fL
9723#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x00000000
9724#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007ffc0L
9725#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x00000006
9726#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000L
9727#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x00000013
9728#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
9729#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x00000007
9730#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
9731#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x00000005
9732#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000L
9733#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x00000010
9734#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
9735#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x00000009
9736#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
9737#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0x0000000f
9738#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
9739#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0x0000000e
9740#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001c00L
9741#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0x0000000a
9742#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
9743#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x00000004
9744#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL
9745#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000
9746#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffffL
9747#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x00000000
9748#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000L
9749#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x00000010
9750#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL
9751#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000
9752#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffffL
9753#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x00000000
9754#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x000003c0L
9755#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x00000006
9756#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x00000020L
9757#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x00000005
9758#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0x0000c000L
9759#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0x0000000e
9760#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000L
9761#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x00000016
9762#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003c0L
9763#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x00000006
9764#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001f0000L
9765#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x00000010
9766#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
9767#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x00000005
9768#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000c000L
9769#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0x0000000e
9770#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000L
9771#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x0000001d
9772#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
9773#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x00000004
9774#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000fL
9775#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x00000000
9776#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
9777#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x00000015
9778#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003c00L
9779#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0x0000000a
9780#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x00000010L
9781#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x00000004
9782#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x0000000fL
9783#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x00000000
9784#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x00003c00L
9785#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0x0000000a
9786#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000L
9787#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x0000001e
9788#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffffL
9789#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x00000000
9790#define SQ_TIME_HI__TIME_MASK 0xffffffffL
9791#define SQ_TIME_HI__TIME__SHIFT 0x00000000
9792#define SQ_TIME_LO__TIME_MASK 0xffffffffL
9793#define SQ_TIME_LO__TIME__SHIFT 0x00000000
9794#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
9795#define SQ_VINTRP__ATTRCHAN__SHIFT 0x00000008
9796#define SQ_VINTRP__ATTR_MASK 0x0000fc00L
9797#define SQ_VINTRP__ATTR__SHIFT 0x0000000a
9798#define SQ_VINTRP__ENCODING_MASK 0xfc000000L
9799#define SQ_VINTRP__ENCODING__SHIFT 0x0000001a
9800#define SQ_VINTRP__OP_MASK 0x00030000L
9801#define SQ_VINTRP__OP__SHIFT 0x00000010
9802#define SQ_VINTRP__VDST_MASK 0x03fc0000L
9803#define SQ_VINTRP__VDST__SHIFT 0x00000012
9804#define SQ_VINTRP__VSRC_MASK 0x000000ffL
9805#define SQ_VINTRP__VSRC__SHIFT 0x00000000
9806#define SQ_VOP1__ENCODING_MASK 0xfe000000L
9807#define SQ_VOP1__ENCODING__SHIFT 0x00000019
9808#define SQ_VOP1__OP_MASK 0x0001fe00L
9809#define SQ_VOP1__OP__SHIFT 0x00000009
9810#define SQ_VOP1__SRC0_MASK 0x000001ffL
9811#define SQ_VOP1__SRC0__SHIFT 0x00000000
9812#define SQ_VOP1__VDST_MASK 0x01fe0000L
9813#define SQ_VOP1__VDST__SHIFT 0x00000011
9814#define SQ_VOP2__ENCODING_MASK 0x80000000L
9815#define SQ_VOP2__ENCODING__SHIFT 0x0000001f
9816#define SQ_VOP2__OP_MASK 0x7e000000L
9817#define SQ_VOP2__OP__SHIFT 0x00000019
9818#define SQ_VOP2__SRC0_MASK 0x000001ffL
9819#define SQ_VOP2__SRC0__SHIFT 0x00000000
9820#define SQ_VOP2__VDST_MASK 0x01fe0000L
9821#define SQ_VOP2__VDST__SHIFT 0x00000011
9822#define SQ_VOP2__VSRC1_MASK 0x0001fe00L
9823#define SQ_VOP2__VSRC1__SHIFT 0x00000009
9824#define SQ_VOP3_0__ABS_MASK 0x00000700L
9825#define SQ_VOP3_0__ABS__SHIFT 0x00000008
9826#define SQ_VOP3_0__CLAMP_MASK 0x00000800L
9827#define SQ_VOP3_0__CLAMP__SHIFT 0x0000000b
9828#define SQ_VOP3_0__ENCODING_MASK 0xfc000000L
9829#define SQ_VOP3_0__ENCODING__SHIFT 0x0000001a
9830#define SQ_VOP3_0__OP_MASK 0x03fe0000L
9831#define SQ_VOP3_0__OP__SHIFT 0x00000011
9832#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000L
9833#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x0000001a
9834#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03fe0000L
9835#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x00000011
9836#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007f00L
9837#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x00000008
9838#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000ffL
9839#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x00000000
9840#define SQ_VOP3_0__VDST_MASK 0x000000ffL
9841#define SQ_VOP3_0__VDST__SHIFT 0x00000000
9842#define SQ_VOP3_1__NEG_MASK 0xe0000000L
9843#define SQ_VOP3_1__NEG__SHIFT 0x0000001d
9844#define SQ_VOP3_1__OMOD_MASK 0x18000000L
9845#define SQ_VOP3_1__OMOD__SHIFT 0x0000001b
9846#define SQ_VOP3_1__SRC0_MASK 0x000001ffL
9847#define SQ_VOP3_1__SRC0__SHIFT 0x00000000
9848#define SQ_VOP3_1__SRC1_MASK 0x0003fe00L
9849#define SQ_VOP3_1__SRC1__SHIFT 0x00000009
9850#define SQ_VOP3_1__SRC2_MASK 0x07fc0000L
9851#define SQ_VOP3_1__SRC2__SHIFT 0x00000012
9852#define SQ_VOPC__ENCODING_MASK 0xfe000000L
9853#define SQ_VOPC__ENCODING__SHIFT 0x00000019
9854#define SQ_VOPC__OP_MASK 0x01fe0000L
9855#define SQ_VOPC__OP__SHIFT 0x00000011
9856#define SQ_VOPC__SRC0_MASK 0x000001ffL
9857#define SQ_VOPC__SRC0__SHIFT 0x00000000
9858#define SQ_VOPC__VSRC1_MASK 0x0001fe00L
9859#define SQ_VOPC__VSRC1__SHIFT 0x00000009
9860#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffffL
9861#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x00000000
9862#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffffL
9863#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x00000000
9864#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003f0000L
9865#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x00000010
9866#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0f000000L
9867#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x00000018
9868#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003fL
9869#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x00000000
9870#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003f00L
9871#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x00000008
9872#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000f00L
9873#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x00000008
9874#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000L
9875#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x0000001e
9876#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000c0L
9877#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x00000006
9878#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
9879#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x00000018
9880#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00002000L
9881#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0x0000000d
9882#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
9883#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0x0000000c
9884#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
9885#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x00000004
9886#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
9887#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x0000001b
9888#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000f0000L
9889#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x00000010
9890#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00f00000L
9891#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x00000014
9892#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000fL
9893#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x00000000
9894#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x00c00000L
9895#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x00000016
9896#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x06000000L
9897#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x00000019
9898#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
9899#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x00000008
9900#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
9901#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000
9902#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000c00L
9903#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0x0000000a
9904#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x00070000L
9905#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x00000010
9906#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x01000000L
9907#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x00000018
9908#define SQ_WAVE_IB_DBG0__KILL_MASK 0x08000000L
9909#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x0000001b
9910#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x00380000L
9911#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x00000013
9912#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000L
9913#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x0000001c
9914#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
9915#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x00000004
9916#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000e0L
9917#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x00000005
9918#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
9919#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x00000003
9920#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
9921#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x00000004
9922#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00001f00L
9923#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x00000008
9924#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x0000e000L
9925#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0x0000000d
9926#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000fL
9927#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x00000000
9928#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffffL
9929#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x00000000
9930#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL
9931#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x00000000
9932#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000ffL
9933#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x00000000
9934#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001ff000L
9935#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0x0000000c
9936#define SQ_WAVE_M0__M0_MASK 0xffffffffL
9937#define SQ_WAVE_M0__M0__SHIFT 0x00000000
9938#define SQ_WAVE_MODE__CSP_MASK 0xe0000000L
9939#define SQ_WAVE_MODE__CSP__SHIFT 0x0000001d
9940#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L
9941#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0x0000000b
9942#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
9943#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x00000008
9944#define SQ_WAVE_MODE__EXCP_EN_MASK 0x0007f000L
9945#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0x0000000c
9946#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000f0L
9947#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x00000004
9948#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000fL
9949#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x00000000
9950#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
9951#define SQ_WAVE_MODE__IEEE__SHIFT 0x00000009
9952#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
9953#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0x0000000a
9954#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
9955#define SQ_WAVE_MODE__VSKIP__SHIFT 0x0000001c
9956#define SQ_WAVE_PC_HI__PC_HI_MASK 0x000000ffL
9957#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x00000000
9958#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffffL
9959#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x00000000
9960#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L
9961#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x00000015
9962#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L
9963#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x00000014
9964#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x00400000L
9965#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x00000016
9966#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x07000000L
9967#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x00000018
9968#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
9969#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x00000011
9970#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
9971#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x00000009
9972#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
9973#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x00000008
9974#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
9975#define SQ_WAVE_STATUS__HALT__SHIFT 0x0000000d
9976#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
9977#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0x0000000c
9978#define SQ_WAVE_STATUS__INST_ATC_MASK 0x00800000L
9979#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x00000017
9980#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
9981#define SQ_WAVE_STATUS__IN_TG__SHIFT 0x0000000b
9982#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
9983#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x0000001b
9984#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
9985#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x00000013
9986#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
9987#define SQ_WAVE_STATUS__PRIV__SHIFT 0x00000005
9988#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
9989#define SQ_WAVE_STATUS__SCC__SHIFT 0x00000000
9990#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
9991#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x00000012
9992#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
9993#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x00000001
9994#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
9995#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x00000006
9996#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
9997#define SQ_WAVE_STATUS__TRAP__SHIFT 0x0000000e
9998#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
9999#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0x0000000f
10000#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
10001#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x00000007
10002#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
10003#define SQ_WAVE_STATUS__VALID__SHIFT 0x00000010
10004#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
10005#define SQ_WAVE_STATUS__VCCZ__SHIFT 0x0000000a
10006#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x00000018L
10007#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x00000003
10008#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0x000000ffL
10009#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x00000000
10010#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffffL
10011#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x00000000
10012#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0x000000ffL
10013#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x00000000
10014#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffffL
10015#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x00000000
10016#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000L
10017#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x0000001d
10018#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003f0000L
10019#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x00000010
10020#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x0000007fL
10021#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x00000000
10022#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffffL
10023#define SQ_WAVE_TTMP0__DATA__SHIFT 0x00000000
10024#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffffL
10025#define SQ_WAVE_TTMP10__DATA__SHIFT 0x00000000
10026#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffffL
10027#define SQ_WAVE_TTMP11__DATA__SHIFT 0x00000000
10028#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffffL
10029#define SQ_WAVE_TTMP1__DATA__SHIFT 0x00000000
10030#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffffL
10031#define SQ_WAVE_TTMP2__DATA__SHIFT 0x00000000
10032#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffffL
10033#define SQ_WAVE_TTMP3__DATA__SHIFT 0x00000000
10034#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffffL
10035#define SQ_WAVE_TTMP4__DATA__SHIFT 0x00000000
10036#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL
10037#define SQ_WAVE_TTMP5__DATA__SHIFT 0x00000000
10038#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffffL
10039#define SQ_WAVE_TTMP6__DATA__SHIFT 0x00000000
10040#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffffL
10041#define SQ_WAVE_TTMP7__DATA__SHIFT 0x00000000
10042#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffffL
10043#define SQ_WAVE_TTMP8__DATA__SHIFT 0x00000000
10044#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffffL
10045#define SQ_WAVE_TTMP9__DATA__SHIFT 0x00000000
10046#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80L
10047#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x00000007
10048#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007fL
10049#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x00000000
10050#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L
10051#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x0000001f
10052#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L
10053#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x0000001e
10054#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L
10055#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x0000001d
10056#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L
10057#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x0000001c
10058#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L
10059#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x0000001b
10060#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L
10061#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x0000001a
10062#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L
10063#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x00000019
10064#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L
10065#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x00000017
10066#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x01000000L
10067#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x00000018
10068#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L
10069#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x00000016
10070#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L
10071#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x00000014
10072#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x00200000L
10073#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x00000015
10074#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L
10075#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x00000013
10076#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L
10077#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x00000011
10078#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x00040000L
10079#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x00000012
10080#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L
10081#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x00000010
10082#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L
10083#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0x0000000e
10084#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x00008000L
10085#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0x0000000f
10086#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L
10087#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x0000000d
10088#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L
10089#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0x0000000c
10090#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L
10091#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0x0000000a
10092#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L
10093#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0x0000000b
10094#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L
10095#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x00000009
10096#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L
10097#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x00000007
10098#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L
10099#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x00000008
10100#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L
10101#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x00000006
10102#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L
10103#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x00000004
10104#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L
10105#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x00000005
10106#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L
10107#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x00000003
10108#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L
10109#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x00000001
10110#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L
10111#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x00000002
10112#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x00000001L
10113#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x00000000
10114#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L
10115#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x0000001f
10116#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L
10117#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x0000001e
10118#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L
10119#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x0000001d
10120#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L
10121#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x0000001c
10122#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L
10123#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x0000001b
10124#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L
10125#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x0000001a
10126#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L
10127#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x00000019
10128#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L
10129#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x00000018
10130#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L
10131#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x00000017
10132#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L
10133#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x00000016
10134#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L
10135#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x00000015
10136#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L
10137#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x00000014
10138#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L
10139#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x00000013
10140#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L
10141#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x00000012
10142#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L
10143#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x00000011
10144#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L
10145#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x00000010
10146#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L
10147#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x0000000f
10148#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L
10149#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x0000000e
10150#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L
10151#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x0000000d
10152#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L
10153#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x0000000c
10154#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L
10155#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x0000000b
10156#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L
10157#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x0000000a
10158#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L
10159#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x00000009
10160#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L
10161#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x00000008
10162#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L
10163#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x00000007
10164#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L
10165#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x00000006
10166#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L
10167#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x00000005
10168#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L
10169#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x00000004
10170#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L
10171#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x00000003
10172#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L
10173#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x00000002
10174#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L
10175#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x00000001
10176#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L
10177#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x00000000
10178#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L
10179#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x00000018
10180#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L
10181#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x00000017
10182#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L
10183#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x00000016
10184#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L
10185#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x00000015
10186#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L
10187#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x00000014
10188#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L
10189#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x00000013
10190#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L
10191#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x00000012
10192#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L
10193#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x00000011
10194#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L
10195#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x00000010
10196#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L
10197#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x0000000f
10198#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L
10199#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x0000000e
10200#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L
10201#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x0000000d
10202#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L
10203#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x0000000c
10204#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L
10205#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x0000000b
10206#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L
10207#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x0000000a
10208#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L
10209#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x00000009
10210#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L
10211#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x00000008
10212#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L
10213#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x00000007
10214#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L
10215#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x00000006
10216#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L
10217#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x00000005
10218#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L
10219#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x00000004
10220#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L
10221#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x00000003
10222#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L
10223#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x00000002
10224#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L
10225#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x00000001
10226#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L
10227#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x00000000
10228#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000L
10229#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x00000019
10230#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L
10231#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x0000001f
10232#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L
10233#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x0000001e
10234#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L
10235#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x00000002
10236#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L
10237#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x0000001b
10238#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L
10239#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x00000013
10240#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L
10241#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x00000012
10242#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L
10243#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x00000011
10244#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L
10245#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x00000010
10246#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L
10247#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0x0000000f
10248#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L
10249#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0x0000000e
10250#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L
10251#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0x0000000d
10252#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L
10253#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0x0000000c
10254#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L
10255#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0x0000000b
10256#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L
10257#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0x0000000a
10258#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L
10259#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x00000009
10260#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L
10261#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x00000008
10262#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L
10263#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x00000007
10264#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L
10265#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x00000006
10266#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L
10267#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x00000005
10268#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L
10269#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x00000004
10270#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L
10271#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x00000000
10272#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L
10273#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x00000014
10274#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L
10275#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x00000001
10276#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L
10277#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x00000003
10278#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L
10279#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x0000001d
10280#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L
10281#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x0000001c
10282#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L
10283#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x0000001a
10284#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L
10285#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x00000019
10286#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L
10287#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x00000018
10288#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L
10289#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x00000017
10290#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L
10291#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x00000016
10292#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L
10293#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x00000015
10294#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x000001c0L
10295#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x00000006
10296#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x0000003fL
10297#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000000
10298#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000L
10299#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x0000001f
10300#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L
10301#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e
10302#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x0c000000L
10303#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001a
10304#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x03ff0000L
10305#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000010
10306#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x0000f000L
10307#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x0000000c
10308#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000L
10309#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x0000001c
10310#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00000e00L
10311#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000009
10312#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00300000L
10313#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014
10314#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x0000007fL
10315#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000000
10316#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000L
10317#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x0000001c
10318#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0x0f000000L
10319#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x00000018
10320#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0x000f0000L
10321#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x00000010
10322#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L
10323#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f
10324#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x00007c00L
10325#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0x0000000a
10326#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00000380L
10327#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x00000007
10328#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x00800000L
10329#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x00000017
10330#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x00400000L
10331#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x00000016
10332#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x0000007fL
10333#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x00000000
10334#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x00008000L
10335#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000000f
10336#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x007f0000L
10337#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000010
10338#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000180L
10339#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000007
10340#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x00007e00L
10341#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000009
10342#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000L
10343#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x0000001a
10344#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x03800000L
10345#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000017
10346#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0x000000ffL
10347#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x00000000
10348#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x001fc000L
10349#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x0000000e
10350#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000L
10351#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001d
10352#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000L
10353#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x0000001f
10354#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00600000L
10355#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x00000015
10356#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00002000L
10357#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x0000000d
10358#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00001000L
10359#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x0000000c
10360#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x02000000L
10361#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000019
10362#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x04000000L
10363#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x0000001a
10364#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000L
10365#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x0000001e
10366#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00800000L
10367#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x00000017
10368#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x00000f00L
10369#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000008
10370#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x01000000L
10371#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x00000018
10372#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x08000000L
10373#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x0000001b
10374#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000L
10375#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x0000001c
10376#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10377#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10378#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10379#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10380#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL
10381#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000
10382#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L
10383#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a
10384#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
10385#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
10386#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
10387#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
10388#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
10389#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
10390#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10391#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10392#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10393#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10394#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL
10395#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000
10396#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L
10397#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a
10398#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
10399#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
10400#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
10401#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
10402#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
10403#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
10404#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10405#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10406#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10407#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10408#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
10409#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
10410#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
10411#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
10412#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
10413#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
10414#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10415#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10416#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10417#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10418#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
10419#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
10420#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L
10421#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a
10422#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL
10423#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000
10424#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL
10425#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000
10426#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL
10427#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000
10428#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
10429#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
10430#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL
10431#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000
10432#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
10433#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
10434#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
10435#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
10436#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
10437#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
10438#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
10439#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
10440#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
10441#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
10442#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
10443#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
10444#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
10445#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
10446#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
10447#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
10448#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001f0000L
10449#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x00000010
10450#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
10451#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x00000010
10452#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000e000L
10453#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0x0000000d
10454#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000L
10455#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x00000016
10456#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL
10457#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000
10458#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL
10459#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000
10460#define TA_DEBUG_DATA__DATA_MASK 0xffffffffL
10461#define TA_DEBUG_DATA__DATA__SHIFT 0x00000000
10462#define TA_DEBUG_INDEX__INDEX_MASK 0x0000001fL
10463#define TA_DEBUG_INDEX__INDEX__SHIFT 0x00000000
10464#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10465#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10466#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10467#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10468#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
10469#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
10470#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
10471#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
10472#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL
10473#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
10474#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L
10475#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10476#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
10477#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
10478#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
10479#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
10480#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
10481#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
10482#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L
10483#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
10484#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
10485#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
10486#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10487#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10488#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10489#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10490#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
10491#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
10492#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
10493#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
10494#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
10495#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
10496#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003fc00L
10497#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
10498#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
10499#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
10500#define TA_SCRATCH__SCRATCH_MASK 0xffffffffL
10501#define TA_SCRATCH__SCRATCH__SHIFT 0x00000000
10502#define TA_STATUS__AL_BUSY_MASK 0x40000000L
10503#define TA_STATUS__AL_BUSY__SHIFT 0x0000001e
10504#define TA_STATUS__BUSY_MASK 0x80000000L
10505#define TA_STATUS__BUSY__SHIFT 0x0000001f
10506#define TA_STATUS__FA_BUSY_MASK 0x20000000L
10507#define TA_STATUS__FA_BUSY__SHIFT 0x0000001d
10508#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
10509#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x00000015
10510#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
10511#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x00000014
10512#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
10513#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x00000016
10514#define TA_STATUS__FG_BUSY_MASK 0x02000000L
10515#define TA_STATUS__FG_BUSY__SHIFT 0x00000019
10516#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
10517#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0x0000000d
10518#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
10519#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0x0000000c
10520#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
10521#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0x0000000e
10522#define TA_STATUS__FL_BUSY_MASK 0x08000000L
10523#define TA_STATUS__FL_BUSY__SHIFT 0x0000001b
10524#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
10525#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x00000011
10526#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
10527#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x00000010
10528#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
10529#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x00000012
10530#define TA_STATUS__IN_BUSY_MASK 0x01000000L
10531#define TA_STATUS__IN_BUSY__SHIFT 0x00000018
10532#define TA_STATUS__LA_BUSY_MASK 0x04000000L
10533#define TA_STATUS__LA_BUSY__SHIFT 0x0000001a
10534#define TA_STATUS__TA_BUSY_MASK 0x10000000L
10535#define TA_STATUS__TA_BUSY__SHIFT 0x0000001c
10536#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
10537#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
10538#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL
10539#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000
10540#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
10541#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
10542#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
10543#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
10544#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
10545#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
10546#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
10547#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
10548#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
10549#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
10550#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
10551#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
10552#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
10553#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
10554#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
10555#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
10556#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000fL
10557#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x00000000
10558#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10559#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10560#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10561#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10562#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L
10563#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018
10564#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L
10565#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c
10566#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
10567#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
10568#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
10569#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10570#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
10571#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
10572#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
10573#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
10574#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
10575#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
10576#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
10577#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
10578#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
10579#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
10580#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10581#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10582#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10583#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10584#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L
10585#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018
10586#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L
10587#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c
10588#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
10589#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
10590#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
10591#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10592#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
10593#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
10594#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
10595#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
10596#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
10597#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
10598#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
10599#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
10600#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
10601#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
10602#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10603#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10604#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10605#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10606#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
10607#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
10608#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
10609#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
10610#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
10611#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
10612#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10613#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10614#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10615#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10616#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
10617#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
10618#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
10619#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
10620#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
10621#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
10622#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
10623#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
10624#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL
10625#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000
10626#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
10627#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
10628#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
10629#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
10630#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
10631#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
10632#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
10633#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
10634#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
10635#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
10636#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
10637#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
10638#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
10639#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
10640#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
10641#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
10642#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
10643#define TCC_CTRL__CACHE_SIZE__SHIFT 0x00000000
10644#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000f0000L
10645#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010
10646#define TCC_CTRL__RATE_MASK 0x0000000cL
10647#define TCC_CTRL__RATE__SHIFT 0x00000002
10648#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000f000L
10649#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0x0000000c
10650#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x00100000L
10651#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x00000014
10652#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000f0L
10653#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x00000004
10654#define TCC_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L
10655#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010
10656#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL
10657#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000
10658#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10659#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10660#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10661#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10662#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L
10663#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018
10664#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L
10665#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c
10666#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
10667#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
10668#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
10669#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10670#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
10671#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
10672#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
10673#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
10674#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
10675#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
10676#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
10677#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
10678#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
10679#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
10680#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10681#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10682#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10683#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10684#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L
10685#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018
10686#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L
10687#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c
10688#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
10689#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
10690#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
10691#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10692#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
10693#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
10694#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
10695#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
10696#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
10697#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
10698#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
10699#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
10700#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
10701#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
10702#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10703#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10704#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10705#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10706#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
10707#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
10708#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
10709#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
10710#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
10711#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
10712#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10713#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10714#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10715#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10716#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
10717#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
10718#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
10719#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
10720#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
10721#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
10722#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00ff0000L
10723#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x00000010
10724#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000ffffL
10725#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x00000000
10726#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000L
10727#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x00000018
10728#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
10729#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x00000000
10730#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001feL
10731#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x00000001
10732#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
10733#define TCI_STATUS__TCI_BUSY__SHIFT 0x00000000
10734#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001c0L
10735#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x00000006
10736#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
10737#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x00000004
10738#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000fL
10739#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x00000000
10740#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
10741#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x00000009
10742#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
10743#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x00000008
10744#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
10745#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x00000018
10746#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
10747#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x00000000
10748#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
10749#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x00000010
10750#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000fL
10751#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x00000000
10752#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000f0L
10753#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x00000004
10754#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000f00L
10755#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x00000008
10756#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000f000L
10757#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0x0000000c
10758#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000f0000L
10759#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x00000010
10760#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00f00000L
10761#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x00000014
10762#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0f000000L
10763#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x00000018
10764#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000L
10765#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x0000001c
10766#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000fL
10767#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x00000000
10768#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000f0L
10769#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x00000004
10770#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000f00L
10771#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x00000008
10772#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000f000L
10773#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0x0000000c
10774#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000f0000L
10775#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x00000010
10776#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00f00000L
10777#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x00000014
10778#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0f000000L
10779#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x00000018
10780#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000L
10781#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x0000001c
10782#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
10783#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x0000001c
10784#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
10785#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x00000005
10786#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L
10787#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x00000004
10788#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0fc00000L
10789#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x00000016
10790#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001f8000L
10791#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0x0000000f
10792#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
10793#define TCP_CNTL__FORCE_HIT__SHIFT 0x00000000
10794#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
10795#define TCP_CNTL__FORCE_MISS__SHIFT 0x00000001
10796#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L
10797#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x0000001d
10798#define TCP_CNTL__L1_SIZE_MASK 0x0000000cL
10799#define TCP_CNTL__L1_SIZE__SHIFT 0x00000002
10800#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003ffL
10801#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x00000000
10802#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007f0000L
10803#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x00000010
10804#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000L
10805#define TCP_CREDIT__TD_CREDIT__SHIFT 0x0000001d
10806#define TCP_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L
10807#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010
10808#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL
10809#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000
10810#define TCP_INVALIDATE__START_MASK 0x00000001L
10811#define TCP_INVALIDATE__START__SHIFT 0x00000000
10812#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10813#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10814#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10815#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10816#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
10817#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
10818#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
10819#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
10820#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
10821#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
10822#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
10823#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10824#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
10825#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
10826#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
10827#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
10828#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
10829#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
10830#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
10831#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
10832#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
10833#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
10834#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10835#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10836#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10837#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10838#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L
10839#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c
10840#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L
10841#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018
10842#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
10843#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
10844#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
10845#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10846#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
10847#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
10848#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
10849#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
10850#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
10851#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
10852#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
10853#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
10854#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
10855#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
10856#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10857#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10858#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10859#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10860#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
10861#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
10862#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
10863#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
10864#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
10865#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
10866#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10867#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10868#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10869#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10870#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
10871#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
10872#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
10873#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
10874#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
10875#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
10876#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
10877#define TCP_STATUS__TCP_BUSY__SHIFT 0x00000000
10878#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
10879#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
10880#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL
10881#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000
10882#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
10883#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
10884#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
10885#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
10886#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
10887#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
10888#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
10889#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
10890#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
10891#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
10892#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
10893#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
10894#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
10895#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
10896#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
10897#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
10898#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
10899#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x00000014
10900#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
10901#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x00000009
10902#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
10903#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x00000013
10904#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
10905#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x00000010
10906#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
10907#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x00000012
10908#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
10909#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0x0000000b
10910#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
10911#define TD_CNTL__PAD_STALL_EN__SHIFT 0x00000008
10912#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
10913#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0x0000000f
10914#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
10915#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x00000000
10916#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
10917#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x00000004
10918#define TD_DEBUG_DATA__DATA_MASK 0x00ffffffL
10919#define TD_DEBUG_DATA__DATA__SHIFT 0x00000000
10920#define TD_DEBUG_INDEX__INDEX_MASK 0x0000001fL
10921#define TD_DEBUG_INDEX__INDEX__SHIFT 0x00000000
10922#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
10923#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
10924#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
10925#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
10926#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
10927#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
10928#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
10929#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
10930#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL
10931#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
10932#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L
10933#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
10934#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
10935#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
10936#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
10937#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
10938#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
10939#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
10940#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L
10941#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
10942#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
10943#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
10944#define TD_SCRATCH__SCRATCH_MASK 0xffffffffL
10945#define TD_SCRATCH__SCRATCH__SHIFT 0x00000000
10946#define TD_STATUS__BUSY_MASK 0x80000000L
10947#define TD_STATUS__BUSY__SHIFT 0x0000001f
10948#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L
10949#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010
10950#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L
10951#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014
10952#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L
10953#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018
10954#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L
10955#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c
10956#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000c0L
10957#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x00000006
10958#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
10959#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x00000000
10960#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
10961#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0x0000000b
10962#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001f0000L
10963#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x00000010
10964#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
10965#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0x0000000c
10966#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
10967#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0x0000000d
10968#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
10969#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x00000009
10970#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
10971#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x00000005
10972#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
10973#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000
10974#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
10975#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x00000007
10976#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
10977#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x00000008
10978#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
10979#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000002
10980#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
10981#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000001
10982#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
10983#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x00000006
10984#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
10985#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000003
10986#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
10987#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x00000009
10988#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
10989#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x00000004
10990#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
10991#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000005
10992#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000003fL
10993#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000
10994#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x00000040L
10995#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x00000006
10996#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL
10997#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000
10998#define VGT_DEBUG_REG0__cm_busy_MASK 0x00008000L
10999#define VGT_DEBUG_REG0__cm_busy__SHIFT 0x0000000f
11000#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x00200000L
11001#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x00000015
11002#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x04000000L
11003#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a
11004#define VGT_DEBUG_REG0__frmt_busy_MASK 0x00020000L
11005#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x00000011
11006#define VGT_DEBUG_REG0__gog_busy_MASK 0x00010000L
11007#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x00000010
11008#define VGT_DEBUG_REG0__gs_busy_MASK 0x00001000L
11009#define VGT_DEBUG_REG0__gs_busy__SHIFT 0x0000000c
11010#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x08000000L
11011#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x0000001b
11012#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x00800000L
11013#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x00000017
11014#define VGT_DEBUG_REG0__pi_busy_MASK 0x00000100L
11015#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x00000008
11016#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x00000400L
11017#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0x0000000a
11018#define VGT_DEBUG_REG0__rcm_busy_MASK 0x00002000L
11019#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0x0000000d
11020#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L
11021#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018
11022#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L
11023#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d
11024#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000L
11025#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x0000001e
11026#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000L
11027#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x0000001f
11028#define VGT_DEBUG_REG0__SPARE10_MASK 0x00040000L
11029#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x00000012
11030#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000L
11031#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x0000001c
11032#define VGT_DEBUG_REG0__SPARE2_MASK 0x02000000L
11033#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x00000019
11034#define VGT_DEBUG_REG0__SPARE3_MASK 0x00100000L
11035#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x00000014
11036#define VGT_DEBUG_REG0__SPARE4_MASK 0x00000080L
11037#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x00000007
11038#define VGT_DEBUG_REG0__SPARE5_MASK 0x00000040L
11039#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x00000006
11040#define VGT_DEBUG_REG0__SPARE6_MASK 0x00000020L
11041#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x00000005
11042#define VGT_DEBUG_REG0__SPARE7_MASK 0x00000010L
11043#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x00000004
11044#define VGT_DEBUG_REG0__SPARE8_MASK 0x00000008L
11045#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x00000003
11046#define VGT_DEBUG_REG0__SPARE9_MASK 0x00000002L
11047#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x00000001
11048#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x00400000L
11049#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x00000016
11050#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x00080000L
11051#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x00000013
11052#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x00000800L
11053#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0x0000000b
11054#define VGT_DEBUG_REG0__tm_busy_MASK 0x00004000L
11055#define VGT_DEBUG_REG0__tm_busy__SHIFT 0x0000000e
11056#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00000001L
11057#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x00000000
11058#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00000004L
11059#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x00000002
11060#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x00000200L
11061#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x00000009
11062#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x00000020L
11063#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x00000005
11064#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x00000040L
11065#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x00000006
11066#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000L
11067#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x00000017
11068#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x007fe000L
11069#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0x0000000d
11070#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x0000001fL
11071#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x00000000
11072#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x00000180L
11073#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x00000007
11074#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x00001000L
11075#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x00000800L
11076#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0x0000000b
11077#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0x0000000c
11078#define VGT_DEBUG_REG10__SPARE2_MASK 0x00000600L
11079#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x00000009
11080#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x00001000L
11081#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0x0000000c
11082#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x00000800L
11083#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0x0000000b
11084#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x00000400L
11085#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0x0000000a
11086#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x00100000L
11087#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x00000014
11088#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x00000008L
11089#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x00000003
11090#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x08000000L
11091#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x0000001b
11092#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x00000200L
11093#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x00000009
11094#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000L
11095#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x0000001e
11096#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x00200000L
11097#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x00000015
11098#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x00010000L
11099#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x00000010
11100#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x00080000L
11101#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x00000013
11102#define VGT_DEBUG_REG11__hold_eswave_MASK 0x00000100L
11103#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x00000008
11104#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000L
11105#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x0000001f
11106#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000L
11107#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x0000001d
11108#define VGT_DEBUG_REG11__SPARE0_MASK 0x00040000L
11109#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x00000012
11110#define VGT_DEBUG_REG11__SPARE1_MASK 0x00000020L
11111#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x00000005
11112#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x00000080L
11113#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x00000007
11114#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x00000040L
11115#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x00000006
11116#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x00000001L
11117#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x00000000
11118#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x00000002L
11119#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x00000001
11120#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x00000004L
11121#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x00000002
11122#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x00020000L
11123#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x00000011
11124#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x01000000L
11125#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x00000018
11126#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x00400000L
11127#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x00000016
11128#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x00800000L
11129#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x00000017
11130#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x00008000L
11131#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0x0000000f
11132#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x00004000L
11133#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0x0000000e
11134#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x00000010L
11135#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x00000004
11136#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000L
11137#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x0000001c
11138#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x02000000L
11139#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x00000019
11140#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x04000000L
11141#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x0000001a
11142#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x00002000L
11143#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0x0000000d
11144#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x00000007L
11145#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x00000000
11146#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x00000038L
11147#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x00000003
11148#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x000001c0L
11149#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x00000006
11150#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0x00000e00L
11151#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x00000009
11152#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x00007000L
11153#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0x0000000c
11154#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x00038000L
11155#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0x0000000f
11156#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x001c0000L
11157#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x00000012
11158#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0x00e00000L
11159#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x00000015
11160#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x07000000L
11161#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x00000018
11162#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000L
11163#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x0000001b
11164#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000L
11165#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x0000001e
11166#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000L
11167#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x0000001f
11168#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000L
11169#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x0000001b
11170#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x01000000L
11171#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x00000018
11172#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x00800000L
11173#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x00000017
11174#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00400000L
11175#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000016
11176#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x00000007L
11177#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x00000000
11178#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x00000038L
11179#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x00000003
11180#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x000001c0L
11181#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x00000006
11182#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0x00000e00L
11183#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x00000009
11184#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x00007000L
11185#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0x0000000c
11186#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x00038000L
11187#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0x0000000f
11188#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x003c0000L
11189#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x00000012
11190#define VGT_DEBUG_REG13__SPARE0_MASK 0x04000000L
11191#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x0000001a
11192#define VGT_DEBUG_REG13__SPARE1_MASK 0x02000000L
11193#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x00000019
11194#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x00000400L
11195#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0x0000000a
11196#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x00000010L
11197#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x00000004
11198#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000L
11199#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x0000001d
11200#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x00000020L
11201#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x00000005
11202#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x00000800L
11203#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0x0000000b
11204#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x08000000L
11205#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x0000001b
11206#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x00200000L
11207#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x00000015
11208#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x04000000L
11209#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x0000001a
11210#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x00000040L
11211#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000006
11212#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000L
11213#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x0000001e
11214#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000L
11215#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x0000001c
11216#define VGT_DEBUG_REG14__SPARE2_MASK 0x001ff000L
11217#define VGT_DEBUG_REG14__SPARE2__SHIFT 0x0000000c
11218#define VGT_DEBUG_REG14__SPARE3_MASK 0x0000000fL
11219#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x00000000
11220#define VGT_DEBUG_REG14__SPARE8_MASK 0x00000180L
11221#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x00000007
11222#define VGT_DEBUG_REG14__SPARE_MASK 0x01c00000L
11223#define VGT_DEBUG_REG14__SPARE__SHIFT 0x00000016
11224#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000L
11225#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f
11226#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x02000000L
11227#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000019
11228#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x00000200L
11229#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x00000009
11230#define VGT_DEBUG_REG15__active_sm_q_MASK 0x000003e0L
11231#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x00000005
11232#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x00000001L
11233#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x00000000
11234#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0x000f8000L
11235#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0x0000000f
11236#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x00000002L
11237#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x00000001
11238#define VGT_DEBUG_REG15__counters_full_MASK 0x00000010L
11239#define VGT_DEBUG_REG15__counters_full__SHIFT 0x00000004
11240#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x00007c00L
11241#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0x0000000a
11242#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000L
11243#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x0000001c
11244#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x00000004L
11245#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x00000002
11246#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x00000008L
11247#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x00000003
11248#define VGT_DEBUG_REG15__SPARE25_MASK 0x03f00000L
11249#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x00000014
11250#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000L
11251#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x0000001d
11252#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0x0c000000L
11253#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x0000001a
11254#define VGT_DEBUG_REG16__gog_busy_MASK 0x00000001L
11255#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x00000000
11256#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0x0e000000L
11257#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x00000019
11258#define VGT_DEBUG_REG16__gog_state_q_MASK 0x0000000eL
11259#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x00000001
11260#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x00000800L
11261#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0x0000000b
11262#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x00080000L
11263#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x00000013
11264#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x00020000L
11265#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x00000011
11266#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x00002000L
11267#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0x0000000d
11268#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000L
11269#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x0000001c
11270#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000L
11271#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x0000001f
11272#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000L
11273#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x0000001e
11274#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x00100000L
11275#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x00000014
11276#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x00010000L
11277#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x00000010
11278#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x00004000L
11279#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0x0000000e
11280#define VGT_DEBUG_REG16__r0_rtr_MASK 0x00000010L
11281#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x00000004
11282#define VGT_DEBUG_REG16__r1_rtr_MASK 0x00000020L
11283#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x00000005
11284#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x00000040L
11285#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x00000006
11286#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x00000200L
11287#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x00000009
11288#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x00000100L
11289#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x00000008
11290#define VGT_DEBUG_REG16__r2_rtr_MASK 0x00000400L
11291#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0x0000000a
11292#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x00000080L
11293#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x00000007
11294#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x00001000L
11295#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0x0000000c
11296#define VGT_DEBUG_REG16__send_event_q_MASK 0x00400000L
11297#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x00000016
11298#define VGT_DEBUG_REG16__SPARE24_MASK 0x01800000L
11299#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x00000017
11300#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x00200000L
11301#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x00000015
11302#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x00040000L
11303#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x00000012
11304#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x00008000L
11305#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0x0000000f
11306#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x01000000L
11307#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x00000018
11308#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000L
11309#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x0000001d
11310#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000L
11311#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x00000012
11312#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x0003f000L
11313#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0x0000000c
11314#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0x00000fc0L
11315#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x00000006
11316#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x0000003fL
11317#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x00000000
11318#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000L
11319#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x0000001d
11320#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x00800000L
11321#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x00000017
11322#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x00400000L
11323#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x00000016
11324#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x00000001L
11325#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x00000000
11326#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x08000000L
11327#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x0000001b
11328#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000L
11329#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x0000001c
11330#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x00000700L
11331#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x00000008
11332#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x00040000L
11333#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x00000012
11334#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x00002000L
11335#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0x0000000d
11336#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x00020000L
11337#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x00000011
11338#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x00004000L
11339#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0x0000000e
11340#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x00010000L
11341#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x00000010
11342#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x00008000L
11343#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0x0000000f
11344#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x00100000L
11345#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x00000014
11346#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x00001000L
11347#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0x0000000c
11348#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x00200000L
11349#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x00000015
11350#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x00000040L
11351#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x00000006
11352#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x00000080L
11353#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x00000007
11354#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x00000002L
11355#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x00000001
11356#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x00000010L
11357#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x00000004
11358#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x00000004L
11359#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x00000002
11360#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x00000020L
11361#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x00000005
11362#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x00080000L
11363#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x00000013
11364#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x07000000L
11365#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x00000018
11366#define VGT_DEBUG_REG18__valid_indices_MASK 0x00000800L
11367#define VGT_DEBUG_REG18__valid_indices__SHIFT 0x0000000b
11368#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x00000008L
11369#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x00000003
11370#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x00080000L
11371#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x00000013
11372#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x00040000L
11373#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x00000012
11374#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x00010000L
11375#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x00000010
11376#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x00020000L
11377#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x00000011
11378#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x03f00000L
11379#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x00000014
11380#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000L
11381#define VGT_DEBUG_REG19__filter_event__SHIFT 0x0000001f
11382#define VGT_DEBUG_REG19__hold_prim_MASK 0x00000800L
11383#define VGT_DEBUG_REG19__hold_prim__SHIFT 0x0000000b
11384#define VGT_DEBUG_REG19__new_packet_q_MASK 0x00008000L
11385#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0x0000000f
11386#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000L
11387#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x0000001e
11388#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000L
11389#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x0000001c
11390#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x00000020L
11391#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x00000005
11392#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x00000010L
11393#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x00000004
11394#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x00000400L
11395#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0x0000000a
11396#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x00000004L
11397#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x00000002
11398#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x00000008L
11399#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x00000003
11400#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x00000001L
11401#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x00000000
11402#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x00000002L
11403#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x00000001
11404#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x00000100L
11405#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x00000008
11406#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x00000200L
11407#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x00000009
11408#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x00000080L
11409#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x00000007
11410#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x00000040L
11411#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x00000006
11412#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x00004000L
11413#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0x0000000e
11414#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x08000000L
11415#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000001b
11416#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x04000000L
11417#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000001a
11418#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x00001000L
11419#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0x0000000c
11420#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x00002000L
11421#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0x0000000d
11422#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000L
11423#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x0000001c
11424#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000L
11425#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x0000001e
11426#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x08000000L
11427#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x0000001b
11428#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000L
11429#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x0000001d
11430#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000L
11431#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x0000001f
11432#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x04000000L
11433#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x0000001a
11434#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x00001000L
11435#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0x0000000c
11436#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x00004000L
11437#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0x0000000e
11438#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x00000400L
11439#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0x0000000a
11440#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00100000L
11441#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000014
11442#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00400000L
11443#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000016
11444#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x00002000L
11445#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0x0000000d
11446#define VGT_DEBUG_REG1__SPARE0_MASK 0x00000200L
11447#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x00000009
11448#define VGT_DEBUG_REG1__SPARE10_MASK 0x00200000L
11449#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x00000015
11450#define VGT_DEBUG_REG1__SPARE11_MASK 0x00080000L
11451#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x00000013
11452#define VGT_DEBUG_REG1__SPARE12_MASK 0x00020000L
11453#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x00000011
11454#define VGT_DEBUG_REG1__SPARE1_MASK 0x00000100L
11455#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x00000008
11456#define VGT_DEBUG_REG1__SPARE23_MASK 0x00800000L
11457#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x00000017
11458#define VGT_DEBUG_REG1__SPARE25_MASK 0x02000000L
11459#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x00000019
11460#define VGT_DEBUG_REG1__SPARE2_MASK 0x00000080L
11461#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x00000007
11462#define VGT_DEBUG_REG1__SPARE3_MASK 0x00000040L
11463#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x00000006
11464#define VGT_DEBUG_REG1__SPARE4_MASK 0x00000020L
11465#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x00000005
11466#define VGT_DEBUG_REG1__SPARE5_MASK 0x00000010L
11467#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x00000004
11468#define VGT_DEBUG_REG1__SPARE6_MASK 0x00000008L
11469#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x00000003
11470#define VGT_DEBUG_REG1__SPARE7_MASK 0x00000004L
11471#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x00000002
11472#define VGT_DEBUG_REG1__SPARE8_MASK 0x00000002L
11473#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x00000001
11474#define VGT_DEBUG_REG1__SPARE9_MASK 0x00000001L
11475#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x00000000
11476#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00008000L
11477#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000f
11478#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x01000000L
11479#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000018
11480#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00010000L
11481#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000010
11482#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00040000L
11483#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000012
11484#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x00000800L
11485#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0x0000000b
11486#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x003c0000L
11487#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x00000012
11488#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000L
11489#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x00000016
11490#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000L
11491#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x0000001e
11492#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00010000L
11493#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000010
11494#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0x0000ffffL
11495#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x00000000
11496#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000L
11497#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x0000001f
11498#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000L
11499#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x0000001d
11500#define VGT_DEBUG_REG20__SPARE17_MASK 0x00020000L
11501#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x00000011
11502#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x01000000L
11503#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x00000018
11504#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000L
11505#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x0000001e
11506#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x04000000L
11507#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x0000001a
11508#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x00008000L
11509#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0x0000000f
11510#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x00002000L
11511#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0x0000000d
11512#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x00000002L
11513#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x00000001
11514#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x00000080L
11515#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x00000007
11516#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x00010000L
11517#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x00000010
11518#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x00001000L
11519#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0x0000000c
11520#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x00100000L
11521#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x00000014
11522#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x00200000L
11523#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x00000015
11524#define VGT_DEBUG_REG21__null_r2_q_MASK 0x08000000L
11525#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x0000001b
11526#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x00000001L
11527#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x00000000
11528#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x00000040L
11529#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x00000006
11530#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000L
11531#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x0000001c
11532#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000L
11533#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x0000001f
11534#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000L
11535#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x0000001d
11536#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x00000004L
11537#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x00000002
11538#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x00000100L
11539#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x00000008
11540#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x00000008L
11541#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x00000003
11542#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x00000200L
11543#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x00000009
11544#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x00000010L
11545#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x00000004
11546#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x00000400L
11547#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0x0000000a
11548#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0x000e0000L
11549#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x00000011
11550#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x00400000L
11551#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x00000016
11552#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x02000000L
11553#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x00000019
11554#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x00000020L
11555#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x00000005
11556#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x00000800L
11557#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0x0000000b
11558#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x00800000L
11559#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x00000017
11560#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x00004000L
11561#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0x0000000e
11562#define VGT_DEBUG_REG22__cm_state16_MASK 0x00000003L
11563#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x00000000
11564#define VGT_DEBUG_REG22__cm_state17_MASK 0x0000000cL
11565#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x00000002
11566#define VGT_DEBUG_REG22__cm_state18_MASK 0x00000030L
11567#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x00000004
11568#define VGT_DEBUG_REG22__cm_state19_MASK 0x000000c0L
11569#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x00000006
11570#define VGT_DEBUG_REG22__cm_state20_MASK 0x00000300L
11571#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x00000008
11572#define VGT_DEBUG_REG22__cm_state21_MASK 0x00000c00L
11573#define VGT_DEBUG_REG22__cm_state21__SHIFT 0x0000000a
11574#define VGT_DEBUG_REG22__cm_state22_MASK 0x00003000L
11575#define VGT_DEBUG_REG22__cm_state22__SHIFT 0x0000000c
11576#define VGT_DEBUG_REG22__cm_state23_MASK 0x0000c000L
11577#define VGT_DEBUG_REG22__cm_state23__SHIFT 0x0000000e
11578#define VGT_DEBUG_REG22__cm_state24_MASK 0x00030000L
11579#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x00000010
11580#define VGT_DEBUG_REG22__cm_state25_MASK 0x000c0000L
11581#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x00000012
11582#define VGT_DEBUG_REG22__cm_state26_MASK 0x00300000L
11583#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x00000014
11584#define VGT_DEBUG_REG22__cm_state27_MASK 0x00c00000L
11585#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x00000016
11586#define VGT_DEBUG_REG22__cm_state28_MASK 0x03000000L
11587#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x00000018
11588#define VGT_DEBUG_REG22__cm_state29_MASK 0x0c000000L
11589#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x0000001a
11590#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000L
11591#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x0000001c
11592#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000L
11593#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x0000001e
11594#define VGT_DEBUG_REG23__frmt_busy_MASK 0x00000001L
11595#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x00000000
11596#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x00018000L
11597#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0x0000000f
11598#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x00001000L
11599#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0x0000000c
11600#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x00000200L
11601#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x00000009
11602#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x00000400L
11603#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0x0000000a
11604#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x00000010L
11605#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x00000004
11606#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x00000008L
11607#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x00000003
11608#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0x00e00000L
11609#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x00000015
11610#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x00000004L
11611#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x00000002
11612#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x00000002L
11613#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x00000001
11614#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000L
11615#define VGT_DEBUG_REG23__SPARE__SHIFT 0x00000018
11616#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x00004000L
11617#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0x0000000e
11618#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x00002000L
11619#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0x0000000d
11620#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x00000800L
11621#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0x0000000b
11622#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x00000100L
11623#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x00000008
11624#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x00000080L
11625#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x00000007
11626#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x00000040L
11627#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x00000006
11628#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x00000020L
11629#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x00000005
11630#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x001e0000L
11631#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x00000011
11632#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0x00ffffffL
11633#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x00000000
11634#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x03000000L
11635#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x00000018
11636#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000L
11637#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x0000001a
11638#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000L
11639#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x0000001a
11640#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000L
11641#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x0000001f
11642#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000L
11643#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x0000001e
11644#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL
11645#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x00000000
11646#define VGT_DEBUG_REG26__cm_state0_MASK 0x00000003L
11647#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x00000000
11648#define VGT_DEBUG_REG26__cm_state10_MASK 0x00300000L
11649#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x00000014
11650#define VGT_DEBUG_REG26__cm_state11_MASK 0x00c00000L
11651#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x00000016
11652#define VGT_DEBUG_REG26__cm_state12_MASK 0x03000000L
11653#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x00000018
11654#define VGT_DEBUG_REG26__cm_state13_MASK 0x0c000000L
11655#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x0000001a
11656#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000L
11657#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x0000001c
11658#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000L
11659#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x0000001e
11660#define VGT_DEBUG_REG26__cm_state1_MASK 0x0000000cL
11661#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x00000002
11662#define VGT_DEBUG_REG26__cm_state2_MASK 0x00000030L
11663#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x00000004
11664#define VGT_DEBUG_REG26__cm_state3_MASK 0x000000c0L
11665#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x00000006
11666#define VGT_DEBUG_REG26__cm_state4_MASK 0x00000300L
11667#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x00000008
11668#define VGT_DEBUG_REG26__cm_state5_MASK 0x00000c00L
11669#define VGT_DEBUG_REG26__cm_state5__SHIFT 0x0000000a
11670#define VGT_DEBUG_REG26__cm_state6_MASK 0x00003000L
11671#define VGT_DEBUG_REG26__cm_state6__SHIFT 0x0000000c
11672#define VGT_DEBUG_REG26__cm_state7_MASK 0x0000c000L
11673#define VGT_DEBUG_REG26__cm_state7__SHIFT 0x0000000e
11674#define VGT_DEBUG_REG26__cm_state8_MASK 0x00030000L
11675#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x00000010
11676#define VGT_DEBUG_REG26__cm_state9_MASK 0x000c0000L
11677#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x00000012
11678#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x00000800L
11679#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0x0000000b
11680#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x00000400L
11681#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0x0000000a
11682#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L
11683#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013
11684#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x00000002L
11685#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x00000001
11686#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x00000020L
11687#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x00000005
11688#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x00010000L
11689#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x00000010
11690#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x00020000L
11691#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x00000011
11692#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x00008000L
11693#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0x0000000f
11694#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000L
11695#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x00000014
11696#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x00004000L
11697#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0x0000000e
11698#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x00003000L
11699#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0x0000000c
11700#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x00000300L
11701#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x00000008
11702#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x00000080L
11703#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x00000007
11704#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x00040000L
11705#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x00000012
11706#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000L
11707#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x0000001f
11708#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x00000001L
11709#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x00000000
11710#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x00000010L
11711#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x00000004
11712#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x00000004L
11713#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x00000002
11714#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x00000040L
11715#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x00000006
11716#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x00000008L
11717#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x00000003
11718#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x00800000L
11719#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x00000017
11720#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x00400000L
11721#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x00000016
11722#define VGT_DEBUG_REG28__con_state_q_MASK 0x0000000fL
11723#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x00000000
11724#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x00010000L
11725#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x00000010
11726#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x00040000L
11727#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012
11728#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x00100000L
11729#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x00000014
11730#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x00080000L
11731#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x00000013
11732#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x00020000L
11733#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x00000011
11734#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x01000000L
11735#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x00000018
11736#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L
11737#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015
11738#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x00004000L
11739#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0x0000000e
11740#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x00008000L
11741#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0x0000000f
11742#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x00000200L
11743#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x00000009
11744#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x00001000L
11745#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0x0000000c
11746#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x00000100L
11747#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x00000008
11748#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x00000800L
11749#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0x0000000b
11750#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x00000400L
11751#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0x0000000a
11752#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000L
11753#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x0000001e
11754#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x08000000L
11755#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x0000001b
11756#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000L
11757#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x0000001c
11758#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x02000000L
11759#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x00000019
11760#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x04000000L
11761#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x0000001a
11762#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000L
11763#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x0000001d
11764#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x00002000L
11765#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0x0000000d
11766#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L
11767#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006
11768#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x00000080L
11769#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x00000007
11770#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L
11771#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x00000005
11772#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x00000010L
11773#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x00000004
11774#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000L
11775#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x0000001f
11776#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x00800000L
11777#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x00000017
11778#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x00400000L
11779#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x00000016
11780#define VGT_DEBUG_REG29__con_state_q_MASK 0x0000000fL
11781#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x00000000
11782#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x00010000L
11783#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x00000010
11784#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x00040000L
11785#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012
11786#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x00100000L
11787#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x00000014
11788#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x00080000L
11789#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x00000013
11790#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x00020000L
11791#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x00000011
11792#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x01000000L
11793#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x00000018
11794#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L
11795#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015
11796#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x00004000L
11797#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0x0000000e
11798#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x00008000L
11799#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0x0000000f
11800#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x00000200L
11801#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x00000009
11802#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x00001000L
11803#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0x0000000c
11804#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x00000100L
11805#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x00000008
11806#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x00000800L
11807#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0x0000000b
11808#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x00000400L
11809#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0x0000000a
11810#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000L
11811#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x0000001e
11812#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x08000000L
11813#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x0000001b
11814#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000L
11815#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x0000001c
11816#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x02000000L
11817#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x00000019
11818#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x04000000L
11819#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x0000001a
11820#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000L
11821#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x0000001d
11822#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x00002000L
11823#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0x0000000d
11824#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L
11825#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006
11826#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x00000080L
11827#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x00000007
11828#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x00000020L
11829#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x00000005
11830#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x00000010L
11831#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x00000004
11832#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000L
11833#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x0000001f
11834#define VGT_DEBUG_REG2__grpModBusy_MASK 0x00000080L
11835#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x00000007
11836#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x00000001L
11837#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x00000000
11838#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x00001000L
11839#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0x0000000c
11840#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x00040000L
11841#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x00000012
11842#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x00000002L
11843#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x00000001
11844#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x00000040L
11845#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x00000006
11846#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x00002000L
11847#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0x0000000d
11848#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x00080000L
11849#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x00000013
11850#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x00000400L
11851#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0x0000000a
11852#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x00010000L
11853#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x00000010
11854#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x00000800L
11855#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0x0000000b
11856#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x00020000L
11857#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x00000011
11858#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x08000000L
11859#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x0000001b
11860#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x04000000L
11861#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x0000001a
11862#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x00000100L
11863#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x00000008
11864#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x00004000L
11865#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0x0000000e
11866#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x00000008L
11867#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x00000003
11868#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x00000200L
11869#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x00000009
11870#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x00008000L
11871#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0x0000000f
11872#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x00000020L
11873#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x00000005
11874#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000L
11875#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x0000001c
11876#define VGT_DEBUG_REG2__p0_dr_MASK 0x00400000L
11877#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x00000016
11878#define VGT_DEBUG_REG2__p0_rtr_MASK 0x00100000L
11879#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x00000014
11880#define VGT_DEBUG_REG2__p0_rts_MASK 0x01000000L
11881#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x00000018
11882#define VGT_DEBUG_REG2__p1_dr_MASK 0x00800000L
11883#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x00000017
11884#define VGT_DEBUG_REG2__p1_rtr_MASK 0x00200000L
11885#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x00000015
11886#define VGT_DEBUG_REG2__p1_rts_MASK 0x02000000L
11887#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x00000019
11888#define VGT_DEBUG_REG2__SPARE_MASK 0xffffffffL
11889#define VGT_DEBUG_REG2__SPARE__SHIFT 0x00000000
11890#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x00000010L
11891#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x00000004
11892#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x00000004L
11893#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x00000002
11894#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x01000000L
11895#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x00000018
11896#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x00000008L
11897#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x00000003
11898#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x08000000L
11899#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x0000001b
11900#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x04000000L
11901#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x0000001a
11902#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x02000000L
11903#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x00000019
11904#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x00080000L
11905#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x00000013
11906#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x00000001L
11907#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x00000000
11908#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x00000010L
11909#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x00000004
11910#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x00000002L
11911#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x00000001
11912#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x00000020L
11913#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x00000005
11914#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x00000040L
11915#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x00000006
11916#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x00000004L
11917#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x00000002
11918#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x00000080L
11919#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x00000007
11920#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000L
11921#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x0000001e
11922#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000L
11923#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x0000001f
11924#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x00070000L
11925#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x00000010
11926#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0x00f00000L
11927#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x00000014
11928#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000L
11929#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x0000001c
11930#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x00000200L
11931#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x00000009
11932#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x00000100L
11933#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x00000008
11934#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x00000400L
11935#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0x0000000a
11936#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x00000800L
11937#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0x0000000b
11938#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x00001000L
11939#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0x0000000c
11940#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x00002000L
11941#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0x0000000d
11942#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x00004000L
11943#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0x0000000e
11944#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x00008000L
11945#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0x0000000f
11946#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000L
11947#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x0000001f
11948#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000L
11949#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x0000001e
11950#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x00400000L
11951#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x00000016
11952#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x00800000L
11953#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x00000017
11954#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x00100000L
11955#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x00000014
11956#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x00200000L
11957#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x00000015
11958#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x02000000L
11959#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x00000019
11960#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000L
11961#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x0000001c
11962#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x04000000L
11963#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x0000001a
11964#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000L
11965#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x0000001d
11966#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x01000000L
11967#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x00000018
11968#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x08000000L
11969#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x0000001b
11970#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x00000001L
11971#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x00000000
11972#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x00000002L
11973#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x00000001
11974#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x00000008L
11975#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x00000003
11976#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x00000004L
11977#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x00000002
11978#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x00000020L
11979#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x00000005
11980#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x00002000L
11981#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0x0000000d
11982#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x00000010L
11983#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x00000004
11984#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x00001000L
11985#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0x0000000c
11986#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x00000080L
11987#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x00000007
11988#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x00008000L
11989#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0x0000000f
11990#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x00000040L
11991#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x00000006
11992#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x00004000L
11993#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0x0000000e
11994#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x00000200L
11995#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x00000009
11996#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x00020000L
11997#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x00000011
11998#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x00000100L
11999#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x00000008
12000#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x00010000L
12001#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x00000010
12002#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x00000800L
12003#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0x0000000b
12004#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x00080000L
12005#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x00000013
12006#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x00000400L
12007#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0x0000000a
12008#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x00040000L
12009#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x00000012
12010#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x00000100L
12011#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x00000008
12012#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x00000080L
12013#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x00000007
12014#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x08000000L
12015#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x0000001b
12016#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x00000400L
12017#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0x0000000a
12018#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x00000200L
12019#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x00000009
12020#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x00000001L
12021#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x00000000
12022#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x01000000L
12023#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x00000018
12024#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x02000000L
12025#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x00000019
12026#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x00000010L
12027#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x00000004
12028#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x00000004L
12029#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x00000002
12030#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x00000040L
12031#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x00000006
12032#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x00000800L
12033#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0x0000000b
12034#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x00000020L
12035#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x00000005
12036#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x00000008L
12037#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x00000003
12038#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x00000002L
12039#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x00000001
12040#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x04000000L
12041#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x0000001a
12042#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x00020000L
12043#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x00000011
12044#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x00010000L
12045#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x00000010
12046#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x00100000L
12047#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x00000014
12048#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x00040000L
12049#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x00000012
12050#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x00400000L
12051#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x00000016
12052#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x00200000L
12053#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x00000015
12054#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x00080000L
12055#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x00000013
12056#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x00800000L
12057#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x00000017
12058#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x00008000L
12059#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0x0000000f
12060#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x00004000L
12061#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0x0000000e
12062#define VGT_DEBUG_REG32__SPARE_MASK 0x80000000L
12063#define VGT_DEBUG_REG32__SPARE__SHIFT 0x0000001f
12064#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L
12065#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0x0000000c
12066#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x00040000L
12067#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x00000012
12068#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x00010000L
12069#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x00000010
12070#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000L
12071#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x0000001f
12072#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000L
12073#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x0000001e
12074#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000L
12075#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x0000001d
12076#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x00080000L
12077#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x00000013
12078#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x00020000L
12079#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x00000011
12080#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x00008000L
12081#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0x0000000f
12082#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x00100000L
12083#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x00000014
12084#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x00000001L
12085#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x00000000
12086#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x00000010L
12087#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x00000004
12088#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x00000004L
12089#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x00000002
12090#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x00001000L
12091#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0x0000000c
12092#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x00000008L
12093#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x00000003
12094#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x00000080L
12095#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x00000007
12096#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x00000100L
12097#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x00000008
12098#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x00000200L
12099#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x00000009
12100#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x00000800L
12101#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0x0000000b
12102#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x00000040L
12103#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x00000006
12104#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x00800000L
12105#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x00000017
12106#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x00000400L
12107#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0x0000000a
12108#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x00000020L
12109#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x00000005
12110#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x00400000L
12111#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x00000016
12112#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x00002000L
12113#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0x0000000d
12114#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x00000002L
12115#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x00000001
12116#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x00200000L
12117#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x00000015
12118#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000L
12119#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x0000001c
12120#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0x0c000000L
12121#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x0000001a
12122#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x03000000L
12123#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x00000018
12124#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x00004000L
12125#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0x0000000e
12126#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x00800000L
12127#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x00000017
12128#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x00400000L
12129#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x00000016
12130#define VGT_DEBUG_REG34__con_state_q_MASK 0x0000000fL
12131#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x00000000
12132#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x00010000L
12133#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x00000010
12134#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x00040000L
12135#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012
12136#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x00100000L
12137#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x00000014
12138#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x00080000L
12139#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x00000013
12140#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x00020000L
12141#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x00000011
12142#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x01000000L
12143#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x00000018
12144#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L
12145#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015
12146#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x00004000L
12147#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0x0000000e
12148#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x00008000L
12149#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0x0000000f
12150#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x00000200L
12151#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x00000009
12152#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x00001000L
12153#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0x0000000c
12154#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x00000100L
12155#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x00000008
12156#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x00000800L
12157#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0x0000000b
12158#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x00000400L
12159#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0x0000000a
12160#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000L
12161#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x0000001e
12162#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x08000000L
12163#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x0000001b
12164#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000L
12165#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x0000001c
12166#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x02000000L
12167#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x00000019
12168#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x04000000L
12169#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x0000001a
12170#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000L
12171#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x0000001d
12172#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x00002000L
12173#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0x0000000d
12174#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L
12175#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006
12176#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x00000080L
12177#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x00000007
12178#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x00000020L
12179#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x00000005
12180#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x00000010L
12181#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x00000004
12182#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000L
12183#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x0000001f
12184#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x00040000L
12185#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x00000012
12186#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000L
12187#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x0000001c
12188#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x00000800L
12189#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0x0000000b
12190#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x00080000L
12191#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x00000013
12192#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x00000001L
12193#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x00000000
12194#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x00000004L
12195#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x00000002
12196#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x00000002L
12197#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x00000001
12198#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x00000008L
12199#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x00000003
12200#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x08000000L
12201#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x0000001b
12202#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x0003f000L
12203#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0x0000000c
12204#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000L
12205#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x0000001f
12206#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x00000040L
12207#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x00000006
12208#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x07f00000L
12209#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x00000014
12210#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x00000080L
12211#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x00000007
12212#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x00000010L
12213#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x00000004
12214#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x00000020L
12215#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x00000005
12216#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x00000100L
12217#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x00000008
12218#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x00000200L
12219#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x00000009
12220#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000L
12221#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x0000001e
12222#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x00000400L
12223#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0x0000000a
12224#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000L
12225#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x0000001d
12226#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000L
12227#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x0000001a
12228#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x03fc0000L
12229#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x00000012
12230#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0x00000fffL
12231#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x00000000
12232#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x0003f000L
12233#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0x0000000c
12234#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000L
12235#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x00000018
12236#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000L
12237#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x0000001e
12238#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0x000000ffL
12239#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x00000000
12240#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0x00ffff00L
12241#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x00000008
12242#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000L
12243#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x0000001d
12244#define VGT_DEBUG_REG4__SPARE_MASK 0xffffffffL
12245#define VGT_DEBUG_REG4__SPARE__SHIFT 0x00000000
12246#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0x0000f800L
12247#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0x0000000b
12248#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0x000000f8L
12249#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x00000003
12250#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000L
12251#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x0000001b
12252#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0x00f80000L
12253#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x00000013
12254#define VGT_DEBUG_REG5__SPARE1_MASK 0x07000000L
12255#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x00000018
12256#define VGT_DEBUG_REG5__SPARE2_MASK 0x00070000L
12257#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x00000010
12258#define VGT_DEBUG_REG5__SPARE3_MASK 0x00000700L
12259#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x00000008
12260#define VGT_DEBUG_REG5__SPARE4_MASK 0x00000007L
12261#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x00000000
12262#define VGT_DEBUG_REG6__debug_BASE_MASK 0x0000ffffL
12263#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x00000000
12264#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000L
12265#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x00000010
12266#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x00000001L
12267#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x00000000
12268#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x00000002L
12269#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x00000001
12270#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x00000004L
12271#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x00000002
12272#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x00000008L
12273#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x00000003
12274#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x00000010L
12275#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x00000004
12276#define VGT_DEBUG_REG7__SPARE_MASK 0x0000ffe0L
12277#define VGT_DEBUG_REG7__SPARE__SHIFT 0x00000005
12278#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000L
12279#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x00000010
12280#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x00004000L
12281#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0x0000000e
12282#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x02000000L
12283#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x00000019
12284#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x00008000L
12285#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0x0000000f
12286#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x04000000L
12287#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x0000001a
12288#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x08000000L
12289#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x0000001b
12290#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x00020000L
12291#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x00000011
12292#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x00000020L
12293#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x00000005
12294#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x01000000L
12295#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x00000018
12296#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x00040000L
12297#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x00000012
12298#define VGT_DEBUG_REG8__r0_rtr_MASK 0x00000400L
12299#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0x0000000a
12300#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x00000004L
12301#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x00000002
12302#define VGT_DEBUG_REG8__r1_rtr_MASK 0x00000800L
12303#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0x0000000b
12304#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x00001000L
12305#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0x0000000c
12306#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x00800000L
12307#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x00000017
12308#define VGT_DEBUG_REG8__r2_rtr_MASK 0x00002000L
12309#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0x0000000d
12310#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x00000001L
12311#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x00000000
12312#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x00000002L
12313#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x00000001
12314#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x00000010L
12315#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x00000004
12316#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x00000008L
12317#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x00000003
12318#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000L
12319#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x0000001c
12320#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000L
12321#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x0000001d
12322#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000L
12323#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x0000001e
12324#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000L
12325#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x0000001f
12326#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x00200000L
12327#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x00000015
12328#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x00010000L
12329#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x00000010
12330#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x00100000L
12331#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x00000014
12332#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x00000040L
12333#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x00000006
12334#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x00000080L
12335#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x00000007
12336#define VGT_DEBUG_REG8__valid_r2_MASK 0x00000100L
12337#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x00000200L
12338#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x00000009
12339#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x00000008
12340#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x00400000L
12341#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x00000016
12342#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x00080000L
12343#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x00000013
12344#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x00000010L
12345#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x00000004
12346#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x00000020L
12347#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x00000005
12348#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x00000040L
12349#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x00000006
12350#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x02000000L
12351#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000019
12352#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x00000080L
12353#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x00000007
12354#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x00000008L
12355#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x00000003
12356#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x01000000L
12357#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x00000018
12358#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x00400000L
12359#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x00000016
12360#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x04000000L
12361#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x0000001a
12362#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x00040000L
12363#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x00000012
12364#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L
12365#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a
12366#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x0003f800L
12367#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0x0000000b
12368#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x00380000L
12369#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x00000013
12370#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x00000003L
12371#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x00000000
12372#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x00800000L
12373#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x00000017
12374#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000L
12375#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x0000001f
12376#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x00000200L
12377#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x00000009
12378#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x00000100L
12379#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x00000008
12380#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x08000000L
12381#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x0000001b
12382#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000L
12383#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x0000001e
12384#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x00000004L
12385#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x00000002
12386#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000L
12387#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x0000001d
12388#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000L
12389#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x0000001c
12390#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL
12391#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000
12392#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x000000ffL
12393#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x00000000
12394#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001ffL
12395#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x00000000
12396#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L
12397#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x00000008
12398#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
12399#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x00000004
12400#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
12401#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000
12402#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
12403#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x00000009
12404#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000c0L
12405#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x00000006
12406#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
12407#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0x0000000a
12408#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000cL
12409#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x00000002
12410#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffffL
12411#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x00000000
12412#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL
12413#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000
12414#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003fL
12415#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x00000000
12416#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffffL
12417#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x00000000
12418#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003fL
12419#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x00000000
12420#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000cL
12421#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x00000002
12422#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
12423#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x00000005
12424#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
12425#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000000
12426#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
12427#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x00000004
12428#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
12429#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x00000006
12430#define VGT_ENHANCE__MISC_MASK 0xffffffffL
12431#define VGT_ENHANCE__MISC__SHIFT 0x00000000
12432#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL
12433#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000
12434#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL
12435#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000
12436#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007ffL
12437#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x00000000
12438#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0fffffffL
12439#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x00000000
12440#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fc0000L
12441#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x00000012
12442#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL
12443#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000
12444#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
12445#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b
12446#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003fff00L
12447#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x00000008
12448#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
12449#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x00000007
12450#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0xffc00000L
12451#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x00000016
12452#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007fL
12453#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x00000000
12454#define VGT_GROUP_DECR__DECR_MASK 0x0000000fL
12455#define VGT_GROUP_DECR__DECR__SHIFT 0x00000000
12456#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000fL
12457#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x00000000
12458#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
12459#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x00000010
12460#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001fL
12461#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x00000000
12462#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
12463#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0x0000000e
12464#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
12465#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0x0000000f
12466#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
12467#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x00000003
12468#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
12469#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x00000000
12470#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
12471#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x00000001
12472#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
12473#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x00000002
12474#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00ff0000L
12475#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x00000010
12476#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000ff00L
12477#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x00000008
12478#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0f000000L
12479#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x00000018
12480#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000L
12481#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c
12482#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000fL
12483#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x00000000
12484#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000f0L
12485#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x00000004
12486#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000f00L
12487#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x00000008
12488#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L
12489#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c
12490#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000f0000L
12491#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x00000010
12492#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L
12493#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014
12494#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
12495#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x00000003
12496#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
12497#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x00000000
12498#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
12499#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x00000001
12500#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
12501#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x00000002
12502#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00ff0000L
12503#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x00000010
12504#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000ff00L
12505#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x00000008
12506#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0f000000L
12507#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x00000018
12508#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000L
12509#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c
12510#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000fL
12511#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x00000000
12512#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000f0L
12513#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x00000004
12514#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000f00L
12515#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x00000008
12516#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L
12517#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c
12518#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000f0000L
12519#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x00000010
12520#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L
12521#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014
12522#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001fcL
12523#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x00000002
12524#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
12525#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x00000000
12526#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007ffL
12527#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x00000000
12528#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L
12529#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0x0000000e
12530#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
12531#define VGT_GS_MODE__CUT_MODE__SHIFT 0x00000004
12532#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L
12533#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x00000010
12534#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
12535#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0x0000000d
12536#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
12537#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x00000013
12538#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L
12539#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0x0000000f
12540#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
12541#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0x0000000b
12542#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
12543#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x00000014
12544#define VGT_GS_MODE__MODE_MASK 0x00000007L
12545#define VGT_GS_MODE__MODE__SHIFT 0x00000000
12546#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
12547#define VGT_GS_MODE__ONCHIP__SHIFT 0x00000015
12548#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
12549#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x00000011
12550#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
12551#define VGT_GS_MODE__RESERVED_0__SHIFT 0x00000003
12552#define VGT_GS_MODE__RESERVED_1_MASK 0x000007c0L
12553#define VGT_GS_MODE__RESERVED_1__SHIFT 0x00000006
12554#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
12555#define VGT_GS_MODE__RESERVED_2__SHIFT 0x0000000c
12556#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
12557#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x00000012
12558#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003f00L
12559#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x00000008
12560#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003f0000L
12561#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x00000010
12562#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0fc00000L
12563#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x00000016
12564#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003fL
12565#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x00000000
12566#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
12567#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x0000001f
12568#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007ffL
12569#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x00000000
12570#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000fL
12571#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x00000000
12572#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001fL
12573#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x00000000
12574#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007fffL
12575#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x00000000
12576#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007fffL
12577#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x00000000
12578#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007fffL
12579#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x00000000
12580#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL
12581#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000
12582#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL
12583#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000
12584#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007fffL
12585#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x00000000
12586#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007fffL
12587#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x00000000
12588#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007fffL
12589#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x00000000
12590#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL
12591#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000
12592#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
12593#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x00000000
12594#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffffL
12595#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x00000000
12596#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffffL
12597#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x00000000
12598#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000ffL
12599#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x00000000
12600#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x0000007fL
12601#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x00000000
12602#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
12603#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x00000009
12604#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL
12605#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000
12606#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
12607#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000
12608#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffffL
12609#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000
12610#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffffL
12611#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x00000000
12612#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffffL
12613#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x00000000
12614#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
12615#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010
12616#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
12617#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000
12618#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L
12619#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008
12620#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000fc000L
12621#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0x0000000e
12622#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000ffL
12623#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x00000000
12624#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffffL
12625#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000
12626#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x00000003L
12627#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x00000000
12628#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffffL
12629#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000
12630#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
12631#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x00000000
12632#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffffL
12633#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000
12634#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffffL
12635#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x00000000
12636#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL
12637#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000
12638#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007fL
12639#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000
12640#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
12641#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x00000000
12642#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
12643#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
12644#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
12645#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
12646#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
12647#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
12648#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
12649#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
12650#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
12651#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
12652#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
12653#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
12654#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
12655#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
12656#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
12657#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
12658#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
12659#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
12660#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
12661#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
12662#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
12663#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
12664#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
12665#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
12666#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
12667#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
12668#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L
12669#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c
12670#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L
12671#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018
12672#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
12673#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
12674#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
12675#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
12676#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
12677#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
12678#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
12679#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
12680#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
12681#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
12682#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
12683#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
12684#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
12685#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
12686#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
12687#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
12688#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
12689#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
12690#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
12691#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
12692#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
12693#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
12694#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
12695#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
12696#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
12697#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
12698#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
12699#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
12700#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
12701#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
12702#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000ffL
12703#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x00000000
12704#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
12705#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x00000001
12706#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
12707#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x00000000
12708#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffffL
12709#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x00000000
12710#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL
12711#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000
12712#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
12713#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x00000000
12714#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L
12715#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x00000008
12716#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
12717#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x00000003
12718#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
12719#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x00000005
12720#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
12721#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x00000002
12722#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
12723#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x00000000
12724#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000c0L
12725#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x00000006
12726#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000fL
12727#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x00000000
12728#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000f0L
12729#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x00000004
12730#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000f00L
12731#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x00000008
12732#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000f000L
12733#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0x0000000c
12734#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffffL
12735#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x00000000
12736#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffffL
12737#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x00000000
12738#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffffL
12739#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x00000000
12740#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffffL
12741#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x00000000
12742#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffffL
12743#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x00000000
12744#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffffL
12745#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x00000000
12746#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffffL
12747#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x00000000
12748#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffffL
12749#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x00000000
12750#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffffL
12751#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x00000000
12752#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffffL
12753#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x00000000
12754#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffffL
12755#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x00000000
12756#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffffL
12757#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x00000000
12758#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
12759#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000f00L
12760#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x00000008
12761#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x00000004
12762#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
12763#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x00000000
12764#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
12765#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x00000001
12766#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
12767#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x00000002
12768#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
12769#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x00000003
12770#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
12771#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x0000001f
12772#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffffL
12773#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x00000000
12774#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffffL
12775#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x00000000
12776#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001ffL
12777#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x00000000
12778#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003ffL
12779#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x00000000
12780#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003ffL
12781#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x00000000
12782#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003ffL
12783#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x00000000
12784#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003ffL
12785#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x00000000
12786#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
12787#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x00000007
12788#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
12789#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x00000000
12790#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007eL
12791#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x00000001
12792#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffffL
12793#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x00000000
12794#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
12795#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x00000009
12796#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
12797#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0x0000000e
12798#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003c00L
12799#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0x0000000a
12800#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001cL
12801#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x00000002
12802#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L
12803#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0x0000000f
12804#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
12805#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x00000008
12806#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000e0L
12807#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x00000005
12808#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
12809#define VGT_TF_PARAM__TYPE__SHIFT 0x00000000
12810#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL
12811#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x00000000
12812#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000ffL
12813#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000
12814#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
12815#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x00000000
12816#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003ffL
12817#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000
12818#define WD_DEBUG_DATA__DATA_MASK 0xffffffffL
12819#define WD_DEBUG_DATA__DATA__SHIFT 0x00000000
12820
12821#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h
new file mode 100644
index 000000000000..dc4e5b93801d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h
@@ -0,0 +1,1274 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef GMC_6_0_D_H
24#define GMC_6_0_D_H
25
26#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28#define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29#define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
36#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x01AE
37#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x01BE
38#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x012E
39#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x013E
40#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x016E
41#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x017E
42#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0x00CD
43#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0x00DD
44#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0x00AD
45#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0x00BD
46#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x010D
47#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x011D
48#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x018D
49#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x019D
50#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x01AD
51#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x01BD
52#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x012D
53#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x013D
54#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x016D
55#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x017D
56#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0x00CC
57#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0x00DC
58#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0x00AC
59#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0x00BC
60#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x010C
61#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x011C
62#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x018C
63#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x019C
64#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x01AC
65#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x01BC
66#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x012C
67#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x013C
68#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x016C
69#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x017C
70#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0x00CB
71#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0x00DB
72#define ixMC_IO_DEBUG_CK_MISC_D0 0x00AB
73#define ixMC_IO_DEBUG_CK_MISC_D1 0x00BB
74#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x010B
75#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x011B
76#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x018B
77#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x019B
78#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x01AB
79#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x01BB
80#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x012B
81#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x013B
82#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x016B
83#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x017B
84#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0x00CF
85#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0x00DF
86#define ixMC_IO_DEBUG_CMD_MISC_D0 0x00AF
87#define ixMC_IO_DEBUG_CMD_MISC_D1 0x00BF
88#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0x00EF
89#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0x00FF
90#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x01CF
91#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x01DF
92#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x010F
93#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x011F
94#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x018F
95#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x019F
96#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x01AF
97#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x01BF
98#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x012F
99#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x013F
100#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x016F
101#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x017F
102#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x014F
103#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x015F
104#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0x00C8
105#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0x00D8
106#define ixMC_IO_DEBUG_DBI_MISC_D0 0x00A8
107#define ixMC_IO_DEBUG_DBI_MISC_D1 0x00B8
108#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0x00E8
109#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0x00F8
110#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x01C8
111#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x01D8
112#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x0108
113#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x0118
114#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x0148
115#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x0158
116#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x0188
117#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x0198
118#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x01A8
119#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x01B8
120#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x0128
121#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x0138
122#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x0168
123#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x0178
124#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x01CD
125#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x01DD
126#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x01CB
127#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x01DB
128#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x01CE
129#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x01DE
130#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x01CC
131#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x01DC
132#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x014B
133#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x015B
134#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0x00C1
135#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0x00D1
136#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0x00A1
137#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0x00B1
138#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0x00E1
139#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0x00F1
140#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x01C1
141#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x01D1
142#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x0101
143#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x0111
144#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x0141
145#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x0151
146#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x0181
147#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x0191
148#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x01A1
149#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x01B1
150#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x0121
151#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x0131
152#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x0161
153#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x0171
154#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0x00C0
155#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0x00D0
156#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0x00A0
157#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0x00B0
158#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0x00E0
159#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0x00F0
160#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x01C0
161#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x01D0
162#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x0100
163#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x0110
164#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x0140
165#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x0150
166#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x0180
167#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x0190
168#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x01A0
169#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x01B0
170#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x0120
171#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x0130
172#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x0160
173#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x0170
174#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x014C
175#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x015C
176#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0x00C3
177#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0x00D3
178#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0x00A3
179#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0x00B3
180#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0x00E3
181#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0x00F3
182#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x01C3
183#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x01D3
184#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x0103
185#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x0113
186#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x0143
187#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x0153
188#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x0183
189#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x0193
190#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x01A3
191#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x01B3
192#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x0123
193#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x0133
194#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x0163
195#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x0173
196#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0x00C2
197#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0x00D2
198#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0x00A2
199#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0x00B2
200#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0x00E2
201#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0x00F2
202#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x01C2
203#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x01D2
204#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x0102
205#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x0112
206#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x0142
207#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x0152
208#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x0182
209#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x0192
210#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x01A2
211#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x01B2
212#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x0122
213#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x0132
214#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x0162
215#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x0172
216#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x014D
217#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x015D
218#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0x00C5
219#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0x00D5
220#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0x00A5
221#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0x00B5
222#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0x00E5
223#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0x00F5
224#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x01C5
225#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x01D5
226#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x0105
227#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x0115
228#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x0145
229#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x0155
230#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x0185
231#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x0195
232#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x01A5
233#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x01B5
234#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x0125
235#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x0135
236#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x0165
237#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x0175
238#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0x00C4
239#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0x00D4
240#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0x00A4
241#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0x00B4
242#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0x00E4
243#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0x00F4
244#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x01C4
245#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x01D4
246#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x0104
247#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x0114
248#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x0144
249#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x0154
250#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x0184
251#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x0194
252#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x01A4
253#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x01B4
254#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x0124
255#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x0134
256#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x0164
257#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x0174
258#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x014E
259#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x015E
260#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0x00C7
261#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0x00D7
262#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0x00A7
263#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0x00B7
264#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0x00E7
265#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0x00F7
266#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x01C7
267#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x01D7
268#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x0107
269#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x0117
270#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x0147
271#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x0157
272#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x0187
273#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x0197
274#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x01A7
275#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x01B7
276#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x0127
277#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x0137
278#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x0167
279#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x0177
280#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0x00C6
281#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0x00D6
282#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0x00A6
283#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0x00B6
284#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0x00E6
285#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0x00F6
286#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x01C6
287#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x01D6
288#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x0106
289#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x0116
290#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x0146
291#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x0156
292#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x0186
293#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x0196
294#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x01A6
295#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x01B6
296#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x0126
297#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x0136
298#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x0166
299#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x0176
300#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0x00ED
301#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0x00FD
302#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0x00C9
303#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0x00D9
304#define ixMC_IO_DEBUG_EDC_MISC_D0 0x00A9
305#define ixMC_IO_DEBUG_EDC_MISC_D1 0x00B9
306#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0x00E9
307#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0x00F9
308#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0x00EC
309#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0x00FC
310#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x01C9
311#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x01D9
312#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0x00EB
313#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0x00FB
314#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x0109
315#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x0119
316#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x0149
317#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x0159
318#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x0189
319#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x0199
320#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x01A9
321#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x01B9
322#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x0129
323#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x0139
324#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x0169
325#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x0179
326#define ixMC_IO_DEBUG_UP_0 0x0000
327#define ixMC_IO_DEBUG_UP_100 0x0064
328#define ixMC_IO_DEBUG_UP_10 0x000A
329#define ixMC_IO_DEBUG_UP_101 0x0065
330#define ixMC_IO_DEBUG_UP_102 0x0066
331#define ixMC_IO_DEBUG_UP_103 0x0067
332#define ixMC_IO_DEBUG_UP_104 0x0068
333#define ixMC_IO_DEBUG_UP_105 0x0069
334#define ixMC_IO_DEBUG_UP_106 0x006A
335#define ixMC_IO_DEBUG_UP_107 0x006B
336#define ixMC_IO_DEBUG_UP_108 0x006C
337#define ixMC_IO_DEBUG_UP_109 0x006D
338#define ixMC_IO_DEBUG_UP_1 0x0001
339#define ixMC_IO_DEBUG_UP_110 0x006E
340#define ixMC_IO_DEBUG_UP_11 0x000B
341#define ixMC_IO_DEBUG_UP_111 0x006F
342#define ixMC_IO_DEBUG_UP_112 0x0070
343#define ixMC_IO_DEBUG_UP_113 0x0071
344#define ixMC_IO_DEBUG_UP_114 0x0072
345#define ixMC_IO_DEBUG_UP_115 0x0073
346#define ixMC_IO_DEBUG_UP_116 0x0074
347#define ixMC_IO_DEBUG_UP_117 0x0075
348#define ixMC_IO_DEBUG_UP_118 0x0076
349#define ixMC_IO_DEBUG_UP_119 0x0077
350#define ixMC_IO_DEBUG_UP_120 0x0078
351#define ixMC_IO_DEBUG_UP_12 0x000C
352#define ixMC_IO_DEBUG_UP_121 0x0079
353#define ixMC_IO_DEBUG_UP_122 0x007A
354#define ixMC_IO_DEBUG_UP_123 0x007B
355#define ixMC_IO_DEBUG_UP_124 0x007C
356#define ixMC_IO_DEBUG_UP_125 0x007D
357#define ixMC_IO_DEBUG_UP_126 0x007E
358#define ixMC_IO_DEBUG_UP_127 0x007F
359#define ixMC_IO_DEBUG_UP_128 0x0080
360#define ixMC_IO_DEBUG_UP_129 0x0081
361#define ixMC_IO_DEBUG_UP_130 0x0082
362#define ixMC_IO_DEBUG_UP_13 0x000D
363#define ixMC_IO_DEBUG_UP_131 0x0083
364#define ixMC_IO_DEBUG_UP_132 0x0084
365#define ixMC_IO_DEBUG_UP_133 0x0085
366#define ixMC_IO_DEBUG_UP_134 0x0086
367#define ixMC_IO_DEBUG_UP_135 0x0087
368#define ixMC_IO_DEBUG_UP_136 0x0088
369#define ixMC_IO_DEBUG_UP_137 0x0089
370#define ixMC_IO_DEBUG_UP_138 0x008A
371#define ixMC_IO_DEBUG_UP_139 0x008B
372#define ixMC_IO_DEBUG_UP_140 0x008C
373#define ixMC_IO_DEBUG_UP_14 0x000E
374#define ixMC_IO_DEBUG_UP_141 0x008D
375#define ixMC_IO_DEBUG_UP_142 0x008E
376#define ixMC_IO_DEBUG_UP_143 0x008F
377#define ixMC_IO_DEBUG_UP_144 0x0090
378#define ixMC_IO_DEBUG_UP_145 0x0091
379#define ixMC_IO_DEBUG_UP_146 0x0092
380#define ixMC_IO_DEBUG_UP_147 0x0093
381#define ixMC_IO_DEBUG_UP_148 0x0094
382#define ixMC_IO_DEBUG_UP_149 0x0095
383#define ixMC_IO_DEBUG_UP_150 0x0096
384#define ixMC_IO_DEBUG_UP_15 0x000F
385#define ixMC_IO_DEBUG_UP_151 0x0097
386#define ixMC_IO_DEBUG_UP_152 0x0098
387#define ixMC_IO_DEBUG_UP_153 0x0099
388#define ixMC_IO_DEBUG_UP_154 0x009A
389#define ixMC_IO_DEBUG_UP_155 0x009B
390#define ixMC_IO_DEBUG_UP_156 0x009C
391#define ixMC_IO_DEBUG_UP_157 0x009D
392#define ixMC_IO_DEBUG_UP_158 0x009E
393#define ixMC_IO_DEBUG_UP_159 0x009F
394#define ixMC_IO_DEBUG_UP_16 0x0010
395#define ixMC_IO_DEBUG_UP_17 0x0011
396#define ixMC_IO_DEBUG_UP_18 0x0012
397#define ixMC_IO_DEBUG_UP_19 0x0013
398#define ixMC_IO_DEBUG_UP_20 0x0014
399#define ixMC_IO_DEBUG_UP_2 0x0002
400#define ixMC_IO_DEBUG_UP_21 0x0015
401#define ixMC_IO_DEBUG_UP_22 0x0016
402#define ixMC_IO_DEBUG_UP_23 0x0017
403#define ixMC_IO_DEBUG_UP_24 0x0018
404#define ixMC_IO_DEBUG_UP_25 0x0019
405#define ixMC_IO_DEBUG_UP_26 0x001A
406#define ixMC_IO_DEBUG_UP_27 0x001B
407#define ixMC_IO_DEBUG_UP_28 0x001C
408#define ixMC_IO_DEBUG_UP_29 0x001D
409#define ixMC_IO_DEBUG_UP_30 0x001E
410#define ixMC_IO_DEBUG_UP_3 0x0003
411#define ixMC_IO_DEBUG_UP_31 0x001F
412#define ixMC_IO_DEBUG_UP_32 0x0020
413#define ixMC_IO_DEBUG_UP_33 0x0021
414#define ixMC_IO_DEBUG_UP_34 0x0022
415#define ixMC_IO_DEBUG_UP_35 0x0023
416#define ixMC_IO_DEBUG_UP_36 0x0024
417#define ixMC_IO_DEBUG_UP_37 0x0025
418#define ixMC_IO_DEBUG_UP_38 0x0026
419#define ixMC_IO_DEBUG_UP_39 0x0027
420#define ixMC_IO_DEBUG_UP_40 0x0028
421#define ixMC_IO_DEBUG_UP_4 0x0004
422#define ixMC_IO_DEBUG_UP_41 0x0029
423#define ixMC_IO_DEBUG_UP_42 0x002A
424#define ixMC_IO_DEBUG_UP_43 0x002B
425#define ixMC_IO_DEBUG_UP_44 0x002C
426#define ixMC_IO_DEBUG_UP_45 0x002D
427#define ixMC_IO_DEBUG_UP_46 0x002E
428#define ixMC_IO_DEBUG_UP_47 0x002F
429#define ixMC_IO_DEBUG_UP_48 0x0030
430#define ixMC_IO_DEBUG_UP_49 0x0031
431#define ixMC_IO_DEBUG_UP_50 0x0032
432#define ixMC_IO_DEBUG_UP_5 0x0005
433#define ixMC_IO_DEBUG_UP_51 0x0033
434#define ixMC_IO_DEBUG_UP_52 0x0034
435#define ixMC_IO_DEBUG_UP_53 0x0035
436#define ixMC_IO_DEBUG_UP_54 0x0036
437#define ixMC_IO_DEBUG_UP_55 0x0037
438#define ixMC_IO_DEBUG_UP_56 0x0038
439#define ixMC_IO_DEBUG_UP_57 0x0039
440#define ixMC_IO_DEBUG_UP_58 0x003A
441#define ixMC_IO_DEBUG_UP_59 0x003B
442#define ixMC_IO_DEBUG_UP_60 0x003C
443#define ixMC_IO_DEBUG_UP_6 0x0006
444#define ixMC_IO_DEBUG_UP_61 0x003D
445#define ixMC_IO_DEBUG_UP_62 0x003E
446#define ixMC_IO_DEBUG_UP_63 0x003F
447#define ixMC_IO_DEBUG_UP_64 0x0040
448#define ixMC_IO_DEBUG_UP_65 0x0041
449#define ixMC_IO_DEBUG_UP_66 0x0042
450#define ixMC_IO_DEBUG_UP_67 0x0043
451#define ixMC_IO_DEBUG_UP_68 0x0044
452#define ixMC_IO_DEBUG_UP_69 0x0045
453#define ixMC_IO_DEBUG_UP_70 0x0046
454#define ixMC_IO_DEBUG_UP_7 0x0007
455#define ixMC_IO_DEBUG_UP_71 0x0047
456#define ixMC_IO_DEBUG_UP_72 0x0048
457#define ixMC_IO_DEBUG_UP_73 0x0049
458#define ixMC_IO_DEBUG_UP_74 0x004A
459#define ixMC_IO_DEBUG_UP_75 0x004B
460#define ixMC_IO_DEBUG_UP_76 0x004C
461#define ixMC_IO_DEBUG_UP_77 0x004D
462#define ixMC_IO_DEBUG_UP_78 0x004E
463#define ixMC_IO_DEBUG_UP_79 0x004F
464#define ixMC_IO_DEBUG_UP_80 0x0050
465#define ixMC_IO_DEBUG_UP_8 0x0008
466#define ixMC_IO_DEBUG_UP_81 0x0051
467#define ixMC_IO_DEBUG_UP_82 0x0052
468#define ixMC_IO_DEBUG_UP_83 0x0053
469#define ixMC_IO_DEBUG_UP_84 0x0054
470#define ixMC_IO_DEBUG_UP_85 0x0055
471#define ixMC_IO_DEBUG_UP_86 0x0056
472#define ixMC_IO_DEBUG_UP_87 0x0057
473#define ixMC_IO_DEBUG_UP_88 0x0058
474#define ixMC_IO_DEBUG_UP_89 0x0059
475#define ixMC_IO_DEBUG_UP_90 0x005A
476#define ixMC_IO_DEBUG_UP_9 0x0009
477#define ixMC_IO_DEBUG_UP_91 0x005B
478#define ixMC_IO_DEBUG_UP_92 0x005C
479#define ixMC_IO_DEBUG_UP_93 0x005D
480#define ixMC_IO_DEBUG_UP_94 0x005E
481#define ixMC_IO_DEBUG_UP_95 0x005F
482#define ixMC_IO_DEBUG_UP_96 0x0060
483#define ixMC_IO_DEBUG_UP_97 0x0061
484#define ixMC_IO_DEBUG_UP_98 0x0062
485#define ixMC_IO_DEBUG_UP_99 0x0063
486#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x01EA
487#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x01FA
488#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x01E1
489#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x01F1
490#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x01E0
491#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x01F0
492#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x01E2
493#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x01F2
494#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x01EC
495#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x01FC
496#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x01E9
497#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x01F9
498#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x01EB
499#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x01FB
500#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x01E3
501#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x01F3
502#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x01E5
503#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x01F5
504#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x01E7
505#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x01F7
506#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x01E8
507#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x01F8
508#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x01E4
509#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x01F4
510#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x01E6
511#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x01F6
512#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0x00CA
513#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0x00DA
514#define ixMC_IO_DEBUG_WCK_MISC_D0 0x00AA
515#define ixMC_IO_DEBUG_WCK_MISC_D1 0x00BA
516#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0x00EA
517#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0x00FA
518#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x01CA
519#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x01DA
520#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x010A
521#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x011A
522#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x014A
523#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x015A
524#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x018A
525#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x019A
526#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x01AA
527#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x01BA
528#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x012A
529#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x013A
530#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x016A
531#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x017A
532#define ixMC_TSM_DEBUG_BCNT0 0x0003
533#define ixMC_TSM_DEBUG_BCNT10 0x000D
534#define ixMC_TSM_DEBUG_BCNT1 0x0004
535#define ixMC_TSM_DEBUG_BCNT2 0x0005
536#define ixMC_TSM_DEBUG_BCNT3 0x0006
537#define ixMC_TSM_DEBUG_BCNT4 0x0007
538#define ixMC_TSM_DEBUG_BCNT5 0x0008
539#define ixMC_TSM_DEBUG_BCNT6 0x0009
540#define ixMC_TSM_DEBUG_BCNT7 0x000A
541#define ixMC_TSM_DEBUG_BCNT8 0x000B
542#define ixMC_TSM_DEBUG_BCNT9 0x000C
543#define ixMC_TSM_DEBUG_BKPT 0x0013
544#define ixMC_TSM_DEBUG_FLAG 0x0001
545#define ixMC_TSM_DEBUG_GCNT 0x0000
546#define ixMC_TSM_DEBUG_MISC 0x0002
547#define ixMC_TSM_DEBUG_ST01 0x0010
548#define ixMC_TSM_DEBUG_ST23 0x0011
549#define ixMC_TSM_DEBUG_ST45 0x0012
550#define mmATC_ATS_CNTL 0x0CC9
551#define mmATC_ATS_DEBUG 0x0CCA
552#define mmATC_ATS_DEFAULT_PAGE_CNTL 0x0CD1
553#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0CD0
554#define mmATC_ATS_FAULT_CNTL 0x0CCD
555#define mmATC_ATS_FAULT_DEBUG 0x0CCB
556#define mmATC_ATS_FAULT_STATUS_ADDR 0x0CCF
557#define mmATC_ATS_FAULT_STATUS_INFO 0x0CCE
558#define mmATC_ATS_STATUS 0x0CCC
559#define mmATC_L1_ADDRESS_OFFSET 0x0CDD
560#define mmATC_L1_CNTL 0x0CDC
561#define mmATC_L1RD_DEBUG_TLB 0x0CDE
562#define mmATC_L1RD_STATUS 0x0CE0
563#define mmATC_L1WR_DEBUG_TLB 0x0CDF
564#define mmATC_L1WR_STATUS 0x0CE1
565#define mmATC_L2_CNTL 0x0CD5
566#define mmATC_L2_DEBUG 0x0CD7
567#define mmATC_MISC_CG 0x0CD4
568#define mmATC_VM_APERTURE0_CNTL 0x0CC4
569#define mmATC_VM_APERTURE0_CNTL2 0x0CC6
570#define mmATC_VM_APERTURE0_HIGH_ADDR 0x0CC2
571#define mmATC_VM_APERTURE0_LOW_ADDR 0x0CC0
572#define mmATC_VM_APERTURE1_CNTL 0x0CC5
573#define mmATC_VM_APERTURE1_CNTL2 0x0CC7
574#define mmATC_VM_APERTURE1_HIGH_ADDR 0x0CC3
575#define mmATC_VM_APERTURE1_LOW_ADDR 0x0CC1
576#define mmATC_VMID0_PASID_MAPPING 0x0CE7
577#define mmATC_VMID10_PASID_MAPPING 0x0CF1
578#define mmATC_VMID11_PASID_MAPPING 0x0CF2
579#define mmATC_VMID12_PASID_MAPPING 0x0CF3
580#define mmATC_VMID13_PASID_MAPPING 0x0CF4
581#define mmATC_VMID14_PASID_MAPPING 0x0CF5
582#define mmATC_VMID15_PASID_MAPPING 0x0CF6
583#define mmATC_VMID1_PASID_MAPPING 0x0CE8
584#define mmATC_VMID2_PASID_MAPPING 0x0CE9
585#define mmATC_VMID3_PASID_MAPPING 0x0CEA
586#define mmATC_VMID4_PASID_MAPPING 0x0CEB
587#define mmATC_VMID5_PASID_MAPPING 0x0CEC
588#define mmATC_VMID6_PASID_MAPPING 0x0CED
589#define mmATC_VMID7_PASID_MAPPING 0x0CEE
590#define mmATC_VMID8_PASID_MAPPING 0x0CEF
591#define mmATC_VMID9_PASID_MAPPING 0x0CF0
592#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0CE6
593#define mmCC_MC_MAX_CHANNEL 0x096E
594#define mmDLL_CNTL 0x0AE9
595#define mmGMCON_DEBUG 0x0D5F
596#define mmGMCON_MISC 0x0D43
597#define mmGMCON_MISC2 0x0D44
598#define mmGMCON_MISC3 0x0D51
599#define mmGMCON_PERF_MON_CNTL0 0x0D4A
600#define mmGMCON_PERF_MON_CNTL1 0x0D4B
601#define mmGMCON_PERF_MON_RSLT0 0x0D4C
602#define mmGMCON_PERF_MON_RSLT1 0x0D4D
603#define mmGMCON_PGFSM_CONFIG 0x0D4E
604#define mmGMCON_PGFSM_READ 0x0D50
605#define mmGMCON_PGFSM_WRITE 0x0D4F
606#define mmGMCON_RENG_EXECUTE 0x0D42
607#define mmGMCON_RENG_RAM_DATA 0x0D41
608#define mmGMCON_RENG_RAM_INDEX 0x0D40
609#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0D48
610#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0D49
611#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0x0D45
612#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0x0D46
613#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0x0D47
614#define mmMC_ARB_ADDR_HASH 0x09DC
615#define mmMC_ARB_AGE_RD 0x09E9
616#define mmMC_ARB_AGE_WR 0x09EA
617#define mmMC_ARB_BANKMAP 0x09D7
618#define mmMC_ARB_BURST_TIME 0x0A02
619#define mmMC_ARB_CAC_CNTL 0x09D4
620#define mmMC_ARB_CG 0x09FA
621#define mmMC_ARB_DRAM_TIMING 0x09DD
622#define mmMC_ARB_DRAM_TIMING_1 0x09FC
623#define mmMC_ARB_DRAM_TIMING2 0x09DE
624#define mmMC_ARB_DRAM_TIMING2_1 0x09FF
625#define mmMC_ARB_FED_CNTL 0x09C1
626#define mmMC_ARB_GDEC_RD_CNTL 0x09EE
627#define mmMC_ARB_GDEC_WR_CNTL 0x09EF
628#define mmMC_ARB_GECC2 0x09C9
629#define mmMC_ARB_GECC2_CLI 0x09CA
630#define mmMC_ARB_GECC2_DEBUG 0x09C4
631#define mmMC_ARB_GECC2_DEBUG2 0x09C5
632#define mmMC_ARB_GECC2_MISC 0x09C3
633#define mmMC_ARB_GECC2_STATUS 0x09C2
634#define mmMC_ARB_LAZY0_RD 0x09E5
635#define mmMC_ARB_LAZY0_WR 0x09E6
636#define mmMC_ARB_LAZY1_RD 0x09E7
637#define mmMC_ARB_LAZY1_WR 0x09E8
638#define mmMC_ARB_LM_RD 0x09F0
639#define mmMC_ARB_LM_WR 0x09F1
640#define mmMC_ARB_MINCLKS 0x09DA
641#define mmMC_ARB_MISC 0x09D6
642#define mmMC_ARB_MISC2 0x09D5
643#define mmMC_ARB_PM_CNTL 0x09ED
644#define mmMC_ARB_POP 0x09D9
645#define mmMC_ARB_RAMCFG 0x09D8
646#define mmMC_ARB_REMREQ 0x09F2
647#define mmMC_ARB_REPLAY 0x09F3
648#define mmMC_ARB_RET_CREDITS_RD 0x09F4
649#define mmMC_ARB_RET_CREDITS_WR 0x09F5
650#define mmMC_ARB_RFSH_CNTL 0x09EB
651#define mmMC_ARB_RFSH_RATE 0x09EC
652#define mmMC_ARB_RTT_CNTL0 0x09D0
653#define mmMC_ARB_RTT_CNTL1 0x09D1
654#define mmMC_ARB_RTT_CNTL2 0x09D2
655#define mmMC_ARB_RTT_DATA 0x09CF
656#define mmMC_ARB_RTT_DEBUG 0x09D3
657#define mmMC_ARB_SQM_CNTL 0x09DB
658#define mmMC_ARB_TM_CNTL_RD 0x09E3
659#define mmMC_ARB_TM_CNTL_WR 0x09E4
660#define mmMC_ARB_WCDR 0x09FB
661#define mmMC_ARB_WCDR_2 0x09CE
662#define mmMC_ARB_WTM_CNTL_RD 0x09DF
663#define mmMC_ARB_WTM_CNTL_WR 0x09E0
664#define mmMC_ARB_WTM_GRPWT_RD 0x09E1
665#define mmMC_ARB_WTM_GRPWT_WR 0x09E2
666#define mmMC_BIST_AUTO_CNTL 0x0A06
667#define mmMC_BIST_CMD_CNTL 0x0A8E
668#define mmMC_BIST_CMP_CNTL 0x0A8D
669#define mmMC_BIST_CMP_CNTL_2 0x0AB6
670#define mmMC_BIST_CNTL 0x0A05
671#define mmMC_BIST_DATA_MASK 0x0A12
672#define mmMC_BIST_DATA_WORD0 0x0A0A
673#define mmMC_BIST_DATA_WORD1 0x0A0B
674#define mmMC_BIST_DATA_WORD2 0x0A0C
675#define mmMC_BIST_DATA_WORD3 0x0A0D
676#define mmMC_BIST_DATA_WORD4 0x0A0E
677#define mmMC_BIST_DATA_WORD5 0x0A0F
678#define mmMC_BIST_DATA_WORD6 0x0A10
679#define mmMC_BIST_DATA_WORD7 0x0A11
680#define mmMC_BIST_DIR_CNTL 0x0A07
681#define mmMC_BIST_EADDR 0x0A09
682#define mmMC_BIST_MISMATCH_ADDR 0x0A13
683#define mmMC_BIST_RDATA_EDC 0x0A1D
684#define mmMC_BIST_RDATA_MASK 0x0A1C
685#define mmMC_BIST_RDATA_WORD0 0x0A14
686#define mmMC_BIST_RDATA_WORD1 0x0A15
687#define mmMC_BIST_RDATA_WORD2 0x0A16
688#define mmMC_BIST_RDATA_WORD3 0x0A17
689#define mmMC_BIST_RDATA_WORD4 0x0A18
690#define mmMC_BIST_RDATA_WORD5 0x0A19
691#define mmMC_BIST_RDATA_WORD6 0x0A1A
692#define mmMC_BIST_RDATA_WORD7 0x0A1B
693#define mmMC_BIST_SADDR 0x0A08
694#define mmMC_CG_CONFIG 0x096F
695#define mmMC_CG_CONFIG_MCD 0x0829
696#define mmMC_CG_DATAPORT 0x0A21
697#define mmMC_CITF_CNTL 0x0970
698#define mmMC_CITF_CREDITS_ARB_RD 0x0972
699#define mmMC_CITF_CREDITS_ARB_WR 0x0973
700#define mmMC_CITF_CREDITS_VM 0x0971
701#define mmMC_CITF_CREDITS_XBAR 0x0989
702#define mmMC_CITF_DAGB_CNTL 0x0974
703#define mmMC_CITF_DAGB_DLY 0x0977
704#define mmMC_CITF_INT_CREDITS 0x0975
705#define mmMC_CITF_INT_CREDITS_WR 0x097D
706#define mmMC_CITF_MISC_RD_CG 0x0992
707#define mmMC_CITF_MISC_VM_CG 0x0994
708#define mmMC_CITF_MISC_WR_CG 0x0993
709#define mmMC_CITF_PERF_MON_CNTL2 0x098E
710#define mmMC_CITF_PERF_MON_RSLT2 0x0991
711#define mmMC_CITF_REMREQ 0x097A
712#define mmMC_CITF_RET_MODE 0x0976
713#define mmMC_CITF_WTM_RD_CNTL 0x097F
714#define mmMC_CITF_WTM_WR_CNTL 0x0980
715#define mmMC_CITF_XTRA_ENABLE 0x096D
716#define mmMC_CONFIG 0x0800
717#define mmMC_CONFIG_MCD 0x0828
718#define mmMC_HUB_MISC_DBG 0x0831
719#define mmMC_HUB_MISC_FRAMING 0x0834
720#define mmMC_HUB_MISC_HUB_CG 0x082E
721#define mmMC_HUB_MISC_IDLE_STATUS 0x0847
722#define mmMC_HUB_MISC_OVERRIDE 0x0833
723#define mmMC_HUB_MISC_POWER 0x082D
724#define mmMC_HUB_MISC_SIP_CG 0x0830
725#define mmMC_HUB_MISC_STATUS 0x0832
726#define mmMC_HUB_MISC_VM_CG 0x082F
727#define mmMC_HUB_RDREQ_CNTL 0x083B
728#define mmMC_HUB_RDREQ_CREDITS 0x0844
729#define mmMC_HUB_RDREQ_CREDITS2 0x0845
730#define mmMC_HUB_RDREQ_DMIF 0x0863
731#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x0848
732#define mmMC_HUB_RDREQ_GBL0 0x0856
733#define mmMC_HUB_RDREQ_GBL1 0x0857
734#define mmMC_HUB_RDREQ_HDP 0x085B
735#define mmMC_HUB_RDREQ_MCDW 0x0851
736#define mmMC_HUB_RDREQ_MCDX 0x0852
737#define mmMC_HUB_RDREQ_MCDY 0x0853
738#define mmMC_HUB_RDREQ_MCDZ 0x0854
739#define mmMC_HUB_RDREQ_MCIF 0x0864
740#define mmMC_HUB_RDREQ_RLC 0x085D
741#define mmMC_HUB_RDREQ_SEM 0x085E
742#define mmMC_HUB_RDREQ_SIP 0x0855
743#define mmMC_HUB_RDREQ_SMU 0x0858
744#define mmMC_HUB_RDREQ_STATUS 0x0839
745#define mmMC_HUB_RDREQ_UMC 0x0860
746#define mmMC_HUB_RDREQ_UVD 0x0861
747#define mmMC_HUB_RDREQ_VCE 0x085F
748#define mmMC_HUB_RDREQ_VCEU 0x0866
749#define mmMC_HUB_RDREQ_VMC 0x0865
750#define mmMC_HUB_RDREQ_WTM_CNTL 0x083D
751#define mmMC_HUB_RDREQ_XDMAM 0x0882
752#define mmMC_HUB_SHARED_DAGB_DLY 0x0846
753#define mmMC_HUB_WDP_BP 0x0837
754#define mmMC_HUB_WDP_CNTL 0x0835
755#define mmMC_HUB_WDP_CREDITS 0x083F
756#define mmMC_HUB_WDP_ERR 0x0836
757#define mmMC_HUB_WDP_GBL0 0x0841
758#define mmMC_HUB_WDP_GBL1 0x0842
759#define mmMC_HUB_WDP_HDP 0x0879
760#define mmMC_HUB_WDP_IH 0x0872
761#define mmMC_HUB_WDP_MCDW 0x0867
762#define mmMC_HUB_WDP_MCDX 0x0868
763#define mmMC_HUB_WDP_MCDY 0x0869
764#define mmMC_HUB_WDP_MCDZ 0x086A
765#define mmMC_HUB_WDP_MCIF 0x086F
766#define mmMC_HUB_WDP_MGPU 0x0843
767#define mmMC_HUB_WDP_MGPU2 0x0840
768#define mmMC_HUB_WDP_RLC 0x0873
769#define mmMC_HUB_WDP_SEM 0x0874
770#define mmMC_HUB_WDP_SH0 0x086E
771#define mmMC_HUB_WDP_SH1 0x0876
772#define mmMC_HUB_WDP_SIP 0x086B
773#define mmMC_HUB_WDP_SMU 0x0875
774#define mmMC_HUB_WDP_STATUS 0x0838
775#define mmMC_HUB_WDP_UMC 0x0877
776#define mmMC_HUB_WDP_UVD 0x0878
777#define mmMC_HUB_WDP_VCE 0x0870
778#define mmMC_HUB_WDP_VCEU 0x087F
779#define mmMC_HUB_WDP_WTM_CNTL 0x083E
780#define mmMC_HUB_WDP_XDMA 0x0881
781#define mmMC_HUB_WDP_XDMAM 0x0880
782#define mmMC_HUB_WDP_XDP 0x0871
783#define mmMC_HUB_WRRET_CNTL 0x083C
784#define mmMC_HUB_WRRET_MCDW 0x087B
785#define mmMC_HUB_WRRET_MCDX 0x087C
786#define mmMC_HUB_WRRET_MCDY 0x087D
787#define mmMC_HUB_WRRET_MCDZ 0x087E
788#define mmMC_HUB_WRRET_STATUS 0x083A
789#define mmMC_IMP_CNTL 0x0A36
790#define mmMC_IMP_DEBUG 0x0A37
791#define mmMC_IMP_DQ_STATUS 0x0ABC
792#define mmMC_IMP_STATUS 0x0A38
793#define mmMC_IO_APHY_STR_CNTL_D0 0x0A97
794#define mmMC_IO_APHY_STR_CNTL_D1 0x0A98
795#define mmMC_IO_CDRCNTL1_D0 0x0ADD
796#define mmMC_IO_CDRCNTL1_D1 0x0ADE
797#define mmMC_IO_CDRCNTL2_D0 0x0AE4
798#define mmMC_IO_CDRCNTL2_D1 0x0AE5
799#define mmMC_IO_CDRCNTL_D0 0x0A55
800#define mmMC_IO_CDRCNTL_D1 0x0A56
801#define mmMC_IO_DPHY_STR_CNTL_D0 0x0A4E
802#define mmMC_IO_DPHY_STR_CNTL_D1 0x0A54
803#define mmMC_IO_PAD_CNTL 0x0A73
804#define mmMC_IO_PAD_CNTL_D0 0x0A74
805#define mmMC_IO_PAD_CNTL_D1 0x0A75
806#define mmMC_IO_RXCNTL1_DPHY0_D0 0x0ADF
807#define mmMC_IO_RXCNTL1_DPHY0_D1 0x0AE1
808#define mmMC_IO_RXCNTL1_DPHY1_D0 0x0AE0
809#define mmMC_IO_RXCNTL1_DPHY1_D1 0x0AE2
810#define mmMC_IO_RXCNTL_DPHY0_D0 0x0A4C
811#define mmMC_IO_RXCNTL_DPHY0_D1 0x0A52
812#define mmMC_IO_RXCNTL_DPHY1_D0 0x0A4D
813#define mmMC_IO_RXCNTL_DPHY1_D1 0x0A53
814#define mmMC_IO_TXCNTL_APHY_D0 0x0A4B
815#define mmMC_IO_TXCNTL_APHY_D1 0x0A51
816#define mmMC_IO_TXCNTL_DPHY0_D0 0x0A49
817#define mmMC_IO_TXCNTL_DPHY0_D1 0x0A4F
818#define mmMC_IO_TXCNTL_DPHY1_D0 0x0A4A
819#define mmMC_IO_TXCNTL_DPHY1_D1 0x0A50
820#define mmMCLK_PWRMGT_CNTL 0x0AE8
821#define mmMC_MEM_POWER_LS 0x082A
822#define mmMC_NPL_STATUS 0x0A76
823#define mmMC_PHY_TIMING_2 0x0ACE
824#define mmMC_PHY_TIMING_D0 0x0ACC
825#define mmMC_PHY_TIMING_D1 0x0ACD
826#define mmMC_PMG_AUTO_CFG 0x0A35
827#define mmMC_PMG_AUTO_CMD 0x0A34
828#define mmMC_PMG_CFG 0x0A84
829#define mmMC_PMG_CMD_EMRS 0x0A83
830#define mmMC_PMG_CMD_MRS 0x0AAB
831#define mmMC_PMG_CMD_MRS1 0x0AD1
832#define mmMC_PMG_CMD_MRS2 0x0AD7
833#define mmMC_RD_CB 0x0981
834#define mmMC_RD_DB 0x0982
835#define mmMC_RD_GRP_EXT 0x0978
836#define mmMC_RD_GRP_GFX 0x0803
837#define mmMC_RD_GRP_LCL 0x098A
838#define mmMC_RD_GRP_OTH 0x0807
839#define mmMC_RD_GRP_SYS 0x0805
840#define mmMC_RD_HUB 0x0985
841#define mmMC_RD_TC0 0x0983
842#define mmMC_RD_TC1 0x0984
843#define mmMC_RPB_ARB_CNTL 0x0951
844#define mmMC_RPB_BIF_CNTL 0x0952
845#define mmMC_RPB_CID_QUEUE_EX 0x095A
846#define mmMC_RPB_CID_QUEUE_EX_DATA 0x095B
847#define mmMC_RPB_CID_QUEUE_RD 0x0957
848#define mmMC_RPB_CID_QUEUE_WR 0x0956
849#define mmMC_RPB_CONF 0x094D
850#define mmMC_RPB_DBG1 0x094F
851#define mmMC_RPB_EFF_CNTL 0x0950
852#define mmMC_RPB_IF_CONF 0x094E
853#define mmMC_RPB_PERF_COUNTER_CNTL 0x0958
854#define mmMC_RPB_PERF_COUNTER_STATUS 0x0959
855#define mmMC_RPB_RD_SWITCH_CNTL 0x0955
856#define mmMC_RPB_WR_COMBINE_CNTL 0x0954
857#define mmMC_RPB_WR_SWITCH_CNTL 0x0953
858#define mmMC_SEQ_BIT_REMAP_B0_D0 0x0AA3
859#define mmMC_SEQ_BIT_REMAP_B0_D1 0x0AA7
860#define mmMC_SEQ_BIT_REMAP_B1_D0 0x0AA4
861#define mmMC_SEQ_BIT_REMAP_B1_D1 0x0AA8
862#define mmMC_SEQ_BIT_REMAP_B2_D0 0x0AA5
863#define mmMC_SEQ_BIT_REMAP_B2_D1 0x0AA9
864#define mmMC_SEQ_BIT_REMAP_B3_D0 0x0AA6
865#define mmMC_SEQ_BIT_REMAP_B3_D1 0x0AAA
866#define mmMC_SEQ_BYTE_REMAP_D0 0x0A93
867#define mmMC_SEQ_BYTE_REMAP_D1 0x0A94
868#define mmMC_SEQ_CAS_TIMING 0x0A29
869#define mmMC_SEQ_CAS_TIMING_LP 0x0A9C
870#define mmMC_SEQ_CG 0x0A9A
871#define mmMC_SEQ_CMD 0x0A31
872#define mmMC_SEQ_CNTL 0x0A25
873#define mmMC_SEQ_CNTL_2 0x0AD4
874#define mmMC_SEQ_DRAM 0x0A26
875#define mmMC_SEQ_DRAM_2 0x0A27
876#define mmMC_SEQ_DRAM_ERROR_INSERTION 0x0ACB
877#define mmMC_SEQ_FIFO_CTL 0x0A57
878#define mmMC_SEQ_IO_DEBUG_DATA 0x0A92
879#define mmMC_SEQ_IO_DEBUG_INDEX 0x0A91
880#define mmMC_SEQ_IO_RDBI 0x0AB4
881#define mmMC_SEQ_IO_REDC 0x0AB5
882#define mmMC_SEQ_IO_RESERVE_D0 0x0AB7
883#define mmMC_SEQ_IO_RESERVE_D1 0x0AB8
884#define mmMC_SEQ_IO_RWORD0 0x0AAC
885#define mmMC_SEQ_IO_RWORD1 0x0AAD
886#define mmMC_SEQ_IO_RWORD2 0x0AAE
887#define mmMC_SEQ_IO_RWORD3 0x0AAF
888#define mmMC_SEQ_IO_RWORD4 0x0AB0
889#define mmMC_SEQ_IO_RWORD5 0x0AB1
890#define mmMC_SEQ_IO_RWORD6 0x0AB2
891#define mmMC_SEQ_IO_RWORD7 0x0AB3
892#define mmMC_SEQ_MISC0 0x0A80
893#define mmMC_SEQ_MISC1 0x0A81
894#define mmMC_SEQ_MISC3 0x0A8B
895#define mmMC_SEQ_MISC4 0x0A8C
896#define mmMC_SEQ_MISC5 0x0A95
897#define mmMC_SEQ_MISC6 0x0A96
898#define mmMC_SEQ_MISC7 0x0A99
899#define mmMC_SEQ_MISC8 0x0A5F
900#define mmMC_SEQ_MISC9 0x0AE7
901#define mmMC_SEQ_MISC_TIMING 0x0A2A
902#define mmMC_SEQ_MISC_TIMING2 0x0A2B
903#define mmMC_SEQ_MISC_TIMING2_LP 0x0A9E
904#define mmMC_SEQ_MISC_TIMING_LP 0x0A9D
905#define mmMC_SEQ_MPLL_OVERRIDE 0x0A22
906#define mmMC_SEQ_PERF_CNTL 0x0A77
907#define mmMC_SEQ_PERF_CNTL_1 0x0AFD
908#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0x0A79
909#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0x0A7A
910#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0x0A7B
911#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0x0A7C
912#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0x0AD9
913#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0x0ADA
914#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0x0ADB
915#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0x0ADC
916#define mmMC_SEQ_PERF_SEQ_CTL 0x0A78
917#define mmMC_SEQ_PMG_CMD_EMRS_LP 0x0AA1
918#define mmMC_SEQ_PMG_CMD_MRS1_LP 0x0AD2
919#define mmMC_SEQ_PMG_CMD_MRS2_LP 0x0AD8
920#define mmMC_SEQ_PMG_CMD_MRS_LP 0x0AA2
921#define mmMC_SEQ_PMG_PG_HWCNTL 0x0AB9
922#define mmMC_SEQ_PMG_PG_SWCNTL_0 0x0ABA
923#define mmMC_SEQ_PMG_PG_SWCNTL_1 0x0ABB
924#define mmMC_SEQ_PMG_TIMING 0x0A2C
925#define mmMC_SEQ_PMG_TIMING_LP 0x0AD3
926#define mmMC_SEQ_RAS_TIMING 0x0A28
927#define mmMC_SEQ_RAS_TIMING_LP 0x0A9B
928#define mmMC_SEQ_RD_CTL_D0 0x0A2D
929#define mmMC_SEQ_RD_CTL_D0_LP 0x0AC7
930#define mmMC_SEQ_RD_CTL_D1 0x0A2E
931#define mmMC_SEQ_RD_CTL_D1_LP 0x0AC8
932#define mmMC_SEQ_RESERVE_0_S 0x0A1E
933#define mmMC_SEQ_RESERVE_1_S 0x0A1F
934#define mmMC_SEQ_RESERVE_M 0x0A82
935#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0x0A67
936#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0x0A6D
937#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0x0A68
938#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0x0A6E
939#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0x0A69
940#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0x0A6F
941#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0x0A6A
942#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0x0A70
943#define mmMC_SEQ_RXFRAMING_DBI_D0 0x0A6B
944#define mmMC_SEQ_RXFRAMING_DBI_D1 0x0A71
945#define mmMC_SEQ_RXFRAMING_EDC_D0 0x0A6C
946#define mmMC_SEQ_RXFRAMING_EDC_D1 0x0A72
947#define mmMC_SEQ_STATUS_M 0x0A7D
948#define mmMC_SEQ_STATUS_S 0x0A20
949#define mmMC_SEQ_SUP_CNTL 0x0A32
950#define mmMC_SEQ_SUP_DEC_STAT 0x0A88
951#define mmMC_SEQ_SUP_GP0_STAT 0x0A8F
952#define mmMC_SEQ_SUP_GP1_STAT 0x0A90
953#define mmMC_SEQ_SUP_GP2_STAT 0x0A85
954#define mmMC_SEQ_SUP_GP3_STAT 0x0A86
955#define mmMC_SEQ_SUP_IR_STAT 0x0A87
956#define mmMC_SEQ_SUP_PGM 0x0A33
957#define mmMC_SEQ_SUP_PGM_STAT 0x0A89
958#define mmMC_SEQ_SUP_R_PGM 0x0A8A
959#define mmMC_SEQ_TCG_CNTL 0x0ABD
960#define mmMC_SEQ_TIMER_RD 0x0ACA
961#define mmMC_SEQ_TIMER_WR 0x0AC9
962#define mmMC_SEQ_TRAIN_CAPTURE 0x0A3E
963#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0x0A3B
964#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0x0AFE
965#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0x0AFF
966#define mmMC_SEQ_TRAIN_TIMING 0x0A40
967#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0x0A3F
968#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0x0A3A
969#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0x0A3C
970#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0x0A3D
971#define mmMC_SEQ_TSM_BCNT 0x0AC2
972#define mmMC_SEQ_TSM_CTRL 0x0ABE
973#define mmMC_SEQ_TSM_DBI 0x0AC6
974#define mmMC_SEQ_TSM_DEBUG_DATA 0x0AD0
975#define mmMC_SEQ_TSM_DEBUG_INDEX 0x0ACF
976#define mmMC_SEQ_TSM_EDC 0x0AC5
977#define mmMC_SEQ_TSM_FLAG 0x0AC3
978#define mmMC_SEQ_TSM_GCNT 0x0ABF
979#define mmMC_SEQ_TSM_MISC 0x0AE6
980#define mmMC_SEQ_TSM_NCNT 0x0AC1
981#define mmMC_SEQ_TSM_OCNT 0x0AC0
982#define mmMC_SEQ_TSM_UPDATE 0x0AC4
983#define mmMC_SEQ_TSM_WCDR 0x0AE3
984#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0x0A58
985#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0x0A60
986#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0x0A59
987#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0x0A61
988#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0x0A5A
989#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0x0A62
990#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0x0A5B
991#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0x0A63
992#define mmMC_SEQ_TXFRAMING_DBI_D0 0x0A5C
993#define mmMC_SEQ_TXFRAMING_DBI_D1 0x0A64
994#define mmMC_SEQ_TXFRAMING_EDC_D0 0x0A5D
995#define mmMC_SEQ_TXFRAMING_EDC_D1 0x0A65
996#define mmMC_SEQ_TXFRAMING_FCK_D0 0x0A5E
997#define mmMC_SEQ_TXFRAMING_FCK_D1 0x0A66
998#define mmMC_SEQ_VENDOR_ID_I0 0x0A7E
999#define mmMC_SEQ_VENDOR_ID_I1 0x0A7F
1000#define mmMC_SEQ_WCDR_CTRL 0x0A39
1001#define mmMC_SEQ_WR_CTL_2 0x0AD5
1002#define mmMC_SEQ_WR_CTL_2_LP 0x0AD6
1003#define mmMC_SEQ_WR_CTL_D0 0x0A2F
1004#define mmMC_SEQ_WR_CTL_D0_LP 0x0A9F
1005#define mmMC_SEQ_WR_CTL_D1 0x0A30
1006#define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0
1007#define mmMC_SHARED_BLACKOUT_CNTL 0x082B
1008#define mmMC_SHARED_CHMAP 0x0801
1009#define mmMC_SHARED_CHREMAP 0x0802
1010#define mmMC_TRAIN_EDCCDR_R_D0 0x0A41
1011#define mmMC_TRAIN_EDCCDR_R_D1 0x0A42
1012#define mmMC_TRAIN_EDC_STATUS_D0 0x0A45
1013#define mmMC_TRAIN_EDC_STATUS_D1 0x0A48
1014#define mmMC_TRAIN_PRBSERR_0_D0 0x0A43
1015#define mmMC_TRAIN_PRBSERR_0_D1 0x0A46
1016#define mmMC_TRAIN_PRBSERR_1_D0 0x0A44
1017#define mmMC_TRAIN_PRBSERR_1_D1 0x0A47
1018#define mmMC_TRAIN_PRBSERR_2_D0 0x0AFB
1019#define mmMC_TRAIN_PRBSERR_2_D1 0x0AFC
1020#define mmMC_VM_AGP_BASE 0x080C
1021#define mmMC_VM_AGP_BOT 0x080B
1022#define mmMC_VM_AGP_TOP 0x080A
1023#define mmMC_VM_DC_WRITE_CNTL 0x0810
1024#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x0815
1025#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x0811
1026#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x0816
1027#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x0812
1028#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x0817
1029#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x0813
1030#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x0818
1031#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x0814
1032#define mmMC_VM_FB_LOCATION 0x0809
1033#define mmMC_VM_FB_OFFSET 0x081A
1034#define mmMC_VM_MB_L1_TLB0_DEBUG 0x0891
1035#define mmMC_VM_MB_L1_TLB0_STATUS 0x0895
1036#define mmMC_VM_MB_L1_TLB1_STATUS 0x0896
1037#define mmMC_VM_MB_L1_TLB2_DEBUG 0x0893
1038#define mmMC_VM_MB_L1_TLB2_STATUS 0x0897
1039#define mmMC_VM_MB_L1_TLB3_DEBUG 0x08A5
1040#define mmMC_VM_MB_L1_TLB3_STATUS 0x08A6
1041#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x08A1
1042#define mmMC_VM_MD_L1_TLB0_DEBUG 0x0998
1043#define mmMC_VM_MD_L1_TLB0_STATUS 0x099B
1044#define mmMC_VM_MD_L1_TLB1_DEBUG 0x0999
1045#define mmMC_VM_MD_L1_TLB1_STATUS 0x099C
1046#define mmMC_VM_MD_L1_TLB2_DEBUG 0x099A
1047#define mmMC_VM_MD_L1_TLB2_STATUS 0x099D
1048#define mmMC_VM_MD_L1_TLB3_DEBUG 0x09A7
1049#define mmMC_VM_MD_L1_TLB3_STATUS 0x09A8
1050#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x09A4
1051#define mmMC_VM_MX_L1_TLB_CNTL 0x0819
1052#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x080F
1053#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x080E
1054#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x080D
1055#define mmMC_WR_CB 0x0986
1056#define mmMC_WR_DB 0x0987
1057#define mmMC_WR_GRP_EXT 0x0979
1058#define mmMC_WR_GRP_GFX 0x0804
1059#define mmMC_WR_GRP_LCL 0x098B
1060#define mmMC_WR_GRP_OTH 0x0808
1061#define mmMC_WR_GRP_SYS 0x0806
1062#define mmMC_WR_HUB 0x0988
1063#define mmMC_WR_TC0 0x097B
1064#define mmMC_WR_TC1 0x097C
1065#define mmMC_XBAR_ADDR_DEC 0x0C80
1066#define mmMC_XBAR_ARB 0x0C8D
1067#define mmMC_XBAR_ARB_MAX_BURST 0x0C8E
1068#define mmMC_XBAR_CHTRIREMAP 0x0C8B
1069#define mmMC_XBAR_PERF_MON_CNTL0 0x0C8F
1070#define mmMC_XBAR_PERF_MON_CNTL1 0x0C90
1071#define mmMC_XBAR_PERF_MON_CNTL2 0x0C91
1072#define mmMC_XBAR_PERF_MON_MAX_THSH 0x0C96
1073#define mmMC_XBAR_PERF_MON_RSLT0 0x0C92
1074#define mmMC_XBAR_PERF_MON_RSLT1 0x0C93
1075#define mmMC_XBAR_PERF_MON_RSLT2 0x0C94
1076#define mmMC_XBAR_PERF_MON_RSLT3 0x0C95
1077#define mmMC_XBAR_RDREQ_CREDIT 0x0C83
1078#define mmMC_XBAR_RDREQ_PRI_CREDIT 0x0C84
1079#define mmMC_XBAR_RDRET_CREDIT1 0x0C87
1080#define mmMC_XBAR_RDRET_CREDIT2 0x0C88
1081#define mmMC_XBAR_RDRET_PRI_CREDIT1 0x0C89
1082#define mmMC_XBAR_RDRET_PRI_CREDIT2 0x0C8A
1083#define mmMC_XBAR_REMOTE 0x0C81
1084#define mmMC_XBAR_SPARE0 0x0C97
1085#define mmMC_XBAR_SPARE1 0x0C98
1086#define mmMC_XBAR_TWOCHAN 0x0C8C
1087#define mmMC_XBAR_WRREQ_CREDIT 0x0C82
1088#define mmMC_XBAR_WRRET_CREDIT1 0x0C85
1089#define mmMC_XBAR_WRRET_CREDIT2 0x0C86
1090#define mmMC_XPB_CLG_CFG0 0x08E9
1091#define mmMC_XPB_CLG_CFG10 0x08F3
1092#define mmMC_XPB_CLG_CFG1 0x08EA
1093#define mmMC_XPB_CLG_CFG11 0x08F4
1094#define mmMC_XPB_CLG_CFG12 0x08F5
1095#define mmMC_XPB_CLG_CFG13 0x08F6
1096#define mmMC_XPB_CLG_CFG14 0x08F7
1097#define mmMC_XPB_CLG_CFG15 0x08F8
1098#define mmMC_XPB_CLG_CFG16 0x08F9
1099#define mmMC_XPB_CLG_CFG17 0x08FA
1100#define mmMC_XPB_CLG_CFG18 0x08FB
1101#define mmMC_XPB_CLG_CFG19 0x08FC
1102#define mmMC_XPB_CLG_CFG20 0x0928
1103#define mmMC_XPB_CLG_CFG2 0x08EB
1104#define mmMC_XPB_CLG_CFG21 0x0929
1105#define mmMC_XPB_CLG_CFG22 0x092A
1106#define mmMC_XPB_CLG_CFG23 0x092B
1107#define mmMC_XPB_CLG_CFG24 0x092C
1108#define mmMC_XPB_CLG_CFG25 0x092D
1109#define mmMC_XPB_CLG_CFG26 0x092E
1110#define mmMC_XPB_CLG_CFG27 0x092F
1111#define mmMC_XPB_CLG_CFG28 0x0930
1112#define mmMC_XPB_CLG_CFG29 0x0931
1113#define mmMC_XPB_CLG_CFG30 0x0932
1114#define mmMC_XPB_CLG_CFG3 0x08EC
1115#define mmMC_XPB_CLG_CFG31 0x0933
1116#define mmMC_XPB_CLG_CFG32 0x0936
1117#define mmMC_XPB_CLG_CFG33 0x0937
1118#define mmMC_XPB_CLG_CFG34 0x0938
1119#define mmMC_XPB_CLG_CFG35 0x0939
1120#define mmMC_XPB_CLG_CFG36 0x093A
1121#define mmMC_XPB_CLG_CFG4 0x08ED
1122#define mmMC_XPB_CLG_CFG5 0x08EE
1123#define mmMC_XPB_CLG_CFG6 0x08EF
1124#define mmMC_XPB_CLG_CFG7 0x08F0
1125#define mmMC_XPB_CLG_CFG8 0x08F1
1126#define mmMC_XPB_CLG_CFG9 0x08F2
1127#define mmMC_XPB_CLG_EXTRA 0x08FD
1128#define mmMC_XPB_CLG_EXTRA_RD 0x0935
1129#define mmMC_XPB_CLK_GAT 0x091E
1130#define mmMC_XPB_INTF_CFG 0x091F
1131#define mmMC_XPB_INTF_CFG2 0x0934
1132#define mmMC_XPB_INTF_STS 0x0920
1133#define mmMC_XPB_LB_ADDR 0x08FE
1134#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x0923
1135#define mmMC_XPB_MISC_CFG 0x0927
1136#define mmMC_XPB_P2P_BAR0 0x0904
1137#define mmMC_XPB_P2P_BAR1 0x0905
1138#define mmMC_XPB_P2P_BAR2 0x0906
1139#define mmMC_XPB_P2P_BAR3 0x0907
1140#define mmMC_XPB_P2P_BAR4 0x0908
1141#define mmMC_XPB_P2P_BAR5 0x0909
1142#define mmMC_XPB_P2P_BAR6 0x090A
1143#define mmMC_XPB_P2P_BAR7 0x090B
1144#define mmMC_XPB_P2P_BAR_CFG 0x0903
1145#define mmMC_XPB_P2P_BAR_DEBUG 0x090D
1146#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x090E
1147#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x090F
1148#define mmMC_XPB_P2P_BAR_SETUP 0x090C
1149#define mmMC_XPB_PEER_SYS_BAR0 0x0910
1150#define mmMC_XPB_PEER_SYS_BAR1 0x0911
1151#define mmMC_XPB_PEER_SYS_BAR2 0x0912
1152#define mmMC_XPB_PEER_SYS_BAR3 0x0913
1153#define mmMC_XPB_PEER_SYS_BAR4 0x0914
1154#define mmMC_XPB_PEER_SYS_BAR5 0x0915
1155#define mmMC_XPB_PEER_SYS_BAR6 0x0916
1156#define mmMC_XPB_PEER_SYS_BAR7 0x0917
1157#define mmMC_XPB_PEER_SYS_BAR8 0x0918
1158#define mmMC_XPB_PEER_SYS_BAR9 0x0919
1159#define mmMC_XPB_PERF_KNOBS 0x0924
1160#define mmMC_XPB_PIPE_STS 0x0921
1161#define mmMC_XPB_RTR_DEST_MAP0 0x08DB
1162#define mmMC_XPB_RTR_DEST_MAP1 0x08DC
1163#define mmMC_XPB_RTR_DEST_MAP2 0x08DD
1164#define mmMC_XPB_RTR_DEST_MAP3 0x08DE
1165#define mmMC_XPB_RTR_DEST_MAP4 0x08DF
1166#define mmMC_XPB_RTR_DEST_MAP5 0x08E0
1167#define mmMC_XPB_RTR_DEST_MAP6 0x08E1
1168#define mmMC_XPB_RTR_DEST_MAP7 0x08E2
1169#define mmMC_XPB_RTR_DEST_MAP8 0x08E3
1170#define mmMC_XPB_RTR_DEST_MAP9 0x08E4
1171#define mmMC_XPB_RTR_SRC_APRTR0 0x08CD
1172#define mmMC_XPB_RTR_SRC_APRTR1 0x08CE
1173#define mmMC_XPB_RTR_SRC_APRTR2 0x08CF
1174#define mmMC_XPB_RTR_SRC_APRTR3 0x08D0
1175#define mmMC_XPB_RTR_SRC_APRTR4 0x08D1
1176#define mmMC_XPB_RTR_SRC_APRTR5 0x08D2
1177#define mmMC_XPB_RTR_SRC_APRTR6 0x08D3
1178#define mmMC_XPB_RTR_SRC_APRTR7 0x08D4
1179#define mmMC_XPB_RTR_SRC_APRTR8 0x08D5
1180#define mmMC_XPB_RTR_SRC_APRTR9 0x08D6
1181#define mmMC_XPB_STICKY 0x0925
1182#define mmMC_XPB_STICKY_W1C 0x0926
1183#define mmMC_XPB_SUB_CTRL 0x0922
1184#define mmMC_XPB_UNC_THRESH_HST 0x08FF
1185#define mmMC_XPB_UNC_THRESH_SID 0x0900
1186#define mmMC_XPB_WCB_CFG 0x0902
1187#define mmMC_XPB_WCB_STS 0x0901
1188#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x091A
1189#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x091B
1190#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x091C
1191#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x091D
1192#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x08E5
1193#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x08E6
1194#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x08E7
1195#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x08E8
1196#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x08D7
1197#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x08D8
1198#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x08D9
1199#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x08DA
1200#define mmMPLL_AD_FUNC_CNTL 0x0AF0
1201#define mmMPLL_AD_STATUS 0x0AF6
1202#define mmMPLL_CNTL_MODE 0x0AEC
1203#define mmMPLL_CONTROL 0x0AF5
1204#define mmMPLL_DQ_0_0_STATUS 0x0AF7
1205#define mmMPLL_DQ_0_1_STATUS 0x0AF8
1206#define mmMPLL_DQ_1_0_STATUS 0x0AF9
1207#define mmMPLL_DQ_1_1_STATUS 0x0AFA
1208#define mmMPLL_DQ_FUNC_CNTL 0x0AF1
1209#define mmMPLL_FUNC_CNTL 0x0AED
1210#define mmMPLL_FUNC_CNTL_1 0x0AEE
1211#define mmMPLL_FUNC_CNTL_2 0x0AEF
1212#define mmMPLL_SEQ_UCODE_1 0x0AEA
1213#define mmMPLL_SEQ_UCODE_2 0x0AEB
1214#define mmMPLL_SS1 0x0AF3
1215#define mmMPLL_SS2 0x0AF4
1216#define mmMPLL_TIME 0x0AF2
1217#define mmVM_CONTEXT0_CNTL 0x0504
1218#define mmVM_CONTEXT0_CNTL2 0x050C
1219#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F
1220#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x055F
1221#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x0557
1222#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x053E
1223#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x0546
1224#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x0536
1225#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x0510
1226#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x0511
1227#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x0512
1228#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x0513
1229#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x0514
1230#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x0515
1231#define mmVM_CONTEXT1_CNTL 0x0505
1232#define mmVM_CONTEXT1_CNTL2 0x050D
1233#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x0550
1234#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x0560
1235#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x0558
1236#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x053F
1237#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x0547
1238#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0537
1239#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x0551
1240#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x0552
1241#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x0553
1242#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x0554
1243#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x0555
1244#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x0556
1245#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x050E
1246#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x050F
1247#define mmVM_CONTEXTS_DISABLE 0x0535
1248#define mmVM_DEBUG 0x056F
1249#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x0507
1250#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0506
1251#define mmVM_FAULT_CLIENT_ID 0x054E
1252#define mmVM_INVALIDATE_REQUEST 0x051E
1253#define mmVM_INVALIDATE_RESPONSE 0x051F
1254#define mmVM_L2_BANK_SELECT_MASKA 0x0572
1255#define mmVM_L2_BANK_SELECT_MASKB 0x0573
1256#define mmVM_L2_CG 0x0570
1257#define mmVM_L2_CNTL 0x0500
1258#define mmVM_L2_CNTL2 0x0501
1259#define mmVM_L2_CNTL3 0x0502
1260#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x0576
1261#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x0575
1262#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x0577
1263#define mmVM_L2_STATUS 0x0503
1264#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x0530
1265#define mmVM_PRT_APERTURE0_LOW_ADDR 0x052C
1266#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x0531
1267#define mmVM_PRT_APERTURE1_LOW_ADDR 0x052D
1268#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x0532
1269#define mmVM_PRT_APERTURE2_LOW_ADDR 0x052E
1270#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x0533
1271#define mmVM_PRT_APERTURE3_LOW_ADDR 0x052F
1272#define mmVM_PRT_CNTL 0x0534
1273
1274#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
new file mode 100644
index 000000000000..0f6c6c8d089b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
@@ -0,0 +1,11895 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef GMC_6_0_SH_MASK_H
24#define GMC_6_0_SH_MASK_H
25
26#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
36#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L
37#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002
38#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L
39#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e
40#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L
41#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007
42#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L
43#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001
44#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L
45#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f
46#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L
47#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000
48#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L
49#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010
50#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L
51#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a
52#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L
53#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008
54#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L
55#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005
56#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L
57#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006
58#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L
59#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009
60#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x0000003cL
61#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x00000002
62#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x00000001L
63#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x00000000
64#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL
65#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000
66#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x03f00000L
67#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014
68#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0000fc00L
69#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a
70#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x0000003fL
71#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000
72#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000100L
73#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000008
74#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00010000L
75#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000010
76#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x0000001fL
77#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x00000000
78#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL
79#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000
80#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
81#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010
82#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
83#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f
84#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x0000003fL
85#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000
86#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
87#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011
88#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L
89#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018
90#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
91#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012
92#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L
93#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013
94#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L
95#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a
96#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
97#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000
98#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
99#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001
100#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
101#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002
102#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffffL
103#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x00000000
104#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x00000003L
105#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x00000000
106#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x00000004L
107#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x00000002
108#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x00000010L
109#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x00000004
110#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L
111#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c
112#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L
113#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014
114#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L
115#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c
116#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L
117#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000
118#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L
119#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004
120#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
121#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008
122#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L
123#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e
124#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x00000100L
125#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x00000008
126#define ATC_L1RD_STATUS__BUSY_MASK 0x00000001L
127#define ATC_L1RD_STATUS__BUSY__SHIFT 0x00000000
128#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L
129#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001
130#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L
131#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c
132#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L
133#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014
134#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L
135#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c
136#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L
137#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000
138#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L
139#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004
140#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
141#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008
142#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L
143#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e
144#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x00000100L
145#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x00000008
146#define ATC_L1WR_STATUS__BUSY_MASK 0x00000001L
147#define ATC_L1WR_STATUS__BUSY__SHIFT 0x00000000
148#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L
149#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001
150#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
151#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000
152#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L
153#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000a
154#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000030L
155#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000004
156#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L
157#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000b
158#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000003fL
159#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000
160#define ATC_MISC_CG__ENABLE_MASK 0x00040000L
161#define ATC_MISC_CG__ENABLE__SHIFT 0x00000012
162#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
163#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013
164#define ATC_MISC_CG__OFFDLY_MASK 0x00000fc0L
165#define ATC_MISC_CG__OFFDLY__SHIFT 0x00000006
166#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL
167#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000
168#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L
169#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000
170#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
171#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
172#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
173#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
174#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL
175#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000
176#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L
177#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000
178#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
179#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
180#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
181#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
182#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL
183#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000
184#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
185#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f
186#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL
187#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000
188#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
189#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f
190#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL
191#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000
192#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
193#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f
194#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL
195#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000
196#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
197#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f
198#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL
199#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000
200#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
201#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f
202#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL
203#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000
204#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
205#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f
206#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL
207#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000
208#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
209#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f
210#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL
211#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000
212#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
213#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f
214#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL
215#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000
216#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
217#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f
218#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL
219#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000
220#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
221#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f
222#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL
223#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000
224#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
225#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f
226#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL
227#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000
228#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
229#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f
230#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL
231#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000
232#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
233#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f
234#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL
235#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000
236#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
237#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f
238#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL
239#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000
240#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
241#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f
242#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL
243#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000
244#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
245#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f
246#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
247#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000
248#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
249#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a
250#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
251#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b
252#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
253#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c
254#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
255#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d
256#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
257#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e
258#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
259#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f
260#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
261#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001
262#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
263#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002
264#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
265#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003
266#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
267#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004
268#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
269#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005
270#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
271#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006
272#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
273#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007
274#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
275#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008
276#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
277#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009
278#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL
279#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001
280#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x003ff000L
281#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0x0000000c
282#define DLL_CNTL__DLL_RESET_TIME_MASK 0x000003ffL
283#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x00000000
284#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x01000000L
285#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x00000018
286#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x02000000L
287#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x00000019
288#define DLL_CNTL__PWR2_MODE_MASK 0x04000000L
289#define DLL_CNTL__PWR2_MODE__SHIFT 0x0000001a
290#define GMCON_DEBUG__GFX_CLEAR_MASK 0x00000002L
291#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x00000001
292#define GMCON_DEBUG__GFX_STALL_MASK 0x00000001L
293#define GMCON_DEBUG__GFX_STALL__SHIFT 0x00000000
294#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffcL
295#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x00000002
296#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x00000007L
297#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x00000000
298#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x00000038L
299#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x00000003
300#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x0000fc00L
301#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0x0000000a
302#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x20000000L
303#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x0000001d
304#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x10000000L
305#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x0000001c
306#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x0fff0000L
307#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x00000010
308#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x0000003fL
309#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x00000000
310#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0x00000fc0L
311#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x00000006
312#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00fff000L
313#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x0000000c
314#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000L
315#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0000001c
316#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x08000000L
317#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x0000001b
318#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x00000400L
319#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0x0000000a
320#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00000800L
321#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x0000000b
322#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0x0000f000L
323#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0x0000000c
324#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x02000000L
325#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x00000019
326#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x04000000L
327#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x0000001a
328#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x40000000L
329#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x0000001e
330#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x00060000L
331#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x00000011
332#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x00400000L
333#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x00000016
334#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x00200000L
335#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x00000015
336#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x01000000L
337#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x00000018
338#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x00800000L
339#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x00000017
340#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x00180000L
341#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x00000013
342#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x00010000L
343#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x00000010
344#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L
345#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c
346#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L
347#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018
348#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL
349#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000
350#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L
351#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a
352#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L
353#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c
354#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x00fc0000L
355#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x00000012
356#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000L
357#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x00000018
358#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x00000fc0L
359#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000006
360#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x0003f000L
361#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x0000000c
362#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x0000003fL
363#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000
364#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL
365#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000
366#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL
367#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000
368#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL
369#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000
370#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
371#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a
372#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
373#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b
374#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
375#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008
376#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
377#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009
378#define GMCON_PGFSM_CONFIG__READ_MASK 0x00002000L
379#define GMCON_PGFSM_CONFIG__READ__SHIFT 0x0000000d
380#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L
381#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c
382#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x07ffc000L
383#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0x0000000e
384#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
385#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b
386#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x00001000L
387#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c
388#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0x0f000000L
389#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x00000018
390#define GMCON_PGFSM_READ__READ_VALUE_MASK 0x00ffffffL
391#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x00000000
392#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000L
393#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x0000001c
394#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffffL
395#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x00000000
396#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x003ff000L
397#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0x0000000c
398#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000L
399#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x00000016
400#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
401#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x00000001
402#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000ffcL
403#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x00000002
404#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
405#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x00000000
406#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffffL
407#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x00000000
408#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003ffL
409#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x00000000
410#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000ffffL
411#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x00000000
412#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000L
413#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x00000010
414#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000ffffL
415#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x00000000
416#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000L
417#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x00000010
418#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0x0000ffffL
419#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x00000000
420#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000L
421#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x00000010
422#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0x0000ffffL
423#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x00000000
424#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000L
425#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x00000010
426#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0x0000ffffL
427#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x00000000
428#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000L
429#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x00000010
430#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL
431#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000
432#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L
433#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004
434#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L
435#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c
436#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L
437#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018
438#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L
439#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019
440#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L
441#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a
442#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L
443#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b
444#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L
445#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c
446#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L
447#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d
448#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L
449#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e
450#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L
451#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f
452#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L
453#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010
454#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L
455#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011
456#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L
457#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012
458#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L
459#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013
460#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L
461#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014
462#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L
463#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015
464#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L
465#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016
466#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L
467#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017
468#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L
469#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000
470#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL
471#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002
472#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L
473#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004
474#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L
475#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006
476#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L
477#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008
478#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L
479#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a
480#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L
481#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c
482#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L
483#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e
484#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L
485#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018
486#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L
487#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019
488#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L
489#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a
490#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L
491#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b
492#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L
493#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c
494#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L
495#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d
496#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L
497#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e
498#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L
499#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f
500#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L
501#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010
502#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L
503#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011
504#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L
505#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012
506#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L
507#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013
508#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L
509#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014
510#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L
511#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015
512#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L
513#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016
514#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L
515#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017
516#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L
517#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000
518#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL
519#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002
520#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L
521#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004
522#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L
523#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006
524#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L
525#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008
526#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L
527#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a
528#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L
529#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c
530#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L
531#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e
532#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL
533#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000
534#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L
535#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004
536#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L
537#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008
538#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L
539#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c
540#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L
541#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010
542#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL
543#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000
544#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L
545#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005
546#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L
547#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a
548#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L
549#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f
550#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L
551#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d
552#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L
553#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000
554#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL
555#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001
556#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L
557#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007
558#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL
559#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000
560#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L
561#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008
562#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL
563#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000
564#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L
565#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008
566#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L
567#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010
568#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L
569#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018
570#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L
571#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018
572#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL
573#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000
574#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L
575#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008
576#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L
577#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010
578#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L
579#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018
580#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL
581#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000
582#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L
583#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008
584#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L
585#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010
586#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL
587#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000
588#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L
589#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008
590#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L
591#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010
592#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L
593#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018
594#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L
595#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004
596#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L
597#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000
598#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL
599#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002
600#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL
601#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000
602#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L
603#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004
604#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L
605#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a
606#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L
607#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008
608#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L
609#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009
610#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL
611#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000
612#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L
613#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004
614#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L
615#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a
616#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L
617#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008
618#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L
619#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009
620#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL
621#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000
622#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L
623#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008
624#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L
625#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010
626#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L
627#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018
628#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L
629#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e
630#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L
631#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f
632#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L
633#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008
634#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L
635#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010
636#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L
637#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018
638#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL
639#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000
640#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L
641#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003
642#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L
643#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002
644#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L
645#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000
646#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L
647#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005
648#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L
649#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001
650#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L
651#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000
652#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L
653#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005
654#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL
655#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000
656#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L
657#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007
658#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L
659#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003
660#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L
661#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b
662#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L
663#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008
664#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L
665#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c
666#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L
667#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000
668#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L
669#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004
670#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L
671#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a
672#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L
673#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e
674#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L
675#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002
676#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L
677#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006
678#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L
679#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003
680#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L
681#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007
682#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L
683#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b
684#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L
685#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009
686#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L
687#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d
688#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L
689#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001
690#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L
691#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005
692#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL
693#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000
694#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L
695#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008
696#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L
697#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010
698#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L
699#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018
700#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL
701#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000
702#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L
703#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008
704#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L
705#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010
706#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L
707#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018
708#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL
709#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000
710#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L
711#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008
712#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L
713#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010
714#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L
715#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018
716#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL
717#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000
718#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L
719#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008
720#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L
721#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010
722#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L
723#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018
724#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L
725#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015
726#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L
727#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012
728#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L
729#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013
730#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L
731#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014
732#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L
733#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010
734#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL
735#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000
736#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L
737#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008
738#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L
739#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011
740#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L
741#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015
742#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L
743#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012
744#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L
745#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013
746#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L
747#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014
748#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L
749#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010
750#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL
751#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000
752#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L
753#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008
754#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L
755#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011
756#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L
757#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010
758#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL
759#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000
760#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L
761#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008
762#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L
763#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d
764#define MC_ARB_MISC2__GECC_MASK 0x00040000L
765#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L
766#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013
767#define MC_ARB_MISC2__GECC__SHIFT 0x00000012
768#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L
769#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014
770#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L
771#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b
772#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L
773#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d
774#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L
775#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c
776#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L
777#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e
778#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L
779#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c
780#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L
781#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e
782#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L
783#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015
784#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L
785#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006
786#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L
787#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007
788#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L
789#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008
790#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L
791#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009
792#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L
793#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a
794#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L
795#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005
796#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L
797#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f
798#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L
799#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019
800#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L
801#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014
802#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L
803#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015
804#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L
805#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003
806#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L
807#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018
808#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L
809#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019
810#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L
811#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a
812#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L
813#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017
814#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L
815#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b
816#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L
817#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001
818#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L
819#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013
820#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L
821#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000
822#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L
823#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002
824#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L
825#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005
826#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L
827#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014
828#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L
829#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006
830#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L
831#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012
832#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L
833#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013
834#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L
835#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000
836#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L
837#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002
838#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L
839#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003
840#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L
841#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007
842#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L
843#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008
844#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L
845#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a
846#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L
847#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b
848#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L
849#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e
850#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L
851#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f
852#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L
853#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c
854#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L
855#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d
856#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L
857#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004
858#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L
859#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013
860#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L
861#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000
862#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L
863#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012
864#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL
865#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002
866#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L
867#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011
868#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L
869#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c
870#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L
871#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001
872#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L
873#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f
874#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L
875#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006
876#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L
877#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008
878#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L
879#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000
880#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L
881#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006
882#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L
883#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c
884#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L
885#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002
886#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L
887#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003
888#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL
889#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000
890#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L
891#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014
892#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L
893#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010
894#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L
895#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008
896#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L
897#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007
898#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L
899#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008
900#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L
901#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006
902#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L
903#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000
904#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L
905#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001
906#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L
907#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005
908#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L
909#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004
910#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L
911#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003
912#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L
913#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002
914#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L
915#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010
916#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L
917#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008
918#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL
919#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000
920#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L
921#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018
922#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L
923#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008
924#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL
925#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000
926#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L
927#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010
928#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L
929#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018
930#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L
931#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b
932#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L
933#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000
934#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL
935#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001
936#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L
937#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006
938#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL
939#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000
940#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L
941#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008
942#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L
943#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009
944#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L
945#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a
946#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L
947#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018
948#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L
949#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f
950#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L
951#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010
952#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L
953#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011
954#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L
955#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012
956#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L
957#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013
958#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L
959#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014
960#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L
961#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015
962#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L
963#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016
964#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L
965#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017
966#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L
967#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000
968#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L
969#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004
970#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L
971#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005
972#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L
973#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019
974#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L
975#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001
976#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL
977#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L
978#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e
979#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002
980#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L
981#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006
982#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L
983#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b
984#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L
985#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007
986#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L
987#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d
988#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L
989#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006
990#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL
991#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L
992#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014
993#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L
994#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019
995#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000
996#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L
997#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e
998#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L
999#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005
1000#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L
1001#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d
1002#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L
1003#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c
1004#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L
1005#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006
1006#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL
1007#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000
1008#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL
1009#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000
1010#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L
1011#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000
1012#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL
1013#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002
1014#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L
1015#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004
1016#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L
1017#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011
1018#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L
1019#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c
1020#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L
1021#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019
1022#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L
1023#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008
1024#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL
1025#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000
1026#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L
1027#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018
1028#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L
1029#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010
1030#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0x0000fe00L
1031#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0x00000009
1032#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L
1033#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001
1034#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L
1035#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000
1036#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L
1037#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004
1038#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L
1039#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003
1040#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L
1041#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001
1042#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L
1043#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000
1044#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L
1045#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004
1046#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L
1047#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003
1048#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x00000200L
1049#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x00000009
1050#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x00000400L
1051#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0x0000000a
1052#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x00000800L
1053#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0x0000000b
1054#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x00001000L
1055#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0x0000000c
1056#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x00002000L
1057#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0x0000000d
1058#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x00004000L
1059#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0x0000000e
1060#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0x0000000fL
1061#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x00000000
1062#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x000001f0L
1063#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x00000004
1064#define MC_ARB_WCDR__IDLE_BURST_MASK 0x00001f80L
1065#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x00002000L
1066#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0x0000000d
1067#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x00000007
1068#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x00010000L
1069#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x00000010
1070#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x00000001L
1071#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x00000000
1072#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x0000007cL
1073#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x00000002
1074#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0x0000c000L
1075#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0x0000000e
1076#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x00000002L
1077#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x00000001
1078#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x00020000L
1079#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x00000011
1080#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x02000000L
1081#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x00000019
1082#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x08000000L
1083#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x0000001b
1084#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x04000000L
1085#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x0000001a
1086#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x01c00000L
1087#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x00000016
1088#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x003c0000L
1089#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x00000012
1090#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000L
1091#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x0000001c
1092#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L
1093#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003
1094#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L
1095#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004
1096#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L
1097#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005
1098#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L
1099#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006
1100#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L
1101#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007
1102#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L
1103#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008
1104#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L
1105#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009
1106#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L
1107#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a
1108#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L
1109#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002
1110#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L
1111#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000
1112#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L
1113#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003
1114#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L
1115#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004
1116#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L
1117#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005
1118#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L
1119#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006
1120#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L
1121#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007
1122#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L
1123#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008
1124#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L
1125#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009
1126#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L
1127#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a
1128#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L
1129#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002
1130#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L
1131#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000
1132#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L
1133#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000
1134#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL
1135#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002
1136#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L
1137#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004
1138#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L
1139#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006
1140#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L
1141#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008
1142#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L
1143#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a
1144#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L
1145#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c
1146#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L
1147#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e
1148#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L
1149#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010
1150#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L
1151#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000
1152#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL
1153#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002
1154#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L
1155#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004
1156#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L
1157#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006
1158#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L
1159#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008
1160#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L
1161#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a
1162#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L
1163#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c
1164#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L
1165#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e
1166#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L
1167#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010
1168#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0x000000f0L
1169#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x00000004
1170#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x02000000L
1171#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x00000019
1172#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0x00ffff00L
1173#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x00000008
1174#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x01000000L
1175#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x00000018
1176#define MC_BIST_AUTO_CNTL__MOP_MASK 0x00000003L
1177#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x00000000
1178#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x00000004L
1179#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x00000002
1180#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x00000002L
1181#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x00000001
1182#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x00010000L
1183#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x00000010
1184#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x00020000L
1185#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x00000011
1186#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000L
1187#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x0000001f
1188#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000L
1189#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x0000001c
1190#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000L
1191#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x0000001d
1192#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0x0000fff0L
1193#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x00000004
1194#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0x0ffc0000L
1195#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x00000012
1196#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x00000008L
1197#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x00000003
1198#define MC_BIST_CMD_CNTL__RESET_MASK 0x00000001L
1199#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x00000000
1200#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000L
1201#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x0000001e
1202#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x0000001fL
1203#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x00000100L
1204#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x00000008
1205#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x00000000
1206#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x0001f000L
1207#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x00100000L
1208#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x00000014
1209#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0x0000000c
1210#define MC_BIST_CMP_CNTL__CMP_MASK 0x00030000L
1211#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0x00000ff0L
1212#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x00000004
1213#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0x0000000fL
1214#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x00000000
1215#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x00000010
1216#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x00300000L
1217#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x00000014
1218#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x00002000L
1219#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0x0000000d
1220#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x00040000L
1221#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x00000012
1222#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x00080000L
1223#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x00000013
1224#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x00004000L
1225#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0x0000000e
1226#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x00008000L
1227#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0x0000000f
1228#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x00001000L
1229#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0x0000000c
1230#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000L
1231#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x00000016
1232#define MC_BIST_CNTL__ADR_MODE_MASK 0x00000020L
1233#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x00000005
1234#define MC_BIST_CNTL__DAT_MODE_MASK 0x00000040L
1235#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x00000006
1236#define MC_BIST_CNTL__DONE_MASK 0x40000000L
1237#define MC_BIST_CNTL__DONE__SHIFT 0x0000001e
1238#define MC_BIST_CNTL__ENABLE_D0_MASK 0x00001000L
1239#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0x0000000c
1240#define MC_BIST_CNTL__ENABLE_D1_MASK 0x00002000L
1241#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0x0000000d
1242#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x00004000L
1243#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0x0000000e
1244#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000L
1245#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x0000001f
1246#define MC_BIST_CNTL__LOOP_CNT_MASK 0x0fff0000L
1247#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x00000010
1248#define MC_BIST_CNTL__LOOP_MASK 0x00000c00L
1249#define MC_BIST_CNTL__LOOP__SHIFT 0x0000000a
1250#define MC_BIST_CNTL__MOP_MODE_MASK 0x00000010L
1251#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x00000004
1252#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x00000004L
1253#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x00000002
1254#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x00000008L
1255#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x00000003
1256#define MC_BIST_CNTL__RESET_MASK 0x00000001L
1257#define MC_BIST_CNTL__RESET__SHIFT 0x00000000
1258#define MC_BIST_CNTL__RUN_MASK 0x00000002L
1259#define MC_BIST_CNTL__RUN__SHIFT 0x00000001
1260#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffffL
1261#define MC_BIST_DATA_MASK__MASK__SHIFT 0x00000000
1262#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffffL
1263#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x00000000
1264#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffffL
1265#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x00000000
1266#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffffL
1267#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x00000000
1268#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffffL
1269#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x00000000
1270#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffffL
1271#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x00000000
1272#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffffL
1273#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x00000000
1274#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffffL
1275#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x00000000
1276#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffffL
1277#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x00000000
1278#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x00000040L
1279#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x00000006
1280#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x00000100L
1281#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x00000008
1282#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x00000020L
1283#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x00000005
1284#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x00000080L
1285#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x00000007
1286#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x00000200L
1287#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x00000009
1288#define MC_BIST_DIR_CNTL__EOB_MASK 0x00000008L
1289#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x00000003
1290#define MC_BIST_DIR_CNTL__MOP3_MASK 0x00000400L
1291#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0x0000000a
1292#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x00000010L
1293#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x00000004
1294#define MC_BIST_DIR_CNTL__MOP_MASK 0x00000007L
1295#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x00000000
1296#define MC_BIST_EADDR__BANK_MASK 0x0f000000L
1297#define MC_BIST_EADDR__BANK__SHIFT 0x00000018
1298#define MC_BIST_EADDR__COLH_MASK 0x20000000L
1299#define MC_BIST_EADDR__COLH__SHIFT 0x0000001d
1300#define MC_BIST_EADDR__COL_MASK 0x000003ffL
1301#define MC_BIST_EADDR__COL__SHIFT 0x00000000
1302#define MC_BIST_EADDR__RANK_MASK 0x10000000L
1303#define MC_BIST_EADDR__RANK__SHIFT 0x0000001c
1304#define MC_BIST_EADDR__ROWH_MASK 0xc0000000L
1305#define MC_BIST_EADDR__ROWH__SHIFT 0x0000001e
1306#define MC_BIST_EADDR__ROW_MASK 0x00fffc00L
1307#define MC_BIST_EADDR__ROW__SHIFT 0x0000000a
1308#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0x0f000000L
1309#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x00000018
1310#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000L
1311#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x0000001d
1312#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x000003ffL
1313#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x00000000
1314#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000L
1315#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x0000001c
1316#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000L
1317#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x0000001e
1318#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0x00fffc00L
1319#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0x0000000a
1320#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffffL
1321#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x00000000
1322#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffffL
1323#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x00000000
1324#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffffL
1325#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x00000000
1326#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffffL
1327#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x00000000
1328#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffffL
1329#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x00000000
1330#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffffL
1331#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x00000000
1332#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffffL
1333#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x00000000
1334#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffffL
1335#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x00000000
1336#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffffL
1337#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x00000000
1338#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffffL
1339#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x00000000
1340#define MC_BIST_SADDR__BANK_MASK 0x0f000000L
1341#define MC_BIST_SADDR__BANK__SHIFT 0x00000018
1342#define MC_BIST_SADDR__COLH_MASK 0x20000000L
1343#define MC_BIST_SADDR__COLH__SHIFT 0x0000001d
1344#define MC_BIST_SADDR__COL_MASK 0x000003ffL
1345#define MC_BIST_SADDR__COL__SHIFT 0x00000000
1346#define MC_BIST_SADDR__RANK_MASK 0x10000000L
1347#define MC_BIST_SADDR__RANK__SHIFT 0x0000001c
1348#define MC_BIST_SADDR__ROWH_MASK 0xc0000000L
1349#define MC_BIST_SADDR__ROWH__SHIFT 0x0000001e
1350#define MC_BIST_SADDR__ROW_MASK 0x00fffc00L
1351#define MC_BIST_SADDR__ROW__SHIFT 0x0000000a
1352#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L
1353#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006
1354#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L
1355#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d
1356#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L
1357#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000
1358#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L
1359#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001
1360#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L
1361#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002
1362#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L
1363#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003
1364#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L
1365#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004
1366#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L
1367#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005
1368#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L
1369#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008
1370#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L
1371#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000
1372#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L
1373#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001
1374#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L
1375#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002
1376#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L
1377#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003
1378#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L
1379#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004
1380#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL
1381#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000
1382#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L
1383#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003
1384#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L
1385#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004
1386#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L
1387#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002
1388#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L
1389#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006
1390#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L
1391#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019
1392#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L
1393#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018
1394#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L
1395#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008
1396#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL
1397#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000
1398#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L
1399#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010
1400#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x00010000L
1401#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x00000010
1402#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x00020000L
1403#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x00000011
1404#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L
1405#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008
1406#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL
1407#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000
1408#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL
1409#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000
1410#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L
1411#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006
1412#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL
1413#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000
1414#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L
1415#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008
1416#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL
1417#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001
1418#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x000003c0L
1419#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x00000006
1420#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L
1421#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005
1422#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L
1423#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000
1424#define MC_CITF_DAGB_DLY__CLI_MASK 0x001f0000L
1425#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010
1426#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL
1427#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000
1428#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000L
1429#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018
1430#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L
1431#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012
1432#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L
1433#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c
1434#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L
1435#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018
1436#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL
1437#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000
1438#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x0000003fL
1439#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x00000000
1440#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0x00000fc0L
1441#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x00000006
1442#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L
1443#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012
1444#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L
1445#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1446#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L
1447#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006
1448#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL
1449#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000
1450#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L
1451#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c
1452#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L
1453#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012
1454#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L
1455#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1456#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L
1457#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006
1458#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL
1459#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000
1460#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L
1461#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c
1462#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L
1463#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012
1464#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L
1465#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1466#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L
1467#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006
1468#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL
1469#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000
1470#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L
1471#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c
1472#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0x000001ffL
1473#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000
1474#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x00000040L
1475#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x00000006
1476#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x00001000L
1477#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x0000000c
1478#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x00000080L
1479#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x00000007
1480#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x00002000L
1481#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x0000000d
1482#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x00004000L
1483#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x0000000e
1484#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x00000100L
1485#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x00000008
1486#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x00010000L
1487#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x00000010
1488#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x00000400L
1489#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x0000000a
1490#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x00020000L
1491#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x00000011
1492#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x00008000L
1493#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0x0000000f
1494#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x00040000L
1495#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x00000012
1496#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x00000200L
1497#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x00000009
1498#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x00000800L
1499#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x0000000b
1500#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L
1501#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e
1502#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL
1503#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000
1504#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L
1505#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007
1506#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L
1507#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000
1508#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L
1509#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001
1510#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L
1511#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004
1512#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L
1513#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005
1514#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L
1515#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002
1516#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L
1517#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003
1518#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L
1519#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018
1520#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
1521#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
1522#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
1523#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
1524#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
1525#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
1526#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
1527#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
1528#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
1529#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
1530#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
1531#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
1532#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
1533#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
1534#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
1535#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
1536#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L
1537#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018
1538#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
1539#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
1540#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
1541#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
1542#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
1543#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
1544#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
1545#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
1546#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
1547#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
1548#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
1549#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
1550#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
1551#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
1552#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
1553#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
1554#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L
1555#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008
1556#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L
1557#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000
1558#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L
1559#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001
1560#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L
1561#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002
1562#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L
1563#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003
1564#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L
1565#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004
1566#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L
1567#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c
1568#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L
1569#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f
1570#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L
1571#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000
1572#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L
1573#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001
1574#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L
1575#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002
1576#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L
1577#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003
1578#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L
1579#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004
1580#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L
1581#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005
1582#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L
1583#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f
1584#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L
1585#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008
1586#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L
1587#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000
1588#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L
1589#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001
1590#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L
1591#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002
1592#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L
1593#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003
1594#define MC_CONFIG__MC_RD_ENABLE_MASK 0x00000030L
1595#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004
1596#define MC_HUB_MISC_DBG__SELECT0_MASK 0x0000000fL
1597#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x00000000
1598#define MC_HUB_MISC_DBG__SELECT1_MASK 0x000000f0L
1599#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x00000004
1600#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL
1601#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000
1602#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L
1603#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012
1604#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L
1605#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1606#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L
1607#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006
1608#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL
1609#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000
1610#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L
1611#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c
1612#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x00000001L
1613#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x00000000
1614#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x00000002L
1615#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x00000001
1616#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x00000400L
1617#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x0000000a
1618#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x00000800L
1619#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x0000000b
1620#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x00000004L
1621#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x00000002
1622#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x00000008L
1623#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x00000003
1624#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x00010000L
1625#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0x00000010
1626#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x00020000L
1627#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0x00000011
1628#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x00040000L
1629#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x00000012
1630#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x00080000L
1631#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x00000013
1632#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x00000040L
1633#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x00000006
1634#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x00000080L
1635#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x00000007
1636#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x00004000L
1637#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0x0000000e
1638#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x00008000L
1639#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0x0000000f
1640#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x00001000L
1641#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0x0000000c
1642#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x00002000L
1643#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0x0000000d
1644#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x01000000L
1645#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x00000018
1646#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x02000000L
1647#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x00000019
1648#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x00100000L
1649#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x00000014
1650#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x00200000L
1651#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x00000015
1652#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L
1653#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000
1654#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L
1655#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003
1656#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L
1657#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002
1658#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L
1659#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012
1660#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L
1661#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1662#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L
1663#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006
1664#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL
1665#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000
1666#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L
1667#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c
1668#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x00002000L
1669#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x0000000d
1670#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x00000004L
1671#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x00000002
1672#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x00000008L
1673#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x00000003
1674#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x00000010L
1675#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x00000004
1676#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x00000020L
1677#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x00000005
1678#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x00000100L
1679#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x00000008
1680#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x00000200L
1681#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x00000009
1682#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L
1683#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000
1684#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x00000040L
1685#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x00000006
1686#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x00000080L
1687#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x00000007
1688#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L
1689#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001
1690#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x00001000L
1691#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x0000000c
1692#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x00000400L
1693#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0x0000000a
1694#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x00000800L
1695#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x0000000b
1696#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L
1697#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012
1698#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L
1699#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1700#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L
1701#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006
1702#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL
1703#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000
1704#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L
1705#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c
1706#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x00000200L
1707#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x00000009
1708#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x0001fc00L
1709#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0x0000000a
1710#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00020000L
1711#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x00000011
1712#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00040000L
1713#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x00000012
1714#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L
1715#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002
1716#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L
1717#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003
1718#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L
1719#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005
1720#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L
1721#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006
1722#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L
1723#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007
1724#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L
1725#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008
1726#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L
1727#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004
1728#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x00080000L
1729#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x00000013
1730#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L
1731#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000
1732#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0x000000ffL
1733#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x00000000
1734#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L
1735#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010
1736#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L
1737#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018
1738#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL
1739#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000
1740#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L
1741#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008
1742#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L
1743#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
1744#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L
1745#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000
1746#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L
1747#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b
1748#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L
1749#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000
1750#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL
1751#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002
1752#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L
1753#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007
1754#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L
1755#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001
1756#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L
1757#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004
1758#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L
1759#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006
1760#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
1761#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1762#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL
1763#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000
1764#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL
1765#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000
1766#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L
1767#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
1768#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L
1769#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000
1770#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L
1771#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b
1772#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L
1773#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007
1774#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L
1775#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001
1776#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L
1777#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004
1778#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L
1779#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006
1780#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
1781#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1782#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L
1783#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b
1784#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L
1785#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001
1786#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L
1787#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002
1788#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L
1789#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012
1790#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L
1791#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000
1792#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L
1793#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007
1794#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L
1795#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003
1796#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000L
1797#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x00000019
1798#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L
1799#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b
1800#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L
1801#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001
1802#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L
1803#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002
1804#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L
1805#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012
1806#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L
1807#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000
1808#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L
1809#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007
1810#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L
1811#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003
1812#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000L
1813#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x00000019
1814#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L
1815#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b
1816#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L
1817#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001
1818#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L
1819#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002
1820#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L
1821#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012
1822#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L
1823#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000
1824#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L
1825#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007
1826#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L
1827#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003
1828#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000L
1829#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x00000019
1830#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L
1831#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b
1832#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L
1833#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001
1834#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L
1835#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002
1836#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L
1837#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012
1838#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L
1839#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000
1840#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L
1841#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007
1842#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L
1843#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003
1844#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000L
1845#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x00000019
1846#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L
1847#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
1848#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L
1849#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000
1850#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L
1851#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b
1852#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L
1853#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007
1854#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L
1855#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001
1856#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L
1857#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004
1858#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L
1859#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006
1860#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
1861#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1862#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L
1863#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003
1864#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L
1865#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000
1866#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L
1867#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b
1868#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L
1869#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007
1870#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L
1871#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001
1872#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L
1873#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004
1874#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L
1875#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006
1876#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L
1877#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1878#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L
1879#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003
1880#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L
1881#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000
1882#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L
1883#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b
1884#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L
1885#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007
1886#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L
1887#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001
1888#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L
1889#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004
1890#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L
1891#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006
1892#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L
1893#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1894#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL
1895#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000
1896#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L
1897#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008
1898#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x00000080L
1899#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x00000007
1900#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L
1901#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003
1902#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L
1903#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000
1904#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L
1905#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b
1906#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L
1907#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007
1908#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L
1909#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001
1910#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L
1911#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004
1912#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L
1913#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006
1914#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L
1915#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1916#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L
1917#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007
1918#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x00000040L
1919#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006
1920#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x00000020L
1921#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x00000005
1922#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L
1923#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a
1924#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x00000200L
1925#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009
1926#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x00000100L
1927#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x00000008
1928#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L
1929#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001
1930#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L
1931#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002
1932#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L
1933#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003
1934#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L
1935#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004
1936#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x00000800L
1937#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0x0000000b
1938#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L
1939#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000
1940#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L
1941#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
1942#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L
1943#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000
1944#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L
1945#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b
1946#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L
1947#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007
1948#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L
1949#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001
1950#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L
1951#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004
1952#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L
1953#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006
1954#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
1955#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1956#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L
1957#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003
1958#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L
1959#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000
1960#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L
1961#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b
1962#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L
1963#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007
1964#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L
1965#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001
1966#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L
1967#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004
1968#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L
1969#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006
1970#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L
1971#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1972#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L
1973#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010
1974#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L
1975#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003
1976#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x00000001L
1977#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x00000000
1978#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x00007800L
1979#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0x0000000b
1980#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x00000780L
1981#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x00000007
1982#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x00000006L
1983#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x00000001
1984#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x00000030L
1985#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x00000004
1986#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x00000040L
1987#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x00000006
1988#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L
1989#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1990#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L
1991#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003
1992#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x00000001L
1993#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x00000000
1994#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x00007800L
1995#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0x0000000b
1996#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x00000780L
1997#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x00000007
1998#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x00000006L
1999#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x00000001
2000#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x00000030L
2001#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x00000004
2002#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x00000040L
2003#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x00000006
2004#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L
2005#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2006#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L
2007#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
2008#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L
2009#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000
2010#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L
2011#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b
2012#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L
2013#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007
2014#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L
2015#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001
2016#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L
2017#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004
2018#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L
2019#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006
2020#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
2021#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2022#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
2023#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
2024#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
2025#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
2026#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
2027#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
2028#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
2029#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
2030#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
2031#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
2032#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
2033#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
2034#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
2035#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
2036#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
2037#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
2038#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L
2039#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003
2040#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L
2041#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000
2042#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L
2043#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b
2044#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L
2045#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007
2046#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L
2047#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001
2048#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L
2049#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004
2050#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L
2051#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006
2052#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L
2053#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2054#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x001f0000L
2055#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010
2056#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL
2057#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000
2058#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L
2059#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018
2060#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L
2061#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000
2062#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL
2063#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001
2064#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L
2065#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012
2066#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L
2067#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005
2068#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L
2069#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d
2070#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L
2071#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e
2072#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L
2073#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f
2074#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L
2075#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012
2076#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L
2077#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010
2078#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L
2079#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001
2080#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L
2081#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002
2082#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L
2083#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003
2084#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L
2085#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011
2086#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L
2087#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013
2088#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L
2089#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004
2090#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L
2091#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014
2092#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L
2093#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010
2094#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L
2095#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018
2096#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL
2097#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000
2098#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L
2099#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008
2100#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L
2101#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000
2102#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L
2103#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001
2104#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L
2105#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004
2106#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL
2107#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000
2108#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L
2109#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010
2110#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L
2111#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008
2112#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L
2113#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004
2114#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL
2115#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000
2116#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L
2117#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010
2118#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L
2119#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008
2120#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L
2121#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
2122#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L
2123#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000
2124#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L
2125#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b
2126#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L
2127#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007
2128#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L
2129#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001
2130#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L
2131#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004
2132#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L
2133#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006
2134#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
2135#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2136#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L
2137#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003
2138#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L
2139#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000
2140#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L
2141#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b
2142#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L
2143#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007
2144#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L
2145#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001
2146#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L
2147#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004
2148#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L
2149#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006
2150#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L
2151#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2152#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L
2153#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007
2154#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L
2155#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018
2156#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L
2157#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001
2158#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L
2159#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000
2160#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L
2161#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d
2162#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L
2163#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003
2164#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L
2165#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002
2166#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L
2167#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011
2168#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L
2169#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007
2170#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L
2171#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018
2172#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L
2173#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001
2174#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L
2175#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000
2176#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L
2177#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d
2178#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L
2179#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003
2180#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L
2181#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002
2182#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L
2183#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011
2184#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L
2185#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007
2186#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L
2187#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018
2188#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L
2189#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001
2190#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L
2191#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000
2192#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L
2193#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d
2194#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L
2195#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003
2196#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L
2197#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002
2198#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L
2199#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011
2200#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L
2201#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007
2202#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L
2203#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018
2204#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L
2205#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001
2206#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L
2207#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000
2208#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L
2209#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d
2210#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L
2211#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003
2212#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L
2213#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002
2214#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L
2215#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011
2216#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L
2217#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
2218#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L
2219#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000
2220#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L
2221#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b
2222#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L
2223#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007
2224#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L
2225#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001
2226#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L
2227#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004
2228#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L
2229#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006
2230#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
2231#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2232#define MC_HUB_WDP_MGPU2__CID2_MASK 0x000000ffL
2233#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x00000000
2234#define MC_HUB_WDP_MGPU__CID_MASK 0x0000ff00L
2235#define MC_HUB_WDP_MGPU__CID__SHIFT 0x00000008
2236#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x00800000L
2237#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x00000017
2238#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x007f0000L
2239#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x00000010
2240#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000L
2241#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x00000018
2242#define MC_HUB_WDP_MGPU__STOR_MASK 0x000000ffL
2243#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x00000000
2244#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L
2245#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003
2246#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L
2247#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000
2248#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L
2249#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b
2250#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L
2251#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007
2252#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L
2253#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001
2254#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L
2255#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004
2256#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L
2257#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006
2258#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L
2259#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2260#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L
2261#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003
2262#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L
2263#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000
2264#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L
2265#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b
2266#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L
2267#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007
2268#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L
2269#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001
2270#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L
2271#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004
2272#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L
2273#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006
2274#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L
2275#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2276#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L
2277#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003
2278#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L
2279#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000
2280#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L
2281#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b
2282#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L
2283#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007
2284#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L
2285#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001
2286#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L
2287#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004
2288#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L
2289#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006
2290#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L
2291#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2292#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L
2293#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003
2294#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L
2295#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000
2296#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L
2297#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b
2298#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L
2299#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007
2300#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L
2301#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001
2302#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L
2303#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004
2304#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L
2305#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006
2306#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L
2307#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2308#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL
2309#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002
2310#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L
2311#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000
2312#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L
2313#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003
2314#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L
2315#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000
2316#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L
2317#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b
2318#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L
2319#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007
2320#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L
2321#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001
2322#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L
2323#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004
2324#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L
2325#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006
2326#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L
2327#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2328#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L
2329#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007
2330#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x00000040L
2331#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006
2332#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x00000020L
2333#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x00000005
2334#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L
2335#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a
2336#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x00000200L
2337#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009
2338#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x00000100L
2339#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x00000008
2340#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L
2341#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001
2342#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x00000800L
2343#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x0000000b
2344#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L
2345#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002
2346#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x00001000L
2347#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0x0000000c
2348#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L
2349#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003
2350#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x00002000L
2351#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0x0000000d
2352#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L
2353#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004
2354#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x00004000L
2355#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0x0000000e
2356#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L
2357#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000
2358#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L
2359#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
2360#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L
2361#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000
2362#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L
2363#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b
2364#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L
2365#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007
2366#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L
2367#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001
2368#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L
2369#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004
2370#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L
2371#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006
2372#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
2373#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2374#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L
2375#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003
2376#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L
2377#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000
2378#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L
2379#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b
2380#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L
2381#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007
2382#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L
2383#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001
2384#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L
2385#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004
2386#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L
2387#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006
2388#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L
2389#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2390#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L
2391#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010
2392#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L
2393#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003
2394#define MC_HUB_WDP_VCE__ENABLE_MASK 0x00000001L
2395#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x00000000
2396#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x00007800L
2397#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0x0000000b
2398#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x00000780L
2399#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x00000007
2400#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x00000006L
2401#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x00000001
2402#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x00000030L
2403#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x00000004
2404#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x00000040L
2405#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x00000006
2406#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L
2407#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2408#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L
2409#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003
2410#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x00000001L
2411#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x00000000
2412#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x00007800L
2413#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0x0000000b
2414#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x00000780L
2415#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x00000007
2416#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x00000006L
2417#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x00000001
2418#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x00000030L
2419#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x00000004
2420#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x00000040L
2421#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x00000006
2422#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L
2423#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2424#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
2425#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
2426#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
2427#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
2428#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
2429#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
2430#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
2431#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
2432#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
2433#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
2434#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
2435#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
2436#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
2437#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
2438#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
2439#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
2440#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L
2441#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003
2442#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L
2443#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010
2444#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L
2445#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000
2446#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L
2447#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b
2448#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L
2449#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007
2450#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L
2451#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003
2452#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L
2453#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010
2454#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L
2455#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000
2456#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L
2457#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b
2458#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L
2459#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007
2460#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L
2461#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001
2462#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L
2463#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004
2464#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L
2465#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006
2466#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L
2467#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2468#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L
2469#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001
2470#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L
2471#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004
2472#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L
2473#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006
2474#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L
2475#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2476#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L
2477#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
2478#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L
2479#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000
2480#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L
2481#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b
2482#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L
2483#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007
2484#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L
2485#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001
2486#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L
2487#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004
2488#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L
2489#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006
2490#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
2491#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2492#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L
2493#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015
2494#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL
2495#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001
2496#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L
2497#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016
2498#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L
2499#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e
2500#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L
2501#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f
2502#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L
2503#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000
2504#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL
2505#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001
2506#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L
2507#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000
2508#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL
2509#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001
2510#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L
2511#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000
2512#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL
2513#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001
2514#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L
2515#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000
2516#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL
2517#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001
2518#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L
2519#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000
2520#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L
2521#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000
2522#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L
2523#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001
2524#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L
2525#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002
2526#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L
2527#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003
2528#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000L
2529#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x0000001f
2530#define MC_IMP_CNTL__CAL_VREF_MASK 0x007f0000L
2531#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x00000040L
2532#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x00000006
2533#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x00000020L
2534#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x00000005
2535#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x00000010
2536#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000L
2537#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x0000001d
2538#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000L
2539#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x0000001e
2540#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x00000200L
2541#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x00000009
2542#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0x0000e000L
2543#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0x0000000d
2544#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x0000001fL
2545#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x00000000
2546#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x00000100L
2547#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x00000008
2548#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000L
2549#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x0000001f
2550#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000L
2551#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x0000001c
2552#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000L
2553#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x0000001e
2554#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000L
2555#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x0000001d
2556#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0x0fff0000L
2557#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x00000010
2558#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0x0000ff00L
2559#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x00000008
2560#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0x000000ffL
2561#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x00000000
2562#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0x0000ff00L
2563#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008
2564#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0x000000ffL
2565#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x00000000
2566#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000L
2567#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x00000018
2568#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0x00ff0000L
2569#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x00000010
2570#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000L
2571#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x00000018
2572#define MC_IMP_STATUS__NSTR_CAL_MASK 0x00ff0000L
2573#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x00000010
2574#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0x0000ff00L
2575#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x00000008
2576#define MC_IMP_STATUS__PSTR_CAL_MASK 0x000000ffL
2577#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x00000000
2578#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L
2579#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a
2580#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000L
2581#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x0000001c
2582#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000L
2583#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x0000001d
2584#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0x00000fc0L
2585#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x00000006
2586#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x0000003fL
2587#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x00000000
2588#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x0003f000L
2589#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0x0000000c
2590#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x01000000L
2591#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x00000018
2592#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x02000000L
2593#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x00000019
2594#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L
2595#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a
2596#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000L
2597#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x0000001c
2598#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000L
2599#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x0000001d
2600#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0x00000fc0L
2601#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x00000006
2602#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x0000003fL
2603#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x00000000
2604#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x0003f000L
2605#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0x0000000c
2606#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x01000000L
2607#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x00000018
2608#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x02000000L
2609#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x00000019
2610#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0x000000ffL
2611#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x00000000
2612#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0x0000ff00L
2613#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x00000008
2614#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0x00ff0000L
2615#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x00000010
2616#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000L
2617#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x00000018
2618#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0x000000ffL
2619#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x00000000
2620#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0x0000ff00L
2621#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x00000008
2622#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0x00ff0000L
2623#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x00000010
2624#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000L
2625#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x00000018
2626#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x00000001L
2627#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x00000000
2628#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x00000002L
2629#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x00000001
2630#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x00000004L
2631#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x00000002
2632#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x00000008L
2633#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x00000003
2634#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x00000010L
2635#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x00000004
2636#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x00000020L
2637#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x00000005
2638#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x00000040L
2639#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x00000006
2640#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x00000080L
2641#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x00000007
2642#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x00000001L
2643#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x00000000
2644#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x00000002L
2645#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x00000001
2646#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x00000004L
2647#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x00000002
2648#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x00000008L
2649#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x00000003
2650#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x00000010L
2651#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x00000004
2652#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x00000020L
2653#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x00000005
2654#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x00000040L
2655#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x00000006
2656#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x00000080L
2657#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x00000007
2658#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x00400000L
2659#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x00000016
2660#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x00800000L
2661#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x00000017
2662#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000L
2663#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x0000001c
2664#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000L
2665#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x0000001d
2666#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x00100000L
2667#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x00000014
2668#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x00200000L
2669#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x00000015
2670#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000L
2671#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x0000001e
2672#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000L
2673#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x0000001f
2674#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x00000400L
2675#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0x0000000a
2676#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x00000800L
2677#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0x0000000b
2678#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x00000100L
2679#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x00000008
2680#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x00000200L
2681#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x00000009
2682#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0x0000f000L
2683#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0x0000000c
2684#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0x000f0000L
2685#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x00000010
2686#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0x0000000fL
2687#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x00000000
2688#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0x000000f0L
2689#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x00000004
2690#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x04000000L
2691#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x0000001a
2692#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x08000000L
2693#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x0000001b
2694#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x01000000L
2695#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x00000018
2696#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x02000000L
2697#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x00000019
2698#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x00400000L
2699#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x00000016
2700#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x00800000L
2701#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x00000017
2702#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000L
2703#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x0000001c
2704#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000L
2705#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x0000001d
2706#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x00100000L
2707#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x00000014
2708#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x00200000L
2709#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x00000015
2710#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000L
2711#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x0000001e
2712#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000L
2713#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x0000001f
2714#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x00000400L
2715#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0x0000000a
2716#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x00000800L
2717#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0x0000000b
2718#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x00000100L
2719#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x00000008
2720#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x00000200L
2721#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x00000009
2722#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0x0000f000L
2723#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0x0000000c
2724#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0x000f0000L
2725#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x00000010
2726#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0x0000000fL
2727#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x00000000
2728#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0x000000f0L
2729#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x00000004
2730#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x04000000L
2731#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x0000001a
2732#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x08000000L
2733#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x0000001b
2734#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x01000000L
2735#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x00000018
2736#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x02000000L
2737#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x00000019
2738#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL
2739#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000
2740#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
2741#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008
2742#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
2743#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010
2744#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000L
2745#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018
2746#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL
2747#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000
2748#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
2749#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008
2750#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
2751#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010
2752#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000L
2753#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018
2754#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0x000000ffL
2755#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x00000000
2756#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0x0000ff00L
2757#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x00000008
2758#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0x00ff0000L
2759#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x00000010
2760#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000L
2761#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x00000018
2762#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0x000000ffL
2763#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x00000000
2764#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0x0000ff00L
2765#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x00000008
2766#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0x00ff0000L
2767#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x00000010
2768#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000L
2769#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x00000018
2770#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL
2771#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000
2772#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
2773#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008
2774#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
2775#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010
2776#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000L
2777#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018
2778#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL
2779#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000
2780#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
2781#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008
2782#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
2783#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010
2784#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000L
2785#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018
2786#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL
2787#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000
2788#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
2789#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008
2790#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
2791#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010
2792#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000L
2793#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018
2794#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL
2795#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000
2796#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
2797#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008
2798#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
2799#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010
2800#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000L
2801#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018
2802#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
2803#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
2804#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
2805#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
2806#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
2807#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
2808#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L
2809#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
2810#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
2811#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
2812#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
2813#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
2814#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
2815#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
2816#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L
2817#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
2818#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
2819#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
2820#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
2821#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
2822#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
2823#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
2824#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L
2825#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
2826#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
2827#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
2828#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
2829#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
2830#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
2831#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
2832#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L
2833#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
2834#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL
2835#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000
2836#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
2837#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008
2838#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
2839#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010
2840#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000L
2841#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018
2842#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL
2843#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000
2844#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
2845#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008
2846#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
2847#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010
2848#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000L
2849#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018
2850#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0x000000ffL
2851#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x00000000
2852#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L
2853#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x00000008
2854#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L
2855#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x00000010
2856#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000L
2857#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x00000018
2858#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0x000000ffL
2859#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x00000000
2860#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L
2861#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x00000008
2862#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L
2863#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x00000010
2864#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000L
2865#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x00000018
2866#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0x000000ffL
2867#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x00000000
2868#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
2869#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x00000008
2870#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
2871#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x00000010
2872#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000L
2873#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x00000018
2874#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0x000000ffL
2875#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x00000000
2876#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
2877#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x00000008
2878#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
2879#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x00000010
2880#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000L
2881#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x00000018
2882#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0x000000ffL
2883#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x00000000
2884#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0x0000ff00L
2885#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x00000008
2886#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0x00ff0000L
2887#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x00000010
2888#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000L
2889#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x00000018
2890#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0x000000ffL
2891#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x00000000
2892#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0x0000ff00L
2893#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x00000008
2894#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0x00ff0000L
2895#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x00000010
2896#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000L
2897#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x00000018
2898#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0x000000ffL
2899#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x00000000
2900#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
2901#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x00000008
2902#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
2903#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x00000010
2904#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000L
2905#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x00000018
2906#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0x000000ffL
2907#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x00000000
2908#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
2909#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x00000008
2910#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
2911#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x00000010
2912#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000L
2913#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x00000018
2914#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
2915#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
2916#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
2917#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
2918#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
2919#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
2920#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000L
2921#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
2922#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
2923#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
2924#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
2925#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
2926#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
2927#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
2928#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000L
2929#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
2930#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
2931#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
2932#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
2933#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
2934#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
2935#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
2936#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000L
2937#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
2938#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
2939#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
2940#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
2941#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
2942#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
2943#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
2944#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000L
2945#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
2946#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0x000000ffL
2947#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x00000000
2948#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
2949#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x00000008
2950#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
2951#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x00000010
2952#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000L
2953#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x00000018
2954#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0x000000ffL
2955#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x00000000
2956#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
2957#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x00000008
2958#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
2959#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x00000010
2960#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000L
2961#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x00000018
2962#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0x000000ffL
2963#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x00000000
2964#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0x0000ff00L
2965#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x00000008
2966#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0x00ff0000L
2967#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x00000010
2968#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000L
2969#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x00000018
2970#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0x000000ffL
2971#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x00000000
2972#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0x0000ff00L
2973#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x00000008
2974#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0x00ff0000L
2975#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x00000010
2976#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000L
2977#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x00000018
2978#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0x000000ffL
2979#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x00000000
2980#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
2981#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x00000008
2982#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
2983#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x00000010
2984#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000L
2985#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x00000018
2986#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0x000000ffL
2987#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x00000000
2988#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
2989#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x00000008
2990#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
2991#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x00000010
2992#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000L
2993#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x00000018
2994#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0x000000ffL
2995#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x00000000
2996#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0x0000ff00L
2997#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x00000008
2998#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0x00ff0000L
2999#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x00000010
3000#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000L
3001#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x00000018
3002#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0x000000ffL
3003#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x00000000
3004#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0x0000ff00L
3005#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x00000008
3006#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0x00ff0000L
3007#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x00000010
3008#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000L
3009#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x00000018
3010#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3011#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3012#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3013#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3014#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3015#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3016#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000L
3017#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3018#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3019#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3020#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3021#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3022#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3023#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3024#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000L
3025#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3026#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3027#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3028#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3029#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3030#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3031#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3032#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3033#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3034#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3035#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3036#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3037#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3038#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3039#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3040#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3041#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3042#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3043#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3044#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3045#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3046#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3047#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3048#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3049#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3050#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3051#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3052#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3053#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3054#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3055#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3056#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3057#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3058#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3059#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3060#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3061#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3062#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3063#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3064#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000L
3065#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3066#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3067#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3068#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3069#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3070#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3071#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3072#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000L
3073#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3074#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0x000000ffL
3075#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x00000000
3076#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3077#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x00000008
3078#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3079#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x00000010
3080#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000L
3081#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x00000018
3082#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0x000000ffL
3083#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x00000000
3084#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3085#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x00000008
3086#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3087#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x00000010
3088#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000L
3089#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x00000018
3090#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3091#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3092#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3093#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3094#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3095#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3096#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000L
3097#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3098#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3099#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3100#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3101#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3102#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3103#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3104#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000L
3105#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3106#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0x000000ffL
3107#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x00000000
3108#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0x0000ff00L
3109#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x00000008
3110#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0x00ff0000L
3111#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x00000010
3112#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000L
3113#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x00000018
3114#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0x000000ffL
3115#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x00000000
3116#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0x0000ff00L
3117#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x00000008
3118#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0x00ff0000L
3119#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x00000010
3120#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000L
3121#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x00000018
3122#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3123#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3124#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3125#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3126#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3127#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3128#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000L
3129#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3130#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3131#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3132#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3133#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3134#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3135#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3136#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000L
3137#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3138#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3139#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3140#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3141#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3142#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3143#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3144#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3145#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3146#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3147#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3148#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3149#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3150#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3151#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3152#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3153#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3154#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3155#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3156#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3157#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3158#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3159#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3160#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3161#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3162#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3163#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3164#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3165#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3166#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3167#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3168#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3169#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3170#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3171#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3172#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3173#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3174#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3175#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3176#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000L
3177#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3178#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3179#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3180#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3181#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3182#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3183#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3184#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000L
3185#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3186#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0x000000ffL
3187#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x00000000
3188#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3189#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x00000008
3190#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3191#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x00000010
3192#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000L
3193#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x00000018
3194#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0x000000ffL
3195#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x00000000
3196#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3197#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x00000008
3198#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3199#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x00000010
3200#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000L
3201#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x00000018
3202#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3203#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3204#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3205#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3206#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3207#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3208#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000L
3209#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3210#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3211#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3212#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3213#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3214#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3215#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3216#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000L
3217#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3218#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0x000000ffL
3219#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x00000000
3220#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0x0000ff00L
3221#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x00000008
3222#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0x00ff0000L
3223#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x00000010
3224#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000L
3225#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x00000018
3226#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0x000000ffL
3227#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x00000000
3228#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0x0000ff00L
3229#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x00000008
3230#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0x00ff0000L
3231#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x00000010
3232#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000L
3233#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x00000018
3234#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3235#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3236#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3237#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3238#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3239#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3240#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000L
3241#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3242#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3243#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3244#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3245#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3246#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3247#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3248#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000L
3249#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3250#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3251#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3252#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3253#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3254#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3255#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3256#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000L
3257#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3258#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3259#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3260#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3261#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3262#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3263#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3264#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000L
3265#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3266#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3267#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3268#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3269#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3270#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3271#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3272#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000L
3273#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3274#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3275#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3276#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3277#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3278#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3279#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3280#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000L
3281#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3282#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3283#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3284#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3285#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3286#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3287#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3288#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3289#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3290#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3291#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3292#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3293#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3294#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3295#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3296#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3297#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3298#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3299#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3300#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3301#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3302#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3303#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3304#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3305#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3306#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3307#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3308#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3309#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3310#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3311#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3312#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3313#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3314#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3315#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3316#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3317#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3318#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3319#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3320#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000L
3321#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3322#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3323#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3324#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3325#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3326#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3327#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3328#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000L
3329#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3330#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0x000000ffL
3331#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x00000000
3332#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3333#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x00000008
3334#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3335#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x00000010
3336#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000L
3337#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x00000018
3338#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0x000000ffL
3339#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x00000000
3340#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3341#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x00000008
3342#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3343#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x00000010
3344#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000L
3345#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x00000018
3346#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
3347#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
3348#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
3349#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
3350#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
3351#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
3352#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
3353#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
3354#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
3355#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
3356#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
3357#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
3358#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
3359#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
3360#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
3361#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
3362#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3363#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3364#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3365#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3366#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3367#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3368#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000L
3369#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3370#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3371#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3372#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3373#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3374#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3375#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3376#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000L
3377#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3378#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0x000000ffL
3379#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x00000000
3380#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0x0000ff00L
3381#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x00000008
3382#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0x00ff0000L
3383#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x00000010
3384#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000L
3385#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x00000018
3386#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0x000000ffL
3387#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x00000000
3388#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0x0000ff00L
3389#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x00000008
3390#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0x00ff0000L
3391#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x00000010
3392#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000L
3393#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x00000018
3394#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3395#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3396#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3397#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3398#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3399#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3400#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000L
3401#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3402#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3403#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3404#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3405#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3406#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3407#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3408#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000L
3409#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3410#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3411#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3412#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3413#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3414#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3415#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3416#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000L
3417#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3418#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3419#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3420#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3421#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3422#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3423#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3424#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000L
3425#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3426#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3427#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3428#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3429#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3430#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3431#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3432#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000L
3433#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3434#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3435#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3436#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3437#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3438#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3439#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3440#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000L
3441#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3442#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
3443#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
3444#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
3445#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
3446#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
3447#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
3448#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
3449#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
3450#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
3451#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
3452#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
3453#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
3454#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
3455#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
3456#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
3457#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
3458#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3459#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3460#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3461#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3462#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3463#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3464#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3465#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3466#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3467#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3468#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3469#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3470#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3471#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3472#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3473#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3474#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3475#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3476#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3477#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3478#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3479#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3480#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3481#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3482#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3483#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3484#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3485#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3486#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3487#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3488#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3489#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3490#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3491#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3492#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3493#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3494#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3495#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3496#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000L
3497#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3498#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3499#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3500#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3501#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3502#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3503#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3504#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000L
3505#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3506#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0x000000ffL
3507#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x00000000
3508#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3509#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x00000008
3510#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3511#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x00000010
3512#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000L
3513#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x00000018
3514#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0x000000ffL
3515#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x00000000
3516#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3517#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x00000008
3518#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3519#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x00000010
3520#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000L
3521#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x00000018
3522#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL
3523#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000
3524#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L
3525#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008
3526#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L
3527#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010
3528#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L
3529#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018
3530#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL
3531#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000
3532#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L
3533#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008
3534#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L
3535#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010
3536#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L
3537#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018
3538#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL
3539#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000
3540#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L
3541#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008
3542#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L
3543#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010
3544#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L
3545#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018
3546#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL
3547#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000
3548#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L
3549#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008
3550#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L
3551#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010
3552#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L
3553#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018
3554#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL
3555#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000
3556#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L
3557#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008
3558#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L
3559#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010
3560#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L
3561#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018
3562#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL
3563#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000
3564#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L
3565#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008
3566#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L
3567#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010
3568#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L
3569#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018
3570#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL
3571#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000
3572#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L
3573#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008
3574#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L
3575#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010
3576#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L
3577#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018
3578#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL
3579#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000
3580#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L
3581#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008
3582#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L
3583#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010
3584#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L
3585#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018
3586#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
3587#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
3588#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
3589#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
3590#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
3591#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
3592#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
3593#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
3594#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
3595#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
3596#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
3597#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
3598#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
3599#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
3600#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
3601#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
3602#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3603#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3604#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3605#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3606#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3607#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3608#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000L
3609#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3610#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3611#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3612#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3613#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3614#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3615#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3616#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000L
3617#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3618#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0x000000ffL
3619#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x00000000
3620#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0x0000ff00L
3621#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x00000008
3622#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0x00ff0000L
3623#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x00000010
3624#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000L
3625#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x00000018
3626#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0x000000ffL
3627#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x00000000
3628#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0x0000ff00L
3629#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x00000008
3630#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0x00ff0000L
3631#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x00000010
3632#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000L
3633#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x00000018
3634#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3635#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3636#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3637#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3638#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3639#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3640#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000L
3641#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3642#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3643#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3644#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3645#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3646#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3647#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3648#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000L
3649#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3650#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3651#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3652#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3653#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3654#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3655#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3656#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000L
3657#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3658#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3659#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3660#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3661#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3662#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3663#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3664#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000L
3665#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3666#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3667#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3668#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3669#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3670#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3671#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3672#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000L
3673#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3674#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3675#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3676#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3677#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3678#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3679#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3680#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000L
3681#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3682#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
3683#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
3684#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
3685#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
3686#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
3687#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
3688#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
3689#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
3690#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
3691#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
3692#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
3693#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
3694#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
3695#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
3696#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
3697#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
3698#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3699#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3700#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3701#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3702#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3703#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3704#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3705#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3706#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3707#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3708#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3709#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3710#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3711#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3712#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3713#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3714#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3715#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3716#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3717#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3718#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3719#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3720#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3721#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3722#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3723#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3724#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3725#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3726#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3727#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3728#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3729#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3730#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3731#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3732#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3733#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3734#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3735#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3736#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000L
3737#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3738#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3739#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3740#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3741#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3742#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3743#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3744#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000L
3745#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3746#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0x000000ffL
3747#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x00000000
3748#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3749#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x00000008
3750#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3751#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x00000010
3752#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000L
3753#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x00000018
3754#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0x000000ffL
3755#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x00000000
3756#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3757#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x00000008
3758#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3759#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x00000010
3760#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000L
3761#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x00000018
3762#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3763#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3764#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3765#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3766#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3767#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3768#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000L
3769#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3770#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3771#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3772#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3773#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3774#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3775#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3776#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000L
3777#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3778#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0x000000ffL
3779#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x00000000
3780#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0x0000ff00L
3781#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x00000008
3782#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0x00ff0000L
3783#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x00000010
3784#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000L
3785#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x00000018
3786#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0x000000ffL
3787#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x00000000
3788#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0x0000ff00L
3789#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x00000008
3790#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0x00ff0000L
3791#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x00000010
3792#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000L
3793#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x00000018
3794#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3795#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3796#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3797#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3798#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3799#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3800#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000L
3801#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3802#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3803#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3804#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3805#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3806#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3807#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3808#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000L
3809#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3810#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3811#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3812#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3813#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3814#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3815#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3816#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000L
3817#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3818#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3819#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3820#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3821#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3822#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3823#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3824#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000L
3825#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3826#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3827#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3828#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3829#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3830#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3831#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3832#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000L
3833#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3834#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3835#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3836#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3837#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3838#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3839#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3840#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000L
3841#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3842#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
3843#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
3844#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
3845#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
3846#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
3847#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
3848#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
3849#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
3850#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
3851#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
3852#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
3853#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
3854#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
3855#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
3856#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
3857#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
3858#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3859#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3860#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3861#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3862#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3863#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3864#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3865#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3866#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3867#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3868#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3869#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3870#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3871#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3872#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3873#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3874#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3875#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3876#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3877#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3878#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3879#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3880#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3881#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3882#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3883#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3884#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3885#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3886#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3887#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3888#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3889#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3890#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3891#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3892#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3893#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3894#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3895#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3896#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000L
3897#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3898#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3899#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3900#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3901#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3902#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3903#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3904#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000L
3905#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3906#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0x000000ffL
3907#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x00000000
3908#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3909#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x00000008
3910#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3911#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x00000010
3912#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000L
3913#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x00000018
3914#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0x000000ffL
3915#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x00000000
3916#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3917#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x00000008
3918#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3919#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x00000010
3920#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000L
3921#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x00000018
3922#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
3923#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
3924#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
3925#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
3926#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
3927#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
3928#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
3929#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
3930#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
3931#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
3932#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
3933#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
3934#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
3935#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
3936#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
3937#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
3938#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3939#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3940#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3941#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3942#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3943#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3944#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000L
3945#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3946#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3947#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3948#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3949#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3950#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3951#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3952#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000L
3953#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3954#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0x000000ffL
3955#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x00000000
3956#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0x0000ff00L
3957#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x00000008
3958#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0x00ff0000L
3959#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x00000010
3960#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000L
3961#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x00000018
3962#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0x000000ffL
3963#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x00000000
3964#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0x0000ff00L
3965#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x00000008
3966#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0x00ff0000L
3967#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x00000010
3968#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000L
3969#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x00000018
3970#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3971#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3972#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3973#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3974#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3975#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3976#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000L
3977#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3978#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3979#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3980#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3981#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3982#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3983#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3984#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000L
3985#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3986#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3987#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3988#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3989#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3990#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3991#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3992#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000L
3993#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3994#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3995#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3996#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3997#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3998#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3999#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4000#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000L
4001#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4002#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4003#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4004#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4005#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4006#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4007#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4008#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000L
4009#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4010#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4011#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4012#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4013#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4014#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4015#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4016#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000L
4017#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4018#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4019#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4020#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4021#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4022#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4023#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4024#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4025#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4026#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4027#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4028#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4029#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4030#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4031#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4032#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4033#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4034#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4035#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4036#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4037#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4038#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4039#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4040#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4041#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4042#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4043#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4044#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4045#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4046#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4047#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4048#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4049#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4050#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4051#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4052#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4053#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4054#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4055#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4056#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4057#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4058#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4059#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4060#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4061#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4062#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4063#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4064#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4065#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4066#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4067#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4068#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4069#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4070#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4071#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4072#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000L
4073#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4074#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4075#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4076#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4077#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4078#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4079#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4080#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000L
4081#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4082#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0x000000ffL
4083#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x00000000
4084#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4085#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x00000008
4086#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4087#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x00000010
4088#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000L
4089#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x00000018
4090#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0x000000ffL
4091#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x00000000
4092#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4093#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x00000008
4094#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4095#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x00000010
4096#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000L
4097#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x00000018
4098#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4099#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4100#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4101#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4102#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4103#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4104#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000L
4105#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4106#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4107#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4108#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4109#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4110#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4111#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4112#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000L
4113#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4114#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0x000000ffL
4115#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x00000000
4116#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0x0000ff00L
4117#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x00000008
4118#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0x00ff0000L
4119#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x00000010
4120#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000L
4121#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x00000018
4122#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0x000000ffL
4123#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x00000000
4124#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0x0000ff00L
4125#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x00000008
4126#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0x00ff0000L
4127#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x00000010
4128#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000L
4129#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x00000018
4130#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4131#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4132#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4133#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4134#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4135#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4136#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000L
4137#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4138#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4139#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4140#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4141#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4142#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4143#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4144#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000L
4145#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4146#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4147#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4148#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4149#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4150#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4151#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4152#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000L
4153#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4154#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4155#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4156#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4157#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4158#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4159#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4160#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000L
4161#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4162#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4163#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4164#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4165#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4166#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4167#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4168#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000L
4169#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4170#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4171#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4172#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4173#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4174#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4175#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4176#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000L
4177#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4178#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4179#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4180#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4181#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4182#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4183#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4184#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4185#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4186#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4187#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4188#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4189#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4190#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4191#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4192#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4193#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4194#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4195#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4196#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4197#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4198#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4199#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4200#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4201#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4202#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4203#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4204#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4205#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4206#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4207#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4208#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4209#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4210#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4211#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4212#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4213#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4214#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4215#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4216#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4217#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4218#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4219#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4220#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4221#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4222#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4223#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4224#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4225#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4226#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4227#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4228#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4229#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4230#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4231#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4232#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000L
4233#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4234#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4235#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4236#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4237#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4238#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4239#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4240#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000L
4241#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4242#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0x000000ffL
4243#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x00000000
4244#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4245#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x00000008
4246#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4247#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x00000010
4248#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000L
4249#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x00000018
4250#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0x000000ffL
4251#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x00000000
4252#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4253#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x00000008
4254#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4255#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x00000010
4256#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000L
4257#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x00000018
4258#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
4259#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
4260#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
4261#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
4262#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
4263#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
4264#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
4265#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
4266#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
4267#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
4268#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
4269#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
4270#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
4271#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
4272#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
4273#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
4274#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4275#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4276#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4277#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4278#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4279#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4280#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000L
4281#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4282#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4283#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4284#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4285#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4286#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4287#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4288#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000L
4289#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4290#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0x000000ffL
4291#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x00000000
4292#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0x0000ff00L
4293#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x00000008
4294#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0x00ff0000L
4295#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x00000010
4296#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000L
4297#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x00000018
4298#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0x000000ffL
4299#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x00000000
4300#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0x0000ff00L
4301#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x00000008
4302#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0x00ff0000L
4303#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x00000010
4304#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000L
4305#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x00000018
4306#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4307#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4308#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4309#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4310#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4311#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4312#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000L
4313#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4314#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4315#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4316#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4317#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4318#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4319#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4320#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000L
4321#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4322#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4323#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4324#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4325#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4326#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4327#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4328#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000L
4329#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4330#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4331#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4332#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4333#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4334#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4335#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4336#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000L
4337#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4338#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4339#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4340#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4341#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4342#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4343#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4344#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000L
4345#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4346#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4347#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4348#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4349#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4350#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4351#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4352#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000L
4353#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4354#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4355#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4356#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4357#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4358#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4359#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4360#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4361#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4362#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4363#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4364#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4365#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4366#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4367#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4368#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4369#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4370#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4371#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4372#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4373#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4374#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4375#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4376#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4377#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4378#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4379#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4380#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4381#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4382#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4383#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4384#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4385#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4386#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4387#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4388#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4389#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4390#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4391#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4392#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4393#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4394#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4395#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4396#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4397#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4398#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4399#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4400#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4401#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4402#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4403#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4404#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4405#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4406#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4407#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4408#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000L
4409#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4410#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4411#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4412#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4413#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4414#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4415#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4416#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000L
4417#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4418#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0x000000ffL
4419#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x00000000
4420#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4421#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x00000008
4422#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4423#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x00000010
4424#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000L
4425#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x00000018
4426#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0x000000ffL
4427#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x00000000
4428#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4429#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x00000008
4430#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4431#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x00000010
4432#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000L
4433#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x00000018
4434#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4435#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4436#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4437#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4438#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4439#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4440#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000L
4441#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4442#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4443#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4444#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4445#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4446#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4447#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4448#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000L
4449#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4450#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0x000000ffL
4451#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x00000000
4452#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0x0000ff00L
4453#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x00000008
4454#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0x00ff0000L
4455#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x00000010
4456#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000L
4457#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x00000018
4458#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0x000000ffL
4459#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x00000000
4460#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0x0000ff00L
4461#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x00000008
4462#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0x00ff0000L
4463#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x00000010
4464#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000L
4465#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x00000018
4466#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4467#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4468#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4469#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4470#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4471#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4472#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000L
4473#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4474#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4475#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4476#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4477#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4478#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4479#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4480#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000L
4481#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4482#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4483#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4484#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4485#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4486#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4487#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4488#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000L
4489#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4490#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4491#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4492#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4493#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4494#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4495#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4496#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000L
4497#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4498#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4499#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4500#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4501#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4502#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4503#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4504#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000L
4505#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4506#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4507#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4508#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4509#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4510#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4511#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4512#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000L
4513#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4514#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4515#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4516#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4517#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4518#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4519#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4520#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4521#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4522#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4523#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4524#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4525#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4526#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4527#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4528#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4529#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4530#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4531#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4532#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4533#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4534#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4535#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4536#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4537#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4538#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4539#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4540#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4541#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4542#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4543#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4544#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4545#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4546#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4547#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4548#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4549#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4550#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4551#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4552#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4553#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4554#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4555#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4556#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4557#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4558#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4559#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4560#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4561#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4562#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4563#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4564#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4565#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4566#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4567#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4568#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000L
4569#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4570#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4571#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4572#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4573#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4574#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4575#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4576#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000L
4577#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4578#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0x000000ffL
4579#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x00000000
4580#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4581#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x00000008
4582#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4583#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x00000010
4584#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000L
4585#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x00000018
4586#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0x000000ffL
4587#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x00000000
4588#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4589#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x00000008
4590#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4591#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x00000010
4592#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000L
4593#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x00000018
4594#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
4595#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
4596#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
4597#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
4598#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
4599#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
4600#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
4601#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
4602#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
4603#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
4604#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
4605#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
4606#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
4607#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
4608#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
4609#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
4610#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4611#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4612#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4613#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4614#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4615#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4616#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000L
4617#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4618#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4619#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4620#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4621#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4622#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4623#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4624#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000L
4625#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4626#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0x000000ffL
4627#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x00000000
4628#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0x0000ff00L
4629#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x00000008
4630#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0x00ff0000L
4631#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x00000010
4632#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000L
4633#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x00000018
4634#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0x000000ffL
4635#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x00000000
4636#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0x0000ff00L
4637#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x00000008
4638#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0x00ff0000L
4639#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x00000010
4640#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000L
4641#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x00000018
4642#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4643#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4644#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4645#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4646#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4647#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4648#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000L
4649#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4650#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4651#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4652#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4653#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4654#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4655#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4656#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000L
4657#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4658#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4659#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4660#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4661#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4662#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4663#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4664#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000L
4665#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4666#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4667#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4668#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4669#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4670#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4671#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4672#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000L
4673#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4674#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4675#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4676#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4677#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4678#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4679#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4680#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000L
4681#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4682#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4683#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4684#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4685#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4686#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4687#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4688#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000L
4689#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4690#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4691#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4692#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4693#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4694#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4695#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4696#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4697#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4698#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4699#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4700#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4701#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4702#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4703#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4704#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4705#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4706#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4707#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4708#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4709#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4710#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4711#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4712#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4713#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4714#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4715#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4716#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4717#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4718#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4719#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4720#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4721#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4722#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4723#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4724#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4725#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4726#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4727#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4728#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4729#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4730#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4731#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4732#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4733#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4734#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4735#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4736#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4737#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4738#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4739#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4740#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4741#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4742#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4743#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4744#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000L
4745#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4746#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4747#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4748#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4749#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4750#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4751#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4752#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000L
4753#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4754#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0x000000ffL
4755#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x00000000
4756#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4757#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x00000008
4758#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4759#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x00000010
4760#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000L
4761#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x00000018
4762#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0x000000ffL
4763#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x00000000
4764#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4765#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x00000008
4766#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4767#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x00000010
4768#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000L
4769#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x00000018
4770#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4771#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4772#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4773#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4774#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4775#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4776#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000L
4777#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4778#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4779#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4780#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4781#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4782#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4783#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4784#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000L
4785#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4786#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0x000000ffL
4787#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x00000000
4788#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0x0000ff00L
4789#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x00000008
4790#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0x00ff0000L
4791#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x00000010
4792#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000L
4793#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x00000018
4794#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0x000000ffL
4795#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x00000000
4796#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0x0000ff00L
4797#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x00000008
4798#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0x00ff0000L
4799#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x00000010
4800#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000L
4801#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x00000018
4802#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4803#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4804#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4805#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4806#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4807#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4808#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000L
4809#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4810#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4811#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4812#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4813#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4814#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4815#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4816#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000L
4817#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4818#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4819#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4820#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4821#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4822#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4823#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4824#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000L
4825#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4826#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4827#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4828#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4829#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4830#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4831#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4832#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000L
4833#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4834#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4835#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4836#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4837#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4838#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4839#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4840#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000L
4841#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4842#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4843#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4844#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4845#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4846#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4847#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4848#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000L
4849#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4850#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4851#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4852#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4853#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4854#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4855#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4856#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4857#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4858#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4859#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4860#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4861#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4862#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4863#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4864#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4865#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4866#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4867#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4868#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4869#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4870#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4871#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4872#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4873#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4874#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4875#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4876#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4877#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4878#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4879#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4880#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4881#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4882#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4883#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4884#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4885#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4886#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4887#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4888#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4889#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4890#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4891#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4892#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4893#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4894#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4895#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4896#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4897#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4898#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4899#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4900#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4901#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4902#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4903#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4904#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000L
4905#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4906#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4907#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4908#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4909#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4910#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4911#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4912#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000L
4913#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4914#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0x000000ffL
4915#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x00000000
4916#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4917#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x00000008
4918#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4919#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x00000010
4920#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000L
4921#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x00000018
4922#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0x000000ffL
4923#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x00000000
4924#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4925#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x00000008
4926#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4927#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x00000010
4928#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000L
4929#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x00000018
4930#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
4931#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
4932#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
4933#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
4934#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
4935#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
4936#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
4937#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
4938#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
4939#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
4940#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
4941#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
4942#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
4943#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
4944#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
4945#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
4946#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4947#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4948#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4949#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4950#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4951#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4952#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000L
4953#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4954#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4955#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4956#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4957#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4958#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4959#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4960#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000L
4961#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4962#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0x000000ffL
4963#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x00000000
4964#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0x0000ff00L
4965#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x00000008
4966#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0x00ff0000L
4967#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x00000010
4968#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000L
4969#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x00000018
4970#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0x000000ffL
4971#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x00000000
4972#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0x0000ff00L
4973#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x00000008
4974#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0x00ff0000L
4975#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x00000010
4976#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000L
4977#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x00000018
4978#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4979#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4980#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4981#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4982#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4983#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4984#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000L
4985#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4986#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4987#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4988#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4989#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4990#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4991#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4992#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000L
4993#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4994#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL
4995#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000
4996#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L
4997#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008
4998#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L
4999#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010
5000#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L
5001#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018
5002#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL
5003#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000
5004#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L
5005#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008
5006#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L
5007#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010
5008#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L
5009#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018
5010#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0x000000ffL
5011#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x00000000
5012#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
5013#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x00000008
5014#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
5015#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x00000010
5016#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000L
5017#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x00000018
5018#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0x000000ffL
5019#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x00000000
5020#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
5021#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x00000008
5022#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
5023#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x00000010
5024#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000L
5025#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x00000018
5026#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL
5027#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000
5028#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L
5029#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008
5030#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L
5031#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010
5032#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L
5033#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018
5034#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL
5035#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000
5036#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L
5037#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008
5038#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L
5039#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010
5040#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L
5041#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018
5042#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0x000000ffL
5043#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x00000000
5044#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
5045#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x00000008
5046#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
5047#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x00000010
5048#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000L
5049#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x00000018
5050#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0x000000ffL
5051#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x00000000
5052#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
5053#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x00000008
5054#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
5055#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x00000010
5056#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000L
5057#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x00000018
5058#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
5059#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
5060#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
5061#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
5062#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
5063#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
5064#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
5065#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
5066#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
5067#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
5068#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
5069#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
5070#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
5071#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
5072#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
5073#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
5074#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
5075#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
5076#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
5077#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
5078#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
5079#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
5080#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000L
5081#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
5082#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
5083#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
5084#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
5085#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
5086#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
5087#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
5088#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000L
5089#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
5090#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
5091#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
5092#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
5093#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
5094#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
5095#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
5096#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000L
5097#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
5098#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
5099#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
5100#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
5101#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
5102#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
5103#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
5104#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000L
5105#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
5106#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0x000000ffL
5107#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x00000000
5108#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
5109#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x00000008
5110#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
5111#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x00000010
5112#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000L
5113#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x00000018
5114#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0x000000ffL
5115#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x00000000
5116#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
5117#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x00000008
5118#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
5119#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x00000010
5120#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000L
5121#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x00000018
5122#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0x000000ffL
5123#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x00000000
5124#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0x0000ff00L
5125#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x00000008
5126#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0x00ff0000L
5127#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x00000010
5128#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000L
5129#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x00000018
5130#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0x000000ffL
5131#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x00000000
5132#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0x0000ff00L
5133#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x00000008
5134#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0x00ff0000L
5135#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x00000010
5136#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000L
5137#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x00000018
5138#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0x000000ffL
5139#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x00000000
5140#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0x0000ff00L
5141#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x00000008
5142#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0x00ff0000L
5143#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x00000010
5144#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000L
5145#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x00000018
5146#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0x000000ffL
5147#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x00000000
5148#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0x0000ff00L
5149#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x00000008
5150#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0x00ff0000L
5151#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x00000010
5152#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000L
5153#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x00000018
5154#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0x000000ffL
5155#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x00000000
5156#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0x0000ff00L
5157#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x00000008
5158#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0x00ff0000L
5159#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x00000010
5160#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000L
5161#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x00000018
5162#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0x000000ffL
5163#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x00000000
5164#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0x0000ff00L
5165#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x00000008
5166#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0x00ff0000L
5167#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x00000010
5168#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000L
5169#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x00000018
5170#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0x000000ffL
5171#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x00000000
5172#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0x0000ff00L
5173#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x00000008
5174#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0x00ff0000L
5175#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x00000010
5176#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000L
5177#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x00000018
5178#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0x000000ffL
5179#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x00000000
5180#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0x0000ff00L
5181#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x00000008
5182#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0x00ff0000L
5183#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x00000010
5184#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000L
5185#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x00000018
5186#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0x000000ffL
5187#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x00000000
5188#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0x0000ff00L
5189#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x00000008
5190#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0x00ff0000L
5191#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x00000010
5192#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000L
5193#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x00000018
5194#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0x000000ffL
5195#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x00000000
5196#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0x0000ff00L
5197#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x00000008
5198#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0x00ff0000L
5199#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x00000010
5200#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000L
5201#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x00000018
5202#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0x000000ffL
5203#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x00000000
5204#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0x0000ff00L
5205#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x00000008
5206#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0x00ff0000L
5207#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x00000010
5208#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000L
5209#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x00000018
5210#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0x000000ffL
5211#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x00000000
5212#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0x0000ff00L
5213#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x00000008
5214#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0x00ff0000L
5215#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x00000010
5216#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000L
5217#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x00000018
5218#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0x000000ffL
5219#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x00000000
5220#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0x0000ff00L
5221#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x00000008
5222#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0x00ff0000L
5223#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x00000010
5224#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000L
5225#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x00000018
5226#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0x000000ffL
5227#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x00000000
5228#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0x0000ff00L
5229#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x00000008
5230#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0x00ff0000L
5231#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x00000010
5232#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000L
5233#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x00000018
5234#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0x000000ffL
5235#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x00000000
5236#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0x0000ff00L
5237#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x00000008
5238#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0x00ff0000L
5239#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x00000010
5240#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000L
5241#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x00000018
5242#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0x000000ffL
5243#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x00000000
5244#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0x0000ff00L
5245#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x00000008
5246#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0x00ff0000L
5247#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x00000010
5248#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000L
5249#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x00000018
5250#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0x000000ffL
5251#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x00000000
5252#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0x0000ff00L
5253#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x00000008
5254#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0x00ff0000L
5255#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x00000010
5256#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000L
5257#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x00000018
5258#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0x000000ffL
5259#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x00000000
5260#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0x0000ff00L
5261#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x00000008
5262#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0x00ff0000L
5263#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x00000010
5264#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000L
5265#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x00000018
5266#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0x000000ffL
5267#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x00000000
5268#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0x0000ff00L
5269#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x00000008
5270#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0x00ff0000L
5271#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x00000010
5272#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000L
5273#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x00000018
5274#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0x000000ffL
5275#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x00000000
5276#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0x0000ff00L
5277#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x00000008
5278#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0x00ff0000L
5279#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x00000010
5280#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000L
5281#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x00000018
5282#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0x000000ffL
5283#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x00000000
5284#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0x0000ff00L
5285#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x00000008
5286#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0x00ff0000L
5287#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x00000010
5288#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000L
5289#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x00000018
5290#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0x000000ffL
5291#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x00000000
5292#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0x0000ff00L
5293#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x00000008
5294#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0x00ff0000L
5295#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x00000010
5296#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000L
5297#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x00000018
5298#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0x000000ffL
5299#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x00000000
5300#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0x0000ff00L
5301#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x00000008
5302#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0x00ff0000L
5303#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x00000010
5304#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000L
5305#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x00000018
5306#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0x000000ffL
5307#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x00000000
5308#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0x0000ff00L
5309#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x00000008
5310#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0x00ff0000L
5311#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x00000010
5312#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000L
5313#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x00000018
5314#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0x000000ffL
5315#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x00000000
5316#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0x0000ff00L
5317#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x00000008
5318#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0x00ff0000L
5319#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x00000010
5320#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000L
5321#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x00000018
5322#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0x000000ffL
5323#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x00000000
5324#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0x0000ff00L
5325#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x00000008
5326#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0x00ff0000L
5327#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x00000010
5328#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000L
5329#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x00000018
5330#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0x000000ffL
5331#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x00000000
5332#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0x0000ff00L
5333#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x00000008
5334#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0x00ff0000L
5335#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x00000010
5336#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000L
5337#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x00000018
5338#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0x000000ffL
5339#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x00000000
5340#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0x0000ff00L
5341#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x00000008
5342#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0x00ff0000L
5343#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x00000010
5344#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000L
5345#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x00000018
5346#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0x000000ffL
5347#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x00000000
5348#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0x0000ff00L
5349#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x00000008
5350#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0x00ff0000L
5351#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x00000010
5352#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000L
5353#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x00000018
5354#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0x000000ffL
5355#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x00000000
5356#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0x0000ff00L
5357#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x00000008
5358#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0x00ff0000L
5359#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x00000010
5360#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000L
5361#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x00000018
5362#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0x000000ffL
5363#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x00000000
5364#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0x0000ff00L
5365#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x00000008
5366#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0x00ff0000L
5367#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x00000010
5368#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000L
5369#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x00000018
5370#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0x000000ffL
5371#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x00000000
5372#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0x0000ff00L
5373#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x00000008
5374#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0x00ff0000L
5375#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x00000010
5376#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000L
5377#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x00000018
5378#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0x000000ffL
5379#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x00000000
5380#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0x0000ff00L
5381#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x00000008
5382#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0x00ff0000L
5383#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x00000010
5384#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000L
5385#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x00000018
5386#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0x000000ffL
5387#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x00000000
5388#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0x0000ff00L
5389#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x00000008
5390#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0x00ff0000L
5391#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x00000010
5392#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000L
5393#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x00000018
5394#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0x000000ffL
5395#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x00000000
5396#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0x0000ff00L
5397#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x00000008
5398#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0x00ff0000L
5399#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x00000010
5400#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000L
5401#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x00000018
5402#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0x000000ffL
5403#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x00000000
5404#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0x0000ff00L
5405#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x00000008
5406#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0x00ff0000L
5407#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x00000010
5408#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000L
5409#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x00000018
5410#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0x000000ffL
5411#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x00000000
5412#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0x0000ff00L
5413#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x00000008
5414#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0x00ff0000L
5415#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x00000010
5416#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000L
5417#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x00000018
5418#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0x000000ffL
5419#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x00000000
5420#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0x0000ff00L
5421#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x00000008
5422#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0x00ff0000L
5423#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x00000010
5424#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000L
5425#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x00000018
5426#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0x000000ffL
5427#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x00000000
5428#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0x0000ff00L
5429#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x00000008
5430#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0x00ff0000L
5431#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x00000010
5432#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000L
5433#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x00000018
5434#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0x000000ffL
5435#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x00000000
5436#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0x0000ff00L
5437#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x00000008
5438#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0x00ff0000L
5439#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x00000010
5440#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000L
5441#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x00000018
5442#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0x000000ffL
5443#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x00000000
5444#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0x0000ff00L
5445#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x00000008
5446#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0x00ff0000L
5447#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x00000010
5448#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000L
5449#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x00000018
5450#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0x000000ffL
5451#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x00000000
5452#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0x0000ff00L
5453#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x00000008
5454#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0x00ff0000L
5455#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x00000010
5456#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000L
5457#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x00000018
5458#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0x000000ffL
5459#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x00000000
5460#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0x0000ff00L
5461#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x00000008
5462#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0x00ff0000L
5463#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x00000010
5464#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000L
5465#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x00000018
5466#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0x000000ffL
5467#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x00000000
5468#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0x0000ff00L
5469#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x00000008
5470#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0x00ff0000L
5471#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x00000010
5472#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000L
5473#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x00000018
5474#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0x000000ffL
5475#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x00000000
5476#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0x0000ff00L
5477#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x00000008
5478#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0x00ff0000L
5479#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x00000010
5480#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000L
5481#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x00000018
5482#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0x000000ffL
5483#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x00000000
5484#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0x0000ff00L
5485#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x00000008
5486#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0x00ff0000L
5487#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x00000010
5488#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000L
5489#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x00000018
5490#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0x000000ffL
5491#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x00000000
5492#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0x0000ff00L
5493#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x00000008
5494#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0x00ff0000L
5495#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x00000010
5496#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000L
5497#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x00000018
5498#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0x000000ffL
5499#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x00000000
5500#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0x0000ff00L
5501#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x00000008
5502#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0x00ff0000L
5503#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x00000010
5504#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000L
5505#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x00000018
5506#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0x000000ffL
5507#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x00000000
5508#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0x0000ff00L
5509#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x00000008
5510#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0x00ff0000L
5511#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x00000010
5512#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000L
5513#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x00000018
5514#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0x000000ffL
5515#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x00000000
5516#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0x0000ff00L
5517#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x00000008
5518#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0x00ff0000L
5519#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x00000010
5520#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000L
5521#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x00000018
5522#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0x000000ffL
5523#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x00000000
5524#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0x0000ff00L
5525#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x00000008
5526#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0x00ff0000L
5527#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x00000010
5528#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000L
5529#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x00000018
5530#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0x000000ffL
5531#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x00000000
5532#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0x0000ff00L
5533#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x00000008
5534#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0x00ff0000L
5535#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x00000010
5536#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000L
5537#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x00000018
5538#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0x000000ffL
5539#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x00000000
5540#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0x0000ff00L
5541#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x00000008
5542#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0x00ff0000L
5543#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x00000010
5544#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000L
5545#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x00000018
5546#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0x000000ffL
5547#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x00000000
5548#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0x0000ff00L
5549#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x00000008
5550#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0x00ff0000L
5551#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x00000010
5552#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000L
5553#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x00000018
5554#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0x000000ffL
5555#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x00000000
5556#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0x0000ff00L
5557#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x00000008
5558#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0x00ff0000L
5559#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x00000010
5560#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000L
5561#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x00000018
5562#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0x000000ffL
5563#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x00000000
5564#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0x0000ff00L
5565#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x00000008
5566#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0x00ff0000L
5567#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x00000010
5568#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000L
5569#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x00000018
5570#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0x000000ffL
5571#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x00000000
5572#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0x0000ff00L
5573#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x00000008
5574#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0x00ff0000L
5575#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x00000010
5576#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000L
5577#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x00000018
5578#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0x000000ffL
5579#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x00000000
5580#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0x0000ff00L
5581#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x00000008
5582#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0x00ff0000L
5583#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x00000010
5584#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000L
5585#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x00000018
5586#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0x000000ffL
5587#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x00000000
5588#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0x0000ff00L
5589#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x00000008
5590#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0x00ff0000L
5591#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x00000010
5592#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000L
5593#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x00000018
5594#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0x000000ffL
5595#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x00000000
5596#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0x0000ff00L
5597#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x00000008
5598#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0x00ff0000L
5599#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x00000010
5600#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000L
5601#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x00000018
5602#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0x000000ffL
5603#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x00000000
5604#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0x0000ff00L
5605#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x00000008
5606#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0x00ff0000L
5607#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x00000010
5608#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000L
5609#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x00000018
5610#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0x000000ffL
5611#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x00000000
5612#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0x0000ff00L
5613#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x00000008
5614#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0x00ff0000L
5615#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x00000010
5616#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000L
5617#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x00000018
5618#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0x000000ffL
5619#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x00000000
5620#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0x0000ff00L
5621#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x00000008
5622#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0x00ff0000L
5623#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x00000010
5624#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000L
5625#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x00000018
5626#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0x000000ffL
5627#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x00000000
5628#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0x0000ff00L
5629#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x00000008
5630#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0x00ff0000L
5631#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x00000010
5632#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000L
5633#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x00000018
5634#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0x000000ffL
5635#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x00000000
5636#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0x0000ff00L
5637#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x00000008
5638#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0x00ff0000L
5639#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x00000010
5640#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000L
5641#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x00000018
5642#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0x000000ffL
5643#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x00000000
5644#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0x0000ff00L
5645#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x00000008
5646#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0x00ff0000L
5647#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x00000010
5648#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000L
5649#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x00000018
5650#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0x000000ffL
5651#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x00000000
5652#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0x0000ff00L
5653#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x00000008
5654#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0x00ff0000L
5655#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x00000010
5656#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000L
5657#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x00000018
5658#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0x000000ffL
5659#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x00000000
5660#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0x0000ff00L
5661#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x00000008
5662#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0x00ff0000L
5663#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x00000010
5664#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000L
5665#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x00000018
5666#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0x000000ffL
5667#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x00000000
5668#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0x0000ff00L
5669#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x00000008
5670#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0x00ff0000L
5671#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x00000010
5672#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000L
5673#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x00000018
5674#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0x000000ffL
5675#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x00000000
5676#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0x0000ff00L
5677#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x00000008
5678#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0x00ff0000L
5679#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x00000010
5680#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000L
5681#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x00000018
5682#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0x000000ffL
5683#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x00000000
5684#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0x0000ff00L
5685#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x00000008
5686#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0x00ff0000L
5687#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x00000010
5688#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000L
5689#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x00000018
5690#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0x000000ffL
5691#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x00000000
5692#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0x0000ff00L
5693#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x00000008
5694#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0x00ff0000L
5695#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x00000010
5696#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000L
5697#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x00000018
5698#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0x000000ffL
5699#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x00000000
5700#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0x0000ff00L
5701#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x00000008
5702#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0x00ff0000L
5703#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x00000010
5704#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000L
5705#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x00000018
5706#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0x000000ffL
5707#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x00000000
5708#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0x0000ff00L
5709#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x00000008
5710#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0x00ff0000L
5711#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x00000010
5712#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000L
5713#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x00000018
5714#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0x000000ffL
5715#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x00000000
5716#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0x0000ff00L
5717#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x00000008
5718#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0x00ff0000L
5719#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x00000010
5720#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000L
5721#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x00000018
5722#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0x000000ffL
5723#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x00000000
5724#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0x0000ff00L
5725#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x00000008
5726#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0x00ff0000L
5727#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x00000010
5728#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000L
5729#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x00000018
5730#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0x000000ffL
5731#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x00000000
5732#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0x0000ff00L
5733#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x00000008
5734#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0x00ff0000L
5735#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x00000010
5736#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000L
5737#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x00000018
5738#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0x000000ffL
5739#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x00000000
5740#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0x0000ff00L
5741#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x00000008
5742#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0x00ff0000L
5743#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x00000010
5744#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000L
5745#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x00000018
5746#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0x000000ffL
5747#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x00000000
5748#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0x0000ff00L
5749#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x00000008
5750#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0x00ff0000L
5751#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x00000010
5752#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000L
5753#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x00000018
5754#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0x000000ffL
5755#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x00000000
5756#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0x0000ff00L
5757#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x00000008
5758#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0x00ff0000L
5759#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x00000010
5760#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000L
5761#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x00000018
5762#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0x000000ffL
5763#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x00000000
5764#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0x0000ff00L
5765#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x00000008
5766#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0x00ff0000L
5767#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x00000010
5768#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000L
5769#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x00000018
5770#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0x000000ffL
5771#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x00000000
5772#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0x0000ff00L
5773#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x00000008
5774#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0x00ff0000L
5775#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x00000010
5776#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000L
5777#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x00000018
5778#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0x000000ffL
5779#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x00000000
5780#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0x0000ff00L
5781#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x00000008
5782#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0x00ff0000L
5783#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x00000010
5784#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000L
5785#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x00000018
5786#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0x000000ffL
5787#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x00000000
5788#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0x0000ff00L
5789#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x00000008
5790#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0x00ff0000L
5791#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x00000010
5792#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000L
5793#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x00000018
5794#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0x000000ffL
5795#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x00000000
5796#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0x0000ff00L
5797#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x00000008
5798#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0x00ff0000L
5799#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x00000010
5800#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000L
5801#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x00000018
5802#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0x000000ffL
5803#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x00000000
5804#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0x0000ff00L
5805#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x00000008
5806#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0x00ff0000L
5807#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x00000010
5808#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000L
5809#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x00000018
5810#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0x000000ffL
5811#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x00000000
5812#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0x0000ff00L
5813#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x00000008
5814#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0x00ff0000L
5815#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x00000010
5816#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000L
5817#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x00000018
5818#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0x000000ffL
5819#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x00000000
5820#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0x0000ff00L
5821#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x00000008
5822#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0x00ff0000L
5823#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x00000010
5824#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000L
5825#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x00000018
5826#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0x000000ffL
5827#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x00000000
5828#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0x0000ff00L
5829#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x00000008
5830#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0x00ff0000L
5831#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x00000010
5832#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000L
5833#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x00000018
5834#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0x000000ffL
5835#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x00000000
5836#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0x0000ff00L
5837#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x00000008
5838#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0x00ff0000L
5839#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x00000010
5840#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000L
5841#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x00000018
5842#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0x000000ffL
5843#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x00000000
5844#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0x0000ff00L
5845#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x00000008
5846#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0x00ff0000L
5847#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x00000010
5848#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000L
5849#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x00000018
5850#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0x000000ffL
5851#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x00000000
5852#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0x0000ff00L
5853#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x00000008
5854#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0x00ff0000L
5855#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x00000010
5856#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000L
5857#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x00000018
5858#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0x000000ffL
5859#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x00000000
5860#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0x0000ff00L
5861#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x00000008
5862#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0x00ff0000L
5863#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x00000010
5864#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000L
5865#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x00000018
5866#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0x000000ffL
5867#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x00000000
5868#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0x0000ff00L
5869#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x00000008
5870#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0x00ff0000L
5871#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x00000010
5872#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000L
5873#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x00000018
5874#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0x000000ffL
5875#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x00000000
5876#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0x0000ff00L
5877#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x00000008
5878#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0x00ff0000L
5879#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x00000010
5880#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000L
5881#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x00000018
5882#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0x000000ffL
5883#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x00000000
5884#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0x0000ff00L
5885#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x00000008
5886#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0x00ff0000L
5887#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x00000010
5888#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000L
5889#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x00000018
5890#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0x000000ffL
5891#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x00000000
5892#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0x0000ff00L
5893#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x00000008
5894#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0x00ff0000L
5895#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x00000010
5896#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000L
5897#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x00000018
5898#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0x000000ffL
5899#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x00000000
5900#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0x0000ff00L
5901#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x00000008
5902#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0x00ff0000L
5903#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x00000010
5904#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000L
5905#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x00000018
5906#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0x000000ffL
5907#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x00000000
5908#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0x0000ff00L
5909#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x00000008
5910#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0x00ff0000L
5911#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x00000010
5912#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000L
5913#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x00000018
5914#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0x000000ffL
5915#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x00000000
5916#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0x0000ff00L
5917#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x00000008
5918#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0x00ff0000L
5919#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x00000010
5920#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000L
5921#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x00000018
5922#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0x000000ffL
5923#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x00000000
5924#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0x0000ff00L
5925#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x00000008
5926#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0x00ff0000L
5927#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x00000010
5928#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000L
5929#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x00000018
5930#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0x000000ffL
5931#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x00000000
5932#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0x0000ff00L
5933#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x00000008
5934#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0x00ff0000L
5935#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x00000010
5936#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000L
5937#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x00000018
5938#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0x000000ffL
5939#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x00000000
5940#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0x0000ff00L
5941#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x00000008
5942#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0x00ff0000L
5943#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x00000010
5944#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000L
5945#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x00000018
5946#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0x000000ffL
5947#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x00000000
5948#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0x0000ff00L
5949#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x00000008
5950#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0x00ff0000L
5951#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x00000010
5952#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000L
5953#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x00000018
5954#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0x000000ffL
5955#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x00000000
5956#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0x0000ff00L
5957#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x00000008
5958#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0x00ff0000L
5959#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x00000010
5960#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000L
5961#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x00000018
5962#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0x000000ffL
5963#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x00000000
5964#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0x0000ff00L
5965#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x00000008
5966#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0x00ff0000L
5967#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x00000010
5968#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000L
5969#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x00000018
5970#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0x000000ffL
5971#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x00000000
5972#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0x0000ff00L
5973#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x00000008
5974#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0x00ff0000L
5975#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x00000010
5976#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000L
5977#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x00000018
5978#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0x000000ffL
5979#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x00000000
5980#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0x0000ff00L
5981#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x00000008
5982#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0x00ff0000L
5983#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x00000010
5984#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000L
5985#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x00000018
5986#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0x000000ffL
5987#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x00000000
5988#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0x0000ff00L
5989#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x00000008
5990#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0x00ff0000L
5991#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x00000010
5992#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000L
5993#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x00000018
5994#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0x000000ffL
5995#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x00000000
5996#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0x0000ff00L
5997#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x00000008
5998#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0x00ff0000L
5999#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x00000010
6000#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000L
6001#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x00000018
6002#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0x000000ffL
6003#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x00000000
6004#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0x0000ff00L
6005#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x00000008
6006#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0x00ff0000L
6007#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x00000010
6008#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000L
6009#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x00000018
6010#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0x000000ffL
6011#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x00000000
6012#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0x0000ff00L
6013#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x00000008
6014#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0x00ff0000L
6015#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x00000010
6016#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000L
6017#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x00000018
6018#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0x000000ffL
6019#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x00000000
6020#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0x0000ff00L
6021#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x00000008
6022#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0x00ff0000L
6023#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x00000010
6024#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000L
6025#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x00000018
6026#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0x000000ffL
6027#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x00000000
6028#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0x0000ff00L
6029#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x00000008
6030#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0x00ff0000L
6031#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x00000010
6032#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000L
6033#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x00000018
6034#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0x000000ffL
6035#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x00000000
6036#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0x0000ff00L
6037#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x00000008
6038#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0x00ff0000L
6039#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x00000010
6040#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000L
6041#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x00000018
6042#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0x000000ffL
6043#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x00000000
6044#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0x0000ff00L
6045#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x00000008
6046#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0x00ff0000L
6047#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x00000010
6048#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000L
6049#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x00000018
6050#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0x000000ffL
6051#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x00000000
6052#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0x0000ff00L
6053#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x00000008
6054#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0x00ff0000L
6055#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x00000010
6056#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000L
6057#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x00000018
6058#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0x000000ffL
6059#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x00000000
6060#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0x0000ff00L
6061#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x00000008
6062#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0x00ff0000L
6063#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x00000010
6064#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000L
6065#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x00000018
6066#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0x000000ffL
6067#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x00000000
6068#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0x0000ff00L
6069#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x00000008
6070#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0x00ff0000L
6071#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x00000010
6072#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000L
6073#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x00000018
6074#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0x000000ffL
6075#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x00000000
6076#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0x0000ff00L
6077#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x00000008
6078#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0x00ff0000L
6079#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x00000010
6080#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000L
6081#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x00000018
6082#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0x000000ffL
6083#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x00000000
6084#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0x0000ff00L
6085#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x00000008
6086#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0x00ff0000L
6087#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x00000010
6088#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000L
6089#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x00000018
6090#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0x000000ffL
6091#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x00000000
6092#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0x0000ff00L
6093#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x00000008
6094#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0x00ff0000L
6095#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x00000010
6096#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000L
6097#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x00000018
6098#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0x000000ffL
6099#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x00000000
6100#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0x0000ff00L
6101#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x00000008
6102#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0x00ff0000L
6103#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x00000010
6104#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000L
6105#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x00000018
6106#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0x000000ffL
6107#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x00000000
6108#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0x0000ff00L
6109#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x00000008
6110#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0x00ff0000L
6111#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x00000010
6112#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000L
6113#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x00000018
6114#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0x000000ffL
6115#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x00000000
6116#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0x0000ff00L
6117#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x00000008
6118#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0x00ff0000L
6119#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x00000010
6120#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000L
6121#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x00000018
6122#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0x000000ffL
6123#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x00000000
6124#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0x0000ff00L
6125#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x00000008
6126#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0x00ff0000L
6127#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x00000010
6128#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000L
6129#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x00000018
6130#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0x000000ffL
6131#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x00000000
6132#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0x0000ff00L
6133#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x00000008
6134#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0x00ff0000L
6135#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x00000010
6136#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000L
6137#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x00000018
6138#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0x000000ffL
6139#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x00000000
6140#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0x0000ff00L
6141#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x00000008
6142#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0x00ff0000L
6143#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x00000010
6144#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000L
6145#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x00000018
6146#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0x000000ffL
6147#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x00000000
6148#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0x0000ff00L
6149#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x00000008
6150#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0x00ff0000L
6151#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x00000010
6152#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000L
6153#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x00000018
6154#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0x000000ffL
6155#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x00000000
6156#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0x0000ff00L
6157#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x00000008
6158#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0x00ff0000L
6159#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x00000010
6160#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000L
6161#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x00000018
6162#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0x000000ffL
6163#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x00000000
6164#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0x0000ff00L
6165#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x00000008
6166#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0x00ff0000L
6167#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x00000010
6168#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000L
6169#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x00000018
6170#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0x000000ffL
6171#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x00000000
6172#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0x0000ff00L
6173#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x00000008
6174#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0x00ff0000L
6175#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x00000010
6176#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000L
6177#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x00000018
6178#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0x000000ffL
6179#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x00000000
6180#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0x0000ff00L
6181#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x00000008
6182#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0x00ff0000L
6183#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x00000010
6184#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000L
6185#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x00000018
6186#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0x000000ffL
6187#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x00000000
6188#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0x0000ff00L
6189#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x00000008
6190#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0x00ff0000L
6191#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x00000010
6192#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000L
6193#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x00000018
6194#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0x000000ffL
6195#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x00000000
6196#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0x0000ff00L
6197#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x00000008
6198#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0x00ff0000L
6199#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x00000010
6200#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000L
6201#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x00000018
6202#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0x000000ffL
6203#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x00000000
6204#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0x0000ff00L
6205#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x00000008
6206#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0x00ff0000L
6207#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x00000010
6208#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000L
6209#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x00000018
6210#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0x000000ffL
6211#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x00000000
6212#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0x0000ff00L
6213#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x00000008
6214#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0x00ff0000L
6215#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x00000010
6216#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000L
6217#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x00000018
6218#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0x000000ffL
6219#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x00000000
6220#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0x0000ff00L
6221#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x00000008
6222#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0x00ff0000L
6223#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x00000010
6224#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000L
6225#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x00000018
6226#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0x000000ffL
6227#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x00000000
6228#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0x0000ff00L
6229#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x00000008
6230#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0x00ff0000L
6231#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x00000010
6232#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000L
6233#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x00000018
6234#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0x000000ffL
6235#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x00000000
6236#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0x0000ff00L
6237#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x00000008
6238#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0x00ff0000L
6239#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x00000010
6240#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000L
6241#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x00000018
6242#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0x000000ffL
6243#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x00000000
6244#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0x0000ff00L
6245#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x00000008
6246#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0x00ff0000L
6247#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x00000010
6248#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000L
6249#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x00000018
6250#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0x000000ffL
6251#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x00000000
6252#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0x0000ff00L
6253#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x00000008
6254#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0x00ff0000L
6255#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x00000010
6256#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000L
6257#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x00000018
6258#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0x000000ffL
6259#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x00000000
6260#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0x0000ff00L
6261#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x00000008
6262#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0x00ff0000L
6263#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x00000010
6264#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000L
6265#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x00000018
6266#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0x000000ffL
6267#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x00000000
6268#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0x0000ff00L
6269#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x00000008
6270#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0x00ff0000L
6271#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x00000010
6272#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000L
6273#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x00000018
6274#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0x000000ffL
6275#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x00000000
6276#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0x0000ff00L
6277#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x00000008
6278#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0x00ff0000L
6279#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x00000010
6280#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000L
6281#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x00000018
6282#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0x000000ffL
6283#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x00000000
6284#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0x0000ff00L
6285#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x00000008
6286#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0x00ff0000L
6287#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x00000010
6288#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000L
6289#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x00000018
6290#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0x000000ffL
6291#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x00000000
6292#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0x0000ff00L
6293#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x00000008
6294#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0x00ff0000L
6295#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x00000010
6296#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000L
6297#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x00000018
6298#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0x000000ffL
6299#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x00000000
6300#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0x0000ff00L
6301#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x00000008
6302#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0x00ff0000L
6303#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x00000010
6304#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000L
6305#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x00000018
6306#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0x000000ffL
6307#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x00000000
6308#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0x0000ff00L
6309#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x00000008
6310#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0x00ff0000L
6311#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x00000010
6312#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000L
6313#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x00000018
6314#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0x000000ffL
6315#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x00000000
6316#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0x0000ff00L
6317#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x00000008
6318#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0x00ff0000L
6319#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x00000010
6320#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000L
6321#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x00000018
6322#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0x000000ffL
6323#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x00000000
6324#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0x0000ff00L
6325#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x00000008
6326#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0x00ff0000L
6327#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x00000010
6328#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000L
6329#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x00000018
6330#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0x000000ffL
6331#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x00000000
6332#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0x0000ff00L
6333#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x00000008
6334#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0x00ff0000L
6335#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x00000010
6336#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000L
6337#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x00000018
6338#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0x000000ffL
6339#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x00000000
6340#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0x0000ff00L
6341#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x00000008
6342#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0x00ff0000L
6343#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x00000010
6344#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000L
6345#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x00000018
6346#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0x000000ffL
6347#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x00000000
6348#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0x0000ff00L
6349#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x00000008
6350#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0x00ff0000L
6351#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x00000010
6352#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000L
6353#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x00000018
6354#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0x000000ffL
6355#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x00000000
6356#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0x0000ff00L
6357#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x00000008
6358#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0x00ff0000L
6359#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x00000010
6360#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000L
6361#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x00000018
6362#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0x000000ffL
6363#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x00000000
6364#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0x0000ff00L
6365#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x00000008
6366#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0x00ff0000L
6367#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x00000010
6368#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000L
6369#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x00000018
6370#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0x000000ffL
6371#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x00000000
6372#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0x0000ff00L
6373#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x00000008
6374#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0x00ff0000L
6375#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x00000010
6376#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000L
6377#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x00000018
6378#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0x000000ffL
6379#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x00000000
6380#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0x0000ff00L
6381#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x00000008
6382#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0x00ff0000L
6383#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x00000010
6384#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000L
6385#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x00000018
6386#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0x000000ffL
6387#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x00000000
6388#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0x0000ff00L
6389#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x00000008
6390#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0x00ff0000L
6391#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x00000010
6392#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000L
6393#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x00000018
6394#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0x000000ffL
6395#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x00000000
6396#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0x0000ff00L
6397#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x00000008
6398#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0x00ff0000L
6399#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x00000010
6400#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000L
6401#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x00000018
6402#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0x000000ffL
6403#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x00000000
6404#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0x0000ff00L
6405#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x00000008
6406#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0x00ff0000L
6407#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x00000010
6408#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000L
6409#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x00000018
6410#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0x000000ffL
6411#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x00000000
6412#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0x0000ff00L
6413#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x00000008
6414#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0x00ff0000L
6415#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x00000010
6416#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000L
6417#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x00000018
6418#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
6419#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
6420#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
6421#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
6422#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
6423#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
6424#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
6425#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
6426#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
6427#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
6428#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
6429#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
6430#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
6431#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
6432#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
6433#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
6434#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0x000000ffL
6435#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x00000000
6436#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
6437#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x00000008
6438#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
6439#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x00000010
6440#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000L
6441#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x00000018
6442#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0x000000ffL
6443#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x00000000
6444#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
6445#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x00000008
6446#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
6447#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x00000010
6448#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000L
6449#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x00000018
6450#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0x000000ffL
6451#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x00000000
6452#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0x0000ff00L
6453#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x00000008
6454#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0x00ff0000L
6455#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x00000010
6456#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000L
6457#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x00000018
6458#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0x000000ffL
6459#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x00000000
6460#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0x0000ff00L
6461#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x00000008
6462#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0x00ff0000L
6463#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x00000010
6464#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000L
6465#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x00000018
6466#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0x000000ffL
6467#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x00000000
6468#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
6469#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x00000008
6470#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
6471#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x00000010
6472#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000L
6473#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x00000018
6474#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0x000000ffL
6475#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x00000000
6476#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
6477#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x00000008
6478#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
6479#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x00000010
6480#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000L
6481#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x00000018
6482#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL
6483#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000
6484#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L
6485#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008
6486#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L
6487#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010
6488#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L
6489#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018
6490#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL
6491#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000
6492#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L
6493#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008
6494#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L
6495#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010
6496#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L
6497#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018
6498#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0x000000ffL
6499#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x00000000
6500#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
6501#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x00000008
6502#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
6503#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x00000010
6504#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000L
6505#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x00000018
6506#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0x000000ffL
6507#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x00000000
6508#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
6509#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x00000008
6510#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
6511#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x00000010
6512#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000L
6513#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x00000018
6514#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL
6515#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000
6516#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L
6517#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008
6518#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L
6519#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010
6520#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L
6521#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018
6522#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL
6523#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000
6524#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L
6525#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008
6526#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L
6527#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010
6528#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L
6529#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018
6530#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0x000000ffL
6531#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x00000000
6532#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
6533#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x00000008
6534#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
6535#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x00000010
6536#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000L
6537#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x00000018
6538#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0x000000ffL
6539#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x00000000
6540#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
6541#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x00000008
6542#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
6543#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x00000010
6544#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000L
6545#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x00000018
6546#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
6547#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
6548#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
6549#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
6550#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
6551#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
6552#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
6553#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
6554#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
6555#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
6556#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
6557#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
6558#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
6559#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
6560#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
6561#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
6562#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
6563#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
6564#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
6565#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
6566#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
6567#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
6568#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000L
6569#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
6570#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
6571#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
6572#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
6573#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
6574#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
6575#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
6576#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000L
6577#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
6578#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
6579#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
6580#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
6581#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
6582#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
6583#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
6584#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000L
6585#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
6586#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
6587#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
6588#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
6589#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
6590#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
6591#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
6592#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000L
6593#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
6594#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0x000000ffL
6595#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x00000000
6596#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
6597#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x00000008
6598#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
6599#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x00000010
6600#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000L
6601#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x00000018
6602#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0x000000ffL
6603#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x00000000
6604#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
6605#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x00000008
6606#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
6607#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x00000010
6608#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000L
6609#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x00000018
6610#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0x000000ffL
6611#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x00000000
6612#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0x0000ff00L
6613#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x00000008
6614#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0x00ff0000L
6615#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x00000010
6616#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000L
6617#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x00000018
6618#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0x000000ffL
6619#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x00000000
6620#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0x0000ff00L
6621#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x00000008
6622#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0x00ff0000L
6623#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x00000010
6624#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000L
6625#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x00000018
6626#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0x000000ffL
6627#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x00000000
6628#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
6629#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x00000008
6630#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
6631#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x00000010
6632#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000L
6633#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x00000018
6634#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0x000000ffL
6635#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x00000000
6636#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
6637#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x00000008
6638#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
6639#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x00000010
6640#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000L
6641#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x00000018
6642#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0x000000ffL
6643#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x00000000
6644#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0x0000ff00L
6645#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x00000008
6646#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0x00ff0000L
6647#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x00000010
6648#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000L
6649#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x00000018
6650#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0x000000ffL
6651#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x00000000
6652#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0x0000ff00L
6653#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x00000008
6654#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0x00ff0000L
6655#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x00000010
6656#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000L
6657#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x00000018
6658#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0x000000ffL
6659#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x00000000
6660#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
6661#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x00000008
6662#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
6663#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x00000010
6664#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000L
6665#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x00000018
6666#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0x000000ffL
6667#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x00000000
6668#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
6669#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x00000008
6670#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
6671#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x00000010
6672#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000L
6673#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x00000018
6674#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0x000000ffL
6675#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x00000000
6676#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
6677#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x00000008
6678#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
6679#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x00000010
6680#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000L
6681#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x00000018
6682#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0x000000ffL
6683#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x00000000
6684#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
6685#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x00000008
6686#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
6687#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x00000010
6688#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000L
6689#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x00000018
6690#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0x000000ffL
6691#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x00000000
6692#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
6693#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x00000008
6694#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
6695#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x00000010
6696#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000L
6697#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x00000018
6698#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0x000000ffL
6699#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x00000000
6700#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
6701#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x00000008
6702#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
6703#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x00000010
6704#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000L
6705#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x00000018
6706#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
6707#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
6708#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
6709#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
6710#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
6711#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
6712#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
6713#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
6714#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
6715#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
6716#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
6717#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
6718#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
6719#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
6720#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
6721#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
6722#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
6723#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
6724#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
6725#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
6726#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
6727#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
6728#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000L
6729#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
6730#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
6731#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
6732#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
6733#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
6734#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
6735#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
6736#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000L
6737#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
6738#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
6739#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
6740#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
6741#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
6742#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
6743#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
6744#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000L
6745#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
6746#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
6747#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
6748#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
6749#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
6750#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
6751#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
6752#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000L
6753#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
6754#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0x000000ffL
6755#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x00000000
6756#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
6757#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x00000008
6758#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
6759#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x00000010
6760#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000L
6761#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x00000018
6762#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0x000000ffL
6763#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x00000000
6764#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
6765#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x00000008
6766#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
6767#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x00000010
6768#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000L
6769#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x00000018
6770#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0x000000ffL
6771#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x00000000
6772#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0x0000ff00L
6773#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x00000008
6774#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0x00ff0000L
6775#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x00000010
6776#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000L
6777#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x00000018
6778#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0x000000ffL
6779#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x00000000
6780#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0x0000ff00L
6781#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x00000008
6782#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0x00ff0000L
6783#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x00000010
6784#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000L
6785#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x00000018
6786#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L
6787#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a
6788#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000L
6789#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x0000001c
6790#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000L
6791#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x0000001d
6792#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0x00000fc0L
6793#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x00000006
6794#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0x00fc0000L
6795#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x00000012
6796#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x0000003fL
6797#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x00000000
6798#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x0003f000L
6799#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0x0000000c
6800#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x01000000L
6801#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x00000018
6802#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x02000000L
6803#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x00000019
6804#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L
6805#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a
6806#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000L
6807#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x0000001c
6808#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000L
6809#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x0000001d
6810#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0x00000fc0L
6811#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x00000006
6812#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0x00fc0000L
6813#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x00000012
6814#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x0000003fL
6815#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x00000000
6816#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x0003f000L
6817#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0x0000000c
6818#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x01000000L
6819#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x00000018
6820#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x02000000L
6821#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x00000019
6822#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000L
6823#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x00000018
6824#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000L
6825#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x0000001f
6826#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000L
6827#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x0000001e
6828#define MC_IO_PAD_CNTL__ATBSEL_MASK 0x00f00000L
6829#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x00000014
6830#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x00100000L
6831#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x00000014
6832#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0x00c00000L
6833#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x00000016
6834#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x03000000L
6835#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x00000018
6836#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x00200000L
6837#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x00000015
6838#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x00000010L
6839#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x00000004
6840#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x00000004L
6841#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x00000002
6842#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x00000008L
6843#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x00000003
6844#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000L
6845#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x0000001d
6846#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x00002000L
6847#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0x0000000d
6848#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x00001000L
6849#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0x0000000c
6850#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x00000800L
6851#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0x0000000b
6852#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x00000400L
6853#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0x0000000a
6854#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000L
6855#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x0000001e
6856#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x00000200L
6857#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x00000009
6858#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x00000080L
6859#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x00000007
6860#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x00000100L
6861#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x00000008
6862#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x08000000L
6863#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x0000001b
6864#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000L
6865#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x0000001f
6866#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000L
6867#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x0000001c
6868#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x00004000L
6869#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0x0000000e
6870#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0x000f8000L
6871#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0x0000000f
6872#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x00100000L
6873#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x00000014
6874#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0x00c00000L
6875#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x00000016
6876#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x03000000L
6877#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x00000018
6878#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x00200000L
6879#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x00000015
6880#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x00000010L
6881#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x00000004
6882#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x00000004L
6883#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x00000002
6884#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x00000008L
6885#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x00000003
6886#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x00000001L
6887#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x00000000
6888#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x00000002L
6889#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x00000001
6890#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000L
6891#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x0000001d
6892#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x00002000L
6893#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0x0000000d
6894#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x00001000L
6895#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0x0000000c
6896#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x00000800L
6897#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0x0000000b
6898#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x00000400L
6899#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0x0000000a
6900#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000L
6901#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x0000001e
6902#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x00000200L
6903#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x00000009
6904#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x00000080L
6905#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x00000007
6906#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x00000100L
6907#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x00000008
6908#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x00000020L
6909#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x00000005
6910#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x00000040L
6911#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x00000006
6912#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x08000000L
6913#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x0000001b
6914#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000L
6915#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x0000001f
6916#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000L
6917#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x0000001c
6918#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x00004000L
6919#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0x0000000e
6920#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0x000f8000L
6921#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0x0000000f
6922#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0x0000ff00L
6923#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x00000008
6924#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0x000000ffL
6925#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x00000000
6926#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x00040000L
6927#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x00000012
6928#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x00080000L
6929#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x00000013
6930#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x00020000L
6931#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x00000011
6932#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x00010000L
6933#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x00000010
6934#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000L
6935#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x0000001c
6936#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0x0e000000L
6937#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x00000019
6938#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0x0000000fL
6939#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x00000000
6940#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0x000000f0L
6941#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x00000004
6942#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0x0000ff00L
6943#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x00000008
6944#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x00040000L
6945#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x00000012
6946#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x00010000L
6947#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x00000010
6948#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x00020000L
6949#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x00000011
6950#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000L
6951#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x0000001c
6952#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0x0e000000L
6953#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x00000019
6954#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0x0000000fL
6955#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x00000000
6956#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0x000000f0L
6957#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x00000004
6958#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0x0000ff00L
6959#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x00000008
6960#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x00040000L
6961#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x00000012
6962#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x00010000L
6963#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x00000010
6964#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x00020000L
6965#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x00000011
6966#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000L
6967#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x0000001c
6968#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0x0e000000L
6969#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x00000019
6970#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0x0000000fL
6971#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x00000000
6972#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0x000000f0L
6973#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x00000004
6974#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0x0000ff00L
6975#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x00000008
6976#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x00040000L
6977#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x00000012
6978#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x00010000L
6979#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x00000010
6980#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x00020000L
6981#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x00000011
6982#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000L
6983#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x0000001c
6984#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0x0e000000L
6985#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x00000019
6986#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0x0000000fL
6987#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x00000000
6988#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0x000000f0L
6989#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x00000004
6990#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0x0000ff00L
6991#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x00000008
6992#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x00040000L
6993#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x00000012
6994#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x00010000L
6995#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x00000010
6996#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x00020000L
6997#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x00000011
6998#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x00700000L
6999#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x00000014
7000#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x07000000L
7001#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x00000018
7002#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000L
7003#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x0000001c
7004#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000L
7005#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x0000001e
7006#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x00000004L
7007#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x00000002
7008#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000L
7009#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x0000001d
7010#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x00000003L
7011#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x00000000
7012#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x00000030L
7013#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x00000004
7014#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x00000080L
7015#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x00000007
7016#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x00000040L
7017#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x00000006
7018#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0x000c0000L
7019#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x00000012
7020#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0x00000f00L
7021#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x00000008
7022#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0x0000f000L
7023#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0x0000000c
7024#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x00000008L
7025#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x00000003
7026#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x00010000L
7027#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x00000010
7028#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x00700000L
7029#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x00000014
7030#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x07000000L
7031#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x00000018
7032#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000L
7033#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x0000001c
7034#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000L
7035#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x0000001e
7036#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x00000004L
7037#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x00000002
7038#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000L
7039#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x0000001d
7040#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x00000003L
7041#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x00000000
7042#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x00000030L
7043#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x00000004
7044#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x00000080L
7045#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x00000007
7046#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x00000040L
7047#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x00000006
7048#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0x000c0000L
7049#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x00000012
7050#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0x00000f00L
7051#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x00000008
7052#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0x0000f000L
7053#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0x0000000c
7054#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x00000008L
7055#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x00000003
7056#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x00010000L
7057#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x00000010
7058#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x00700000L
7059#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x00000014
7060#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x07000000L
7061#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x00000018
7062#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000L
7063#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x0000001c
7064#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000L
7065#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x0000001e
7066#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x00000004L
7067#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x00000002
7068#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000L
7069#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x0000001d
7070#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x00000003L
7071#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x00000000
7072#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x00000030L
7073#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x00000004
7074#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x00000080L
7075#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x00000007
7076#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x00000040L
7077#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x00000006
7078#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0x000c0000L
7079#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x00000012
7080#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0x00000f00L
7081#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x00000008
7082#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0x0000f000L
7083#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0x0000000c
7084#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x00000008L
7085#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x00000003
7086#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x00010000L
7087#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x00000010
7088#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x00700000L
7089#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x00000014
7090#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x07000000L
7091#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x00000018
7092#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000L
7093#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x0000001c
7094#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000L
7095#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x0000001e
7096#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x00000004L
7097#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x00000002
7098#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000L
7099#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x0000001d
7100#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x00000003L
7101#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x00000000
7102#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x00000030L
7103#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x00000004
7104#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x00000080L
7105#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x00000007
7106#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x00000040L
7107#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x00000006
7108#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0x000c0000L
7109#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x00000012
7110#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0x00000f00L
7111#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x00000008
7112#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0x0000f000L
7113#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0x0000000c
7114#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x00000008L
7115#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x00000003
7116#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x00010000L
7117#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x00000010
7118#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x00000003L
7119#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x00000000
7120#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000L
7121#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x0000001e
7122#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000L
7123#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x0000001f
7124#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0x0000000cL
7125#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x00000002
7126#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x00000040L
7127#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x00000006
7128#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x00000010L
7129#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x00000004
7130#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x00700000L
7131#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x00000014
7132#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0x000f0000L
7133#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x00000010
7134#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0x0000e000L
7135#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0x0000000d
7136#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0x00000f00L
7137#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x00000008
7138#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x00000020L
7139#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x00000005
7140#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x01000000L
7141#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x00000018
7142#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x00001000L
7143#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0x0000000c
7144#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000L
7145#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x0000001b
7146#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x04000000L
7147#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x0000001a
7148#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x00000080L
7149#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x00000007
7150#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x02000000L
7151#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x00000019
7152#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x00800000L
7153#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x00000017
7154#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x00000003L
7155#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x00000000
7156#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000L
7157#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x0000001e
7158#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000L
7159#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x0000001f
7160#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0x0000000cL
7161#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x00000002
7162#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x00000040L
7163#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x00000006
7164#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x00000010L
7165#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x00000004
7166#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x00700000L
7167#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x00000014
7168#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0x000f0000L
7169#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x00000010
7170#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0x0000e000L
7171#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0x0000000d
7172#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0x00000f00L
7173#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x00000008
7174#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x00000020L
7175#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x00000005
7176#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x01000000L
7177#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x00000018
7178#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x00001000L
7179#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0x0000000c
7180#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000L
7181#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x0000001b
7182#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x04000000L
7183#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x0000001a
7184#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x00000080L
7185#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x00000007
7186#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x02000000L
7187#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x00000019
7188#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x00800000L
7189#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x00000017
7190#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x00000003L
7191#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x00000000
7192#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0x0000000cL
7193#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x00000002
7194#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L
7195#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019
7196#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x00000040L
7197#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x00000006
7198#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x00000010L
7199#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x00000004
7200#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0x00f00000L
7201#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x00000014
7202#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0x0000f000L
7203#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0x0000000c
7204#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0x000f0000L
7205#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x00000010
7206#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x08000000L
7207#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x0000001b
7208#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0x00000f00L
7209#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x00000008
7210#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x00000020L
7211#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x00000005
7212#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x01000000L
7213#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x00000018
7214#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000L
7215#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x0000001c
7216#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x04000000L
7217#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x0000001a
7218#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x00000080L
7219#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x00000007
7220#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x00000003L
7221#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x00000000
7222#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0x0000000cL
7223#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x00000002
7224#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L
7225#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019
7226#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x00000040L
7227#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x00000006
7228#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x00000010L
7229#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x00000004
7230#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0x00f00000L
7231#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x00000014
7232#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0x0000f000L
7233#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0x0000000c
7234#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0x000f0000L
7235#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x00000010
7236#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x08000000L
7237#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x0000001b
7238#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0x00000f00L
7239#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x00000008
7240#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x00000020L
7241#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x00000005
7242#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x01000000L
7243#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x00000018
7244#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000L
7245#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x0000001c
7246#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x04000000L
7247#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x0000001a
7248#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x00000080L
7249#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x00000007
7250#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x00000003L
7251#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x00000000
7252#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0x0000000cL
7253#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x00000002
7254#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L
7255#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019
7256#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x00000040L
7257#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x00000006
7258#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x00000010L
7259#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x00000004
7260#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0x00f00000L
7261#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x00000014
7262#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0x0000f000L
7263#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0x0000000c
7264#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0x000f0000L
7265#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x00000010
7266#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x08000000L
7267#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x0000001b
7268#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0x00000f00L
7269#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x00000008
7270#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x00000020L
7271#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x00000005
7272#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x01000000L
7273#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x00000018
7274#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000L
7275#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x0000001c
7276#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x04000000L
7277#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x0000001a
7278#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x00000080L
7279#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x00000007
7280#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x00000003L
7281#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x00000000
7282#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0x0000000cL
7283#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x00000002
7284#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L
7285#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019
7286#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x00000040L
7287#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x00000006
7288#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x00000010L
7289#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x00000004
7290#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0x00f00000L
7291#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x00000014
7292#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0x0000f000L
7293#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0x0000000c
7294#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0x000f0000L
7295#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x00000010
7296#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x08000000L
7297#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x0000001b
7298#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0x00000f00L
7299#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x00000008
7300#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x00000020L
7301#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x00000005
7302#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x01000000L
7303#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x00000018
7304#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000L
7305#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x0000001c
7306#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x04000000L
7307#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x0000001a
7308#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x00000080L
7309#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x00000007
7310#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x00000040L
7311#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x01000000L
7312#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x00000018
7313#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000006
7314#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x0000001fL
7315#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x00000000
7316#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00000080L
7317#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000007
7318#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x00000100L
7319#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x00000008
7320#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x00010000L
7321#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x00000010
7322#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x00000200L
7323#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x00000009
7324#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x00020000L
7325#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x00000011
7326#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L
7327#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006
7328#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL
7329#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000
7330#define MC_NPL_STATUS__D0_NDELAY_MASK 0x0000000cL
7331#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x00000002
7332#define MC_NPL_STATUS__D0_NEARLY_MASK 0x00000020L
7333#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x00000005
7334#define MC_NPL_STATUS__D0_PDELAY_MASK 0x00000003L
7335#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x00000000
7336#define MC_NPL_STATUS__D0_PEARLY_MASK 0x00000010L
7337#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x00000004
7338#define MC_NPL_STATUS__D1_NDELAY_MASK 0x00000300L
7339#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x00000008
7340#define MC_NPL_STATUS__D1_NEARLY_MASK 0x00000800L
7341#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0x0000000b
7342#define MC_NPL_STATUS__D1_PDELAY_MASK 0x000000c0L
7343#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x00000006
7344#define MC_NPL_STATUS__D1_PEARLY_MASK 0x00000400L
7345#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0x0000000a
7346#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x00040000L
7347#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x00000012
7348#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x00080000L
7349#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x00000013
7350#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x0000007fL
7351#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x00000000
7352#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x00001000L
7353#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0x0000000c
7354#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x00000100L
7355#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x00000008
7356#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x00002000L
7357#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0x0000000d
7358#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x00000200L
7359#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x00000009
7360#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x00004000L
7361#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0x0000000e
7362#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x00000400L
7363#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0x0000000a
7364#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x00008000L
7365#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0x0000000f
7366#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x00000800L
7367#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0x0000000b
7368#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x00010000L
7369#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x00000010
7370#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x00020000L
7371#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x00000011
7372#define MC_PHY_TIMING_2__WR_DLY_MASK 0x00f00000L
7373#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x00000014
7374#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0x0000000fL
7375#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x00000000
7376#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0x000000f0L
7377#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x00000004
7378#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0x00000f00L
7379#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x00000008
7380#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0x0000f000L
7381#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0x0000000c
7382#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x00070000L
7383#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x00000010
7384#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0x00f00000L
7385#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x00000014
7386#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x07000000L
7387#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x00000018
7388#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000L
7389#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x0000001c
7390#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0x0000000fL
7391#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x00000000
7392#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0x000000f0L
7393#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x00000004
7394#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0x00000f00L
7395#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x00000008
7396#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0x0000f000L
7397#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0x0000000c
7398#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x00070000L
7399#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x00000010
7400#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0x00f00000L
7401#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x00000014
7402#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x07000000L
7403#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x00000018
7404#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000L
7405#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x0000001c
7406#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000L
7407#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x00000018
7408#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x00000800L
7409#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0x0000000b
7410#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0x000f0000L
7411#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x00000010
7412#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x00002000L
7413#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0x0000000d
7414#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x00001000L
7415#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0x0000000c
7416#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x00000002L
7417#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x00000001
7418#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x00400000L
7419#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x00000016
7420#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x00000400L
7421#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0x0000000a
7422#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x00008000L
7423#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0x0000000f
7424#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x00800000L
7425#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x00000017
7426#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x00000100L
7427#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x00000008
7428#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x00000200L
7429#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x00000009
7430#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x00004000L
7431#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0x0000000e
7432#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x00000001L
7433#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x00000000
7434#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x00000004L
7435#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x00000002
7436#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L
7437#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014
7438#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0x000000f0L
7439#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x00000004
7440#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x00200000L
7441#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x00000015
7442#define MC_PMG_AUTO_CMD__ADR_MASK 0x0001ffffL
7443#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000L
7444#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x0000001d
7445#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000L
7446#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x0000001c
7447#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x00000000
7448#define MC_PMG_CFG__DPM_WAKE_MASK 0x00000400L
7449#define MC_PMG_CFG__DPM_WAKE__SHIFT 0x0000000a
7450#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x00400000L
7451#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x00000016
7452#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0x000f0000L
7453#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x00000010
7454#define MC_PMG_CFG__PREA_SRX_MASK 0x00002000L
7455#define MC_PMG_CFG__PREA_SRX__SHIFT 0x0000000d
7456#define MC_PMG_CFG__RFS_SRX_MASK 0x00001000L
7457#define MC_PMG_CFG__RFS_SRX__SHIFT 0x0000000c
7458#define MC_PMG_CFG__RST_EMRS_MASK 0x00000004L
7459#define MC_PMG_CFG__RST_EMRS__SHIFT 0x00000002
7460#define MC_PMG_CFG__RST_MRS1_MASK 0x00000100L
7461#define MC_PMG_CFG__RST_MRS1__SHIFT 0x00000008
7462#define MC_PMG_CFG__RST_MRS2_MASK 0x00000200L
7463#define MC_PMG_CFG__RST_MRS2__SHIFT 0x00000009
7464#define MC_PMG_CFG__RST_MRS_MASK 0x00000002L
7465#define MC_PMG_CFG__RST_MRS__SHIFT 0x00000001
7466#define MC_PMG_CFG__RXPDNB_MASK 0x02000000L
7467#define MC_PMG_CFG__RXPDNB__SHIFT 0x00000019
7468#define MC_PMG_CFG__SYC_CLK_MASK 0x00000001L
7469#define MC_PMG_CFG__SYC_CLK__SHIFT 0x00000000
7470#define MC_PMG_CFG__TRI_MIO_MASK 0x00000008L
7471#define MC_PMG_CFG__TRI_MIO__SHIFT 0x00000003
7472#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L
7473#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014
7474#define MC_PMG_CFG__XSR_TMR_MASK 0x000000f0L
7475#define MC_PMG_CFG__XSR_TMR__SHIFT 0x00000004
7476#define MC_PMG_CFG__YCLK_ON_MASK 0x00200000L
7477#define MC_PMG_CFG__YCLK_ON__SHIFT 0x00000015
7478#define MC_PMG_CFG__ZQCL_SEND_MASK 0x0c000000L
7479#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x0000001a
7480#define MC_PMG_CMD_EMRS__ADR_MASK 0x0000ffffL
7481#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000L
7482#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x0000001d
7483#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000L
7484#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x0000001c
7485#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x00000000
7486#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x00080000L
7487#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x00000013
7488#define MC_PMG_CMD_EMRS__CSB_MASK 0x00600000L
7489#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x00000015
7490#define MC_PMG_CMD_EMRS__END_MASK 0x00100000L
7491#define MC_PMG_CMD_EMRS__END__SHIFT 0x00000014
7492#define MC_PMG_CMD_EMRS__MOP_MASK 0x00070000L
7493#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x00000010
7494#define MC_PMG_CMD_MRS1__ADR_MASK 0x0000ffffL
7495#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000L
7496#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x0000001d
7497#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000L
7498#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x0000001c
7499#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x00000000
7500#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x00080000L
7501#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x00000013
7502#define MC_PMG_CMD_MRS1__CSB_MASK 0x00600000L
7503#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x00000015
7504#define MC_PMG_CMD_MRS1__END_MASK 0x00100000L
7505#define MC_PMG_CMD_MRS1__END__SHIFT 0x00000014
7506#define MC_PMG_CMD_MRS1__MOP_MASK 0x00070000L
7507#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x00000010
7508#define MC_PMG_CMD_MRS2__ADR_MASK 0x0000ffffL
7509#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000L
7510#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x0000001d
7511#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000L
7512#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x0000001c
7513#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x00000000
7514#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x00080000L
7515#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x00000013
7516#define MC_PMG_CMD_MRS2__CSB_MASK 0x00600000L
7517#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x00000015
7518#define MC_PMG_CMD_MRS2__END_MASK 0x00100000L
7519#define MC_PMG_CMD_MRS2__END__SHIFT 0x00000014
7520#define MC_PMG_CMD_MRS2__MOP_MASK 0x00070000L
7521#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x00000010
7522#define MC_PMG_CMD_MRS__ADR_MASK 0x0000ffffL
7523#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000L
7524#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x0000001d
7525#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000L
7526#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x0000001c
7527#define MC_PMG_CMD_MRS__ADR__SHIFT 0x00000000
7528#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x00080000L
7529#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x00000013
7530#define MC_PMG_CMD_MRS__CSB_MASK 0x00600000L
7531#define MC_PMG_CMD_MRS__CSB__SHIFT 0x00000015
7532#define MC_PMG_CMD_MRS__END_MASK 0x00100000L
7533#define MC_PMG_CMD_MRS__END__SHIFT 0x00000014
7534#define MC_PMG_CMD_MRS__MOP_MASK 0x00070000L
7535#define MC_PMG_CMD_MRS__MOP__SHIFT 0x00000010
7536#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x00000008L
7537#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003
7538#define MC_RD_CB__ENABLE_MASK 0x00000001L
7539#define MC_RD_CB__ENABLE__SHIFT 0x00000000
7540#define MC_RD_CB__LAZY_TIMER_MASK 0x00007800L
7541#define MC_RD_CB__LAZY_TIMER__SHIFT 0x0000000b
7542#define MC_RD_CB__MAX_BURST_MASK 0x00000780L
7543#define MC_RD_CB__MAX_BURST__SHIFT 0x00000007
7544#define MC_RD_CB__PRESCALE_MASK 0x00000006L
7545#define MC_RD_CB__PRESCALE__SHIFT 0x00000001
7546#define MC_RD_CB__STALL_MODE_MASK 0x00000030L
7547#define MC_RD_CB__STALL_MODE__SHIFT 0x00000004
7548#define MC_RD_CB__STALL_OVERRIDE_MASK 0x00000040L
7549#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x00000006
7550#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L
7551#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
7552#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x00000008L
7553#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003
7554#define MC_RD_DB__ENABLE_MASK 0x00000001L
7555#define MC_RD_DB__ENABLE__SHIFT 0x00000000
7556#define MC_RD_DB__LAZY_TIMER_MASK 0x00007800L
7557#define MC_RD_DB__LAZY_TIMER__SHIFT 0x0000000b
7558#define MC_RD_DB__MAX_BURST_MASK 0x00000780L
7559#define MC_RD_DB__MAX_BURST__SHIFT 0x00000007
7560#define MC_RD_DB__PRESCALE_MASK 0x00000006L
7561#define MC_RD_DB__PRESCALE__SHIFT 0x00000001
7562#define MC_RD_DB__STALL_MODE_MASK 0x00000030L
7563#define MC_RD_DB__STALL_MODE__SHIFT 0x00000004
7564#define MC_RD_DB__STALL_OVERRIDE_MASK 0x00000040L
7565#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x00000006
7566#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L
7567#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
7568#define MC_RD_GRP_EXT__DBSTEN0_MASK 0x0000000fL
7569#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x00000000
7570#define MC_RD_GRP_EXT__TC0_MASK 0x000000f0L
7571#define MC_RD_GRP_EXT__TC0__SHIFT 0x00000004
7572#define MC_RD_GRP_GFX__CP_MASK 0x0000000fL
7573#define MC_RD_GRP_GFX__CP__SHIFT 0x00000000
7574#define MC_RD_GRP_GFX__XDMAM_MASK 0x000f0000L
7575#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x00000010
7576#define MC_RD_GRP_LCL__CB0_MASK 0x0000f000L
7577#define MC_RD_GRP_LCL__CB0__SHIFT 0x0000000c
7578#define MC_RD_GRP_LCL__CBCMASK0_MASK 0x000f0000L
7579#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x00000010
7580#define MC_RD_GRP_LCL__CBFMASK0_MASK 0x00f00000L
7581#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x00000014
7582#define MC_RD_GRP_LCL__DB0_MASK 0x0f000000L
7583#define MC_RD_GRP_LCL__DB0__SHIFT 0x00000018
7584#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000L
7585#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x0000001c
7586#define MC_RD_GRP_OTH__HDP_MASK 0x00000f00L
7587#define MC_RD_GRP_OTH__HDP__SHIFT 0x00000008
7588#define MC_RD_GRP_OTH__SEM_MASK 0x0000f000L
7589#define MC_RD_GRP_OTH__SEM__SHIFT 0x0000000c
7590#define MC_RD_GRP_OTH__UMC_MASK 0x000f0000L
7591#define MC_RD_GRP_OTH__UMC__SHIFT 0x00000010
7592#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0x0000000fL
7593#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x00000000
7594#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0x0f000000L
7595#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x00000018
7596#define MC_RD_GRP_OTH__UVD_MASK 0x00f00000L
7597#define MC_RD_GRP_OTH__UVD__SHIFT 0x00000014
7598#define MC_RD_GRP_SYS__DMIF_MASK 0x0000f000L
7599#define MC_RD_GRP_SYS__DMIF__SHIFT 0x0000000c
7600#define MC_RD_GRP_SYS__MCIF_MASK 0x000f0000L
7601#define MC_RD_GRP_SYS__MCIF__SHIFT 0x00000010
7602#define MC_RD_GRP_SYS__RLC_MASK 0x0000000fL
7603#define MC_RD_GRP_SYS__RLC__SHIFT 0x00000000
7604#define MC_RD_GRP_SYS__SMU_MASK 0x00f00000L
7605#define MC_RD_GRP_SYS__SMU__SHIFT 0x00000014
7606#define MC_RD_GRP_SYS__VCE_MASK 0x0f000000L
7607#define MC_RD_GRP_SYS__VCE__SHIFT 0x00000018
7608#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000L
7609#define MC_RD_GRP_SYS__VCEU__SHIFT 0x0000001c
7610#define MC_RD_GRP_SYS__VMC_MASK 0x000000f0L
7611#define MC_RD_GRP_SYS__VMC__SHIFT 0x00000004
7612#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L
7613#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003
7614#define MC_RD_HUB__ENABLE_MASK 0x00000001L
7615#define MC_RD_HUB__ENABLE__SHIFT 0x00000000
7616#define MC_RD_HUB__LAZY_TIMER_MASK 0x00007800L
7617#define MC_RD_HUB__LAZY_TIMER__SHIFT 0x0000000b
7618#define MC_RD_HUB__MAX_BURST_MASK 0x00000780L
7619#define MC_RD_HUB__MAX_BURST__SHIFT 0x00000007
7620#define MC_RD_HUB__PRESCALE_MASK 0x00000006L
7621#define MC_RD_HUB__PRESCALE__SHIFT 0x00000001
7622#define MC_RD_HUB__STALL_MODE_MASK 0x00000030L
7623#define MC_RD_HUB__STALL_MODE__SHIFT 0x00000004
7624#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x00000040L
7625#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x00000006
7626#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L
7627#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
7628#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L
7629#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003
7630#define MC_RD_TC0__ENABLE_MASK 0x00000001L
7631#define MC_RD_TC0__ENABLE__SHIFT 0x00000000
7632#define MC_RD_TC0__LAZY_TIMER_MASK 0x00007800L
7633#define MC_RD_TC0__LAZY_TIMER__SHIFT 0x0000000b
7634#define MC_RD_TC0__MAX_BURST_MASK 0x00000780L
7635#define MC_RD_TC0__MAX_BURST__SHIFT 0x00000007
7636#define MC_RD_TC0__PRESCALE_MASK 0x00000006L
7637#define MC_RD_TC0__PRESCALE__SHIFT 0x00000001
7638#define MC_RD_TC0__STALL_MODE_MASK 0x00000030L
7639#define MC_RD_TC0__STALL_MODE__SHIFT 0x00000004
7640#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x00000040L
7641#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x00000006
7642#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L
7643#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
7644#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L
7645#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003
7646#define MC_RD_TC1__ENABLE_MASK 0x00000001L
7647#define MC_RD_TC1__ENABLE__SHIFT 0x00000000
7648#define MC_RD_TC1__LAZY_TIMER_MASK 0x00007800L
7649#define MC_RD_TC1__LAZY_TIMER__SHIFT 0x0000000b
7650#define MC_RD_TC1__MAX_BURST_MASK 0x00000780L
7651#define MC_RD_TC1__MAX_BURST__SHIFT 0x00000007
7652#define MC_RD_TC1__PRESCALE_MASK 0x00000006L
7653#define MC_RD_TC1__PRESCALE__SHIFT 0x00000001
7654#define MC_RD_TC1__STALL_MODE_MASK 0x00000030L
7655#define MC_RD_TC1__STALL_MODE__SHIFT 0x00000004
7656#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x00000040L
7657#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x00000006
7658#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L
7659#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
7660#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0x00ff0000L
7661#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x00000010
7662#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x0000ff00L
7663#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x00000008
7664#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x000000ffL
7665#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x00000000
7666#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0x000000ffL
7667#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x00000000
7668#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0x0000ff00L
7669#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x00000008
7670#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000L
7671#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x00000010
7672#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000ffffL
7673#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x00000000
7674#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x0000003eL
7675#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x00000001
7676#define MC_RPB_CID_QUEUE_EX__START_MASK 0x00000001L
7677#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x00000000
7678#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0x000000ffL
7679#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x00000000
7680#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x00000c00L
7681#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0x0000000a
7682#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00000300L
7683#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x00000008
7684#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0x000000ffL
7685#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x00000000
7686#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00001800L
7687#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0x0000000b
7688#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x00002000L
7689#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000100L
7690#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x00000008
7691#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x0000000d
7692#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00000600L
7693#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x00000009
7694#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x00010000L
7695#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x00000010
7696#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x00020000L
7697#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x00000011
7698#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x00008000L
7699#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0x0000000f
7700#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000L
7701#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x00000014
7702#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0x000fff00L
7703#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x00000008
7704#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0x000000ffL
7705#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x00000000
7706#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000ff00L
7707#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x00000008
7708#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000ffL
7709#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x00000000
7710#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0x0000ff00L
7711#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x00000008
7712#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0x000000ffL
7713#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x00000000
7714#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L
7715#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x00000003
7716#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L
7717#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x00000002
7718#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001e0L
7719#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x00000005
7720#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003e00L
7721#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x00000009
7722#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007c000L
7723#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0x0000000e
7724#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00f80000L
7725#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x00000013
7726#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000L
7727#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x00000018
7728#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L
7729#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000
7730#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L
7731#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x00000004
7732#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffffL
7733#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x00000000
7734#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL
7735#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000
7736#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L
7737#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008
7738#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L
7739#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010
7740#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L
7741#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018
7742#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000080L
7743#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x00000007
7744#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x00000001L
7745#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x00000000
7746#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x00000078L
7747#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x00000003
7748#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000006L
7749#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x00000001
7750#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL
7751#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000
7752#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L
7753#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008
7754#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L
7755#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010
7756#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L
7757#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018
7758#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x00000007L
7759#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x00000000
7760#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x00000038L
7761#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x00000003
7762#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x000001c0L
7763#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x00000006
7764#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0x00000e00L
7765#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x00000009
7766#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x00007000L
7767#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0x0000000c
7768#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x00038000L
7769#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0x0000000f
7770#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x001c0000L
7771#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x00000012
7772#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0x00e00000L
7773#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x00000015
7774#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x00000007L
7775#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x00000000
7776#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x00000038L
7777#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x00000003
7778#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x000001c0L
7779#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x00000006
7780#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0x00000e00L
7781#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x00000009
7782#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x00007000L
7783#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0x0000000c
7784#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x00038000L
7785#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0x0000000f
7786#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x001c0000L
7787#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x00000012
7788#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0x00e00000L
7789#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x00000015
7790#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x00000007L
7791#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x00000000
7792#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x00000038L
7793#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x00000003
7794#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x000001c0L
7795#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x00000006
7796#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0x00000e00L
7797#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x00000009
7798#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x00007000L
7799#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0x0000000c
7800#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x00038000L
7801#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0x0000000f
7802#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x001c0000L
7803#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x00000012
7804#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0x00e00000L
7805#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x00000015
7806#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x00000007L
7807#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x00000000
7808#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x00000038L
7809#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x00000003
7810#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x000001c0L
7811#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x00000006
7812#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0x00000e00L
7813#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x00000009
7814#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x00007000L
7815#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0x0000000c
7816#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x00038000L
7817#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0x0000000f
7818#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x001c0000L
7819#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x00000012
7820#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0x00e00000L
7821#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x00000015
7822#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x00000007L
7823#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x00000000
7824#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x00000038L
7825#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x00000003
7826#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x000001c0L
7827#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x00000006
7828#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0x00000e00L
7829#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x00000009
7830#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x00007000L
7831#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0x0000000c
7832#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x00038000L
7833#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0x0000000f
7834#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x001c0000L
7835#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x00000012
7836#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0x00e00000L
7837#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x00000015
7838#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x00000007L
7839#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x00000000
7840#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x00000038L
7841#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x00000003
7842#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x000001c0L
7843#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x00000006
7844#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0x00000e00L
7845#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x00000009
7846#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x00007000L
7847#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0x0000000c
7848#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x00038000L
7849#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0x0000000f
7850#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x001c0000L
7851#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x00000012
7852#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0x00e00000L
7853#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x00000015
7854#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x00000007L
7855#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x00000000
7856#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x00000038L
7857#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x00000003
7858#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x000001c0L
7859#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x00000006
7860#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0x00000e00L
7861#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x00000009
7862#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x00007000L
7863#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0x0000000c
7864#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x00038000L
7865#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0x0000000f
7866#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x001c0000L
7867#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x00000012
7868#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0x00e00000L
7869#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x00000015
7870#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x00000007L
7871#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x00000000
7872#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x00000038L
7873#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x00000003
7874#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x000001c0L
7875#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x00000006
7876#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0x00000e00L
7877#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x00000009
7878#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x00007000L
7879#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0x0000000c
7880#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x00038000L
7881#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0x0000000f
7882#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x001c0000L
7883#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x00000012
7884#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0x00e00000L
7885#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x00000015
7886#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x00000003L
7887#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x00000000
7888#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0x0000000cL
7889#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x00000002
7890#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x00000030L
7891#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x00000004
7892#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0x000000c0L
7893#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x00000006
7894#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x00000003L
7895#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x00000000
7896#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0x0000000cL
7897#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x00000002
7898#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x00000030L
7899#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x00000004
7900#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0x000000c0L
7901#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x00000006
7902#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0x00000e00L
7903#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x00000009
7904#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000L
7905#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x00000018
7906#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0x0000000cL
7907#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x00000002
7908#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x00000003L
7909#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x00000000
7910#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0x0000f000L
7911#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0x0000000c
7912#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x000001f0L
7913#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x00000004
7914#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x001f0000L
7915#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x00000010
7916#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0x00000e00L
7917#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x00000009
7918#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000L
7919#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x00000018
7920#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0x0000000cL
7921#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x00000002
7922#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x00000003L
7923#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x00000000
7924#define MC_SEQ_CAS_TIMING__TR2R_MASK 0x0000f000L
7925#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0x0000000c
7926#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x000001f0L
7927#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x00000004
7928#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x001f0000L
7929#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x00000010
7930#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0x000000ffL
7931#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x00000000
7932#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0x0000ff00L
7933#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x00000008
7934#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0x00ff0000L
7935#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x00000010
7936#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000L
7937#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x00000018
7938#define MC_SEQ_CMD__ADR_MASK 0x0000ffffL
7939#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000L
7940#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x0000001d
7941#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000L
7942#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x0000001c
7943#define MC_SEQ_CMD__ADR__SHIFT 0x00000000
7944#define MC_SEQ_CMD__CHAN0_MASK 0x01000000L
7945#define MC_SEQ_CMD__CHAN0__SHIFT 0x00000018
7946#define MC_SEQ_CMD__CHAN1_MASK 0x02000000L
7947#define MC_SEQ_CMD__CHAN1__SHIFT 0x00000019
7948#define MC_SEQ_CMD__CSB_MASK 0x00600000L
7949#define MC_SEQ_CMD__CSB__SHIFT 0x00000015
7950#define MC_SEQ_CMD__END_MASK 0x00100000L
7951#define MC_SEQ_CMD__END__SHIFT 0x00000014
7952#define MC_SEQ_CMD__MOP_MASK 0x000f0000L
7953#define MC_SEQ_CMD__MOP__SHIFT 0x00000010
7954#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x00000300L
7955#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x00000008
7956#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0x0000fc00L
7957#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0x0000000a
7958#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x003f0000L
7959#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x00000010
7960#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0x0f000000L
7961#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x00000018
7962#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000L
7963#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x0000001c
7964#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x00400000L
7965#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x00000016
7966#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x00800000L
7967#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x00000017
7968#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0x00f00000L
7969#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x00000014
7970#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0x0f000000L
7971#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x00000018
7972#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000L
7973#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x0000001c
7974#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x00040000L
7975#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x00000012
7976#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x00020000L
7977#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x00000011
7978#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x00000300L
7979#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x00000008
7980#define MC_SEQ_CNTL__DAT_INV_MASK 0x00000040L
7981#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x00000006
7982#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0x0000000cL
7983#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x00000002
7984#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x00000003L
7985#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x00000000
7986#define MC_SEQ_CNTL__MSK_DF1_MASK 0x00000080L
7987#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x00000007
7988#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x00008000L
7989#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0x0000000f
7990#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x00004000L
7991#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0x0000000e
7992#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x00010000L
7993#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x00000010
7994#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x00080000L
7995#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x00000013
7996#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x00000030L
7997#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x00000004
7998#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x04000000L
7999#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x0000001a
8000#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x02000000L
8001#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x00000019
8002#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x00000004L
8003#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x00000002
8004#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x00000002L
8005#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x00000001
8006#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x00000001L
8007#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x00000000
8008#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x00002000L
8009#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0x0000000d
8010#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x00000008L
8011#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x00000003
8012#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000L
8013#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x0000001f
8014#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x00000010L
8015#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x00000004
8016#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000L
8017#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x0000001c
8018#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x08000000L
8019#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x0000001b
8020#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000L
8021#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x0000001d
8022#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x00004000L
8023#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0x0000000e
8024#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x00001000L
8025#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0x0000000c
8026#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x00000080L
8027#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x00000007
8028#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x01000000L
8029#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x00000018
8030#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x00000800L
8031#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0x0000000b
8032#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0x00ff0000L
8033#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x00000010
8034#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x00000400L
8035#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0x0000000a
8036#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x00000040L
8037#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x00000006
8038#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x00000100L
8039#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x00000008
8040#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000L
8041#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x0000001e
8042#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x00008000L
8043#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0x0000000f
8044#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x00000020L
8045#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x00000005
8046#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x00000200L
8047#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x00000009
8048#define MC_SEQ_DRAM__ADR_2CK_MASK 0x00000001L
8049#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x00000000
8050#define MC_SEQ_DRAM__ADR_DF1_MASK 0x00000004L
8051#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x00000002
8052#define MC_SEQ_DRAM__ADR_MUX_MASK 0x00000002L
8053#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x00000001
8054#define MC_SEQ_DRAM__AP8_MASK 0x00000008L
8055#define MC_SEQ_DRAM__AP8__SHIFT 0x00000003
8056#define MC_SEQ_DRAM__BO4_MASK 0x00004000L
8057#define MC_SEQ_DRAM__BO4__SHIFT 0x0000000e
8058#define MC_SEQ_DRAM__CKE_ACT_MASK 0x00002000L
8059#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0x0000000d
8060#define MC_SEQ_DRAM__CKE_DYN_MASK 0x00001000L
8061#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0x0000000c
8062#define MC_SEQ_DRAM__DAT_DF1_MASK 0x00000010L
8063#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x00000004
8064#define MC_SEQ_DRAM__DAT_INV_MASK 0x01000000L
8065#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x00000018
8066#define MC_SEQ_DRAM__DLL_CLR_MASK 0x00008000L
8067#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0x0000000f
8068#define MC_SEQ_DRAM__DLL_CNT_MASK 0x00ff0000L
8069#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x00000010
8070#define MC_SEQ_DRAM__DQM_ACT_MASK 0x00000080L
8071#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x00000007
8072#define MC_SEQ_DRAM__DQM_DF1_MASK 0x00000040L
8073#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x00000006
8074#define MC_SEQ_DRAM__DQS_DF1_MASK 0x00000020L
8075#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x00000005
8076#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000L
8077#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x00000010
8078#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0x0000ffffL
8079#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x00000000
8080#define MC_SEQ_DRAM__INV_ACM_MASK 0x02000000L
8081#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x00000019
8082#define MC_SEQ_DRAM__ODT_ACT_MASK 0x08000000L
8083#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x0000001b
8084#define MC_SEQ_DRAM__ODT_ENB_MASK 0x04000000L
8085#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x0000001a
8086#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000L
8087#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x0000001c
8088#define MC_SEQ_DRAM__STB_CNT_MASK 0x00000f00L
8089#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x00000008
8090#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000L
8091#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x0000001e
8092#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000L
8093#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x0000001d
8094#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x00000100L
8095#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x00000008
8096#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x00000200L
8097#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x00000009
8098#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x00000030L
8099#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x00000004
8100#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0x000000c0L
8101#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x00000006
8102#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x00007000L
8103#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0x0000000c
8104#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x00030000L
8105#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x00000010
8106#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0x000c0000L
8107#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x00000012
8108#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x00000003L
8109#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x00000000
8110#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0x00000c00L
8111#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0x0000000a
8112#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0x0000000cL
8113#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x00000002
8114#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffffL
8115#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x00000000
8116#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x000001ffL
8117#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x00000000
8118#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffffL
8119#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x00000000
8120#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffffL
8121#define MC_SEQ_IO_REDC__EDC__SHIFT 0x00000000
8122#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000L
8123#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x00000018
8124#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0x00000fffL
8125#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x00000000
8126#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0x00fff000L
8127#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0x0000000c
8128#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000L
8129#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x00000018
8130#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0x00000fffL
8131#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x00000000
8132#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0x00fff000L
8133#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0x0000000c
8134#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffffL
8135#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x00000000
8136#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffffL
8137#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x00000000
8138#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffffL
8139#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x00000000
8140#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffffL
8141#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x00000000
8142#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffffL
8143#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x00000000
8144#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffffL
8145#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x00000000
8146#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffffL
8147#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x00000000
8148#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffffL
8149#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x00000000
8150#define MC_SEQ_MISC0__VALUE_MASK 0xffffffffL
8151#define MC_SEQ_MISC0__VALUE__SHIFT 0x00000000
8152#define MC_SEQ_MISC1__VALUE_MASK 0xffffffffL
8153#define MC_SEQ_MISC1__VALUE__SHIFT 0x00000000
8154#define MC_SEQ_MISC3__VALUE_MASK 0xffffffffL
8155#define MC_SEQ_MISC3__VALUE__SHIFT 0x00000000
8156#define MC_SEQ_MISC4__VALUE_MASK 0xffffffffL
8157#define MC_SEQ_MISC4__VALUE__SHIFT 0x00000000
8158#define MC_SEQ_MISC5__VALUE_MASK 0xffffffffL
8159#define MC_SEQ_MISC5__VALUE__SHIFT 0x00000000
8160#define MC_SEQ_MISC6__VALUE_MASK 0xffffffffL
8161#define MC_SEQ_MISC6__VALUE__SHIFT 0x00000000
8162#define MC_SEQ_MISC7__VALUE_MASK 0xffffffffL
8163#define MC_SEQ_MISC7__VALUE__SHIFT 0x00000000
8164#define MC_SEQ_MISC8__VALUE_MASK 0xffffffffL
8165#define MC_SEQ_MISC8__VALUE__SHIFT 0x00000000
8166#define MC_SEQ_MISC9__VALUE_MASK 0xffffffffL
8167#define MC_SEQ_MISC9__VALUE__SHIFT 0x00000000
8168#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x00001f00L
8169#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x00000008
8170#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x00001f00L
8171#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x00000008
8172#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x00000007L
8173#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x00000000
8174#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x00000070L
8175#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x00000004
8176#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0x00e00000L
8177#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x00000015
8178#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0x0f000000L
8179#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x00000018
8180#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0x0000e000L
8181#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0x0000000d
8182#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000L
8183#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x0000001c
8184#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x001f0000L
8185#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x00000010
8186#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x00000007L
8187#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x00000000
8188#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x00000070L
8189#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x00000004
8190#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x01e00000L
8191#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x00000015
8192#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0x0000e000L
8193#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0x0000000d
8194#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000L
8195#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x0000001c
8196#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x001f0000L
8197#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x00000010
8198#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000L
8199#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x00000014
8200#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0x000f8000L
8201#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x00003f00L
8202#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x00000008
8203#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0x0000000f
8204#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x0000003fL
8205#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x00000000
8206#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000L
8207#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x00000014
8208#define MC_SEQ_MISC_TIMING__TRP_MASK 0x000f8000L
8209#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x00003f00L
8210#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x00000008
8211#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0x0000000f
8212#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x0000003fL
8213#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x00000000
8214#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x00000001L
8215#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x00000000
8216#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x00000020L
8217#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x00000005
8218#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x00000002L
8219#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x00000001
8220#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x00000004L
8221#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x00000002
8222#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x00000008L
8223#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x00000003
8224#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x00000010L
8225#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x00000004
8226#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x00000040L
8227#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x00000006
8228#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x00000080L
8229#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x00000007
8230#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x00000001L
8231#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x00000000
8232#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x00000100L
8233#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x00000008
8234#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x00000200L
8235#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x00000009
8236#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x00000400L
8237#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0x0000000a
8238#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x00000800L
8239#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0x0000000b
8240#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x00001000L
8241#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0x0000000c
8242#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x00002000L
8243#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0x0000000d
8244#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x00004000L
8245#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0x0000000e
8246#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x00008000L
8247#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0x0000000f
8248#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000L
8249#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x0000001e
8250#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffffL
8251#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x00000000
8252#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffffL
8253#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x00000000
8254#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffffL
8255#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x00000000
8256#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffffL
8257#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x00000000
8258#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffffL
8259#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x00000000
8260#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffffL
8261#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x00000000
8262#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffffL
8263#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x00000000
8264#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffffL
8265#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x00000000
8266#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffffL
8267#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x00000000
8268#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0x0000000fL
8269#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x00000000
8270#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0x000000f0L
8271#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x00000004
8272#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0x00000f00L
8273#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x00000008
8274#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0x0000f000L
8275#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0x0000000c
8276#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0x000f0000L
8277#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x00000010
8278#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0x00f00000L
8279#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x00000014
8280#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0x0f000000L
8281#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x00000018
8282#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000L
8283#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x0000001c
8284#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0x0000ffffL
8285#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000L
8286#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x0000001d
8287#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000L
8288#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x0000001c
8289#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x00000000
8290#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x00080000L
8291#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x00000013
8292#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x00600000L
8293#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x00000015
8294#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x00100000L
8295#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x00000014
8296#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x00070000L
8297#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x00000010
8298#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0x0000ffffL
8299#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000L
8300#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x0000001d
8301#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000L
8302#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x0000001c
8303#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x00000000
8304#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x00080000L
8305#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x00000013
8306#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x00600000L
8307#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x00000015
8308#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x00100000L
8309#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x00000014
8310#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x00070000L
8311#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x00000010
8312#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0x0000ffffL
8313#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000L
8314#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x0000001d
8315#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000L
8316#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x0000001c
8317#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x00000000
8318#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x00080000L
8319#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x00000013
8320#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x00600000L
8321#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x00000015
8322#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x00100000L
8323#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x00000014
8324#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x00070000L
8325#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x00000010
8326#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0x0000ffffL
8327#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000L
8328#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x0000001d
8329#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000L
8330#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x0000001c
8331#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x00000000
8332#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x00080000L
8333#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x00000013
8334#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x00600000L
8335#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x00000015
8336#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x00100000L
8337#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x00000014
8338#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x00070000L
8339#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x00000010
8340#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x00040000L
8341#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x00000012
8342#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x00000300L
8343#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x00000008
8344#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0x000000c0L
8345#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x00000006
8346#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x00003c00L
8347#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0x0000000a
8348#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x00000001L
8349#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x00000000
8350#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x00020000L
8351#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x00000011
8352#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x00000002L
8353#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x00000001
8354#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x0000003cL
8355#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x00000002
8356#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x00010000L
8357#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x00000010
8358#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000L
8359#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x0000001f
8360#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x00010000L
8361#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x00000010
8362#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x00000020L
8363#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x00000005
8364#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x00000002L
8365#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x00000001
8366#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x00000010L
8367#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x00000004
8368#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x00000001L
8369#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x00000000
8370#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x00000040L
8371#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x00000006
8372#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x00000004L
8373#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x00000002
8374#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x00000080L
8375#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x00000007
8376#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x00000008L
8377#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x00000003
8378#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x00002000L
8379#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0x0000000d
8380#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x00000200L
8381#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x00000009
8382#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x00001000L
8383#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0x0000000c
8384#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x00000100L
8385#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x00000008
8386#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x00004000L
8387#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0x0000000e
8388#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x00000400L
8389#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0x0000000a
8390#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x00008000L
8391#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0x0000000f
8392#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x00000800L
8393#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0x0000000b
8394#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000L
8395#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x0000001f
8396#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x00010000L
8397#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x00000010
8398#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x00000020L
8399#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x00000005
8400#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x00000002L
8401#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x00000001
8402#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x00000010L
8403#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x00000004
8404#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x00000001L
8405#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x00000000
8406#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x00000040L
8407#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x00000006
8408#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x00000004L
8409#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x00000002
8410#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x00000080L
8411#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x00000007
8412#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x00000008L
8413#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x00000003
8414#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x00002000L
8415#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0x0000000d
8416#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x00000200L
8417#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x00000009
8418#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x00001000L
8419#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0x0000000c
8420#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x00000100L
8421#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x00000008
8422#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x00004000L
8423#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0x0000000e
8424#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x00000400L
8425#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0x0000000a
8426#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x00008000L
8427#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0x0000000f
8428#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x00000800L
8429#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0x0000000b
8430#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x001c0000L
8431#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x00000012
8432#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000L
8433#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x00000018
8434#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x0003f000L
8435#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0x00000f00L
8436#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x00800000L
8437#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x00000017
8438#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x00000008
8439#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0x0000000c
8440#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x00000007L
8441#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x00000000
8442#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x00000070L
8443#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x00000004
8444#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x001c0000L
8445#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x00000012
8446#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000L
8447#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x00000018
8448#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x0003f000L
8449#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0x00000f00L
8450#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x00800000L
8451#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x00000017
8452#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x00000008
8453#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0x0000000c
8454#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x00000007L
8455#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x00000000
8456#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x00000070L
8457#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x00000004
8458#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0x000f8000L
8459#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0x0000000f
8460#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x00007c00L
8461#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0x0000000a
8462#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x000003e0L
8463#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x00000005
8464#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x0000001fL
8465#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x00000000
8466#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000L
8467#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x00000018
8468#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0x00f00000L
8469#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x00000014
8470#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0x000f8000L
8471#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0x0000000f
8472#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x00007c00L
8473#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0x0000000a
8474#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x000003e0L
8475#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x00000005
8476#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x0000001fL
8477#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x00000000
8478#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000L
8479#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x00000018
8480#define MC_SEQ_RAS_TIMING__TRRD_MASK 0x00f00000L
8481#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x00000014
8482#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x01f00000L
8483#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x00000014
8484#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000L
8485#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x00000019
8486#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x00000007L
8487#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x00000000
8488#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0x000000f8L
8489#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x00000003
8490#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0x0000f000L
8491#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0x0000000c
8492#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x00000300L
8493#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x00000008
8494#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0x00000c00L
8495#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0x0000000a
8496#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x00010000L
8497#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x00000010
8498#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x00020000L
8499#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x00000011
8500#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x01f00000L
8501#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x00000014
8502#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000L
8503#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x00000019
8504#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x00000007L
8505#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x00000000
8506#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0x000000f8L
8507#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x00000003
8508#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0x0000f000L
8509#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0x0000000c
8510#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x00000300L
8511#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x00000008
8512#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0x00000c00L
8513#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0x0000000a
8514#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x00010000L
8515#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x00000010
8516#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x00020000L
8517#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x00000011
8518#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x01f00000L
8519#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x00000014
8520#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000L
8521#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x00000019
8522#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x00000007L
8523#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x00000000
8524#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0x000000f8L
8525#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x00000003
8526#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0x0000f000L
8527#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0x0000000c
8528#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x00000300L
8529#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x00000008
8530#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0x00000c00L
8531#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0x0000000a
8532#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x00010000L
8533#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x00000010
8534#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x00020000L
8535#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x00000011
8536#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x01f00000L
8537#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x00000014
8538#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000L
8539#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x00000019
8540#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x00000007L
8541#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x00000000
8542#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0x000000f8L
8543#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x00000003
8544#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0x0000f000L
8545#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0x0000000c
8546#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x00000300L
8547#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x00000008
8548#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0x00000c00L
8549#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0x0000000a
8550#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x00010000L
8551#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x00000010
8552#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x00020000L
8553#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x00000011
8554#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffffL
8555#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x00000000
8556#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffffL
8557#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x00000000
8558#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffffL
8559#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x00000000
8560#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL
8561#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000
8562#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L
8563#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004
8564#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L
8565#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008
8566#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L
8567#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c
8568#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L
8569#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010
8570#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L
8571#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014
8572#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L
8573#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018
8574#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L
8575#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c
8576#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL
8577#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000
8578#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L
8579#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004
8580#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L
8581#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008
8582#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L
8583#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c
8584#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L
8585#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010
8586#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L
8587#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014
8588#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L
8589#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018
8590#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L
8591#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c
8592#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL
8593#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000
8594#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L
8595#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004
8596#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L
8597#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008
8598#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L
8599#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c
8600#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L
8601#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010
8602#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L
8603#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014
8604#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L
8605#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018
8606#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L
8607#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c
8608#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL
8609#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000
8610#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L
8611#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004
8612#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L
8613#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008
8614#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L
8615#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c
8616#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L
8617#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010
8618#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L
8619#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014
8620#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L
8621#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018
8622#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L
8623#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c
8624#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL
8625#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000
8626#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L
8627#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004
8628#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L
8629#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008
8630#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L
8631#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c
8632#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L
8633#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010
8634#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L
8635#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014
8636#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L
8637#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018
8638#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L
8639#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c
8640#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL
8641#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000
8642#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L
8643#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004
8644#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L
8645#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008
8646#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L
8647#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c
8648#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L
8649#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010
8650#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L
8651#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014
8652#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L
8653#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018
8654#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L
8655#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c
8656#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL
8657#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000
8658#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L
8659#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004
8660#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L
8661#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008
8662#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L
8663#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c
8664#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L
8665#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010
8666#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L
8667#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014
8668#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L
8669#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018
8670#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L
8671#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c
8672#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL
8673#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000
8674#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L
8675#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004
8676#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L
8677#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008
8678#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L
8679#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c
8680#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L
8681#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010
8682#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L
8683#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014
8684#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L
8685#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018
8686#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L
8687#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c
8688#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL
8689#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000
8690#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L
8691#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004
8692#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L
8693#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008
8694#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L
8695#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c
8696#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL
8697#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000
8698#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L
8699#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004
8700#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L
8701#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008
8702#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L
8703#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c
8704#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL
8705#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000
8706#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L
8707#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004
8708#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L
8709#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008
8710#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L
8711#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c
8712#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L
8713#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010
8714#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L
8715#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014
8716#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L
8717#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018
8718#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L
8719#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c
8720#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL
8721#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000
8722#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L
8723#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004
8724#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L
8725#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008
8726#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L
8727#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c
8728#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L
8729#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010
8730#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L
8731#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014
8732#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L
8733#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018
8734#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L
8735#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c
8736#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x00000004L
8737#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x00000002
8738#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x00000008L
8739#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x00000003
8740#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x01f00000L
8741#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x00000014
8742#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x00010000L
8743#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x00000010
8744#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x00000001L
8745#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x00000000
8746#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x00000002L
8747#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x00000001
8748#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x00000100L
8749#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000008
8750#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x02000000L
8751#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x00000019
8752#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x00004000L
8753#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0x0000000e
8754#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x00001000L
8755#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0x0000000c
8756#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x00000200L
8757#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000009
8758#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x04000000L
8759#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x0000001a
8760#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x00008000L
8761#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0x0000000f
8762#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x00002000L
8763#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0x0000000d
8764#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x00000010L
8765#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x00000004
8766#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x00000020L
8767#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x00000005
8768#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x00000040L
8769#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x00000006
8770#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x00000080L
8771#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x00000007
8772#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x00000010L
8773#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x00000004
8774#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x00000001L
8775#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x00000000
8776#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x00000100L
8777#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x00000008
8778#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x00000020L
8779#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x00000005
8780#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x00000002L
8781#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x00000001
8782#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x00000200L
8783#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x00000009
8784#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x00000080L
8785#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x00000007
8786#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x00000040L
8787#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x00000006
8788#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000L
8789#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x00000017
8790#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x00000020L
8791#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x00000005
8792#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x00000010L
8793#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x00000004
8794#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x00000008L
8795#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x00000003
8796#define MC_SEQ_SUP_CNTL__RUN_MASK 0x00000001L
8797#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x00000000
8798#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x00000002L
8799#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x00000001
8800#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x00000004L
8801#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x00000002
8802#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffffL
8803#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x00000000
8804#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffffL
8805#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x00000000
8806#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffffL
8807#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x00000000
8808#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffffL
8809#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x00000000
8810#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffffL
8811#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x00000000
8812#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffffL
8813#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x00000000
8814#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffffL
8815#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x00000000
8816#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffffL
8817#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x00000000
8818#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffffL
8819#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x00000000
8820#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x04000000L
8821#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x0000001a
8822#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x02000000L
8823#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x00000019
8824#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x00380000L
8825#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x00000013
8826#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0x0000f000L
8827#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0x0000000c
8828#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000L
8829#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x0000001f
8830#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x00000002L
8831#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x00000001
8832#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x00000004L
8833#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x00000002
8834#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x00040000L
8835#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x00000012
8836#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x00000080L
8837#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x00000007
8838#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x00400000L
8839#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x00000016
8840#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x00010000L
8841#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x00000010
8842#define MC_SEQ_TCG_CNTL__MOP_MASK 0x00000f00L
8843#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x00000008
8844#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x00000070L
8845#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x00000004
8846#define MC_SEQ_TCG_CNTL__RESET_MASK 0x00000001L
8847#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x00000000
8848#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x00020000L
8849#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x00000011
8850#define MC_SEQ_TCG_CNTL__START_MASK 0x00000008L
8851#define MC_SEQ_TCG_CNTL__START__SHIFT 0x00000003
8852#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x00800000L
8853#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x00000017
8854#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x01000000L
8855#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x00000018
8856#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffffL
8857#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x00000000
8858#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffffL
8859#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x00000000
8860#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L
8861#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012
8862#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L
8863#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013
8864#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L
8865#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015
8866#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L
8867#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016
8868#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x00000001L
8869#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x00000000
8870#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L
8871#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008
8872#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L
8873#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a
8874#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x01000000L
8875#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x00000018
8876#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x00000004L
8877#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x00000002
8878#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x00000010L
8879#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x00000004
8880#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x00000002L
8881#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x00000001
8882#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L
8883#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009
8884#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L
8885#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b
8886#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x02000000L
8887#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x00000019
8888#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x00000008L
8889#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x00000003
8890#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x00000020L
8891#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x00000005
8892#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x00800000L
8893#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x00000017
8894#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x00100000L
8895#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x00000014
8896#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L
8897#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006
8898#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x04000000L
8899#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x0000001a
8900#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x00002000L
8901#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0x0000000d
8902#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L
8903#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007
8904#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L
8905#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c
8906#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x00020000L
8907#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x00000011
8908#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x00008000L
8909#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f
8910#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x00004000L
8911#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0x0000000e
8912#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffffL
8913#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x00000000
8914#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000100L
8915#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000008
8916#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x00000001L
8917#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x00000000
8918#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000200L
8919#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000009
8920#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x00000002L
8921#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x00000001
8922#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x00000004L
8923#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x00000002
8924#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x00000030L
8925#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x00000004
8926#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x00000008L
8927#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x00000003
8928#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000L
8929#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x00000010
8930#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0x0000ffffL
8931#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x00000000
8932#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x000003e0L
8933#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x00000005
8934#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0x000f8000L
8935#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0x0000000f
8936#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x00007c00L
8937#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0x0000000a
8938#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x0000001fL
8939#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x00000000
8940#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x00040000L
8941#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012
8942#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x00080000L
8943#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013
8944#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L
8945#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015
8946#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L
8947#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016
8948#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x00010000L
8949#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x00000010
8950#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x00000001L
8951#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x00000000
8952#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L
8953#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008
8954#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L
8955#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a
8956#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x01000000L
8957#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x00000018
8958#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x00000004L
8959#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x00000002
8960#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x00000010L
8961#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x00000004
8962#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x00000002L
8963#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x00000001
8964#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L
8965#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009
8966#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L
8967#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b
8968#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x02000000L
8969#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x00000019
8970#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x00000008L
8971#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x00000003
8972#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x00000020L
8973#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x00000005
8974#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x00800000L
8975#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x00000017
8976#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x00100000L
8977#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x00000014
8978#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L
8979#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006
8980#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x04000000L
8981#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x0000001a
8982#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x00002000L
8983#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0x0000000d
8984#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L
8985#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007
8986#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L
8987#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c
8988#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x00020000L
8989#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x00000011
8990#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x00008000L
8991#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0x0000000f
8992#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x00004000L
8993#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0x0000000e
8994#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x00000100L
8995#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x00000008
8996#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x00000400L
8997#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0x0000000a
8998#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x00100000L
8999#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x00000014
9000#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x00000200L
9001#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x00000009
9002#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x00000800L
9003#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0x0000000b
9004#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x01000000L
9005#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x00000018
9006#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x04000000L
9007#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x0000001a
9008#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x02000000L
9009#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x00000019
9010#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x08000000L
9011#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x0000001b
9012#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x00000001L
9013#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x00000000
9014#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x00000004L
9015#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x00000002
9016#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x00000002L
9017#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x00000001
9018#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x00000008L
9019#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x00000003
9020#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000L
9021#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x0000001d
9022#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x00010000L
9023#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x00000010
9024#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x00040000L
9025#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x00000012
9026#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x00020000L
9027#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x00000011
9028#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x00080000L
9029#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x00000013
9030#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x00000010L
9031#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x00000004
9032#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x00000040L
9033#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x00000006
9034#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x00000020L
9035#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x00000005
9036#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x00000080L
9037#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x00000007
9038#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x00200000L
9039#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x00000015
9040#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x00400000L
9041#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x00000016
9042#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000L
9043#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x0000001c
9044#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000L
9045#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x0000001e
9046#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000L
9047#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x0000001f
9048#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x00001000L
9049#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0x0000000c
9050#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x00004000L
9051#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0x0000000e
9052#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x00002000L
9053#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0x0000000d
9054#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x00008000L
9055#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0x0000000f
9056#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L
9057#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012
9058#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L
9059#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013
9060#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L
9061#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015
9062#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L
9063#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016
9064#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x00000001L
9065#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x00000000
9066#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L
9067#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008
9068#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L
9069#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a
9070#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x01000000L
9071#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x00000018
9072#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x00000004L
9073#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x00000002
9074#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x00000010L
9075#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x00000004
9076#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x00000002L
9077#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x00000001
9078#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L
9079#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009
9080#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L
9081#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b
9082#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x02000000L
9083#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x00000019
9084#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x00000008L
9085#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x00000003
9086#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x00000020L
9087#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x00000005
9088#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x00800000L
9089#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x00000017
9090#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x00100000L
9091#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x00000014
9092#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L
9093#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006
9094#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x04000000L
9095#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x0000001a
9096#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x00002000L
9097#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0x0000000d
9098#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L
9099#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007
9100#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L
9101#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c
9102#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x00020000L
9103#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x00000011
9104#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x00008000L
9105#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f
9106#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x00004000L
9107#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0x0000000e
9108#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x00040000L
9109#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012
9110#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x00080000L
9111#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013
9112#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L
9113#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015
9114#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L
9115#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016
9116#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x00000001L
9117#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x00000000
9118#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L
9119#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008
9120#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L
9121#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a
9122#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x01000000L
9123#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x00000018
9124#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x00000004L
9125#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x00000002
9126#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x00000010L
9127#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x00000004
9128#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x00000002L
9129#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x00000001
9130#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L
9131#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009
9132#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L
9133#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b
9134#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x02000000L
9135#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x00000019
9136#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x00000008L
9137#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x00000003
9138#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x00000020L
9139#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x00000005
9140#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x00800000L
9141#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x00000017
9142#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x00100000L
9143#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x00000014
9144#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L
9145#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006
9146#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x04000000L
9147#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x0000001a
9148#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x00002000L
9149#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0x0000000d
9150#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L
9151#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007
9152#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L
9153#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c
9154#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x00020000L
9155#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x00000011
9156#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x00008000L
9157#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0x0000000f
9158#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x00004000L
9159#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0x0000000e
9160#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0x0000ff00L
9161#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x00000008
9162#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0x00ff0000L
9163#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x00000010
9164#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000L
9165#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x00000018
9166#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0x000000f0L
9167#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x00000004
9168#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0x0000000fL
9169#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x00000000
9170#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x00000002L
9171#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x00000001
9172#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x00000020L
9173#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x00000005
9174#define MC_SEQ_TSM_CTRL__DONE_MASK 0x00000004L
9175#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x00000002
9176#define MC_SEQ_TSM_CTRL__ERR_MASK 0x00000008L
9177#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x00000003
9178#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x00000040L
9179#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x00000006
9180#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x00000080L
9181#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x00000007
9182#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000L
9183#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x00000010
9184#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x00000400L
9185#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0x0000000a
9186#define MC_SEQ_TSM_CTRL__START_MASK 0x00000001L
9187#define MC_SEQ_TSM_CTRL__START__SHIFT 0x00000000
9188#define MC_SEQ_TSM_CTRL__STEP_MASK 0x00000010L
9189#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x00000004
9190#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x00000300L
9191#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x00000008
9192#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffffL
9193#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x00000000
9194#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffffL
9195#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x00000000
9196#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x0000001fL
9197#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x00000000
9198#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffffL
9199#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x00000000
9200#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000L
9201#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x00000018
9202#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0x000000f0L
9203#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x00000004
9204#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0x0000ff00L
9205#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x00000008
9206#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0x000f0000L
9207#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x00000010
9208#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0x0000000fL
9209#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x00000000
9210#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000L
9211#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x00000010
9212#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0x000000f0L
9213#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x00000004
9214#define MC_SEQ_TSM_GCNT__TESTS_MASK 0x0000ff00L
9215#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x00000008
9216#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0x0000000fL
9217#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x00000000
9218#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0x000f0000L
9219#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x00000010
9220#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0x0000ffffL
9221#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x00000000
9222#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0x000000f0L
9223#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x00000004
9224#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0x0f000000L
9225#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x00000018
9226#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0x00f00000L
9227#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x00000014
9228#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0x000f0000L
9229#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x00000010
9230#define MC_SEQ_TSM_NCNT__TESTS_MASK 0x0000ff00L
9231#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x00000008
9232#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0x0000000fL
9233#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x00000000
9234#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000L
9235#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x00000010
9236#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0x000000f0L
9237#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x00000004
9238#define MC_SEQ_TSM_OCNT__TESTS_MASK 0x0000ff00L
9239#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x00000008
9240#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0x0000000fL
9241#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x00000000
9242#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0x00ff0000L
9243#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x00000010
9244#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000L
9245#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x00000018
9246#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0x000000f0L
9247#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x00000004
9248#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0x0000000fL
9249#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x00000000
9250#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0x0000ff00L
9251#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x00000008
9252#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffffL
9253#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x00000000
9254#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL
9255#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000
9256#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L
9257#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004
9258#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L
9259#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008
9260#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L
9261#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c
9262#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L
9263#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010
9264#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L
9265#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014
9266#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L
9267#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018
9268#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L
9269#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c
9270#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL
9271#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000
9272#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L
9273#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004
9274#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L
9275#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008
9276#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L
9277#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c
9278#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L
9279#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010
9280#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L
9281#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014
9282#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L
9283#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018
9284#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L
9285#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c
9286#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL
9287#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000
9288#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L
9289#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004
9290#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L
9291#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008
9292#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L
9293#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c
9294#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L
9295#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010
9296#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L
9297#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014
9298#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L
9299#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018
9300#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L
9301#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c
9302#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL
9303#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000
9304#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L
9305#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004
9306#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L
9307#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008
9308#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L
9309#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c
9310#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L
9311#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010
9312#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L
9313#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014
9314#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L
9315#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018
9316#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L
9317#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c
9318#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL
9319#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000
9320#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L
9321#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004
9322#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L
9323#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008
9324#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L
9325#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c
9326#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L
9327#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010
9328#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L
9329#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014
9330#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L
9331#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018
9332#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L
9333#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c
9334#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL
9335#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000
9336#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L
9337#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004
9338#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L
9339#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008
9340#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L
9341#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c
9342#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L
9343#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010
9344#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L
9345#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014
9346#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L
9347#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018
9348#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L
9349#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c
9350#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL
9351#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000
9352#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L
9353#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004
9354#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L
9355#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008
9356#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L
9357#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c
9358#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L
9359#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010
9360#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L
9361#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014
9362#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L
9363#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018
9364#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L
9365#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c
9366#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL
9367#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000
9368#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L
9369#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004
9370#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L
9371#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008
9372#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L
9373#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c
9374#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L
9375#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010
9376#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L
9377#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014
9378#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L
9379#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018
9380#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L
9381#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c
9382#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL
9383#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000
9384#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L
9385#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004
9386#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L
9387#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008
9388#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L
9389#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c
9390#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL
9391#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000
9392#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L
9393#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004
9394#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L
9395#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008
9396#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L
9397#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c
9398#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL
9399#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000
9400#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L
9401#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004
9402#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L
9403#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008
9404#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L
9405#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c
9406#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L
9407#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010
9408#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L
9409#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014
9410#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L
9411#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018
9412#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L
9413#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c
9414#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL
9415#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000
9416#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L
9417#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004
9418#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L
9419#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008
9420#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L
9421#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c
9422#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L
9423#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010
9424#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L
9425#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014
9426#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L
9427#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018
9428#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L
9429#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c
9430#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0x0000000fL
9431#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x00000000
9432#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0x000000f0L
9433#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x00000004
9434#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0x00000f00L
9435#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x00000008
9436#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0x0000f000L
9437#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0x0000000c
9438#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0x0000000fL
9439#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x00000000
9440#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0x000000f0L
9441#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x00000004
9442#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0x00000f00L
9443#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x00000008
9444#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0x0000f000L
9445#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0x0000000c
9446#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffffL
9447#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x00000000
9448#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffffL
9449#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x00000000
9450#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x00004000L
9451#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0x0000000e
9452#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x00100000L
9453#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x00000014
9454#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x00200000L
9455#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x00000015
9456#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0x0f000000L
9457#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x00000018
9458#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000L
9459#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x0000001c
9460#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x00002000L
9461#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0x0000000d
9462#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x00008000L
9463#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0x0000000f
9464#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0x000f0000L
9465#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x00000010
9466#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0x000000ffL
9467#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x00000000
9468#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0x00000f00L
9469#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x00000008
9470#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x00001000L
9471#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0x0000000c
9472#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x00000001L
9473#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x00000000
9474#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x00000008L
9475#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x00000003
9476#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x00000002L
9477#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x00000001
9478#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x00000010L
9479#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x00000004
9480#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x00000001L
9481#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x00000000
9482#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x00000008L
9483#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x00000003
9484#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x00000002L
9485#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x00000001
9486#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x00000010L
9487#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x00000004
9488#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x00000004L
9489#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x00000002
9490#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x00000020L
9491#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x00000005
9492#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x00000040L
9493#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x00000006
9494#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x00000004L
9495#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x00000002
9496#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x00000020L
9497#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x00000005
9498#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x00000040L
9499#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x00000006
9500#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x00000400L
9501#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0x0000000a
9502#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000L
9503#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x0000001d
9504#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x00000800L
9505#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0x0000000b
9506#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000L
9507#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x0000001e
9508#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x00000200L
9509#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x00000009
9510#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0x0000000fL
9511#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x00000000
9512#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0x000000f0L
9513#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x00000004
9514#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x00000100L
9515#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x00000008
9516#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x00000400L
9517#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0x0000000a
9518#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000L
9519#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x0000001d
9520#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x00000800L
9521#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0x0000000b
9522#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000L
9523#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x0000001e
9524#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x00000200L
9525#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x00000009
9526#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0x0000000fL
9527#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x00000000
9528#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0x000000f0L
9529#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x00000004
9530#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x00000100L
9531#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x00000008
9532#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0x0f000000L
9533#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x00000018
9534#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000L
9535#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x0000001c
9536#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0x0000f000L
9537#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0x0000000c
9538#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0x000f0000L
9539#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x00000010
9540#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x00300000L
9541#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x00000014
9542#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0x0f000000L
9543#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x00000018
9544#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000L
9545#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x0000001c
9546#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0x0000f000L
9547#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0x0000000c
9548#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0x000f0000L
9549#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x00000010
9550#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x00300000L
9551#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x00000014
9552#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x00000400L
9553#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0x0000000a
9554#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000L
9555#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x0000001d
9556#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x00000800L
9557#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0x0000000b
9558#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000L
9559#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x0000001e
9560#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x00000200L
9561#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x00000009
9562#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0x0000000fL
9563#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x00000000
9564#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0x000000f0L
9565#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x00000004
9566#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x00000100L
9567#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x00000008
9568#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x00000400L
9569#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0x0000000a
9570#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000L
9571#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x0000001d
9572#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x00000800L
9573#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0x0000000b
9574#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000L
9575#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x0000001e
9576#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x00000200L
9577#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x00000009
9578#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0x0000000fL
9579#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x00000000
9580#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0x000000f0L
9581#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x00000004
9582#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x00000100L
9583#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x00000008
9584#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0x0f000000L
9585#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x00000018
9586#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000L
9587#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x0000001c
9588#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0x0000f000L
9589#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0x0000000c
9590#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0x000f0000L
9591#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x00000010
9592#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x00300000L
9593#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x00000014
9594#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0x0f000000L
9595#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x00000018
9596#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000L
9597#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x0000001c
9598#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0x0000f000L
9599#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0x0000000c
9600#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0x000f0000L
9601#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x00000010
9602#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x00300000L
9603#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x00000014
9604#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x00000007L
9605#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x00000000
9606#define MC_SHARED_CHMAP__CHAN0_MASK 0x0000000fL
9607#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x00000000
9608#define MC_SHARED_CHMAP__CHAN1_MASK 0x000000f0L
9609#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x00000004
9610#define MC_SHARED_CHMAP__CHAN2_MASK 0x00000f00L
9611#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x00000008
9612#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0x0000f000L
9613#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0x0000000c
9614#define MC_SHARED_CHREMAP__CHAN0_MASK 0x00000007L
9615#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x00000000
9616#define MC_SHARED_CHREMAP__CHAN1_MASK 0x00000038L
9617#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x00000003
9618#define MC_SHARED_CHREMAP__CHAN2_MASK 0x000001c0L
9619#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x00000006
9620#define MC_SHARED_CHREMAP__CHAN3_MASK 0x00000e00L
9621#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x00000009
9622#define MC_SHARED_CHREMAP__CHAN4_MASK 0x00007000L
9623#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x0000000c
9624#define MC_SHARED_CHREMAP__CHAN5_MASK 0x00038000L
9625#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x0000000f
9626#define MC_SHARED_CHREMAP__CHAN6_MASK 0x001c0000L
9627#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x00000012
9628#define MC_SHARED_CHREMAP__CHAN7_MASK 0x00e00000L
9629#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x00000015
9630#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0x000000ffL
9631#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x00000000
9632#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0x0000ff00L
9633#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x00000008
9634#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0x00ff0000L
9635#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x00000010
9636#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000L
9637#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x00000018
9638#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0x000000ffL
9639#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x00000000
9640#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0x0000ff00L
9641#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x00000008
9642#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0x00ff0000L
9643#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x00000010
9644#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000L
9645#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x00000018
9646#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000L
9647#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x00000010
9648#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0x0000ffffL
9649#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x00000000
9650#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000L
9651#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x00000010
9652#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0x0000ffffL
9653#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x00000000
9654#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffffL
9655#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x00000000
9656#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffffL
9657#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x00000000
9658#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0x0000000fL
9659#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x00000000
9660#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0x000000f0L
9661#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x00000004
9662#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000L
9663#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x0000001c
9664#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000L
9665#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x0000001d
9666#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000L
9667#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x0000001e
9668#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0x0000f000L
9669#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0x0000000c
9670#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0x00000f00L
9671#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x00000008
9672#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0x0000000fL
9673#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x00000000
9674#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0x000000f0L
9675#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x00000004
9676#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000L
9677#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x0000001c
9678#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000L
9679#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x0000001d
9680#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000L
9681#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x0000001e
9682#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0x0000f000L
9683#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0x0000000c
9684#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0x00000f00L
9685#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x00000008
9686#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000L
9687#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x0000001c
9688#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x03ff0000L
9689#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x00000010
9690#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x00000400L
9691#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0x0000000a
9692#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x00000002L
9693#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x00000001
9694#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x00000100L
9695#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x00000008
9696#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x00000001L
9697#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x00000000
9698#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x00000030L
9699#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x00000004
9700#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x00000200L
9701#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x00000009
9702#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x00000800L
9703#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0x0000000b
9704#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000L
9705#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x0000001c
9706#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x03ff0000L
9707#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x00000010
9708#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x00000400L
9709#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0x0000000a
9710#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x00000002L
9711#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x00000001
9712#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x00000100L
9713#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x00000008
9714#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x00000001L
9715#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x00000000
9716#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x00000030L
9717#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x00000004
9718#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x00000200L
9719#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x00000009
9720#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x00000800L
9721#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0x0000000b
9722#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0x000000ffL
9723#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x00000000
9724#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0x0000ff00L
9725#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x00000008
9726#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0x00ff0000L
9727#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x00000010
9728#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000L
9729#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x00000018
9730#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0x000000ffL
9731#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x00000000
9732#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0x0000ff00L
9733#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x00000008
9734#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0x00ff0000L
9735#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x00000010
9736#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000L
9737#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x00000018
9738#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0x000000ffL
9739#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x00000000
9740#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0x0000ff00L
9741#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x00000008
9742#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0x00ff0000L
9743#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x00000010
9744#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000L
9745#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x00000018
9746#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0x000000ffL
9747#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x00000000
9748#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0x0000ff00L
9749#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x00000008
9750#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0x00ff0000L
9751#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x00000010
9752#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000L
9753#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x00000018
9754#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0x000000ffL
9755#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x00000000
9756#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0x0000ff00L
9757#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x00000008
9758#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0x00ff0000L
9759#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x00000010
9760#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000L
9761#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x00000018
9762#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0x000000ffL
9763#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x00000000
9764#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0x0000ff00L
9765#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x00000008
9766#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0x00ff0000L
9767#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x00000010
9768#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000L
9769#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x00000018
9770#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0x000000ffL
9771#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x00000000
9772#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0x0000ff00L
9773#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x00000008
9774#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0x00ff0000L
9775#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x00000010
9776#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000L
9777#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x00000018
9778#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0x000000ffL
9779#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x00000000
9780#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0x0000ff00L
9781#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x00000008
9782#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0x00ff0000L
9783#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x00000010
9784#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000L
9785#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x00000018
9786#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0x000000ffL
9787#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x00000000
9788#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0x0000ff00L
9789#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x00000008
9790#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0x00ff0000L
9791#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x00000010
9792#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000L
9793#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x00000018
9794#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0x000000ffL
9795#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x00000000
9796#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0x0000ff00L
9797#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x00000008
9798#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0x00ff0000L
9799#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x00000010
9800#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000L
9801#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x00000018
9802#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0x000000ffL
9803#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x00000000
9804#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0x0000ff00L
9805#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x00000008
9806#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0x00ff0000L
9807#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x00000010
9808#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000L
9809#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x00000018
9810#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffffL
9811#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x00000000
9812#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffffL
9813#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x00000000
9814#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffffL
9815#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x00000000
9816#define MC_TSM_DEBUG_MISC__FLAG_MASK 0x000000ffL
9817#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x00000000
9818#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0x00000f00L
9819#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x00000008
9820#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0x0000f000L
9821#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0x0000000c
9822#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffffL
9823#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x00000000
9824#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffffL
9825#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x00000000
9826#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffffL
9827#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x00000000
9828#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x0003ffffL
9829#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x00000000
9830#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x0003ffffL
9831#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x00000000
9832#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x0003ffffL
9833#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x00000000
9834#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x00000100L
9835#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x00000008
9836#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x00000200L
9837#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x00000009
9838#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x00000003L
9839#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x00000000
9840#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0x0000000cL
9841#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x00000002
9842#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x00000030L
9843#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x00000004
9844#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0x000000c0L
9845#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x00000006
9846#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9847#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9848#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9849#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9850#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9851#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9852#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9853#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9854#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9855#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9856#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9857#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9858#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9859#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9860#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL
9861#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000
9862#define MC_VM_FB_LOCATION__FB_BASE_MASK 0x0000ffffL
9863#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x00000000
9864#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000L
9865#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x00000010
9866#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0003ffffL
9867#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x00000000
9868#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9869#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9870#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9871#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9872#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9873#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9874#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9875#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9876#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9877#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9878#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
9879#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000
9880#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
9881#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000
9882#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9883#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9884#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9885#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9886#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9887#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9888#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9889#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9890#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9891#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9892#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
9893#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000
9894#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9895#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9896#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9897#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9898#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9899#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9900#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9901#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9902#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9903#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9904#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
9905#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000
9906#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL
9907#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000
9908#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9909#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9910#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9911#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9912#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9913#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9914#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9915#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9916#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9917#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9918#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
9919#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000
9920#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9921#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9922#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9923#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9924#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9925#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9926#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9927#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9928#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9929#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9930#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
9931#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000
9932#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9933#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9934#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9935#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9936#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9937#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9938#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9939#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9940#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9941#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9942#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
9943#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000
9944#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L
9945#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c
9946#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L
9947#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009
9948#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L
9949#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000
9950#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L
9951#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f
9952#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L
9953#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008
9954#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
9955#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000
9956#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL
9957#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000
9958#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
9959#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x00000007
9960#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
9961#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x00000006
9962#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x00000002L
9963#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x00000001
9964#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
9965#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x00000000
9966#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
9967#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x00000003
9968#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
9969#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x00000005
9970#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
9971#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
9972#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
9973#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
9974#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
9975#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
9976#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x00000008L
9977#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003
9978#define MC_WR_CB__ENABLE_MASK 0x00000001L
9979#define MC_WR_CB__ENABLE__SHIFT 0x00000000
9980#define MC_WR_CB__LAZY_TIMER_MASK 0x00007800L
9981#define MC_WR_CB__LAZY_TIMER__SHIFT 0x0000000b
9982#define MC_WR_CB__MAX_BURST_MASK 0x00000780L
9983#define MC_WR_CB__MAX_BURST__SHIFT 0x00000007
9984#define MC_WR_CB__PRESCALE_MASK 0x00000006L
9985#define MC_WR_CB__PRESCALE__SHIFT 0x00000001
9986#define MC_WR_CB__STALL_MODE_MASK 0x00000030L
9987#define MC_WR_CB__STALL_MODE__SHIFT 0x00000004
9988#define MC_WR_CB__STALL_OVERRIDE_MASK 0x00000040L
9989#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x00000006
9990#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L
9991#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
9992#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x00000008L
9993#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003
9994#define MC_WR_DB__ENABLE_MASK 0x00000001L
9995#define MC_WR_DB__ENABLE__SHIFT 0x00000000
9996#define MC_WR_DB__LAZY_TIMER_MASK 0x00007800L
9997#define MC_WR_DB__LAZY_TIMER__SHIFT 0x0000000b
9998#define MC_WR_DB__MAX_BURST_MASK 0x00000780L
9999#define MC_WR_DB__MAX_BURST__SHIFT 0x00000007
10000#define MC_WR_DB__PRESCALE_MASK 0x00000006L
10001#define MC_WR_DB__PRESCALE__SHIFT 0x00000001
10002#define MC_WR_DB__STALL_MODE_MASK 0x00000030L
10003#define MC_WR_DB__STALL_MODE__SHIFT 0x00000004
10004#define MC_WR_DB__STALL_OVERRIDE_MASK 0x00000040L
10005#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x00000006
10006#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L
10007#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
10008#define MC_WR_GRP_EXT__DBSTEN0_MASK 0x0000000fL
10009#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x00000000
10010#define MC_WR_GRP_EXT__TC0_MASK 0x000000f0L
10011#define MC_WR_GRP_EXT__TC0__SHIFT 0x00000004
10012#define MC_WR_GRP_GFX__CP_MASK 0x0000000fL
10013#define MC_WR_GRP_GFX__CP__SHIFT 0x00000000
10014#define MC_WR_GRP_GFX__XDMA_MASK 0x0000f000L
10015#define MC_WR_GRP_GFX__XDMAM_MASK 0x000f0000L
10016#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x00000010
10017#define MC_WR_GRP_GFX__XDMA__SHIFT 0x0000000c
10018#define MC_WR_GRP_LCL__CB0_MASK 0x0000000fL
10019#define MC_WR_GRP_LCL__CB0__SHIFT 0x00000000
10020#define MC_WR_GRP_LCL__CBCMASK0_MASK 0x000000f0L
10021#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x00000004
10022#define MC_WR_GRP_LCL__CBFMASK0_MASK 0x00000f00L
10023#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x00000008
10024#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000L
10025#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x0000001c
10026#define MC_WR_GRP_LCL__DB0_MASK 0x0000f000L
10027#define MC_WR_GRP_LCL__DB0__SHIFT 0x0000000c
10028#define MC_WR_GRP_LCL__DBHTILE0_MASK 0x000f0000L
10029#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x00000010
10030#define MC_WR_GRP_LCL__SX0_MASK 0x00f00000L
10031#define MC_WR_GRP_LCL__SX0__SHIFT 0x00000014
10032#define MC_WR_GRP_OTH__HDP_MASK 0x00000f00L
10033#define MC_WR_GRP_OTH__HDP__SHIFT 0x00000008
10034#define MC_WR_GRP_OTH__SEM_MASK 0x0000f000L
10035#define MC_WR_GRP_OTH__SEM__SHIFT 0x0000000c
10036#define MC_WR_GRP_OTH__UMC_MASK 0x000f0000L
10037#define MC_WR_GRP_OTH__UMC__SHIFT 0x00000010
10038#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0x0000000fL
10039#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x00000000
10040#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000L
10041#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x0000001c
10042#define MC_WR_GRP_OTH__UVD_MASK 0x00f00000L
10043#define MC_WR_GRP_OTH__UVD__SHIFT 0x00000014
10044#define MC_WR_GRP_OTH__XDP_MASK 0x0f000000L
10045#define MC_WR_GRP_OTH__XDP__SHIFT 0x00000018
10046#define MC_WR_GRP_SYS__IH_MASK 0x0000000fL
10047#define MC_WR_GRP_SYS__IH__SHIFT 0x00000000
10048#define MC_WR_GRP_SYS__MCIF_MASK 0x000000f0L
10049#define MC_WR_GRP_SYS__MCIF__SHIFT 0x00000004
10050#define MC_WR_GRP_SYS__RLC_MASK 0x00000f00L
10051#define MC_WR_GRP_SYS__RLC__SHIFT 0x00000008
10052#define MC_WR_GRP_SYS__SMU_MASK 0x00f00000L
10053#define MC_WR_GRP_SYS__SMU__SHIFT 0x00000014
10054#define MC_WR_GRP_SYS__VCE_MASK 0x0f000000L
10055#define MC_WR_GRP_SYS__VCE__SHIFT 0x00000018
10056#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000L
10057#define MC_WR_GRP_SYS__VCEU__SHIFT 0x0000001c
10058#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L
10059#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003
10060#define MC_WR_HUB__ENABLE_MASK 0x00000001L
10061#define MC_WR_HUB__ENABLE__SHIFT 0x00000000
10062#define MC_WR_HUB__LAZY_TIMER_MASK 0x00007800L
10063#define MC_WR_HUB__LAZY_TIMER__SHIFT 0x0000000b
10064#define MC_WR_HUB__MAX_BURST_MASK 0x00000780L
10065#define MC_WR_HUB__MAX_BURST__SHIFT 0x00000007
10066#define MC_WR_HUB__PRESCALE_MASK 0x00000006L
10067#define MC_WR_HUB__PRESCALE__SHIFT 0x00000001
10068#define MC_WR_HUB__STALL_MODE_MASK 0x00000030L
10069#define MC_WR_HUB__STALL_MODE__SHIFT 0x00000004
10070#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x00000040L
10071#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x00000006
10072#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L
10073#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
10074#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L
10075#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003
10076#define MC_WR_TC0__ENABLE_MASK 0x00000001L
10077#define MC_WR_TC0__ENABLE__SHIFT 0x00000000
10078#define MC_WR_TC0__LAZY_TIMER_MASK 0x00007800L
10079#define MC_WR_TC0__LAZY_TIMER__SHIFT 0x0000000b
10080#define MC_WR_TC0__MAX_BURST_MASK 0x00000780L
10081#define MC_WR_TC0__MAX_BURST__SHIFT 0x00000007
10082#define MC_WR_TC0__PRESCALE_MASK 0x00000006L
10083#define MC_WR_TC0__PRESCALE__SHIFT 0x00000001
10084#define MC_WR_TC0__STALL_MODE_MASK 0x00000030L
10085#define MC_WR_TC0__STALL_MODE__SHIFT 0x00000004
10086#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x00000040L
10087#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x00000006
10088#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L
10089#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
10090#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L
10091#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003
10092#define MC_WR_TC1__ENABLE_MASK 0x00000001L
10093#define MC_WR_TC1__ENABLE__SHIFT 0x00000000
10094#define MC_WR_TC1__LAZY_TIMER_MASK 0x00007800L
10095#define MC_WR_TC1__LAZY_TIMER__SHIFT 0x0000000b
10096#define MC_WR_TC1__MAX_BURST_MASK 0x00000780L
10097#define MC_WR_TC1__MAX_BURST__SHIFT 0x00000007
10098#define MC_WR_TC1__PRESCALE_MASK 0x00000006L
10099#define MC_WR_TC1__PRESCALE__SHIFT 0x00000001
10100#define MC_WR_TC1__STALL_MODE_MASK 0x00000030L
10101#define MC_WR_TC1__STALL_MODE__SHIFT 0x00000004
10102#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x00000040L
10103#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x00000006
10104#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L
10105#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
10106#define MC_XBAR_ADDR_DEC__GECC_MASK 0x00000002L
10107#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x00000001
10108#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x00000001L
10109#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x00000000
10110#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x00000008L
10111#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x00000003
10112#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x00000004L
10113#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x00000002
10114#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x00000004L
10115#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x00000002
10116#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x00000002L
10117#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x00000001
10118#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x00000001L
10119#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x00000000
10120#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0x0000000fL
10121#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x00000000
10122#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0x000000f0L
10123#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x00000004
10124#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0x00000f00L
10125#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x00000008
10126#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0x0000f000L
10127#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0x0000000c
10128#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0x000f0000L
10129#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x00000010
10130#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0x00f00000L
10131#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x00000014
10132#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0x0f000000L
10133#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x00000018
10134#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000L
10135#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x0000001c
10136#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x00000003L
10137#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x00000000
10138#define MC_XBAR_CHTRIREMAP__CH1_MASK 0x0000000cL
10139#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x00000002
10140#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x00000030L
10141#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x00000004
10142#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L
10143#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c
10144#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L
10145#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018
10146#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL
10147#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000
10148#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L
10149#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a
10150#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L
10151#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c
10152#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x0000ff00L
10153#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000008
10154#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x00ff0000L
10155#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x00000010
10156#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x000000ffL
10157#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000
10158#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0x000000ffL
10159#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x00000000
10160#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0x0000ff00L
10161#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x00000008
10162#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0x00ff0000L
10163#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x00000010
10164#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000L
10165#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x00000018
10166#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0x000000ffL
10167#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x00000000
10168#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0x0000ff00L
10169#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x00000008
10170#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0x00ff0000L
10171#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x00000010
10172#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000L
10173#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x00000018
10174#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL
10175#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000
10176#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL
10177#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000
10178#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffffL
10179#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x00000000
10180#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffffL
10181#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x00000000
10182#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0x000000ffL
10183#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x00000000
10184#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0x0000ff00L
10185#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x00000008
10186#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0x00ff0000L
10187#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x00000010
10188#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000L
10189#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x00000018
10190#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0x000000ffL
10191#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x00000000
10192#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0x0000ff00L
10193#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x00000008
10194#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0x00ff0000L
10195#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x00000010
10196#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000L
10197#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x00000018
10198#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0x000000ffL
10199#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x00000000
10200#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0x0000ff00L
10201#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x00000008
10202#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0x00ff0000L
10203#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x00000010
10204#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000L
10205#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x00000018
10206#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0x00ff0000L
10207#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x00000010
10208#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0x000000ffL
10209#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x00000000
10210#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0x0000ff00L
10211#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x00000008
10212#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0x000000ffL
10213#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x00000000
10214#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0x0000ff00L
10215#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x00000008
10216#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0x00ff0000L
10217#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x00000010
10218#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000L
10219#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x00000018
10220#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0x000000ffL
10221#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x00000000
10222#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0x0000ff00L
10223#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x00000008
10224#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x00000002L
10225#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x00000001
10226#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x00000001L
10227#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x00000000
10228#define MC_XBAR_SPARE0__BIT_MASK 0xffffffffL
10229#define MC_XBAR_SPARE0__BIT__SHIFT 0x00000000
10230#define MC_XBAR_SPARE1__BIT_MASK 0xffffffffL
10231#define MC_XBAR_SPARE1__BIT__SHIFT 0x00000000
10232#define MC_XBAR_TWOCHAN__CH0_MASK 0x00000006L
10233#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x00000001
10234#define MC_XBAR_TWOCHAN__CH1_MASK 0x00000018L
10235#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x00000003
10236#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x00000001L
10237#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x00000000
10238#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0x000000ffL
10239#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x00000000
10240#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0x0000ff00L
10241#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x00000008
10242#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0x00ff0000L
10243#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x00000010
10244#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000L
10245#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x00000018
10246#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0x000000ffL
10247#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x00000000
10248#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0x0000ff00L
10249#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x00000008
10250#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0x00ff0000L
10251#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x00000010
10252#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000L
10253#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x00000018
10254#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0x000000ffL
10255#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x00000000
10256#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0x0000ff00L
10257#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x00000008
10258#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003c00L
10259#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0x0000000a
10260#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L
10261#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x00000004
10262#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L
10263#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x00000007
10264#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003c000L
10265#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0x0000000e
10266#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000fL
10267#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x00000000
10268#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x00003c00L
10269#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0x0000000a
10270#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x00000070L
10271#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x00000004
10272#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x00000380L
10273#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x00000007
10274#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x0003c000L
10275#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0x0000000e
10276#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0x0000000fL
10277#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x00000000
10278#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x00003c00L
10279#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0x0000000a
10280#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x00000070L
10281#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x00000004
10282#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x00000380L
10283#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x00000007
10284#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x0003c000L
10285#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0x0000000e
10286#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0x0000000fL
10287#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x00000000
10288#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x00003c00L
10289#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0x0000000a
10290#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x00000070L
10291#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x00000004
10292#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x00000380L
10293#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x00000007
10294#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x0003c000L
10295#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0x0000000e
10296#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0x0000000fL
10297#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x00000000
10298#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x00003c00L
10299#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0x0000000a
10300#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x00000070L
10301#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x00000004
10302#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x00000380L
10303#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x00000007
10304#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x0003c000L
10305#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0x0000000e
10306#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0x0000000fL
10307#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x00000000
10308#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x00003c00L
10309#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0x0000000a
10310#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x00000070L
10311#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x00000004
10312#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x00000380L
10313#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x00000007
10314#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x0003c000L
10315#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0x0000000e
10316#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0x0000000fL
10317#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x00000000
10318#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x00003c00L
10319#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0x0000000a
10320#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x00000070L
10321#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x00000004
10322#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x00000380L
10323#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x00000007
10324#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x0003c000L
10325#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0x0000000e
10326#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0x0000000fL
10327#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x00000000
10328#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x00003c00L
10329#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0x0000000a
10330#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x00000070L
10331#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x00000004
10332#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x00000380L
10333#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x00000007
10334#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x0003c000L
10335#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0x0000000e
10336#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0x0000000fL
10337#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x00000000
10338#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x00003c00L
10339#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0x0000000a
10340#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x00000070L
10341#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x00000004
10342#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x00000380L
10343#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x00000007
10344#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x0003c000L
10345#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0x0000000e
10346#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0x0000000fL
10347#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x00000000
10348#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x00003c00L
10349#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0x0000000a
10350#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x00000070L
10351#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x00000004
10352#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x00000380L
10353#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x00000007
10354#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x0003c000L
10355#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0x0000000e
10356#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0x0000000fL
10357#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x00000000
10358#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x00003c00L
10359#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0x0000000a
10360#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x00000070L
10361#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x00000004
10362#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x00000380L
10363#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x00000007
10364#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x0003c000L
10365#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0x0000000e
10366#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0x0000000fL
10367#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x00000000
10368#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003c00L
10369#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0x0000000a
10370#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L
10371#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x00000004
10372#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L
10373#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x00000007
10374#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003c000L
10375#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0x0000000e
10376#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000fL
10377#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x00000000
10378#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x00003c00L
10379#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0x0000000a
10380#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x00000070L
10381#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x00000004
10382#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x00000380L
10383#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x00000007
10384#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x0003c000L
10385#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0x0000000e
10386#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0x0000000fL
10387#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x00000000
10388#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x00003c00L
10389#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0x0000000a
10390#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x00000070L
10391#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x00000004
10392#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x00000380L
10393#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x00000007
10394#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x0003c000L
10395#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0x0000000e
10396#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0x0000000fL
10397#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x00000000
10398#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x00003c00L
10399#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0x0000000a
10400#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x00000070L
10401#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x00000004
10402#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x00000380L
10403#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x00000007
10404#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x0003c000L
10405#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0x0000000e
10406#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0x0000000fL
10407#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x00000000
10408#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x00003c00L
10409#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0x0000000a
10410#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x00000070L
10411#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x00000004
10412#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x00000380L
10413#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x00000007
10414#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x0003c000L
10415#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0x0000000e
10416#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0x0000000fL
10417#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x00000000
10418#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x00003c00L
10419#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0x0000000a
10420#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x00000070L
10421#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x00000004
10422#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x00000380L
10423#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x00000007
10424#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x0003c000L
10425#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0x0000000e
10426#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0x0000000fL
10427#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x00000000
10428#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x00003c00L
10429#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0x0000000a
10430#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x00000070L
10431#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x00000004
10432#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x00000380L
10433#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x00000007
10434#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x0003c000L
10435#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0x0000000e
10436#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0x0000000fL
10437#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x00000000
10438#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x00003c00L
10439#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0x0000000a
10440#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x00000070L
10441#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x00000004
10442#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x00000380L
10443#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x00000007
10444#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x0003c000L
10445#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0x0000000e
10446#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0x0000000fL
10447#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x00000000
10448#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x00003c00L
10449#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0x0000000a
10450#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x00000070L
10451#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x00000004
10452#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x00000380L
10453#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x00000007
10454#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x0003c000L
10455#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0x0000000e
10456#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0x0000000fL
10457#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x00000000
10458#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x00003c00L
10459#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0x0000000a
10460#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x00000070L
10461#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x00000004
10462#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x00000380L
10463#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x00000007
10464#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x0003c000L
10465#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0x0000000e
10466#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0x0000000fL
10467#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x00000000
10468#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x00003c00L
10469#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0x0000000a
10470#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x00000070L
10471#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x00000004
10472#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x00000380L
10473#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x00000007
10474#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x0003c000L
10475#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0x0000000e
10476#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0x0000000fL
10477#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x00000000
10478#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003c00L
10479#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0x0000000a
10480#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L
10481#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x00000004
10482#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L
10483#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x00000007
10484#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003c000L
10485#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0x0000000e
10486#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000fL
10487#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x00000000
10488#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x00003c00L
10489#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0x0000000a
10490#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x00000070L
10491#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x00000004
10492#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x00000380L
10493#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x00000007
10494#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x0003c000L
10495#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0x0000000e
10496#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0x0000000fL
10497#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x00000000
10498#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x00003c00L
10499#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0x0000000a
10500#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x00000070L
10501#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x00000004
10502#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x00000380L
10503#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x00000007
10504#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x0003c000L
10505#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0x0000000e
10506#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0x0000000fL
10507#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x00000000
10508#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x00003c00L
10509#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0x0000000a
10510#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x00000070L
10511#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x00000004
10512#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x00000380L
10513#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x00000007
10514#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x0003c000L
10515#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0x0000000e
10516#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0x0000000fL
10517#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x00000000
10518#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x00003c00L
10519#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0x0000000a
10520#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x00000070L
10521#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x00000004
10522#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x00000380L
10523#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x00000007
10524#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x0003c000L
10525#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0x0000000e
10526#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0x0000000fL
10527#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x00000000
10528#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x00003c00L
10529#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0x0000000a
10530#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x00000070L
10531#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x00000004
10532#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x00000380L
10533#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x00000007
10534#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x0003c000L
10535#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0x0000000e
10536#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0x0000000fL
10537#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x00000000
10538#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x00003c00L
10539#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0x0000000a
10540#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x00000070L
10541#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x00000004
10542#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x00000380L
10543#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x00000007
10544#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x0003c000L
10545#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0x0000000e
10546#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0x0000000fL
10547#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x00000000
10548#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x00003c00L
10549#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0x0000000a
10550#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x00000070L
10551#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x00000004
10552#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x00000380L
10553#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x00000007
10554#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x0003c000L
10555#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0x0000000e
10556#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0x0000000fL
10557#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x00000000
10558#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003c00L
10559#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0x0000000a
10560#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L
10561#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x00000004
10562#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L
10563#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x00000007
10564#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003c000L
10565#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0x0000000e
10566#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000fL
10567#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x00000000
10568#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003c00L
10569#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0x0000000a
10570#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L
10571#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x00000004
10572#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L
10573#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x00000007
10574#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003c000L
10575#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0x0000000e
10576#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000fL
10577#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x00000000
10578#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003c00L
10579#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0x0000000a
10580#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L
10581#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x00000004
10582#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L
10583#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x00000007
10584#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003c000L
10585#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0x0000000e
10586#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000fL
10587#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x00000000
10588#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003c00L
10589#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0x0000000a
10590#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L
10591#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x00000004
10592#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L
10593#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x00000007
10594#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003c000L
10595#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0x0000000e
10596#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000fL
10597#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x00000000
10598#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003c00L
10599#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0x0000000a
10600#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L
10601#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x00000004
10602#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L
10603#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x00000007
10604#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003c000L
10605#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0x0000000e
10606#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000fL
10607#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x00000000
10608#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x00003c00L
10609#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0x0000000a
10610#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x00000070L
10611#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x00000004
10612#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x00000380L
10613#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x00000007
10614#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x0003c000L
10615#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0x0000000e
10616#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0x0000000fL
10617#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x00000000
10618#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x00003c00L
10619#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0x0000000a
10620#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x00000070L
10621#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x00000004
10622#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x00000380L
10623#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x00000007
10624#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x0003c000L
10625#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0x0000000e
10626#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0x0000000fL
10627#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x00000000
10628#define MC_XPB_CLG_EXTRA__CMP0_MASK 0x000000ffL
10629#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x00000000
10630#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x01fe0000L
10631#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x00000011
10632#define MC_XPB_CLG_EXTRA__MSK0_MASK 0x0000ff00L
10633#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x00000008
10634#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0x000000ffL
10635#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x00000000
10636#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x01fe0000L
10637#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x00000011
10638#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0x0000ff00L
10639#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x00000008
10640#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x00010000L
10641#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x00000010
10642#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x02000000L
10643#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x00000019
10644#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x00010000L
10645#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x00000010
10646#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x02000000L
10647#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x00000019
10648#define MC_XPB_CLK_GAT__ENABLE_MASK 0x00040000L
10649#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x00000012
10650#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L
10651#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x00000013
10652#define MC_XPB_CLK_GAT__OFFDLY_MASK 0x00000fc0L
10653#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x00000006
10654#define MC_XPB_CLK_GAT__ONDLY_MASK 0x0000003fL
10655#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x00000000
10656#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x0003f000L
10657#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0x0000000c
10658#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000ffL
10659#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x00000000
10660#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L
10661#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x00000019
10662#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L
10663#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x0000001a
10664#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L
10665#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x00000017
10666#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L
10667#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x00000018
10668#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000ff00L
10669#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x00000008
10670#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000ffL
10671#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x00000000
10672#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L
10673#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x0000001e
10674#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L
10675#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x0000001f
10676#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007f0000L
10677#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x00000010
10678#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L
10679#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x0000001b
10680#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L
10681#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x0000001d
10682#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L
10683#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x00000012
10684#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L
10685#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x00000011
10686#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L
10687#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x00000010
10688#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L
10689#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0x0000000f
10690#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07f80000L
10691#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x00000013
10692#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000ffL
10693#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x00000000
10694#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007f00L
10695#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x00000008
10696#define MC_XPB_LB_ADDR__CMP0_MASK 0x000003ffL
10697#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x00000000
10698#define MC_XPB_LB_ADDR__CMP1_MASK 0x03f00000L
10699#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x00000014
10700#define MC_XPB_LB_ADDR__MASK0_MASK 0x000ffc00L
10701#define MC_XPB_LB_ADDR__MASK0__SHIFT 0x0000000a
10702#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000L
10703#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x0000001a
10704#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000ffffL
10705#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x00000000
10706#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0x000000ffL
10707#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x00000000
10708#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0x0000ff00L
10709#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x00000008
10710#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0x00ff0000L
10711#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x00000010
10712#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000L
10713#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x00000018
10714#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L
10715#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x0000001f
10716#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000L
10717#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x00000010
10718#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L
10719#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0x0000000e
10720#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000fL
10721#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x00000000
10722#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000f00L
10723#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x00000008
10724#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000f0L
10725#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x00000004
10726#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x00008000L
10727#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0x0000000f
10728#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L
10729#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0x0000000d
10730#define MC_XPB_P2P_BAR0__VALID_MASK 0x00001000L
10731#define MC_XPB_P2P_BAR0__VALID__SHIFT 0x0000000c
10732#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000L
10733#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x00000010
10734#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L
10735#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0x0000000e
10736#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000fL
10737#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x00000000
10738#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000f00L
10739#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x00000008
10740#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000f0L
10741#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x00000004
10742#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x00008000L
10743#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0x0000000f
10744#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L
10745#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0x0000000d
10746#define MC_XPB_P2P_BAR1__VALID_MASK 0x00001000L
10747#define MC_XPB_P2P_BAR1__VALID__SHIFT 0x0000000c
10748#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000L
10749#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x00000010
10750#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L
10751#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0x0000000e
10752#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000fL
10753#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x00000000
10754#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000f00L
10755#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x00000008
10756#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000f0L
10757#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x00000004
10758#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x00008000L
10759#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0x0000000f
10760#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L
10761#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0x0000000d
10762#define MC_XPB_P2P_BAR2__VALID_MASK 0x00001000L
10763#define MC_XPB_P2P_BAR2__VALID__SHIFT 0x0000000c
10764#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000L
10765#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x00000010
10766#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L
10767#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0x0000000e
10768#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000fL
10769#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x00000000
10770#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000f00L
10771#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x00000008
10772#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000f0L
10773#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x00000004
10774#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x00008000L
10775#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0x0000000f
10776#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L
10777#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0x0000000d
10778#define MC_XPB_P2P_BAR3__VALID_MASK 0x00001000L
10779#define MC_XPB_P2P_BAR3__VALID__SHIFT 0x0000000c
10780#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000L
10781#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x00000010
10782#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L
10783#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0x0000000e
10784#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000fL
10785#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x00000000
10786#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000f00L
10787#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x00000008
10788#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000f0L
10789#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x00000004
10790#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x00008000L
10791#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0x0000000f
10792#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L
10793#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0x0000000d
10794#define MC_XPB_P2P_BAR4__VALID_MASK 0x00001000L
10795#define MC_XPB_P2P_BAR4__VALID__SHIFT 0x0000000c
10796#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000L
10797#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x00000010
10798#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L
10799#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0x0000000e
10800#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000fL
10801#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x00000000
10802#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000f00L
10803#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x00000008
10804#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000f0L
10805#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x00000004
10806#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x00008000L
10807#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0x0000000f
10808#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L
10809#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0x0000000d
10810#define MC_XPB_P2P_BAR5__VALID_MASK 0x00001000L
10811#define MC_XPB_P2P_BAR5__VALID__SHIFT 0x0000000c
10812#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000L
10813#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x00000010
10814#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L
10815#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0x0000000e
10816#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000fL
10817#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x00000000
10818#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000f00L
10819#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x00000008
10820#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000f0L
10821#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x00000004
10822#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x00008000L
10823#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0x0000000f
10824#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L
10825#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0x0000000d
10826#define MC_XPB_P2P_BAR6__VALID_MASK 0x00001000L
10827#define MC_XPB_P2P_BAR6__VALID__SHIFT 0x0000000c
10828#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000L
10829#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x00000010
10830#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L
10831#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0x0000000e
10832#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000fL
10833#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x00000000
10834#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000f00L
10835#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x00000008
10836#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000f0L
10837#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x00000004
10838#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x00008000L
10839#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0x0000000f
10840#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L
10841#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0x0000000d
10842#define MC_XPB_P2P_BAR7__VALID_MASK 0x00001000L
10843#define MC_XPB_P2P_BAR7__VALID__SHIFT 0x0000000c
10844#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000fL
10845#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x00000000
10846#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L
10847#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0x0000000c
10848#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L
10849#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x00000008
10850#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L
10851#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0x0000000b
10852#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L
10853#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0x0000000a
10854#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L
10855#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x00000004
10856#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L
10857#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x00000007
10858#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L
10859#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x00000006
10860#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L
10861#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x00000009
10862#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0x00000f00L
10863#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x00000008
10864#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0x0000f000L
10865#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0x0000000c
10866#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0x000000ffL
10867#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x00000000
10868#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0fffff00L
10869#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x00000008
10870#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000ffL
10871#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x00000000
10872#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0fffff00L
10873#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x00000008
10874#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000ffL
10875#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x00000000
10876#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000L
10877#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x00000010
10878#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L
10879#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0x0000000e
10880#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000f00L
10881#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x00000008
10882#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L
10883#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0x0000000f
10884#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0x000000ffL
10885#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x00000000
10886#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L
10887#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0x0000000d
10888#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L
10889#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0x0000000c
10890#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL
10891#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002
10892#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L
10893#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001
10894#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L
10895#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x00000000
10896#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL
10897#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002
10898#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L
10899#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001
10900#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L
10901#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x00000000
10902#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL
10903#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002
10904#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L
10905#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001
10906#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L
10907#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x00000000
10908#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL
10909#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002
10910#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L
10911#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001
10912#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L
10913#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x00000000
10914#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x07fffffcL
10915#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x00000002
10916#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x00000002L
10917#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x00000001
10918#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L
10919#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x00000000
10920#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x07fffffcL
10921#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x00000002
10922#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x00000002L
10923#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x00000001
10924#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L
10925#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x00000000
10926#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x07fffffcL
10927#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x00000002
10928#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x00000002L
10929#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x00000001
10930#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L
10931#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x00000000
10932#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x07fffffcL
10933#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x00000002
10934#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x00000002L
10935#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x00000001
10936#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L
10937#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x00000000
10938#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x07fffffcL
10939#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x00000002
10940#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x00000002L
10941#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x00000001
10942#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L
10943#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x00000000
10944#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x07fffffcL
10945#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x00000002
10946#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x00000002L
10947#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x00000001
10948#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L
10949#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x00000000
10950#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003fL
10951#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x00000000
10952#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000fc0L
10953#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x00000006
10954#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003f000L
10955#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0x0000000c
10956#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L
10957#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x00000017
10958#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L
10959#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x00000000
10960#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000feL
10961#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000001
10962#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L
10963#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x00000015
10964#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L
10965#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0x0000000f
10966#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L
10967#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x00000011
10968#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L
10969#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x00000013
10970#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007f00L
10971#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000008
10972#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L
10973#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x00000016
10974#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L
10975#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x00000010
10976#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L
10977#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x00000012
10978#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L
10979#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x00000014
10980#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000L
10981#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x00000018
10982#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L
10983#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a
10984#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL
10985#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001
10986#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L
10987#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
10988#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018
10989#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014
10990#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
10991#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x00000000
10992#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
10993#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019
10994#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L
10995#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a
10996#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL
10997#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001
10998#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L
10999#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
11000#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018
11001#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014
11002#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
11003#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x00000000
11004#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
11005#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019
11006#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L
11007#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a
11008#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL
11009#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001
11010#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L
11011#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
11012#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018
11013#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014
11014#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
11015#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x00000000
11016#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
11017#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019
11018#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L
11019#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a
11020#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL
11021#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001
11022#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L
11023#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
11024#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018
11025#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014
11026#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L
11027#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x00000000
11028#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L
11029#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019
11030#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000L
11031#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x0000001a
11032#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000ffffeL
11033#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x00000001
11034#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00f00000L
11035#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L
11036#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x00000018
11037#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x00000014
11038#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L
11039#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x00000000
11040#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L
11041#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x00000019
11042#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000L
11043#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x0000001a
11044#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000ffffeL
11045#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x00000001
11046#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00f00000L
11047#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L
11048#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x00000018
11049#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x00000014
11050#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L
11051#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x00000000
11052#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L
11053#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x00000019
11054#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000L
11055#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x0000001a
11056#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000ffffeL
11057#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x00000001
11058#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00f00000L
11059#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L
11060#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x00000018
11061#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x00000014
11062#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L
11063#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x00000000
11064#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L
11065#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x00000019
11066#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000L
11067#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x0000001a
11068#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000ffffeL
11069#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x00000001
11070#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00f00000L
11071#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L
11072#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x00000018
11073#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x00000014
11074#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L
11075#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x00000000
11076#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L
11077#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x00000019
11078#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000L
11079#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x0000001a
11080#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000ffffeL
11081#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x00000001
11082#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00f00000L
11083#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L
11084#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x00000018
11085#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x00000014
11086#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L
11087#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x00000000
11088#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L
11089#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x00000019
11090#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000L
11091#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x0000001a
11092#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000ffffeL
11093#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x00000001
11094#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00f00000L
11095#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L
11096#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x00000018
11097#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x00000014
11098#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L
11099#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x00000000
11100#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L
11101#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x00000019
11102#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL
11103#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000
11104#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL
11105#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000
11106#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL
11107#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000
11108#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL
11109#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000
11110#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x01ffffffL
11111#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x00000000
11112#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x01ffffffL
11113#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x00000000
11114#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x01ffffffL
11115#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x00000000
11116#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x01ffffffL
11117#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x00000000
11118#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x01ffffffL
11119#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x00000000
11120#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x01ffffffL
11121#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x00000000
11122#define MC_XPB_STICKY__BITS_MASK 0xffffffffL
11123#define MC_XPB_STICKY__BITS__SHIFT 0x00000000
11124#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffffL
11125#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x00000000
11126#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L
11127#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x00000013
11128#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L
11129#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0x0000000a
11130#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L
11131#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x00000010
11132#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L
11133#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0x0000000f
11134#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L
11135#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0x0000000d
11136#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L
11137#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0x0000000c
11138#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L
11139#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0x0000000b
11140#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L
11141#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x00000011
11142#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L
11143#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x00000012
11144#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L
11145#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0x0000000e
11146#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L
11147#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x00000001
11148#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L
11149#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x00000008
11150#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L
11151#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x00000004
11152#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L
11153#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x00000006
11154#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L
11155#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x00000003
11156#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L
11157#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x00000002
11158#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L
11159#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x00000007
11160#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L
11161#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x00000005
11162#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L
11163#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x00000009
11164#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L
11165#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x00000000
11166#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x0000003fL
11167#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x00000000
11168#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0x00000fc0L
11169#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x00000006
11170#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x0003f000L
11171#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0x0000000c
11172#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x0000003fL
11173#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x00000000
11174#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0x00000fc0L
11175#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x00000006
11176#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x0003f000L
11177#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0x0000000c
11178#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x00030000L
11179#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x00000010
11180#define MC_XPB_WCB_CFG__SID_MAX_MASK 0x000c0000L
11181#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x00000012
11182#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0x0000ffffL
11183#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x00000000
11184#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0x0000ffffL
11185#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x00000000
11186#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007f0000L
11187#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000010
11188#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000L
11189#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000017
11190#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL
11191#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002
11192#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L
11193#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001
11194#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L
11195#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x00000000
11196#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL
11197#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002
11198#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L
11199#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001
11200#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L
11201#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x00000000
11202#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL
11203#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002
11204#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L
11205#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001
11206#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L
11207#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x00000000
11208#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL
11209#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002
11210#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L
11211#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001
11212#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L
11213#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x00000000
11214#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L
11215#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a
11216#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL
11217#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001
11218#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L
11219#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
11220#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018
11221#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014
11222#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L
11223#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x00000000
11224#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
11225#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019
11226#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L
11227#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a
11228#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL
11229#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001
11230#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L
11231#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
11232#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018
11233#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014
11234#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L
11235#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x00000000
11236#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
11237#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019
11238#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L
11239#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a
11240#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL
11241#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001
11242#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L
11243#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
11244#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018
11245#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014
11246#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L
11247#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x00000000
11248#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
11249#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019
11250#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L
11251#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a
11252#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL
11253#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001
11254#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L
11255#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
11256#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018
11257#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014
11258#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L
11259#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x00000000
11260#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L
11261#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019
11262#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL
11263#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000
11264#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL
11265#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000
11266#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL
11267#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000
11268#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL
11269#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000
11270#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8L
11271#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x00000003
11272#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L
11273#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000
11274#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x00040000L
11275#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x00000012
11276#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L
11277#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013
11278#define MPLL_AD_STATUS__OINT_RESET_MASK 0x00020000L
11279#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x00000011
11280#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L
11281#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004
11282#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L
11283#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007
11284#define MPLL_AD_STATUS__VCTRLADC_MASK 0x00000007L
11285#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x00000000
11286#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x00600000L
11287#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x00000015
11288#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x00100000L
11289#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x00000014
11290#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x00020000L
11291#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x00000011
11292#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000L
11293#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x0000001f
11294#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0x000000ffL
11295#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x00000000
11296#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x00010000L
11297#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x00000010
11298#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x00004000L
11299#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0x0000000e
11300#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x00000800L
11301#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0x0000000b
11302#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x00000100L
11303#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x00000008
11304#define MPLL_CNTL_MODE__QDR_MASK 0x00002000L
11305#define MPLL_CNTL_MODE__QDR__SHIFT 0x0000000d
11306#define MPLL_CNTL_MODE__SPARE_1_MASK 0x00001000L
11307#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0x0000000c
11308#define MPLL_CNTL_MODE__SPARE_2_MASK 0x00800000L
11309#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x00000017
11310#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000L
11311#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x0000001c
11312#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x04000000L
11313#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x0000001a
11314#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x03000000L
11315#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x00000018
11316#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x08000000L
11317#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x0000001b
11318#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x00001000L
11319#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0x0000000c
11320#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x00002000L
11321#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0x0000000d
11322#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x00004000L
11323#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0x0000000e
11324#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x00010000L
11325#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x00000010
11326#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x00020000L
11327#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x00000011
11328#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x00040000L
11329#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x00000012
11330#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x00100000L
11331#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x00000014
11332#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x00200000L
11333#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x00000015
11334#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x00400000L
11335#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x00000016
11336#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x01000000L
11337#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x00000018
11338#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x02000000L
11339#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x00000019
11340#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x04000000L
11341#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x0000001a
11342#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000L
11343#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x0000001c
11344#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000L
11345#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x0000001d
11346#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000L
11347#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x0000001e
11348#define MPLL_CONTROL__GDDR_PWRON_MASK 0x00000001L
11349#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x00000000
11350#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x00000004L
11351#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x00000002
11352#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x00000002L
11353#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x00000001
11354#define MPLL_CONTROL__SPARE_AD_0_MASK 0x00008000L
11355#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0x0000000f
11356#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x00080000L
11357#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x00000013
11358#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x00800000L
11359#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x00000017
11360#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x08000000L
11361#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x0000001b
11362#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000L
11363#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x0000001f
11364#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x00040000L
11365#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x00000012
11366#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L
11367#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013
11368#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x00020000L
11369#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x00000011
11370#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L
11371#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004
11372#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L
11373#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007
11374#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x00000007L
11375#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x00000000
11376#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x00040000L
11377#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x00000012
11378#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L
11379#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013
11380#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x00020000L
11381#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x00000011
11382#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L
11383#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004
11384#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L
11385#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007
11386#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x00000007L
11387#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x00000000
11388#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x00040000L
11389#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x00000012
11390#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L
11391#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013
11392#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x00020000L
11393#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x00000011
11394#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L
11395#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004
11396#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L
11397#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007
11398#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x00000007L
11399#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x00000000
11400#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x00040000L
11401#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x00000012
11402#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L
11403#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013
11404#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x00020000L
11405#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x00000011
11406#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L
11407#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004
11408#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L
11409#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007
11410#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x00000007L
11411#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x00000000
11412#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x00000008L
11413#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x00000003
11414#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0L
11415#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x00000005
11416#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L
11417#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000
11418#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x00000010L
11419#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x00000004
11420#define MPLL_FUNC_CNTL_1__CLKF_MASK 0x0fff0000L
11421#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0x0000fff0L
11422#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x00000004
11423#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x00000010
11424#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0x0000000cL
11425#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x00000002
11426#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000L
11427#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x0000001c
11428#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x00000003L
11429#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x00000000
11430#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0x000e0000L
11431#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x00000011
11432#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000L
11433#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x0000001b
11434#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x07f00000L
11435#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x00000014
11436#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x00000080L
11437#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x00000007
11438#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x00003000L
11439#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0x0000000c
11440#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x00000004L
11441#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x00000002
11442#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0x00000c00L
11443#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0x0000000a
11444#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x00000008L
11445#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x00000003
11446#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x00000010L
11447#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x00000004
11448#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x00000040L
11449#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x00000006
11450#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x00000020L
11451#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000005
11452#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x00000200L
11453#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x00000009
11454#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x00000100L
11455#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x00000008
11456#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x00000002L
11457#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x00000001
11458#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x00000001L
11459#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x00000000
11460#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0x00000f00L
11461#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x00000008
11462#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0x000f0000L
11463#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x00000010
11464#define MPLL_FUNC_CNTL__BWCTRL_MASK 0x0ff00000L
11465#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x00000014
11466#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000L
11467#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x0000001e
11468#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x00000020L
11469#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x00000005
11470#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0x0000000fL
11471#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x00000000
11472#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0x000000f0L
11473#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x00000004
11474#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0x00000f00L
11475#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x00000008
11476#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0x0000f000L
11477#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0x0000000c
11478#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0x000f0000L
11479#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x00000010
11480#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0x00f00000L
11481#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x00000014
11482#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0x0f000000L
11483#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x00000018
11484#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000L
11485#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x0000001c
11486#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0x00000f00L
11487#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x00000008
11488#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0x0000f000L
11489#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0x0000000c
11490#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0x000f0000L
11491#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x00000010
11492#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0x00f00000L
11493#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x00000014
11494#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0x0f000000L
11495#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x00000018
11496#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000L
11497#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x0000001c
11498#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0x0000000fL
11499#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x00000000
11500#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0x000000f0L
11501#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x00000004
11502#define MPLL_SS1__CLKV_MASK 0x03ffffffL
11503#define MPLL_SS1__CLKV__SHIFT 0x00000000
11504#define MPLL_SS1__SPARE_MASK 0xfc000000L
11505#define MPLL_SS1__SPARE__SHIFT 0x0000001a
11506#define MPLL_SS2__CLKS_MASK 0x00000fffL
11507#define MPLL_SS2__CLKS__SHIFT 0x00000000
11508#define MPLL_SS2__SPARE_MASK 0xfffff000L
11509#define MPLL_SS2__SPARE__SHIFT 0x0000000c
11510#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0x0000ffffL
11511#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x00000000
11512#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000L
11513#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x00000010
11514#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L
11515#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003
11516#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
11517#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000
11518#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L
11519#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001
11520#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L
11521#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002
11522#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L
11523#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004
11524#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
11525#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007
11526#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L
11527#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006
11528#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
11529#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000
11530#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L
11531#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018
11532#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
11533#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001
11534#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
11535#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a
11536#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
11537#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009
11538#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L
11539#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b
11540#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
11541#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016
11542#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
11543#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015
11544#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L
11545#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017
11546#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
11547#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004
11548#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
11549#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003
11550#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
11551#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010
11552#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
11553#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f
11554#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L
11555#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011
11556#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
11557#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d
11558#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
11559#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c
11560#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L
11561#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e
11562#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L
11563#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013
11564#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L
11565#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012
11566#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L
11567#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014
11568#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11569#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11570#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11571#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11572#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11573#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11574#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL
11575#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000
11576#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL
11577#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000
11578#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L
11579#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c
11580#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L
11581#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018
11582#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL
11583#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000
11584#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L
11585#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019
11586#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11587#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11588#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11589#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11590#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11591#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11592#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11593#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11594#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11595#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11596#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11597#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11598#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L
11599#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003
11600#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
11601#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000
11602#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L
11603#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001
11604#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L
11605#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002
11606#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L
11607#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004
11608#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
11609#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007
11610#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L
11611#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006
11612#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
11613#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000
11614#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L
11615#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018
11616#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
11617#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001
11618#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
11619#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a
11620#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
11621#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009
11622#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L
11623#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b
11624#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
11625#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016
11626#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
11627#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015
11628#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L
11629#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017
11630#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
11631#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004
11632#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L
11633#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003
11634#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
11635#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010
11636#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
11637#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f
11638#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L
11639#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011
11640#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L
11641#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d
11642#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L
11643#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c
11644#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L
11645#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e
11646#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L
11647#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013
11648#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L
11649#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012
11650#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L
11651#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014
11652#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11653#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11654#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11655#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11656#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11657#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11658#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL
11659#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000
11660#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL
11661#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000
11662#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L
11663#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c
11664#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L
11665#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018
11666#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL
11667#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000
11668#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L
11669#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019
11670#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11671#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11672#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11673#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11674#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11675#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11676#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11677#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11678#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11679#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11680#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11681#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11682#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11683#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11684#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL
11685#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000
11686#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
11687#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x00000000
11688#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
11689#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0x0000000a
11690#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
11691#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0x0000000b
11692#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
11693#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0x0000000c
11694#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
11695#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0x0000000d
11696#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
11697#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0x0000000e
11698#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
11699#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0x0000000f
11700#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
11701#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x00000001
11702#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
11703#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x00000002
11704#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
11705#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x00000003
11706#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
11707#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x00000004
11708#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
11709#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x00000005
11710#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
11711#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x00000006
11712#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
11713#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x00000007
11714#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
11715#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x00000008
11716#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
11717#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x00000009
11718#define VM_DEBUG__FLAGS_MASK 0xffffffffL
11719#define VM_DEBUG__FLAGS__SHIFT 0x00000000
11720#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0x0fffffffL
11721#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x00000000
11722#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
11723#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x00000001
11724#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0x0000000cL
11725#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x00000002
11726#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
11727#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x00000000
11728#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x000001ffL
11729#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x0003fe00L
11730#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x00000009
11731#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x00000000
11732#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x00000001L
11733#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x00000000
11734#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x00000400L
11735#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0x0000000a
11736#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x00000800L
11737#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0x0000000b
11738#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x00001000L
11739#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0x0000000c
11740#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x00002000L
11741#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0x0000000d
11742#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x00004000L
11743#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0x0000000e
11744#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x00008000L
11745#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0x0000000f
11746#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x00000002L
11747#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x00000001
11748#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x00000004L
11749#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x00000002
11750#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x00000008L
11751#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x00000003
11752#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x00000010L
11753#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x00000004
11754#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x00000020L
11755#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x00000005
11756#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x00000040L
11757#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x00000006
11758#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x00000080L
11759#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x00000007
11760#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x00000100L
11761#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x00000008
11762#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x00000200L
11763#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x00000009
11764#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x00000001L
11765#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x00000000
11766#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x00000400L
11767#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0x0000000a
11768#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x00000800L
11769#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0x0000000b
11770#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x00001000L
11771#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0x0000000c
11772#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x00002000L
11773#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0x0000000d
11774#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x00004000L
11775#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0x0000000e
11776#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x00008000L
11777#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0x0000000f
11778#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x00000002L
11779#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x00000001
11780#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x00000004L
11781#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x00000002
11782#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x00000008L
11783#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x00000003
11784#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x00000010L
11785#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x00000004
11786#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x00000020L
11787#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x00000005
11788#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x00000040L
11789#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x00000006
11790#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x00000080L
11791#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x00000007
11792#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x00000100L
11793#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x00000008
11794#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x00000200L
11795#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x00000009
11796#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0x0fffffffL
11797#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x00000000
11798#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x000000ffL
11799#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x00000000
11800#define VM_L2_CG__ENABLE_MASK 0x00040000L
11801#define VM_L2_CG__ENABLE__SHIFT 0x00000012
11802#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x00080000L
11803#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x00000013
11804#define VM_L2_CG__OFFDLY_MASK 0x00000fc0L
11805#define VM_L2_CG__OFFDLY__SHIFT 0x00000006
11806#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
11807#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x00000016
11808#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
11809#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000015
11810#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
11811#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x00000000
11812#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0c000000L
11813#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x0000001a
11814#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
11815#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x00000001
11816#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L
11817#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x00000017
11818#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003fL
11819#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x00000000
11820#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L
11821#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015
11822#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
11823#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x0000001c
11824#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
11825#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x00000014
11826#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L
11827#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x00000018
11828#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
11829#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x0000001d
11830#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000f8000L
11831#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x0000000f
11832#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L
11833#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006
11834#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001f00L
11835#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x00000008
11836#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
11837#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x00000013
11838#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
11839#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f
11840#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
11841#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000
11842#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
11843#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x00000001
11844#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
11845#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a
11846#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
11847#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000009
11848#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03e00000L
11849#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x00000015
11850#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0c000000L
11851#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001a
11852#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L
11853#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001c
11854#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
11855#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x00000004
11856#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000cL
11857#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x00000002
11858#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
11859#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0x0000000c
11860#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
11861#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x00000008
11862#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
11863#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x00000012
11864#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11865#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11866#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11867#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11868#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0x0fffffffL
11869#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x00000000
11870#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001fffeL
11871#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x00000001
11872#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
11873#define VM_L2_STATUS__L2_BUSY__SHIFT 0x00000000
11874#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11875#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11876#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11877#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11878#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11879#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11880#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11881#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11882#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11883#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11884#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11885#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11886#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11887#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11888#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL
11889#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000
11890#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x00000008L
11891#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003
11892#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L
11893#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002
11894
11895#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h
new file mode 100644
index 000000000000..edc8a793a95d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h
@@ -0,0 +1,275 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef OSS_1_0_D_H
24#define OSS_1_0_D_H
25
26#define ixCLIENT0_BM 0x0220
27#define ixCLIENT0_CD0 0x0210
28#define ixCLIENT0_CD1 0x0214
29#define ixCLIENT0_CD2 0x0218
30#define ixCLIENT0_CD3 0x021C
31#define ixCLIENT0_CK0 0x0200
32#define ixCLIENT0_CK1 0x0204
33#define ixCLIENT0_CK2 0x0208
34#define ixCLIENT0_CK3 0x020C
35#define ixCLIENT0_K0 0x01F0
36#define ixCLIENT0_K1 0x01F4
37#define ixCLIENT0_K2 0x01F8
38#define ixCLIENT0_K3 0x01FC
39#define ixCLIENT0_OFFSET 0x0224
40#define ixCLIENT0_OFFSET_HI 0x0290
41#define ixCLIENT0_STATUS 0x0228
42#define ixCLIENT1_BM 0x025C
43#define ixCLIENT1_CD0 0x024C
44#define ixCLIENT1_CD1 0x0250
45#define ixCLIENT1_CD2 0x0254
46#define ixCLIENT1_CD3 0x0258
47#define ixCLIENT1_CK0 0x023C
48#define ixCLIENT1_CK1 0x0240
49#define ixCLIENT1_CK2 0x0244
50#define ixCLIENT1_CK3 0x0248
51#define ixCLIENT1_K0 0x022C
52#define ixCLIENT1_K1 0x0230
53#define ixCLIENT1_K2 0x0234
54#define ixCLIENT1_K3 0x0238
55#define ixCLIENT1_OFFSET 0x0260
56#define ixCLIENT1_OFFSET_HI 0x0294
57#define ixCLIENT1_PORT_STATUS 0x0264
58#define ixCLIENT2_BM 0x01E4
59#define ixCLIENT2_CD0 0x01D4
60#define ixCLIENT2_CD1 0x01D8
61#define ixCLIENT2_CD2 0x01DC
62#define ixCLIENT2_CD3 0x01E0
63#define ixCLIENT2_CK0 0x01C4
64#define ixCLIENT2_CK1 0x01C8
65#define ixCLIENT2_CK2 0x01CC
66#define ixCLIENT2_CK3 0x01D0
67#define ixCLIENT2_K0 0x01B4
68#define ixCLIENT2_K1 0x01B8
69#define ixCLIENT2_K2 0x01BC
70#define ixCLIENT2_K3 0x01C0
71#define ixCLIENT2_OFFSET 0x01E8
72#define ixCLIENT2_OFFSET_HI 0x0298
73#define ixCLIENT2_STATUS 0x01EC
74#define ixCLIENT3_BM 0x02D4
75#define ixCLIENT3_CD0 0x02C4
76#define ixCLIENT3_CD1 0x02C8
77#define ixCLIENT3_CD2 0x02CC
78#define ixCLIENT3_CD3 0x02D0
79#define ixCLIENT3_CK0 0x02B4
80#define ixCLIENT3_CK1 0x02B8
81#define ixCLIENT3_CK2 0x02BC
82#define ixCLIENT3_CK3 0x02C0
83#define ixCLIENT3_K0 0x02A4
84#define ixCLIENT3_K1 0x02A8
85#define ixCLIENT3_K2 0x02AC
86#define ixCLIENT3_K3 0x02B0
87#define ixCLIENT3_OFFSET 0x02D8
88#define ixCLIENT3_OFFSET_HI 0x02A0
89#define ixCLIENT3_STATUS 0x02DC
90#define ixDH_TEST 0x0000
91#define ixEXP0 0x0034
92#define ixEXP1 0x0038
93#define ixEXP2 0x003C
94#define ixEXP3 0x0040
95#define ixEXP4 0x0044
96#define ixEXP5 0x0048
97#define ixEXP6 0x004C
98#define ixEXP7 0x0050
99#define ixHFS_SEED0 0x0278
100#define ixHFS_SEED1 0x027C
101#define ixHFS_SEED2 0x0280
102#define ixHFS_SEED3 0x0284
103#define ixKEFUSE0 0x0268
104#define ixKEFUSE1 0x026C
105#define ixKEFUSE2 0x0270
106#define ixKEFUSE3 0x0274
107#define ixKHFS0 0x0004
108#define ixKHFS1 0x0008
109#define ixKHFS2 0x000C
110#define ixKHFS3 0x0010
111#define ixKSESSION0 0x0014
112#define ixKSESSION1 0x0018
113#define ixKSESSION2 0x001C
114#define ixKSESSION3 0x0020
115#define ixKSIG0 0x0024
116#define ixKSIG1 0x0028
117#define ixKSIG2 0x002C
118#define ixKSIG3 0x0030
119#define ixLX0 0x0054
120#define ixLX1 0x0058
121#define ixLX2 0x005C
122#define ixLX3 0x0060
123#define ixRINGOSC_MASK 0x0288
124#define ixSPU_PORT_STATUS 0x029C
125#define mmCC_DRM_ID_STRAPS 0x1559
126#define mmCC_SYS_RB_BACKEND_DISABLE 0x03A0
127#define mmCC_SYS_RB_REDUNDANCY 0x039F
128#define mmCGTT_DRM_CLK_CTRL0 0x1579
129#define mmCP_CONFIG 0x0F92
130#define mmDC_TEST_DEBUG_DATA 0x157D
131#define mmDC_TEST_DEBUG_INDEX 0x157C
132#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x03A1
133#define mmHDP_ADDR_CONFIG 0x0BD2
134#define mmHDP_DEBUG0 0x0BCC
135#define mmHDP_DEBUG1 0x0BCD
136#define mmHDP_HOST_PATH_CNTL 0x0B00
137#define mmHDP_LAST_SURFACE_HIT 0x0BCE
138#define mmHDP_MEMIO_ADDR 0x0BF7
139#define mmHDP_MEMIO_CNTL 0x0BF6
140#define mmHDP_MEMIO_RD_DATA 0x0BFA
141#define mmHDP_MEMIO_STATUS 0x0BF8
142#define mmHDP_MEMIO_WR_DATA 0x0BF9
143#define mmHDP_MEM_POWER_LS 0x0BD4
144#define mmHDP_MISC_CNTL 0x0BD3
145#define mmHDP_NONSURFACE_BASE 0x0B01
146#define mmHDP_NONSURFACE_INFO 0x0B02
147#define mmHDP_NONSURFACE_PREFETCH 0x0BD5
148#define mmHDP_NONSURFACE_SIZE 0x0B03
149#define mmHDP_NONSURF_FLAGS 0x0BC9
150#define mmHDP_NONSURF_FLAGS_CLR 0x0BCA
151#define mmHDP_OUTSTANDING_REQ 0x0BD1
152#define mmHDP_SC_MULTI_CHIP_CNTL 0x0BD0
153#define mmHDP_SW_SEMAPHORE 0x0BCB
154#define mmHDP_TILING_CONFIG 0x0BCF
155#define mmHDP_XDP_BARS_ADDR_39_36 0x0C44
156#define mmHDP_XDP_BUSY_STS 0x0C3E
157#define mmHDP_XDP_CGTT_BLK_CTRL 0x0C33
158#define mmHDP_XDP_CHKN 0x0C40
159#define mmHDP_XDP_D2H_BAR_UPDATE 0x0C02
160#define mmHDP_XDP_D2H_FLUSH 0x0C01
161#define mmHDP_XDP_D2H_RSVD_10 0x0C0A
162#define mmHDP_XDP_D2H_RSVD_11 0x0C0B
163#define mmHDP_XDP_D2H_RSVD_12 0x0C0C
164#define mmHDP_XDP_D2H_RSVD_13 0x0C0D
165#define mmHDP_XDP_D2H_RSVD_14 0x0C0E
166#define mmHDP_XDP_D2H_RSVD_15 0x0C0F
167#define mmHDP_XDP_D2H_RSVD_16 0x0C10
168#define mmHDP_XDP_D2H_RSVD_17 0x0C11
169#define mmHDP_XDP_D2H_RSVD_18 0x0C12
170#define mmHDP_XDP_D2H_RSVD_19 0x0C13
171#define mmHDP_XDP_D2H_RSVD_20 0x0C14
172#define mmHDP_XDP_D2H_RSVD_21 0x0C15
173#define mmHDP_XDP_D2H_RSVD_22 0x0C16
174#define mmHDP_XDP_D2H_RSVD_23 0x0C17
175#define mmHDP_XDP_D2H_RSVD_24 0x0C18
176#define mmHDP_XDP_D2H_RSVD_25 0x0C19
177#define mmHDP_XDP_D2H_RSVD_26 0x0C1A
178#define mmHDP_XDP_D2H_RSVD_27 0x0C1B
179#define mmHDP_XDP_D2H_RSVD_28 0x0C1C
180#define mmHDP_XDP_D2H_RSVD_29 0x0C1D
181#define mmHDP_XDP_D2H_RSVD_30 0x0C1E
182#define mmHDP_XDP_D2H_RSVD_3 0x0C03
183#define mmHDP_XDP_D2H_RSVD_31 0x0C1F
184#define mmHDP_XDP_D2H_RSVD_32 0x0C20
185#define mmHDP_XDP_D2H_RSVD_33 0x0C21
186#define mmHDP_XDP_D2H_RSVD_34 0x0C22
187#define mmHDP_XDP_D2H_RSVD_4 0x0C04
188#define mmHDP_XDP_D2H_RSVD_5 0x0C05
189#define mmHDP_XDP_D2H_RSVD_6 0x0C06
190#define mmHDP_XDP_D2H_RSVD_7 0x0C07
191#define mmHDP_XDP_D2H_RSVD_8 0x0C08
192#define mmHDP_XDP_D2H_RSVD_9 0x0C09
193#define mmHDP_XDP_DBG_ADDR 0x0C41
194#define mmHDP_XDP_DBG_DATA 0x0C42
195#define mmHDP_XDP_DBG_MASK 0x0C43
196#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0C00
197#define mmHDP_XDP_DIRECT2HDP_LAST 0x0C23
198#define mmHDP_XDP_FLUSH_ARMED_STS 0x0C3C
199#define mmHDP_XDP_FLUSH_CNTR0_STS 0x0C3D
200#define mmHDP_XDP_HDP_IPH_CFG 0x0C31
201#define mmHDP_XDP_HDP_MBX_MC_CFG 0x0C2D
202#define mmHDP_XDP_HDP_MC_CFG 0x0C2E
203#define mmHDP_XDP_HST_CFG 0x0C2F
204#define mmHDP_XDP_P2P_BAR0 0x0C34
205#define mmHDP_XDP_P2P_BAR1 0x0C35
206#define mmHDP_XDP_P2P_BAR2 0x0C36
207#define mmHDP_XDP_P2P_BAR3 0x0C37
208#define mmHDP_XDP_P2P_BAR4 0x0C38
209#define mmHDP_XDP_P2P_BAR5 0x0C39
210#define mmHDP_XDP_P2P_BAR6 0x0C3A
211#define mmHDP_XDP_P2P_BAR7 0x0C3B
212#define mmHDP_XDP_P2P_BAR_CFG 0x0C24
213#define mmHDP_XDP_P2P_MBX_ADDR0 0x0C26
214#define mmHDP_XDP_P2P_MBX_ADDR1 0x0C27
215#define mmHDP_XDP_P2P_MBX_ADDR2 0x0C28
216#define mmHDP_XDP_P2P_MBX_ADDR3 0x0C29
217#define mmHDP_XDP_P2P_MBX_ADDR4 0x0C2A
218#define mmHDP_XDP_P2P_MBX_ADDR5 0x0C2B
219#define mmHDP_XDP_P2P_MBX_ADDR6 0x0C2C
220#define mmHDP_XDP_P2P_MBX_OFFSET 0x0C25
221#define mmHDP_XDP_SID_CFG 0x0C30
222#define mmHDP_XDP_SRBM_CFG 0x0C32
223#define mmHDP_XDP_STICKY 0x0C3F
224#define mmIH_ADVFAULT_CNTL 0x0F8C
225#define mmIH_CNTL 0x0F86
226#define mmIH_LEVEL_STATUS 0x0F87
227#define mmIH_PERFCOUNTER0_RESULT 0x0F8A
228#define mmIH_PERFCOUNTER1_RESULT 0x0F8B
229#define mmIH_PERFMON_CNTL 0x0F89
230#define mmIH_RB_BASE 0x0F81
231#define mmIH_RB_CNTL 0x0F80
232#define mmIH_RB_RPTR 0x0F82
233#define mmIH_RB_WPTR 0x0F83
234#define mmIH_RB_WPTR_ADDR_HI 0x0F84
235#define mmIH_RB_WPTR_ADDR_LO 0x0F85
236#define mmIH_STATUS 0x0F88
237#define mmSEM_MAILBOX 0x0F9B
238#define mmSEM_MAILBOX_CLIENTCONFIG 0x0F9A
239#define mmSEM_MAILBOX_CONTROL 0x0F9C
240#define mmSEM_MCIF_CONFIG 0x0F90
241#define mmSRBM_CAM_DATA 0x0397
242#define mmSRBM_CAM_INDEX 0x0396
243#define mmSRBM_CHIP_REVISION 0x039B
244#define mmSRBM_CNTL 0x0390
245#define mmSRBM_DEBUG 0x03A4
246#define mmSRBM_DEBUG_CNTL 0x0399
247#define mmSRBM_DEBUG_DATA 0x039A
248#define mmSRBM_DEBUG_SNAPSHOT 0x03A5
249#define mmSRBM_GFX_CNTL 0x0391
250#define mmSRBM_INT_ACK 0x03AA
251#define mmSRBM_INT_CNTL 0x03A8
252#define mmSRBM_INT_STATUS 0x03A9
253#define mmSRBM_MC_CLKEN_CNTL 0x03B3
254#define mmSRBM_PERFCOUNTER0_HI 0x0704
255#define mmSRBM_PERFCOUNTER0_LO 0x0703
256#define mmSRBM_PERFCOUNTER0_SELECT 0x0701
257#define mmSRBM_PERFCOUNTER1_HI 0x0706
258#define mmSRBM_PERFCOUNTER1_LO 0x0705
259#define mmSRBM_PERFCOUNTER1_SELECT 0x0702
260#define mmSRBM_PERFMON_CNTL 0x0700
261#define mmSRBM_READ_ERROR 0x03A6
262#define mmSRBM_SOFT_RESET 0x0398
263#define mmSRBM_STATUS 0x0394
264#define mmSRBM_STATUS2 0x0393
265#define mmSRBM_SYS_CLKEN_CNTL 0x03B4
266#define mmSRBM_UVD_CLKEN_CNTL 0x03B6
267#define mmSRBM_VCE_CLKEN_CNTL 0x03B5
268#define mmUVD_CONFIG 0x0F98
269#define mmVCE_CONFIG 0x0F94
270#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x03F8
271
272/* from the old sid.h */
273#define mmDMA_TILING_CONFIG 0x342E
274
275#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h
new file mode 100644
index 000000000000..1c540fe136cb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h
@@ -0,0 +1,1079 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef OSS_1_0_SH_MASK_H
24#define OSS_1_0_SH_MASK_H
25
26#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
36#define CLIENT0_BM__RESERVED_MASK 0xffffffffL
37#define CLIENT0_BM__RESERVED__SHIFT 0x00000000
38#define CLIENT0_CD0__RESERVED_MASK 0xffffffffL
39#define CLIENT0_CD0__RESERVED__SHIFT 0x00000000
40#define CLIENT0_CD1__RESERVED_MASK 0xffffffffL
41#define CLIENT0_CD1__RESERVED__SHIFT 0x00000000
42#define CLIENT0_CD2__RESERVED_MASK 0xffffffffL
43#define CLIENT0_CD2__RESERVED__SHIFT 0x00000000
44#define CLIENT0_CD3__RESERVED_MASK 0xffffffffL
45#define CLIENT0_CD3__RESERVED__SHIFT 0x00000000
46#define CLIENT0_CK0__RESERVED_MASK 0xffffffffL
47#define CLIENT0_CK0__RESERVED__SHIFT 0x00000000
48#define CLIENT0_CK1__RESERVED_MASK 0xffffffffL
49#define CLIENT0_CK1__RESERVED__SHIFT 0x00000000
50#define CLIENT0_CK2__RESERVED_MASK 0xffffffffL
51#define CLIENT0_CK2__RESERVED__SHIFT 0x00000000
52#define CLIENT0_CK3__RESERVED_MASK 0xffffffffL
53#define CLIENT0_CK3__RESERVED__SHIFT 0x00000000
54#define CLIENT0_K0__RESERVED_MASK 0xffffffffL
55#define CLIENT0_K0__RESERVED__SHIFT 0x00000000
56#define CLIENT0_K1__RESERVED_MASK 0xffffffffL
57#define CLIENT0_K1__RESERVED__SHIFT 0x00000000
58#define CLIENT0_K2__RESERVED_MASK 0xffffffffL
59#define CLIENT0_K2__RESERVED__SHIFT 0x00000000
60#define CLIENT0_K3__RESERVED_MASK 0xffffffffL
61#define CLIENT0_K3__RESERVED__SHIFT 0x00000000
62#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL
63#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000
64#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL
65#define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000
66#define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL
67#define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000
68#define CLIENT1_BM__RESERVED_MASK 0xffffffffL
69#define CLIENT1_BM__RESERVED__SHIFT 0x00000000
70#define CLIENT1_CD0__RESERVED_MASK 0xffffffffL
71#define CLIENT1_CD0__RESERVED__SHIFT 0x00000000
72#define CLIENT1_CD1__RESERVED_MASK 0xffffffffL
73#define CLIENT1_CD1__RESERVED__SHIFT 0x00000000
74#define CLIENT1_CD2__RESERVED_MASK 0xffffffffL
75#define CLIENT1_CD2__RESERVED__SHIFT 0x00000000
76#define CLIENT1_CD3__RESERVED_MASK 0xffffffffL
77#define CLIENT1_CD3__RESERVED__SHIFT 0x00000000
78#define CLIENT1_CK0__RESERVED_MASK 0xffffffffL
79#define CLIENT1_CK0__RESERVED__SHIFT 0x00000000
80#define CLIENT1_CK1__RESERVED_MASK 0xffffffffL
81#define CLIENT1_CK1__RESERVED__SHIFT 0x00000000
82#define CLIENT1_CK2__RESERVED_MASK 0xffffffffL
83#define CLIENT1_CK2__RESERVED__SHIFT 0x00000000
84#define CLIENT1_CK3__RESERVED_MASK 0xffffffffL
85#define CLIENT1_CK3__RESERVED__SHIFT 0x00000000
86#define CLIENT1_K0__RESERVED_MASK 0xffffffffL
87#define CLIENT1_K0__RESERVED__SHIFT 0x00000000
88#define CLIENT1_K1__RESERVED_MASK 0xffffffffL
89#define CLIENT1_K1__RESERVED__SHIFT 0x00000000
90#define CLIENT1_K2__RESERVED_MASK 0xffffffffL
91#define CLIENT1_K2__RESERVED__SHIFT 0x00000000
92#define CLIENT1_K3__RESERVED_MASK 0xffffffffL
93#define CLIENT1_K3__RESERVED__SHIFT 0x00000000
94#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL
95#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000
96#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL
97#define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000
98#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL
99#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000
100#define CLIENT2_BM__RESERVED_MASK 0xffffffffL
101#define CLIENT2_BM__RESERVED__SHIFT 0x00000000
102#define CLIENT2_CD0__RESERVED_MASK 0xffffffffL
103#define CLIENT2_CD0__RESERVED__SHIFT 0x00000000
104#define CLIENT2_CD1__RESERVED_MASK 0xffffffffL
105#define CLIENT2_CD1__RESERVED__SHIFT 0x00000000
106#define CLIENT2_CD2__RESERVED_MASK 0xffffffffL
107#define CLIENT2_CD2__RESERVED__SHIFT 0x00000000
108#define CLIENT2_CD3__RESERVED_MASK 0xffffffffL
109#define CLIENT2_CD3__RESERVED__SHIFT 0x00000000
110#define CLIENT2_CK0__RESERVED_MASK 0xffffffffL
111#define CLIENT2_CK0__RESERVED__SHIFT 0x00000000
112#define CLIENT2_CK1__RESERVED_MASK 0xffffffffL
113#define CLIENT2_CK1__RESERVED__SHIFT 0x00000000
114#define CLIENT2_CK2__RESERVED_MASK 0xffffffffL
115#define CLIENT2_CK2__RESERVED__SHIFT 0x00000000
116#define CLIENT2_CK3__RESERVED_MASK 0xffffffffL
117#define CLIENT2_CK3__RESERVED__SHIFT 0x00000000
118#define CLIENT2_K0__RESERVED_MASK 0xffffffffL
119#define CLIENT2_K0__RESERVED__SHIFT 0x00000000
120#define CLIENT2_K1__RESERVED_MASK 0xffffffffL
121#define CLIENT2_K1__RESERVED__SHIFT 0x00000000
122#define CLIENT2_K2__RESERVED_MASK 0xffffffffL
123#define CLIENT2_K2__RESERVED__SHIFT 0x00000000
124#define CLIENT2_K3__RESERVED_MASK 0xffffffffL
125#define CLIENT2_K3__RESERVED__SHIFT 0x00000000
126#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffffL
127#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x00000000
128#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL
129#define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000
130#define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL
131#define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000
132#define CLIENT3_BM__RESERVED_MASK 0xffffffffL
133#define CLIENT3_BM__RESERVED__SHIFT 0x00000000
134#define CLIENT3_CD0__RESERVED_MASK 0xffffffffL
135#define CLIENT3_CD0__RESERVED__SHIFT 0x00000000
136#define CLIENT3_CD1__RESERVED_MASK 0xffffffffL
137#define CLIENT3_CD1__RESERVED__SHIFT 0x00000000
138#define CLIENT3_CD2__RESERVED_MASK 0xffffffffL
139#define CLIENT3_CD2__RESERVED__SHIFT 0x00000000
140#define CLIENT3_CD3__RESERVED_MASK 0xffffffffL
141#define CLIENT3_CD3__RESERVED__SHIFT 0x00000000
142#define CLIENT3_CK0__RESERVED_MASK 0xffffffffL
143#define CLIENT3_CK0__RESERVED__SHIFT 0x00000000
144#define CLIENT3_CK1__RESERVED_MASK 0xffffffffL
145#define CLIENT3_CK1__RESERVED__SHIFT 0x00000000
146#define CLIENT3_CK2__RESERVED_MASK 0xffffffffL
147#define CLIENT3_CK2__RESERVED__SHIFT 0x00000000
148#define CLIENT3_CK3__RESERVED_MASK 0xffffffffL
149#define CLIENT3_CK3__RESERVED__SHIFT 0x00000000
150#define CLIENT3_K0__RESERVED_MASK 0xffffffffL
151#define CLIENT3_K0__RESERVED__SHIFT 0x00000000
152#define CLIENT3_K1__RESERVED_MASK 0xffffffffL
153#define CLIENT3_K1__RESERVED__SHIFT 0x00000000
154#define CLIENT3_K2__RESERVED_MASK 0xffffffffL
155#define CLIENT3_K2__RESERVED__SHIFT 0x00000000
156#define CLIENT3_K3__RESERVED_MASK 0xffffffffL
157#define CLIENT3_K3__RESERVED__SHIFT 0x00000000
158#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffffL
159#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x00000000
160#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffffL
161#define CLIENT3_OFFSET__RESERVED__SHIFT 0x00000000
162#define CLIENT3_STATUS__RESERVED_MASK 0xffffffffL
163#define CLIENT3_STATUS__RESERVED__SHIFT 0x00000000
164#define CP_CONFIG__CP_RDREQ_URG_MASK 0x00000f00L
165#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x00000008
166#define CP_CONFIG__CP_REQ_TRAN_MASK 0x00010000L
167#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x00000010
168#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffffL
169#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x00000000
170#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0x000000ffL
171#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x00000000
172#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
173#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
174#define DH_TEST__DH_TEST_MASK 0x00000001L
175#define DH_TEST__DH_TEST__SHIFT 0x00000000
176#define EXP0__RESERVED_MASK 0xffffffffL
177#define EXP0__RESERVED__SHIFT 0x00000000
178#define EXP1__RESERVED_MASK 0xffffffffL
179#define EXP1__RESERVED__SHIFT 0x00000000
180#define EXP2__RESERVED_MASK 0xffffffffL
181#define EXP2__RESERVED__SHIFT 0x00000000
182#define EXP3__RESERVED_MASK 0xffffffffL
183#define EXP3__RESERVED__SHIFT 0x00000000
184#define EXP4__RESERVED_MASK 0xffffffffL
185#define EXP4__RESERVED__SHIFT 0x00000000
186#define EXP5__RESERVED_MASK 0xffffffffL
187#define EXP5__RESERVED__SHIFT 0x00000000
188#define EXP6__RESERVED_MASK 0xffffffffL
189#define EXP6__RESERVED__SHIFT 0x00000000
190#define EXP7__RESERVED_MASK 0xffffffffL
191#define EXP7__RESERVED__SHIFT 0x00000000
192#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
193#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
194#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
195#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
196#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
197#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
198#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
199#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
200#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
201#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
202#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
203#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
204#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
205#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
206#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
207#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
208#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
209#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
210#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
211#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
212#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000
213#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000
214#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
215#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d
216#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L
217#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000
218#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L
219#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016
220#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L
221#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017
222#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
223#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f
224#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L
225#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003
226#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
227#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b
228#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L
229#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018
230#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
231#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015
232#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
233#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013
234#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
235#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e
236#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
237#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009
238#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL
239#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000
240#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffffL
241#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x00000000
242#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003f00L
243#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x00000008
244#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003cL
245#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x00000002
246#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
247#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0x0000000f
248#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
249#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0x0000000e
250#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
251#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x00000001
252#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
253#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x00000007
254#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
255#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000
256#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
257#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x00000006
258#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffffL
259#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x00000000
260#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
261#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x00000003
262#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
263#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x00000001
264#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
265#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x00000002
266#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
267#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x00000000
268#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffffL
269#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x00000000
270#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L
271#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x00000000
272#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001f80L
273#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000007
274#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x0000007eL
275#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000001
276#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x00100000L
277#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x00000014
278#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
279#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x00000015
280#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
281#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x00000000
282#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x00000780L
283#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x00000007
284#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L
285#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d
286#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
287#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x00000006
288#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x00001000L
289#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0x0000000c
290#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
291#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x00000005
292#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x00080000L
293#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x00000013
294#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
295#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0x0000000b
296#define HDP_MISC_CNTL__VM_ID_MASK 0x0000001eL
297#define HDP_MISC_CNTL__VM_ID__SHIFT 0x00000001
298#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffffL
299#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000
300#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L
301#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000
302#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL
303#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001
304#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x03000000L
305#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x00000018
306#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0x00c00000L
307#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x00000016
308#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L
309#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005
310#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0x0c000000L
311#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x0000001a
312#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x30000000L
313#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x0000001c
314#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x00300000L
315#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x00000014
316#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L
317#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007
318#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L
319#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f
320#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L
321#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a
322#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L
323#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d
324#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x40000000L
325#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x0000001e
326#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L
327#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010
328#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0x000e0000L
329#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x00000011
330#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000L
331#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x0000001b
332#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x00000038L
333#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x00000003
334#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0x000ffe00L
335#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x00000009
336#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x000001c0L
337#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x00000006
338#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x00000007L
339#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x00000000
340#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000007ffL
341#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000
342#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800L
343#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000b
344#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
345#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001
346#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
347#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000
348#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
349#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001
350#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
351#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000
352#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L
353#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008
354#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL
355#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000
356#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L
357#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000
358#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L
359#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003
360#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL
361#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000
362#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L
363#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b
364#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L
365#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004
366#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L
367#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006
368#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL
369#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001
370#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L
371#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008
372#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L
373#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e
374#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000fL
375#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x00000000
376#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000f0L
377#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x00000004
378#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000f00L
379#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x00000008
380#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000f000L
381#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0x0000000c
382#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000f0000L
383#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x00000010
384#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00f00000L
385#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x00000014
386#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0f000000L
387#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x00000018
388#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000L
389#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x0000001c
390#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003ffffL
391#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000
392#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL
393#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000
394#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L
395#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004
396#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L
397#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c
398#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L
399#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e
400#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L
401#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f
402#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL
403#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000
404#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L
405#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008
406#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L
407#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010
408#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L
409#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018
410#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL
411#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000
412#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
413#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014
414#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L
415#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010
416#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
417#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012
418#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL
419#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000
420#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
421#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008
422#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L
423#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004
424#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
425#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013
426#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
427#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014
428#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
429#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010
430#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L
431#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011
432#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L
433#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b
434#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL
435#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000
436#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL
437#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000
438#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL
439#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000
440#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL
441#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000
442#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL
443#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000
444#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL
445#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000
446#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL
447#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000
448#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL
449#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000
450#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL
451#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000
452#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL
453#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000
454#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL
455#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000
456#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL
457#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000
458#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL
459#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000
460#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL
461#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000
462#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL
463#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000
464#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL
465#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000
466#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL
467#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000
468#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL
469#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000
470#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL
471#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000
472#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL
473#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000
474#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL
475#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000
476#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL
477#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000
478#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL
479#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000
480#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL
481#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000
482#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL
483#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000
484#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL
485#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000
486#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL
487#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000
488#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL
489#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000
490#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL
491#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000
492#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL
493#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000
494#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL
495#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000
496#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL
497#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000
498#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L
499#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010
500#define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL
501#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000
502#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L
503#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010
504#define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL
505#define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000
506#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L
507#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010
508#define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL
509#define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000
510#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL
511#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000
512#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL
513#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000
514#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL
515#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000
516#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL
517#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000
518#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
519#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c
520#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
521#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0x0000000d
522#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL
523#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000
524#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L
525#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006
526#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L
527#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000
528#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L
529#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001
530#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L
531#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003
532#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x000000f0L
533#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x00000004
534#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L
535#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000
536#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L
537#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001
538#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L
539#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003
540#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x07800000L
541#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x00000017
542#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L
543#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014
544#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L
545#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004
546#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L
547#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005
548#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L
549#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007
550#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000L
551#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x0000001b
552#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L
553#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e
554#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L
555#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008
556#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
557#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000
558#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
559#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001
560#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL
561#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000
562#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L
563#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010
564#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
565#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014
566#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL
567#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000
568#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L
569#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010
570#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
571#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014
572#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL
573#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000
574#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L
575#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010
576#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
577#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014
578#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL
579#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000
580#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L
581#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010
582#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
583#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014
584#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL
585#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000
586#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L
587#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010
588#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
589#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014
590#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL
591#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000
592#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L
593#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010
594#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
595#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014
596#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL
597#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000
598#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L
599#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010
600#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
601#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014
602#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL
603#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000
604#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L
605#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010
606#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
607#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014
608#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL
609#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000
610#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
611#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004
612#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x01e00000L
613#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x00000015
614#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL
615#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001
616#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
617#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000
618#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x01e00000L
619#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x00000015
620#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL
621#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001
622#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
623#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000
624#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x01e00000L
625#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x00000015
626#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL
627#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001
628#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
629#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000
630#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x01e00000L
631#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x00000015
632#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL
633#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001
634#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
635#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000
636#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x01e00000L
637#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x00000015
638#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL
639#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001
640#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
641#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000
642#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x01e00000L
643#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x00000015
644#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL
645#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001
646#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
647#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000
648#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x01e00000L
649#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x00000015
650#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL
651#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001
652#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
653#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000
654#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL
655#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000
656#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L
657#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003
658#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L
659#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000
660#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
661#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001
662#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL
663#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000
664#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L
665#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006
666#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L
667#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007
668#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL
669#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000
670#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L
671#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010
672#define HFS_SEED0__RESERVED_MASK 0xffffffffL
673#define HFS_SEED0__RESERVED__SHIFT 0x00000000
674#define HFS_SEED1__RESERVED_MASK 0xffffffffL
675#define HFS_SEED1__RESERVED__SHIFT 0x00000000
676#define HFS_SEED2__RESERVED_MASK 0xffffffffL
677#define HFS_SEED2__RESERVED__SHIFT 0x00000000
678#define HFS_SEED3__RESERVED_MASK 0xffffffffL
679#define HFS_SEED3__RESERVED__SHIFT 0x00000000
680#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0x0000ff00L
681#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x00000008
682#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000L
683#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x00000010
684#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x00000008L
685#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x00000003
686#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x00000007L
687#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x00000010L
688#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x00000004
689#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x00000000
690#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L
691#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008
692#define IH_CNTL__ENABLE_INTR_MASK 0x00000001L
693#define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000
694#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L
695#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a
696#define IH_CNTL__MC_SWAP_MASK 0x00000006L
697#define IH_CNTL__MC_SWAP__SHIFT 0x00000001
698#define IH_CNTL__MC_TRAN_MASK 0x00000008L
699#define IH_CNTL__MC_TRAN__SHIFT 0x00000003
700#define IH_CNTL__MC_VMID_MASK 0x1e000000L
701#define IH_CNTL__MC_VMID__SHIFT 0x00000019
702#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L
703#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014
704#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L
705#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f
706#define IH_CNTL__RPTR_REARM_MASK 0x00000010L
707#define IH_CNTL__RPTR_REARM__SHIFT 0x00000004
708#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L
709#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004
710#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L
711#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000
712#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L
713#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002
714#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L
715#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003
716#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x00000020L
717#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x00000005
718#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL
719#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000
720#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL
721#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000
722#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
723#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001
724#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00000200L
725#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000009
726#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
727#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000
728#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00000100L
729#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000008
730#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000000fcL
731#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002
732#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0000fc00L
733#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000a
734#define IH_RB_BASE__ADDR_MASK 0xffffffffL
735#define IH_RB_BASE__ADDR__SHIFT 0x00000000
736#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
737#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000
738#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L
739#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006
740#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L
741#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007
742#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL
743#define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001
744#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
745#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f
746#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
747#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010
748#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
749#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008
750#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L
751#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009
752#define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL
753#define IH_RB_RPTR__OFFSET__SHIFT 0x00000002
754#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL
755#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000
756#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL
757#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002
758#define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL
759#define IH_RB_WPTR__OFFSET__SHIFT 0x00000002
760#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
761#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000
762#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
763#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a
764#define IH_STATUS__IDLE_MASK 0x00000001L
765#define IH_STATUS__IDLE__SHIFT 0x00000000
766#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
767#define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001
768#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
769#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008
770#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
771#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009
772#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
773#define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006
774#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
775#define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007
776#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
777#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004
778#define IH_STATUS__RB_FULL_MASK 0x00000008L
779#define IH_STATUS__RB_FULL__SHIFT 0x00000003
780#define IH_STATUS__RB_IDLE_MASK 0x00000004L
781#define IH_STATUS__RB_IDLE__SHIFT 0x00000002
782#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
783#define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005
784#define KEFUSE0__RESERVED_MASK 0xffffffffL
785#define KEFUSE0__RESERVED__SHIFT 0x00000000
786#define KEFUSE1__RESERVED_MASK 0xffffffffL
787#define KEFUSE1__RESERVED__SHIFT 0x00000000
788#define KEFUSE2__RESERVED_MASK 0xffffffffL
789#define KEFUSE2__RESERVED__SHIFT 0x00000000
790#define KEFUSE3__RESERVED_MASK 0xffffffffL
791#define KEFUSE3__RESERVED__SHIFT 0x00000000
792#define KHFS0__RESERVED_MASK 0xffffffffL
793#define KHFS0__RESERVED__SHIFT 0x00000000
794#define KHFS1__RESERVED_MASK 0xffffffffL
795#define KHFS1__RESERVED__SHIFT 0x00000000
796#define KHFS2__RESERVED_MASK 0xffffffffL
797#define KHFS2__RESERVED__SHIFT 0x00000000
798#define KHFS3__RESERVED_MASK 0xffffffffL
799#define KHFS3__RESERVED__SHIFT 0x00000000
800#define KSESSION0__RESERVED_MASK 0xffffffffL
801#define KSESSION0__RESERVED__SHIFT 0x00000000
802#define KSESSION1__RESERVED_MASK 0xffffffffL
803#define KSESSION1__RESERVED__SHIFT 0x00000000
804#define KSESSION2__RESERVED_MASK 0xffffffffL
805#define KSESSION2__RESERVED__SHIFT 0x00000000
806#define KSESSION3__RESERVED_MASK 0xffffffffL
807#define KSESSION3__RESERVED__SHIFT 0x00000000
808#define KSIG0__RESERVED_MASK 0xffffffffL
809#define KSIG0__RESERVED__SHIFT 0x00000000
810#define KSIG1__RESERVED_MASK 0xffffffffL
811#define KSIG1__RESERVED__SHIFT 0x00000000
812#define KSIG2__RESERVED_MASK 0xffffffffL
813#define KSIG2__RESERVED__SHIFT 0x00000000
814#define KSIG3__RESERVED_MASK 0xffffffffL
815#define KSIG3__RESERVED__SHIFT 0x00000000
816#define LX0__RESERVED_MASK 0xffffffffL
817#define LX0__RESERVED__SHIFT 0x00000000
818#define LX1__RESERVED_MASK 0xffffffffL
819#define LX1__RESERVED__SHIFT 0x00000000
820#define LX2__RESERVED_MASK 0xffffffffL
821#define LX2__RESERVED__SHIFT 0x00000000
822#define LX3__RESERVED_MASK 0xffffffffL
823#define LX3__RESERVED__SHIFT 0x00000000
824#define RINGOSC_MASK__MASK_MASK 0x0000ffffL
825#define RINGOSC_MASK__MASK__SHIFT 0x00000000
826#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L
827#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000
828#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L
829#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003
830#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L
831#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006
832#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L
833#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009
834#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L
835#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f
836#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L
837#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015
838#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L
839#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008
840#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL
841#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000
842#define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L
843#define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008
844#define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL
845#define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000
846#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L
847#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000
848#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffffL
849#define SPU_PORT_STATUS__RESERVED__SHIFT 0x00000000
850#define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL
851#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000
852#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L
853#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010
854#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
855#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000
856#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL
857#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000
858#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x00020000L
859#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x00000011
860#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L
861#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010
862#define SRBM_CNTL__READ_TIMEOUT_MASK 0x000003ffL
863#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000
864#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL
865#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000
866#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL
867#define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000
868#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L
869#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001
870#define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L
871#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000
872#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000100L
873#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000008
874#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L
875#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007
876#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L
877#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006
878#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L
879#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002
880#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L
881#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005
882#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L
883#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000
884#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L
885#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c
886#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L
887#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b
888#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L
889#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a
890#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L
891#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019
892#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L
893#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018
894#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L
895#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017
896#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L
897#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016
898#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L
899#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015
900#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L
901#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014
902#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L
903#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013
904#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L
905#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012
906#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L
907#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011
908#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L
909#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010
910#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L
911#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f
912#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L
913#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e
914#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L
915#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d
916#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x00001000L
917#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0x0000000c
918#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L
919#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b
920#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L
921#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009
922#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000L
923#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x0000001d
924#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L
925#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008
926#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x00000400L
927#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0x0000000a
928#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L
929#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004
930#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L
931#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006
932#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L
933#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005
934#define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L
935#define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004
936#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L
937#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000
938#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L
939#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000
940#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L
941#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000
942#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
943#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
944#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
945#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
946#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL
947#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000
948#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL
949#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000
950#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL
951#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
952#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL
953#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000
954#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL
955#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000
956#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL
957#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
958#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
959#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008
960#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
961#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
962#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL
963#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
964#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL
965#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002
966#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
967#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f
968#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L
969#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019
970#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L
971#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018
972#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L
973#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a
974#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L
975#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016
976#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L
977#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d
978#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x00100000L
979#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x00000014
980#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L
981#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001
982#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L
983#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005
984#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L
985#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008
986#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L
987#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009
988#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L
989#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a
990#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L
991#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b
992#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x00800000L
993#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x00000017
994#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L
995#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016
996#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L
997#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e
998#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L
999#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f
1000#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L
1001#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015
1002#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L
1003#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012
1004#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x01000000L
1005#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x00000018
1006#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L
1007#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011
1008#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L
1009#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019
1010#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x00080000L
1011#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x00000013
1012#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L
1013#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001
1014#define SRBM_STATUS2__VCE_BUSY_MASK 0x00000080L
1015#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x00000007
1016#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x00000008L
1017#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x00000003
1018#define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L
1019#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008
1020#define SRBM_STATUS2__XSP_BUSY_MASK 0x00000010L
1021#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x00000004
1022#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L
1023#define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d
1024#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L
1025#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005
1026#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L
1027#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006
1028#define SRBM_STATUS__IH_BUSY_MASK 0x00020000L
1029#define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011
1030#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x00000080L
1031#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x00000007
1032#define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L
1033#define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009
1034#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L
1035#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a
1036#define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L
1037#define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b
1038#define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L
1039#define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c
1040#define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L
1041#define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e
1042#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L
1043#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004
1044#define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L
1045#define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013
1046#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L
1047#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001
1048#define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L
1049#define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008
1050#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
1051#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
1052#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
1053#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
1054#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
1055#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
1056#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
1057#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
1058#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
1059#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
1060#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
1061#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
1062#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0x00000f00L
1063#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x00000008
1064#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x00010000L
1065#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x00000010
1066#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0x00000f00L
1067#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x00000008
1068#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x00010000L
1069#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x00000010
1070#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x00080000L
1071#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x00000013
1072#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000L
1073#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x0000001f
1074#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0x0000ffffL
1075#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x00000000
1076#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000L
1077#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x00000010
1078
1079#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h
new file mode 100644
index 000000000000..6b10be61efc3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h
@@ -0,0 +1,148 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef SMU_6_0_D_H
24#define SMU_6_0_D_H
25
26#define ixLCAC_MC0_CNTL 0x011C
27#define ixLCAC_MC0_OVR_SEL 0x011D
28#define ixLCAC_MC0_OVR_VAL 0x011E
29#define ixLCAC_MC1_CNTL 0x011F
30#define ixLCAC_MC1_OVR_SEL 0x0120
31#define ixLCAC_MC1_OVR_VAL 0x0121
32#define ixLCAC_MC2_CNTL 0x0122
33#define ixLCAC_MC2_OVR_SEL 0x0123
34#define ixLCAC_MC2_OVR_VAL 0x0124
35#define ixLCAC_MC3_CNTL 0x0125
36#define ixLCAC_MC3_OVR_SEL 0x0126
37#define ixLCAC_MC3_OVR_VAL 0x0127
38#define ixLCAC_MC4_CNTL 0x0128
39#define ixLCAC_MC4_OVR_SEL 0x0129
40#define ixLCAC_MC4_OVR_VAL 0x012A
41#define ixLCAC_MC5_CNTL 0x012B
42#define ixLCAC_MC5_OVR_SEL 0x012C
43#define ixLCAC_MC5_OVR_VAL 0x012D
44#define ixSMC_PC_C 0x80000370
45#define ixTHM_TMON0_DEBUG 0x03F0
46#define ixTHM_TMON0_INT_DATA 0x0380
47#define ixTHM_TMON0_RDIL0_DATA 0x0300
48#define ixTHM_TMON0_RDIL10_DATA 0x030A
49#define ixTHM_TMON0_RDIL11_DATA 0x030B
50#define ixTHM_TMON0_RDIL12_DATA 0x030C
51#define ixTHM_TMON0_RDIL13_DATA 0x030D
52#define ixTHM_TMON0_RDIL14_DATA 0x030E
53#define ixTHM_TMON0_RDIL15_DATA 0x030F
54#define ixTHM_TMON0_RDIL1_DATA 0x0301
55#define ixTHM_TMON0_RDIL2_DATA 0x0302
56#define ixTHM_TMON0_RDIL3_DATA 0x0303
57#define ixTHM_TMON0_RDIL4_DATA 0x0304
58#define ixTHM_TMON0_RDIL5_DATA 0x0305
59#define ixTHM_TMON0_RDIL6_DATA 0x0306
60#define ixTHM_TMON0_RDIL7_DATA 0x0307
61#define ixTHM_TMON0_RDIL8_DATA 0x0308
62#define ixTHM_TMON0_RDIL9_DATA 0x0309
63#define ixTHM_TMON0_RDIR0_DATA 0x0310
64#define ixTHM_TMON0_RDIR10_DATA 0x031A
65#define ixTHM_TMON0_RDIR11_DATA 0x031B
66#define ixTHM_TMON0_RDIR12_DATA 0x031C
67#define ixTHM_TMON0_RDIR13_DATA 0x031D
68#define ixTHM_TMON0_RDIR14_DATA 0x031E
69#define ixTHM_TMON0_RDIR15_DATA 0x031F
70#define ixTHM_TMON0_RDIR1_DATA 0x0311
71#define ixTHM_TMON0_RDIR2_DATA 0x0312
72#define ixTHM_TMON0_RDIR3_DATA 0x0313
73#define ixTHM_TMON0_RDIR4_DATA 0x0314
74#define ixTHM_TMON0_RDIR5_DATA 0x0315
75#define ixTHM_TMON0_RDIR6_DATA 0x0316
76#define ixTHM_TMON0_RDIR7_DATA 0x0317
77#define ixTHM_TMON0_RDIR8_DATA 0x0318
78#define ixTHM_TMON0_RDIR9_DATA 0x0319
79#define ixTHM_TMON1_DEBUG 0x03F1
80#define ixTHM_TMON1_INT_DATA 0x0381
81#define ixTHM_TMON1_RDIL0_DATA 0x0320
82#define ixTHM_TMON1_RDIL10_DATA 0x032A
83#define ixTHM_TMON1_RDIL11_DATA 0x032B
84#define ixTHM_TMON1_RDIL12_DATA 0x032C
85#define ixTHM_TMON1_RDIL13_DATA 0x032D
86#define ixTHM_TMON1_RDIL14_DATA 0x032E
87#define ixTHM_TMON1_RDIL15_DATA 0x032F
88#define ixTHM_TMON1_RDIL1_DATA 0x0321
89#define ixTHM_TMON1_RDIL2_DATA 0x0322
90#define ixTHM_TMON1_RDIL3_DATA 0x0323
91#define ixTHM_TMON1_RDIL4_DATA 0x0324
92#define ixTHM_TMON1_RDIL5_DATA 0x0325
93#define ixTHM_TMON1_RDIL6_DATA 0x0326
94#define ixTHM_TMON1_RDIL7_DATA 0x0327
95#define ixTHM_TMON1_RDIL8_DATA 0x0328
96#define ixTHM_TMON1_RDIL9_DATA 0x0329
97#define ixTHM_TMON1_RDIR0_DATA 0x0330
98#define ixTHM_TMON1_RDIR10_DATA 0x033A
99#define ixTHM_TMON1_RDIR11_DATA 0x033B
100#define ixTHM_TMON1_RDIR12_DATA 0x033C
101#define ixTHM_TMON1_RDIR13_DATA 0x033D
102#define ixTHM_TMON1_RDIR14_DATA 0x033E
103#define ixTHM_TMON1_RDIR15_DATA 0x033F
104#define ixTHM_TMON1_RDIR1_DATA 0x0331
105#define ixTHM_TMON1_RDIR2_DATA 0x0332
106#define ixTHM_TMON1_RDIR3_DATA 0x0333
107#define ixTHM_TMON1_RDIR4_DATA 0x0334
108#define ixTHM_TMON1_RDIR5_DATA 0x0335
109#define ixTHM_TMON1_RDIR6_DATA 0x0336
110#define ixTHM_TMON1_RDIR7_DATA 0x0337
111#define ixTHM_TMON1_RDIR8_DATA 0x0338
112#define ixTHM_TMON1_RDIR9_DATA 0x0339
113#define mmGPIOPAD_A 0x05E7
114#define mmGPIOPAD_EN 0x05E8
115#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x05F1
116#define mmGPIOPAD_INT_EN 0x05EE
117#define mmGPIOPAD_INT_POLARITY 0x05F0
118#define mmGPIOPAD_INT_STAT 0x05EC
119#define mmGPIOPAD_INT_STAT_AK 0x05ED
120#define mmGPIOPAD_INT_STAT_EN 0x05EB
121#define mmGPIOPAD_INT_TYPE 0x05EF
122#define mmGPIOPAD_MASK 0x05E6
123#define mmGPIOPAD_PD_EN 0x05F4
124#define mmGPIOPAD_PINSTRAPS 0x05EA
125#define mmGPIOPAD_PU_EN 0x05F3
126#define mmGPIOPAD_RCVR_SEL 0x05F2
127#define mmGPIOPAD_STRENGTH 0x05E5
128#define mmGPIOPAD_SW_INT_STAT 0x05E4
129#define mmGPIOPAD_Y 0x05E9
130#define mmSMC_IND_ACCESS_CNTL 0x008A
131#define mmSMC_IND_DATA_0 0x0081
132#define mmSMC_IND_DATA 0x0081
133#define mmSMC_IND_DATA_1 0x0083
134#define mmSMC_IND_DATA_2 0x0085
135#define mmSMC_IND_DATA_3 0x0087
136#define mmSMC_IND_INDEX_0 0x0080
137#define mmSMC_IND_INDEX 0x0080
138#define mmSMC_IND_INDEX_1 0x0082
139#define mmSMC_IND_INDEX_2 0x0084
140#define mmSMC_IND_INDEX_3 0x0086
141#define mmSMC_MESSAGE_0 0x008B
142#define mmSMC_MESSAGE_1 0x008D
143#define mmSMC_MESSAGE_2 0x008F
144#define mmSMC_RESP_0 0x008C
145#define mmSMC_RESP_1 0x008E
146#define mmSMC_RESP_2 0x0090
147
148#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h
new file mode 100644
index 000000000000..7d3925b7266e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h
@@ -0,0 +1,715 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef SMU_6_0_SH_MASK_H
24#define SMU_6_0_SH_MASK_H
25
26#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL
27#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
28#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L
29#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
30#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
31#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
32#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
33#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
34#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
35#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
36#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L
37#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006
38#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL
39#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000
40#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL
41#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000
42#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
43#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f
44#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL
45#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000
46#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
47#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f
48#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
49#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000
50#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
51#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a
52#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
53#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b
54#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
55#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c
56#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
57#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d
58#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
59#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e
60#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
61#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f
62#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
63#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010
64#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
65#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011
66#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
67#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012
68#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
69#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013
70#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
71#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001
72#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
73#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014
74#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
75#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015
76#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
77#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016
78#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
79#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017
80#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
81#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018
82#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
83#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019
84#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
85#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a
86#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
87#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b
88#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
89#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c
90#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
91#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002
92#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
93#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003
94#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
95#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004
96#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
97#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005
98#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
99#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006
100#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
101#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007
102#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
103#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008
104#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
105#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009
106#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
107#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f
108#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL
109#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000
110#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
111#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f
112#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL
113#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000
114#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
115#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f
116#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL
117#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000
118#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
119#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f
120#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL
121#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000
122#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL
123#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000
124#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
125#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000
126#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
127#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a
128#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
129#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b
130#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
131#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c
132#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
133#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d
134#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
135#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e
136#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
137#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f
138#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
139#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010
140#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
141#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011
142#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
143#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012
144#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
145#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013
146#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
147#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001
148#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
149#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014
150#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
151#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015
152#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
153#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016
154#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
155#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017
156#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
157#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018
158#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
159#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019
160#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
161#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a
162#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
163#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b
164#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
165#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c
166#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
167#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d
168#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
169#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002
170#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
171#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e
172#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
173#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003
174#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
175#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004
176#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
177#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005
178#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
179#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006
180#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
181#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007
182#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
183#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008
184#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
185#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009
186#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL
187#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000
188#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL
189#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000
190#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL
191#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000
192#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L
193#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004
194#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
195#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000
196#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL
197#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000
198#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x00000001L
199#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x00000000
200#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x0001fffeL
201#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x00000001
202#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffffL
203#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x00000000
204#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffffL
205#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x00000000
206#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x00000001L
207#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x00000000
208#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x0001fffeL
209#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x00000001
210#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffffL
211#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x00000000
212#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffffL
213#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x00000000
214#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x00000001L
215#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x00000000
216#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x0001fffeL
217#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x00000001
218#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffffL
219#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x00000000
220#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffffL
221#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x00000000
222#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x00000001L
223#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x00000000
224#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x0001fffeL
225#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x00000001
226#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffffL
227#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x00000000
228#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffffL
229#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x00000000
230#define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x00000001L
231#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x00000000
232#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x0001fffeL
233#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x00000001
234#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffffL
235#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x00000000
236#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffffL
237#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x00000000
238#define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x00000001L
239#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x00000000
240#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x0001fffeL
241#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x00000001
242#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffffL
243#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x00000000
244#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffffL
245#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x00000000
246#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L
247#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000
248#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x00000100L
249#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x00000008
250#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x00010000L
251#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x00000010
252#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x01000000L
253#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018
254#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffffL
255#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x00000000
256#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffffL
257#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x00000000
258#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffffL
259#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x00000000
260#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffffL
261#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x00000000
262#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL
263#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000
264#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffffL
265#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x00000000
266#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffffL
267#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x00000000
268#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffffL
269#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x00000000
270#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffffL
271#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x00000000
272#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL
273#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000
274#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffffffffL
275#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000
276#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffffffffL
277#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000
278#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffffffffL
279#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x00000000
280#define SMC_PC_C__smc_pc_c_MASK 0xffffffffL
281#define SMC_PC_C__smc_pc_c__SHIFT 0x00000000
282#define SMC_RESP_0__SMC_RESP_MASK 0xffffffffL
283#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000
284#define SMC_RESP_1__SMC_RESP_MASK 0xffffffffL
285#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000
286#define SMC_RESP_2__SMC_RESP_MASK 0xffffffffL
287#define SMC_RESP_2__SMC_RESP__SHIFT 0x00000000
288#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L
289#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c
290#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L
291#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004
292#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L
293#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003
294#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L
295#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001
296#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L
297#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c
298#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L
299#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000
300#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L
301#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a
302#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L
303#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002
304#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L
305#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d
306#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L
307#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018
308#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L
309#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c
310#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001fL
311#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x00000000
312#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000ffe0L
313#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x00000005
314#define THM_TMON0_INT_DATA__TEMP_MASK 0x00fff000L
315#define THM_TMON0_INT_DATA__TEMP__SHIFT 0x0000000c
316#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L
317#define THM_TMON0_INT_DATA__VALID__SHIFT 0x0000000b
318#define THM_TMON0_INT_DATA__Z_MASK 0x000007ffL
319#define THM_TMON0_INT_DATA__Z__SHIFT 0x00000000
320#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00fff000L
321#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0x0000000c
322#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L
323#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0x0000000b
324#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007ffL
325#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x00000000
326#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00fff000L
327#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0x0000000c
328#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L
329#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0x0000000b
330#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007ffL
331#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x00000000
332#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00fff000L
333#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0x0000000c
334#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L
335#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0x0000000b
336#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007ffL
337#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x00000000
338#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00fff000L
339#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0x0000000c
340#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L
341#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0x0000000b
342#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007ffL
343#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x00000000
344#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00fff000L
345#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0x0000000c
346#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L
347#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0x0000000b
348#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007ffL
349#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x00000000
350#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00fff000L
351#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0x0000000c
352#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L
353#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0x0000000b
354#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007ffL
355#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x00000000
356#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00fff000L
357#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0x0000000c
358#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L
359#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0x0000000b
360#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007ffL
361#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x00000000
362#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00fff000L
363#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0x0000000c
364#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L
365#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0x0000000b
366#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007ffL
367#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x00000000
368#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00fff000L
369#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0x0000000c
370#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L
371#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0x0000000b
372#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007ffL
373#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x00000000
374#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00fff000L
375#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0x0000000c
376#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L
377#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0x0000000b
378#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007ffL
379#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x00000000
380#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00fff000L
381#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0x0000000c
382#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L
383#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0x0000000b
384#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007ffL
385#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x00000000
386#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00fff000L
387#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0x0000000c
388#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L
389#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0x0000000b
390#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007ffL
391#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000
392#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00fff000L
393#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0x0000000c
394#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L
395#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0x0000000b
396#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007ffL
397#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x00000000
398#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00fff000L
399#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0x0000000c
400#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L
401#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0x0000000b
402#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007ffL
403#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x00000000
404#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00fff000L
405#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0x0000000c
406#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L
407#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b
408#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007ffL
409#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x00000000
410#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00fff000L
411#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0x0000000c
412#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L
413#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0x0000000b
414#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007ffL
415#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x00000000
416#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00fff000L
417#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0x0000000c
418#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L
419#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0x0000000b
420#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007ffL
421#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x00000000
422#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00fff000L
423#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0x0000000c
424#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L
425#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b
426#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007ffL
427#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x00000000
428#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00fff000L
429#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0x0000000c
430#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L
431#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0x0000000b
432#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007ffL
433#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x00000000
434#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00fff000L
435#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0x0000000c
436#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L
437#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0x0000000b
438#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007ffL
439#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x00000000
440#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00fff000L
441#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0x0000000c
442#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L
443#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0x0000000b
444#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007ffL
445#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x00000000
446#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00fff000L
447#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0x0000000c
448#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L
449#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0x0000000b
450#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007ffL
451#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x00000000
452#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00fff000L
453#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0x0000000c
454#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L
455#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0x0000000b
456#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007ffL
457#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x00000000
458#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00fff000L
459#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0x0000000c
460#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L
461#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0x0000000b
462#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007ffL
463#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x00000000
464#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00fff000L
465#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0x0000000c
466#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L
467#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0x0000000b
468#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007ffL
469#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x00000000
470#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00fff000L
471#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0x0000000c
472#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L
473#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0x0000000b
474#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007ffL
475#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x00000000
476#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00fff000L
477#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0x0000000c
478#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L
479#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0x0000000b
480#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007ffL
481#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x00000000
482#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00fff000L
483#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0x0000000c
484#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L
485#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b
486#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007ffL
487#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x00000000
488#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00fff000L
489#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0x0000000c
490#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L
491#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0x0000000b
492#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007ffL
493#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x00000000
494#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00fff000L
495#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0x0000000c
496#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L
497#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0x0000000b
498#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007ffL
499#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x00000000
500#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00fff000L
501#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0x0000000c
502#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L
503#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0x0000000b
504#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007ffL
505#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x00000000
506#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00fff000L
507#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0x0000000c
508#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L
509#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0x0000000b
510#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007ffL
511#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x00000000
512#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001fL
513#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x00000000
514#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000ffe0L
515#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x00000005
516#define THM_TMON1_INT_DATA__TEMP_MASK 0x00fff000L
517#define THM_TMON1_INT_DATA__TEMP__SHIFT 0x0000000c
518#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L
519#define THM_TMON1_INT_DATA__VALID__SHIFT 0x0000000b
520#define THM_TMON1_INT_DATA__Z_MASK 0x000007ffL
521#define THM_TMON1_INT_DATA__Z__SHIFT 0x00000000
522#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00fff000L
523#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0x0000000c
524#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L
525#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0x0000000b
526#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007ffL
527#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x00000000
528#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00fff000L
529#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0x0000000c
530#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L
531#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0x0000000b
532#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007ffL
533#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x00000000
534#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00fff000L
535#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0x0000000c
536#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L
537#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0x0000000b
538#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007ffL
539#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x00000000
540#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00fff000L
541#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0x0000000c
542#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L
543#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0x0000000b
544#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007ffL
545#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x00000000
546#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00fff000L
547#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0x0000000c
548#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L
549#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0x0000000b
550#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007ffL
551#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x00000000
552#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00fff000L
553#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0x0000000c
554#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L
555#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0x0000000b
556#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007ffL
557#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x00000000
558#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00fff000L
559#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0x0000000c
560#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L
561#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0x0000000b
562#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007ffL
563#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x00000000
564#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00fff000L
565#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0x0000000c
566#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L
567#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0x0000000b
568#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007ffL
569#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x00000000
570#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00fff000L
571#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0x0000000c
572#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L
573#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0x0000000b
574#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007ffL
575#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x00000000
576#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00fff000L
577#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0x0000000c
578#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L
579#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0x0000000b
580#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007ffL
581#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x00000000
582#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00fff000L
583#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0x0000000c
584#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L
585#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0x0000000b
586#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007ffL
587#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x00000000
588#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00fff000L
589#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0x0000000c
590#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L
591#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0x0000000b
592#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007ffL
593#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x00000000
594#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00fff000L
595#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0x0000000c
596#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L
597#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0x0000000b
598#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007ffL
599#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x00000000
600#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00fff000L
601#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0x0000000c
602#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L
603#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0x0000000b
604#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007ffL
605#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x00000000
606#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00fff000L
607#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0x0000000c
608#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L
609#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0x0000000b
610#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007ffL
611#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x00000000
612#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00fff000L
613#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0x0000000c
614#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L
615#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0x0000000b
616#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007ffL
617#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x00000000
618#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00fff000L
619#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0x0000000c
620#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L
621#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0x0000000b
622#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007ffL
623#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x00000000
624#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00fff000L
625#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0x0000000c
626#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L
627#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0x0000000b
628#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007ffL
629#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x00000000
630#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00fff000L
631#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0x0000000c
632#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L
633#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0x0000000b
634#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007ffL
635#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x00000000
636#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00fff000L
637#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0x0000000c
638#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L
639#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0x0000000b
640#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007ffL
641#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x00000000
642#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00fff000L
643#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0x0000000c
644#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L
645#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0x0000000b
646#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007ffL
647#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x00000000
648#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00fff000L
649#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0x0000000c
650#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L
651#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0x0000000b
652#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007ffL
653#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x00000000
654#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00fff000L
655#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0x0000000c
656#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L
657#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0x0000000b
658#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007ffL
659#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x00000000
660#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00fff000L
661#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0x0000000c
662#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L
663#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0x0000000b
664#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007ffL
665#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x00000000
666#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00fff000L
667#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0x0000000c
668#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L
669#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0x0000000b
670#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007ffL
671#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x00000000
672#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00fff000L
673#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0x0000000c
674#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L
675#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0x0000000b
676#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007ffL
677#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x00000000
678#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00fff000L
679#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0x0000000c
680#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L
681#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0x0000000b
682#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007ffL
683#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x00000000
684#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00fff000L
685#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0x0000000c
686#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L
687#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0x0000000b
688#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007ffL
689#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x00000000
690#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00fff000L
691#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0x0000000c
692#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L
693#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0x0000000b
694#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007ffL
695#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x00000000
696#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00fff000L
697#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0x0000000c
698#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L
699#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0x0000000b
700#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007ffL
701#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x00000000
702#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00fff000L
703#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0x0000000c
704#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L
705#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0x0000000b
706#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007ffL
707#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x00000000
708#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00fff000L
709#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0x0000000c
710#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L
711#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0x0000000b
712#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007ffL
713#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x00000000
714
715#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h
new file mode 100644
index 000000000000..5c0e3f3332e5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h
@@ -0,0 +1,96 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef UVD_4_0_D_H
24#define UVD_4_0_D_H
25
26#define ixUVD_CGC_CTRL2 0x00C1
27#define ixUVD_CGC_MEM_CTRL 0x00C0
28#define ixUVD_LMI_ADDR_EXT2 0x00AB
29#define ixUVD_LMI_CACHE_CTRL 0x009B
30#define ixUVD_LMI_SWAP_CNTL2 0x00AA
31#define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048
32#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114
33#define ixUVD_MIF_REF_ADDR_CONFIG 0x004C
34#define mmUVD_CGC_CTRL 0x3D2C
35#define mmUVD_CGC_GATE 0x3D2A
36#define mmUVD_CGC_STATUS 0x3D2B
37#define mmUVD_CGC_UDEC_STATUS 0x3D2D
38#define mmUVD_CONTEXT_ID 0x3DBD
39#define mmUVD_CTX_DATA 0x3D29
40#define mmUVD_CTX_INDEX 0x3D28
41#define mmUVD_ENGINE_CNTL 0x3BC6
42#define mmUVD_GPCOM_VCPU_CMD 0x3BC3
43#define mmUVD_GPCOM_VCPU_DATA0 0x3BC4
44#define mmUVD_GPCOM_VCPU_DATA1 0x3BC5
45#define mmUVD_GP_SCRATCH4 0x3D38
46#define mmUVD_LMI_ADDR_EXT 0x3D65
47#define mmUVD_LMI_CTRL 0x3D66
48#define mmUVD_LMI_CTRL2 0x3D3D
49#define mmUVD_LMI_EXT40_ADDR 0x3D26
50#define mmUVD_LMI_STATUS 0x3D67
51#define mmUVD_LMI_SWAP_CNTL 0x3D6D
52#define mmUVD_MASTINT_EN 0x3D40
53#define mmUVD_MPC_CNTL 0x3D77
54#define mmUVD_MPC_SET_ALU 0x3D7E
55#define mmUVD_MPC_SET_MUX 0x3D7D
56#define mmUVD_MPC_SET_MUXA0 0x3D79
57#define mmUVD_MPC_SET_MUXA1 0x3D7A
58#define mmUVD_MPC_SET_MUXB0 0x3D7B
59#define mmUVD_MPC_SET_MUXB1 0x3D7C
60#define mmUVD_MP_SWAP_CNTL 0x3D6F
61#define mmUVD_NO_OP 0x3BFF
62#define mmUVD_PGFSM_CONFIG 0x38F8
63#define mmUVD_PGFSM_READ_TILE1 0x38FA
64#define mmUVD_PGFSM_READ_TILE2 0x38FB
65#define mmUVD_POWER_STATUS 0x38FC
66#define mmUVD_RBC_IB_BASE 0x3DA1
67#define mmUVD_RBC_IB_SIZE 0x3DA2
68#define mmUVD_RBC_IB_SIZE_UPDATE 0x3DF1
69#define mmUVD_RBC_RB_BASE 0x3DA3
70#define mmUVD_RBC_RB_CNTL 0x3DA9
71#define mmUVD_RBC_RB_RPTR 0x3DA4
72#define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA
73#define mmUVD_RBC_RB_WPTR 0x3DA5
74#define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6
75#define mmUVD_SEMA_ADDR_HIGH 0x3BC1
76#define mmUVD_SEMA_ADDR_LOW 0x3BC0
77#define mmUVD_SEMA_CMD 0x3BC2
78#define mmUVD_SEMA_CNTL 0x3D00
79#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3
80#define mmUVD_SEMA_TIMEOUT_STATUS 0x3DB0
81#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3DB2
82#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3DB1
83#define mmUVD_SOFT_RESET 0x3DA0
84#define mmUVD_STATUS 0x3DAF
85#define mmUVD_UDEC_ADDR_CONFIG 0x3BD3
86#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3BD4
87#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5
88#define mmUVD_VCPU_CACHE_OFFSET0 0x3D36
89#define mmUVD_VCPU_CACHE_OFFSET1 0x3D38
90#define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A
91#define mmUVD_VCPU_CACHE_SIZE0 0x3D37
92#define mmUVD_VCPU_CACHE_SIZE1 0x3D39
93#define mmUVD_VCPU_CACHE_SIZE2 0x3D3B
94#define mmUVD_VCPU_CNTL 0x3D98
95
96#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
new file mode 100644
index 000000000000..8ee3149df5b7
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
@@ -0,0 +1,795 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef UVD_4_0_SH_MASK_H
24#define UVD_4_0_SH_MASK_H
25
26#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
36#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
37#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000
38#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
39#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017
40#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
41#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a
42#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
43#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015
44#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
45#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016
46#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
47#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x0000001b
48#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
49#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x00000019
50#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
51#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012
52#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
53#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018
54#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
55#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014
56#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
57#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013
58#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
59#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e
60#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
61#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010
62#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
63#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c
64#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
65#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0x0000000e
66#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
67#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d
68#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
69#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011
70#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
71#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f
72#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
73#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b
74#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
75#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x0000001d
76#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
77#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c
78#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
79#define UVD_CGC_GATE__IDCT__SHIFT 0x00000007
80#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
81#define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a
82#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
83#define UVD_CGC_GATE__LMI_MC__SHIFT 0x00000005
84#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
85#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006
86#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
87#define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b
88#define UVD_CGC_GATE__MPC_MASK 0x00000200L
89#define UVD_CGC_GATE__MPC__SHIFT 0x00000009
90#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
91#define UVD_CGC_GATE__MPEG2__SHIFT 0x00000002
92#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
93#define UVD_CGC_GATE__MPRD__SHIFT 0x00000008
94#define UVD_CGC_GATE__RBC_MASK 0x00000010L
95#define UVD_CGC_GATE__RBC__SHIFT 0x00000004
96#define UVD_CGC_GATE__REGS_MASK 0x00000008L
97#define UVD_CGC_GATE__REGS__SHIFT 0x00000003
98#define UVD_CGC_GATE__SCPU_MASK 0x00080000L
99#define UVD_CGC_GATE__SCPU__SHIFT 0x00000013
100#define UVD_CGC_GATE__SYS_MASK 0x00000001L
101#define UVD_CGC_GATE__SYS__SHIFT 0x00000000
102#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
103#define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d
104#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
105#define UVD_CGC_GATE__UDEC_DB__SHIFT 0x0000000f
106#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
107#define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e
108#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
109#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
110#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x00000010
111#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
112#define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c
113#define UVD_CGC_GATE__UDEC__SHIFT 0x00000001
114#define UVD_CGC_GATE__VCPU_MASK 0x00040000L
115#define UVD_CGC_GATE__VCPU__SHIFT 0x00000012
116#define UVD_CGC_GATE__WCB_MASK 0x00020000L
117#define UVD_CGC_GATE__WCB__SHIFT 0x00000011
118#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L
119#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0x0000000d
120#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L
121#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x00000000
122#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00f00000L
123#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x00000014
124#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000f0000L
125#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x00000010
126#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L
127#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0x0000000c
128#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L
129#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x00000001
130#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L
131#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x00000002
132#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x00000800L
133#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0x0000000b
134#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L
135#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x00000009
136#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L
137#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x00000005
138#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L
139#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x00000007
140#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L
141#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x00000006
142#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L
143#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x00000008
144#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L
145#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x00000004
146#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L
147#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0x0000000a
148#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L
149#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x00000003
150#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
151#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0x0000000e
152#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
153#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0x0000000f
154#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
155#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x00000015
156#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
157#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x00000016
158#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
159#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0x0000000c
160#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
161#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0x0000000d
162#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
163#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x00000017
164#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
165#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014
166#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
167#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013
168#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
169#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x00000007
170#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
171#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x00000006
172#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
173#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x00000008
174#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
175#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x00000011
176#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
177#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x00000010
178#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
179#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x00000012
180#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
181#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0x0000000b
182#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
183#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x00000009
184#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
185#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0x0000000a
186#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L
187#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x0000001b
188#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L
189#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x0000001c
190#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
191#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x00000001
192#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
193#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x00000000
194#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
195#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x00000002
196#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
197#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x00000004
198#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
199#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x00000003
200#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
201#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x00000005
202#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
203#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x00000019
204#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
205#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x0000001a
206#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
207#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x00000018
208#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
209#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x00000004
210#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L
211#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x00000003
212#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L
213#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005
214#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L
215#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0x0000000a
216#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L
217#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x00000009
218#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L
219#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0x0000000b
220#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L
221#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x00000007
222#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L
223#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x00000006
224#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L
225#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x00000008
226#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L
227#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0x0000000d
228#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L
229#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0x0000000c
230#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
231#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0x0000000e
232#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L
233#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x00000001
234#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L
235#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x00000000
236#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L
237#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x00000002
238#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffffL
239#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x00000000
240#define UVD_CTX_DATA__DATA_MASK 0xffffffffL
241#define UVD_CTX_DATA__DATA__SHIFT 0x00000000
242#define UVD_CTX_INDEX__INDEX_MASK 0x000001ffL
243#define UVD_CTX_INDEX__INDEX__SHIFT 0x00000000
244#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L
245#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L
246#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x00000001
247#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x00000000
248#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffeL
249#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
250#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000
251#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001
252#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
253#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x0000001f
254#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffffL
255#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x00000000
256#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffffL
257#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000
258#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0x0000000fL
259#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x00000000
260#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0x00000f00L
261#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x00000008
262#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0x0000f000L
263#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0x0000000c
264#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0x000000f0L
265#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x00000004
266#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0x000000f0L
267#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x00000004
268#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0x00000f00L
269#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x00000008
270#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0x00f00000L
271#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x00000014
272#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0x000f0000L
273#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x00000010
274#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0x0000000fL
275#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x00000000
276#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0x0f000000L
277#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x00000018
278#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000L
279#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x0000001c
280#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0x0000f000L
281#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0x0000000c
282#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x00000004L
283#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x00000002
284#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x00000008L
285#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x00000003
286#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x00000001L
287#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x00000000
288#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x00000002L
289#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x00000001
290#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000010L
291#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000004
292#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000020L
293#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x00000005
294#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
295#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x00000002
296#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
297#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x00000007
298#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
299#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x00000003
300#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x00000070L
301#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x00000004
302#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
303#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x00000009
304#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
305#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0x0000000b
306#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
307#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x00000000
308#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L
309#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0x0000000f
310#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
311#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x00000001
312#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
313#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008
314#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L
315#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0x0000000d
316#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L
317#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0x0000000e
318#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
319#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x0000000b
320#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
321#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x00000016
322#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
323#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0x0000000e
324#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000f8000L
325#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0x0000000f
326#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
327#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0x0000000d
328#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
329#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x00000017
330#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
331#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x00000018
332#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L
333#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x00000014
334#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
335#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x00000019
336#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
337#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0x0000000c
338#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L
339#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x0000001a
340#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
341#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009
342#define UVD_LMI_CTRL__RFU_MASK 0xf8000000L
343#define UVD_LMI_CTRL__RFU_MASK 0xfc000000L
344#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a
345#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b
346#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
347#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
348#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
349#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x00000008
350#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000ffL
351#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000
352#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0x000000ffL
353#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x00000000
354#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x001f0000L
355#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x00000010
356#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000L
357#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x0000001f
358#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L
359#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0x0000000c
360#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L
361#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0x0000000d
362#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L
363#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x00000007
364#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
365#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L
366#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x00000008
367#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x00000000
368#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L
369#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0x0000000b
370#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L
371#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
372#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x00000009
373#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x00000004
374#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L
375#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0x0000000a
376#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L
377#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
378#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x00000006
379#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x00000005
380#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
381#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x00000003
382#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
383#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
384#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x00000002
385#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x00000001
386#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L
387#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x00000000
388#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000cL
389#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x00000002
390#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000c00L
391#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0x0000000a
392#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000c0000L
393#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x00000012
394#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000c000L
395#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0x0000000e
396#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
397#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
398#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x00000010
399#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x00000018
400#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000cL
401#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x00000002
402#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
403#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0x0000000c
404#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000L
405#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x0000001e
406#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00c00000L
407#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x00000016
408#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
409#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x00000000
410#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
411#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x00000004
412#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0c000000L
413#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x0000001a
414#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
415#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x0000001c
416#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000c0L
417#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x00000006
418#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
419#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000008
420#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007ffff0L
421#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x00000004
422#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
423#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x00000000
424#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
425#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x00000002
426#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
427#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x00000001
428#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
429#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
430#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
431#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
432#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
433#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
434#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
435#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
436#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
437#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
438#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
439#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
440#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
441#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
442#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
443#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
444#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
445#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
446#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
447#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
448#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
449#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
450#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
451#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
452#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
453#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
454#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
455#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
456#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
457#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
458#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
459#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
460#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
461#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
462#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
463#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
464#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
465#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
466#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
467#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
468#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
469#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
470#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
471#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
472#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
473#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
474#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
475#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
476#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
477#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
478#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
479#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
480#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
481#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
482#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L
483#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x00000010
484#define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000700L
485#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x00000008
486#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
487#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x00000006
488#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
489#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x00000003
490#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L
491#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x00000012
492#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
493#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x00000000
494#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000ff0L
495#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x00000004
496#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL
497#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000
498#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000fc0L
499#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006
500#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003f000L
501#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c
502#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00fc0000L
503#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012
504#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000L
505#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018
506#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL
507#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000
508#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L
509#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x00000006
510#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L
511#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c
512#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003fL
513#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000
514#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000fc0L
515#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006
516#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003f000L
517#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c
518#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00fc0000L
519#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012
520#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000L
521#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018
522#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003fL
523#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000
524#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000fc0L
525#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006
526#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003f000L
527#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0x0000000c
528#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
529#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000
530#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
531#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003
532#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001c0L
533#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006
534#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
535#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x00000000
536#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
537#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x00000014
538#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00c00000L
539#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x00000016
540#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
541#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x00000018
542#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0c000000L
543#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x0000001a
544#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
545#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x0000001c
546#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000L
547#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x0000001e
548#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000cL
549#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x00000002
550#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
551#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x00000004
552#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000c0L
553#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x00000006
554#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
555#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x00000008
556#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000c00L
557#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0x0000000a
558#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
559#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0x0000000c
560#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000c000L
561#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0x0000000e
562#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
563#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x00000010
564#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000c0000L
565#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x00000012
566#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0x000000ffL
567#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x00000000
568#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x00000400L
569#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0x0000000a
570#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x00000800L
571#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0x0000000b
572#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x00000100L
573#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x00000008
574#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x00000200L
575#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x00000009
576#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x00002000L
577#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0x0000000d
578#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000L
579#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x0000001c
580#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x00001000L
581#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0x0000000c
582#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0x00ffffffL
583#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x00000000
584#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0x00ffffffL
585#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x00000000
586#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L
587#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x00000000
588#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0L
589#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x00000006
590#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007ffff0L
591#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x00000004
592#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0L
593#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x00000006
594#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001f00L
595#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
596#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001fL
597#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
598#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
599#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x00000010
600#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
601#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x00000018
602#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
603#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x0000001c
604#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
605#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x00000014
606#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffffL
607#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000000
608#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007ffff0L
609#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x00000004
610#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007ffff0L
611#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x00000004
612#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0x000fffffL
613#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x00000000
614#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0x000fffffL
615#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x00000000
616#define UVD_SEMA_CMD__MODE_MASK 0x00000040L
617#define UVD_SEMA_CMD__MODE__SHIFT 0x00000006
618#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000fL
619#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x00000000
620#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
621#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x00000007
622#define UVD_SEMA_CMD__VMID_MASK 0x00000f00L
623#define UVD_SEMA_CMD__VMID__SHIFT 0x00000008
624#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
625#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004
626#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
627#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x00000001
628#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
629#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000
630#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
631#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
632#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001ffffeL
633#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x00000001
634#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
635#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x00000000
636#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
637#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000002
638#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
639#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x00000003
640#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
641#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x00000001
642#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
643#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000000
644#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
645#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
646#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001ffffeL
647#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x00000001
648#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
649#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x00000000
650#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
651#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
652#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001ffffeL
653#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x00000001
654#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
655#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x00000000
656#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L
657#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x00000005
658#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
659#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x00000006
660#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x00000200L
661#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x00000009
662#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L
663#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0x0000000c
664#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
665#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0x0000000a
666#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
667#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x00000001
668#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
669#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x00000010
670#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
671#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x00000002
672#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
673#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x0000000d
674#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
675#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x0000000f
676#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
677#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x00000008
678#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L
679#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0x0000000b
680#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
681#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x00000000
682#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
683#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0x0000000e
684#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
685#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x00000007
686#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
687#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x00000004
688#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
689#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x00000003
690#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
691#define UVD_STATUS__RBC_BUSY__SHIFT 0x00000000
692#define UVD_STATUS__VCPU_REPORT_MASK 0x000000feL
693#define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001
694#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
695#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
696#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
697#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
698#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
699#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
700#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
701#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
702#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
703#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
704#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
705#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
706#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
707#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
708#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
709#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
710#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
711#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
712#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
713#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
714#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
715#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
716#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
717#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
718#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
719#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
720#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
721#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
722#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
723#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
724#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
725#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
726#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
727#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
728#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
729#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
730#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
731#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
732#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
733#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
734#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
735#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
736#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
737#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
738#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
739#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
740#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
741#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
742#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
743#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
744#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
745#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
746#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
747#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
748#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01ffffffL
749#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000
750#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01ffffffL
751#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000
752#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01ffffffL
753#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000
754#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001fffffL
755#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x00000000
756#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001fffffL
757#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x00000000
758#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001fffffL
759#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x00000000
760#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L
761#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x00000008
762#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L
763#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x00000004
764#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L
765#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x0000001c
766#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x00020000L
767#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x00000011
768#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
769#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x00000009
770#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000e000L
771#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0x0000000d
772#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000L
773#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x0000001d
774#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000fL
775#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x00000000
776#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L
777#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x00000010
778#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L
779#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x00000005
780#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L
781#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x00000006
782#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0ff00000L
783#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014
784#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L
785#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000007
786#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L
787#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x00000012
788#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L
789#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0x0000000a
790#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L
791#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b
792#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L
793#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x0000001e
794
795#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
new file mode 100644
index 000000000000..2176548e9203
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h
@@ -0,0 +1,64 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef VCE_1_0_D_H
24#define VCE_1_0_D_H
25
26#define mmVCE_CLOCK_GATING_A 0x80BE
27#define mmVCE_CLOCK_GATING_B 0x80BF
28#define mmVCE_LMI_CACHE_CTRL 0x83BD
29#define mmVCE_LMI_CTRL 0x83A6
30#define mmVCE_LMI_CTRL2 0x839D
31#define mmVCE_LMI_MISC_CTRL 0x83B5
32#define mmVCE_LMI_STATUS 0x83A7
33#define mmVCE_LMI_SWAP_CNTL 0x83AD
34#define mmVCE_LMI_SWAP_CNTL1 0x83AE
35#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397
36#define mmVCE_LMI_VM_CTRL 0x83A8
37#define mmVCE_RB_ARB_CTRL 0x809F
38#define mmVCE_RB_BASE_HI 0x8061
39#define mmVCE_RB_BASE_HI2 0x805C
40#define mmVCE_RB_BASE_LO 0x8060
41#define mmVCE_RB_BASE_LO2 0x805B
42#define mmVCE_RB_RPTR 0x8063
43#define mmVCE_RB_RPTR2 0x805E
44#define mmVCE_RB_SIZE 0x8062
45#define mmVCE_RB_SIZE2 0x805D
46#define mmVCE_RB_WPTR 0x8064
47#define mmVCE_RB_WPTR2 0x805F
48#define mmVCE_SOFT_RESET 0x8048
49#define mmVCE_STATUS 0x8001
50#define mmVCE_SYS_INT_ACK 0x8341
51#define mmVCE_SYS_INT_EN 0x8340
52#define mmVCE_SYS_INT_STATUS 0x8341
53#define mmVCE_UENC_CLOCK_GATING 0x816F
54#define mmVCE_UENC_DMA_DCLK_CTRL 0x8250
55#define mmVCE_UENC_REG_CLOCK_GATING 0x8170
56#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
57#define mmVCE_VCPU_CACHE_OFFSET1 0x800B
58#define mmVCE_VCPU_CACHE_OFFSET2 0x800D
59#define mmVCE_VCPU_CACHE_SIZE0 0x800A
60#define mmVCE_VCPU_CACHE_SIZE1 0x800C
61#define mmVCE_VCPU_CACHE_SIZE2 0x800E
62#define mmVCE_VCPU_CNTL 0x8005
63
64#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
new file mode 100644
index 000000000000..ea5b26b11cb1
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h
@@ -0,0 +1,99 @@
1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef VCE_1_0_SH_MASK_H
24#define VCE_1_0_SH_MASK_H
25
26#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
27#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000
28#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
29#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008
30#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
31#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
32#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL
33#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002
34#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L
35#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000
36#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L
37#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000000
38#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003ffcL
39#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x00000002
40#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffffL
41#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x00000000
42#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffffL
43#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x00000000
44#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffffL
45#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
46#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0L
47#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x00000006
48#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0L
49#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x00000006
50#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007ffff0L
51#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x00000004
52#define VCE_RB_RPTR__RB_RPTR_MASK 0x007ffff0L
53#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x00000004
54#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007ffff0L
55#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x00000004
56#define VCE_RB_SIZE__RB_SIZE_MASK 0x007ffff0L
57#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x00000004
58#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007ffff0L
59#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x00000004
60#define VCE_RB_WPTR__RB_WPTR_MASK 0x007ffff0L
61#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004
62#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L
63#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000
64#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
65#define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000
66#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
67#define VCE_STATUS__UENC_BUSY__SHIFT 0x00000008
68#define VCE_STATUS__VCPU_REPORT_MASK 0x000000feL
69#define VCE_STATUS__VCPU_REPORT__SHIFT 0x00000001
70#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L
71#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x00000003
72#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L
73#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x00000003
74#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L
75#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x00000003
76#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x00000002L
77#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x00000001
78#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x00000004L
79#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x00000002
80#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x00000001L
81#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x00000000
82#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0fffffffL
83#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x00000000
84#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0fffffffL
85#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x00000000
86#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0fffffffL
87#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x00000000
88#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00ffffffL
89#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x00000000
90#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00ffffffL
91#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x00000000
92#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00ffffffL
93#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x00000000
94#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L
95#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000
96#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
97#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012
98
99#endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 0b1f2205c2f1..51a36077b993 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -41,7 +41,7 @@
41#define PP_CHECK_HW(hwmgr) \ 41#define PP_CHECK_HW(hwmgr) \
42 do { \ 42 do { \
43 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ 43 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
44 return -EINVAL; \ 44 return 0; \
45 } while (0) 45 } while (0)
46 46
47static int pp_early_init(void *handle) 47static int pp_early_init(void *handle)
@@ -115,6 +115,7 @@ static int pp_hw_init(void *handle)
115 struct pp_instance *pp_handle; 115 struct pp_instance *pp_handle;
116 struct pp_smumgr *smumgr; 116 struct pp_smumgr *smumgr;
117 struct pp_eventmgr *eventmgr; 117 struct pp_eventmgr *eventmgr;
118 struct pp_hwmgr *hwmgr;
118 int ret = 0; 119 int ret = 0;
119 120
120 if (handle == NULL) 121 if (handle == NULL)
@@ -122,6 +123,7 @@ static int pp_hw_init(void *handle)
122 123
123 pp_handle = (struct pp_instance *)handle; 124 pp_handle = (struct pp_instance *)handle;
124 smumgr = pp_handle->smu_mgr; 125 smumgr = pp_handle->smu_mgr;
126 hwmgr = pp_handle->hwmgr;
125 127
126 if (smumgr == NULL || smumgr->smumgr_funcs == NULL || 128 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
127 smumgr->smumgr_funcs->smu_init == NULL || 129 smumgr->smumgr_funcs->smu_init == NULL ||
@@ -141,9 +143,11 @@ static int pp_hw_init(void *handle)
141 return ret; 143 return ret;
142 } 144 }
143 145
144 hw_init_power_state_table(pp_handle->hwmgr); 146 PP_CHECK_HW(hwmgr);
145 eventmgr = pp_handle->eventmgr; 147
148 hw_init_power_state_table(hwmgr);
146 149
150 eventmgr = pp_handle->eventmgr;
147 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) 151 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
148 return -EINVAL; 152 return -EINVAL;
149 153
@@ -243,7 +247,9 @@ static int pp_suspend(void *handle)
243 247
244 pp_handle = (struct pp_instance *)handle; 248 pp_handle = (struct pp_instance *)handle;
245 eventmgr = pp_handle->eventmgr; 249 eventmgr = pp_handle->eventmgr;
246 pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); 250
251 if (eventmgr != NULL)
252 pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
247 return 0; 253 return 0;
248} 254}
249 255
@@ -273,7 +279,8 @@ static int pp_resume(void *handle)
273 } 279 }
274 280
275 eventmgr = pp_handle->eventmgr; 281 eventmgr = pp_handle->eventmgr;
276 pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); 282 if (eventmgr != NULL)
283 pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
277 284
278 return 0; 285 return 0;
279} 286}
@@ -340,8 +347,7 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level(
340 347
341 hwmgr = ((struct pp_instance *)handle)->hwmgr; 348 hwmgr = ((struct pp_instance *)handle)->hwmgr;
342 349
343 if (hwmgr == NULL) 350 PP_CHECK_HW(hwmgr);
344 return -EINVAL;
345 351
346 return (((struct pp_instance *)handle)->hwmgr->dpm_level); 352 return (((struct pp_instance *)handle)->hwmgr->dpm_level);
347} 353}
@@ -448,6 +454,9 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
448 if (pp_handle == NULL) 454 if (pp_handle == NULL)
449 return -EINVAL; 455 return -EINVAL;
450 456
457 if (pp_handle->eventmgr == NULL)
458 return 0;
459
451 switch (event_id) { 460 switch (event_id) {
452 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: 461 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
453 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); 462 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
@@ -582,6 +591,23 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
582 return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); 591 return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
583} 592}
584 593
594static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
595{
596 struct pp_hwmgr *hwmgr;
597
598 if (handle == NULL)
599 return -EINVAL;
600
601 hwmgr = ((struct pp_instance *)handle)->hwmgr;
602
603 PP_CHECK_HW(hwmgr);
604
605 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
606 return -EINVAL;
607
608 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
609}
610
585static int pp_dpm_get_temperature(void *handle) 611static int pp_dpm_get_temperature(void *handle)
586{ 612{
587 struct pp_hwmgr *hwmgr; 613 struct pp_hwmgr *hwmgr;
@@ -852,6 +878,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
852 .get_fan_control_mode = pp_dpm_get_fan_control_mode, 878 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
853 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, 879 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
854 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, 880 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
881 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
855 .get_pp_num_states = pp_dpm_get_pp_num_states, 882 .get_pp_num_states = pp_dpm_get_pp_num_states,
856 .get_pp_table = pp_dpm_get_pp_table, 883 .get_pp_table = pp_dpm_get_pp_table,
857 .set_pp_table = pp_dpm_set_pp_table, 884 .set_pp_table = pp_dpm_set_pp_table,
@@ -881,6 +908,13 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init,
881 if (ret) 908 if (ret)
882 goto fail_smum; 909 goto fail_smum;
883 910
911
912 amd_pp->pp_handle = handle;
913
914 if ((amdgpu_dpm == 0)
915 || cgs_is_virtualization_enabled(pp_init->device))
916 return 0;
917
884 ret = hwmgr_init(pp_init, handle); 918 ret = hwmgr_init(pp_init, handle);
885 if (ret) 919 if (ret)
886 goto fail_hwmgr; 920 goto fail_hwmgr;
@@ -889,7 +923,6 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init,
889 if (ret) 923 if (ret)
890 goto fail_eventmgr; 924 goto fail_eventmgr;
891 925
892 amd_pp->pp_handle = handle;
893 return 0; 926 return 0;
894 927
895fail_eventmgr: 928fail_eventmgr:
@@ -908,12 +941,13 @@ static int amd_pp_instance_fini(void *handle)
908 if (instance == NULL) 941 if (instance == NULL)
909 return -EINVAL; 942 return -EINVAL;
910 943
911 eventmgr_fini(instance->eventmgr); 944 if ((amdgpu_dpm != 0)
912 945 && !cgs_is_virtualization_enabled(instance->smu_mgr->device)) {
913 hwmgr_fini(instance->hwmgr); 946 eventmgr_fini(instance->eventmgr);
947 hwmgr_fini(instance->hwmgr);
948 }
914 949
915 smum_fini(instance->smu_mgr); 950 smum_fini(instance->smu_mgr);
916
917 kfree(handle); 951 kfree(handle);
918 return 0; 952 return 0;
919} 953}
@@ -972,6 +1006,10 @@ int amd_powerplay_reset(void *handle)
972 1006
973 hw_init_power_state_table(instance->hwmgr); 1007 hw_init_power_state_table(instance->hwmgr);
974 1008
1009 if ((amdgpu_dpm == 0)
1010 || cgs_is_virtualization_enabled(instance->smu_mgr->device))
1011 return 0;
1012
975 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) 1013 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
976 return -EINVAL; 1014 return -EINVAL;
977 1015
@@ -993,6 +1031,8 @@ int amd_powerplay_display_configuration_change(void *handle,
993 1031
994 hwmgr = ((struct pp_instance *)handle)->hwmgr; 1032 hwmgr = ((struct pp_instance *)handle)->hwmgr;
995 1033
1034 PP_CHECK_HW(hwmgr);
1035
996 phm_store_dal_configuration_data(hwmgr, display_config); 1036 phm_store_dal_configuration_data(hwmgr, display_config);
997 1037
998 return 0; 1038 return 0;
@@ -1010,6 +1050,8 @@ int amd_powerplay_get_display_power_level(void *handle,
1010 1050
1011 hwmgr = ((struct pp_instance *)handle)->hwmgr; 1051 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1012 1052
1053 PP_CHECK_HW(hwmgr);
1054
1013 return phm_get_dal_power_level(hwmgr, output); 1055 return phm_get_dal_power_level(hwmgr, output);
1014} 1056}
1015 1057
@@ -1027,6 +1069,8 @@ int amd_powerplay_get_current_clocks(void *handle,
1027 1069
1028 hwmgr = ((struct pp_instance *)handle)->hwmgr; 1070 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1029 1071
1072 PP_CHECK_HW(hwmgr);
1073
1030 phm_get_dal_power_level(hwmgr, &simple_clocks); 1074 phm_get_dal_power_level(hwmgr, &simple_clocks);
1031 1075
1032 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { 1076 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
@@ -1071,6 +1115,8 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
1071 1115
1072 hwmgr = ((struct pp_instance *)handle)->hwmgr; 1116 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1073 1117
1118 PP_CHECK_HW(hwmgr);
1119
1074 result = phm_get_clock_by_type(hwmgr, type, clocks); 1120 result = phm_get_clock_by_type(hwmgr, type, clocks);
1075 1121
1076 return result; 1122 return result;
@@ -1089,6 +1135,8 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1089 1135
1090 hwmgr = ((struct pp_instance *)handle)->hwmgr; 1136 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1091 1137
1138 PP_CHECK_HW(hwmgr);
1139
1092 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) 1140 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1093 result = phm_get_max_high_clocks(hwmgr, clocks); 1141 result = phm_get_max_high_clocks(hwmgr, clocks);
1094 1142
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 2028980f1ed4..b0c63c5f54c9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -169,7 +169,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
169 if (bgate) { 169 if (bgate) {
170 cgs_set_clockgating_state(hwmgr->device, 170 cgs_set_clockgating_state(hwmgr->device,
171 AMD_IP_BLOCK_TYPE_UVD, 171 AMD_IP_BLOCK_TYPE_UVD,
172 AMD_CG_STATE_UNGATE); 172 AMD_CG_STATE_GATE);
173 cgs_set_powergating_state(hwmgr->device, 173 cgs_set_powergating_state(hwmgr->device,
174 AMD_IP_BLOCK_TYPE_UVD, 174 AMD_IP_BLOCK_TYPE_UVD,
175 AMD_PG_STATE_GATE); 175 AMD_PG_STATE_GATE);
@@ -182,7 +182,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
182 AMD_CG_STATE_UNGATE); 182 AMD_CG_STATE_UNGATE);
183 cgs_set_clockgating_state(hwmgr->device, 183 cgs_set_clockgating_state(hwmgr->device,
184 AMD_IP_BLOCK_TYPE_UVD, 184 AMD_IP_BLOCK_TYPE_UVD,
185 AMD_PG_STATE_GATE); 185 AMD_PG_STATE_UNGATE);
186 cz_dpm_update_uvd_dpm(hwmgr, false); 186 cz_dpm_update_uvd_dpm(hwmgr, false);
187 } 187 }
188 188
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index e03dcb6ea9c1..dc6700aee18f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
80 switch (hwmgr->chip_id) { 80 switch (hwmgr->chip_id) {
81 case CHIP_TOPAZ: 81 case CHIP_TOPAZ:
82 topaz_set_asic_special_caps(hwmgr); 82 topaz_set_asic_special_caps(hwmgr);
83 hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | 83 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
84 PP_VBI_TIME_SUPPORT_MASK |
85 PP_ENABLE_GFX_CG_THRU_SMU); 84 PP_ENABLE_GFX_CG_THRU_SMU);
86 hwmgr->pp_table_version = PP_TABLE_V0; 85 hwmgr->pp_table_version = PP_TABLE_V0;
87 break; 86 break;
88 case CHIP_TONGA: 87 case CHIP_TONGA:
89 tonga_set_asic_special_caps(hwmgr); 88 tonga_set_asic_special_caps(hwmgr);
90 hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | 89 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
91 PP_VBI_TIME_SUPPORT_MASK);
92 break; 90 break;
93 case CHIP_FIJI: 91 case CHIP_FIJI:
94 fiji_set_asic_special_caps(hwmgr); 92 fiji_set_asic_special_caps(hwmgr);
95 hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | 93 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
96 PP_VBI_TIME_SUPPORT_MASK |
97 PP_ENABLE_GFX_CG_THRU_SMU); 94 PP_ENABLE_GFX_CG_THRU_SMU);
98 break; 95 break;
99 case CHIP_POLARIS11: 96 case CHIP_POLARIS11:
@@ -685,20 +682,24 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
685 682
686int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) 683int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
687{ 684{
688 if (amdgpu_sclk_deep_sleep_en) 685 if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
689 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 686 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
690 PHM_PlatformCaps_SclkDeepSleep); 687 PHM_PlatformCaps_SclkDeepSleep);
691 else 688 else
692 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 689 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
693 PHM_PlatformCaps_SclkDeepSleep); 690 PHM_PlatformCaps_SclkDeepSleep);
694 691
695 if (amdgpu_powercontainment) 692 if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) {
696 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 693 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
697 PHM_PlatformCaps_PowerContainment); 694 PHM_PlatformCaps_PowerContainment);
698 else 695 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
696 PHM_PlatformCaps_CAC);
697 } else {
699 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 698 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
700 PHM_PlatformCaps_PowerContainment); 699 PHM_PlatformCaps_PowerContainment);
701 700 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
701 PHM_PlatformCaps_CAC);
702 }
702 hwmgr->feature_mask = amdgpu_pp_feature_mask; 703 hwmgr->feature_mask = amdgpu_pp_feature_mask;
703 704
704 return 0; 705 return 0;
@@ -736,9 +737,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
736 PHM_PlatformCaps_TCPRamping); 737 PHM_PlatformCaps_TCPRamping);
737 738
738 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 739 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
739 PHM_PlatformCaps_CAC);
740
741 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
742 PHM_PlatformCaps_RegulatorHot); 740 PHM_PlatformCaps_RegulatorHot);
743 741
744 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 742 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
@@ -767,8 +765,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
767 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 765 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
768 PHM_PlatformCaps_TablelessHardwareInterface); 766 PHM_PlatformCaps_TablelessHardwareInterface);
769 767
770 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
771 PHM_PlatformCaps_CAC);
772 return 0; 768 return 0;
773} 769}
774 770
@@ -791,9 +787,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
791 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 787 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
792 PHM_PlatformCaps_TablelessHardwareInterface); 788 PHM_PlatformCaps_TablelessHardwareInterface);
793 789
794 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
795 PHM_PlatformCaps_CAC);
796
797 return 0; 790 return 0;
798} 791}
799 792
@@ -810,8 +803,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
810 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 803 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
811 PHM_PlatformCaps_TablelessHardwareInterface); 804 PHM_PlatformCaps_TablelessHardwareInterface);
812 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 805 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
813 PHM_PlatformCaps_CAC);
814 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
815 PHM_PlatformCaps_EVV); 806 PHM_PlatformCaps_EVV);
816 return 0; 807 return 0;
817} 808}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index cf2ee93d8475..a1fc4fcac1e0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -149,7 +149,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
149 if (bgate) { 149 if (bgate) {
150 cgs_set_clockgating_state(hwmgr->device, 150 cgs_set_clockgating_state(hwmgr->device,
151 AMD_IP_BLOCK_TYPE_UVD, 151 AMD_IP_BLOCK_TYPE_UVD,
152 AMD_CG_STATE_UNGATE); 152 AMD_CG_STATE_GATE);
153 cgs_set_powergating_state(hwmgr->device, 153 cgs_set_powergating_state(hwmgr->device,
154 AMD_IP_BLOCK_TYPE_UVD, 154 AMD_IP_BLOCK_TYPE_UVD,
155 AMD_PG_STATE_GATE); 155 AMD_PG_STATE_GATE);
@@ -162,7 +162,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
162 AMD_CG_STATE_UNGATE); 162 AMD_CG_STATE_UNGATE);
163 cgs_set_clockgating_state(hwmgr->device, 163 cgs_set_clockgating_state(hwmgr->device,
164 AMD_IP_BLOCK_TYPE_UVD, 164 AMD_IP_BLOCK_TYPE_UVD,
165 AMD_CG_STATE_GATE); 165 AMD_CG_STATE_UNGATE);
166 smu7_update_uvd_dpm(hwmgr, false); 166 smu7_update_uvd_dpm(hwmgr, false);
167 } 167 }
168 168
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 85621a77335d..a74f60a575ae 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -993,13 +993,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
993 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 993 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
994 SWRST_COMMAND_1, RESETLC, 0x0); 994 SWRST_COMMAND_1, RESETLC, 0x0);
995 995
996 PP_ASSERT_WITH_CODE(
997 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
998 PPSMC_MSG_Voltage_Cntl_Enable)),
999 "Failed to enable voltage DPM during DPM Start Function!",
1000 return -EINVAL);
1001
1002
1003 if (smu7_enable_sclk_mclk_dpm(hwmgr)) { 996 if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1004 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); 997 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
1005 return -EINVAL; 998 return -EINVAL;
@@ -1428,7 +1421,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1428 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1421 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1429 PHM_PlatformCaps_ControlVDDCI); 1422 PHM_PlatformCaps_ControlVDDCI);
1430 1423
1431 if ((hwmgr->pp_table_version != PP_TABLE_V0) 1424 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1432 && (table_info->cac_dtp_table->usClockStretchAmount != 0)) 1425 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1433 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1426 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1434 PHM_PlatformCaps_ClockStretcher); 1427 PHM_PlatformCaps_ClockStretcher);
@@ -2008,8 +2001,9 @@ static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2008 2001
2009 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = 2002 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2010 table_info->cac_dtp_table->usTargetOperatingTemp; 2003 table_info->cac_dtp_table->usTargetOperatingTemp;
2011 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2004 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2012 PHM_PlatformCaps_ODFuzzyFanControlSupport); 2005 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2006 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2013 } 2007 }
2014 2008
2015 return 0; 2009 return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 41b634ffa5b0..26477f0f09dc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -603,9 +603,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
603 return 0; 603 return 0;
604} 604}
605 605
606static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) 606static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
607 uint32_t target_tdp)
607{ 608{
608 return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, 609 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
609 PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); 610 PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
610} 611}
611 612
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index eb3e83d7af31..3a883e6c601a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -29,6 +29,8 @@
29#include "amd_shared.h" 29#include "amd_shared.h"
30#include "cgs_common.h" 30#include "cgs_common.h"
31 31
32extern int amdgpu_dpm;
33
32enum amd_pp_sensors { 34enum amd_pp_sensors {
33 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 35 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
34 AMDGPU_PP_SENSOR_VDDNB, 36 AMDGPU_PP_SENSOR_VDDNB,
@@ -349,6 +351,7 @@ struct amd_powerplay_funcs {
349 int (*get_fan_control_mode)(void *handle); 351 int (*get_fan_control_mode)(void *handle);
350 int (*set_fan_speed_percent)(void *handle, uint32_t percent); 352 int (*set_fan_speed_percent)(void *handle, uint32_t percent);
351 int (*get_fan_speed_percent)(void *handle, uint32_t *speed); 353 int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
354 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
352 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 355 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
353 int (*get_pp_table)(void *handle, char **table); 356 int (*get_pp_table)(void *handle, char **table);
354 int (*set_pp_table)(void *handle, const char *buf, size_t size); 357 int (*set_pp_table)(void *handle, const char *buf, size_t size);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index e38b999e3235..6cdb7cbf515e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -38,8 +38,6 @@ struct pp_hwmgr;
38struct phm_fan_speed_info; 38struct phm_fan_speed_info;
39struct pp_atomctrl_voltage_table; 39struct pp_atomctrl_voltage_table;
40 40
41extern int amdgpu_powercontainment;
42extern int amdgpu_sclk_deep_sleep_en;
43extern unsigned amdgpu_pp_feature_mask; 41extern unsigned amdgpu_pp_feature_mask;
44 42
45#define VOLTAGE_SCALE 4 43#define VOLTAGE_SCALE 4
@@ -85,7 +83,9 @@ enum PP_FEATURE_MASK {
85 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 83 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
86 PP_VBI_TIME_SUPPORT_MASK = 0x80, 84 PP_VBI_TIME_SUPPORT_MASK = 0x80,
87 PP_ULV_MASK = 0x100, 85 PP_ULV_MASK = 0x100,
88 PP_ENABLE_GFX_CG_THRU_SMU = 0x200 86 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
87 PP_CLOCK_STRETCH_MASK = 0x400,
88 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800
89}; 89};
90 90
91enum PHM_BackEnd_Magic { 91enum PHM_BackEnd_Magic {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index b86e48fb40d1..26eff56b4a99 100755
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -396,7 +396,8 @@ static int fiji_start_smu(struct pp_smumgr *smumgr)
396 struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); 396 struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
397 397
398 /* Only start SMC if SMC RAM is not running */ 398 /* Only start SMC if SMC RAM is not running */
399 if (!smu7_is_smc_ram_running(smumgr)) { 399 if (!(smu7_is_smc_ram_running(smumgr)
400 || cgs_is_virtualization_enabled(smumgr->device))) {
400 fiji_avfs_event_mgr(smumgr, false); 401 fiji_avfs_event_mgr(smumgr, false);
401 402
402 /* Check if SMU is running in protected mode */ 403 /* Check if SMU is running in protected mode */
@@ -443,6 +444,9 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
443 uint32_t efuse = 0; 444 uint32_t efuse = 0;
444 uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; 445 uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
445 446
447 if (cgs_is_virtualization_enabled(smumgr->device))
448 return 0;
449
446 if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, 450 if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
447 mask, &efuse)) { 451 mask, &efuse)) {
448 if (efuse) 452 if (efuse)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 5f9124046b9b..eff9a232e72e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -140,7 +140,8 @@ static int tonga_start_smu(struct pp_smumgr *smumgr)
140 int result; 140 int result;
141 141
142 /* Only start SMC if SMC RAM is not running */ 142 /* Only start SMC if SMC RAM is not running */
143 if (!smu7_is_smc_ram_running(smumgr)) { 143 if (!(smu7_is_smc_ram_running(smumgr) ||
144 cgs_is_virtualization_enabled(smumgr->device))) {
144 /*Check if SMU is running in protected mode*/ 145 /*Check if SMU is running in protected mode*/
145 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, 146 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
146 SMU_FIRMWARE, SMU_MODE)) { 147 SMU_FIRMWARE, SMU_MODE)) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 23:23:07 -0400