1 files changed, 3 insertions, 5 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 352b5fad5a06..ba2b66be9022 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev)
                 pi->caps_td_ramping = true;
                 pi->caps_tcp_ramping = true;
         }
-        if (amdgpu_sclk_deep_sleep_en)
+        if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
                 pi->caps_sclk_ds = true;
         else
                 pi->caps_sclk_ds = false;
@@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 
         if (gate) {
                 if (pi->caps_uvd_pg) {
-                        /* disable clockgating so we can properly shut down the block */
                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_CG_STATE_UNGATE);
+                                                            AMD_CG_STATE_GATE);
                         if (ret) {
                                 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
                                 return;
@@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
                                 return;
                         }
 
-                        /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                            AMD_CG_STATE_GATE);
+                                                            AMD_CG_STATE_UNGATE);
                         if (ret) {
                                 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
                                 return;