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authorLinus Torvalds <torvalds@linux-foundation.org>2016-07-30 14:20:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-07-30 14:20:02 -0400
commit1056c9bd2702ea1bb79abf9bd1e78c578589d247 (patch)
treefaada7d658151c059a845cdb9d9d521817d1e611
parent797cee982eef9195736afc5e7f3b8f613c41d19a (diff)
parentd22527fed2f094c2e4f9a66f35b68a090c3d906a (diff)
Merge tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Michael Turquette: "The bulk of the changes are updates and fixes to existing clk provider drivers, along with a pretty standard number of new drivers. The core recieved a small number of updates as well. Core changes of note: - removed CLK_IS_ROOT flag New clk provider drivers: - Renesas r8a7796 clock pulse generator / module standby and software reset - Allwinner sun8i H3 clock controller unit - AmLogic meson8b clock controller (rewritten) - AmLogic gxbb clock controller - support for some new ICs was added by simple changes to static data tables for chips sharing the same family Driver updates of note: - the Allwinner sunxi clock driver infrastucture was rewritten to comform to the state of the art at drivers/clk/sunxi-ng. The old implementation is still supported for backwards compatibility with the DT ABI" * tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: Makefile: re-sort and clean up Revert "clk: gxbb: expose CLKID_MMC_PCLK" clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver clk: samsung: make clk-s5pv210-audss explicitly non-modular clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocks clk: oxnas: Add hardware dependencies clk: imx7d: do not set parent of ethernet time/ref clocks ARM: dt: sun8i: switch the H3 to the new CCU driver clk: sunxi-ng: h3: Fix Kconfig symbol typo clk: sunxi-ng: h3: Fix audio clock divider offset clk: sunxi-ng: Add H3 clocks clk: sunxi-ng: Add N-K-M-P factor clock clk: sunxi-ng: Add N-K-M Factor clock clk: sunxi-ng: Add N-M-factor clock support clk: sunxi-ng: Add N-K-factor clock support clk: sunxi-ng: Add M-P factor clock support clk: sunxi-ng: Add divider clk: sunxi-ng: Add phase clock support clk: sunxi-ng: Add mux clock support clk: sunxi-ng: Add gate clock support ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt36
-rw-r--r--Documentation/devicetree/bindings/clock/fixed-factor-clock.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt7
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi-ccu.txt24
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi312
-rw-r--r--drivers/clk/Kconfig7
-rw-r--r--drivers/clk/Makefile21
-rw-r--r--drivers/clk/at91/clk-generated.c2
-rw-r--r--drivers/clk/bcm/clk-iproc-armpll.c11
-rw-r--r--drivers/clk/bcm/clk-iproc-asiu.c27
-rw-r--r--drivers/clk/bcm/clk-iproc-pll.c32
-rw-r--r--drivers/clk/clk-conf.c2
-rw-r--r--drivers/clk/clk-fixed-factor.c11
-rw-r--r--drivers/clk/clk-fixed-rate.c11
-rw-r--r--drivers/clk/clk-highbank.c9
-rw-r--r--drivers/clk/clk-multiplier.c20
-rw-r--r--drivers/clk/clk-nomadik.c48
-rw-r--r--drivers/clk/clk-oxnas.c15
-rw-r--r--drivers/clk/clk-s2mps11.c21
-rw-r--r--drivers/clk/clk-stm32f4.c14
-rw-r--r--drivers/clk/clk-u300.c59
-rw-r--r--drivers/clk/clk-vt8500.c99
-rw-r--r--drivers/clk/clk.c347
-rw-r--r--drivers/clk/hisilicon/clk-hi3519.c116
-rw-r--r--drivers/clk/hisilicon/clk-hi6220.c6
-rw-r--r--drivers/clk/hisilicon/clk.c89
-rw-r--r--drivers/clk/hisilicon/clk.h34
-rw-r--r--drivers/clk/hisilicon/clkdivider-hi6220.c2
-rw-r--r--drivers/clk/hisilicon/reset.c19
-rw-r--r--drivers/clk/hisilicon/reset.h5
-rw-r--r--drivers/clk/imx/clk-imx6q.c14
-rw-r--r--drivers/clk/imx/clk-imx6sl.c14
-rw-r--r--drivers/clk/imx/clk-imx6sx.c14
-rw-r--r--drivers/clk/imx/clk-imx6ul.c18
-rw-r--r--drivers/clk/imx/clk-imx7d.c755
-rw-r--r--drivers/clk/imx/clk-pllv3.c28
-rw-r--r--drivers/clk/imx/clk-vf610.c12
-rw-r--r--drivers/clk/imx/clk.h90
-rw-r--r--drivers/clk/meson/Kconfig19
-rw-r--r--drivers/clk/meson/Makefile5
-rw-r--r--drivers/clk/meson/clk-cpu.c73
-rw-r--r--drivers/clk/meson/clk-mpll.c94
-rw-r--r--drivers/clk/meson/clk-pll.c104
-rw-r--r--drivers/clk/meson/clkc.c249
-rw-r--r--drivers/clk/meson/clkc.h179
-rw-r--r--drivers/clk/meson/gxbb.c944
-rw-r--r--drivers/clk/meson/gxbb.h271
-rw-r--r--drivers/clk/meson/meson8b-clkc.c425
-rw-r--r--drivers/clk/nxp/clk-lpc32xx.c3
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c28
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c16
-rw-r--r--drivers/clk/renesas/Kconfig2
-rw-r--r--drivers/clk/renesas/Makefile4
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c374
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c192
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c359
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h43
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c6
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h1
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c125
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c11
-rw-r--r--drivers/clk/samsung/Kconfig9
-rw-r--r--drivers/clk/samsung/Makefile2
-rw-r--r--drivers/clk/samsung/clk-cpu.c131
-rw-r--r--drivers/clk/samsung/clk-cpu.h4
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c12
-rw-r--r--drivers/clk/samsung/clk-exynos-clkout.c2
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c41
-rw-r--r--drivers/clk/samsung/clk-exynos4.c64
-rw-r--r--drivers/clk/samsung/clk-exynos4415.c30
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c27
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c114
-rw-r--r--drivers/clk/samsung/clk-exynos5410.c58
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c40
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c437
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c12
-rw-r--r--drivers/clk/samsung/clk-exynos7.c119
-rw-r--r--drivers/clk/samsung/clk-pll.c122
-rw-r--r--drivers/clk/samsung/clk-s3c2410-dclk.c5
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c2
-rw-r--r--drivers/clk/samsung/clk-s3c2412.c2
-rw-r--r--drivers/clk/samsung/clk-s3c2443.c2
-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c2
-rw-r--r--drivers/clk/samsung/clk-s5pv210-audss.c29
-rw-r--r--drivers/clk/samsung/clk-s5pv210.c2
-rw-r--r--drivers/clk/samsung/clk.c14
-rw-r--r--drivers/clk/samsung/clk.h22
-rw-r--r--drivers/clk/st/clk-flexgen.c4
-rw-r--r--drivers/clk/st/clkgen-fsyn.c10
-rw-r--r--drivers/clk/st/clkgen-pll.c27
-rw-r--r--drivers/clk/sunxi-ng/Kconfig65
-rw-r--r--drivers/clk/sunxi-ng/Makefile20
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c826
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.h62
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.c90
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h85
-rw-r--r--drivers/clk/sunxi-ng/ccu_div.c136
-rw-r--r--drivers/clk/sunxi-ng/ccu_div.h133
-rw-r--r--drivers/clk/sunxi-ng/ccu_frac.c110
-rw-r--r--drivers/clk/sunxi-ng/ccu_frac.h53
-rw-r--r--drivers/clk/sunxi-ng/ccu_gate.c82
-rw-r--r--drivers/clk/sunxi-ng/ccu_gate.h52
-rw-r--r--drivers/clk/sunxi-ng/ccu_mp.c158
-rw-r--r--drivers/clk/sunxi-ng/ccu_mp.h77
-rw-r--r--drivers/clk/sunxi-ng/ccu_mult.h15
-rw-r--r--drivers/clk/sunxi-ng/ccu_mux.c187
-rw-r--r--drivers/clk/sunxi-ng/ccu_mux.h91
-rw-r--r--drivers/clk/sunxi-ng/ccu_nk.c147
-rw-r--r--drivers/clk/sunxi-ng/ccu_nk.h71
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkm.c153
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkm.h68
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkmp.c167
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkmp.h71
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.c114
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.h91
-rw-r--r--drivers/clk/sunxi-ng/ccu_phase.c126
-rw-r--r--drivers/clk/sunxi-ng/ccu_phase.h50
-rw-r--r--drivers/clk/sunxi-ng/ccu_reset.c55
-rw-r--r--drivers/clk/sunxi-ng/ccu_reset.h40
-rw-r--r--drivers/clk/sunxi/clk-factors.c1
-rw-r--r--drivers/clk/sunxi/clk-sun6i-apb0-gates.c9
-rw-r--r--drivers/clk/sunxi/clk-sun6i-apb0.c9
-rw-r--r--drivers/clk/sunxi/clk-sun6i-ar100.c21
-rw-r--r--drivers/clk/sunxi/clk-sun8i-apb0.c9
-rw-r--r--drivers/clk/sunxi/clk-sun9i-mmc.c28
-rw-r--r--drivers/clk/tegra/clk-id.h1
-rw-r--r--drivers/clk/tegra/clk-pll.c505
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c25
-rw-r--r--drivers/clk/tegra/clk-tegra114.c156
-rw-r--r--drivers/clk/tegra/clk-tegra124.c156
-rw-r--r--drivers/clk/tegra/clk-tegra210.c295
-rw-r--r--drivers/clk/tegra/clk-tegra30.c113
-rw-r--r--drivers/clk/tegra/clk.h17
-rw-r--r--include/dt-bindings/clock/exynos5410.h76
-rw-r--r--include/dt-bindings/clock/exynos5433.h3
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h12
-rw-r--r--include/dt-bindings/clock/hi6220-clock.h5
-rw-r--r--include/dt-bindings/clock/lpc32xx-clock.h1
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h4
-rw-r--r--include/dt-bindings/clock/r8a7796-cpg-mssr.h69
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h15
-rw-r--r--include/dt-bindings/clock/sun8i-h3-ccu.h145
-rw-r--r--include/dt-bindings/clock/tegra210-car.h2
-rw-r--r--include/dt-bindings/reset/sun8i-h3-ccu.h103
-rw-r--r--include/linux/clk-provider.h3
-rw-r--r--include/linux/clk.h16
148 files changed, 9004 insertions, 3419 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
new file mode 100644
index 000000000000..ce06435d28ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -0,0 +1,36 @@
1* Amlogic GXBB Clock and Reset Unit
2
3The Amlogic GXBB clock controller generates and supplies clock to various
4controllers within the SoC.
5
6Required Properties:
7
8- compatible: should be "amlogic,gxbb-clkc"
9- reg: physical base address of the clock controller and length of memory
10 mapped region.
11
12- #clock-cells: should be 1.
13
14Each clock is assigned an identifier and client nodes can use this identifier
15to specify the clock which they consume. All available clocks are defined as
16preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
17used in device tree sources.
18
19Example: Clock controller node:
20
21 clkc: clock-controller@c883c000 {
22 #clock-cells = <1>;
23 compatible = "amlogic,gxbb-clkc";
24 reg = <0x0 0xc883c000 0x0 0x3db>;
25 };
26
27Example: UART controller node that consumes the clock generated by the clock
28 controller:
29
30 uart_AO: serial@c81004c0 {
31 compatible = "amlogic,meson-uart";
32 reg = <0xc81004c0 0x14>;
33 interrupts = <0 90 1>;
34 clocks = <&clkc CLKID_CLK81>;
35 status = "disabled";
36 };
diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
index 1bae8527eb9b..189467a7188a 100644
--- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
@@ -14,6 +14,10 @@ Required properties:
14Optional properties: 14Optional properties:
15- clock-output-names : From common clock binding. 15- clock-output-names : From common clock binding.
16 16
17Some clocks that require special treatments are also handled by that
18driver, with the compatibles:
19 - allwinner,sun4i-a10-pll3-2x-clk
20
17Example: 21Example:
18 clock { 22 clock {
19 compatible = "fixed-factor-clock"; 23 compatible = "fixed-factor-clock";
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index fefb8023020f..394d725ac7e0 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,7 +13,8 @@ They provide the following functionalities:
13 13
14Required Properties: 14Required Properties:
15 - compatible: Must be one of: 15 - compatible: Must be one of:
16 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC 16 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
17 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
17 18
18 - reg: Base address and length of the memory resource used by the CPG/MSSR 19 - reg: Base address and length of the memory resource used by the CPG/MSSR
19 block 20 block
@@ -21,8 +22,8 @@ Required Properties:
21 - clocks: References to external parent clocks, one entry for each entry in 22 - clocks: References to external parent clocks, one entry for each entry in
22 clock-names 23 clock-names
23 - clock-names: List of external parent clock names. Valid names are: 24 - clock-names: List of external parent clock names. Valid names are:
24 - "extal" (r8a7795) 25 - "extal" (r8a7795, r8a7796)
25 - "extalr" (r8a7795) 26 - "extalr" (r8a7795, r8a7796)
26 27
27 - #clock-cells: Must be 2 28 - #clock-cells: Must be 2
28 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 29 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 16ed18155160..da578ebdda28 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -17,6 +17,7 @@ Required Properties:
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks 17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks 18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks 19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
20 - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
20 - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks 21 - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
21 - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks 22 - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
22 - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks 23 - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 2a9a8edc8f35..f8c05bb4116e 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -10,6 +10,7 @@ Required Properties:
10 - compatible: Must be one of 10 - compatible: Must be one of
11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG 11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG 12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
13 - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
13 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG 14 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
14 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG 15 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
15 and "renesas,rcar-gen2-cpg-clocks" as a fallback. 16 and "renesas,rcar-gen2-cpg-clocks" as a fallback.
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
new file mode 100644
index 000000000000..cb91507ffb1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -0,0 +1,24 @@
1Allwinner Clock Control Unit Binding
2------------------------------------
3
4Required properties :
5- compatible: must contain one of the following compatible:
6 - "allwinner,sun8i-h3-ccu"
7
8- reg: Must contain the registers base address and length
9- clocks: phandle to the oscillators feeding the CCU. Two are needed:
10 - "hosc": the high frequency oscillator (usually at 24MHz)
11 - "losc": the low frequency oscillator (usually at 32kHz)
12- clock-names: Must contain the clock names described just above
13- #clock-cells : must contain 1
14- #reset-cells : must contain 1
15
16Example:
17ccu: clock@01c20000 {
18 compatible = "allwinner,sun8i-h3-ccu";
19 reg = <0x01c20000 0x400>;
20 clocks = <&osc24M>, <&osc32k>;
21 clock-names = "hosc", "losc";
22 #clock-cells = <1>;
23 #reset-cells = <1>;
24};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 4a4926b0b0ed..9871bad34742 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -42,8 +42,10 @@
42 42
43#include "skeleton.dtsi" 43#include "skeleton.dtsi"
44 44
45#include <dt-bindings/clock/sun8i-h3-ccu.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/pinctrl/sun4i-a10.h> 47#include <dt-bindings/pinctrl/sun4i-a10.h>
48#include <dt-bindings/reset/sun8i-h3-ccu.h>
47 49
48/ { 50/ {
49 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
@@ -104,191 +106,6 @@
104 clock-output-names = "osc32k"; 106 clock-output-names = "osc32k";
105 }; 107 };
106 108
107 pll1: clk@01c20000 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun8i-a23-pll1-clk";
110 reg = <0x01c20000 0x4>;
111 clocks = <&osc24M>;
112 clock-output-names = "pll1";
113 };
114
115 /* dummy clock until actually implemented */
116 pll5: pll5_clk {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "pll5";
121 };
122
123 pll6: clk@01c20028 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-pll6-clk";
126 reg = <0x01c20028 0x4>;
127 clocks = <&osc24M>;
128 clock-output-names = "pll6", "pll6x2";
129 };
130
131 pll6d2: pll6d2_clk {
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clock-div = <2>;
135 clock-mult = <1>;
136 clocks = <&pll6 0>;
137 clock-output-names = "pll6d2";
138 };
139
140 /* dummy clock until pll6 can be reused */
141 pll8: pll8_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 clock-frequency = <1>;
145 clock-output-names = "pll8";
146 };
147
148 cpu: cpu_clk@01c20050 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-cpu-clk";
151 reg = <0x01c20050 0x4>;
152 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
153 clock-output-names = "cpu";
154 };
155
156 axi: axi_clk@01c20050 {
157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-a10-axi-clk";
159 reg = <0x01c20050 0x4>;
160 clocks = <&cpu>;
161 clock-output-names = "axi";
162 };
163
164 ahb1: ahb1_clk@01c20054 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun6i-a31-ahb1-clk";
167 reg = <0x01c20054 0x4>;
168 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
169 clock-output-names = "ahb1";
170 };
171
172 ahb2: ahb2_clk@01c2005c {
173 #clock-cells = <0>;
174 compatible = "allwinner,sun8i-h3-ahb2-clk";
175 reg = <0x01c2005c 0x4>;
176 clocks = <&ahb1>, <&pll6d2>;
177 clock-output-names = "ahb2";
178 };
179
180 apb1: apb1_clk@01c20054 {
181 #clock-cells = <0>;
182 compatible = "allwinner,sun4i-a10-apb0-clk";
183 reg = <0x01c20054 0x4>;
184 clocks = <&ahb1>;
185 clock-output-names = "apb1";
186 };
187
188 apb2: apb2_clk@01c20058 {
189 #clock-cells = <0>;
190 compatible = "allwinner,sun4i-a10-apb1-clk";
191 reg = <0x01c20058 0x4>;
192 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
193 clock-output-names = "apb2";
194 };
195
196 bus_gates: clk@01c20060 {
197 #clock-cells = <1>;
198 compatible = "allwinner,sun8i-h3-bus-gates-clk";
199 reg = <0x01c20060 0x14>;
200 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
201 clock-names = "ahb1", "ahb2", "apb1", "apb2";
202 clock-indices = <5>, <6>, <8>,
203 <9>, <10>, <13>,
204 <14>, <17>, <18>,
205 <19>, <20>,
206 <21>, <23>,
207 <24>, <25>,
208 <26>, <27>,
209 <28>, <29>,
210 <30>, <31>, <32>,
211 <35>, <36>, <37>,
212 <40>, <41>, <43>,
213 <44>, <52>, <53>,
214 <54>, <64>,
215 <65>, <69>, <72>,
216 <76>, <77>, <78>,
217 <96>, <97>, <98>,
218 <112>, <113>,
219 <114>, <115>,
220 <116>, <128>, <135>;
221 clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
222 "bus_mmc1", "bus_mmc2", "bus_nand",
223 "bus_sdram", "bus_gmac", "bus_ts",
224 "bus_hstimer", "bus_spi0",
225 "bus_spi1", "bus_otg",
226 "bus_otg_ehci0", "bus_ehci1",
227 "bus_ehci2", "bus_ehci3",
228 "bus_otg_ohci0", "bus_ohci1",
229 "bus_ohci2", "bus_ohci3", "bus_ve",
230 "bus_lcd0", "bus_lcd1", "bus_deint",
231 "bus_csi", "bus_tve", "bus_hdmi",
232 "bus_de", "bus_gpu", "bus_msgbox",
233 "bus_spinlock", "bus_codec",
234 "bus_spdif", "bus_pio", "bus_ths",
235 "bus_i2s0", "bus_i2s1", "bus_i2s2",
236 "bus_i2c0", "bus_i2c1", "bus_i2c2",
237 "bus_uart0", "bus_uart1",
238 "bus_uart2", "bus_uart3",
239 "bus_scr", "bus_ephy", "bus_dbg";
240 };
241
242 mmc0_clk: clk@01c20088 {
243 #clock-cells = <1>;
244 compatible = "allwinner,sun4i-a10-mmc-clk";
245 reg = <0x01c20088 0x4>;
246 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
247 clock-output-names = "mmc0",
248 "mmc0_output",
249 "mmc0_sample";
250 };
251
252 mmc1_clk: clk@01c2008c {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun4i-a10-mmc-clk";
255 reg = <0x01c2008c 0x4>;
256 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
257 clock-output-names = "mmc1",
258 "mmc1_output",
259 "mmc1_sample";
260 };
261
262 mmc2_clk: clk@01c20090 {
263 #clock-cells = <1>;
264 compatible = "allwinner,sun4i-a10-mmc-clk";
265 reg = <0x01c20090 0x4>;
266 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
267 clock-output-names = "mmc2",
268 "mmc2_output",
269 "mmc2_sample";
270 };
271
272 usb_clk: clk@01c200cc {
273 #clock-cells = <1>;
274 #reset-cells = <1>;
275 compatible = "allwinner,sun8i-h3-usb-clk";
276 reg = <0x01c200cc 0x4>;
277 clocks = <&osc24M>;
278 clock-output-names = "usb_phy0", "usb_phy1",
279 "usb_phy2", "usb_phy3",
280 "usb_ohci0", "usb_ohci1",
281 "usb_ohci2", "usb_ohci3";
282 };
283
284 mbus_clk: clk@01c2015c {
285 #clock-cells = <0>;
286 compatible = "allwinner,sun8i-a23-mbus-clk";
287 reg = <0x01c2015c 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
289 clock-output-names = "mbus";
290 };
291
292 apb0: apb0_clk { 109 apb0: apb0_clk {
293 compatible = "fixed-factor-clock"; 110 compatible = "fixed-factor-clock";
294 #clock-cells = <0>; 111 #clock-cells = <0>;
@@ -327,23 +144,23 @@
327 compatible = "allwinner,sun8i-h3-dma"; 144 compatible = "allwinner,sun8i-h3-dma";
328 reg = <0x01c02000 0x1000>; 145 reg = <0x01c02000 0x1000>;
329 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&bus_gates 6>; 147 clocks = <&ccu CLK_BUS_DMA>;
331 resets = <&ahb_rst 6>; 148 resets = <&ccu RST_BUS_DMA>;
332 #dma-cells = <1>; 149 #dma-cells = <1>;
333 }; 150 };
334 151
335 mmc0: mmc@01c0f000 { 152 mmc0: mmc@01c0f000 {
336 compatible = "allwinner,sun5i-a13-mmc"; 153 compatible = "allwinner,sun5i-a13-mmc";
337 reg = <0x01c0f000 0x1000>; 154 reg = <0x01c0f000 0x1000>;
338 clocks = <&bus_gates 8>, 155 clocks = <&ccu CLK_BUS_MMC0>,
339 <&mmc0_clk 0>, 156 <&ccu CLK_MMC0>,
340 <&mmc0_clk 1>, 157 <&ccu CLK_MMC0_OUTPUT>,
341 <&mmc0_clk 2>; 158 <&ccu CLK_MMC0_SAMPLE>;
342 clock-names = "ahb", 159 clock-names = "ahb",
343 "mmc", 160 "mmc",
344 "output", 161 "output",
345 "sample"; 162 "sample";
346 resets = <&ahb_rst 8>; 163 resets = <&ccu RST_BUS_MMC0>;
347 reset-names = "ahb"; 164 reset-names = "ahb";
348 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 165 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
349 status = "disabled"; 166 status = "disabled";
@@ -354,15 +171,15 @@
354 mmc1: mmc@01c10000 { 171 mmc1: mmc@01c10000 {
355 compatible = "allwinner,sun5i-a13-mmc"; 172 compatible = "allwinner,sun5i-a13-mmc";
356 reg = <0x01c10000 0x1000>; 173 reg = <0x01c10000 0x1000>;
357 clocks = <&bus_gates 9>, 174 clocks = <&ccu CLK_BUS_MMC1>,
358 <&mmc1_clk 0>, 175 <&ccu CLK_MMC1>,
359 <&mmc1_clk 1>, 176 <&ccu CLK_MMC1_OUTPUT>,
360 <&mmc1_clk 2>; 177 <&ccu CLK_MMC1_SAMPLE>;
361 clock-names = "ahb", 178 clock-names = "ahb",
362 "mmc", 179 "mmc",
363 "output", 180 "output",
364 "sample"; 181 "sample";
365 resets = <&ahb_rst 9>; 182 resets = <&ccu RST_BUS_MMC1>;
366 reset-names = "ahb"; 183 reset-names = "ahb";
367 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 184 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
368 status = "disabled"; 185 status = "disabled";
@@ -373,15 +190,15 @@
373 mmc2: mmc@01c11000 { 190 mmc2: mmc@01c11000 {
374 compatible = "allwinner,sun5i-a13-mmc"; 191 compatible = "allwinner,sun5i-a13-mmc";
375 reg = <0x01c11000 0x1000>; 192 reg = <0x01c11000 0x1000>;
376 clocks = <&bus_gates 10>, 193 clocks = <&ccu CLK_BUS_MMC2>,
377 <&mmc2_clk 0>, 194 <&ccu CLK_MMC2>,
378 <&mmc2_clk 1>, 195 <&ccu CLK_MMC2_OUTPUT>,
379 <&mmc2_clk 2>; 196 <&ccu CLK_MMC2_SAMPLE>;
380 clock-names = "ahb", 197 clock-names = "ahb",
381 "mmc", 198 "mmc",
382 "output", 199 "output",
383 "sample"; 200 "sample";
384 resets = <&ahb_rst 10>; 201 resets = <&ccu RST_BUS_MMC2>;
385 reset-names = "ahb"; 202 reset-names = "ahb";
386 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
387 status = "disabled"; 204 status = "disabled";
@@ -401,18 +218,18 @@
401 "pmu1", 218 "pmu1",
402 "pmu2", 219 "pmu2",
403 "pmu3"; 220 "pmu3";
404 clocks = <&usb_clk 8>, 221 clocks = <&ccu CLK_USB_PHY0>,
405 <&usb_clk 9>, 222 <&ccu CLK_USB_PHY1>,
406 <&usb_clk 10>, 223 <&ccu CLK_USB_PHY2>,
407 <&usb_clk 11>; 224 <&ccu CLK_USB_PHY3>;
408 clock-names = "usb0_phy", 225 clock-names = "usb0_phy",
409 "usb1_phy", 226 "usb1_phy",
410 "usb2_phy", 227 "usb2_phy",
411 "usb3_phy"; 228 "usb3_phy";
412 resets = <&usb_clk 0>, 229 resets = <&ccu RST_USB_PHY0>,
413 <&usb_clk 1>, 230 <&ccu RST_USB_PHY1>,
414 <&usb_clk 2>, 231 <&ccu RST_USB_PHY2>,
415 <&usb_clk 3>; 232 <&ccu RST_USB_PHY3>;
416 reset-names = "usb0_reset", 233 reset-names = "usb0_reset",
417 "usb1_reset", 234 "usb1_reset",
418 "usb2_reset", 235 "usb2_reset",
@@ -425,8 +242,8 @@
425 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 242 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
426 reg = <0x01c1b000 0x100>; 243 reg = <0x01c1b000 0x100>;
427 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 244 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&bus_gates 25>, <&bus_gates 29>; 245 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
429 resets = <&ahb_rst 25>, <&ahb_rst 29>; 246 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
430 phys = <&usbphy 1>; 247 phys = <&usbphy 1>;
431 phy-names = "usb"; 248 phy-names = "usb";
432 status = "disabled"; 249 status = "disabled";
@@ -436,9 +253,9 @@
436 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 253 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
437 reg = <0x01c1b400 0x100>; 254 reg = <0x01c1b400 0x100>;
438 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&bus_gates 29>, <&bus_gates 25>, 256 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
440 <&usb_clk 17>; 257 <&ccu CLK_USB_OHCI1>;
441 resets = <&ahb_rst 29>, <&ahb_rst 25>; 258 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
442 phys = <&usbphy 1>; 259 phys = <&usbphy 1>;
443 phy-names = "usb"; 260 phy-names = "usb";
444 status = "disabled"; 261 status = "disabled";
@@ -448,8 +265,8 @@
448 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 265 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
449 reg = <0x01c1c000 0x100>; 266 reg = <0x01c1c000 0x100>;
450 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&bus_gates 26>, <&bus_gates 30>; 268 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
452 resets = <&ahb_rst 26>, <&ahb_rst 30>; 269 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
453 phys = <&usbphy 2>; 270 phys = <&usbphy 2>;
454 phy-names = "usb"; 271 phy-names = "usb";
455 status = "disabled"; 272 status = "disabled";
@@ -459,9 +276,9 @@
459 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 276 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
460 reg = <0x01c1c400 0x100>; 277 reg = <0x01c1c400 0x100>;
461 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 278 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&bus_gates 30>, <&bus_gates 26>, 279 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
463 <&usb_clk 18>; 280 <&ccu CLK_USB_OHCI2>;
464 resets = <&ahb_rst 30>, <&ahb_rst 26>; 281 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
465 phys = <&usbphy 2>; 282 phys = <&usbphy 2>;
466 phy-names = "usb"; 283 phy-names = "usb";
467 status = "disabled"; 284 status = "disabled";
@@ -471,8 +288,8 @@
471 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 288 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
472 reg = <0x01c1d000 0x100>; 289 reg = <0x01c1d000 0x100>;
473 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 290 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&bus_gates 27>, <&bus_gates 31>; 291 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
475 resets = <&ahb_rst 27>, <&ahb_rst 31>; 292 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
476 phys = <&usbphy 3>; 293 phys = <&usbphy 3>;
477 phy-names = "usb"; 294 phy-names = "usb";
478 status = "disabled"; 295 status = "disabled";
@@ -482,20 +299,29 @@
482 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 299 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
483 reg = <0x01c1d400 0x100>; 300 reg = <0x01c1d400 0x100>;
484 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 301 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&bus_gates 31>, <&bus_gates 27>, 302 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
486 <&usb_clk 19>; 303 <&ccu CLK_USB_OHCI3>;
487 resets = <&ahb_rst 31>, <&ahb_rst 27>; 304 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
488 phys = <&usbphy 3>; 305 phys = <&usbphy 3>;
489 phy-names = "usb"; 306 phy-names = "usb";
490 status = "disabled"; 307 status = "disabled";
491 }; 308 };
492 309
310 ccu: clock@01c20000 {
311 compatible = "allwinner,sun8i-h3-ccu";
312 reg = <0x01c20000 0x400>;
313 clocks = <&osc24M>, <&osc32k>;
314 clock-names = "hosc", "losc";
315 #clock-cells = <1>;
316 #reset-cells = <1>;
317 };
318
493 pio: pinctrl@01c20800 { 319 pio: pinctrl@01c20800 {
494 compatible = "allwinner,sun8i-h3-pinctrl"; 320 compatible = "allwinner,sun8i-h3-pinctrl";
495 reg = <0x01c20800 0x400>; 321 reg = <0x01c20800 0x400>;
496 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&bus_gates 69>; 324 clocks = <&ccu CLK_BUS_PIO>;
499 gpio-controller; 325 gpio-controller;
500 #gpio-cells = <3>; 326 #gpio-cells = <3>;
501 interrupt-controller; 327 interrupt-controller;
@@ -542,24 +368,6 @@
542 }; 368 };
543 }; 369 };
544 370
545 ahb_rst: reset@01c202c0 {
546 #reset-cells = <1>;
547 compatible = "allwinner,sun6i-a31-ahb1-reset";
548 reg = <0x01c202c0 0xc>;
549 };
550
551 apb1_rst: reset@01c202d0 {
552 #reset-cells = <1>;
553 compatible = "allwinner,sun6i-a31-clock-reset";
554 reg = <0x01c202d0 0x4>;
555 };
556
557 apb2_rst: reset@01c202d8 {
558 #reset-cells = <1>;
559 compatible = "allwinner,sun6i-a31-clock-reset";
560 reg = <0x01c202d8 0x4>;
561 };
562
563 timer@01c20c00 { 371 timer@01c20c00 {
564 compatible = "allwinner,sun4i-a10-timer"; 372 compatible = "allwinner,sun4i-a10-timer";
565 reg = <0x01c20c00 0xa0>; 373 reg = <0x01c20c00 0xa0>;
@@ -580,8 +388,8 @@
580 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 388 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
581 reg-shift = <2>; 389 reg-shift = <2>;
582 reg-io-width = <4>; 390 reg-io-width = <4>;
583 clocks = <&bus_gates 112>; 391 clocks = <&ccu CLK_BUS_UART0>;
584 resets = <&apb2_rst 16>; 392 resets = <&ccu RST_BUS_UART0>;
585 dmas = <&dma 6>, <&dma 6>; 393 dmas = <&dma 6>, <&dma 6>;
586 dma-names = "rx", "tx"; 394 dma-names = "rx", "tx";
587 status = "disabled"; 395 status = "disabled";
@@ -593,8 +401,8 @@
593 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 401 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
594 reg-shift = <2>; 402 reg-shift = <2>;
595 reg-io-width = <4>; 403 reg-io-width = <4>;
596 clocks = <&bus_gates 113>; 404 clocks = <&ccu CLK_BUS_UART1>;
597 resets = <&apb2_rst 17>; 405 resets = <&ccu RST_BUS_UART1>;
598 dmas = <&dma 7>, <&dma 7>; 406 dmas = <&dma 7>, <&dma 7>;
599 dma-names = "rx", "tx"; 407 dma-names = "rx", "tx";
600 status = "disabled"; 408 status = "disabled";
@@ -606,8 +414,8 @@
606 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 414 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
607 reg-shift = <2>; 415 reg-shift = <2>;
608 reg-io-width = <4>; 416 reg-io-width = <4>;
609 clocks = <&bus_gates 114>; 417 clocks = <&ccu CLK_BUS_UART2>;
610 resets = <&apb2_rst 18>; 418 resets = <&ccu RST_BUS_UART2>;
611 dmas = <&dma 8>, <&dma 8>; 419 dmas = <&dma 8>, <&dma 8>;
612 dma-names = "rx", "tx"; 420 dma-names = "rx", "tx";
613 status = "disabled"; 421 status = "disabled";
@@ -619,8 +427,8 @@
619 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
620 reg-shift = <2>; 428 reg-shift = <2>;
621 reg-io-width = <4>; 429 reg-io-width = <4>;
622 clocks = <&bus_gates 115>; 430 clocks = <&ccu CLK_BUS_UART3>;
623 resets = <&apb2_rst 19>; 431 resets = <&ccu RST_BUS_UART3>;
624 dmas = <&dma 9>, <&dma 9>; 432 dmas = <&dma 9>, <&dma 9>;
625 dma-names = "rx", "tx"; 433 dma-names = "rx", "tx";
626 status = "disabled"; 434 status = "disabled";
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 98efbfcdb503..e2d9bd760c84 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -49,10 +49,10 @@ config COMMON_CLK_MAX77802
49 This driver supports Maxim 77802 crystal oscillator clock. 49 This driver supports Maxim 77802 crystal oscillator clock.
50 50
51config COMMON_CLK_RK808 51config COMMON_CLK_RK808
52 tristate "Clock driver for RK808" 52 tristate "Clock driver for RK808/RK818"
53 depends on MFD_RK808 53 depends on MFD_RK808
54 ---help--- 54 ---help---
55 This driver supports RK808 crystal oscillator clock. These 55 This driver supports RK808 and RK818 crystal oscillator clock. These
56 multi-function devices have two fixed-rate oscillators, 56 multi-function devices have two fixed-rate oscillators,
57 clocked at 32KHz each. Clkout1 is always on, Clkout2 can off 57 clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
58 by control register. 58 by control register.
@@ -203,16 +203,19 @@ config COMMON_CLK_PIC32
203 203
204config COMMON_CLK_OXNAS 204config COMMON_CLK_OXNAS
205 bool "Clock driver for the OXNAS SoC Family" 205 bool "Clock driver for the OXNAS SoC Family"
206 depends on ARCH_OXNAS || COMPILE_TEST
206 select MFD_SYSCON 207 select MFD_SYSCON
207 ---help--- 208 ---help---
208 Support for the OXNAS SoC Family clocks. 209 Support for the OXNAS SoC Family clocks.
209 210
210source "drivers/clk/bcm/Kconfig" 211source "drivers/clk/bcm/Kconfig"
211source "drivers/clk/hisilicon/Kconfig" 212source "drivers/clk/hisilicon/Kconfig"
213source "drivers/clk/meson/Kconfig"
212source "drivers/clk/mvebu/Kconfig" 214source "drivers/clk/mvebu/Kconfig"
213source "drivers/clk/qcom/Kconfig" 215source "drivers/clk/qcom/Kconfig"
214source "drivers/clk/renesas/Kconfig" 216source "drivers/clk/renesas/Kconfig"
215source "drivers/clk/samsung/Kconfig" 217source "drivers/clk/samsung/Kconfig"
218source "drivers/clk/sunxi-ng/Kconfig"
216source "drivers/clk/tegra/Kconfig" 219source "drivers/clk/tegra/Kconfig"
217source "drivers/clk/ti/Kconfig" 220source "drivers/clk/ti/Kconfig"
218 221
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dcc5e698ff6d..3b6f9cf3464a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -16,13 +16,14 @@ obj-$(CONFIG_COMMON_CLK) += clk-conf.o
16endif 16endif
17 17
18# hardware specific clock types 18# hardware specific clock types
19# please keep this section sorted lexicographically by file/directory path name 19# please keep this section sorted lexicographically by file path name
20obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o 20obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
21obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o 21obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
22obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o 22obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
23obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o 23obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
24obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o 24obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
25obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o 25obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
26obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
26obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 27obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
27obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 28obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
28obj-$(CONFIG_MACH_LOONGSON32) += clk-ls1x.o 29obj-$(CONFIG_MACH_LOONGSON32) += clk-ls1x.o
@@ -35,6 +36,7 @@ obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
35obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o 36obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
36obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o 37obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
37obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o 38obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
39obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
38obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o 40obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
39obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o 41obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
40obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o 42obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
@@ -42,7 +44,6 @@ obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o
42obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o 44obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
43obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o 45obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
44obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o 46obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
45obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
46obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o 47obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
47obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o 48obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
48obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o 49obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
@@ -50,35 +51,39 @@ obj-$(CONFIG_ARCH_U300) += clk-u300.o
50obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 51obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
51obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 52obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
52obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 53obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
53obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o 54
55# please keep this section sorted lexicographically by directory path name
54obj-$(CONFIG_COMMON_CLK_AT91) += at91/ 56obj-$(CONFIG_COMMON_CLK_AT91) += at91/
55obj-$(CONFIG_ARCH_ARTPEC) += axis/ 57obj-$(CONFIG_ARCH_ARTPEC) += axis/
58obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
56obj-y += bcm/ 59obj-y += bcm/
57obj-$(CONFIG_ARCH_BERLIN) += berlin/ 60obj-$(CONFIG_ARCH_BERLIN) += berlin/
61obj-$(CONFIG_H8300) += h8300/
58obj-$(CONFIG_ARCH_HISI) += hisilicon/ 62obj-$(CONFIG_ARCH_HISI) += hisilicon/
59obj-$(CONFIG_ARCH_MXC) += imx/ 63obj-$(CONFIG_ARCH_MXC) += imx/
60obj-$(CONFIG_MACH_INGENIC) += ingenic/ 64obj-$(CONFIG_MACH_INGENIC) += ingenic/
61obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 65obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
62obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ 66obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
67obj-$(CONFIG_COMMON_CLK_AMLOGIC) += meson/
63obj-$(CONFIG_MACH_PIC32) += microchip/ 68obj-$(CONFIG_MACH_PIC32) += microchip/
64ifeq ($(CONFIG_COMMON_CLK), y) 69ifeq ($(CONFIG_COMMON_CLK), y)
65obj-$(CONFIG_ARCH_MMP) += mmp/ 70obj-$(CONFIG_ARCH_MMP) += mmp/
66endif 71endif
67obj-y += mvebu/ 72obj-y += mvebu/
68obj-$(CONFIG_ARCH_MESON) += meson/
69obj-$(CONFIG_ARCH_MXS) += mxs/ 73obj-$(CONFIG_ARCH_MXS) += mxs/
70obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
71obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ 74obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
75obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
72obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ 76obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
73obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ 77obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
78obj-$(CONFIG_ARCH_RENESAS) += renesas/
74obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 79obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
75obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ 80obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
76obj-$(CONFIG_ARCH_RENESAS) += renesas/
77obj-$(CONFIG_ARCH_SIRF) += sirf/ 81obj-$(CONFIG_ARCH_SIRF) += sirf/
78obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 82obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
79obj-$(CONFIG_PLAT_SPEAR) += spear/ 83obj-$(CONFIG_PLAT_SPEAR) += spear/
80obj-$(CONFIG_ARCH_STI) += st/ 84obj-$(CONFIG_ARCH_STI) += st/
81obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 85obj-$(CONFIG_ARCH_SUNXI) += sunxi/
86obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/
82obj-$(CONFIG_ARCH_TEGRA) += tegra/ 87obj-$(CONFIG_ARCH_TEGRA) += tegra/
83obj-y += ti/ 88obj-y += ti/
84obj-$(CONFIG_ARCH_U8500) += ux500/ 89obj-$(CONFIG_ARCH_U8500) += ux500/
@@ -86,5 +91,3 @@ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
86obj-$(CONFIG_X86) += x86/ 91obj-$(CONFIG_X86) += x86/
87obj-$(CONFIG_ARCH_ZX) += zte/ 92obj-$(CONFIG_ARCH_ZX) += zte/
88obj-$(CONFIG_ARCH_ZYNQ) += zynq/ 93obj-$(CONFIG_ARCH_ZYNQ) += zynq/
89obj-$(CONFIG_H8300) += h8300/
90obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index e1aa210dd7aa..7f6bec8837ea 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -267,7 +267,7 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const char
267 return clk; 267 return clk;
268} 268}
269 269
270void __init of_sama5d2_clk_generated_setup(struct device_node *np) 270static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
271{ 271{
272 int num; 272 int num;
273 u32 id; 273 u32 id;
diff --git a/drivers/clk/bcm/clk-iproc-armpll.c b/drivers/clk/bcm/clk-iproc-armpll.c
index a196ee28a17a..d7d628214b85 100644
--- a/drivers/clk/bcm/clk-iproc-armpll.c
+++ b/drivers/clk/bcm/clk-iproc-armpll.c
@@ -20,6 +20,8 @@
20#include <linux/clkdev.h> 20#include <linux/clkdev.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22 22
23#include "clk-iproc.h"
24
23#define IPROC_CLK_MAX_FREQ_POLICY 0x3 25#define IPROC_CLK_MAX_FREQ_POLICY 0x3
24#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008 26#define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
25#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8 27#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
@@ -242,7 +244,6 @@ static const struct clk_ops iproc_arm_pll_ops = {
242void __init iproc_armpll_setup(struct device_node *node) 244void __init iproc_armpll_setup(struct device_node *node)
243{ 245{
244 int ret; 246 int ret;
245 struct clk *clk;
246 struct iproc_arm_pll *pll; 247 struct iproc_arm_pll *pll;
247 struct clk_init_data init; 248 struct clk_init_data init;
248 const char *parent_name; 249 const char *parent_name;
@@ -263,18 +264,18 @@ void __init iproc_armpll_setup(struct device_node *node)
263 init.num_parents = (parent_name ? 1 : 0); 264 init.num_parents = (parent_name ? 1 : 0);
264 pll->hw.init = &init; 265 pll->hw.init = &init;
265 266
266 clk = clk_register(NULL, &pll->hw); 267 ret = clk_hw_register(NULL, &pll->hw);
267 if (WARN_ON(IS_ERR(clk))) 268 if (WARN_ON(ret))
268 goto err_iounmap; 269 goto err_iounmap;
269 270
270 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 271 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw);
271 if (WARN_ON(ret)) 272 if (WARN_ON(ret))
272 goto err_clk_unregister; 273 goto err_clk_unregister;
273 274
274 return; 275 return;
275 276
276err_clk_unregister: 277err_clk_unregister:
277 clk_unregister(clk); 278 clk_hw_unregister(&pll->hw);
278err_iounmap: 279err_iounmap:
279 iounmap(pll->base); 280 iounmap(pll->base);
280err_free_pll: 281err_free_pll:
diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
index f630e1bbdcfe..4360e481368b 100644
--- a/drivers/clk/bcm/clk-iproc-asiu.c
+++ b/drivers/clk/bcm/clk-iproc-asiu.c
@@ -37,7 +37,7 @@ struct iproc_asiu {
37 void __iomem *div_base; 37 void __iomem *div_base;
38 void __iomem *gate_base; 38 void __iomem *gate_base;
39 39
40 struct clk_onecell_data clk_data; 40 struct clk_hw_onecell_data *clk_data;
41 struct iproc_asiu_clk *clks; 41 struct iproc_asiu_clk *clks;
42}; 42};
43 43
@@ -197,11 +197,11 @@ void __init iproc_asiu_setup(struct device_node *node,
197 if (WARN_ON(!asiu)) 197 if (WARN_ON(!asiu))
198 return; 198 return;
199 199
200 asiu->clk_data.clk_num = num_clks; 200 asiu->clk_data = kzalloc(sizeof(*asiu->clk_data->hws) * num_clks +
201 asiu->clk_data.clks = kcalloc(num_clks, sizeof(*asiu->clk_data.clks), 201 sizeof(*asiu->clk_data), GFP_KERNEL);
202 GFP_KERNEL); 202 if (WARN_ON(!asiu->clk_data))
203 if (WARN_ON(!asiu->clk_data.clks))
204 goto err_clks; 203 goto err_clks;
204 asiu->clk_data->num = num_clks;
205 205
206 asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL); 206 asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
207 if (WARN_ON(!asiu->clks)) 207 if (WARN_ON(!asiu->clks))
@@ -217,7 +217,6 @@ void __init iproc_asiu_setup(struct device_node *node,
217 217
218 for (i = 0; i < num_clks; i++) { 218 for (i = 0; i < num_clks; i++) {
219 struct clk_init_data init; 219 struct clk_init_data init;
220 struct clk *clk;
221 const char *parent_name; 220 const char *parent_name;
222 struct iproc_asiu_clk *asiu_clk; 221 struct iproc_asiu_clk *asiu_clk;
223 const char *clk_name; 222 const char *clk_name;
@@ -240,22 +239,22 @@ void __init iproc_asiu_setup(struct device_node *node,
240 init.num_parents = (parent_name ? 1 : 0); 239 init.num_parents = (parent_name ? 1 : 0);
241 asiu_clk->hw.init = &init; 240 asiu_clk->hw.init = &init;
242 241
243 clk = clk_register(NULL, &asiu_clk->hw); 242 ret = clk_hw_register(NULL, &asiu_clk->hw);
244 if (WARN_ON(IS_ERR(clk))) 243 if (WARN_ON(ret))
245 goto err_clk_register; 244 goto err_clk_register;
246 asiu->clk_data.clks[i] = clk; 245 asiu->clk_data->hws[i] = &asiu_clk->hw;
247 } 246 }
248 247
249 ret = of_clk_add_provider(node, of_clk_src_onecell_get, 248 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
250 &asiu->clk_data); 249 asiu->clk_data);
251 if (WARN_ON(ret)) 250 if (WARN_ON(ret))
252 goto err_clk_register; 251 goto err_clk_register;
253 252
254 return; 253 return;
255 254
256err_clk_register: 255err_clk_register:
257 for (i = 0; i < num_clks; i++) 256 while (--i >= 0)
258 clk_unregister(asiu->clk_data.clks[i]); 257 clk_hw_unregister(asiu->clk_data->hws[i]);
259 iounmap(asiu->gate_base); 258 iounmap(asiu->gate_base);
260 259
261err_iomap_gate: 260err_iomap_gate:
@@ -265,7 +264,7 @@ err_iomap_div:
265 kfree(asiu->clks); 264 kfree(asiu->clks);
266 265
267err_asiu_clks: 266err_asiu_clks:
268 kfree(asiu->clk_data.clks); 267 kfree(asiu->clk_data);
269 268
270err_clks: 269err_clks:
271 kfree(asiu); 270 kfree(asiu);
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index fd492a5dad12..e04634c46395 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -89,7 +89,7 @@ struct iproc_pll {
89 const struct iproc_pll_vco_param *vco_param; 89 const struct iproc_pll_vco_param *vco_param;
90 unsigned int num_vco_entries; 90 unsigned int num_vco_entries;
91 91
92 struct clk_onecell_data clk_data; 92 struct clk_hw_onecell_data *clk_data;
93 struct iproc_clk *clks; 93 struct iproc_clk *clks;
94}; 94};
95 95
@@ -625,7 +625,6 @@ void __init iproc_pll_clk_setup(struct device_node *node,
625 unsigned int num_clks) 625 unsigned int num_clks)
626{ 626{
627 int i, ret; 627 int i, ret;
628 struct clk *clk;
629 struct iproc_pll *pll; 628 struct iproc_pll *pll;
630 struct iproc_clk *iclk; 629 struct iproc_clk *iclk;
631 struct clk_init_data init; 630 struct clk_init_data init;
@@ -638,11 +637,11 @@ void __init iproc_pll_clk_setup(struct device_node *node,
638 if (WARN_ON(!pll)) 637 if (WARN_ON(!pll))
639 return; 638 return;
640 639
641 pll->clk_data.clk_num = num_clks; 640 pll->clk_data = kzalloc(sizeof(*pll->clk_data->hws) * num_clks +
642 pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks), 641 sizeof(*pll->clk_data), GFP_KERNEL);
643 GFP_KERNEL); 642 if (WARN_ON(!pll->clk_data))
644 if (WARN_ON(!pll->clk_data.clks))
645 goto err_clk_data; 643 goto err_clk_data;
644 pll->clk_data->num = num_clks;
646 645
647 pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL); 646 pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL);
648 if (WARN_ON(!pll->clks)) 647 if (WARN_ON(!pll->clks))
@@ -694,11 +693,11 @@ void __init iproc_pll_clk_setup(struct device_node *node,
694 693
695 iproc_pll_sw_cfg(pll); 694 iproc_pll_sw_cfg(pll);
696 695
697 clk = clk_register(NULL, &iclk->hw); 696 ret = clk_hw_register(NULL, &iclk->hw);
698 if (WARN_ON(IS_ERR(clk))) 697 if (WARN_ON(ret))
699 goto err_pll_register; 698 goto err_pll_register;
700 699
701 pll->clk_data.clks[0] = clk; 700 pll->clk_data->hws[0] = &iclk->hw;
702 701
703 /* now initialize and register all leaf clocks */ 702 /* now initialize and register all leaf clocks */
704 for (i = 1; i < num_clks; i++) { 703 for (i = 1; i < num_clks; i++) {
@@ -724,22 +723,23 @@ void __init iproc_pll_clk_setup(struct device_node *node,
724 init.num_parents = (parent_name ? 1 : 0); 723 init.num_parents = (parent_name ? 1 : 0);
725 iclk->hw.init = &init; 724 iclk->hw.init = &init;
726 725
727 clk = clk_register(NULL, &iclk->hw); 726 ret = clk_hw_register(NULL, &iclk->hw);
728 if (WARN_ON(IS_ERR(clk))) 727 if (WARN_ON(ret))
729 goto err_clk_register; 728 goto err_clk_register;
730 729
731 pll->clk_data.clks[i] = clk; 730 pll->clk_data->hws[i] = &iclk->hw;
732 } 731 }
733 732
734 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data); 733 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
734 pll->clk_data);
735 if (WARN_ON(ret)) 735 if (WARN_ON(ret))
736 goto err_clk_register; 736 goto err_clk_register;
737 737
738 return; 738 return;
739 739
740err_clk_register: 740err_clk_register:
741 for (i = 0; i < num_clks; i++) 741 while (--i >= 0)
742 clk_unregister(pll->clk_data.clks[i]); 742 clk_hw_unregister(pll->clk_data->hws[i]);
743 743
744err_pll_register: 744err_pll_register:
745 if (pll->status_base != pll->control_base) 745 if (pll->status_base != pll->control_base)
@@ -759,7 +759,7 @@ err_pll_iomap:
759 kfree(pll->clks); 759 kfree(pll->clks);
760 760
761err_clks: 761err_clks:
762 kfree(pll->clk_data.clks); 762 kfree(pll->clk_data);
763 763
764err_clk_data: 764err_clk_data:
765 kfree(pll); 765 kfree(pll);
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 43a218f35b19..674785d968a3 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -55,7 +55,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
55 } 55 }
56 clk = of_clk_get_from_provider(&clkspec); 56 clk = of_clk_get_from_provider(&clkspec);
57 if (IS_ERR(clk)) { 57 if (IS_ERR(clk)) {
58 pr_warn("clk: couldn't get parent clock %d for %s\n", 58 pr_warn("clk: couldn't get assigned clock %d for %s\n",
59 index, node->full_name); 59 index, node->full_name);
60 rc = PTR_ERR(clk); 60 rc = PTR_ERR(clk);
61 goto err; 61 goto err;
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 75cd6c792cb8..4db3be214077 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -142,6 +142,11 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
142EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); 142EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
143 143
144#ifdef CONFIG_OF 144#ifdef CONFIG_OF
145static const struct of_device_id set_rate_parent_matches[] = {
146 { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
147 { /* Sentinel */ },
148};
149
145/** 150/**
146 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock 151 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
147 */ 152 */
@@ -150,6 +155,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
150 struct clk *clk; 155 struct clk *clk;
151 const char *clk_name = node->name; 156 const char *clk_name = node->name;
152 const char *parent_name; 157 const char *parent_name;
158 unsigned long flags = 0;
153 u32 div, mult; 159 u32 div, mult;
154 160
155 if (of_property_read_u32(node, "clock-div", &div)) { 161 if (of_property_read_u32(node, "clock-div", &div)) {
@@ -167,7 +173,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node)
167 of_property_read_string(node, "clock-output-names", &clk_name); 173 of_property_read_string(node, "clock-output-names", &clk_name);
168 parent_name = of_clk_get_parent_name(node, 0); 174 parent_name = of_clk_get_parent_name(node, 0);
169 175
170 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 176 if (of_match_node(set_rate_parent_matches, node))
177 flags |= CLK_SET_RATE_PARENT;
178
179 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
171 mult, div); 180 mult, div);
172 if (!IS_ERR(clk)) 181 if (!IS_ERR(clk))
173 of_clk_add_provider(node, of_clk_src_simple_get, clk); 182 of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 8e4453eb54e8..2edb39342a02 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -145,6 +145,17 @@ void clk_unregister_fixed_rate(struct clk *clk)
145} 145}
146EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate); 146EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate);
147 147
148void clk_hw_unregister_fixed_rate(struct clk_hw *hw)
149{
150 struct clk_fixed_rate *fixed;
151
152 fixed = to_clk_fixed_rate(hw);
153
154 clk_hw_unregister(hw);
155 kfree(fixed);
156}
157EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_rate);
158
148#ifdef CONFIG_OF 159#ifdef CONFIG_OF
149/** 160/**
150 * of_fixed_clk_setup() - Setup function for simple fixed rate clock 161 * of_fixed_clk_setup() - Setup function for simple fixed rate clock
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index be3a21abb185..727ed8e1bb72 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -275,7 +275,6 @@ static const struct clk_ops periclk_ops = {
275static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops) 275static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
276{ 276{
277 u32 reg; 277 u32 reg;
278 struct clk *clk;
279 struct hb_clk *hb_clk; 278 struct hb_clk *hb_clk;
280 const char *clk_name = node->name; 279 const char *clk_name = node->name;
281 const char *parent_name; 280 const char *parent_name;
@@ -308,13 +307,13 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
308 307
309 hb_clk->hw.init = &init; 308 hb_clk->hw.init = &init;
310 309
311 clk = clk_register(NULL, &hb_clk->hw); 310 rc = clk_hw_register(NULL, &hb_clk->hw);
312 if (WARN_ON(IS_ERR(clk))) { 311 if (WARN_ON(rc)) {
313 kfree(hb_clk); 312 kfree(hb_clk);
314 return NULL; 313 return NULL;
315 } 314 }
316 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 315 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
317 return clk; 316 return hb_clk->hw.clk;
318} 317}
319 318
320static void __init hb_pll_init(struct device_node *node) 319static void __init hb_pll_init(struct device_node *node)
diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
index 9e449c7b751c..dc037c957acd 100644
--- a/drivers/clk/clk-multiplier.c
+++ b/drivers/clk/clk-multiplier.c
@@ -52,14 +52,28 @@ static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
52 unsigned long *best_parent_rate, 52 unsigned long *best_parent_rate,
53 u8 width, unsigned long flags) 53 u8 width, unsigned long flags)
54{ 54{
55 struct clk_multiplier *mult = to_clk_multiplier(hw);
55 unsigned long orig_parent_rate = *best_parent_rate; 56 unsigned long orig_parent_rate = *best_parent_rate;
56 unsigned long parent_rate, current_rate, best_rate = ~0; 57 unsigned long parent_rate, current_rate, best_rate = ~0;
57 unsigned int i, bestmult = 0; 58 unsigned int i, bestmult = 0;
59 unsigned int maxmult = (1 << width) - 1;
60
61 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
62 bestmult = rate / orig_parent_rate;
63
64 /* Make sure we don't end up with a 0 multiplier */
65 if ((bestmult == 0) &&
66 !(mult->flags & CLK_MULTIPLIER_ZERO_BYPASS))
67 bestmult = 1;
58 68
59 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) 69 /* Make sure we don't overflow the multiplier */
60 return rate / *best_parent_rate; 70 if (bestmult > maxmult)
71 bestmult = maxmult;
72
73 return bestmult;
74 }
61 75
62 for (i = 1; i < ((1 << width) - 1); i++) { 76 for (i = 1; i < maxmult; i++) {
63 if (rate == orig_parent_rate * i) { 77 if (rate == orig_parent_rate * i) {
64 /* 78 /*
65 * This is the best case for us if we have a 79 * This is the best case for us if we have a
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
index e4d8a991c58f..71677eb12565 100644
--- a/drivers/clk/clk-nomadik.c
+++ b/drivers/clk/clk-nomadik.c
@@ -253,11 +253,11 @@ static const struct clk_ops pll_clk_ops = {
253 .recalc_rate = pll_clk_recalc_rate, 253 .recalc_rate = pll_clk_recalc_rate,
254}; 254};
255 255
256static struct clk * __init 256static struct clk_hw * __init
257pll_clk_register(struct device *dev, const char *name, 257pll_clk_register(struct device *dev, const char *name,
258 const char *parent_name, u32 id) 258 const char *parent_name, u32 id)
259{ 259{
260 struct clk *clk; 260 int ret;
261 struct clk_pll *pll; 261 struct clk_pll *pll;
262 struct clk_init_data init; 262 struct clk_init_data init;
263 263
@@ -281,11 +281,13 @@ pll_clk_register(struct device *dev, const char *name,
281 281
282 pr_debug("register PLL1 clock \"%s\"\n", name); 282 pr_debug("register PLL1 clock \"%s\"\n", name);
283 283
284 clk = clk_register(dev, &pll->hw); 284 ret = clk_hw_register(dev, &pll->hw);
285 if (IS_ERR(clk)) 285 if (ret) {
286 kfree(pll); 286 kfree(pll);
287 return ERR_PTR(ret);
288 }
287 289
288 return clk; 290 return &pll->hw;
289} 291}
290 292
291/* 293/*
@@ -345,11 +347,11 @@ static const struct clk_ops src_clk_ops = {
345 .recalc_rate = src_clk_recalc_rate, 347 .recalc_rate = src_clk_recalc_rate,
346}; 348};
347 349
348static struct clk * __init 350static struct clk_hw * __init
349src_clk_register(struct device *dev, const char *name, 351src_clk_register(struct device *dev, const char *name,
350 const char *parent_name, u8 id) 352 const char *parent_name, u8 id)
351{ 353{
352 struct clk *clk; 354 int ret;
353 struct clk_src *sclk; 355 struct clk_src *sclk;
354 struct clk_init_data init; 356 struct clk_init_data init;
355 357
@@ -376,11 +378,13 @@ src_clk_register(struct device *dev, const char *name,
376 pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n", 378 pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
377 name, id, sclk->group1, sclk->clkbit); 379 name, id, sclk->group1, sclk->clkbit);
378 380
379 clk = clk_register(dev, &sclk->hw); 381 ret = clk_hw_register(dev, &sclk->hw);
380 if (IS_ERR(clk)) 382 if (ret) {
381 kfree(sclk); 383 kfree(sclk);
384 return ERR_PTR(ret);
385 }
382 386
383 return clk; 387 return &sclk->hw;
384} 388}
385 389
386#ifdef CONFIG_DEBUG_FS 390#ifdef CONFIG_DEBUG_FS
@@ -508,7 +512,7 @@ device_initcall(nomadik_src_clk_init_debugfs);
508 512
509static void __init of_nomadik_pll_setup(struct device_node *np) 513static void __init of_nomadik_pll_setup(struct device_node *np)
510{ 514{
511 struct clk *clk = ERR_PTR(-EINVAL); 515 struct clk_hw *hw;
512 const char *clk_name = np->name; 516 const char *clk_name = np->name;
513 const char *parent_name; 517 const char *parent_name;
514 u32 pll_id; 518 u32 pll_id;
@@ -522,16 +526,16 @@ static void __init of_nomadik_pll_setup(struct device_node *np)
522 return; 526 return;
523 } 527 }
524 parent_name = of_clk_get_parent_name(np, 0); 528 parent_name = of_clk_get_parent_name(np, 0);
525 clk = pll_clk_register(NULL, clk_name, parent_name, pll_id); 529 hw = pll_clk_register(NULL, clk_name, parent_name, pll_id);
526 if (!IS_ERR(clk)) 530 if (!IS_ERR(hw))
527 of_clk_add_provider(np, of_clk_src_simple_get, clk); 531 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
528} 532}
529CLK_OF_DECLARE(nomadik_pll_clk, 533CLK_OF_DECLARE(nomadik_pll_clk,
530 "st,nomadik-pll-clock", of_nomadik_pll_setup); 534 "st,nomadik-pll-clock", of_nomadik_pll_setup);
531 535
532static void __init of_nomadik_hclk_setup(struct device_node *np) 536static void __init of_nomadik_hclk_setup(struct device_node *np)
533{ 537{
534 struct clk *clk = ERR_PTR(-EINVAL); 538 struct clk_hw *hw;
535 const char *clk_name = np->name; 539 const char *clk_name = np->name;
536 const char *parent_name; 540 const char *parent_name;
537 541
@@ -542,20 +546,20 @@ static void __init of_nomadik_hclk_setup(struct device_node *np)
542 /* 546 /*
543 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4. 547 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
544 */ 548 */
545 clk = clk_register_divider(NULL, clk_name, parent_name, 549 hw = clk_hw_register_divider(NULL, clk_name, parent_name,
546 0, src_base + SRC_CR, 550 0, src_base + SRC_CR,
547 13, 2, 551 13, 2,
548 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 552 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
549 &src_lock); 553 &src_lock);
550 if (!IS_ERR(clk)) 554 if (!IS_ERR(hw))
551 of_clk_add_provider(np, of_clk_src_simple_get, clk); 555 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
552} 556}
553CLK_OF_DECLARE(nomadik_hclk_clk, 557CLK_OF_DECLARE(nomadik_hclk_clk,
554 "st,nomadik-hclk-clock", of_nomadik_hclk_setup); 558 "st,nomadik-hclk-clock", of_nomadik_hclk_setup);
555 559
556static void __init of_nomadik_src_clk_setup(struct device_node *np) 560static void __init of_nomadik_src_clk_setup(struct device_node *np)
557{ 561{
558 struct clk *clk = ERR_PTR(-EINVAL); 562 struct clk_hw *hw;
559 const char *clk_name = np->name; 563 const char *clk_name = np->name;
560 const char *parent_name; 564 const char *parent_name;
561 u32 clk_id; 565 u32 clk_id;
@@ -569,9 +573,9 @@ static void __init of_nomadik_src_clk_setup(struct device_node *np)
569 return; 573 return;
570 } 574 }
571 parent_name = of_clk_get_parent_name(np, 0); 575 parent_name = of_clk_get_parent_name(np, 0);
572 clk = src_clk_register(NULL, clk_name, parent_name, clk_id); 576 hw = src_clk_register(NULL, clk_name, parent_name, clk_id);
573 if (!IS_ERR(clk)) 577 if (!IS_ERR(hw))
574 of_clk_add_provider(np, of_clk_src_simple_get, clk); 578 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
575} 579}
576CLK_OF_DECLARE(nomadik_src_clk, 580CLK_OF_DECLARE(nomadik_src_clk,
577 "st,nomadik-src-clock", of_nomadik_src_clk_setup); 581 "st,nomadik-src-clock", of_nomadik_src_clk_setup);
diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
index 79bcb2e42060..47649ac5d399 100644
--- a/drivers/clk/clk-oxnas.c
+++ b/drivers/clk/clk-oxnas.c
@@ -18,7 +18,7 @@
18 18
19#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/module.h> 21#include <linux/init.h>
22#include <linux/of.h> 22#include <linux/of.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/stringify.h> 24#include <linux/stringify.h>
@@ -170,26 +170,17 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
170 clk_oxnas->onecell_data); 170 clk_oxnas->onecell_data);
171} 171}
172 172
173static int oxnas_stdclk_remove(struct platform_device *pdev)
174{
175 of_clk_del_provider(pdev->dev.of_node);
176
177 return 0;
178}
179
180static const struct of_device_id oxnas_stdclk_dt_ids[] = { 173static const struct of_device_id oxnas_stdclk_dt_ids[] = {
181 { .compatible = "oxsemi,ox810se-stdclk" }, 174 { .compatible = "oxsemi,ox810se-stdclk" },
182 { } 175 { }
183}; 176};
184MODULE_DEVICE_TABLE(of, oxnas_stdclk_dt_ids);
185 177
186static struct platform_driver oxnas_stdclk_driver = { 178static struct platform_driver oxnas_stdclk_driver = {
187 .probe = oxnas_stdclk_probe, 179 .probe = oxnas_stdclk_probe,
188 .remove = oxnas_stdclk_remove,
189 .driver = { 180 .driver = {
190 .name = "oxnas-stdclk", 181 .name = "oxnas-stdclk",
182 .suppress_bind_attrs = true,
191 .of_match_table = oxnas_stdclk_dt_ids, 183 .of_match_table = oxnas_stdclk_dt_ids,
192 }, 184 },
193}; 185};
194 186builtin_platform_driver(oxnas_stdclk_driver);
195module_platform_driver(oxnas_stdclk_driver);
diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
index f8c83977c7fa..fbaa84a33c46 100644
--- a/drivers/clk/clk-s2mps11.c
+++ b/drivers/clk/clk-s2mps11.c
@@ -137,7 +137,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
137{ 137{
138 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); 138 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
139 struct s2mps11_clk *s2mps11_clks; 139 struct s2mps11_clk *s2mps11_clks;
140 struct clk_onecell_data *clk_data; 140 struct clk_hw_onecell_data *clk_data;
141 unsigned int s2mps11_reg; 141 unsigned int s2mps11_reg;
142 int i, ret = 0; 142 int i, ret = 0;
143 enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data; 143 enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data;
@@ -147,15 +147,12 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
147 if (!s2mps11_clks) 147 if (!s2mps11_clks)
148 return -ENOMEM; 148 return -ENOMEM;
149 149
150 clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); 150 clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data) +
151 sizeof(*clk_data->hws) * S2MPS11_CLKS_NUM,
152 GFP_KERNEL);
151 if (!clk_data) 153 if (!clk_data)
152 return -ENOMEM; 154 return -ENOMEM;
153 155
154 clk_data->clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
155 sizeof(struct clk *), GFP_KERNEL);
156 if (!clk_data->clks)
157 return -ENOMEM;
158
159 switch (hwid) { 156 switch (hwid) {
160 case S2MPS11X: 157 case S2MPS11X:
161 s2mps11_reg = S2MPS11_REG_RTC_CTRL; 158 s2mps11_reg = S2MPS11_REG_RTC_CTRL;
@@ -196,18 +193,18 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
196 goto err_reg; 193 goto err_reg;
197 } 194 }
198 195
199 s2mps11_clks[i].lookup = clkdev_create(s2mps11_clks[i].clk, 196 s2mps11_clks[i].lookup = clkdev_hw_create(&s2mps11_clks[i].hw,
200 s2mps11_clks_init[i].name, NULL); 197 s2mps11_clks_init[i].name, NULL);
201 if (!s2mps11_clks[i].lookup) { 198 if (!s2mps11_clks[i].lookup) {
202 ret = -ENOMEM; 199 ret = -ENOMEM;
203 goto err_reg; 200 goto err_reg;
204 } 201 }
205 clk_data->clks[i] = s2mps11_clks[i].clk; 202 clk_data->hws[i] = &s2mps11_clks[i].hw;
206 } 203 }
207 204
208 clk_data->clk_num = S2MPS11_CLKS_NUM; 205 clk_data->num = S2MPS11_CLKS_NUM;
209 of_clk_add_provider(s2mps11_clks->clk_np, of_clk_src_onecell_get, 206 of_clk_add_hw_provider(s2mps11_clks->clk_np, of_clk_hw_onecell_get,
210 clk_data); 207 clk_data);
211 208
212 platform_set_drvdata(pdev, s2mps11_clks); 209 platform_set_drvdata(pdev, s2mps11_clks);
213 210
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index fd89e771107e..02d681008401 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -136,7 +136,7 @@ static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ffull,
136 0x0000000000000001ull, 136 0x0000000000000001ull,
137 0x04777f33f6fec9ffull }; 137 0x04777f33f6fec9ffull };
138 138
139static struct clk *clks[MAX_CLKS]; 139static struct clk_hw *clks[MAX_CLKS];
140static DEFINE_SPINLOCK(stm32f4_clk_lock); 140static DEFINE_SPINLOCK(stm32f4_clk_lock);
141static void __iomem *base; 141static void __iomem *base;
142 142
@@ -281,7 +281,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
281 (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0); 281 (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
282} 282}
283 283
284static struct clk * 284static struct clk_hw *
285stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) 285stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
286{ 286{
287 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]); 287 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
@@ -346,9 +346,9 @@ static void __init stm32f4_rcc_init(struct device_node *np)
346 clk_register_apb_mul(NULL, "apb2_mul", "apb2_div", 346 clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
347 CLK_SET_RATE_PARENT, 15); 347 CLK_SET_RATE_PARENT, 15);
348 348
349 clks[SYSTICK] = clk_register_fixed_factor(NULL, "systick", "ahb_div", 349 clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
350 0, 1, 8); 350 0, 1, 8);
351 clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div", 351 clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
352 0, 1, 1); 352 0, 1, 1);
353 353
354 for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) { 354 for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) {
@@ -360,18 +360,18 @@ static void __init stm32f4_rcc_init(struct device_node *np)
360 if (idx < 0) 360 if (idx < 0)
361 goto fail; 361 goto fail;
362 362
363 clks[idx] = clk_register_gate( 363 clks[idx] = clk_hw_register_gate(
364 NULL, gd->name, gd->parent_name, gd->flags, 364 NULL, gd->name, gd->parent_name, gd->flags,
365 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); 365 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
366 366
367 if (IS_ERR(clks[n])) { 367 if (IS_ERR(clks[idx])) {
368 pr_err("%s: Unable to register leaf clock %s\n", 368 pr_err("%s: Unable to register leaf clock %s\n",
369 np->full_name, gd->name); 369 np->full_name, gd->name);
370 goto fail; 370 goto fail;
371 } 371 }
372 } 372 }
373 373
374 of_clk_add_provider(np, stm32f4_rcc_lookup_clk, NULL); 374 of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
375 return; 375 return;
376fail: 376fail:
377 iounmap(base); 377 iounmap(base);
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 95d1742dac30..ec8aafda6e24 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -689,7 +689,7 @@ static const struct clk_ops syscon_clk_ops = {
689 .set_rate = syscon_clk_set_rate, 689 .set_rate = syscon_clk_set_rate,
690}; 690};
691 691
692static struct clk * __init 692static struct clk_hw * __init
693syscon_clk_register(struct device *dev, const char *name, 693syscon_clk_register(struct device *dev, const char *name,
694 const char *parent_name, unsigned long flags, 694 const char *parent_name, unsigned long flags,
695 bool hw_ctrld, 695 bool hw_ctrld,
@@ -697,9 +697,10 @@ syscon_clk_register(struct device *dev, const char *name,
697 void __iomem *en_reg, u8 en_bit, 697 void __iomem *en_reg, u8 en_bit,
698 u16 clk_val) 698 u16 clk_val)
699{ 699{
700 struct clk *clk; 700 struct clk_hw *hw;
701 struct clk_syscon *sclk; 701 struct clk_syscon *sclk;
702 struct clk_init_data init; 702 struct clk_init_data init;
703 int ret;
703 704
704 sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL); 705 sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL);
705 if (!sclk) { 706 if (!sclk) {
@@ -722,11 +723,14 @@ syscon_clk_register(struct device *dev, const char *name,
722 sclk->en_bit = en_bit; 723 sclk->en_bit = en_bit;
723 sclk->clk_val = clk_val; 724 sclk->clk_val = clk_val;
724 725
725 clk = clk_register(dev, &sclk->hw); 726 hw = &sclk->hw;
726 if (IS_ERR(clk)) 727 ret = clk_hw_register(dev, hw);
728 if (ret) {
727 kfree(sclk); 729 kfree(sclk);
730 hw = ERR_PTR(ret);
731 }
728 732
729 return clk; 733 return hw;
730} 734}
731 735
732#define U300_CLK_TYPE_SLOW 0 736#define U300_CLK_TYPE_SLOW 0
@@ -868,7 +872,7 @@ static struct u300_clock const u300_clk_lookup[] __initconst = {
868 872
869static void __init of_u300_syscon_clk_init(struct device_node *np) 873static void __init of_u300_syscon_clk_init(struct device_node *np)
870{ 874{
871 struct clk *clk = ERR_PTR(-EINVAL); 875 struct clk_hw *hw = ERR_PTR(-EINVAL);
872 const char *clk_name = np->name; 876 const char *clk_name = np->name;
873 const char *parent_name; 877 const char *parent_name;
874 void __iomem *res_reg; 878 void __iomem *res_reg;
@@ -911,16 +915,15 @@ static void __init of_u300_syscon_clk_init(struct device_node *np)
911 const struct u300_clock *u3clk = &u300_clk_lookup[i]; 915 const struct u300_clock *u3clk = &u300_clk_lookup[i];
912 916
913 if (u3clk->type == clk_type && u3clk->id == clk_id) 917 if (u3clk->type == clk_type && u3clk->id == clk_id)
914 clk = syscon_clk_register(NULL, 918 hw = syscon_clk_register(NULL, clk_name, parent_name,
915 clk_name, parent_name, 919 0, u3clk->hw_ctrld,
916 0, u3clk->hw_ctrld, 920 res_reg, u3clk->id,
917 res_reg, u3clk->id, 921 en_reg, u3clk->id,
918 en_reg, u3clk->id, 922 u3clk->clk_val);
919 u3clk->clk_val);
920 } 923 }
921 924
922 if (!IS_ERR(clk)) { 925 if (!IS_ERR(hw)) {
923 of_clk_add_provider(np, of_clk_src_simple_get, clk); 926 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
924 927
925 /* 928 /*
926 * Some few system clocks - device tree does not 929 * Some few system clocks - device tree does not
@@ -928,11 +931,11 @@ static void __init of_u300_syscon_clk_init(struct device_node *np)
928 * for now we add these three clocks here. 931 * for now we add these three clocks here.
929 */ 932 */
930 if (clk_type == U300_CLK_TYPE_REST && clk_id == 5) 933 if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
931 clk_register_clkdev(clk, NULL, "pl172"); 934 clk_hw_register_clkdev(hw, NULL, "pl172");
932 if (clk_type == U300_CLK_TYPE_REST && clk_id == 9) 935 if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
933 clk_register_clkdev(clk, NULL, "semi"); 936 clk_hw_register_clkdev(hw, NULL, "semi");
934 if (clk_type == U300_CLK_TYPE_REST && clk_id == 12) 937 if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
935 clk_register_clkdev(clk, NULL, "intcon"); 938 clk_hw_register_clkdev(hw, NULL, "intcon");
936 } 939 }
937} 940}
938 941
@@ -1111,13 +1114,14 @@ static const struct clk_ops mclk_ops = {
1111 .set_rate = mclk_clk_set_rate, 1114 .set_rate = mclk_clk_set_rate,
1112}; 1115};
1113 1116
1114static struct clk * __init 1117static struct clk_hw * __init
1115mclk_clk_register(struct device *dev, const char *name, 1118mclk_clk_register(struct device *dev, const char *name,
1116 const char *parent_name, bool is_mspro) 1119 const char *parent_name, bool is_mspro)
1117{ 1120{
1118 struct clk *clk; 1121 struct clk_hw *hw;
1119 struct clk_mclk *mclk; 1122 struct clk_mclk *mclk;
1120 struct clk_init_data init; 1123 struct clk_init_data init;
1124 int ret;
1121 1125
1122 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL); 1126 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL);
1123 if (!mclk) { 1127 if (!mclk) {
@@ -1133,23 +1137,26 @@ mclk_clk_register(struct device *dev, const char *name,
1133 mclk->hw.init = &init; 1137 mclk->hw.init = &init;
1134 mclk->is_mspro = is_mspro; 1138 mclk->is_mspro = is_mspro;
1135 1139
1136 clk = clk_register(dev, &mclk->hw); 1140 hw = &mclk->hw;
1137 if (IS_ERR(clk)) 1141 ret = clk_hw_register(dev, hw);
1142 if (ret) {
1138 kfree(mclk); 1143 kfree(mclk);
1144 hw = ERR_PTR(ret);
1145 }
1139 1146
1140 return clk; 1147 return hw;
1141} 1148}
1142 1149
1143static void __init of_u300_syscon_mclk_init(struct device_node *np) 1150static void __init of_u300_syscon_mclk_init(struct device_node *np)
1144{ 1151{
1145 struct clk *clk = ERR_PTR(-EINVAL); 1152 struct clk_hw *hw;
1146 const char *clk_name = np->name; 1153 const char *clk_name = np->name;
1147 const char *parent_name; 1154 const char *parent_name;
1148 1155
1149 parent_name = of_clk_get_parent_name(np, 0); 1156 parent_name = of_clk_get_parent_name(np, 0);
1150 clk = mclk_clk_register(NULL, clk_name, parent_name, false); 1157 hw = mclk_clk_register(NULL, clk_name, parent_name, false);
1151 if (!IS_ERR(clk)) 1158 if (!IS_ERR(hw))
1152 of_clk_add_provider(np, of_clk_src_simple_get, clk); 1159 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
1153} 1160}
1154 1161
1155static const struct of_device_id u300_clk_match[] __initconst = { 1162static const struct of_device_id u300_clk_match[] __initconst = {
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index b0f76a84f1e9..37368a399ff9 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -383,51 +383,49 @@ static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
383 return 0; 383 return 0;
384} 384}
385 385
386static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate, 386/*
387 u32 *multiplier, u32 *divisor1, u32 *divisor2) 387 * M * parent [O1] => / P [O2] => / D [O3]
388 * Where O1 is 900MHz...3GHz;
389 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
390 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
391 * Possible ranges (O3):
392 * D = 8: 37,5MHz...75MHz
393 * D = 4: 75MHz...150MHz
394 * D = 2: 150MHz...300MHz
395 * D = 1: 300MHz...600MHz
396 */
397static int wm8650_find_pll_bits(unsigned long rate,
398 unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
399 u32 *divisor2)
388{ 400{
389 u32 mul, div1; 401 unsigned long O1, min_err, rate_err;
390 int div2;
391 u32 best_mul, best_div1, best_div2;
392 unsigned long tclk, rate_err, best_err;
393
394 best_err = (unsigned long)-1;
395 402
396 /* Find the closest match (lower or equal to requested) */ 403 if (!parent_rate || (rate < 37500000) || (rate > 600000000))
397 for (div1 = 5; div1 >= 3; div1--) 404 return -EINVAL;
398 for (div2 = 3; div2 >= 0; div2--)
399 for (mul = 3; mul <= 1023; mul++) {
400 tclk = parent_rate * mul / (div1 * (1 << div2));
401 if (tclk > rate)
402 continue;
403 /* error will always be +ve */
404 rate_err = rate - tclk;
405 if (rate_err == 0) {
406 *multiplier = mul;
407 *divisor1 = div1;
408 *divisor2 = div2;
409 return 0;
410 }
411 405
412 if (rate_err < best_err) { 406 *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
413 best_err = rate_err; 407 rate <= 300000000 ? 1 : 0;
414 best_mul = mul; 408 /*
415 best_div1 = div1; 409 * Divisor P cannot be calculated. Test all divisors and find where M
416 best_div2 = div2; 410 * will be as close as possible to the requested rate.
417 } 411 */
418 } 412 min_err = ULONG_MAX;
413 for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
414 O1 = rate * *divisor1 * (1 << (*divisor2));
415 rate_err = O1 % parent_rate;
416 if (rate_err < min_err) {
417 *multiplier = O1 / parent_rate;
418 if (rate_err == 0)
419 return 0;
420
421 min_err = rate_err;
422 }
423 }
419 424
420 if (best_err == (unsigned long)-1) { 425 if ((*multiplier < 3) || (*multiplier > 1023))
421 pr_warn("%s: impossible rate %lu\n", __func__, rate);
422 return -EINVAL; 426 return -EINVAL;
423 }
424 427
425 /* if we got here, it wasn't an exact match */ 428 pr_warn("%s: rate error is %lu\n", __func__, min_err);
426 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
427 rate - best_err);
428 *multiplier = best_mul;
429 *divisor1 = best_div1;
430 *divisor2 = best_div2;
431 429
432 return 0; 430 return 0;
433} 431}
@@ -464,7 +462,6 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
464{ 462{
465 u32 mul; 463 u32 mul;
466 int div1, div2; 464 int div1, div2;
467 u32 best_mul, best_div1, best_div2;
468 unsigned long tclk, rate_err, best_err; 465 unsigned long tclk, rate_err, best_err;
469 466
470 best_err = (unsigned long)-1; 467 best_err = (unsigned long)-1;
@@ -488,9 +485,9 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
488 485
489 if (rate_err < best_err) { 486 if (rate_err < best_err) {
490 best_err = rate_err; 487 best_err = rate_err;
491 best_mul = mul; 488 *multiplier = mul;
492 best_div1 = div1; 489 *divisor1 = div1;
493 best_div2 = div2; 490 *divisor2 = div2;
494 } 491 }
495 } 492 }
496 493
@@ -503,10 +500,7 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
503 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 500 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
504 rate - best_err); 501 rate - best_err);
505 502
506 *filter = wm8750_get_filter(parent_rate, best_div1); 503 *filter = wm8750_get_filter(parent_rate, *divisor1);
507 *multiplier = best_mul;
508 *divisor1 = best_div1;
509 *divisor2 = best_div2;
510 504
511 return 0; 505 return 0;
512} 506}
@@ -516,7 +510,6 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
516{ 510{
517 u32 mul; 511 u32 mul;
518 int div1, div2; 512 int div1, div2;
519 u32 best_mul, best_div1, best_div2;
520 unsigned long tclk, rate_err, best_err; 513 unsigned long tclk, rate_err, best_err;
521 514
522 best_err = (unsigned long)-1; 515 best_err = (unsigned long)-1;
@@ -540,9 +533,9 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
540 533
541 if (rate_err < best_err) { 534 if (rate_err < best_err) {
542 best_err = rate_err; 535 best_err = rate_err;
543 best_mul = mul; 536 *multiplier = mul;
544 best_div1 = div1; 537 *divisor1 = div1;
545 best_div2 = div2; 538 *divisor2 = div2;
546 } 539 }
547 } 540 }
548 541
@@ -555,10 +548,6 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
555 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 548 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
556 rate - best_err); 549 rate - best_err);
557 550
558 *multiplier = best_mul;
559 *divisor1 = best_div1;
560 *divisor2 = best_div2;
561
562 return 0; 551 return 0;
563} 552}
564 553
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index d584004f7af7..820a939fb6bb 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -172,104 +172,6 @@ static bool clk_core_is_enabled(struct clk_core *core)
172 return core->ops->is_enabled(core->hw); 172 return core->ops->is_enabled(core->hw);
173} 173}
174 174
175static void clk_unprepare_unused_subtree(struct clk_core *core)
176{
177 struct clk_core *child;
178
179 lockdep_assert_held(&prepare_lock);
180
181 hlist_for_each_entry(child, &core->children, child_node)
182 clk_unprepare_unused_subtree(child);
183
184 if (core->prepare_count)
185 return;
186
187 if (core->flags & CLK_IGNORE_UNUSED)
188 return;
189
190 if (clk_core_is_prepared(core)) {
191 trace_clk_unprepare(core);
192 if (core->ops->unprepare_unused)
193 core->ops->unprepare_unused(core->hw);
194 else if (core->ops->unprepare)
195 core->ops->unprepare(core->hw);
196 trace_clk_unprepare_complete(core);
197 }
198}
199
200static void clk_disable_unused_subtree(struct clk_core *core)
201{
202 struct clk_core *child;
203 unsigned long flags;
204
205 lockdep_assert_held(&prepare_lock);
206
207 hlist_for_each_entry(child, &core->children, child_node)
208 clk_disable_unused_subtree(child);
209
210 flags = clk_enable_lock();
211
212 if (core->enable_count)
213 goto unlock_out;
214
215 if (core->flags & CLK_IGNORE_UNUSED)
216 goto unlock_out;
217
218 /*
219 * some gate clocks have special needs during the disable-unused
220 * sequence. call .disable_unused if available, otherwise fall
221 * back to .disable
222 */
223 if (clk_core_is_enabled(core)) {
224 trace_clk_disable(core);
225 if (core->ops->disable_unused)
226 core->ops->disable_unused(core->hw);
227 else if (core->ops->disable)
228 core->ops->disable(core->hw);
229 trace_clk_disable_complete(core);
230 }
231
232unlock_out:
233 clk_enable_unlock(flags);
234}
235
236static bool clk_ignore_unused;
237static int __init clk_ignore_unused_setup(char *__unused)
238{
239 clk_ignore_unused = true;
240 return 1;
241}
242__setup("clk_ignore_unused", clk_ignore_unused_setup);
243
244static int clk_disable_unused(void)
245{
246 struct clk_core *core;
247
248 if (clk_ignore_unused) {
249 pr_warn("clk: Not disabling unused clocks\n");
250 return 0;
251 }
252
253 clk_prepare_lock();
254
255 hlist_for_each_entry(core, &clk_root_list, child_node)
256 clk_disable_unused_subtree(core);
257
258 hlist_for_each_entry(core, &clk_orphan_list, child_node)
259 clk_disable_unused_subtree(core);
260
261 hlist_for_each_entry(core, &clk_root_list, child_node)
262 clk_unprepare_unused_subtree(core);
263
264 hlist_for_each_entry(core, &clk_orphan_list, child_node)
265 clk_unprepare_unused_subtree(core);
266
267 clk_prepare_unlock();
268
269 return 0;
270}
271late_initcall_sync(clk_disable_unused);
272
273/*** helper functions ***/ 175/*** helper functions ***/
274 176
275const char *__clk_get_name(const struct clk *clk) 177const char *__clk_get_name(const struct clk *clk)
@@ -591,6 +493,13 @@ static void clk_core_unprepare(struct clk_core *core)
591 clk_core_unprepare(core->parent); 493 clk_core_unprepare(core->parent);
592} 494}
593 495
496static void clk_core_unprepare_lock(struct clk_core *core)
497{
498 clk_prepare_lock();
499 clk_core_unprepare(core);
500 clk_prepare_unlock();
501}
502
594/** 503/**
595 * clk_unprepare - undo preparation of a clock source 504 * clk_unprepare - undo preparation of a clock source
596 * @clk: the clk being unprepared 505 * @clk: the clk being unprepared
@@ -607,9 +516,7 @@ void clk_unprepare(struct clk *clk)
607 if (IS_ERR_OR_NULL(clk)) 516 if (IS_ERR_OR_NULL(clk))
608 return; 517 return;
609 518
610 clk_prepare_lock(); 519 clk_core_unprepare_lock(clk->core);
611 clk_core_unprepare(clk->core);
612 clk_prepare_unlock();
613} 520}
614EXPORT_SYMBOL_GPL(clk_unprepare); 521EXPORT_SYMBOL_GPL(clk_unprepare);
615 522
@@ -645,6 +552,17 @@ static int clk_core_prepare(struct clk_core *core)
645 return 0; 552 return 0;
646} 553}
647 554
555static int clk_core_prepare_lock(struct clk_core *core)
556{
557 int ret;
558
559 clk_prepare_lock();
560 ret = clk_core_prepare(core);
561 clk_prepare_unlock();
562
563 return ret;
564}
565
648/** 566/**
649 * clk_prepare - prepare a clock source 567 * clk_prepare - prepare a clock source
650 * @clk: the clk being prepared 568 * @clk: the clk being prepared
@@ -659,16 +577,10 @@ static int clk_core_prepare(struct clk_core *core)
659 */ 577 */
660int clk_prepare(struct clk *clk) 578int clk_prepare(struct clk *clk)
661{ 579{
662 int ret;
663
664 if (!clk) 580 if (!clk)
665 return 0; 581 return 0;
666 582
667 clk_prepare_lock(); 583 return clk_core_prepare_lock(clk->core);
668 ret = clk_core_prepare(clk->core);
669 clk_prepare_unlock();
670
671 return ret;
672} 584}
673EXPORT_SYMBOL_GPL(clk_prepare); 585EXPORT_SYMBOL_GPL(clk_prepare);
674 586
@@ -688,16 +600,25 @@ static void clk_core_disable(struct clk_core *core)
688 if (--core->enable_count > 0) 600 if (--core->enable_count > 0)
689 return; 601 return;
690 602
691 trace_clk_disable(core); 603 trace_clk_disable_rcuidle(core);
692 604
693 if (core->ops->disable) 605 if (core->ops->disable)
694 core->ops->disable(core->hw); 606 core->ops->disable(core->hw);
695 607
696 trace_clk_disable_complete(core); 608 trace_clk_disable_complete_rcuidle(core);
697 609
698 clk_core_disable(core->parent); 610 clk_core_disable(core->parent);
699} 611}
700 612
613static void clk_core_disable_lock(struct clk_core *core)
614{
615 unsigned long flags;
616
617 flags = clk_enable_lock();
618 clk_core_disable(core);
619 clk_enable_unlock(flags);
620}
621
701/** 622/**
702 * clk_disable - gate a clock 623 * clk_disable - gate a clock
703 * @clk: the clk being gated 624 * @clk: the clk being gated
@@ -712,14 +633,10 @@ static void clk_core_disable(struct clk_core *core)
712 */ 633 */
713void clk_disable(struct clk *clk) 634void clk_disable(struct clk *clk)
714{ 635{
715 unsigned long flags;
716
717 if (IS_ERR_OR_NULL(clk)) 636 if (IS_ERR_OR_NULL(clk))
718 return; 637 return;
719 638
720 flags = clk_enable_lock(); 639 clk_core_disable_lock(clk->core);
721 clk_core_disable(clk->core);
722 clk_enable_unlock(flags);
723} 640}
724EXPORT_SYMBOL_GPL(clk_disable); 641EXPORT_SYMBOL_GPL(clk_disable);
725 642
@@ -741,12 +658,12 @@ static int clk_core_enable(struct clk_core *core)
741 if (ret) 658 if (ret)
742 return ret; 659 return ret;
743 660
744 trace_clk_enable(core); 661 trace_clk_enable_rcuidle(core);
745 662
746 if (core->ops->enable) 663 if (core->ops->enable)
747 ret = core->ops->enable(core->hw); 664 ret = core->ops->enable(core->hw);
748 665
749 trace_clk_enable_complete(core); 666 trace_clk_enable_complete_rcuidle(core);
750 667
751 if (ret) { 668 if (ret) {
752 clk_core_disable(core->parent); 669 clk_core_disable(core->parent);
@@ -758,6 +675,18 @@ static int clk_core_enable(struct clk_core *core)
758 return 0; 675 return 0;
759} 676}
760 677
678static int clk_core_enable_lock(struct clk_core *core)
679{
680 unsigned long flags;
681 int ret;
682
683 flags = clk_enable_lock();
684 ret = clk_core_enable(core);
685 clk_enable_unlock(flags);
686
687 return ret;
688}
689
761/** 690/**
762 * clk_enable - ungate a clock 691 * clk_enable - ungate a clock
763 * @clk: the clk being ungated 692 * @clk: the clk being ungated
@@ -773,19 +702,136 @@ static int clk_core_enable(struct clk_core *core)
773 */ 702 */
774int clk_enable(struct clk *clk) 703int clk_enable(struct clk *clk)
775{ 704{
776 unsigned long flags;
777 int ret;
778
779 if (!clk) 705 if (!clk)
780 return 0; 706 return 0;
781 707
708 return clk_core_enable_lock(clk->core);
709}
710EXPORT_SYMBOL_GPL(clk_enable);
711
712static int clk_core_prepare_enable(struct clk_core *core)
713{
714 int ret;
715
716 ret = clk_core_prepare_lock(core);
717 if (ret)
718 return ret;
719
720 ret = clk_core_enable_lock(core);
721 if (ret)
722 clk_core_unprepare_lock(core);
723
724 return ret;
725}
726
727static void clk_core_disable_unprepare(struct clk_core *core)
728{
729 clk_core_disable_lock(core);
730 clk_core_unprepare_lock(core);
731}
732
733static void clk_unprepare_unused_subtree(struct clk_core *core)
734{
735 struct clk_core *child;
736
737 lockdep_assert_held(&prepare_lock);
738
739 hlist_for_each_entry(child, &core->children, child_node)
740 clk_unprepare_unused_subtree(child);
741
742 if (core->prepare_count)
743 return;
744
745 if (core->flags & CLK_IGNORE_UNUSED)
746 return;
747
748 if (clk_core_is_prepared(core)) {
749 trace_clk_unprepare(core);
750 if (core->ops->unprepare_unused)
751 core->ops->unprepare_unused(core->hw);
752 else if (core->ops->unprepare)
753 core->ops->unprepare(core->hw);
754 trace_clk_unprepare_complete(core);
755 }
756}
757
758static void clk_disable_unused_subtree(struct clk_core *core)
759{
760 struct clk_core *child;
761 unsigned long flags;
762
763 lockdep_assert_held(&prepare_lock);
764
765 hlist_for_each_entry(child, &core->children, child_node)
766 clk_disable_unused_subtree(child);
767
768 if (core->flags & CLK_OPS_PARENT_ENABLE)
769 clk_core_prepare_enable(core->parent);
770
782 flags = clk_enable_lock(); 771 flags = clk_enable_lock();
783 ret = clk_core_enable(clk->core); 772
773 if (core->enable_count)
774 goto unlock_out;
775
776 if (core->flags & CLK_IGNORE_UNUSED)
777 goto unlock_out;
778
779 /*
780 * some gate clocks have special needs during the disable-unused
781 * sequence. call .disable_unused if available, otherwise fall
782 * back to .disable
783 */
784 if (clk_core_is_enabled(core)) {
785 trace_clk_disable(core);
786 if (core->ops->disable_unused)
787 core->ops->disable_unused(core->hw);
788 else if (core->ops->disable)
789 core->ops->disable(core->hw);
790 trace_clk_disable_complete(core);
791 }
792
793unlock_out:
784 clk_enable_unlock(flags); 794 clk_enable_unlock(flags);
795 if (core->flags & CLK_OPS_PARENT_ENABLE)
796 clk_core_disable_unprepare(core->parent);
797}
785 798
786 return ret; 799static bool clk_ignore_unused;
800static int __init clk_ignore_unused_setup(char *__unused)
801{
802 clk_ignore_unused = true;
803 return 1;
787} 804}
788EXPORT_SYMBOL_GPL(clk_enable); 805__setup("clk_ignore_unused", clk_ignore_unused_setup);
806
807static int clk_disable_unused(void)
808{
809 struct clk_core *core;
810
811 if (clk_ignore_unused) {
812 pr_warn("clk: Not disabling unused clocks\n");
813 return 0;
814 }
815
816 clk_prepare_lock();
817
818 hlist_for_each_entry(core, &clk_root_list, child_node)
819 clk_disable_unused_subtree(core);
820
821 hlist_for_each_entry(core, &clk_orphan_list, child_node)
822 clk_disable_unused_subtree(core);
823
824 hlist_for_each_entry(core, &clk_root_list, child_node)
825 clk_unprepare_unused_subtree(core);
826
827 hlist_for_each_entry(core, &clk_orphan_list, child_node)
828 clk_unprepare_unused_subtree(core);
829
830 clk_prepare_unlock();
831
832 return 0;
833}
834late_initcall_sync(clk_disable_unused);
789 835
790static int clk_core_round_rate_nolock(struct clk_core *core, 836static int clk_core_round_rate_nolock(struct clk_core *core,
791 struct clk_rate_request *req) 837 struct clk_rate_request *req)
@@ -828,9 +874,7 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
828/** 874/**
829 * __clk_determine_rate - get the closest rate actually supported by a clock 875 * __clk_determine_rate - get the closest rate actually supported by a clock
830 * @hw: determine the rate of this clock 876 * @hw: determine the rate of this clock
831 * @rate: target rate 877 * @req: target rate request
832 * @min_rate: returned rate must be greater than this rate
833 * @max_rate: returned rate must be less than this rate
834 * 878 *
835 * Useful for clk_ops such as .set_rate and .determine_rate. 879 * Useful for clk_ops such as .set_rate and .determine_rate.
836 */ 880 */
@@ -1128,7 +1172,9 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1128 struct clk_core *old_parent = core->parent; 1172 struct clk_core *old_parent = core->parent;
1129 1173
1130 /* 1174 /*
1131 * Migrate prepare state between parents and prevent race with 1175 * 1. enable parents for CLK_OPS_PARENT_ENABLE clock
1176 *
1177 * 2. Migrate prepare state between parents and prevent race with
1132 * clk_enable(). 1178 * clk_enable().
1133 * 1179 *
1134 * If the clock is not prepared, then a race with 1180 * If the clock is not prepared, then a race with
@@ -1144,12 +1190,17 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1144 * 1190 *
1145 * See also: Comment for clk_set_parent() below. 1191 * See also: Comment for clk_set_parent() below.
1146 */ 1192 */
1193
1194 /* enable old_parent & parent if CLK_OPS_PARENT_ENABLE is set */
1195 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1196 clk_core_prepare_enable(old_parent);
1197 clk_core_prepare_enable(parent);
1198 }
1199
1200 /* migrate prepare count if > 0 */
1147 if (core->prepare_count) { 1201 if (core->prepare_count) {
1148 clk_core_prepare(parent); 1202 clk_core_prepare_enable(parent);
1149 flags = clk_enable_lock(); 1203 clk_core_enable_lock(core);
1150 clk_core_enable(parent);
1151 clk_core_enable(core);
1152 clk_enable_unlock(flags);
1153 } 1204 }
1154 1205
1155 /* update the clk tree topology */ 1206 /* update the clk tree topology */
@@ -1164,18 +1215,19 @@ static void __clk_set_parent_after(struct clk_core *core,
1164 struct clk_core *parent, 1215 struct clk_core *parent,
1165 struct clk_core *old_parent) 1216 struct clk_core *old_parent)
1166{ 1217{
1167 unsigned long flags;
1168
1169 /* 1218 /*
1170 * Finish the migration of prepare state and undo the changes done 1219 * Finish the migration of prepare state and undo the changes done
1171 * for preventing a race with clk_enable(). 1220 * for preventing a race with clk_enable().
1172 */ 1221 */
1173 if (core->prepare_count) { 1222 if (core->prepare_count) {
1174 flags = clk_enable_lock(); 1223 clk_core_disable_lock(core);
1175 clk_core_disable(core); 1224 clk_core_disable_unprepare(old_parent);
1176 clk_core_disable(old_parent); 1225 }
1177 clk_enable_unlock(flags); 1226
1178 clk_core_unprepare(old_parent); 1227 /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */
1228 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1229 clk_core_disable_unprepare(parent);
1230 clk_core_disable_unprepare(old_parent);
1179 } 1231 }
1180} 1232}
1181 1233
@@ -1422,13 +1474,17 @@ static void clk_change_rate(struct clk_core *core)
1422 unsigned long best_parent_rate = 0; 1474 unsigned long best_parent_rate = 0;
1423 bool skip_set_rate = false; 1475 bool skip_set_rate = false;
1424 struct clk_core *old_parent; 1476 struct clk_core *old_parent;
1477 struct clk_core *parent = NULL;
1425 1478
1426 old_rate = core->rate; 1479 old_rate = core->rate;
1427 1480
1428 if (core->new_parent) 1481 if (core->new_parent) {
1482 parent = core->new_parent;
1429 best_parent_rate = core->new_parent->rate; 1483 best_parent_rate = core->new_parent->rate;
1430 else if (core->parent) 1484 } else if (core->parent) {
1485 parent = core->parent;
1431 best_parent_rate = core->parent->rate; 1486 best_parent_rate = core->parent->rate;
1487 }
1432 1488
1433 if (core->flags & CLK_SET_RATE_UNGATE) { 1489 if (core->flags & CLK_SET_RATE_UNGATE) {
1434 unsigned long flags; 1490 unsigned long flags;
@@ -1456,6 +1512,9 @@ static void clk_change_rate(struct clk_core *core)
1456 __clk_set_parent_after(core, core->new_parent, old_parent); 1512 __clk_set_parent_after(core, core->new_parent, old_parent);
1457 } 1513 }
1458 1514
1515 if (core->flags & CLK_OPS_PARENT_ENABLE)
1516 clk_core_prepare_enable(parent);
1517
1459 trace_clk_set_rate(core, core->new_rate); 1518 trace_clk_set_rate(core, core->new_rate);
1460 1519
1461 if (!skip_set_rate && core->ops->set_rate) 1520 if (!skip_set_rate && core->ops->set_rate)
@@ -1474,6 +1533,9 @@ static void clk_change_rate(struct clk_core *core)
1474 clk_core_unprepare(core); 1533 clk_core_unprepare(core);
1475 } 1534 }
1476 1535
1536 if (core->flags & CLK_OPS_PARENT_ENABLE)
1537 clk_core_disable_unprepare(parent);
1538
1477 if (core->notifier_count && old_rate != core->rate) 1539 if (core->notifier_count && old_rate != core->rate)
1478 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate); 1540 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
1479 1541
@@ -1501,7 +1563,6 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
1501{ 1563{
1502 struct clk_core *top, *fail_clk; 1564 struct clk_core *top, *fail_clk;
1503 unsigned long rate = req_rate; 1565 unsigned long rate = req_rate;
1504 int ret = 0;
1505 1566
1506 if (!core) 1567 if (!core)
1507 return 0; 1568 return 0;
@@ -1532,7 +1593,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
1532 1593
1533 core->req_rate = req_rate; 1594 core->req_rate = req_rate;
1534 1595
1535 return ret; 1596 return 0;
1536} 1597}
1537 1598
1538/** 1599/**
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
index 715c7301a66a..51b173ef1dda 100644
--- a/drivers/clk/hisilicon/clk-hi3519.c
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -38,6 +38,11 @@
38 38
39#define HI3519_NR_CLKS 128 39#define HI3519_NR_CLKS 128
40 40
41struct hi3519_crg_data {
42 struct hisi_clock_data *clk_data;
43 struct hisi_reset_controller *rstc;
44};
45
41static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = { 46static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
42 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, }, 47 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
43 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, }, 48 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
@@ -80,33 +85,105 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = {
80 CLK_SET_RATE_PARENT, 0xe4, 18, 0, }, 85 CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
81}; 86};
82 87
83static int hi3519_clk_probe(struct platform_device *pdev) 88static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)
84{ 89{
85 struct device_node *np = pdev->dev.of_node;
86 struct hisi_clock_data *clk_data; 90 struct hisi_clock_data *clk_data;
87 struct hisi_reset_controller *rstc; 91 int ret;
88 92
89 rstc = hisi_reset_init(np); 93 clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS);
90 if (!rstc) 94 if (!clk_data)
95 return ERR_PTR(-ENOMEM);
96
97 ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
98 ARRAY_SIZE(hi3519_fixed_rate_clks),
99 clk_data);
100 if (ret)
101 return ERR_PTR(ret);
102
103 ret = hisi_clk_register_mux(hi3519_mux_clks,
104 ARRAY_SIZE(hi3519_mux_clks),
105 clk_data);
106 if (ret)
107 goto unregister_fixed_rate;
108
109 ret = hisi_clk_register_gate(hi3519_gate_clks,
110 ARRAY_SIZE(hi3519_gate_clks),
111 clk_data);
112 if (ret)
113 goto unregister_mux;
114
115 ret = of_clk_add_provider(pdev->dev.of_node,
116 of_clk_src_onecell_get, &clk_data->clk_data);
117 if (ret)
118 goto unregister_gate;
119
120 return clk_data;
121
122unregister_fixed_rate:
123 hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
124 ARRAY_SIZE(hi3519_fixed_rate_clks),
125 clk_data);
126
127unregister_mux:
128 hisi_clk_unregister_mux(hi3519_mux_clks,
129 ARRAY_SIZE(hi3519_mux_clks),
130 clk_data);
131unregister_gate:
132 hisi_clk_unregister_gate(hi3519_gate_clks,
133 ARRAY_SIZE(hi3519_gate_clks),
134 clk_data);
135 return ERR_PTR(ret);
136}
137
138static void hi3519_clk_unregister(struct platform_device *pdev)
139{
140 struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
141
142 of_clk_del_provider(pdev->dev.of_node);
143
144 hisi_clk_unregister_gate(hi3519_gate_clks,
145 ARRAY_SIZE(hi3519_mux_clks),
146 crg->clk_data);
147 hisi_clk_unregister_mux(hi3519_mux_clks,
148 ARRAY_SIZE(hi3519_mux_clks),
149 crg->clk_data);
150 hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
151 ARRAY_SIZE(hi3519_fixed_rate_clks),
152 crg->clk_data);
153}
154
155static int hi3519_clk_probe(struct platform_device *pdev)
156{
157 struct hi3519_crg_data *crg;
158
159 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
160 if (!crg)
161 return -ENOMEM;
162
163 crg->rstc = hisi_reset_init(pdev);
164 if (!crg->rstc)
91 return -ENOMEM; 165 return -ENOMEM;
92 166
93 clk_data = hisi_clk_init(np, HI3519_NR_CLKS); 167 crg->clk_data = hi3519_clk_register(pdev);
94 if (!clk_data) { 168 if (IS_ERR(crg->clk_data)) {
95 hisi_reset_exit(rstc); 169 hisi_reset_exit(crg->rstc);
96 return -ENODEV; 170 return PTR_ERR(crg->clk_data);
97 } 171 }
98 172
99 hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks, 173 platform_set_drvdata(pdev, crg);
100 ARRAY_SIZE(hi3519_fixed_rate_clks), 174 return 0;
101 clk_data); 175}
102 hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks), 176
103 clk_data); 177static int hi3519_clk_remove(struct platform_device *pdev)
104 hisi_clk_register_gate(hi3519_gate_clks, 178{
105 ARRAY_SIZE(hi3519_gate_clks), clk_data); 179 struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
106 180
181 hisi_reset_exit(crg->rstc);
182 hi3519_clk_unregister(pdev);
107 return 0; 183 return 0;
108} 184}
109 185
186
110static const struct of_device_id hi3519_clk_match_table[] = { 187static const struct of_device_id hi3519_clk_match_table[] = {
111 { .compatible = "hisilicon,hi3519-crg" }, 188 { .compatible = "hisilicon,hi3519-crg" },
112 { } 189 { }
@@ -115,6 +192,7 @@ MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
115 192
116static struct platform_driver hi3519_clk_driver = { 193static struct platform_driver hi3519_clk_driver = {
117 .probe = hi3519_clk_probe, 194 .probe = hi3519_clk_probe,
195 .remove = hi3519_clk_remove,
118 .driver = { 196 .driver = {
119 .name = "hi3519-clk", 197 .name = "hi3519-clk",
120 .of_match_table = hi3519_clk_match_table, 198 .of_match_table = hi3519_clk_match_table,
@@ -127,5 +205,11 @@ static int __init hi3519_clk_init(void)
127} 205}
128core_initcall(hi3519_clk_init); 206core_initcall(hi3519_clk_init);
129 207
208static void __exit hi3519_clk_exit(void)
209{
210 platform_driver_unregister(&hi3519_clk_driver);
211}
212module_exit(hi3519_clk_exit);
213
130MODULE_LICENSE("GPL v2"); 214MODULE_LICENSE("GPL v2");
131MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver"); 215MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index f02cb41d40a4..fe364e63f8de 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -34,8 +34,8 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
34 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, }, 34 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, },
35 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,}, 35 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,},
36 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,}, 36 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,},
37 { HI6220_PLL_SYS, "syspll", NULL, 0, 1200000000,}, 37 { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,},
38 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1200000000,}, 38 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,},
39 { HI6220_DDR_SRC, "ddr_sel_src", NULL, 0, 1200000000,}, 39 { HI6220_DDR_SRC, "ddr_sel_src", NULL, 0, 1200000000,},
40 { HI6220_PLL_MEDIA, "media_pll", NULL, 0, 1440000000,}, 40 { HI6220_PLL_MEDIA, "media_pll", NULL, 0, 1440000000,},
41 { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,}, 41 { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,},
@@ -68,6 +68,8 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
68 { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, }, 68 { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
69 { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, }, 69 { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
70 { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, }, 70 { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
71 { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, },
72 { HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
71}; 73};
72 74
73static void __init hi6220_clk_ao_init(struct device_node *np) 75static void __init hi6220_clk_ao_init(struct device_node *np)
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 9b15adbfc30c..9ba2d91f4d3a 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -37,6 +37,35 @@
37 37
38static DEFINE_SPINLOCK(hisi_clk_lock); 38static DEFINE_SPINLOCK(hisi_clk_lock);
39 39
40struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev,
41 int nr_clks)
42{
43 struct hisi_clock_data *clk_data;
44 struct resource *res;
45 struct clk **clk_table;
46
47 clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
48 if (!clk_data)
49 return NULL;
50
51 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
52 clk_data->base = devm_ioremap(&pdev->dev,
53 res->start, resource_size(res));
54 if (!clk_data->base)
55 return NULL;
56
57 clk_table = devm_kmalloc(&pdev->dev, sizeof(struct clk *) * nr_clks,
58 GFP_KERNEL);
59 if (!clk_table)
60 return NULL;
61
62 clk_data->clk_data.clks = clk_table;
63 clk_data->clk_data.clk_num = nr_clks;
64
65 return clk_data;
66}
67EXPORT_SYMBOL_GPL(hisi_clk_alloc);
68
40struct hisi_clock_data *hisi_clk_init(struct device_node *np, 69struct hisi_clock_data *hisi_clk_init(struct device_node *np,
41 int nr_clks) 70 int nr_clks)
42{ 71{
@@ -73,7 +102,7 @@ err:
73} 102}
74EXPORT_SYMBOL_GPL(hisi_clk_init); 103EXPORT_SYMBOL_GPL(hisi_clk_init);
75 104
76void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, 105int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
77 int nums, struct hisi_clock_data *data) 106 int nums, struct hisi_clock_data *data)
78{ 107{
79 struct clk *clk; 108 struct clk *clk;
@@ -87,14 +116,22 @@ void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
87 if (IS_ERR(clk)) { 116 if (IS_ERR(clk)) {
88 pr_err("%s: failed to register clock %s\n", 117 pr_err("%s: failed to register clock %s\n",
89 __func__, clks[i].name); 118 __func__, clks[i].name);
90 continue; 119 goto err;
91 } 120 }
92 data->clk_data.clks[clks[i].id] = clk; 121 data->clk_data.clks[clks[i].id] = clk;
93 } 122 }
123
124 return 0;
125
126err:
127 while (i--)
128 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]);
129
130 return PTR_ERR(clk);
94} 131}
95EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate); 132EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate);
96 133
97void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, 134int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
98 int nums, 135 int nums,
99 struct hisi_clock_data *data) 136 struct hisi_clock_data *data)
100{ 137{
@@ -109,14 +146,22 @@ void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
109 if (IS_ERR(clk)) { 146 if (IS_ERR(clk)) {
110 pr_err("%s: failed to register clock %s\n", 147 pr_err("%s: failed to register clock %s\n",
111 __func__, clks[i].name); 148 __func__, clks[i].name);
112 continue; 149 goto err;
113 } 150 }
114 data->clk_data.clks[clks[i].id] = clk; 151 data->clk_data.clks[clks[i].id] = clk;
115 } 152 }
153
154 return 0;
155
156err:
157 while (i--)
158 clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]);
159
160 return PTR_ERR(clk);
116} 161}
117EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor); 162EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor);
118 163
119void hisi_clk_register_mux(const struct hisi_mux_clock *clks, 164int hisi_clk_register_mux(const struct hisi_mux_clock *clks,
120 int nums, struct hisi_clock_data *data) 165 int nums, struct hisi_clock_data *data)
121{ 166{
122 struct clk *clk; 167 struct clk *clk;
@@ -135,7 +180,7 @@ void hisi_clk_register_mux(const struct hisi_mux_clock *clks,
135 if (IS_ERR(clk)) { 180 if (IS_ERR(clk)) {
136 pr_err("%s: failed to register clock %s\n", 181 pr_err("%s: failed to register clock %s\n",
137 __func__, clks[i].name); 182 __func__, clks[i].name);
138 continue; 183 goto err;
139 } 184 }
140 185
141 if (clks[i].alias) 186 if (clks[i].alias)
@@ -143,10 +188,18 @@ void hisi_clk_register_mux(const struct hisi_mux_clock *clks,
143 188
144 data->clk_data.clks[clks[i].id] = clk; 189 data->clk_data.clks[clks[i].id] = clk;
145 } 190 }
191
192 return 0;
193
194err:
195 while (i--)
196 clk_unregister_mux(data->clk_data.clks[clks[i].id]);
197
198 return PTR_ERR(clk);
146} 199}
147EXPORT_SYMBOL_GPL(hisi_clk_register_mux); 200EXPORT_SYMBOL_GPL(hisi_clk_register_mux);
148 201
149void hisi_clk_register_divider(const struct hisi_divider_clock *clks, 202int hisi_clk_register_divider(const struct hisi_divider_clock *clks,
150 int nums, struct hisi_clock_data *data) 203 int nums, struct hisi_clock_data *data)
151{ 204{
152 struct clk *clk; 205 struct clk *clk;
@@ -165,7 +218,7 @@ void hisi_clk_register_divider(const struct hisi_divider_clock *clks,
165 if (IS_ERR(clk)) { 218 if (IS_ERR(clk)) {
166 pr_err("%s: failed to register clock %s\n", 219 pr_err("%s: failed to register clock %s\n",
167 __func__, clks[i].name); 220 __func__, clks[i].name);
168 continue; 221 goto err;
169 } 222 }
170 223
171 if (clks[i].alias) 224 if (clks[i].alias)
@@ -173,10 +226,18 @@ void hisi_clk_register_divider(const struct hisi_divider_clock *clks,
173 226
174 data->clk_data.clks[clks[i].id] = clk; 227 data->clk_data.clks[clks[i].id] = clk;
175 } 228 }
229
230 return 0;
231
232err:
233 while (i--)
234 clk_unregister_divider(data->clk_data.clks[clks[i].id]);
235
236 return PTR_ERR(clk);
176} 237}
177EXPORT_SYMBOL_GPL(hisi_clk_register_divider); 238EXPORT_SYMBOL_GPL(hisi_clk_register_divider);
178 239
179void hisi_clk_register_gate(const struct hisi_gate_clock *clks, 240int hisi_clk_register_gate(const struct hisi_gate_clock *clks,
180 int nums, struct hisi_clock_data *data) 241 int nums, struct hisi_clock_data *data)
181{ 242{
182 struct clk *clk; 243 struct clk *clk;
@@ -194,7 +255,7 @@ void hisi_clk_register_gate(const struct hisi_gate_clock *clks,
194 if (IS_ERR(clk)) { 255 if (IS_ERR(clk)) {
195 pr_err("%s: failed to register clock %s\n", 256 pr_err("%s: failed to register clock %s\n",
196 __func__, clks[i].name); 257 __func__, clks[i].name);
197 continue; 258 goto err;
198 } 259 }
199 260
200 if (clks[i].alias) 261 if (clks[i].alias)
@@ -202,6 +263,14 @@ void hisi_clk_register_gate(const struct hisi_gate_clock *clks,
202 263
203 data->clk_data.clks[clks[i].id] = clk; 264 data->clk_data.clks[clks[i].id] = clk;
204 } 265 }
266
267 return 0;
268
269err:
270 while (i--)
271 clk_unregister_gate(data->clk_data.clks[clks[i].id]);
272
273 return PTR_ERR(clk);
205} 274}
206EXPORT_SYMBOL_GPL(hisi_clk_register_gate); 275EXPORT_SYMBOL_GPL(hisi_clk_register_gate);
207 276
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
index 20d64afe4ad8..4e1d1affc6f5 100644
--- a/drivers/clk/hisilicon/clk.h
+++ b/drivers/clk/hisilicon/clk.h
@@ -30,6 +30,8 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/spinlock.h> 31#include <linux/spinlock.h>
32 32
33struct platform_device;
34
33struct hisi_clock_data { 35struct hisi_clock_data {
34 struct clk_onecell_data clk_data; 36 struct clk_onecell_data clk_data;
35 void __iomem *base; 37 void __iomem *base;
@@ -110,19 +112,41 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
110 const char *parent_name, unsigned long flags, void __iomem *reg, 112 const char *parent_name, unsigned long flags, void __iomem *reg,
111 u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); 113 u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
112 114
115struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int);
113struct hisi_clock_data *hisi_clk_init(struct device_node *, int); 116struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
114void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, 117int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
115 int, struct hisi_clock_data *); 118 int, struct hisi_clock_data *);
116void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, 119int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
117 int, struct hisi_clock_data *); 120 int, struct hisi_clock_data *);
118void hisi_clk_register_mux(const struct hisi_mux_clock *, int, 121int hisi_clk_register_mux(const struct hisi_mux_clock *, int,
119 struct hisi_clock_data *); 122 struct hisi_clock_data *);
120void hisi_clk_register_divider(const struct hisi_divider_clock *, 123int hisi_clk_register_divider(const struct hisi_divider_clock *,
121 int, struct hisi_clock_data *); 124 int, struct hisi_clock_data *);
122void hisi_clk_register_gate(const struct hisi_gate_clock *, 125int hisi_clk_register_gate(const struct hisi_gate_clock *,
123 int, struct hisi_clock_data *); 126 int, struct hisi_clock_data *);
124void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, 127void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
125 int, struct hisi_clock_data *); 128 int, struct hisi_clock_data *);
126void hi6220_clk_register_divider(const struct hi6220_divider_clock *, 129void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
127 int, struct hisi_clock_data *); 130 int, struct hisi_clock_data *);
131
132#define hisi_clk_unregister(type) \
133static inline \
134void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
135 int nums, struct hisi_clock_data *data) \
136{ \
137 struct clk **clocks = data->clk_data.clks; \
138 int i; \
139 for (i = 0; i < nums; i++) { \
140 int id = clks[i].id; \
141 if (clocks[id]) \
142 clk_unregister_##type(clocks[id]); \
143 } \
144}
145
146hisi_clk_unregister(fixed_rate)
147hisi_clk_unregister(fixed_factor)
148hisi_clk_unregister(mux)
149hisi_clk_unregister(divider)
150hisi_clk_unregister(gate)
151
128#endif /* __HISI_CLK_H */ 152#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c
index 113eee8ed23a..a1c1f684ad58 100644
--- a/drivers/clk/hisilicon/clkdivider-hi6220.c
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -18,6 +18,8 @@
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/spinlock.h> 19#include <linux/spinlock.h>
20 20
21#include "clk.h"
22
21#define div_mask(width) ((1 << (width)) - 1) 23#define div_mask(width) ((1 << (width)) - 1)
22 24
23/** 25/**
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
index 6aa49c2204d0..2a5015c736ce 100644
--- a/drivers/clk/hisilicon/reset.c
+++ b/drivers/clk/hisilicon/reset.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/platform_device.h>
22#include <linux/reset-controller.h> 23#include <linux/reset-controller.h>
23#include <linux/slab.h> 24#include <linux/slab.h>
24#include <linux/spinlock.h> 25#include <linux/spinlock.h>
@@ -98,25 +99,25 @@ static const struct reset_control_ops hisi_reset_ops = {
98 .deassert = hisi_reset_deassert, 99 .deassert = hisi_reset_deassert,
99}; 100};
100 101
101struct hisi_reset_controller *hisi_reset_init(struct device_node *np) 102struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev)
102{ 103{
103 struct hisi_reset_controller *rstc; 104 struct hisi_reset_controller *rstc;
105 struct resource *res;
104 106
105 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 107 rstc = devm_kmalloc(&pdev->dev, sizeof(*rstc), GFP_KERNEL);
106 if (!rstc) 108 if (!rstc)
107 return NULL; 109 return NULL;
108 110
109 rstc->membase = of_iomap(np, 0); 111 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110 if (!rstc->membase) { 112 rstc->membase = devm_ioremap(&pdev->dev,
111 kfree(rstc); 113 res->start, resource_size(res));
114 if (!rstc->membase)
112 return NULL; 115 return NULL;
113 }
114 116
115 spin_lock_init(&rstc->lock); 117 spin_lock_init(&rstc->lock);
116
117 rstc->rcdev.owner = THIS_MODULE; 118 rstc->rcdev.owner = THIS_MODULE;
118 rstc->rcdev.ops = &hisi_reset_ops; 119 rstc->rcdev.ops = &hisi_reset_ops;
119 rstc->rcdev.of_node = np; 120 rstc->rcdev.of_node = pdev->dev.of_node;
120 rstc->rcdev.of_reset_n_cells = 2; 121 rstc->rcdev.of_reset_n_cells = 2;
121 rstc->rcdev.of_xlate = hisi_reset_of_xlate; 122 rstc->rcdev.of_xlate = hisi_reset_of_xlate;
122 reset_controller_register(&rstc->rcdev); 123 reset_controller_register(&rstc->rcdev);
@@ -128,7 +129,5 @@ EXPORT_SYMBOL_GPL(hisi_reset_init);
128void hisi_reset_exit(struct hisi_reset_controller *rstc) 129void hisi_reset_exit(struct hisi_reset_controller *rstc)
129{ 130{
130 reset_controller_unregister(&rstc->rcdev); 131 reset_controller_unregister(&rstc->rcdev);
131 iounmap(rstc->membase);
132 kfree(rstc);
133} 132}
134EXPORT_SYMBOL_GPL(hisi_reset_exit); 133EXPORT_SYMBOL_GPL(hisi_reset_exit);
diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
index 677d773ed27c..9a69374a0b32 100644
--- a/drivers/clk/hisilicon/reset.h
+++ b/drivers/clk/hisilicon/reset.h
@@ -22,10 +22,11 @@ struct device_node;
22struct hisi_reset_controller; 22struct hisi_reset_controller;
23 23
24#ifdef CONFIG_RESET_CONTROLLER 24#ifdef CONFIG_RESET_CONTROLLER
25struct hisi_reset_controller *hisi_reset_init(struct device_node *np); 25struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev);
26void hisi_reset_exit(struct hisi_reset_controller *rstc); 26void hisi_reset_exit(struct hisi_reset_controller *rstc);
27#else 27#else
28static inline hisi_reset_controller *hisi_reset_init(struct device_node *np) 28static inline
29struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev)
29{ 30{
30 return 0; 31 return 0;
31} 32}
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 2beb396fe652..ba1c1ae72ac2 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -192,13 +192,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
192 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 192 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
193 193
194 /* type name parent_name base div_mask */ 194 /* type name parent_name base div_mask */
195 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); 195 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
196 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); 196 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
197 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); 197 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
198 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); 198 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
199 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); 199 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
200 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); 200 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
201 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); 201 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
202 202
203 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 203 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
204 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 204 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 1be6230a07af..5fd4ddac1bf1 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -218,13 +218,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
218 clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 218 clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
219 219
220 /* type name parent_name base div_mask */ 220 /* type name parent_name base div_mask */
221 clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); 221 clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
222 clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); 222 clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
223 clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); 223 clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
224 clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); 224 clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
225 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); 225 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
226 clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); 226 clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
227 clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); 227 clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
228 228
229 clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 229 clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
230 clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 230 clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index 97e742a8be17..b5c96de41ccf 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -174,13 +174,13 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
174 clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 174 clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
175 175
176 /* type name parent_name base div_mask */ 176 /* type name parent_name base div_mask */
177 clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); 177 clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
178 clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); 178 clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
179 clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); 179 clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
180 clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); 180 clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
181 clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); 181 clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
182 clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); 182 clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
183 clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); 183 clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
184 184
185 clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 185 clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
186 clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 186 clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 0f1f17a8f3ed..d1d7787ce211 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -130,13 +130,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
130 clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 130 clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
131 clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); 131 clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
132 132
133 clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); 133 clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
134 clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); 134 clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
135 clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); 135 clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
136 clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); 136 clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
137 clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); 137 clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
138 clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); 138 clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
139 clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); 139 clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
140 140
141 clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); 141 clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
142 clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); 142 clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
@@ -305,8 +305,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
305 clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); 305 clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
306 clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 306 clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
307 clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); 307 clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
308 clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x68, 24); 308 clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt2_bus", "perclk", base + 0x68, 24);
309 clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x68, 26); 309 clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26);
310 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); 310 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
311 clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); 311 clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
312 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); 312 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 522996800d5b..6ed4f8fa0667 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -65,7 +65,7 @@ static const char *dram_phym_sel[] = { "pll_dram_main_clk",
65 "dram_phym_alt_clk", }; 65 "dram_phym_alt_clk", };
66 66
67static const char *dram_sel[] = { "pll_dram_main_clk", 67static const char *dram_sel[] = { "pll_dram_main_clk",
68 "dram_alt_clk", }; 68 "dram_alt_root_clk", };
69 69
70static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", 70static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
71 "pll_sys_main_clk", "pll_enet_500m_clk", 71 "pll_sys_main_clk", "pll_enet_500m_clk",
@@ -361,6 +361,14 @@ static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src
361static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", }; 361static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", };
362static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", }; 362static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", };
363 363
364static int const clks_init_on[] __initconst = {
365 IMX7D_ARM_A7_ROOT_CLK, IMX7D_MAIN_AXI_ROOT_CLK,
366 IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK,
367 IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK,
368 IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK,
369 IMX7D_AHB_CHANNEL_ROOT_CLK,
370};
371
364static struct clk_onecell_data clk_data; 372static struct clk_onecell_data clk_data;
365 373
366static struct clk ** const uart_clks[] __initconst = { 374static struct clk ** const uart_clks[] __initconst = {
@@ -395,12 +403,12 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
395 clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 403 clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
396 clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 404 clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
397 405
398 clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "pll_arm_main_src", base + 0x60, 0x7f); 406 clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f);
399 clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_dram_main", "pll_dram_main_src", base + 0x70, 0x7f); 407 clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_dram_main", "osc", base + 0x70, 0x7f);
400 clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "pll_sys_main_src", base + 0xb0, 0x1); 408 clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
401 clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "pll_enet_main_src", base + 0xe0, 0x0); 409 clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);
402 clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "pll_audio_main_src", base + 0xf0, 0x7f); 410 clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f);
403 clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "pll_video_main_src", base + 0x130, 0x7f); 411 clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f);
404 412
405 clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); 413 clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);
406 clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); 414 clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);
@@ -474,363 +482,363 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
474 base = of_iomap(np, 0); 482 base = of_iomap(np, 0);
475 WARN_ON(!base); 483 WARN_ON(!base);
476 484
477 clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); 485 clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel));
478 clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); 486 clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel));
479 clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux("arm_m0_src", base + 0x8100, 24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel)); 487 clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux2("arm_m0_src", base + 0x8100, 24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel));
480 clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); 488 clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel));
481 clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); 489 clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel));
482 clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); 490 clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel));
483 clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); 491 clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux2("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel));
484 clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); 492 clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel));
485 clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); 493 clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux2("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel));
486 clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); 494 clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel));
487 clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); 495 clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux2("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel));
488 clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); 496 clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
489 clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); 497 clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux2("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel));
490 clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); 498 clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux2("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel));
491 clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); 499 clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux2("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel));
492 clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); 500 clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux2("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel));
493 clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); 501 clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel));
494 clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); 502 clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux2("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel));
495 clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); 503 clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux2("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel));
496 clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); 504 clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux2("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel));
497 clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); 505 clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux2("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel));
498 clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); 506 clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux2("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel));
499 clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); 507 clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux2("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel));
500 clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); 508 clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux2("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel));
501 clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); 509 clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux2("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel));
502 clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); 510 clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux2("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel));
503 clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); 511 clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux2("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel));
504 clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); 512 clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux2("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel));
505 clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); 513 clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux2("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel));
506 clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); 514 clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux2("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel));
507 clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); 515 clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux2("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel));
508 clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); 516 clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux2("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel));
509 clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); 517 clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux2("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel));
510 clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); 518 clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux2("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel));
511 clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); 519 clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux2("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel));
512 clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); 520 clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel));
513 clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); 521 clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel));
514 clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); 522 clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux2("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel));
515 clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); 523 clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux2("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel));
516 clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); 524 clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux2("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel));
517 clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); 525 clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux2("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel));
518 clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); 526 clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux2("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel));
519 clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); 527 clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux2("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel));
520 clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); 528 clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux2("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel));
521 clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); 529 clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux2("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel));
522 clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); 530 clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux2("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel));
523 clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); 531 clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux2("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel));
524 clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); 532 clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux2("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel));
525 clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); 533 clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux2("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel));
526 clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); 534 clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux2("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel));
527 clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); 535 clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux2("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel));
528 clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); 536 clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux2("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel));
529 clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); 537 clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux2("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel));
530 clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); 538 clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux2("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel));
531 clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); 539 clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux2("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel));
532 clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); 540 clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux2("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel));
533 clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); 541 clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux2("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel));
534 clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); 542 clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux2("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel));
535 clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); 543 clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux2("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel));
536 clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); 544 clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux2("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel));
537 clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); 545 clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux2("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel));
538 clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); 546 clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux2("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel));
539 clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); 547 clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux2("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel));
540 clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); 548 clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux2("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel));
541 clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); 549 clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux2("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel));
542 clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); 550 clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux2("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel));
543 clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); 551 clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux2("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel));
544 clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); 552 clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux2("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel));
545 clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); 553 clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux2("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel));
546 clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); 554 clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux2("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel));
547 clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); 555 clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux2("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel));
548 556
549 clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); 557 clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28);
550 clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); 558 clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
551 clks[IMX7D_ARM_M0_ROOT_CG] = imx_clk_gate("arm_m0_cg", "arm_m0_src", base + 0x8100, 28); 559 clks[IMX7D_ARM_M0_ROOT_CG] = imx_clk_gate3("arm_m0_cg", "arm_m0_src", base + 0x8100, 28);
552 clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate("axi_cg", "axi_src", base + 0x8800, 28); 560 clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate3("axi_cg", "axi_src", base + 0x8800, 28);
553 clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); 561 clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28);
554 clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); 562 clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28);
555 clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28); 563 clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate3("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28);
556 clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate("ahb_cg", "ahb_src", base + 0x9000, 28); 564 clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate3("ahb_cg", "ahb_src", base + 0x9000, 28);
557 clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate("dram_phym_cg", "dram_phym_src", base + 0x9800, 28); 565 clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate3("dram_phym_cg", "dram_phym_src", base + 0x9800, 28);
558 clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate("dram_cg", "dram_src", base + 0x9880, 28); 566 clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate3("dram_cg", "dram_src", base + 0x9880, 28);
559 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28); 567 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate3("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28);
560 clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate("dram_alt_cg", "dram_alt_src", base + 0xa080, 28); 568 clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate3("dram_alt_cg", "dram_alt_src", base + 0xa080, 28);
561 clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28); 569 clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate3("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28);
562 clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28); 570 clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate3("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28);
563 clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28); 571 clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate3("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28);
564 clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28); 572 clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate3("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28);
565 clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28); 573 clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate3("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28);
566 clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28); 574 clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate3("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28);
567 clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28); 575 clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate3("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28);
568 clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28); 576 clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate3("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28);
569 clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate("sai1_cg", "sai1_src", base + 0xa500, 28); 577 clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate3("sai1_cg", "sai1_src", base + 0xa500, 28);
570 clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate("sai2_cg", "sai2_src", base + 0xa580, 28); 578 clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate3("sai2_cg", "sai2_src", base + 0xa580, 28);
571 clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate("sai3_cg", "sai3_src", base + 0xa600, 28); 579 clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate3("sai3_cg", "sai3_src", base + 0xa600, 28);
572 clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate("spdif_cg", "spdif_src", base + 0xa680, 28); 580 clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate3("spdif_cg", "spdif_src", base + 0xa680, 28);
573 clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28); 581 clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28);
574 clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate("enet1_time_cg", "enet1_time_src", base + 0xa780, 28); 582 clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28);
575 clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28); 583 clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28);
576 clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate("enet2_time_cg", "enet2_time_src", base + 0xa880, 28); 584 clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28);
577 clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28); 585 clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate3("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28);
578 clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate("eim_cg", "eim_src", base + 0xa980, 28); 586 clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate3("eim_cg", "eim_src", base + 0xa980, 28);
579 clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate("nand_cg", "nand_src", base + 0xaa00, 28); 587 clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate3("nand_cg", "nand_src", base + 0xaa00, 28);
580 clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate("qspi_cg", "qspi_src", base + 0xaa80, 28); 588 clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate3("qspi_cg", "qspi_src", base + 0xaa80, 28);
581 clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate("usdhc1_cg", "usdhc1_src", base + 0xab00, 28); 589 clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate3("usdhc1_cg", "usdhc1_src", base + 0xab00, 28);
582 clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate("usdhc2_cg", "usdhc2_src", base + 0xab80, 28); 590 clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate3("usdhc2_cg", "usdhc2_src", base + 0xab80, 28);
583 clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate("usdhc3_cg", "usdhc3_src", base + 0xac00, 28); 591 clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate3("usdhc3_cg", "usdhc3_src", base + 0xac00, 28);
584 clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate("can1_cg", "can1_src", base + 0xac80, 28); 592 clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate3("can1_cg", "can1_src", base + 0xac80, 28);
585 clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate("can2_cg", "can2_src", base + 0xad00, 28); 593 clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate3("can2_cg", "can2_src", base + 0xad00, 28);
586 clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate("i2c1_cg", "i2c1_src", base + 0xad80, 28); 594 clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate3("i2c1_cg", "i2c1_src", base + 0xad80, 28);
587 clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate("i2c2_cg", "i2c2_src", base + 0xae00, 28); 595 clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate3("i2c2_cg", "i2c2_src", base + 0xae00, 28);
588 clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate("i2c3_cg", "i2c3_src", base + 0xae80, 28); 596 clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate3("i2c3_cg", "i2c3_src", base + 0xae80, 28);
589 clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate("i2c4_cg", "i2c4_src", base + 0xaf00, 28); 597 clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate3("i2c4_cg", "i2c4_src", base + 0xaf00, 28);
590 clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate("uart1_cg", "uart1_src", base + 0xaf80, 28); 598 clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate3("uart1_cg", "uart1_src", base + 0xaf80, 28);
591 clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate("uart2_cg", "uart2_src", base + 0xb000, 28); 599 clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate3("uart2_cg", "uart2_src", base + 0xb000, 28);
592 clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate("uart3_cg", "uart3_src", base + 0xb080, 28); 600 clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate3("uart3_cg", "uart3_src", base + 0xb080, 28);
593 clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate("uart4_cg", "uart4_src", base + 0xb100, 28); 601 clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate3("uart4_cg", "uart4_src", base + 0xb100, 28);
594 clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate("uart5_cg", "uart5_src", base + 0xb180, 28); 602 clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate3("uart5_cg", "uart5_src", base + 0xb180, 28);
595 clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate("uart6_cg", "uart6_src", base + 0xb200, 28); 603 clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate3("uart6_cg", "uart6_src", base + 0xb200, 28);
596 clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate("uart7_cg", "uart7_src", base + 0xb280, 28); 604 clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate3("uart7_cg", "uart7_src", base + 0xb280, 28);
597 clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate("ecspi1_cg", "ecspi1_src", base + 0xb300, 28); 605 clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate3("ecspi1_cg", "ecspi1_src", base + 0xb300, 28);
598 clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate("ecspi2_cg", "ecspi2_src", base + 0xb380, 28); 606 clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate3("ecspi2_cg", "ecspi2_src", base + 0xb380, 28);
599 clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate("ecspi3_cg", "ecspi3_src", base + 0xb400, 28); 607 clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate3("ecspi3_cg", "ecspi3_src", base + 0xb400, 28);
600 clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate("ecspi4_cg", "ecspi4_src", base + 0xb480, 28); 608 clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate3("ecspi4_cg", "ecspi4_src", base + 0xb480, 28);
601 clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate("pwm1_cg", "pwm1_src", base + 0xb500, 28); 609 clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate3("pwm1_cg", "pwm1_src", base + 0xb500, 28);
602 clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate("pwm2_cg", "pwm2_src", base + 0xb580, 28); 610 clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate3("pwm2_cg", "pwm2_src", base + 0xb580, 28);
603 clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate("pwm3_cg", "pwm3_src", base + 0xb600, 28); 611 clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate3("pwm3_cg", "pwm3_src", base + 0xb600, 28);
604 clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate("pwm4_cg", "pwm4_src", base + 0xb680, 28); 612 clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate3("pwm4_cg", "pwm4_src", base + 0xb680, 28);
605 clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate("flextimer1_cg", "flextimer1_src", base + 0xb700, 28); 613 clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate3("flextimer1_cg", "flextimer1_src", base + 0xb700, 28);
606 clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate("flextimer2_cg", "flextimer2_src", base + 0xb780, 28); 614 clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate3("flextimer2_cg", "flextimer2_src", base + 0xb780, 28);
607 clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate("sim1_cg", "sim1_src", base + 0xb800, 28); 615 clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate3("sim1_cg", "sim1_src", base + 0xb800, 28);
608 clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate("sim2_cg", "sim2_src", base + 0xb880, 28); 616 clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate3("sim2_cg", "sim2_src", base + 0xb880, 28);
609 clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate("gpt1_cg", "gpt1_src", base + 0xb900, 28); 617 clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate3("gpt1_cg", "gpt1_src", base + 0xb900, 28);
610 clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate("gpt2_cg", "gpt2_src", base + 0xb980, 28); 618 clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate3("gpt2_cg", "gpt2_src", base + 0xb980, 28);
611 clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate("gpt3_cg", "gpt3_src", base + 0xbA00, 28); 619 clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate3("gpt3_cg", "gpt3_src", base + 0xbA00, 28);
612 clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate("gpt4_cg", "gpt4_src", base + 0xbA80, 28); 620 clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate3("gpt4_cg", "gpt4_src", base + 0xbA80, 28);
613 clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate("trace_cg", "trace_src", base + 0xbb00, 28); 621 clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate3("trace_cg", "trace_src", base + 0xbb00, 28);
614 clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate("wdog_cg", "wdog_src", base + 0xbb80, 28); 622 clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate3("wdog_cg", "wdog_src", base + 0xbb80, 28);
615 clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28); 623 clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate3("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28);
616 clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28); 624 clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate3("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28);
617 clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate("wrclk_cg", "wrclk_src", base + 0xbd00, 28); 625 clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate3("wrclk_cg", "wrclk_src", base + 0xbd00, 28);
618 clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate("clko1_cg", "clko1_src", base + 0xbd80, 28); 626 clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate3("clko1_cg", "clko1_src", base + 0xbd80, 28);
619 clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate("clko2_cg", "clko2_src", base + 0xbe00, 28); 627 clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate3("clko2_cg", "clko2_src", base + 0xbe00, 28);
620 628
621 clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider("axi_pre_div", "axi_cg", base + 0x8800, 16, 3); 629 clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider2("axi_pre_div", "axi_cg", base + 0x8800, 16, 3);
622 clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3); 630 clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3);
623 clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3); 631 clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3);
624 clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3); 632 clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider2("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3);
625 clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); 633 clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3);
626 clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3); 634 clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider2("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3);
627 clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3); 635 clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3);
628 clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3); 636 clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider2("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3);
629 clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3); 637 clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider2("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3);
630 clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3); 638 clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider2("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3);
631 clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3); 639 clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider2("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3);
632 clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3); 640 clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3);
633 clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3); 641 clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider2("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3);
634 clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3); 642 clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider2("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3);
635 clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3); 643 clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider2("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3);
636 clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3); 644 clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider2("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3);
637 clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3); 645 clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider2("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3);
638 clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3); 646 clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider2("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3);
639 clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3); 647 clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider2("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3);
640 clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3); 648 clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3);
641 clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3); 649 clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider2("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3);
642 clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3); 650 clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3);
643 clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3); 651 clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider2("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3);
644 clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3); 652 clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3);
645 clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider("eim_pre_div", "eim_cg", base + 0xa980, 16, 3); 653 clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider2("eim_pre_div", "eim_cg", base + 0xa980, 16, 3);
646 clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3); 654 clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider2("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3);
647 clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3); 655 clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider2("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3);
648 clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3); 656 clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3);
649 clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3); 657 clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3);
650 clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3); 658 clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider2("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3);
651 clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); 659 clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3);
652 clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); 660 clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3);
653 clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3); 661 clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3);
654 clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3); 662 clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider2("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3);
655 clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3); 663 clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3);
656 clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3); 664 clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider2("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3);
657 clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3); 665 clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider2("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3);
658 clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3); 666 clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider2("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3);
659 clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3); 667 clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider2("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3);
660 clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3); 668 clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider2("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3);
661 clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3); 669 clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider2("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3);
662 clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3); 670 clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider2("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3);
663 clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3); 671 clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider2("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3);
664 clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3); 672 clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3);
665 clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3); 673 clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3);
666 clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3); 674 clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3);
667 clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3); 675 clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider2("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3);
668 clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3); 676 clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3);
669 clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3); 677 clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3);
670 clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3); 678 clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3);
671 clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3); 679 clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3);
672 clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3); 680 clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider2("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3);
673 clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3); 681 clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider2("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3);
674 clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3); 682 clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider2("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3);
675 clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3); 683 clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider2("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3);
676 clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3); 684 clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3);
677 clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3); 685 clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider2("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3);
678 clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3); 686 clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider2("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3);
679 clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3); 687 clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider2("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3);
680 clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3); 688 clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider2("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3);
681 clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3); 689 clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider2("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3);
682 clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3); 690 clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider2("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3);
683 clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3); 691 clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider2("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3);
684 clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3); 692 clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider2("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3);
685 clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); 693 clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider2("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3);
686 clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); 694 clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3);
687 695
688 clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); 696 clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3);
689 clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); 697 clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
690 clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3); 698 clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider2("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3);
691 clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); 699 clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6);
692 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); 700 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
693 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); 701 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
694 clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); 702 clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
695 clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); 703 clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6);
696 clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider("dram_post_div", "dram_cg", base + 0x9880, 0, 3); 704 clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3);
697 clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); 705 clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
698 clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); 706 clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);
699 clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6); 707 clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider2("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6);
700 clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6); 708 clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider2("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6);
701 clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6); 709 clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider2("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6);
702 clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6); 710 clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider2("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6);
703 clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); 711 clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
704 clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); 712 clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
705 clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); 713 clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
706 clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6); 714 clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6);
707 clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); 715 clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
708 clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); 716 clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
709 clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); 717 clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);
710 clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6); 718 clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider2("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6);
711 clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6); 719 clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider2("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6);
712 clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); 720 clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6);
713 clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); 721 clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6);
714 clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); 722 clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
715 clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); 723 clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
716 clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); 724 clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
717 clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); 725 clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6);
718 clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); 726 clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
719 clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); 727 clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6);
720 clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); 728 clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6);
721 clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6); 729 clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider2("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6);
722 clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); 730 clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6);
723 clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); 731 clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6);
724 clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6); 732 clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider2("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6);
725 clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6); 733 clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider2("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6);
726 clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6); 734 clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider2("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6);
727 clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6); 735 clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider2("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6);
728 clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6); 736 clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider2("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6);
729 clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6); 737 clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider2("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6);
730 clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6); 738 clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider2("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6);
731 clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6); 739 clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider2("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6);
732 clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6); 740 clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider2("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6);
733 clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6); 741 clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider2("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6);
734 clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6); 742 clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider2("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6);
735 clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6); 743 clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider2("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6);
736 clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6); 744 clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider2("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6);
737 clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6); 745 clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider2("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6);
738 clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6); 746 clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider2("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6);
739 clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6); 747 clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider2("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6);
740 clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6); 748 clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider2("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6);
741 clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6); 749 clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider2("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6);
742 clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6); 750 clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider2("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6);
743 clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6); 751 clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider2("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6);
744 clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6); 752 clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider2("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6);
745 clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6); 753 clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider2("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6);
746 clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6); 754 clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider2("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6);
747 clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6); 755 clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider2("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6);
748 clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6); 756 clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider2("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6);
749 clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6); 757 clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider2("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6);
750 clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6); 758 clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider2("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6);
751 clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6); 759 clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider2("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6);
752 clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6); 760 clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider2("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6);
753 clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6); 761 clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider2("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6);
754 clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6); 762 clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider2("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6);
755 clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6); 763 clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6);
756 clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); 764 clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6);
757 clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); 765 clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6);
758 766
759 clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0); 767 clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0);
760 clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate2("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); 768 clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0);
761 clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate2("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0); 769 clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0);
762 clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate2("main_axi_root_clk", "axi_post_div", base + 0x4040, 0); 770 clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate4("main_axi_root_clk", "axi_post_div", base + 0x4040, 0);
763 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate2("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); 771 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0);
764 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate2("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); 772 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0);
765 clks[IMX7D_OCRAM_CLK] = imx_clk_gate2("ocram_clk", "axi_post_div", base + 0x4110, 0); 773 clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div", base + 0x4110, 0);
766 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate2("ocram_s_clk", "ahb_post_div", base + 0x4120, 0); 774 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_post_div", base + 0x4120, 0);
767 clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate2("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0); 775 clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0);
768 clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate2("ahb_root_clk", "ahb_post_div", base + 0x4200, 0); 776 clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate4("ahb_root_clk", "ahb_post_div", base + 0x4200, 0);
769 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate2("dram_root_clk", "dram_post_div", base + 0x4130, 0); 777 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0);
770 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); 778 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0);
771 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); 779 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
772 clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); 780 clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
773 clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate2("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); 781 clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
774 clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate2("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); 782 clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
775 clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate2("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); 783 clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
776 clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate2("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); 784 clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
777 clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate2("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); 785 clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
778 clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate2("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); 786 clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
779 clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate2("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); 787 clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
780 clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate2("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); 788 clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
781 clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0); 789 clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate4("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0);
782 clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0); 790 clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate4("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0);
783 clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0); 791 clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate4("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0);
784 clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate2("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); 792 clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
785 clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate2("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0); 793 clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
786 clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0); 794 clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
787 clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate2("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0); 795 clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
788 clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); 796 clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
789 clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate2("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); 797 clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
790 clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate2("eim_root_clk", "eim_post_div", base + 0x4160, 0); 798 clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
791 clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate2("nand_root_clk", "nand_post_div", base + 0x4140, 0); 799 clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0);
792 clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate2("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); 800 clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);
793 clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate2("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); 801 clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0);
794 clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate2("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); 802 clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0);
795 clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate2("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0); 803 clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate4("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0);
796 clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate2("can1_root_clk", "can1_post_div", base + 0x4740, 0); 804 clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0);
797 clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate2("can2_root_clk", "can2_post_div", base + 0x4750, 0); 805 clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0);
798 clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate2("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0); 806 clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate4("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0);
799 clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate2("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0); 807 clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate4("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0);
800 clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate2("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0); 808 clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate4("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0);
801 clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate2("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0); 809 clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate4("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0);
802 clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate2("uart1_root_clk", "uart1_post_div", base + 0x4940, 0); 810 clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate4("uart1_root_clk", "uart1_post_div", base + 0x4940, 0);
803 clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate2("uart2_root_clk", "uart2_post_div", base + 0x4950, 0); 811 clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate4("uart2_root_clk", "uart2_post_div", base + 0x4950, 0);
804 clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate2("uart3_root_clk", "uart3_post_div", base + 0x4960, 0); 812 clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate4("uart3_root_clk", "uart3_post_div", base + 0x4960, 0);
805 clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate2("uart4_root_clk", "uart4_post_div", base + 0x4970, 0); 813 clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate4("uart4_root_clk", "uart4_post_div", base + 0x4970, 0);
806 clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate2("uart5_root_clk", "uart5_post_div", base + 0x4980, 0); 814 clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate4("uart5_root_clk", "uart5_post_div", base + 0x4980, 0);
807 clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate2("uart6_root_clk", "uart6_post_div", base + 0x4990, 0); 815 clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate4("uart6_root_clk", "uart6_post_div", base + 0x4990, 0);
808 clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate2("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0); 816 clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate4("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0);
809 clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate2("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0); 817 clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate4("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0);
810 clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate2("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0); 818 clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate4("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0);
811 clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate2("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0); 819 clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate4("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0);
812 clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate2("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0); 820 clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate4("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0);
813 clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate2("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0); 821 clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate4("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0);
814 clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate2("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0); 822 clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate4("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0);
815 clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate2("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0); 823 clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate4("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0);
816 clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate2("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0); 824 clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate4("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0);
817 clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate2("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0); 825 clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate4("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0);
818 clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate2("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0); 826 clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate4("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0);
819 clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate2("sim1_root_clk", "sim1_post_div", base + 0x4900, 0); 827 clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate4("sim1_root_clk", "sim1_post_div", base + 0x4900, 0);
820 clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate2("sim2_root_clk", "sim2_post_div", base + 0x4910, 0); 828 clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate4("sim2_root_clk", "sim2_post_div", base + 0x4910, 0);
821 clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate2("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0); 829 clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate4("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0);
822 clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate2("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0); 830 clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate4("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0);
823 clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate2("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0); 831 clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate4("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0);
824 clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate2("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0); 832 clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate4("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0);
825 clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate2("trace_root_clk", "trace_post_div", base + 0x4300, 0); 833 clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate4("trace_root_clk", "trace_post_div", base + 0x4300, 0);
826 clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate2("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0); 834 clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate4("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0);
827 clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate2("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); 835 clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
828 clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate2("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); 836 clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
829 clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate2("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); 837 clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
830 clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); 838 clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
831 clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); 839 clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
832 clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); 840 clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
833 clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); 841 clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
834 842
835 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 843 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
836 844
@@ -846,28 +854,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
846 clk_data.clk_num = ARRAY_SIZE(clks); 854 clk_data.clk_num = ARRAY_SIZE(clks);
847 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 855 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
848 856
849 /* TO BE FIXED LATER 857 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
850 * Enable all clock to bring up imx7, otherwise system will be halt and block 858 clk_prepare_enable(clks[clks_init_on[i]]);
851 * the other part upstream Because imx7d clock design changed, clock framework
852 * need do a little modify.
853 * Dong Aisheng is working on this. After that, this part need be changed.
854 */
855 for (i = 0; i < IMX7D_CLK_END; i++)
856 clk_prepare_enable(clks[i]);
857 859
858 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ 860 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
859 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 861 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
860 862
861 /*
862 * init enet clock source:
863 * AXI clock source is 250MHz
864 * Phy refrence clock is 25MHz
865 * 1588 time clock source is 100MHz
866 */
867 clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); 863 clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]);
868 clk_set_parent(clks[IMX7D_ENET_PHY_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_25M_CLK]);
869 clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
870 clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
871 864
872 /* set uart module clock's parent clock source that must be great then 80MHz */ 865 /* set uart module clock's parent clock source that must be great then 80MHz */
873 clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 866 clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 4826b3c9e19e..19f9b622981a 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -29,8 +29,8 @@
29 * struct clk_pllv3 - IMX PLL clock version 3 29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source 30 * @clk_hw: clock source
31 * @base: base address of PLL registers 31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL 32 * @power_bit: pll power bit mask
33 * @powerdown: pll powerdown offset bit 33 * @powerup_set: set power_bit to power up the PLL
34 * @div_mask: mask of divider bits 34 * @div_mask: mask of divider bits
35 * @div_shift: shift of divider bits 35 * @div_shift: shift of divider bits
36 * 36 *
@@ -40,8 +40,8 @@
40struct clk_pllv3 { 40struct clk_pllv3 {
41 struct clk_hw hw; 41 struct clk_hw hw;
42 void __iomem *base; 42 void __iomem *base;
43 u32 power_bit;
43 bool powerup_set; 44 bool powerup_set;
44 u32 powerdown;
45 u32 div_mask; 45 u32 div_mask;
46 u32 div_shift; 46 u32 div_shift;
47 unsigned long ref_clock; 47 unsigned long ref_clock;
@@ -52,7 +52,7 @@ struct clk_pllv3 {
52static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 52static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
53{ 53{
54 unsigned long timeout = jiffies + msecs_to_jiffies(10); 54 unsigned long timeout = jiffies + msecs_to_jiffies(10);
55 u32 val = readl_relaxed(pll->base) & pll->powerdown; 55 u32 val = readl_relaxed(pll->base) & pll->power_bit;
56 56
57 /* No need to wait for lock when pll is not powered up */ 57 /* No need to wait for lock when pll is not powered up */
58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
@@ -77,9 +77,9 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
77 77
78 val = readl_relaxed(pll->base); 78 val = readl_relaxed(pll->base);
79 if (pll->powerup_set) 79 if (pll->powerup_set)
80 val |= BM_PLL_POWER; 80 val |= pll->power_bit;
81 else 81 else
82 val &= ~BM_PLL_POWER; 82 val &= ~pll->power_bit;
83 writel_relaxed(val, pll->base); 83 writel_relaxed(val, pll->base);
84 84
85 return clk_pllv3_wait_lock(pll); 85 return clk_pllv3_wait_lock(pll);
@@ -92,9 +92,9 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
92 92
93 val = readl_relaxed(pll->base); 93 val = readl_relaxed(pll->base);
94 if (pll->powerup_set) 94 if (pll->powerup_set)
95 val &= ~BM_PLL_POWER; 95 val &= ~pll->power_bit;
96 else 96 else
97 val |= BM_PLL_POWER; 97 val |= pll->power_bit;
98 writel_relaxed(val, pll->base); 98 writel_relaxed(val, pll->base);
99} 99}
100 100
@@ -218,8 +218,12 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
218 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); 218 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
219 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); 219 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
220 u32 div = readl_relaxed(pll->base) & pll->div_mask; 220 u32 div = readl_relaxed(pll->base) & pll->div_mask;
221 u64 temp64 = (u64)parent_rate;
221 222
222 return (parent_rate * div) + ((parent_rate / mfd) * mfn); 223 temp64 *= mfn;
224 do_div(temp64, mfd);
225
226 return (parent_rate * div) + (u32)temp64;
223} 227}
224 228
225static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 229static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -243,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
243 do_div(temp64, parent_rate); 247 do_div(temp64, parent_rate);
244 mfn = temp64; 248 mfn = temp64;
245 249
246 return parent_rate * div + parent_rate / mfd * mfn; 250 return parent_rate * div + parent_rate * mfn / mfd;
247} 251}
248 252
249static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 253static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -312,7 +316,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
312 if (!pll) 316 if (!pll)
313 return ERR_PTR(-ENOMEM); 317 return ERR_PTR(-ENOMEM);
314 318
315 pll->powerdown = BM_PLL_POWER; 319 pll->power_bit = BM_PLL_POWER;
316 320
317 switch (type) { 321 switch (type) {
318 case IMX_PLLV3_SYS: 322 case IMX_PLLV3_SYS:
@@ -328,7 +332,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
328 ops = &clk_pllv3_av_ops; 332 ops = &clk_pllv3_av_ops;
329 break; 333 break;
330 case IMX_PLLV3_ENET_IMX7: 334 case IMX_PLLV3_ENET_IMX7:
331 pll->powerdown = IMX7_ENET_PLL_POWER; 335 pll->power_bit = IMX7_ENET_PLL_POWER;
332 pll->ref_clock = 1000000000; 336 pll->ref_clock = 1000000000;
333 ops = &clk_pllv3_enet_ops; 337 ops = &clk_pllv3_enet_ops;
334 break; 338 break;
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 3a1f24475ee4..0476353ab423 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -315,12 +315,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
315 315
316 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); 316 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
317 317
318 clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); 318 clk[VF610_CLK_UART0] = imx_clk_gate2_cgr("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7), 0x2);
319 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); 319 clk[VF610_CLK_UART1] = imx_clk_gate2_cgr("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8), 0x2);
320 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); 320 clk[VF610_CLK_UART2] = imx_clk_gate2_cgr("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9), 0x2);
321 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); 321 clk[VF610_CLK_UART3] = imx_clk_gate2_cgr("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10), 0x2);
322 clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9)); 322 clk[VF610_CLK_UART4] = imx_clk_gate2_cgr("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9), 0x2);
323 clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10)); 323 clk[VF610_CLK_UART5] = imx_clk_gate2_cgr("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10), 0x2);
324 324
325 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); 325 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
326 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); 326 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 508d0fad84cf..a81c0385ed64 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -51,28 +51,6 @@ struct clk * imx_obtain_fixed_clock(
51struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 51struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
52 void __iomem *reg, u8 shift, u32 exclusive_mask); 52 void __iomem *reg, u8 shift, u32 exclusive_mask);
53 53
54static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
55 void __iomem *reg, u8 shift)
56{
57 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
58 shift, 0x3, 0, &imx_ccm_lock, NULL);
59}
60
61static inline struct clk *imx_clk_gate2_shared(const char *name,
62 const char *parent, void __iomem *reg, u8 shift,
63 unsigned int *share_count)
64{
65 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
66 shift, 0x3, 0, &imx_ccm_lock, share_count);
67}
68
69static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
70 void __iomem *reg, u8 shift, u8 cgr_val)
71{
72 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
73 shift, cgr_val, 0, &imx_ccm_lock, NULL);
74}
75
76struct clk *imx_clk_pfd(const char *name, const char *parent_name, 54struct clk *imx_clk_pfd(const char *name, const char *parent_name,
77 void __iomem *reg, u8 idx); 55 void __iomem *reg, u8 idx);
78 56
@@ -97,6 +75,13 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
97 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 75 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
98} 76}
99 77
78static inline struct clk *imx_clk_fixed_factor(const char *name,
79 const char *parent, unsigned int mult, unsigned int div)
80{
81 return clk_register_fixed_factor(NULL, name, parent,
82 CLK_SET_RATE_PARENT, mult, div);
83}
84
100static inline struct clk *imx_clk_divider(const char *name, const char *parent, 85static inline struct clk *imx_clk_divider(const char *name, const char *parent,
101 void __iomem *reg, u8 shift, u8 width) 86 void __iomem *reg, u8 shift, u8 width)
102{ 87{
@@ -112,6 +97,14 @@ static inline struct clk *imx_clk_divider_flags(const char *name,
112 reg, shift, width, 0, &imx_ccm_lock); 97 reg, shift, width, 0, &imx_ccm_lock);
113} 98}
114 99
100static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
101 void __iomem *reg, u8 shift, u8 width)
102{
103 return clk_register_divider(NULL, name, parent,
104 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
105 reg, shift, width, 0, &imx_ccm_lock);
106}
107
115static inline struct clk *imx_clk_gate(const char *name, const char *parent, 108static inline struct clk *imx_clk_gate(const char *name, const char *parent,
116 void __iomem *reg, u8 shift) 109 void __iomem *reg, u8 shift)
117{ 110{
@@ -126,6 +119,44 @@ static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
126 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 119 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
127} 120}
128 121
122static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
123 void __iomem *reg, u8 shift)
124{
125 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
126 shift, 0x3, 0, &imx_ccm_lock, NULL);
127}
128
129static inline struct clk *imx_clk_gate2_shared(const char *name,
130 const char *parent, void __iomem *reg, u8 shift,
131 unsigned int *share_count)
132{
133 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
134 shift, 0x3, 0, &imx_ccm_lock, share_count);
135}
136
137static inline struct clk *imx_clk_gate2_cgr(const char *name,
138 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
139{
140 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
141 shift, cgr_val, 0, &imx_ccm_lock, NULL);
142}
143
144static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
145 void __iomem *reg, u8 shift)
146{
147 return clk_register_gate(NULL, name, parent,
148 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
149 reg, shift, 0, &imx_ccm_lock);
150}
151
152static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
153 void __iomem *reg, u8 shift)
154{
155 return clk_register_gate2(NULL, name, parent,
156 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
157 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
158}
159
129static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 160static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
130 u8 shift, u8 width, const char **parents, int num_parents) 161 u8 shift, u8 width, const char **parents, int num_parents)
131{ 162{
@@ -134,6 +165,14 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
134 width, 0, &imx_ccm_lock); 165 width, 0, &imx_ccm_lock);
135} 166}
136 167
168static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
169 u8 shift, u8 width, const char **parents, int num_parents)
170{
171 return clk_register_mux(NULL, name, parents, num_parents,
172 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
173 reg, shift, width, 0, &imx_ccm_lock);
174}
175
137static inline struct clk *imx_clk_mux_flags(const char *name, 176static inline struct clk *imx_clk_mux_flags(const char *name,
138 void __iomem *reg, u8 shift, u8 width, const char **parents, 177 void __iomem *reg, u8 shift, u8 width, const char **parents,
139 int num_parents, unsigned long flags) 178 int num_parents, unsigned long flags)
@@ -143,13 +182,6 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
143 &imx_ccm_lock); 182 &imx_ccm_lock);
144} 183}
145 184
146static inline struct clk *imx_clk_fixed_factor(const char *name,
147 const char *parent, unsigned int mult, unsigned int div)
148{
149 return clk_register_fixed_factor(NULL, name, parent,
150 CLK_SET_RATE_PARENT, mult, div);
151}
152
153struct clk *imx_clk_cpu(const char *name, const char *parent_name, 185struct clk *imx_clk_cpu(const char *name, const char *parent_name,
154 struct clk *div, struct clk *mux, struct clk *pll, 186 struct clk *div, struct clk *mux, struct clk *pll,
155 struct clk *step); 187 struct clk *step);
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
new file mode 100644
index 000000000000..19480bcc7046
--- /dev/null
+++ b/drivers/clk/meson/Kconfig
@@ -0,0 +1,19 @@
1config COMMON_CLK_AMLOGIC
2 bool
3 depends on OF
4 depends on ARCH_MESON || COMPILE_TEST
5
6config COMMON_CLK_MESON8B
7 bool
8 depends on COMMON_CLK_AMLOGIC
9 help
10 Support for the clock controller on AmLogic S805 devices, aka
11 meson8b. Say Y if you want peripherals and CPU frequency scaling to
12 work.
13
14config COMMON_CLK_GXBB
15 bool
16 depends on COMMON_CLK_AMLOGIC
17 help
18 Support for the clock controller on AmLogic S905 devices, aka gxbb.
19 Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 6d45531df9ab..197e40175166 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,5 +2,6 @@
2# Makefile for Meson specific clk 2# Makefile for Meson specific clk
3# 3#
4 4
5obj-y += clkc.o clk-pll.o clk-cpu.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
6obj-y += meson8b-clkc.o 6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o
diff --git a/drivers/clk/meson/clk-cpu.c b/drivers/clk/meson/clk-cpu.c
index f7c30ea54ca8..f8b2b7efd016 100644
--- a/drivers/clk/meson/clk-cpu.c
+++ b/drivers/clk/meson/clk-cpu.c
@@ -51,13 +51,6 @@
51 51
52#include "clkc.h" 52#include "clkc.h"
53 53
54struct meson_clk_cpu {
55 struct notifier_block clk_nb;
56 const struct clk_div_table *div_table;
57 struct clk_hw hw;
58 void __iomem *base;
59 u16 reg_off;
60};
61#define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw) 54#define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw)
62#define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb) 55#define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb)
63 56
@@ -119,6 +112,7 @@ static unsigned long meson_clk_cpu_recalc_rate(struct clk_hw *hw,
119 return parent_rate / div; 112 return parent_rate / div;
120} 113}
121 114
115/* FIXME MUX1 & MUX2 should be struct clk_hw objects */
122static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu, 116static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu,
123 struct clk_notifier_data *ndata) 117 struct clk_notifier_data *ndata)
124{ 118{
@@ -140,6 +134,7 @@ static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu,
140 return 0; 134 return 0;
141} 135}
142 136
137/* FIXME MUX1 & MUX2 should be struct clk_hw objects */
143static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu, 138static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu,
144 struct clk_notifier_data *ndata) 139 struct clk_notifier_data *ndata)
145{ 140{
@@ -161,7 +156,7 @@ static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu,
161 * PLL clock is to be changed. We use the xtal input as temporary parent 156 * PLL clock is to be changed. We use the xtal input as temporary parent
162 * while the PLL frequency is stabilized. 157 * while the PLL frequency is stabilized.
163 */ 158 */
164static int meson_clk_cpu_notifier_cb(struct notifier_block *nb, 159int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
165 unsigned long event, void *data) 160 unsigned long event, void *data)
166{ 161{
167 struct clk_notifier_data *ndata = data; 162 struct clk_notifier_data *ndata = data;
@@ -176,68 +171,8 @@ static int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
176 return notifier_from_errno(ret); 171 return notifier_from_errno(ret);
177} 172}
178 173
179static const struct clk_ops meson_clk_cpu_ops = { 174const struct clk_ops meson_clk_cpu_ops = {
180 .recalc_rate = meson_clk_cpu_recalc_rate, 175 .recalc_rate = meson_clk_cpu_recalc_rate,
181 .round_rate = meson_clk_cpu_round_rate, 176 .round_rate = meson_clk_cpu_round_rate,
182 .set_rate = meson_clk_cpu_set_rate, 177 .set_rate = meson_clk_cpu_set_rate,
183}; 178};
184
185struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
186 void __iomem *reg_base,
187 spinlock_t *lock)
188{
189 struct clk *clk;
190 struct clk *pclk;
191 struct meson_clk_cpu *clk_cpu;
192 struct clk_init_data init;
193 int ret;
194
195 clk_cpu = kzalloc(sizeof(*clk_cpu), GFP_KERNEL);
196 if (!clk_cpu)
197 return ERR_PTR(-ENOMEM);
198
199 clk_cpu->base = reg_base;
200 clk_cpu->reg_off = clk_conf->reg_off;
201 clk_cpu->div_table = clk_conf->conf.div_table;
202 clk_cpu->clk_nb.notifier_call = meson_clk_cpu_notifier_cb;
203
204 init.name = clk_conf->clk_name;
205 init.ops = &meson_clk_cpu_ops;
206 init.flags = clk_conf->flags | CLK_GET_RATE_NOCACHE;
207 init.flags |= CLK_SET_RATE_PARENT;
208 init.parent_names = clk_conf->clks_parent;
209 init.num_parents = 1;
210
211 clk_cpu->hw.init = &init;
212
213 pclk = __clk_lookup(clk_conf->clks_parent[0]);
214 if (!pclk) {
215 pr_err("%s: could not lookup parent clock %s\n",
216 __func__, clk_conf->clks_parent[0]);
217 ret = -EINVAL;
218 goto free_clk;
219 }
220
221 ret = clk_notifier_register(pclk, &clk_cpu->clk_nb);
222 if (ret) {
223 pr_err("%s: failed to register clock notifier for %s\n",
224 __func__, clk_conf->clk_name);
225 goto free_clk;
226 }
227
228 clk = clk_register(NULL, &clk_cpu->hw);
229 if (IS_ERR(clk)) {
230 ret = PTR_ERR(clk);
231 goto unregister_clk_nb;
232 }
233
234 return clk;
235
236unregister_clk_nb:
237 clk_notifier_unregister(pclk, &clk_cpu->clk_nb);
238free_clk:
239 kfree(clk_cpu);
240
241 return ERR_PTR(ret);
242}
243
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
new file mode 100644
index 000000000000..03af79005ddb
--- /dev/null
+++ b/drivers/clk/meson/clk-mpll.c
@@ -0,0 +1,94 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 AmLogic, Inc.
8 * Author: Michael Turquette <mturquette@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING
24 *
25 * BSD LICENSE
26 *
27 * Copyright (c) 2016 AmLogic, Inc.
28 * Author: Michael Turquette <mturquette@baylibre.com>
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 *
34 * * Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * * Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in
38 * the documentation and/or other materials provided with the
39 * distribution.
40 * * Neither the name of Intel Corporation nor the names of its
41 * contributors may be used to endorse or promote products derived
42 * from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */
56
57/*
58 * MultiPhase Locked Loops are outputs from a PLL with additional frequency
59 * scaling capabilities. MPLL rates are calculated as:
60 *
61 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
62 */
63
64#include <linux/clk-provider.h>
65#include "clkc.h"
66
67#define SDM_MAX 16384
68
69#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
70
71static unsigned long mpll_recalc_rate(struct clk_hw *hw,
72 unsigned long parent_rate)
73{
74 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
75 struct parm *p;
76 unsigned long rate = 0;
77 unsigned long reg, sdm, n2;
78
79 p = &mpll->sdm;
80 reg = readl(mpll->base + p->reg_off);
81 sdm = PARM_GET(p->width, p->shift, reg);
82
83 p = &mpll->n2;
84 reg = readl(mpll->base + p->reg_off);
85 n2 = PARM_GET(p->width, p->shift, reg);
86
87 rate = (parent_rate * SDM_MAX) / ((SDM_MAX * n2) + sdm);
88
89 return rate;
90}
91
92const struct clk_ops meson_clk_mpll_ro_ops = {
93 .recalc_rate = mpll_recalc_rate,
94};
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 664edf0708ea..4adc1e89212c 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -44,13 +44,6 @@
44#define MESON_PLL_RESET BIT(29) 44#define MESON_PLL_RESET BIT(29)
45#define MESON_PLL_LOCK BIT(31) 45#define MESON_PLL_LOCK BIT(31)
46 46
47struct meson_clk_pll {
48 struct clk_hw hw;
49 void __iomem *base;
50 struct pll_conf *conf;
51 unsigned int rate_count;
52 spinlock_t *lock;
53};
54#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) 47#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
55 48
56static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, 49static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
@@ -60,22 +53,36 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
60 struct parm *p; 53 struct parm *p;
61 unsigned long parent_rate_mhz = parent_rate / 1000000; 54 unsigned long parent_rate_mhz = parent_rate / 1000000;
62 unsigned long rate_mhz; 55 unsigned long rate_mhz;
63 u16 n, m, od; 56 u16 n, m, frac = 0, od, od2 = 0;
64 u32 reg; 57 u32 reg;
65 58
66 p = &pll->conf->n; 59 p = &pll->n;
67 reg = readl(pll->base + p->reg_off); 60 reg = readl(pll->base + p->reg_off);
68 n = PARM_GET(p->width, p->shift, reg); 61 n = PARM_GET(p->width, p->shift, reg);
69 62
70 p = &pll->conf->m; 63 p = &pll->m;
71 reg = readl(pll->base + p->reg_off); 64 reg = readl(pll->base + p->reg_off);
72 m = PARM_GET(p->width, p->shift, reg); 65 m = PARM_GET(p->width, p->shift, reg);
73 66
74 p = &pll->conf->od; 67 p = &pll->od;
75 reg = readl(pll->base + p->reg_off); 68 reg = readl(pll->base + p->reg_off);
76 od = PARM_GET(p->width, p->shift, reg); 69 od = PARM_GET(p->width, p->shift, reg);
77 70
78 rate_mhz = (parent_rate_mhz * m / n) >> od; 71 p = &pll->od2;
72 if (p->width) {
73 reg = readl(pll->base + p->reg_off);
74 od2 = PARM_GET(p->width, p->shift, reg);
75 }
76
77 p = &pll->frac;
78 if (p->width) {
79 reg = readl(pll->base + p->reg_off);
80 frac = PARM_GET(p->width, p->shift, reg);
81 rate_mhz = (parent_rate_mhz * m + \
82 (parent_rate_mhz * frac >> 12)) * 2 / n;
83 rate_mhz = rate_mhz >> od >> od2;
84 } else
85 rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;
79 86
80 return rate_mhz * 1000000; 87 return rate_mhz * 1000000;
81} 88}
@@ -84,7 +91,7 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
84 unsigned long *parent_rate) 91 unsigned long *parent_rate)
85{ 92{
86 struct meson_clk_pll *pll = to_meson_clk_pll(hw); 93 struct meson_clk_pll *pll = to_meson_clk_pll(hw);
87 const struct pll_rate_table *rate_table = pll->conf->rate_table; 94 const struct pll_rate_table *rate_table = pll->rate_table;
88 int i; 95 int i;
89 96
90 for (i = 0; i < pll->rate_count; i++) { 97 for (i = 0; i < pll->rate_count; i++) {
@@ -99,7 +106,7 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
99static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_pll *pll, 106static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_pll *pll,
100 unsigned long rate) 107 unsigned long rate)
101{ 108{
102 const struct pll_rate_table *rate_table = pll->conf->rate_table; 109 const struct pll_rate_table *rate_table = pll->rate_table;
103 int i; 110 int i;
104 111
105 for (i = 0; i < pll->rate_count; i++) { 112 for (i = 0; i < pll->rate_count; i++) {
@@ -145,24 +152,38 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
145 return -EINVAL; 152 return -EINVAL;
146 153
147 /* PLL reset */ 154 /* PLL reset */
148 p = &pll->conf->n; 155 p = &pll->n;
149 reg = readl(pll->base + p->reg_off); 156 reg = readl(pll->base + p->reg_off);
150 writel(reg | MESON_PLL_RESET, pll->base + p->reg_off); 157 writel(reg | MESON_PLL_RESET, pll->base + p->reg_off);
151 158
152 reg = PARM_SET(p->width, p->shift, reg, rate_set->n); 159 reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
153 writel(reg, pll->base + p->reg_off); 160 writel(reg, pll->base + p->reg_off);
154 161
155 p = &pll->conf->m; 162 p = &pll->m;
156 reg = readl(pll->base + p->reg_off); 163 reg = readl(pll->base + p->reg_off);
157 reg = PARM_SET(p->width, p->shift, reg, rate_set->m); 164 reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
158 writel(reg, pll->base + p->reg_off); 165 writel(reg, pll->base + p->reg_off);
159 166
160 p = &pll->conf->od; 167 p = &pll->od;
161 reg = readl(pll->base + p->reg_off); 168 reg = readl(pll->base + p->reg_off);
162 reg = PARM_SET(p->width, p->shift, reg, rate_set->od); 169 reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
163 writel(reg, pll->base + p->reg_off); 170 writel(reg, pll->base + p->reg_off);
164 171
165 p = &pll->conf->n; 172 p = &pll->od2;
173 if (p->width) {
174 reg = readl(pll->base + p->reg_off);
175 reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
176 writel(reg, pll->base + p->reg_off);
177 }
178
179 p = &pll->frac;
180 if (p->width) {
181 reg = readl(pll->base + p->reg_off);
182 reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
183 writel(reg, pll->base + p->reg_off);
184 }
185
186 p = &pll->n;
166 ret = meson_clk_pll_wait_lock(pll, p); 187 ret = meson_clk_pll_wait_lock(pll, p);
167 if (ret) { 188 if (ret) {
168 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", 189 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
@@ -173,55 +194,12 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
173 return ret; 194 return ret;
174} 195}
175 196
176static const struct clk_ops meson_clk_pll_ops = { 197const struct clk_ops meson_clk_pll_ops = {
177 .recalc_rate = meson_clk_pll_recalc_rate, 198 .recalc_rate = meson_clk_pll_recalc_rate,
178 .round_rate = meson_clk_pll_round_rate, 199 .round_rate = meson_clk_pll_round_rate,
179 .set_rate = meson_clk_pll_set_rate, 200 .set_rate = meson_clk_pll_set_rate,
180}; 201};
181 202
182static const struct clk_ops meson_clk_pll_ro_ops = { 203const struct clk_ops meson_clk_pll_ro_ops = {
183 .recalc_rate = meson_clk_pll_recalc_rate, 204 .recalc_rate = meson_clk_pll_recalc_rate,
184}; 205};
185
186struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
187 void __iomem *reg_base,
188 spinlock_t *lock)
189{
190 struct clk *clk;
191 struct meson_clk_pll *clk_pll;
192 struct clk_init_data init;
193
194 clk_pll = kzalloc(sizeof(*clk_pll), GFP_KERNEL);
195 if (!clk_pll)
196 return ERR_PTR(-ENOMEM);
197
198 clk_pll->base = reg_base + clk_conf->reg_off;
199 clk_pll->lock = lock;
200 clk_pll->conf = clk_conf->conf.pll;
201
202 init.name = clk_conf->clk_name;
203 init.flags = clk_conf->flags | CLK_GET_RATE_NOCACHE;
204
205 init.parent_names = &clk_conf->clks_parent[0];
206 init.num_parents = 1;
207 init.ops = &meson_clk_pll_ro_ops;
208
209 /* If no rate_table is specified we assume the PLL is read-only */
210 if (clk_pll->conf->rate_table) {
211 int len;
212
213 for (len = 0; clk_pll->conf->rate_table[len].rate != 0; )
214 len++;
215
216 clk_pll->rate_count = len;
217 init.ops = &meson_clk_pll_ops;
218 }
219
220 clk_pll->hw.init = &init;
221
222 clk = clk_register(NULL, &clk_pll->hw);
223 if (IS_ERR(clk))
224 kfree(clk_pll);
225
226 return clk;
227}
diff --git a/drivers/clk/meson/clkc.c b/drivers/clk/meson/clkc.c
deleted file mode 100644
index d920d410b51d..000000000000
--- a/drivers/clk/meson/clkc.c
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/mfd/syscon.h>
20#include <linux/slab.h>
21
22#include "clkc.h"
23
24static DEFINE_SPINLOCK(clk_lock);
25
26static struct clk **clks;
27static struct clk_onecell_data clk_data;
28
29struct clk ** __init meson_clk_init(struct device_node *np,
30 unsigned long nr_clks)
31{
32 clks = kcalloc(nr_clks, sizeof(*clks), GFP_KERNEL);
33 if (!clks)
34 return ERR_PTR(-ENOMEM);
35
36 clk_data.clks = clks;
37 clk_data.clk_num = nr_clks;
38 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
39
40 return clks;
41}
42
43static void meson_clk_add_lookup(struct clk *clk, unsigned int id)
44{
45 if (clks && id)
46 clks[id] = clk;
47}
48
49static struct clk * __init
50meson_clk_register_composite(const struct clk_conf *clk_conf,
51 void __iomem *clk_base)
52{
53 struct clk *clk;
54 struct clk_mux *mux = NULL;
55 struct clk_divider *div = NULL;
56 struct clk_gate *gate = NULL;
57 const struct clk_ops *mux_ops = NULL;
58 const struct composite_conf *composite_conf;
59
60 composite_conf = clk_conf->conf.composite;
61
62 if (clk_conf->num_parents > 1) {
63 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
64 if (!mux)
65 return ERR_PTR(-ENOMEM);
66
67 mux->reg = clk_base + clk_conf->reg_off
68 + composite_conf->mux_parm.reg_off;
69 mux->shift = composite_conf->mux_parm.shift;
70 mux->mask = BIT(composite_conf->mux_parm.width) - 1;
71 mux->flags = composite_conf->mux_flags;
72 mux->lock = &clk_lock;
73 mux->table = composite_conf->mux_table;
74 mux_ops = (composite_conf->mux_flags & CLK_MUX_READ_ONLY) ?
75 &clk_mux_ro_ops : &clk_mux_ops;
76 }
77
78 if (MESON_PARM_APPLICABLE(&composite_conf->div_parm)) {
79 div = kzalloc(sizeof(*div), GFP_KERNEL);
80 if (!div) {
81 clk = ERR_PTR(-ENOMEM);
82 goto error;
83 }
84
85 div->reg = clk_base + clk_conf->reg_off
86 + composite_conf->div_parm.reg_off;
87 div->shift = composite_conf->div_parm.shift;
88 div->width = composite_conf->div_parm.width;
89 div->lock = &clk_lock;
90 div->flags = composite_conf->div_flags;
91 div->table = composite_conf->div_table;
92 }
93
94 if (MESON_PARM_APPLICABLE(&composite_conf->gate_parm)) {
95 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
96 if (!gate) {
97 clk = ERR_PTR(-ENOMEM);
98 goto error;
99 }
100
101 gate->reg = clk_base + clk_conf->reg_off
102 + composite_conf->div_parm.reg_off;
103 gate->bit_idx = composite_conf->gate_parm.shift;
104 gate->flags = composite_conf->gate_flags;
105 gate->lock = &clk_lock;
106 }
107
108 clk = clk_register_composite(NULL, clk_conf->clk_name,
109 clk_conf->clks_parent,
110 clk_conf->num_parents,
111 mux ? &mux->hw : NULL, mux_ops,
112 div ? &div->hw : NULL, &clk_divider_ops,
113 gate ? &gate->hw : NULL, &clk_gate_ops,
114 clk_conf->flags);
115 if (IS_ERR(clk))
116 goto error;
117
118 return clk;
119
120error:
121 kfree(gate);
122 kfree(div);
123 kfree(mux);
124
125 return clk;
126}
127
128static struct clk * __init
129meson_clk_register_fixed_factor(const struct clk_conf *clk_conf,
130 void __iomem *clk_base)
131{
132 struct clk *clk;
133 const struct fixed_fact_conf *fixed_fact_conf;
134 const struct parm *p;
135 unsigned int mult, div;
136 u32 reg;
137
138 fixed_fact_conf = &clk_conf->conf.fixed_fact;
139
140 mult = clk_conf->conf.fixed_fact.mult;
141 div = clk_conf->conf.fixed_fact.div;
142
143 if (!mult) {
144 mult = 1;
145 p = &fixed_fact_conf->mult_parm;
146 if (MESON_PARM_APPLICABLE(p)) {
147 reg = readl(clk_base + clk_conf->reg_off + p->reg_off);
148 mult = PARM_GET(p->width, p->shift, reg);
149 }
150 }
151
152 if (!div) {
153 div = 1;
154 p = &fixed_fact_conf->div_parm;
155 if (MESON_PARM_APPLICABLE(p)) {
156 reg = readl(clk_base + clk_conf->reg_off + p->reg_off);
157 mult = PARM_GET(p->width, p->shift, reg);
158 }
159 }
160
161 clk = clk_register_fixed_factor(NULL,
162 clk_conf->clk_name,
163 clk_conf->clks_parent[0],
164 clk_conf->flags,
165 mult, div);
166
167 return clk;
168}
169
170static struct clk * __init
171meson_clk_register_fixed_rate(const struct clk_conf *clk_conf,
172 void __iomem *clk_base)
173{
174 struct clk *clk;
175 const struct fixed_rate_conf *fixed_rate_conf;
176 const struct parm *r;
177 unsigned long rate;
178 u32 reg;
179
180 fixed_rate_conf = &clk_conf->conf.fixed_rate;
181 rate = fixed_rate_conf->rate;
182
183 if (!rate) {
184 r = &fixed_rate_conf->rate_parm;
185 reg = readl(clk_base + clk_conf->reg_off + r->reg_off);
186 rate = PARM_GET(r->width, r->shift, reg);
187 }
188
189 rate *= 1000000;
190
191 clk = clk_register_fixed_rate(NULL,
192 clk_conf->clk_name,
193 clk_conf->num_parents
194 ? clk_conf->clks_parent[0] : NULL,
195 clk_conf->flags, rate);
196
197 return clk;
198}
199
200void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
201 unsigned int nr_confs,
202 void __iomem *clk_base)
203{
204 unsigned int i;
205 struct clk *clk = NULL;
206
207 for (i = 0; i < nr_confs; i++) {
208 const struct clk_conf *clk_conf = &clk_confs[i];
209
210 switch (clk_conf->clk_type) {
211 case CLK_FIXED_RATE:
212 clk = meson_clk_register_fixed_rate(clk_conf,
213 clk_base);
214 break;
215 case CLK_FIXED_FACTOR:
216 clk = meson_clk_register_fixed_factor(clk_conf,
217 clk_base);
218 break;
219 case CLK_COMPOSITE:
220 clk = meson_clk_register_composite(clk_conf,
221 clk_base);
222 break;
223 case CLK_CPU:
224 clk = meson_clk_register_cpu(clk_conf, clk_base,
225 &clk_lock);
226 break;
227 case CLK_PLL:
228 clk = meson_clk_register_pll(clk_conf, clk_base,
229 &clk_lock);
230 break;
231 default:
232 clk = NULL;
233 }
234
235 if (!clk) {
236 pr_err("%s: unknown clock type %d\n", __func__,
237 clk_conf->clk_type);
238 continue;
239 }
240
241 if (IS_ERR(clk)) {
242 pr_warn("%s: Unable to create %s clock\n", __func__,
243 clk_conf->clk_name);
244 continue;
245 }
246
247 meson_clk_add_lookup(clk, clk_conf->clk_id);
248 }
249}
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 609ae92cc13f..53326c32e853 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -34,19 +34,16 @@ struct parm {
34 u8 shift; 34 u8 shift;
35 u8 width; 35 u8 width;
36}; 36};
37#define PARM(_r, _s, _w) \
38 { \
39 .reg_off = (_r), \
40 .shift = (_s), \
41 .width = (_w), \
42 } \
43 37
44struct pll_rate_table { 38struct pll_rate_table {
45 unsigned long rate; 39 unsigned long rate;
46 u16 m; 40 u16 m;
47 u16 n; 41 u16 n;
48 u16 od; 42 u16 od;
43 u16 od2;
44 u16 frac;
49}; 45};
46
50#define PLL_RATE(_r, _m, _n, _od) \ 47#define PLL_RATE(_r, _m, _n, _od) \
51 { \ 48 { \
52 .rate = (_r), \ 49 .rate = (_r), \
@@ -55,133 +52,69 @@ struct pll_rate_table {
55 .od = (_od), \ 52 .od = (_od), \
56 } \ 53 } \
57 54
58struct pll_conf { 55#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \
59 const struct pll_rate_table *rate_table; 56 { \
60 struct parm m; 57 .rate = (_r), \
61 struct parm n; 58 .m = (_m), \
62 struct parm od; 59 .n = (_n), \
63}; 60 .od = (_od), \
61 .od2 = (_od2), \
62 .frac = (_frac), \
63 } \
64 64
65struct fixed_fact_conf { 65struct meson_clk_pll {
66 unsigned int div; 66 struct clk_hw hw;
67 unsigned int mult; 67 void __iomem *base;
68 struct parm div_parm; 68 struct parm m;
69 struct parm mult_parm; 69 struct parm n;
70 struct parm frac;
71 struct parm od;
72 struct parm od2;
73 const struct pll_rate_table *rate_table;
74 unsigned int rate_count;
75 spinlock_t *lock;
70}; 76};
71 77
72struct fixed_rate_conf { 78#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
73 unsigned long rate;
74 struct parm rate_parm;
75};
76 79
77struct composite_conf { 80struct meson_clk_cpu {
78 struct parm mux_parm; 81 struct clk_hw hw;
79 struct parm div_parm; 82 void __iomem *base;
80 struct parm gate_parm; 83 u16 reg_off;
81 struct clk_div_table *div_table; 84 struct notifier_block clk_nb;
82 u32 *mux_table; 85 const struct clk_div_table *div_table;
83 u8 mux_flags;
84 u8 div_flags;
85 u8 gate_flags;
86}; 86};
87 87
88#define PNAME(x) static const char *x[] 88int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event,
89 void *data);
89 90
90enum clk_type { 91struct meson_clk_mpll {
91 CLK_FIXED_FACTOR, 92 struct clk_hw hw;
92 CLK_FIXED_RATE, 93 void __iomem *base;
93 CLK_COMPOSITE, 94 struct parm sdm;
94 CLK_CPU, 95 struct parm n2;
95 CLK_PLL, 96 /* FIXME ssen gate control? */
97 spinlock_t *lock;
96}; 98};
97 99
98struct clk_conf { 100#define MESON_GATE(_name, _reg, _bit) \
99 u16 reg_off; 101struct clk_gate gxbb_##_name = { \
100 enum clk_type clk_type; 102 .reg = (void __iomem *) _reg, \
101 unsigned int clk_id; 103 .bit_idx = (_bit), \
102 const char *clk_name; 104 .lock = &clk_lock, \
103 const char **clks_parent; 105 .hw.init = &(struct clk_init_data) { \
104 int num_parents; 106 .name = #_name, \
105 unsigned long flags; 107 .ops = &clk_gate_ops, \
106 union { 108 .parent_names = (const char *[]){ "clk81" }, \
107 struct fixed_fact_conf fixed_fact; 109 .num_parents = 1, \
108 struct fixed_rate_conf fixed_rate; 110 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
109 const struct composite_conf *composite; 111 }, \
110 struct pll_conf *pll;
111 const struct clk_div_table *div_table;
112 } conf;
113}; 112};
114 113
115#define FIXED_RATE_P(_ro, _ci, _cn, _f, _c) \ 114/* clk_ops */
116 { \ 115extern const struct clk_ops meson_clk_pll_ro_ops;
117 .reg_off = (_ro), \ 116extern const struct clk_ops meson_clk_pll_ops;
118 .clk_type = CLK_FIXED_RATE, \ 117extern const struct clk_ops meson_clk_cpu_ops;
119 .clk_id = (_ci), \ 118extern const struct clk_ops meson_clk_mpll_ro_ops;
120 .clk_name = (_cn), \
121 .flags = (_f), \
122 .conf.fixed_rate.rate_parm = _c, \
123 } \
124
125#define FIXED_RATE(_ci, _cn, _f, _r) \
126 { \
127 .clk_type = CLK_FIXED_RATE, \
128 .clk_id = (_ci), \
129 .clk_name = (_cn), \
130 .flags = (_f), \
131 .conf.fixed_rate.rate = (_r), \
132 } \
133
134#define PLL(_ro, _ci, _cn, _cp, _f, _c) \
135 { \
136 .reg_off = (_ro), \
137 .clk_type = CLK_PLL, \
138 .clk_id = (_ci), \
139 .clk_name = (_cn), \
140 .clks_parent = (_cp), \
141 .num_parents = ARRAY_SIZE(_cp), \
142 .flags = (_f), \
143 .conf.pll = (_c), \
144 } \
145
146#define FIXED_FACTOR_DIV(_ci, _cn, _cp, _f, _d) \
147 { \
148 .clk_type = CLK_FIXED_FACTOR, \
149 .clk_id = (_ci), \
150 .clk_name = (_cn), \
151 .clks_parent = (_cp), \
152 .num_parents = ARRAY_SIZE(_cp), \
153 .conf.fixed_fact.div = (_d), \
154 } \
155
156#define CPU(_ro, _ci, _cn, _cp, _dt) \
157 { \
158 .reg_off = (_ro), \
159 .clk_type = CLK_CPU, \
160 .clk_id = (_ci), \
161 .clk_name = (_cn), \
162 .clks_parent = (_cp), \
163 .num_parents = ARRAY_SIZE(_cp), \
164 .conf.div_table = (_dt), \
165 } \
166
167#define COMPOSITE(_ro, _ci, _cn, _cp, _f, _c) \
168 { \
169 .reg_off = (_ro), \
170 .clk_type = CLK_COMPOSITE, \
171 .clk_id = (_ci), \
172 .clk_name = (_cn), \
173 .clks_parent = (_cp), \
174 .num_parents = ARRAY_SIZE(_cp), \
175 .flags = (_f), \
176 .conf.composite = (_c), \
177 } \
178
179struct clk **meson_clk_init(struct device_node *np, unsigned long nr_clks);
180void meson_clk_register_clks(const struct clk_conf *clk_confs,
181 unsigned int nr_confs, void __iomem *clk_base);
182struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
183 void __iomem *reg_base, spinlock_t *lock);
184struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
185 void __iomem *reg_base, spinlock_t *lock);
186 119
187#endif /* __CLKC_H */ 120#endif /* __CLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
new file mode 100644
index 000000000000..a4c6684b3019
--- /dev/null
+++ b/drivers/clk/meson/gxbb.c
@@ -0,0 +1,944 @@
1/*
2 * AmLogic S905 / GXBB Clock Controller Driver
3 *
4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/of_address.h>
23#include <linux/platform_device.h>
24#include <linux/init.h>
25
26#include "clkc.h"
27#include "gxbb.h"
28
29static DEFINE_SPINLOCK(clk_lock);
30
31static const struct pll_rate_table sys_pll_rate_table[] = {
32 PLL_RATE(24000000, 56, 1, 2),
33 PLL_RATE(48000000, 64, 1, 2),
34 PLL_RATE(72000000, 72, 1, 2),
35 PLL_RATE(96000000, 64, 1, 2),
36 PLL_RATE(120000000, 80, 1, 2),
37 PLL_RATE(144000000, 96, 1, 2),
38 PLL_RATE(168000000, 56, 1, 1),
39 PLL_RATE(192000000, 64, 1, 1),
40 PLL_RATE(216000000, 72, 1, 1),
41 PLL_RATE(240000000, 80, 1, 1),
42 PLL_RATE(264000000, 88, 1, 1),
43 PLL_RATE(288000000, 96, 1, 1),
44 PLL_RATE(312000000, 52, 1, 2),
45 PLL_RATE(336000000, 56, 1, 2),
46 PLL_RATE(360000000, 60, 1, 2),
47 PLL_RATE(384000000, 64, 1, 2),
48 PLL_RATE(408000000, 68, 1, 2),
49 PLL_RATE(432000000, 72, 1, 2),
50 PLL_RATE(456000000, 76, 1, 2),
51 PLL_RATE(480000000, 80, 1, 2),
52 PLL_RATE(504000000, 84, 1, 2),
53 PLL_RATE(528000000, 88, 1, 2),
54 PLL_RATE(552000000, 92, 1, 2),
55 PLL_RATE(576000000, 96, 1, 2),
56 PLL_RATE(600000000, 50, 1, 1),
57 PLL_RATE(624000000, 52, 1, 1),
58 PLL_RATE(648000000, 54, 1, 1),
59 PLL_RATE(672000000, 56, 1, 1),
60 PLL_RATE(696000000, 58, 1, 1),
61 PLL_RATE(720000000, 60, 1, 1),
62 PLL_RATE(744000000, 62, 1, 1),
63 PLL_RATE(768000000, 64, 1, 1),
64 PLL_RATE(792000000, 66, 1, 1),
65 PLL_RATE(816000000, 68, 1, 1),
66 PLL_RATE(840000000, 70, 1, 1),
67 PLL_RATE(864000000, 72, 1, 1),
68 PLL_RATE(888000000, 74, 1, 1),
69 PLL_RATE(912000000, 76, 1, 1),
70 PLL_RATE(936000000, 78, 1, 1),
71 PLL_RATE(960000000, 80, 1, 1),
72 PLL_RATE(984000000, 82, 1, 1),
73 PLL_RATE(1008000000, 84, 1, 1),
74 PLL_RATE(1032000000, 86, 1, 1),
75 PLL_RATE(1056000000, 88, 1, 1),
76 PLL_RATE(1080000000, 90, 1, 1),
77 PLL_RATE(1104000000, 92, 1, 1),
78 PLL_RATE(1128000000, 94, 1, 1),
79 PLL_RATE(1152000000, 96, 1, 1),
80 PLL_RATE(1176000000, 98, 1, 1),
81 PLL_RATE(1200000000, 50, 1, 0),
82 PLL_RATE(1224000000, 51, 1, 0),
83 PLL_RATE(1248000000, 52, 1, 0),
84 PLL_RATE(1272000000, 53, 1, 0),
85 PLL_RATE(1296000000, 54, 1, 0),
86 PLL_RATE(1320000000, 55, 1, 0),
87 PLL_RATE(1344000000, 56, 1, 0),
88 PLL_RATE(1368000000, 57, 1, 0),
89 PLL_RATE(1392000000, 58, 1, 0),
90 PLL_RATE(1416000000, 59, 1, 0),
91 PLL_RATE(1440000000, 60, 1, 0),
92 PLL_RATE(1464000000, 61, 1, 0),
93 PLL_RATE(1488000000, 62, 1, 0),
94 PLL_RATE(1512000000, 63, 1, 0),
95 PLL_RATE(1536000000, 64, 1, 0),
96 PLL_RATE(1560000000, 65, 1, 0),
97 PLL_RATE(1584000000, 66, 1, 0),
98 PLL_RATE(1608000000, 67, 1, 0),
99 PLL_RATE(1632000000, 68, 1, 0),
100 PLL_RATE(1656000000, 68, 1, 0),
101 PLL_RATE(1680000000, 68, 1, 0),
102 PLL_RATE(1704000000, 68, 1, 0),
103 PLL_RATE(1728000000, 69, 1, 0),
104 PLL_RATE(1752000000, 69, 1, 0),
105 PLL_RATE(1776000000, 69, 1, 0),
106 PLL_RATE(1800000000, 69, 1, 0),
107 PLL_RATE(1824000000, 70, 1, 0),
108 PLL_RATE(1848000000, 70, 1, 0),
109 PLL_RATE(1872000000, 70, 1, 0),
110 PLL_RATE(1896000000, 70, 1, 0),
111 PLL_RATE(1920000000, 71, 1, 0),
112 PLL_RATE(1944000000, 71, 1, 0),
113 PLL_RATE(1968000000, 71, 1, 0),
114 PLL_RATE(1992000000, 71, 1, 0),
115 PLL_RATE(2016000000, 72, 1, 0),
116 PLL_RATE(2040000000, 72, 1, 0),
117 PLL_RATE(2064000000, 72, 1, 0),
118 PLL_RATE(2088000000, 72, 1, 0),
119 PLL_RATE(2112000000, 73, 1, 0),
120 { /* sentinel */ },
121};
122
123static const struct pll_rate_table gp0_pll_rate_table[] = {
124 PLL_RATE(96000000, 32, 1, 3),
125 PLL_RATE(99000000, 33, 1, 3),
126 PLL_RATE(102000000, 34, 1, 3),
127 PLL_RATE(105000000, 35, 1, 3),
128 PLL_RATE(108000000, 36, 1, 3),
129 PLL_RATE(111000000, 37, 1, 3),
130 PLL_RATE(114000000, 38, 1, 3),
131 PLL_RATE(117000000, 39, 1, 3),
132 PLL_RATE(120000000, 40, 1, 3),
133 PLL_RATE(123000000, 41, 1, 3),
134 PLL_RATE(126000000, 42, 1, 3),
135 PLL_RATE(129000000, 43, 1, 3),
136 PLL_RATE(132000000, 44, 1, 3),
137 PLL_RATE(135000000, 45, 1, 3),
138 PLL_RATE(138000000, 46, 1, 3),
139 PLL_RATE(141000000, 47, 1, 3),
140 PLL_RATE(144000000, 48, 1, 3),
141 PLL_RATE(147000000, 49, 1, 3),
142 PLL_RATE(150000000, 50, 1, 3),
143 PLL_RATE(153000000, 51, 1, 3),
144 PLL_RATE(156000000, 52, 1, 3),
145 PLL_RATE(159000000, 53, 1, 3),
146 PLL_RATE(162000000, 54, 1, 3),
147 PLL_RATE(165000000, 55, 1, 3),
148 PLL_RATE(168000000, 56, 1, 3),
149 PLL_RATE(171000000, 57, 1, 3),
150 PLL_RATE(174000000, 58, 1, 3),
151 PLL_RATE(177000000, 59, 1, 3),
152 PLL_RATE(180000000, 60, 1, 3),
153 PLL_RATE(183000000, 61, 1, 3),
154 PLL_RATE(186000000, 62, 1, 3),
155 PLL_RATE(192000000, 32, 1, 2),
156 PLL_RATE(198000000, 33, 1, 2),
157 PLL_RATE(204000000, 34, 1, 2),
158 PLL_RATE(210000000, 35, 1, 2),
159 PLL_RATE(216000000, 36, 1, 2),
160 PLL_RATE(222000000, 37, 1, 2),
161 PLL_RATE(228000000, 38, 1, 2),
162 PLL_RATE(234000000, 39, 1, 2),
163 PLL_RATE(240000000, 40, 1, 2),
164 PLL_RATE(246000000, 41, 1, 2),
165 PLL_RATE(252000000, 42, 1, 2),
166 PLL_RATE(258000000, 43, 1, 2),
167 PLL_RATE(264000000, 44, 1, 2),
168 PLL_RATE(270000000, 45, 1, 2),
169 PLL_RATE(276000000, 46, 1, 2),
170 PLL_RATE(282000000, 47, 1, 2),
171 PLL_RATE(288000000, 48, 1, 2),
172 PLL_RATE(294000000, 49, 1, 2),
173 PLL_RATE(300000000, 50, 1, 2),
174 PLL_RATE(306000000, 51, 1, 2),
175 PLL_RATE(312000000, 52, 1, 2),
176 PLL_RATE(318000000, 53, 1, 2),
177 PLL_RATE(324000000, 54, 1, 2),
178 PLL_RATE(330000000, 55, 1, 2),
179 PLL_RATE(336000000, 56, 1, 2),
180 PLL_RATE(342000000, 57, 1, 2),
181 PLL_RATE(348000000, 58, 1, 2),
182 PLL_RATE(354000000, 59, 1, 2),
183 PLL_RATE(360000000, 60, 1, 2),
184 PLL_RATE(366000000, 61, 1, 2),
185 PLL_RATE(372000000, 62, 1, 2),
186 PLL_RATE(384000000, 32, 1, 1),
187 PLL_RATE(396000000, 33, 1, 1),
188 PLL_RATE(408000000, 34, 1, 1),
189 PLL_RATE(420000000, 35, 1, 1),
190 PLL_RATE(432000000, 36, 1, 1),
191 PLL_RATE(444000000, 37, 1, 1),
192 PLL_RATE(456000000, 38, 1, 1),
193 PLL_RATE(468000000, 39, 1, 1),
194 PLL_RATE(480000000, 40, 1, 1),
195 PLL_RATE(492000000, 41, 1, 1),
196 PLL_RATE(504000000, 42, 1, 1),
197 PLL_RATE(516000000, 43, 1, 1),
198 PLL_RATE(528000000, 44, 1, 1),
199 PLL_RATE(540000000, 45, 1, 1),
200 PLL_RATE(552000000, 46, 1, 1),
201 PLL_RATE(564000000, 47, 1, 1),
202 PLL_RATE(576000000, 48, 1, 1),
203 PLL_RATE(588000000, 49, 1, 1),
204 PLL_RATE(600000000, 50, 1, 1),
205 PLL_RATE(612000000, 51, 1, 1),
206 PLL_RATE(624000000, 52, 1, 1),
207 PLL_RATE(636000000, 53, 1, 1),
208 PLL_RATE(648000000, 54, 1, 1),
209 PLL_RATE(660000000, 55, 1, 1),
210 PLL_RATE(672000000, 56, 1, 1),
211 PLL_RATE(684000000, 57, 1, 1),
212 PLL_RATE(696000000, 58, 1, 1),
213 PLL_RATE(708000000, 59, 1, 1),
214 PLL_RATE(720000000, 60, 1, 1),
215 PLL_RATE(732000000, 61, 1, 1),
216 PLL_RATE(744000000, 62, 1, 1),
217 PLL_RATE(768000000, 32, 1, 0),
218 PLL_RATE(792000000, 33, 1, 0),
219 PLL_RATE(816000000, 34, 1, 0),
220 PLL_RATE(840000000, 35, 1, 0),
221 PLL_RATE(864000000, 36, 1, 0),
222 PLL_RATE(888000000, 37, 1, 0),
223 PLL_RATE(912000000, 38, 1, 0),
224 PLL_RATE(936000000, 39, 1, 0),
225 PLL_RATE(960000000, 40, 1, 0),
226 PLL_RATE(984000000, 41, 1, 0),
227 PLL_RATE(1008000000, 42, 1, 0),
228 PLL_RATE(1032000000, 43, 1, 0),
229 PLL_RATE(1056000000, 44, 1, 0),
230 PLL_RATE(1080000000, 45, 1, 0),
231 PLL_RATE(1104000000, 46, 1, 0),
232 PLL_RATE(1128000000, 47, 1, 0),
233 PLL_RATE(1152000000, 48, 1, 0),
234 PLL_RATE(1176000000, 49, 1, 0),
235 PLL_RATE(1200000000, 50, 1, 0),
236 PLL_RATE(1224000000, 51, 1, 0),
237 PLL_RATE(1248000000, 52, 1, 0),
238 PLL_RATE(1272000000, 53, 1, 0),
239 PLL_RATE(1296000000, 54, 1, 0),
240 PLL_RATE(1320000000, 55, 1, 0),
241 PLL_RATE(1344000000, 56, 1, 0),
242 PLL_RATE(1368000000, 57, 1, 0),
243 PLL_RATE(1392000000, 58, 1, 0),
244 PLL_RATE(1416000000, 59, 1, 0),
245 PLL_RATE(1440000000, 60, 1, 0),
246 PLL_RATE(1464000000, 61, 1, 0),
247 PLL_RATE(1488000000, 62, 1, 0),
248 { /* sentinel */ },
249};
250
251static const struct clk_div_table cpu_div_table[] = {
252 { .val = 1, .div = 1 },
253 { .val = 2, .div = 2 },
254 { .val = 3, .div = 3 },
255 { .val = 2, .div = 4 },
256 { .val = 3, .div = 6 },
257 { .val = 4, .div = 8 },
258 { .val = 5, .div = 10 },
259 { .val = 6, .div = 12 },
260 { .val = 7, .div = 14 },
261 { .val = 8, .div = 16 },
262 { /* sentinel */ },
263};
264
265static struct meson_clk_pll gxbb_fixed_pll = {
266 .m = {
267 .reg_off = HHI_MPLL_CNTL,
268 .shift = 0,
269 .width = 9,
270 },
271 .n = {
272 .reg_off = HHI_MPLL_CNTL,
273 .shift = 9,
274 .width = 5,
275 },
276 .od = {
277 .reg_off = HHI_MPLL_CNTL,
278 .shift = 16,
279 .width = 2,
280 },
281 .lock = &clk_lock,
282 .hw.init = &(struct clk_init_data){
283 .name = "fixed_pll",
284 .ops = &meson_clk_pll_ro_ops,
285 .parent_names = (const char *[]){ "xtal" },
286 .num_parents = 1,
287 .flags = CLK_GET_RATE_NOCACHE,
288 },
289};
290
291static struct meson_clk_pll gxbb_hdmi_pll = {
292 .m = {
293 .reg_off = HHI_HDMI_PLL_CNTL,
294 .shift = 0,
295 .width = 9,
296 },
297 .n = {
298 .reg_off = HHI_HDMI_PLL_CNTL,
299 .shift = 9,
300 .width = 5,
301 },
302 .frac = {
303 .reg_off = HHI_HDMI_PLL_CNTL2,
304 .shift = 0,
305 .width = 12,
306 },
307 .od = {
308 .reg_off = HHI_HDMI_PLL_CNTL2,
309 .shift = 16,
310 .width = 2,
311 },
312 .od2 = {
313 .reg_off = HHI_HDMI_PLL_CNTL2,
314 .shift = 22,
315 .width = 2,
316 },
317 .lock = &clk_lock,
318 .hw.init = &(struct clk_init_data){
319 .name = "hdmi_pll",
320 .ops = &meson_clk_pll_ro_ops,
321 .parent_names = (const char *[]){ "xtal" },
322 .num_parents = 1,
323 .flags = CLK_GET_RATE_NOCACHE,
324 },
325};
326
327static struct meson_clk_pll gxbb_sys_pll = {
328 .m = {
329 .reg_off = HHI_SYS_PLL_CNTL,
330 .shift = 0,
331 .width = 9,
332 },
333 .n = {
334 .reg_off = HHI_SYS_PLL_CNTL,
335 .shift = 9,
336 .width = 5,
337 },
338 .od = {
339 .reg_off = HHI_SYS_PLL_CNTL,
340 .shift = 10,
341 .width = 2,
342 },
343 .rate_table = sys_pll_rate_table,
344 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
345 .lock = &clk_lock,
346 .hw.init = &(struct clk_init_data){
347 .name = "sys_pll",
348 .ops = &meson_clk_pll_ro_ops,
349 .parent_names = (const char *[]){ "xtal" },
350 .num_parents = 1,
351 .flags = CLK_GET_RATE_NOCACHE,
352 },
353};
354
355static struct meson_clk_pll gxbb_gp0_pll = {
356 .m = {
357 .reg_off = HHI_GP0_PLL_CNTL,
358 .shift = 0,
359 .width = 9,
360 },
361 .n = {
362 .reg_off = HHI_GP0_PLL_CNTL,
363 .shift = 9,
364 .width = 5,
365 },
366 .od = {
367 .reg_off = HHI_GP0_PLL_CNTL,
368 .shift = 16,
369 .width = 2,
370 },
371 .rate_table = gp0_pll_rate_table,
372 .rate_count = ARRAY_SIZE(gp0_pll_rate_table),
373 .lock = &clk_lock,
374 .hw.init = &(struct clk_init_data){
375 .name = "gp0_pll",
376 .ops = &meson_clk_pll_ops,
377 .parent_names = (const char *[]){ "xtal" },
378 .num_parents = 1,
379 .flags = CLK_GET_RATE_NOCACHE,
380 },
381};
382
383static struct clk_fixed_factor gxbb_fclk_div2 = {
384 .mult = 1,
385 .div = 2,
386 .hw.init = &(struct clk_init_data){
387 .name = "fclk_div2",
388 .ops = &clk_fixed_factor_ops,
389 .parent_names = (const char *[]){ "fixed_pll" },
390 .num_parents = 1,
391 },
392};
393
394static struct clk_fixed_factor gxbb_fclk_div3 = {
395 .mult = 1,
396 .div = 3,
397 .hw.init = &(struct clk_init_data){
398 .name = "fclk_div3",
399 .ops = &clk_fixed_factor_ops,
400 .parent_names = (const char *[]){ "fixed_pll" },
401 .num_parents = 1,
402 },
403};
404
405static struct clk_fixed_factor gxbb_fclk_div4 = {
406 .mult = 1,
407 .div = 4,
408 .hw.init = &(struct clk_init_data){
409 .name = "fclk_div4",
410 .ops = &clk_fixed_factor_ops,
411 .parent_names = (const char *[]){ "fixed_pll" },
412 .num_parents = 1,
413 },
414};
415
416static struct clk_fixed_factor gxbb_fclk_div5 = {
417 .mult = 1,
418 .div = 5,
419 .hw.init = &(struct clk_init_data){
420 .name = "fclk_div5",
421 .ops = &clk_fixed_factor_ops,
422 .parent_names = (const char *[]){ "fixed_pll" },
423 .num_parents = 1,
424 },
425};
426
427static struct clk_fixed_factor gxbb_fclk_div7 = {
428 .mult = 1,
429 .div = 7,
430 .hw.init = &(struct clk_init_data){
431 .name = "fclk_div7",
432 .ops = &clk_fixed_factor_ops,
433 .parent_names = (const char *[]){ "fixed_pll" },
434 .num_parents = 1,
435 },
436};
437
438static struct meson_clk_mpll gxbb_mpll0 = {
439 .sdm = {
440 .reg_off = HHI_MPLL_CNTL7,
441 .shift = 0,
442 .width = 14,
443 },
444 .n2 = {
445 .reg_off = HHI_MPLL_CNTL7,
446 .shift = 16,
447 .width = 9,
448 },
449 .lock = &clk_lock,
450 .hw.init = &(struct clk_init_data){
451 .name = "mpll0",
452 .ops = &meson_clk_mpll_ro_ops,
453 .parent_names = (const char *[]){ "fixed_pll" },
454 .num_parents = 1,
455 },
456};
457
458static struct meson_clk_mpll gxbb_mpll1 = {
459 .sdm = {
460 .reg_off = HHI_MPLL_CNTL8,
461 .shift = 0,
462 .width = 14,
463 },
464 .n2 = {
465 .reg_off = HHI_MPLL_CNTL8,
466 .shift = 16,
467 .width = 9,
468 },
469 .lock = &clk_lock,
470 .hw.init = &(struct clk_init_data){
471 .name = "mpll1",
472 .ops = &meson_clk_mpll_ro_ops,
473 .parent_names = (const char *[]){ "fixed_pll" },
474 .num_parents = 1,
475 },
476};
477
478static struct meson_clk_mpll gxbb_mpll2 = {
479 .sdm = {
480 .reg_off = HHI_MPLL_CNTL9,
481 .shift = 0,
482 .width = 14,
483 },
484 .n2 = {
485 .reg_off = HHI_MPLL_CNTL9,
486 .shift = 16,
487 .width = 9,
488 },
489 .lock = &clk_lock,
490 .hw.init = &(struct clk_init_data){
491 .name = "mpll2",
492 .ops = &meson_clk_mpll_ro_ops,
493 .parent_names = (const char *[]){ "fixed_pll" },
494 .num_parents = 1,
495 },
496};
497
498/*
499 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
500 * post-dividers and should be modeled with their respective PLLs via the
501 * forthcoming coordinated clock rates feature
502 */
503static struct meson_clk_cpu gxbb_cpu_clk = {
504 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
505 .div_table = cpu_div_table,
506 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
507 .hw.init = &(struct clk_init_data){
508 .name = "cpu_clk",
509 .ops = &meson_clk_cpu_ops,
510 .parent_names = (const char *[]){ "sys_pll" },
511 .num_parents = 1,
512 },
513};
514
515static u32 mux_table_clk81[] = { 6, 5, 7 };
516
517static struct clk_mux gxbb_mpeg_clk_sel = {
518 .reg = (void *)HHI_MPEG_CLK_CNTL,
519 .mask = 0x7,
520 .shift = 12,
521 .flags = CLK_MUX_READ_ONLY,
522 .table = mux_table_clk81,
523 .lock = &clk_lock,
524 .hw.init = &(struct clk_init_data){
525 .name = "mpeg_clk_sel",
526 .ops = &clk_mux_ro_ops,
527 /*
528 * FIXME bits 14:12 selects from 8 possible parents:
529 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
530 * fclk_div4, fclk_div3, fclk_div5
531 */
532 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
533 "fclk_div5" },
534 .num_parents = 3,
535 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
536 },
537};
538
539static struct clk_divider gxbb_mpeg_clk_div = {
540 .reg = (void *)HHI_MPEG_CLK_CNTL,
541 .shift = 0,
542 .width = 7,
543 .lock = &clk_lock,
544 .hw.init = &(struct clk_init_data){
545 .name = "mpeg_clk_div",
546 .ops = &clk_divider_ops,
547 .parent_names = (const char *[]){ "mpeg_clk_sel" },
548 .num_parents = 1,
549 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
550 },
551};
552
553/* the mother of dragons^W gates */
554static struct clk_gate gxbb_clk81 = {
555 .reg = (void *)HHI_MPEG_CLK_CNTL,
556 .bit_idx = 7,
557 .lock = &clk_lock,
558 .hw.init = &(struct clk_init_data){
559 .name = "clk81",
560 .ops = &clk_gate_ops,
561 .parent_names = (const char *[]){ "mpeg_clk_div" },
562 .num_parents = 1,
563 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL),
564 },
565};
566
567/* Everything Else (EE) domain gates */
568static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
569static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);
570static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);
571static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);
572static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);
573static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);
574static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);
575static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
576static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);
577static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);
578static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);
579static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);
580static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);
581static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
582static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
583static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
584static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
585static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
586static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
587
588static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
589static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);
590static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);
591static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
592static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);
593static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
594static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);
595static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);
596static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);
597static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
598static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);
599static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);
600static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);
601static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);
602static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);
603static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);
604static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);
605static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);
606static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);
607static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
608static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);
609static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);
610static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
611static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);
612static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
613
614static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
615static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
616static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
617static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
618static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
619static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
620static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
621static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);
622static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);
623static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);
624static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
625static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
626static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);
627
628static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
629static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
630static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
631static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
632static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
633static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
634static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);
635static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
636static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
637static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);
638static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);
639static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
640static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
641static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
642static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);
643static MESON_GATE(edp, HHI_GCLK_OTHER, 31);
644
645/* Always On (AO) domain gates */
646
647static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
648static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
649static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
650static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);
651static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);
652
653/* Array of all clocks provided by this provider */
654
655static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
656 .hws = {
657 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
658 [CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
659 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
660 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
661 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
662 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
663 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
664 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
665 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
666 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
667 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
668 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
669 [CLKID_CLK81] = &gxbb_clk81.hw,
670 [CLKID_MPLL0] = &gxbb_mpll0.hw,
671 [CLKID_MPLL1] = &gxbb_mpll1.hw,
672 [CLKID_MPLL2] = &gxbb_mpll2.hw,
673 [CLKID_DDR] = &gxbb_ddr.hw,
674 [CLKID_DOS] = &gxbb_dos.hw,
675 [CLKID_ISA] = &gxbb_isa.hw,
676 [CLKID_PL301] = &gxbb_pl301.hw,
677 [CLKID_PERIPHS] = &gxbb_periphs.hw,
678 [CLKID_SPICC] = &gxbb_spicc.hw,
679 [CLKID_I2C] = &gxbb_i2c.hw,
680 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
681 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
682 [CLKID_RNG0] = &gxbb_rng0.hw,
683 [CLKID_UART0] = &gxbb_uart0.hw,
684 [CLKID_SDHC] = &gxbb_sdhc.hw,
685 [CLKID_STREAM] = &gxbb_stream.hw,
686 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
687 [CLKID_SDIO] = &gxbb_sdio.hw,
688 [CLKID_ABUF] = &gxbb_abuf.hw,
689 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
690 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
691 [CLKID_SPI] = &gxbb_spi.hw,
692 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
693 [CLKID_ETH] = &gxbb_eth.hw,
694 [CLKID_DEMUX] = &gxbb_demux.hw,
695 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
696 [CLKID_IEC958] = &gxbb_iec958.hw,
697 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
698 [CLKID_AMCLK] = &gxbb_amclk.hw,
699 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
700 [CLKID_MIXER] = &gxbb_mixer.hw,
701 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
702 [CLKID_ADC] = &gxbb_adc.hw,
703 [CLKID_BLKMV] = &gxbb_blkmv.hw,
704 [CLKID_AIU] = &gxbb_aiu.hw,
705 [CLKID_UART1] = &gxbb_uart1.hw,
706 [CLKID_G2D] = &gxbb_g2d.hw,
707 [CLKID_USB0] = &gxbb_usb0.hw,
708 [CLKID_USB1] = &gxbb_usb1.hw,
709 [CLKID_RESET] = &gxbb_reset.hw,
710 [CLKID_NAND] = &gxbb_nand.hw,
711 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
712 [CLKID_USB] = &gxbb_usb.hw,
713 [CLKID_VDIN1] = &gxbb_vdin1.hw,
714 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
715 [CLKID_EFUSE] = &gxbb_efuse.hw,
716 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
717 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
718 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
719 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
720 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
721 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
722 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
723 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
724 [CLKID_DVIN] = &gxbb_dvin.hw,
725 [CLKID_UART2] = &gxbb_uart2.hw,
726 [CLKID_SANA] = &gxbb_sana.hw,
727 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
728 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
729 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
730 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
731 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
732 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
733 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
734 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
735 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
736 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
737 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
738 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
739 [CLKID_ENC480P] = &gxbb_enc480p.hw,
740 [CLKID_RNG1] = &gxbb_rng1.hw,
741 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
742 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
743 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
744 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
745 [CLKID_EDP] = &gxbb_edp.hw,
746 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
747 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
748 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
749 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
750 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
751 },
752 .num = NR_CLKS,
753};
754
755/* Convenience tables to populate base addresses in .probe */
756
757static struct meson_clk_pll *const gxbb_clk_plls[] = {
758 &gxbb_fixed_pll,
759 &gxbb_hdmi_pll,
760 &gxbb_sys_pll,
761 &gxbb_gp0_pll,
762};
763
764static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
765 &gxbb_mpll0,
766 &gxbb_mpll1,
767 &gxbb_mpll2,
768};
769
770static struct clk_gate *gxbb_clk_gates[] = {
771 &gxbb_clk81,
772 &gxbb_ddr,
773 &gxbb_dos,
774 &gxbb_isa,
775 &gxbb_pl301,
776 &gxbb_periphs,
777 &gxbb_spicc,
778 &gxbb_i2c,
779 &gxbb_sar_adc,
780 &gxbb_smart_card,
781 &gxbb_rng0,
782 &gxbb_uart0,
783 &gxbb_sdhc,
784 &gxbb_stream,
785 &gxbb_async_fifo,
786 &gxbb_sdio,
787 &gxbb_abuf,
788 &gxbb_hiu_iface,
789 &gxbb_assist_misc,
790 &gxbb_spi,
791 &gxbb_i2s_spdif,
792 &gxbb_eth,
793 &gxbb_demux,
794 &gxbb_aiu_glue,
795 &gxbb_iec958,
796 &gxbb_i2s_out,
797 &gxbb_amclk,
798 &gxbb_aififo2,
799 &gxbb_mixer,
800 &gxbb_mixer_iface,
801 &gxbb_adc,
802 &gxbb_blkmv,
803 &gxbb_aiu,
804 &gxbb_uart1,
805 &gxbb_g2d,
806 &gxbb_usb0,
807 &gxbb_usb1,
808 &gxbb_reset,
809 &gxbb_nand,
810 &gxbb_dos_parser,
811 &gxbb_usb,
812 &gxbb_vdin1,
813 &gxbb_ahb_arb0,
814 &gxbb_efuse,
815 &gxbb_boot_rom,
816 &gxbb_ahb_data_bus,
817 &gxbb_ahb_ctrl_bus,
818 &gxbb_hdmi_intr_sync,
819 &gxbb_hdmi_pclk,
820 &gxbb_usb1_ddr_bridge,
821 &gxbb_usb0_ddr_bridge,
822 &gxbb_mmc_pclk,
823 &gxbb_dvin,
824 &gxbb_uart2,
825 &gxbb_sana,
826 &gxbb_vpu_intr,
827 &gxbb_sec_ahb_ahb3_bridge,
828 &gxbb_clk81_a53,
829 &gxbb_vclk2_venci0,
830 &gxbb_vclk2_venci1,
831 &gxbb_vclk2_vencp0,
832 &gxbb_vclk2_vencp1,
833 &gxbb_gclk_venci_int0,
834 &gxbb_gclk_vencp_int,
835 &gxbb_dac_clk,
836 &gxbb_aoclk_gate,
837 &gxbb_iec958_gate,
838 &gxbb_enc480p,
839 &gxbb_rng1,
840 &gxbb_gclk_venci_int1,
841 &gxbb_vclk2_venclmcc,
842 &gxbb_vclk2_vencl,
843 &gxbb_vclk_other,
844 &gxbb_edp,
845 &gxbb_ao_media_cpu,
846 &gxbb_ao_ahb_sram,
847 &gxbb_ao_ahb_bus,
848 &gxbb_ao_iface,
849 &gxbb_ao_i2c,
850};
851
852static int gxbb_clkc_probe(struct platform_device *pdev)
853{
854 void __iomem *clk_base;
855 int ret, clkid, i;
856 struct clk_hw *parent_hw;
857 struct clk *parent_clk;
858 struct device *dev = &pdev->dev;
859
860 /* Generic clocks and PLLs */
861 clk_base = of_iomap(dev->of_node, 0);
862 if (!clk_base) {
863 pr_err("%s: Unable to map clk base\n", __func__);
864 return -ENXIO;
865 }
866
867 /* Populate base address for PLLs */
868 for (i = 0; i < ARRAY_SIZE(gxbb_clk_plls); i++)
869 gxbb_clk_plls[i]->base = clk_base;
870
871 /* Populate base address for MPLLs */
872 for (i = 0; i < ARRAY_SIZE(gxbb_clk_mplls); i++)
873 gxbb_clk_mplls[i]->base = clk_base;
874
875 /* Populate the base address for CPU clk */
876 gxbb_cpu_clk.base = clk_base;
877
878 /* Populate the base address for the MPEG clks */
879 gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
880 gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
881
882 /* Populate base address for gates */
883 for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
884 gxbb_clk_gates[i]->reg = clk_base +
885 (u64)gxbb_clk_gates[i]->reg;
886
887 /*
888 * register all clks
889 */
890 for (clkid = 0; clkid < NR_CLKS; clkid++) {
891 ret = devm_clk_hw_register(dev, gxbb_hw_onecell_data.hws[clkid]);
892 if (ret)
893 goto iounmap;
894 }
895
896 /*
897 * Register CPU clk notifier
898 *
899 * FIXME this is wrong for a lot of reasons. First, the muxes should be
900 * struct clk_hw objects. Second, we shouldn't program the muxes in
901 * notifier handlers. The tricky programming sequence will be handled
902 * by the forthcoming coordinated clock rates mechanism once that
903 * feature is released.
904 *
905 * Furthermore, looking up the parent this way is terrible. At some
906 * point we will stop allocating a default struct clk when registering
907 * a new clk_hw, and this hack will no longer work. Releasing the ccr
908 * feature before that time solves the problem :-)
909 */
910 parent_hw = clk_hw_get_parent(&gxbb_cpu_clk.hw);
911 parent_clk = parent_hw->clk;
912 ret = clk_notifier_register(parent_clk, &gxbb_cpu_clk.clk_nb);
913 if (ret) {
914 pr_err("%s: failed to register clock notifier for cpu_clk\n",
915 __func__);
916 goto iounmap;
917 }
918
919 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
920 &gxbb_hw_onecell_data);
921
922iounmap:
923 iounmap(clk_base);
924 return ret;
925}
926
927static const struct of_device_id gxbb_clkc_match_table[] = {
928 { .compatible = "amlogic,gxbb-clkc" },
929 { }
930};
931
932static struct platform_driver gxbb_driver = {
933 .probe = gxbb_clkc_probe,
934 .driver = {
935 .name = "gxbb-clkc",
936 .of_match_table = gxbb_clkc_match_table,
937 },
938};
939
940static int __init gxbb_clkc_init(void)
941{
942 return platform_driver_register(&gxbb_driver);
943}
944device_initcall(gxbb_clkc_init);
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
new file mode 100644
index 000000000000..a2adf3448b59
--- /dev/null
+++ b/drivers/clk/meson/gxbb.h
@@ -0,0 +1,271 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 AmLogic, Inc.
8 * Author: Michael Turquette <mturquette@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING
24 *
25 * BSD LICENSE
26 *
27 * Copyright (c) 2016 BayLibre, Inc.
28 * Author: Michael Turquette <mturquette@baylibre.com>
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 *
34 * * Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * * Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in
38 * the documentation and/or other materials provided with the
39 * distribution.
40 * * Neither the name of Intel Corporation nor the names of its
41 * contributors may be used to endorse or promote products derived
42 * from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */
56
57#ifndef __GXBB_H
58#define __GXBB_H
59
60/*
61 * Clock controller register offsets
62 *
63 * Register offsets from the data sheet are listed in comment blocks below.
64 * Those offsets must be multiplied by 4 before adding them to the base address
65 * to get the right value
66 */
67#define SCR 0x2C /* 0x0b offset in data sheet */
68#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
69
70#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
71#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
72#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
73#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
74
75#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
76#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
77
78#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
79#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
80#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
81#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
82#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
83
84#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
85#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
86#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
87#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
88#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
89#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
90#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
91#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
92#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
93
94#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
95#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
96#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
97#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
98#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
99#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
100#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
101#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
102#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
103#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
104
105#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
106#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
107#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
108#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
109#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
110#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
111#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
112
113#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
114#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
115#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
116#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
117#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
118
119#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
120#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
121#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
122
123#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
124#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
125#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
126#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
127#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
128#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
129#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */
130#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */
131#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */
132#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */
133
134#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
135#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
136#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
137#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
138
139#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
140#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
141#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
142#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
143#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
144#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
145#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
146#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
147#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
148#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
149#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
150#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
151#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
152#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
153#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
154
155#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
156#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
157#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
158#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
159
160#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
161#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
162#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
163
164/*
165 * CLKID index values
166 *
167 * These indices are entirely contrived and do not map onto the hardware.
168 * Migrate them out of this header and into the DT header file when they need
169 * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
170 */
171#define CLKID_SYS_PLL 0
172/* CLKID_CPUCLK */
173#define CLKID_HDMI_PLL 2
174#define CLKID_FIXED_PLL 3
175#define CLKID_FCLK_DIV2 4
176#define CLKID_FCLK_DIV3 5
177#define CLKID_FCLK_DIV4 6
178#define CLKID_FCLK_DIV5 7
179#define CLKID_FCLK_DIV7 8
180#define CLKID_GP0_PLL 9
181#define CLKID_MPEG_SEL 10
182#define CLKID_MPEG_DIV 11
183/* CLKID_CLK81 */
184#define CLKID_MPLL0 13
185#define CLKID_MPLL1 14
186#define CLKID_MPLL2 15
187#define CLKID_DDR 16
188#define CLKID_DOS 17
189#define CLKID_ISA 18
190#define CLKID_PL301 19
191#define CLKID_PERIPHS 20
192#define CLKID_SPICC 21
193#define CLKID_I2C 22
194#define CLKID_SAR_ADC 23
195#define CLKID_SMART_CARD 24
196#define CLKID_RNG0 25
197#define CLKID_UART0 26
198#define CLKID_SDHC 27
199#define CLKID_STREAM 28
200#define CLKID_ASYNC_FIFO 29
201#define CLKID_SDIO 30
202#define CLKID_ABUF 31
203#define CLKID_HIU_IFACE 32
204#define CLKID_ASSIST_MISC 33
205#define CLKID_SPI 34
206#define CLKID_I2S_SPDIF 35
207#define CLKID_ETH 36
208#define CLKID_DEMUX 37
209#define CLKID_AIU_GLUE 38
210#define CLKID_IEC958 39
211#define CLKID_I2S_OUT 40
212#define CLKID_AMCLK 41
213#define CLKID_AIFIFO2 42
214#define CLKID_MIXER 43
215#define CLKID_MIXER_IFACE 44
216#define CLKID_ADC 45
217#define CLKID_BLKMV 46
218#define CLKID_AIU 47
219#define CLKID_UART1 48
220#define CLKID_G2D 49
221#define CLKID_USB0 50
222#define CLKID_USB1 51
223#define CLKID_RESET 52
224#define CLKID_NAND 53
225#define CLKID_DOS_PARSER 54
226#define CLKID_USB 55
227#define CLKID_VDIN1 56
228#define CLKID_AHB_ARB0 57
229#define CLKID_EFUSE 58
230#define CLKID_BOOT_ROM 59
231#define CLKID_AHB_DATA_BUS 60
232#define CLKID_AHB_CTRL_BUS 61
233#define CLKID_HDMI_INTR_SYNC 62
234#define CLKID_HDMI_PCLK 63
235#define CLKID_USB1_DDR_BRIDGE 64
236#define CLKID_USB0_DDR_BRIDGE 65
237#define CLKID_MMC_PCLK 66
238#define CLKID_DVIN 67
239#define CLKID_UART2 68
240#define CLKID_SANA 69
241#define CLKID_VPU_INTR 70
242#define CLKID_SEC_AHB_AHB3_BRIDGE 71
243#define CLKID_CLK81_A53 72
244#define CLKID_VCLK2_VENCI0 73
245#define CLKID_VCLK2_VENCI1 74
246#define CLKID_VCLK2_VENCP0 75
247#define CLKID_VCLK2_VENCP1 76
248#define CLKID_GCLK_VENCI_INT0 77
249#define CLKID_GCLK_VENCI_INT 78
250#define CLKID_DAC_CLK 79
251#define CLKID_AOCLK_GATE 80
252#define CLKID_IEC958_GATE 81
253#define CLKID_ENC480P 82
254#define CLKID_RNG1 83
255#define CLKID_GCLK_VENCI_INT1 84
256#define CLKID_VCLK2_VENCLMCC 85
257#define CLKID_VCLK2_VENCL 86
258#define CLKID_VCLK_OTHER 87
259#define CLKID_EDP 88
260#define CLKID_AO_MEDIA_CPU 89
261#define CLKID_AO_AHB_SRAM 90
262#define CLKID_AO_AHB_BUS 91
263#define CLKID_AO_IFACE 92
264#define CLKID_AO_I2C 93
265
266#define NR_CLKS 94
267
268/* include the CLKIDs that have been made part of the stable DT binding */
269#include <dt-bindings/clock/gxbb-clkc.h>
270
271#endif /* __GXBB_H */
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b-clkc.c
index 4d057b3e21b2..4c9413cdf373 100644
--- a/drivers/clk/meson/meson8b-clkc.c
+++ b/drivers/clk/meson/meson8b-clkc.c
@@ -1,7 +1,12 @@
1/* 1/*
2 * AmLogic S805 / Meson8b Clock Controller Driver
3 *
2 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com> 5 * Author: Carlo Caione <carlo@endlessm.com>
4 * 6 *
7 * Copyright (c) 2016 BayLibre, Inc.
8 * Michael Turquette <mturquette@baylibre.com>
9 *
5 * This program is free software; you can redistribute it and/or modify it 10 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 11 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 12 * version 2, as published by the Free Software Foundation.
@@ -15,23 +20,33 @@
15 * this program. If not, see <http://www.gnu.org/licenses/>. 20 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */ 21 */
17 22
23#include <linux/clk.h>
18#include <linux/clk-provider.h> 24#include <linux/clk-provider.h>
19#include <linux/kernel.h>
20#include <linux/of.h>
21#include <linux/of_address.h> 25#include <linux/of_address.h>
22#include <linux/slab.h>
23#include <dt-bindings/clock/meson8b-clkc.h> 26#include <dt-bindings/clock/meson8b-clkc.h>
27#include <linux/platform_device.h>
28#include <linux/init.h>
24 29
25#include "clkc.h" 30#include "clkc.h"
26 31
27#define MESON8B_REG_CTL0_ADDR 0x0000 32/*
28#define MESON8B_REG_SYS_CPU_CNTL1 0x015c 33 * Clock controller register offsets
29#define MESON8B_REG_HHI_MPEG 0x0174 34 *
30#define MESON8B_REG_MALI 0x01b0 35 * Register offsets from the HardKernel[0] data sheet are listed in comment
36 * blocks below. Those offsets must be multiplied by 4 before adding them to
37 * the base address to get the right value
38 *
39 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
40 */
41#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
42#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
43#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
31#define MESON8B_REG_PLL_FIXED 0x0280 44#define MESON8B_REG_PLL_FIXED 0x0280
32#define MESON8B_REG_PLL_SYS 0x0300 45#define MESON8B_REG_PLL_SYS 0x0300
33#define MESON8B_REG_PLL_VID 0x0320 46#define MESON8B_REG_PLL_VID 0x0320
34 47
48static DEFINE_SPINLOCK(clk_lock);
49
35static const struct pll_rate_table sys_pll_rate_table[] = { 50static const struct pll_rate_table sys_pll_rate_table[] = {
36 PLL_RATE(312000000, 52, 1, 2), 51 PLL_RATE(312000000, 52, 1, 2),
37 PLL_RATE(336000000, 56, 1, 2), 52 PLL_RATE(336000000, 56, 1, 2),
@@ -102,95 +117,331 @@ static const struct clk_div_table cpu_div_table[] = {
102 { /* sentinel */ }, 117 { /* sentinel */ },
103}; 118};
104 119
105PNAME(p_xtal) = { "xtal" }; 120static struct clk_fixed_rate meson8b_xtal = {
106PNAME(p_fclk_div) = { "fixed_pll" }; 121 .fixed_rate = 24000000,
107PNAME(p_cpu_clk) = { "sys_pll" }; 122 .hw.init = &(struct clk_init_data){
108PNAME(p_clk81) = { "fclk_div3", "fclk_div4", "fclk_div5" }; 123 .name = "xtal",
109PNAME(p_mali) = { "fclk_div3", "fclk_div4", "fclk_div5", 124 .num_parents = 0,
110 "fclk_div7", "zero" }; 125 .ops = &clk_fixed_rate_ops,
126 },
127};
128
129static struct meson_clk_pll meson8b_fixed_pll = {
130 .m = {
131 .reg_off = MESON8B_REG_PLL_FIXED,
132 .shift = 0,
133 .width = 9,
134 },
135 .n = {
136 .reg_off = MESON8B_REG_PLL_FIXED,
137 .shift = 9,
138 .width = 5,
139 },
140 .od = {
141 .reg_off = MESON8B_REG_PLL_FIXED,
142 .shift = 16,
143 .width = 2,
144 },
145 .lock = &clk_lock,
146 .hw.init = &(struct clk_init_data){
147 .name = "fixed_pll",
148 .ops = &meson_clk_pll_ro_ops,
149 .parent_names = (const char *[]){ "xtal" },
150 .num_parents = 1,
151 .flags = CLK_GET_RATE_NOCACHE,
152 },
153};
154
155static struct meson_clk_pll meson8b_vid_pll = {
156 .m = {
157 .reg_off = MESON8B_REG_PLL_VID,
158 .shift = 0,
159 .width = 9,
160 },
161 .n = {
162 .reg_off = MESON8B_REG_PLL_VID,
163 .shift = 9,
164 .width = 5,
165 },
166 .od = {
167 .reg_off = MESON8B_REG_PLL_VID,
168 .shift = 16,
169 .width = 2,
170 },
171 .lock = &clk_lock,
172 .hw.init = &(struct clk_init_data){
173 .name = "vid_pll",
174 .ops = &meson_clk_pll_ro_ops,
175 .parent_names = (const char *[]){ "xtal" },
176 .num_parents = 1,
177 .flags = CLK_GET_RATE_NOCACHE,
178 },
179};
180
181static struct meson_clk_pll meson8b_sys_pll = {
182 .m = {
183 .reg_off = MESON8B_REG_PLL_SYS,
184 .shift = 0,
185 .width = 9,
186 },
187 .n = {
188 .reg_off = MESON8B_REG_PLL_SYS,
189 .shift = 9,
190 .width = 5,
191 },
192 .od = {
193 .reg_off = MESON8B_REG_PLL_SYS,
194 .shift = 16,
195 .width = 2,
196 },
197 .rate_table = sys_pll_rate_table,
198 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
199 .lock = &clk_lock,
200 .hw.init = &(struct clk_init_data){
201 .name = "sys_pll",
202 .ops = &meson_clk_pll_ops,
203 .parent_names = (const char *[]){ "xtal" },
204 .num_parents = 1,
205 .flags = CLK_GET_RATE_NOCACHE,
206 },
207};
208
209static struct clk_fixed_factor meson8b_fclk_div2 = {
210 .mult = 1,
211 .div = 2,
212 .hw.init = &(struct clk_init_data){
213 .name = "fclk_div2",
214 .ops = &clk_fixed_factor_ops,
215 .parent_names = (const char *[]){ "fixed_pll" },
216 .num_parents = 1,
217 },
218};
219
220static struct clk_fixed_factor meson8b_fclk_div3 = {
221 .mult = 1,
222 .div = 3,
223 .hw.init = &(struct clk_init_data){
224 .name = "fclk_div3",
225 .ops = &clk_fixed_factor_ops,
226 .parent_names = (const char *[]){ "fixed_pll" },
227 .num_parents = 1,
228 },
229};
230
231static struct clk_fixed_factor meson8b_fclk_div4 = {
232 .mult = 1,
233 .div = 4,
234 .hw.init = &(struct clk_init_data){
235 .name = "fclk_div4",
236 .ops = &clk_fixed_factor_ops,
237 .parent_names = (const char *[]){ "fixed_pll" },
238 .num_parents = 1,
239 },
240};
241
242static struct clk_fixed_factor meson8b_fclk_div5 = {
243 .mult = 1,
244 .div = 5,
245 .hw.init = &(struct clk_init_data){
246 .name = "fclk_div5",
247 .ops = &clk_fixed_factor_ops,
248 .parent_names = (const char *[]){ "fixed_pll" },
249 .num_parents = 1,
250 },
251};
252
253static struct clk_fixed_factor meson8b_fclk_div7 = {
254 .mult = 1,
255 .div = 7,
256 .hw.init = &(struct clk_init_data){
257 .name = "fclk_div7",
258 .ops = &clk_fixed_factor_ops,
259 .parent_names = (const char *[]){ "fixed_pll" },
260 .num_parents = 1,
261 },
262};
263
264/*
265 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
266 * post-dividers and should be modeled with their respective PLLs via the
267 * forthcoming coordinated clock rates feature
268 */
269static struct meson_clk_cpu meson8b_cpu_clk = {
270 .reg_off = MESON8B_REG_SYS_CPU_CNTL1,
271 .div_table = cpu_div_table,
272 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
273 .hw.init = &(struct clk_init_data){
274 .name = "cpu_clk",
275 .ops = &meson_clk_cpu_ops,
276 .parent_names = (const char *[]){ "sys_pll" },
277 .num_parents = 1,
278 },
279};
111 280
112static u32 mux_table_clk81[] = { 6, 5, 7 }; 281static u32 mux_table_clk81[] = { 6, 5, 7 };
113static u32 mux_table_mali[] = { 6, 5, 7, 4, 0 };
114
115static struct pll_conf pll_confs = {
116 .m = PARM(0x00, 0, 9),
117 .n = PARM(0x00, 9, 5),
118 .od = PARM(0x00, 16, 2),
119};
120
121static struct pll_conf sys_pll_conf = {
122 .m = PARM(0x00, 0, 9),
123 .n = PARM(0x00, 9, 5),
124 .od = PARM(0x00, 16, 2),
125 .rate_table = sys_pll_rate_table,
126};
127
128static const struct composite_conf clk81_conf __initconst = {
129 .mux_table = mux_table_clk81,
130 .mux_flags = CLK_MUX_READ_ONLY,
131 .mux_parm = PARM(0x00, 12, 3),
132 .div_parm = PARM(0x00, 0, 7),
133 .gate_parm = PARM(0x00, 7, 1),
134};
135
136static const struct composite_conf mali_conf __initconst = {
137 .mux_table = mux_table_mali,
138 .mux_parm = PARM(0x00, 9, 3),
139 .div_parm = PARM(0x00, 0, 7),
140 .gate_parm = PARM(0x00, 8, 1),
141};
142
143static const struct clk_conf meson8b_xtal_conf __initconst =
144 FIXED_RATE_P(MESON8B_REG_CTL0_ADDR, CLKID_XTAL, "xtal", 0,
145 PARM(0x00, 4, 7));
146
147static const struct clk_conf meson8b_clk_confs[] __initconst = {
148 FIXED_RATE(CLKID_ZERO, "zero", 0, 0),
149 PLL(MESON8B_REG_PLL_FIXED, CLKID_PLL_FIXED, "fixed_pll",
150 p_xtal, 0, &pll_confs),
151 PLL(MESON8B_REG_PLL_VID, CLKID_PLL_VID, "vid_pll",
152 p_xtal, 0, &pll_confs),
153 PLL(MESON8B_REG_PLL_SYS, CLKID_PLL_SYS, "sys_pll",
154 p_xtal, 0, &sys_pll_conf),
155 FIXED_FACTOR_DIV(CLKID_FCLK_DIV2, "fclk_div2", p_fclk_div, 0, 2),
156 FIXED_FACTOR_DIV(CLKID_FCLK_DIV3, "fclk_div3", p_fclk_div, 0, 3),
157 FIXED_FACTOR_DIV(CLKID_FCLK_DIV4, "fclk_div4", p_fclk_div, 0, 4),
158 FIXED_FACTOR_DIV(CLKID_FCLK_DIV5, "fclk_div5", p_fclk_div, 0, 5),
159 FIXED_FACTOR_DIV(CLKID_FCLK_DIV7, "fclk_div7", p_fclk_div, 0, 7),
160 CPU(MESON8B_REG_SYS_CPU_CNTL1, CLKID_CPUCLK, "a5_clk", p_cpu_clk,
161 cpu_div_table),
162 COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81,
163 CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf),
164 COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali,
165 CLK_IGNORE_UNUSED, &mali_conf),
166};
167
168static void __init meson8b_clkc_init(struct device_node *np)
169{
170 void __iomem *clk_base;
171 282
172 if (!meson_clk_init(np, CLK_NR_CLKS)) 283struct clk_mux meson8b_mpeg_clk_sel = {
173 return; 284 .reg = (void *)MESON8B_REG_HHI_MPEG,
285 .mask = 0x7,
286 .shift = 12,
287 .flags = CLK_MUX_READ_ONLY,
288 .table = mux_table_clk81,
289 .lock = &clk_lock,
290 .hw.init = &(struct clk_init_data){
291 .name = "mpeg_clk_sel",
292 .ops = &clk_mux_ro_ops,
293 /*
294 * FIXME bits 14:12 selects from 8 possible parents:
295 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
296 * fclk_div4, fclk_div3, fclk_div5
297 */
298 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
299 "fclk_div5" },
300 .num_parents = 3,
301 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
302 },
303};
174 304
175 /* XTAL */ 305struct clk_divider meson8b_mpeg_clk_div = {
176 clk_base = of_iomap(np, 0); 306 .reg = (void *)MESON8B_REG_HHI_MPEG,
177 if (!clk_base) { 307 .shift = 0,
178 pr_err("%s: Unable to map xtal base\n", __func__); 308 .width = 7,
179 return; 309 .lock = &clk_lock,
180 } 310 .hw.init = &(struct clk_init_data){
311 .name = "mpeg_clk_div",
312 .ops = &clk_divider_ops,
313 .parent_names = (const char *[]){ "mpeg_clk_sel" },
314 .num_parents = 1,
315 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
316 },
317};
181 318
182 meson_clk_register_clks(&meson8b_xtal_conf, 1, clk_base); 319struct clk_gate meson8b_clk81 = {
183 iounmap(clk_base); 320 .reg = (void *)MESON8B_REG_HHI_MPEG,
321 .bit_idx = 7,
322 .lock = &clk_lock,
323 .hw.init = &(struct clk_init_data){
324 .name = "clk81",
325 .ops = &clk_gate_ops,
326 .parent_names = (const char *[]){ "mpeg_clk_div" },
327 .num_parents = 1,
328 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
329 },
330};
331
332static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
333 .hws = {
334 [CLKID_XTAL] = &meson8b_xtal.hw,
335 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
336 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
337 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
338 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
339 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
340 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
341 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
342 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
343 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
344 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
345 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
346 [CLKID_CLK81] = &meson8b_clk81.hw,
347 },
348 .num = CLK_NR_CLKS,
349};
350
351static struct meson_clk_pll *const meson8b_clk_plls[] = {
352 &meson8b_fixed_pll,
353 &meson8b_vid_pll,
354 &meson8b_sys_pll,
355};
356
357static int meson8b_clkc_probe(struct platform_device *pdev)
358{
359 void __iomem *clk_base;
360 int ret, clkid, i;
361 struct clk_hw *parent_hw;
362 struct clk *parent_clk;
363 struct device *dev = &pdev->dev;
184 364
185 /* Generic clocks and PLLs */ 365 /* Generic clocks and PLLs */
186 clk_base = of_iomap(np, 1); 366 clk_base = of_iomap(dev->of_node, 1);
187 if (!clk_base) { 367 if (!clk_base) {
188 pr_err("%s: Unable to map clk base\n", __func__); 368 pr_err("%s: Unable to map clk base\n", __func__);
189 return; 369 return -ENXIO;
370 }
371
372 /* Populate base address for PLLs */
373 for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
374 meson8b_clk_plls[i]->base = clk_base;
375
376 /* Populate the base address for CPU clk */
377 meson8b_cpu_clk.base = clk_base;
378
379 /* Populate the base address for the MPEG clks */
380 meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
381 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
382 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
383
384 /*
385 * register all clks
386 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
387 */
388 for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
389 /* array might be sparse */
390 if (!meson8b_hw_onecell_data.hws[clkid])
391 continue;
392
393 /* FIXME convert to devm_clk_register */
394 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
395 if (ret)
396 goto iounmap;
190 } 397 }
191 398
192 meson_clk_register_clks(meson8b_clk_confs, 399 /*
193 ARRAY_SIZE(meson8b_clk_confs), 400 * Register CPU clk notifier
194 clk_base); 401 *
402 * FIXME this is wrong for a lot of reasons. First, the muxes should be
403 * struct clk_hw objects. Second, we shouldn't program the muxes in
404 * notifier handlers. The tricky programming sequence will be handled
405 * by the forthcoming coordinated clock rates mechanism once that
406 * feature is released.
407 *
408 * Furthermore, looking up the parent this way is terrible. At some
409 * point we will stop allocating a default struct clk when registering
410 * a new clk_hw, and this hack will no longer work. Releasing the ccr
411 * feature before that time solves the problem :-)
412 */
413 parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
414 parent_clk = parent_hw->clk;
415 ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
416 if (ret) {
417 pr_err("%s: failed to register clock notifier for cpu_clk\n",
418 __func__);
419 goto iounmap;
420 }
421
422 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
423 &meson8b_hw_onecell_data);
424
425iounmap:
426 iounmap(clk_base);
427 return ret;
428}
429
430static const struct of_device_id meson8b_clkc_match_table[] = {
431 { .compatible = "amlogic,meson8b-clkc" },
432 { }
433};
434
435static struct platform_driver meson8b_driver = {
436 .probe = meson8b_clkc_probe,
437 .driver = {
438 .name = "meson8b-clkc",
439 .of_match_table = meson8b_clkc_match_table,
440 },
441};
442
443static int __init meson8b_clkc_init(void)
444{
445 return platform_driver_register(&meson8b_driver);
195} 446}
196CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init); 447device_initcall(meson8b_clkc_init);
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 481b2646b496..90d740a2fc0d 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -87,7 +87,7 @@ enum {
87 87
88enum { 88enum {
89 /* Start from the last defined clock in dt bindings */ 89 /* Start from the last defined clock in dt bindings */
90 LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_HCLK_PLL + 1, 90 LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1,
91 LPC32XX_CLK_ADC_RTC, 91 LPC32XX_CLK_ADC_RTC,
92 LPC32XX_CLK_TEST1, 92 LPC32XX_CLK_TEST1,
93 LPC32XX_CLK_TEST2, 93 LPC32XX_CLK_TEST2,
@@ -99,7 +99,6 @@ enum {
99 LPC32XX_CLK_HCLK_DIV_PERIPH, 99 LPC32XX_CLK_HCLK_DIV_PERIPH,
100 LPC32XX_CLK_HCLK_DIV, 100 LPC32XX_CLK_HCLK_DIV,
101 LPC32XX_CLK_HCLK, 101 LPC32XX_CLK_HCLK,
102 LPC32XX_CLK_PERIPH,
103 LPC32XX_CLK_ARM, 102 LPC32XX_CLK_ARM,
104 LPC32XX_CLK_ARM_VFP, 103 LPC32XX_CLK_ARM_VFP,
105 104
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index 6dc55864979c..c347a0d44bc8 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -2290,6 +2290,32 @@ static struct clk_branch sdc5_h_clk = {
2290 }, 2290 },
2291}; 2291};
2292 2292
2293static struct clk_branch ebi2_2x_clk = {
2294 .halt_reg = 0x2fcc,
2295 .halt_bit = 18,
2296 .clkr = {
2297 .enable_reg = 0x2660,
2298 .enable_mask = BIT(4),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "ebi2_2x_clk",
2301 .ops = &clk_branch_ops,
2302 },
2303 },
2304};
2305
2306static struct clk_branch ebi2_clk = {
2307 .halt_reg = 0x2fcc,
2308 .halt_bit = 19,
2309 .clkr = {
2310 .enable_reg = 0x2664,
2311 .enable_mask = BIT(4),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "ebi2_clk",
2314 .ops = &clk_branch_ops,
2315 },
2316 },
2317};
2318
2293static struct clk_branch adm0_clk = { 2319static struct clk_branch adm0_clk = {
2294 .halt_reg = 0x2fdc, 2320 .halt_reg = 0x2fdc,
2295 .halt_check = BRANCH_HALT_VOTED, 2321 .halt_check = BRANCH_HALT_VOTED,
@@ -2533,6 +2559,8 @@ static struct clk_regmap *gcc_msm8660_clks[] = {
2533 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2559 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2534 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 2560 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2535 [SDC5_H_CLK] = &sdc5_h_clk.clkr, 2561 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2562 [EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
2563 [EBI2_CLK] = &ebi2_clk.clkr,
2536 [ADM0_CLK] = &adm0_clk.clkr, 2564 [ADM0_CLK] = &adm0_clk.clkr,
2537 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2565 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2538 [ADM1_CLK] = &adm1_clk.clkr, 2566 [ADM1_CLK] = &adm1_clk.clkr,
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index c9b96f318d9c..bbf732bbc3fd 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -2891,21 +2891,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2891 }, 2891 },
2892}; 2892};
2893 2893
2894static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2895 .halt_reg = 0x82014,
2896 .clkr = {
2897 .enable_reg = 0x82014,
2898 .enable_mask = BIT(0),
2899 .hw.init = &(struct clk_init_data){
2900 .name = "gcc_aggre1_pnoc_ahb_clk",
2901 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2902 .num_parents = 1,
2903 .flags = CLK_SET_RATE_PARENT,
2904 .ops = &clk_branch2_ops,
2905 },
2906 },
2907};
2908
2909static struct clk_branch gcc_aggre2_ufs_axi_clk = { 2894static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2910 .halt_reg = 0x83014, 2895 .halt_reg = 0x83014,
2911 .clkr = { 2896 .clkr = {
@@ -3308,7 +3293,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
3308 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr, 3293 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3309 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr, 3294 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3310 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr, 3295 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3311 [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3312 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, 3296 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3313 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, 3297 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3314 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, 3298 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 2115ce410cfb..41a12d376799 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,6 +1,7 @@
1config CLK_RENESAS_CPG_MSSR 1config CLK_RENESAS_CPG_MSSR
2 bool 2 bool
3 default y if ARCH_R8A7795 3 default y if ARCH_R8A7795
4 default y if ARCH_R8A7796
4 5
5config CLK_RENESAS_CPG_MSTP 6config CLK_RENESAS_CPG_MSTP
6 bool 7 bool
@@ -11,6 +12,7 @@ config CLK_RENESAS_CPG_MSTP
11 default y if ARCH_R8A7779 12 default y if ARCH_R8A7779
12 default y if ARCH_R8A7790 13 default y if ARCH_R8A7790
13 default y if ARCH_R8A7791 14 default y if ARCH_R8A7791
15 default y if ARCH_R8A7792
14 default y if ARCH_R8A7793 16 default y if ARCH_R8A7793
15 default y if ARCH_R8A7794 17 default y if ARCH_R8A7794
16 default y if ARCH_SH73A0 18 default y if ARCH_SH73A0
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index ead8bb843524..90dd0db7d9c6 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -6,9 +6,11 @@ obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
6obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o 6obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
7obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o 7obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o 8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
9obj-$(CONFIG_ARCH_R8A7792) += clk-rcar-gen2.o clk-div6.o
9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o 10obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o 11obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
11obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o 12obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o
13obj-$(CONFIG_ARCH_R8A7796) += r8a7796-cpg-mssr.o rcar-gen3-cpg.o
12obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o 14obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
13 15
14obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o 16obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index ca5519c583d4..d359c92e13a6 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -12,22 +12,14 @@
12 * the Free Software Foundation; version 2 of the License. 12 * the Free Software Foundation; version 2 of the License.
13 */ 13 */
14 14
15#include <linux/bug.h>
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/device.h> 15#include <linux/device.h>
19#include <linux/err.h>
20#include <linux/init.h> 16#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h> 17#include <linux/kernel.h>
23#include <linux/of.h>
24#include <linux/slab.h>
25 18
26#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 19#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
27 20
28#include "renesas-cpg-mssr.h" 21#include "renesas-cpg-mssr.h"
29 22#include "rcar-gen3-cpg.h"
30#define CPG_RCKCR 0x240
31 23
32enum clk_ids { 24enum clk_ids {
33 /* Core Clock Outputs exported to DT */ 25 /* Core Clock Outputs exported to DT */
@@ -58,20 +50,6 @@ enum clk_ids {
58 MOD_CLK_BASE 50 MOD_CLK_BASE
59}; 51};
60 52
61enum r8a7795_clk_types {
62 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
63 CLK_TYPE_GEN3_PLL0,
64 CLK_TYPE_GEN3_PLL1,
65 CLK_TYPE_GEN3_PLL2,
66 CLK_TYPE_GEN3_PLL3,
67 CLK_TYPE_GEN3_PLL4,
68 CLK_TYPE_GEN3_SD,
69 CLK_TYPE_GEN3_R,
70};
71
72#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
73 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
74
75static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 53static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
76 /* External Clock Inputs */ 54 /* External Clock Inputs */
77 DEF_INPUT("extal", CLK_EXTAL), 55 DEF_INPUT("extal", CLK_EXTAL),
@@ -129,6 +107,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
129}; 107};
130 108
131static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 109static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
110 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1),
111 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S2D1),
112 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S2D1),
132 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 113 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
133 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 114 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
134 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 115 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
@@ -157,11 +138,20 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
157 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 138 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
158 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), 139 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
159 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), 140 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
141 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
142 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
143 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
144 DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
145 DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
146 DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
147 DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
148 DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
160 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 149 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
161 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 150 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
162 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 151 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
163 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 152 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
164 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 153 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
154 DEF_MOD("thermal", 522, R8A7795_CLK_CP),
165 DEF_MOD("pwm", 523, R8A7795_CLK_S3D4), 155 DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
166 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), 156 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
167 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), 157 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
@@ -199,7 +189,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
199 DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 189 DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
200 DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 190 DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
201 DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 191 DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
202 DEF_MOD("lvds", 727, R8A7795_CLK_S2D1), 192 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
203 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 193 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
204 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 194 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
205 DEF_MOD("vin7", 804, R8A7795_CLK_S2D1), 195 DEF_MOD("vin7", 804, R8A7795_CLK_S2D1),
@@ -262,225 +252,6 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
262 MOD_CLK_ID(408), /* INTC-AP (GIC) */ 252 MOD_CLK_ID(408), /* INTC-AP (GIC) */
263}; 253};
264 254
265/* -----------------------------------------------------------------------------
266 * SDn Clock
267 *
268 */
269#define CPG_SD_STP_HCK BIT(9)
270#define CPG_SD_STP_CK BIT(8)
271
272#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
273#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
274
275#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
276{ \
277 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
278 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
279 ((sd_srcfc) << 2) | \
280 ((sd_fc) << 0), \
281 .div = (sd_div), \
282}
283
284struct sd_div_table {
285 u32 val;
286 unsigned int div;
287};
288
289struct sd_clock {
290 struct clk_hw hw;
291 void __iomem *reg;
292 const struct sd_div_table *div_table;
293 unsigned int div_num;
294 unsigned int div_min;
295 unsigned int div_max;
296};
297
298/* SDn divider
299 * sd_srcfc sd_fc div
300 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
301 *-------------------------------------------------------------------
302 * 0 0 0 (1) 1 (4) 4
303 * 0 0 1 (2) 1 (4) 8
304 * 1 0 2 (4) 1 (4) 16
305 * 1 0 3 (8) 1 (4) 32
306 * 1 0 4 (16) 1 (4) 64
307 * 0 0 0 (1) 0 (2) 2
308 * 0 0 1 (2) 0 (2) 4
309 * 1 0 2 (4) 0 (2) 8
310 * 1 0 3 (8) 0 (2) 16
311 * 1 0 4 (16) 0 (2) 32
312 */
313static const struct sd_div_table cpg_sd_div_table[] = {
314/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
315 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
316 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
317 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
318 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
319 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
320 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
321 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
322 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
323 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
324 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
325};
326
327#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
328
329static int cpg_sd_clock_enable(struct clk_hw *hw)
330{
331 struct sd_clock *clock = to_sd_clock(hw);
332 u32 val, sd_fc;
333 unsigned int i;
334
335 val = clk_readl(clock->reg);
336
337 sd_fc = val & CPG_SD_FC_MASK;
338 for (i = 0; i < clock->div_num; i++)
339 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
340 break;
341
342 if (i >= clock->div_num)
343 return -EINVAL;
344
345 val &= ~(CPG_SD_STP_MASK);
346 val |= clock->div_table[i].val & CPG_SD_STP_MASK;
347
348 clk_writel(val, clock->reg);
349
350 return 0;
351}
352
353static void cpg_sd_clock_disable(struct clk_hw *hw)
354{
355 struct sd_clock *clock = to_sd_clock(hw);
356
357 clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
358}
359
360static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
361{
362 struct sd_clock *clock = to_sd_clock(hw);
363
364 return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
365}
366
367static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
368 unsigned long parent_rate)
369{
370 struct sd_clock *clock = to_sd_clock(hw);
371 unsigned long rate = parent_rate;
372 u32 val, sd_fc;
373 unsigned int i;
374
375 val = clk_readl(clock->reg);
376
377 sd_fc = val & CPG_SD_FC_MASK;
378 for (i = 0; i < clock->div_num; i++)
379 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
380 break;
381
382 if (i >= clock->div_num)
383 return -EINVAL;
384
385 return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
386}
387
388static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
389 unsigned long rate,
390 unsigned long parent_rate)
391{
392 unsigned int div;
393
394 if (!rate)
395 rate = 1;
396
397 div = DIV_ROUND_CLOSEST(parent_rate, rate);
398
399 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
400}
401
402static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
403 unsigned long *parent_rate)
404{
405 struct sd_clock *clock = to_sd_clock(hw);
406 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
407
408 return DIV_ROUND_CLOSEST(*parent_rate, div);
409}
410
411static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
412 unsigned long parent_rate)
413{
414 struct sd_clock *clock = to_sd_clock(hw);
415 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
416 u32 val;
417 unsigned int i;
418
419 for (i = 0; i < clock->div_num; i++)
420 if (div == clock->div_table[i].div)
421 break;
422
423 if (i >= clock->div_num)
424 return -EINVAL;
425
426 val = clk_readl(clock->reg);
427 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
428 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
429 clk_writel(val, clock->reg);
430
431 return 0;
432}
433
434static const struct clk_ops cpg_sd_clock_ops = {
435 .enable = cpg_sd_clock_enable,
436 .disable = cpg_sd_clock_disable,
437 .is_enabled = cpg_sd_clock_is_enabled,
438 .recalc_rate = cpg_sd_clock_recalc_rate,
439 .round_rate = cpg_sd_clock_round_rate,
440 .set_rate = cpg_sd_clock_set_rate,
441};
442
443static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
444 void __iomem *base,
445 const char *parent_name)
446{
447 struct clk_init_data init;
448 struct sd_clock *clock;
449 struct clk *clk;
450 unsigned int i;
451
452 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
453 if (!clock)
454 return ERR_PTR(-ENOMEM);
455
456 init.name = core->name;
457 init.ops = &cpg_sd_clock_ops;
458 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
459 init.parent_names = &parent_name;
460 init.num_parents = 1;
461
462 clock->reg = base + core->offset;
463 clock->hw.init = &init;
464 clock->div_table = cpg_sd_div_table;
465 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
466
467 clock->div_max = clock->div_table[0].div;
468 clock->div_min = clock->div_max;
469 for (i = 1; i < clock->div_num; i++) {
470 clock->div_max = max(clock->div_max, clock->div_table[i].div);
471 clock->div_min = min(clock->div_min, clock->div_table[i].div);
472 }
473
474 clk = clk_register(NULL, &clock->hw);
475 if (IS_ERR(clk))
476 kfree(clock);
477
478 return clk;
479}
480
481#define CPG_PLL0CR 0x00d8
482#define CPG_PLL2CR 0x002c
483#define CPG_PLL4CR 0x01f4
484 255
485/* 256/*
486 * CPG Clock Data 257 * CPG Clock Data
@@ -512,13 +283,7 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
512 (((md) & BIT(19)) >> 18) | \ 283 (((md) & BIT(19)) >> 18) | \
513 (((md) & BIT(17)) >> 17)) 284 (((md) & BIT(17)) >> 17))
514 285
515struct cpg_pll_config { 286static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
516 unsigned int extal_div;
517 unsigned int pll1_mult;
518 unsigned int pll3_mult;
519};
520
521static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
522 /* EXTAL div PLL1 mult PLL3 mult */ 287 /* EXTAL div PLL1 mult PLL3 mult */
523 { 1, 192, 192, }, 288 { 1, 192, 192, },
524 { 1, 192, 128, }, 289 { 1, 192, 128, },
@@ -538,112 +303,9 @@ static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
538 { 2, 192, 192, }, 303 { 2, 192, 192, },
539}; 304};
540 305
541static const struct cpg_pll_config *cpg_pll_config __initdata;
542
543static
544struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
545 const struct cpg_core_clk *core,
546 const struct cpg_mssr_info *info,
547 struct clk **clks,
548 void __iomem *base)
549{
550 const struct clk *parent;
551 unsigned int mult = 1;
552 unsigned int div = 1;
553 u32 value;
554
555 parent = clks[core->parent];
556 if (IS_ERR(parent))
557 return ERR_CAST(parent);
558
559 switch (core->type) {
560 case CLK_TYPE_GEN3_MAIN:
561 div = cpg_pll_config->extal_div;
562 break;
563
564 case CLK_TYPE_GEN3_PLL0:
565 /*
566 * PLL0 is a configurable multiplier clock. Register it as a
567 * fixed factor clock for now as there's no generic multiplier
568 * clock implementation and we currently have no need to change
569 * the multiplier value.
570 */
571 value = readl(base + CPG_PLL0CR);
572 mult = (((value >> 24) & 0x7f) + 1) * 2;
573 break;
574
575 case CLK_TYPE_GEN3_PLL1:
576 mult = cpg_pll_config->pll1_mult;
577 break;
578
579 case CLK_TYPE_GEN3_PLL2:
580 /*
581 * PLL2 is a configurable multiplier clock. Register it as a
582 * fixed factor clock for now as there's no generic multiplier
583 * clock implementation and we currently have no need to change
584 * the multiplier value.
585 */
586 value = readl(base + CPG_PLL2CR);
587 mult = (((value >> 24) & 0x7f) + 1) * 2;
588 break;
589
590 case CLK_TYPE_GEN3_PLL3:
591 mult = cpg_pll_config->pll3_mult;
592 break;
593
594 case CLK_TYPE_GEN3_PLL4:
595 /*
596 * PLL4 is a configurable multiplier clock. Register it as a
597 * fixed factor clock for now as there's no generic multiplier
598 * clock implementation and we currently have no need to change
599 * the multiplier value.
600 */
601 value = readl(base + CPG_PLL4CR);
602 mult = (((value >> 24) & 0x7f) + 1) * 2;
603 break;
604
605 case CLK_TYPE_GEN3_SD:
606 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
607
608 case CLK_TYPE_GEN3_R:
609 /* RINT is default. Only if EXTALR is populated, we switch to it */
610 value = readl(base + CPG_RCKCR) & 0x3f;
611
612 if (clk_get_rate(clks[CLK_EXTALR])) {
613 parent = clks[CLK_EXTALR];
614 value |= BIT(15);
615 }
616
617 writel(value, base + CPG_RCKCR);
618 break;
619
620 default:
621 return ERR_PTR(-EINVAL);
622 }
623
624 return clk_register_fixed_factor(NULL, core->name,
625 __clk_get_name(parent), 0, mult, div);
626}
627
628/*
629 * Reset register definitions.
630 */
631#define MODEMR 0xe6160060
632
633static u32 rcar_gen3_read_mode_pins(void)
634{
635 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
636 u32 mode;
637
638 BUG_ON(!modemr);
639 mode = ioread32(modemr);
640 iounmap(modemr);
641
642 return mode;
643}
644
645static int __init r8a7795_cpg_mssr_init(struct device *dev) 306static int __init r8a7795_cpg_mssr_init(struct device *dev)
646{ 307{
308 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
647 u32 cpg_mode = rcar_gen3_read_mode_pins(); 309 u32 cpg_mode = rcar_gen3_read_mode_pins();
648 310
649 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 311 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
@@ -652,7 +314,7 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev)
652 return -EINVAL; 314 return -EINVAL;
653 } 315 }
654 316
655 return 0; 317 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
656} 318}
657 319
658const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { 320const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
@@ -673,5 +335,5 @@ const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
673 335
674 /* Callbacks */ 336 /* Callbacks */
675 .init = r8a7795_cpg_mssr_init, 337 .init = r8a7795_cpg_mssr_init,
676 .cpg_clk_register = r8a7795_cpg_clk_register, 338 .cpg_clk_register = rcar_gen3_cpg_clk_register,
677}; 339};
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
new file mode 100644
index 000000000000..c84b549c14d2
--- /dev/null
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -0,0 +1,192 @@
1/*
2 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * Based on r8a7795-cpg-mssr.c
7 *
8 * Copyright (C) 2015 Glider bvba
9 * Copyright (C) 2015 Renesas Electronics Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 */
15
16#include <linux/device.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19
20#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
21
22#include "renesas-cpg-mssr.h"
23#include "rcar-gen3-cpg.h"
24
25enum clk_ids {
26 /* Core Clock Outputs exported to DT */
27 LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
28
29 /* External Input Clocks */
30 CLK_EXTAL,
31 CLK_EXTALR,
32
33 /* Internal Core Clocks */
34 CLK_MAIN,
35 CLK_PLL0,
36 CLK_PLL1,
37 CLK_PLL2,
38 CLK_PLL3,
39 CLK_PLL4,
40 CLK_PLL1_DIV2,
41 CLK_PLL1_DIV4,
42 CLK_S0,
43 CLK_S1,
44 CLK_S2,
45 CLK_S3,
46 CLK_SDSRC,
47 CLK_SSPSRC,
48
49 /* Module Clocks */
50 MOD_CLK_BASE
51};
52
53static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
54 /* External Clock Inputs */
55 DEF_INPUT("extal", CLK_EXTAL),
56 DEF_INPUT("extalr", CLK_EXTALR),
57
58 /* Internal Core Clocks */
59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
60 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
64 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
65
66 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
67 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
69 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
70 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
71 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
72
73 /* Core Clock Outputs */
74 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
75 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
76 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
77 DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
78 DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
79 DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
80 DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
81 DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
82 DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
83 DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
84 DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
85 DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
86 DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
87 DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
88 DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
89 DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
90 DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
91 DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
92 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
93 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
94
95 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
96 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
97};
98
99static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
100 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
101 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
102};
103
104static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
105 MOD_CLK_ID(408), /* INTC-AP (GIC) */
106};
107
108
109/*
110 * CPG Clock Data
111 */
112
113/*
114 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
115 * 14 13 19 17 (MHz)
116 *-------------------------------------------------------------------
117 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
118 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
119 * 0 0 1 0 Prohibited setting
120 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
121 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
122 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
123 * 0 1 1 0 Prohibited setting
124 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
125 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
126 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
127 * 1 0 1 0 Prohibited setting
128 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
129 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
130 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
131 * 1 1 1 0 Prohibited setting
132 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
133 */
134#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
135 (((md) & BIT(13)) >> 11) | \
136 (((md) & BIT(19)) >> 18) | \
137 (((md) & BIT(17)) >> 17))
138
139static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
140 /* EXTAL div PLL1 mult PLL3 mult */
141 { 1, 192, 192, },
142 { 1, 192, 128, },
143 { 0, /* Prohibited setting */ },
144 { 1, 192, 192, },
145 { 1, 160, 160, },
146 { 1, 160, 106, },
147 { 0, /* Prohibited setting */ },
148 { 1, 160, 160, },
149 { 1, 128, 128, },
150 { 1, 128, 84, },
151 { 0, /* Prohibited setting */ },
152 { 1, 128, 128, },
153 { 2, 192, 192, },
154 { 2, 192, 128, },
155 { 0, /* Prohibited setting */ },
156 { 2, 192, 192, },
157};
158
159static int __init r8a7796_cpg_mssr_init(struct device *dev)
160{
161 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
162 u32 cpg_mode = rcar_gen3_read_mode_pins();
163
164 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
165 if (!cpg_pll_config->extal_div) {
166 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
167 return -EINVAL;
168 }
169
170 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
171}
172
173const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
174 /* Core Clocks */
175 .core_clks = r8a7796_core_clks,
176 .num_core_clks = ARRAY_SIZE(r8a7796_core_clks),
177 .last_dt_core_clk = LAST_DT_CORE_CLK,
178 .num_total_core_clks = MOD_CLK_BASE,
179
180 /* Module Clocks */
181 .mod_clks = r8a7796_mod_clks,
182 .num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks),
183 .num_hw_mod_clks = 12 * 32,
184
185 /* Critical Module Clocks */
186 .crit_mod_clks = r8a7796_crit_mod_clks,
187 .num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks),
188
189 /* Callbacks */
190 .init = r8a7796_cpg_mssr_init,
191 .cpg_clk_register = rcar_gen3_cpg_clk_register,
192};
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
new file mode 100644
index 000000000000..bb4f2f9a8c2f
--- /dev/null
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -0,0 +1,359 @@
1/*
2 * R-Car Gen3 Clock Pulse Generator
3 *
4 * Copyright (C) 2015-2016 Glider bvba
5 *
6 * Based on clk-rcar-gen3.c
7 *
8 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15#include <linux/bug.h>
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/device.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23
24#include "renesas-cpg-mssr.h"
25#include "rcar-gen3-cpg.h"
26
27#define CPG_PLL0CR 0x00d8
28#define CPG_PLL2CR 0x002c
29#define CPG_PLL4CR 0x01f4
30
31
32/*
33 * SDn Clock
34 */
35#define CPG_SD_STP_HCK BIT(9)
36#define CPG_SD_STP_CK BIT(8)
37
38#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
39#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
40
41#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
42{ \
43 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
44 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
45 ((sd_srcfc) << 2) | \
46 ((sd_fc) << 0), \
47 .div = (sd_div), \
48}
49
50struct sd_div_table {
51 u32 val;
52 unsigned int div;
53};
54
55struct sd_clock {
56 struct clk_hw hw;
57 void __iomem *reg;
58 const struct sd_div_table *div_table;
59 unsigned int div_num;
60 unsigned int div_min;
61 unsigned int div_max;
62};
63
64/* SDn divider
65 * sd_srcfc sd_fc div
66 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
67 *-------------------------------------------------------------------
68 * 0 0 0 (1) 1 (4) 4
69 * 0 0 1 (2) 1 (4) 8
70 * 1 0 2 (4) 1 (4) 16
71 * 1 0 3 (8) 1 (4) 32
72 * 1 0 4 (16) 1 (4) 64
73 * 0 0 0 (1) 0 (2) 2
74 * 0 0 1 (2) 0 (2) 4
75 * 1 0 2 (4) 0 (2) 8
76 * 1 0 3 (8) 0 (2) 16
77 * 1 0 4 (16) 0 (2) 32
78 */
79static const struct sd_div_table cpg_sd_div_table[] = {
80/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
81 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
82 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
83 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
84 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
85 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
86 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
87 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
88 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
89 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
90 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
91};
92
93#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
94
95static int cpg_sd_clock_enable(struct clk_hw *hw)
96{
97 struct sd_clock *clock = to_sd_clock(hw);
98 u32 val, sd_fc;
99 unsigned int i;
100
101 val = clk_readl(clock->reg);
102
103 sd_fc = val & CPG_SD_FC_MASK;
104 for (i = 0; i < clock->div_num; i++)
105 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
106 break;
107
108 if (i >= clock->div_num)
109 return -EINVAL;
110
111 val &= ~(CPG_SD_STP_MASK);
112 val |= clock->div_table[i].val & CPG_SD_STP_MASK;
113
114 clk_writel(val, clock->reg);
115
116 return 0;
117}
118
119static void cpg_sd_clock_disable(struct clk_hw *hw)
120{
121 struct sd_clock *clock = to_sd_clock(hw);
122
123 clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
124}
125
126static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
127{
128 struct sd_clock *clock = to_sd_clock(hw);
129
130 return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
131}
132
133static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
134 unsigned long parent_rate)
135{
136 struct sd_clock *clock = to_sd_clock(hw);
137 unsigned long rate = parent_rate;
138 u32 val, sd_fc;
139 unsigned int i;
140
141 val = clk_readl(clock->reg);
142
143 sd_fc = val & CPG_SD_FC_MASK;
144 for (i = 0; i < clock->div_num; i++)
145 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
146 break;
147
148 if (i >= clock->div_num)
149 return -EINVAL;
150
151 return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
152}
153
154static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
155 unsigned long rate,
156 unsigned long parent_rate)
157{
158 unsigned int div;
159
160 if (!rate)
161 rate = 1;
162
163 div = DIV_ROUND_CLOSEST(parent_rate, rate);
164
165 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
166}
167
168static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
169 unsigned long *parent_rate)
170{
171 struct sd_clock *clock = to_sd_clock(hw);
172 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
173
174 return DIV_ROUND_CLOSEST(*parent_rate, div);
175}
176
177static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
178 unsigned long parent_rate)
179{
180 struct sd_clock *clock = to_sd_clock(hw);
181 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
182 u32 val;
183 unsigned int i;
184
185 for (i = 0; i < clock->div_num; i++)
186 if (div == clock->div_table[i].div)
187 break;
188
189 if (i >= clock->div_num)
190 return -EINVAL;
191
192 val = clk_readl(clock->reg);
193 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
194 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
195 clk_writel(val, clock->reg);
196
197 return 0;
198}
199
200static const struct clk_ops cpg_sd_clock_ops = {
201 .enable = cpg_sd_clock_enable,
202 .disable = cpg_sd_clock_disable,
203 .is_enabled = cpg_sd_clock_is_enabled,
204 .recalc_rate = cpg_sd_clock_recalc_rate,
205 .round_rate = cpg_sd_clock_round_rate,
206 .set_rate = cpg_sd_clock_set_rate,
207};
208
209static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
210 void __iomem *base,
211 const char *parent_name)
212{
213 struct clk_init_data init;
214 struct sd_clock *clock;
215 struct clk *clk;
216 unsigned int i;
217
218 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
219 if (!clock)
220 return ERR_PTR(-ENOMEM);
221
222 init.name = core->name;
223 init.ops = &cpg_sd_clock_ops;
224 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
225 init.parent_names = &parent_name;
226 init.num_parents = 1;
227
228 clock->reg = base + core->offset;
229 clock->hw.init = &init;
230 clock->div_table = cpg_sd_div_table;
231 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
232
233 clock->div_max = clock->div_table[0].div;
234 clock->div_min = clock->div_max;
235 for (i = 1; i < clock->div_num; i++) {
236 clock->div_max = max(clock->div_max, clock->div_table[i].div);
237 clock->div_min = min(clock->div_min, clock->div_table[i].div);
238 }
239
240 clk = clk_register(NULL, &clock->hw);
241 if (IS_ERR(clk))
242 kfree(clock);
243
244 return clk;
245}
246
247
248static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
249static unsigned int cpg_clk_extalr __initdata;
250
251struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
252 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
253 struct clk **clks, void __iomem *base)
254{
255 const struct clk *parent;
256 unsigned int mult = 1;
257 unsigned int div = 1;
258 u32 value;
259
260 parent = clks[core->parent];
261 if (IS_ERR(parent))
262 return ERR_CAST(parent);
263
264 switch (core->type) {
265 case CLK_TYPE_GEN3_MAIN:
266 div = cpg_pll_config->extal_div;
267 break;
268
269 case CLK_TYPE_GEN3_PLL0:
270 /*
271 * PLL0 is a configurable multiplier clock. Register it as a
272 * fixed factor clock for now as there's no generic multiplier
273 * clock implementation and we currently have no need to change
274 * the multiplier value.
275 */
276 value = readl(base + CPG_PLL0CR);
277 mult = (((value >> 24) & 0x7f) + 1) * 2;
278 break;
279
280 case CLK_TYPE_GEN3_PLL1:
281 mult = cpg_pll_config->pll1_mult;
282 break;
283
284 case CLK_TYPE_GEN3_PLL2:
285 /*
286 * PLL2 is a configurable multiplier clock. Register it as a
287 * fixed factor clock for now as there's no generic multiplier
288 * clock implementation and we currently have no need to change
289 * the multiplier value.
290 */
291 value = readl(base + CPG_PLL2CR);
292 mult = (((value >> 24) & 0x7f) + 1) * 2;
293 break;
294
295 case CLK_TYPE_GEN3_PLL3:
296 mult = cpg_pll_config->pll3_mult;
297 break;
298
299 case CLK_TYPE_GEN3_PLL4:
300 /*
301 * PLL4 is a configurable multiplier clock. Register it as a
302 * fixed factor clock for now as there's no generic multiplier
303 * clock implementation and we currently have no need to change
304 * the multiplier value.
305 */
306 value = readl(base + CPG_PLL4CR);
307 mult = (((value >> 24) & 0x7f) + 1) * 2;
308 break;
309
310 case CLK_TYPE_GEN3_SD:
311 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
312
313 case CLK_TYPE_GEN3_R:
314 /*
315 * RINT is default.
316 * Only if EXTALR is populated, we switch to it.
317 */
318 value = readl(base + CPG_RCKCR) & 0x3f;
319
320 if (clk_get_rate(clks[cpg_clk_extalr])) {
321 parent = clks[cpg_clk_extalr];
322 value |= BIT(15);
323 }
324
325 writel(value, base + CPG_RCKCR);
326 break;
327
328 default:
329 return ERR_PTR(-EINVAL);
330 }
331
332 return clk_register_fixed_factor(NULL, core->name,
333 __clk_get_name(parent), 0, mult, div);
334}
335
336/*
337 * Reset register definitions.
338 */
339#define MODEMR 0xe6160060
340
341u32 __init rcar_gen3_read_mode_pins(void)
342{
343 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
344 u32 mode;
345
346 BUG_ON(!modemr);
347 mode = ioread32(modemr);
348 iounmap(modemr);
349
350 return mode;
351}
352
353int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
354 unsigned int clk_extalr)
355{
356 cpg_pll_config = config;
357 cpg_clk_extalr = clk_extalr;
358 return 0;
359}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
new file mode 100644
index 000000000000..f699085147d1
--- /dev/null
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -0,0 +1,43 @@
1/*
2 * R-Car Gen3 Clock Pulse Generator
3 *
4 * Copyright (C) 2015-2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
12#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
13
14enum rcar_gen3_clk_types {
15 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
16 CLK_TYPE_GEN3_PLL0,
17 CLK_TYPE_GEN3_PLL1,
18 CLK_TYPE_GEN3_PLL2,
19 CLK_TYPE_GEN3_PLL3,
20 CLK_TYPE_GEN3_PLL4,
21 CLK_TYPE_GEN3_SD,
22 CLK_TYPE_GEN3_R,
23};
24
25#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
26 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
27
28struct rcar_gen3_cpg_pll_config {
29 unsigned int extal_div;
30 unsigned int pll1_mult;
31 unsigned int pll3_mult;
32};
33
34#define CPG_RCKCR 0x240
35
36u32 rcar_gen3_read_mode_pins(void);
37struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
38 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
39 struct clk **clks, void __iomem *base);
40int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
41 unsigned int clk_extalr);
42
43#endif
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 210cd744a7a9..e1365e7491ae 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -509,6 +509,12 @@ static const struct of_device_id cpg_mssr_match[] = {
509 .data = &r8a7795_cpg_mssr_info, 509 .data = &r8a7795_cpg_mssr_info,
510 }, 510 },
511#endif 511#endif
512#ifdef CONFIG_ARCH_R8A7796
513 {
514 .compatible = "renesas,r8a7796-cpg-mssr",
515 .data = &r8a7796_cpg_mssr_info,
516 },
517#endif
512 { /* sentinel */ } 518 { /* sentinel */ }
513}; 519};
514 520
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 0d1e3e811e79..ee7edfaf1408 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -131,4 +131,5 @@ struct cpg_mssr_info {
131}; 131};
132 132
133extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; 133extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
134extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
134#endif 135#endif
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 016bdb0b793a..db6e5a9e6de6 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -151,8 +151,8 @@ PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
151PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 151PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
152PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 152PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
153 153
154PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" }; 154PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" };
155PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" }; 155PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" };
156PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; 156PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
157 157
158static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { 158static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
@@ -170,6 +170,34 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
170#define DFLAGS CLK_DIVIDER_HIWORD_MASK 170#define DFLAGS CLK_DIVIDER_HIWORD_MASK
171#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 171#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
172 172
173static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
174 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
175 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
176
177static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
178 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
179 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
180
181static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
182 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
183 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
184
185static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
186 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
187 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
188
189static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
190 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
191 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
192
193static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
194 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
195 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
196
197static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
198 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
199 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
200
173static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 201static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
174 /* 202 /*
175 * Clock-Architecture Diagram 1 203 * Clock-Architecture Diagram 1
@@ -335,7 +363,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
335 RK2928_CLKGATE_CON(2), 6, GFLAGS), 363 RK2928_CLKGATE_CON(2), 6, GFLAGS),
336 364
337 GATE(0, "sclk_hsadc", "ext_hsadc", 0, 365 GATE(0, "sclk_hsadc", "ext_hsadc", 0,
338 RK3288_CLKGATE_CON(10), 12, GFLAGS), 366 RK2928_CLKGATE_CON(10), 12, GFLAGS),
339 367
340 COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, 368 COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
341 RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, 369 RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
@@ -379,22 +407,21 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
379 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, 407 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
380 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, 408 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
381 RK2928_CLKGATE_CON(0), 3, GFLAGS), 409 RK2928_CLKGATE_CON(0), 3, GFLAGS),
382 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, 410 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
383 RK3288_CLKSEL_CON(8), 0, 411 RK2928_CLKSEL_CON(8), 0,
384 RK3288_CLKGATE_CON(0), 4, GFLAGS), 412 RK2928_CLKGATE_CON(0), 4, GFLAGS,
385 COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, 413 &rk3228_i2s0_fracmux),
386 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS, 414 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
387 RK2928_CLKGATE_CON(0), 5, GFLAGS), 415 RK2928_CLKGATE_CON(0), 5, GFLAGS),
388 416
389 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, 417 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
390 RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, 418 RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
391 RK2928_CLKGATE_CON(0), 10, GFLAGS), 419 RK2928_CLKGATE_CON(0), 10, GFLAGS),
392 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 420 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
393 RK3288_CLKSEL_CON(7), 0, 421 RK2928_CLKSEL_CON(7), 0,
394 RK3288_CLKGATE_CON(0), 11, GFLAGS), 422 RK2928_CLKGATE_CON(0), 11, GFLAGS,
395 MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, 423 &rk3228_i2s1_fracmux),
396 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), 424 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
397 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
398 RK2928_CLKGATE_CON(0), 14, GFLAGS), 425 RK2928_CLKGATE_CON(0), 14, GFLAGS),
399 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, 426 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
400 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, 427 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
@@ -403,21 +430,20 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
403 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, 430 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
404 RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, 431 RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
405 RK2928_CLKGATE_CON(0), 7, GFLAGS), 432 RK2928_CLKGATE_CON(0), 7, GFLAGS),
406 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 433 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
407 RK3288_CLKSEL_CON(30), 0, 434 RK2928_CLKSEL_CON(30), 0,
408 RK3288_CLKGATE_CON(0), 8, GFLAGS), 435 RK2928_CLKGATE_CON(0), 8, GFLAGS,
409 COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, 436 &rk3228_i2s2_fracmux),
410 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 437 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
411 RK2928_CLKGATE_CON(0), 9, GFLAGS), 438 RK2928_CLKGATE_CON(0), 9, GFLAGS),
412 439
413 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, 440 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
414 RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, 441 RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
415 RK2928_CLKGATE_CON(2), 10, GFLAGS), 442 RK2928_CLKGATE_CON(2), 10, GFLAGS),
416 COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, 443 COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
417 RK3288_CLKSEL_CON(20), 0, 444 RK2928_CLKSEL_CON(20), 0,
418 RK3288_CLKGATE_CON(2), 12, GFLAGS), 445 RK2928_CLKGATE_CON(2), 12, GFLAGS,
419 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, 446 &rk3228_spdif_fracmux),
420 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
421 447
422 GATE(0, "jtag", "ext_jtag", 0, 448 GATE(0, "jtag", "ext_jtag", 0,
423 RK2928_CLKGATE_CON(1), 3, GFLAGS), 449 RK2928_CLKGATE_CON(1), 3, GFLAGS),
@@ -456,45 +482,42 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
456 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, 482 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
457 0, RK2928_CLKSEL_CON(15), 12, 2, 483 0, RK2928_CLKSEL_CON(15), 12, 2,
458 MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), 484 MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
459 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 485 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
460 RK2928_CLKSEL_CON(17), 0, 486 RK2928_CLKSEL_CON(17), 0,
461 RK2928_CLKGATE_CON(1), 9, GFLAGS), 487 RK2928_CLKGATE_CON(1), 9, GFLAGS,
462 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 488 &rk3228_uart0_fracmux),
489 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
463 RK2928_CLKSEL_CON(18), 0, 490 RK2928_CLKSEL_CON(18), 0,
464 RK2928_CLKGATE_CON(1), 11, GFLAGS), 491 RK2928_CLKGATE_CON(1), 11, GFLAGS,
465 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 492 &rk3228_uart1_fracmux),
493 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
466 RK2928_CLKSEL_CON(19), 0, 494 RK2928_CLKSEL_CON(19), 0,
467 RK2928_CLKGATE_CON(1), 13, GFLAGS), 495 RK2928_CLKGATE_CON(1), 13, GFLAGS,
468 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 496 &rk3228_uart2_fracmux),
469 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
470 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
471 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
472 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
473 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
474 497
475 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 498 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
476 RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, 499 RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
477 RK2928_CLKGATE_CON(1), 0, GFLAGS), 500 RK2928_CLKGATE_CON(1), 0, GFLAGS),
478 501
479 COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0, 502 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
480 RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS, 503 RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
481 RK2928_CLKGATE_CON(1), 7, GFLAGS), 504 RK2928_CLKGATE_CON(1), 7, GFLAGS),
482 MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0, 505 MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
483 RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), 506 RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
484 MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, 507 MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
485 RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), 508 RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
486 GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0, 509 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
487 RK2928_CLKGATE_CON(5), 4, GFLAGS), 510 RK2928_CLKGATE_CON(5), 4, GFLAGS),
488 GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0, 511 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
489 RK2928_CLKGATE_CON(5), 3, GFLAGS), 512 RK2928_CLKGATE_CON(5), 3, GFLAGS),
490 GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0, 513 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
491 RK2928_CLKGATE_CON(5), 5, GFLAGS), 514 RK2928_CLKGATE_CON(5), 5, GFLAGS),
492 GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0, 515 GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
493 RK2928_CLKGATE_CON(5), 6, GFLAGS), 516 RK2928_CLKGATE_CON(5), 6, GFLAGS),
494 COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0, 517 COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
495 RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS, 518 RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
496 RK2928_CLKGATE_CON(5), 7, GFLAGS), 519 RK2928_CLKGATE_CON(5), 7, GFLAGS),
497 COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0, 520 COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
498 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS, 521 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
499 RK2928_CLKGATE_CON(2), 2, GFLAGS), 522 RK2928_CLKGATE_CON(2), 2, GFLAGS),
500 523
@@ -528,7 +551,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
528 551
529 /* PD_PERI */ 552 /* PD_PERI */
530 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS), 553 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
531 GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), 554 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
532 555
533 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS), 556 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
534 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS), 557 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
@@ -544,7 +567,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
544 GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS), 567 GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
545 GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS), 568 GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
546 569
547 GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), 570 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
548 GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS), 571 GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
549 572
550 /* PD_GPU */ 573 /* PD_GPU */
@@ -558,10 +581,10 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
558 GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), 581 GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
559 582
560 GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), 583 GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
561 GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), 584 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
562 GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), 585 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
563 GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), 586 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
564 GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), 587 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
565 GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), 588 GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
566 GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), 589 GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
567 GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), 590 GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 8059a8d3ea36..c109d80e7a8a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
586 RK3399_CLKGATE_CON(8), 15, GFLAGS), 586 RK3399_CLKGATE_CON(8), 15, GFLAGS),
587 587
588 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, 588 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
589 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, 589 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
590 RK3399_CLKGATE_CON(10), 6, GFLAGS), 590 RK3399_CLKGATE_CON(10), 6, GFLAGS),
591 /* i2s */ 591 /* i2s */
592 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, 592 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
@@ -1500,6 +1500,7 @@ static void __init rk3399_clk_init(struct device_node *np)
1500{ 1500{
1501 struct rockchip_clk_provider *ctx; 1501 struct rockchip_clk_provider *ctx;
1502 void __iomem *reg_base; 1502 void __iomem *reg_base;
1503 struct clk *clk;
1503 1504
1504 reg_base = of_iomap(np, 0); 1505 reg_base = of_iomap(np, 0);
1505 if (!reg_base) { 1506 if (!reg_base) {
@@ -1514,6 +1515,14 @@ static void __init rk3399_clk_init(struct device_node *np)
1514 return; 1515 return;
1515 } 1516 }
1516 1517
1518 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1519 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1520 if (IS_ERR(clk))
1521 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1522 __func__, PTR_ERR(clk));
1523 else
1524 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1525
1517 rockchip_clk_register_plls(ctx, rk3399_pll_clks, 1526 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1518 ARRAY_SIZE(rk3399_pll_clks), -1); 1527 ARRAY_SIZE(rk3399_pll_clks), -1);
1519 1528
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
index 20c5fe92ab4a..addc65270e43 100644
--- a/drivers/clk/samsung/Kconfig
+++ b/drivers/clk/samsung/Kconfig
@@ -9,6 +9,15 @@ config EXYNOS_ARM64_COMMON_CLK
9 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST 9 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
10 depends on COMMON_CLK_SAMSUNG 10 depends on COMMON_CLK_SAMSUNG
11 11
12config EXYNOS_AUDSS_CLK_CON
13 tristate "Samsung Exynos AUDSS clock controller support"
14 depends on COMMON_CLK_SAMSUNG
15 default y if ARCH_EXYNOS
16 help
17 Support for the Audio Subsystem CLKCON clock controller present
18 on some Exynos SoC variants. Choose M or Y here if you want to
19 use audio devices such as I2S, PCM, etc.
20
12# For S3C24XX platforms, select following symbols: 21# For S3C24XX platforms, select following symbols:
13config S3C2410_COMMON_CLK 22config S3C2410_COMMON_CLK
14 bool "Samsung S3C2410 clock controller support" if COMPILE_TEST 23 bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index fc367d4b2902..57f4dc6dc447 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
12obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 12obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
13obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o 13obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
14obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 14obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
15obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 15obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
16obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o 16obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
17obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o 17obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
18obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o 18obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 813003d6ce09..8bf7e805fd34 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -45,6 +45,13 @@
45#define E4210_DIV_STAT_CPU0 0x400 45#define E4210_DIV_STAT_CPU0 0x400
46#define E4210_DIV_STAT_CPU1 0x404 46#define E4210_DIV_STAT_CPU1 0x404
47 47
48#define E5433_MUX_SEL2 0x008
49#define E5433_MUX_STAT2 0x208
50#define E5433_DIV_CPU0 0x400
51#define E5433_DIV_CPU1 0x404
52#define E5433_DIV_STAT_CPU0 0x500
53#define E5433_DIV_STAT_CPU1 0x504
54
48#define E4210_DIV0_RATIO0_MASK 0x7 55#define E4210_DIV0_RATIO0_MASK 0x7
49#define E4210_DIV1_HPM_MASK (0x7 << 4) 56#define E4210_DIV1_HPM_MASK (0x7 << 4)
50#define E4210_DIV1_COPY_MASK (0x7 << 0) 57#define E4210_DIV1_COPY_MASK (0x7 << 0)
@@ -253,6 +260,102 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
253} 260}
254 261
255/* 262/*
263 * Helper function to set the 'safe' dividers for the CPU clock. The parameters
264 * div and mask contain the divider value and the register bit mask of the
265 * dividers to be programmed.
266 */
267static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
268 unsigned long mask)
269{
270 unsigned long div0;
271
272 div0 = readl(base + E5433_DIV_CPU0);
273 div0 = (div0 & ~mask) | (div & mask);
274 writel(div0, base + E5433_DIV_CPU0);
275 wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
276}
277
278/* handler for pre-rate change notification from parent clock */
279static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
280 struct exynos_cpuclk *cpuclk, void __iomem *base)
281{
282 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
283 unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
284 unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
285 unsigned long div0, div1 = 0, mux_reg;
286 unsigned long flags;
287
288 /* find out the divider values to use for clock data */
289 while ((cfg_data->prate * 1000) != ndata->new_rate) {
290 if (cfg_data->prate == 0)
291 return -EINVAL;
292 cfg_data++;
293 }
294
295 spin_lock_irqsave(cpuclk->lock, flags);
296
297 /*
298 * For the selected PLL clock frequency, get the pre-defined divider
299 * values.
300 */
301 div0 = cfg_data->div0;
302 div1 = cfg_data->div1;
303
304 /*
305 * If the old parent clock speed is less than the clock speed of
306 * the alternate parent, then it should be ensured that at no point
307 * the armclk speed is more than the old_prate until the dividers are
308 * set. Also workaround the issue of the dividers being set to lower
309 * values before the parent clock speed is set to new lower speed
310 * (this can result in too high speed of armclk output clocks).
311 */
312 if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
313 unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
314
315 alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
316 WARN_ON(alt_div >= MAX_DIV);
317
318 exynos5433_set_safe_div(base, alt_div, alt_div_mask);
319 div0 |= alt_div;
320 }
321
322 /* select the alternate parent */
323 mux_reg = readl(base + E5433_MUX_SEL2);
324 writel(mux_reg | 1, base + E5433_MUX_SEL2);
325 wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
326
327 /* alternate parent is active now. set the dividers */
328 writel(div0, base + E5433_DIV_CPU0);
329 wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
330
331 writel(div1, base + E5433_DIV_CPU1);
332 wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
333
334 spin_unlock_irqrestore(cpuclk->lock, flags);
335 return 0;
336}
337
338/* handler for post-rate change notification from parent clock */
339static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
340 struct exynos_cpuclk *cpuclk, void __iomem *base)
341{
342 unsigned long div = 0, div_mask = DIV_MASK;
343 unsigned long mux_reg;
344 unsigned long flags;
345
346 spin_lock_irqsave(cpuclk->lock, flags);
347
348 /* select apll as the alternate parent */
349 mux_reg = readl(base + E5433_MUX_SEL2);
350 writel(mux_reg & ~1, base + E5433_MUX_SEL2);
351 wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
352
353 exynos5433_set_safe_div(base, div, div_mask);
354 spin_unlock_irqrestore(cpuclk->lock, flags);
355 return 0;
356}
357
358/*
256 * This notifier function is called for the pre-rate and post-rate change 359 * This notifier function is called for the pre-rate and post-rate change
257 * notifications of the parent clock of cpuclk. 360 * notifications of the parent clock of cpuclk.
258 */ 361 */
@@ -275,6 +378,29 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
275 return notifier_from_errno(err); 378 return notifier_from_errno(err);
276} 379}
277 380
381/*
382 * This notifier function is called for the pre-rate and post-rate change
383 * notifications of the parent clock of cpuclk.
384 */
385static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
386 unsigned long event, void *data)
387{
388 struct clk_notifier_data *ndata = data;
389 struct exynos_cpuclk *cpuclk;
390 void __iomem *base;
391 int err = 0;
392
393 cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
394 base = cpuclk->ctrl_base;
395
396 if (event == PRE_RATE_CHANGE)
397 err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
398 else if (event == POST_RATE_CHANGE)
399 err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
400
401 return notifier_from_errno(err);
402}
403
278/* helper function to register a CPU clock */ 404/* helper function to register a CPU clock */
279int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 405int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
280 unsigned int lookup_id, const char *name, const char *parent, 406 unsigned int lookup_id, const char *name, const char *parent,
@@ -301,7 +427,10 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
301 cpuclk->ctrl_base = ctx->reg_base + offset; 427 cpuclk->ctrl_base = ctx->reg_base + offset;
302 cpuclk->lock = &ctx->lock; 428 cpuclk->lock = &ctx->lock;
303 cpuclk->flags = flags; 429 cpuclk->flags = flags;
304 cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; 430 if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
431 cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
432 else
433 cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
305 434
306 cpuclk->alt_parent = __clk_lookup(alt_parent); 435 cpuclk->alt_parent = __clk_lookup(alt_parent);
307 if (!cpuclk->alt_parent) { 436 if (!cpuclk->alt_parent) {
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 37874d3c3165..d4b6b517fe1b 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -57,10 +57,12 @@ struct exynos_cpuclk {
57 struct notifier_block clk_nb; 57 struct notifier_block clk_nb;
58 unsigned long flags; 58 unsigned long flags;
59 59
60/* The CPU clock registers has DIV1 configuration register */ 60/* The CPU clock registers have DIV1 configuration register */
61#define CLK_CPU_HAS_DIV1 (1 << 0) 61#define CLK_CPU_HAS_DIV1 (1 << 0)
62/* When ALT parent is active, debug clocks need safe divider values */ 62/* When ALT parent is active, debug clocks need safe divider values */
63#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) 63#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
64/* The CPU clock registers have Exynos5433-compatible layout */
65#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
64}; 66};
65 67
66extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 68extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 4e9584d79089..bdf8b971f332 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -273,17 +273,7 @@ static struct platform_driver exynos_audss_clk_driver = {
273 .remove = exynos_audss_clk_remove, 273 .remove = exynos_audss_clk_remove,
274}; 274};
275 275
276static int __init exynos_audss_clk_init(void) 276module_platform_driver(exynos_audss_clk_driver);
277{
278 return platform_driver_register(&exynos_audss_clk_driver);
279}
280core_initcall(exynos_audss_clk_init);
281
282static void __exit exynos_audss_clk_exit(void)
283{
284 platform_driver_unregister(&exynos_audss_clk_driver);
285}
286module_exit(exynos_audss_clk_exit);
287 277
288MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>"); 278MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
289MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller"); 279MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index 7cd02ff37a1f..96fab6cfb202 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -151,6 +151,8 @@ static void __init exynos5_clkout_init(struct device_node *node)
151} 151}
152CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu", 152CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
153 exynos5_clkout_init); 153 exynos5_clkout_init);
154CLK_OF_DECLARE(exynos5410_clkout, "samsung,exynos5410-pmu",
155 exynos5_clkout_init);
154CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu", 156CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
155 exynos5_clkout_init); 157 exynos5_clkout_init);
156CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu", 158CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu",
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 16575ee874cb..1b81e283f605 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -103,7 +103,7 @@
103#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 103#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
104#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 104#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
105 105
106static unsigned long exynos3250_cmu_clk_regs[] __initdata = { 106static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
107 SRC_LEFTBUS, 107 SRC_LEFTBUS,
108 DIV_LEFTBUS, 108 DIV_LEFTBUS,
109 GATE_IP_LEFTBUS, 109 GATE_IP_LEFTBUS,
@@ -226,7 +226,7 @@ PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
226PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" }; 226PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
227PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; 227PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
228 228
229static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { 229static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
230 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0), 230 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
231 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0), 231 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
232 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0), 232 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
@@ -237,7 +237,7 @@ static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
237 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), 237 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
238}; 238};
239 239
240static struct samsung_mux_clock mux_clks[] __initdata = { 240static const struct samsung_mux_clock mux_clks[] __initconst = {
241 /* 241 /*
242 * NOTE: Following table is sorted by register address in ascending 242 * NOTE: Following table is sorted by register address in ascending
243 * order and then bitfield shift in descending order, as it is done 243 * order and then bitfield shift in descending order, as it is done
@@ -326,7 +326,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
326 CLK_SET_RATE_PARENT, 0), 326 CLK_SET_RATE_PARENT, 0),
327}; 327};
328 328
329static struct samsung_div_clock div_clks[] __initdata = { 329static const struct samsung_div_clock div_clks[] __initconst = {
330 /* 330 /*
331 * NOTE: Following table is sorted by register address in ascending 331 * NOTE: Following table is sorted by register address in ascending
332 * order and then bitfield shift in descending order, as it is done 332 * order and then bitfield shift in descending order, as it is done
@@ -429,7 +429,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
429 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 429 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
430}; 430};
431 431
432static struct samsung_gate_clock gate_clks[] __initdata = { 432static const struct samsung_gate_clock gate_clks[] __initconst = {
433 /* 433 /*
434 * NOTE: Following table is sorted by register address in ascending 434 * NOTE: Following table is sorted by register address in ascending
435 * order and then bitfield shift in descending order, as it is done 435 * order and then bitfield shift in descending order, as it is done
@@ -669,7 +669,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
669}; 669};
670 670
671/* APLL & MPLL & BPLL & UPLL */ 671/* APLL & MPLL & BPLL & UPLL */
672static struct samsung_pll_rate_table exynos3250_pll_rates[] = { 672static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
673 PLL_35XX_RATE(1200000000, 400, 4, 1), 673 PLL_35XX_RATE(1200000000, 400, 4, 1),
674 PLL_35XX_RATE(1100000000, 275, 3, 1), 674 PLL_35XX_RATE(1100000000, 275, 3, 1),
675 PLL_35XX_RATE(1066000000, 533, 6, 1), 675 PLL_35XX_RATE(1066000000, 533, 6, 1),
@@ -691,7 +691,7 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
691}; 691};
692 692
693/* EPLL */ 693/* EPLL */
694static struct samsung_pll_rate_table exynos3250_epll_rates[] = { 694static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
695 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 695 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
696 PLL_36XX_RATE(288000000, 96, 2, 2, 0), 696 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
697 PLL_36XX_RATE(192000000, 128, 2, 3, 0), 697 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
@@ -710,7 +710,7 @@ static struct samsung_pll_rate_table exynos3250_epll_rates[] = {
710}; 710};
711 711
712/* VPLL */ 712/* VPLL */
713static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { 713static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
714 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 714 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
715 PLL_36XX_RATE(533000000, 266, 3, 2, 32768), 715 PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
716 PLL_36XX_RATE(519230987, 173, 2, 2, 5046), 716 PLL_36XX_RATE(519230987, 173, 2, 2, 5046),
@@ -740,7 +740,7 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
740 { /* sentinel */ } 740 { /* sentinel */ }
741}; 741};
742 742
743static struct samsung_pll_clock exynos3250_plls[] __initdata = { 743static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
744 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 744 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
745 APLL_LOCK, APLL_CON0, exynos3250_pll_rates), 745 APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
746 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 746 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
@@ -772,7 +772,7 @@ static void __init exynos3_core_down_clock(void __iomem *reg_base)
772 __raw_writel(0x0, reg_base + PWR_CTRL2); 772 __raw_writel(0x0, reg_base + PWR_CTRL2);
773} 773}
774 774
775static struct samsung_cmu_info cmu_info __initdata = { 775static const struct samsung_cmu_info cmu_info __initconst = {
776 .pll_clks = exynos3250_plls, 776 .pll_clks = exynos3250_plls,
777 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls), 777 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
778 .mux_clks = mux_clks, 778 .mux_clks = mux_clks,
@@ -848,7 +848,7 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
848#define EPLL_CON2 0x111c 848#define EPLL_CON2 0x111c
849#define SRC_EPLL 0x1120 849#define SRC_EPLL 0x1120
850 850
851static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { 851static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
852 BPLL_LOCK, 852 BPLL_LOCK,
853 BPLL_CON0, 853 BPLL_CON0,
854 BPLL_CON1, 854 BPLL_CON1,
@@ -874,7 +874,7 @@ PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
874PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; 874PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
875PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", }; 875PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };
876 876
877static struct samsung_mux_clock dmc_mux_clks[] __initdata = { 877static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
878 /* 878 /*
879 * NOTE: Following table is sorted by register address in ascending 879 * NOTE: Following table is sorted by register address in ascending
880 * order and then bitfield shift in descending order, as it is done 880 * order and then bitfield shift in descending order, as it is done
@@ -893,7 +893,7 @@ static struct samsung_mux_clock dmc_mux_clks[] __initdata = {
893 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1), 893 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
894}; 894};
895 895
896static struct samsung_div_clock dmc_div_clks[] __initdata = { 896static const struct samsung_div_clock dmc_div_clks[] __initconst = {
897 /* 897 /*
898 * NOTE: Following table is sorted by register address in ascending 898 * NOTE: Following table is sorted by register address in ascending
899 * order and then bitfield shift in descending order, as it is done 899 * order and then bitfield shift in descending order, as it is done
@@ -910,14 +910,14 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = {
910 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), 910 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
911}; 911};
912 912
913static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = { 913static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
914 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", 914 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
915 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates), 915 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
916 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 916 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
917 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates), 917 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
918}; 918};
919 919
920static struct samsung_cmu_info dmc_cmu_info __initdata = { 920static const struct samsung_cmu_info dmc_cmu_info __initconst = {
921 .pll_clks = exynos3250_dmc_plls, 921 .pll_clks = exynos3250_dmc_plls,
922 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls), 922 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
923 .mux_clks = dmc_mux_clks, 923 .mux_clks = dmc_mux_clks,
@@ -947,7 +947,7 @@ CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
947#define GATE_IP_ISP1 0x804 947#define GATE_IP_ISP1 0x804
948#define GATE_SCLK_ISP 0x900 948#define GATE_SCLK_ISP 0x900
949 949
950static struct samsung_div_clock isp_div_clks[] __initdata = { 950static const struct samsung_div_clock isp_div_clks[] __initconst = {
951 /* 951 /*
952 * NOTE: Following table is sorted by register address in ascending 952 * NOTE: Following table is sorted by register address in ascending
953 * order and then bitfield shift in descending order, as it is done 953 * order and then bitfield shift in descending order, as it is done
@@ -967,7 +967,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = {
967 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3), 967 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
968}; 968};
969 969
970static struct samsung_gate_clock isp_gate_clks[] __initdata = { 970static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
971 /* 971 /*
972 * NOTE: Following table is sorted by register address in ascending 972 * NOTE: Following table is sorted by register address in ascending
973 * order and then bitfield shift in descending order, as it is done 973 * order and then bitfield shift in descending order, as it is done
@@ -1063,7 +1063,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = {
1063 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 1063 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
1064}; 1064};
1065 1065
1066static struct samsung_cmu_info isp_cmu_info __initdata = { 1066static const struct samsung_cmu_info isp_cmu_info __initconst = {
1067 .div_clks = isp_div_clks, 1067 .div_clks = isp_div_clks,
1068 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 1068 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
1069 .gate_clks = isp_gate_clks, 1069 .gate_clks = isp_gate_clks,
@@ -1079,14 +1079,15 @@ static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
1079 return 0; 1079 return 0;
1080} 1080}
1081 1081
1082static const struct of_device_id exynos3250_cmu_isp_of_match[] = { 1082static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
1083 { .compatible = "samsung,exynos3250-cmu-isp", }, 1083 { .compatible = "samsung,exynos3250-cmu-isp", },
1084 { /* sentinel */ } 1084 { /* sentinel */ }
1085}; 1085};
1086 1086
1087static struct platform_driver exynos3250_cmu_isp_driver = { 1087static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
1088 .driver = { 1088 .driver = {
1089 .name = "exynos3250-cmu-isp", 1089 .name = "exynos3250-cmu-isp",
1090 .suppress_bind_attrs = true,
1090 .of_match_table = exynos3250_cmu_isp_of_match, 1091 .of_match_table = exynos3250_cmu_isp_of_match,
1091 }, 1092 },
1092}; 1093};
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7b3d0f975987..faab9b31baf5 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -169,7 +169,7 @@ static struct samsung_clk_reg_dump *exynos4_save_pll;
169 * list of controller registers to be saved and restored during a 169 * list of controller registers to be saved and restored during a
170 * suspend/resume cycle. 170 * suspend/resume cycle.
171 */ 171 */
172static unsigned long exynos4210_clk_save[] __initdata = { 172static const unsigned long exynos4210_clk_save[] __initconst = {
173 E4210_SRC_IMAGE, 173 E4210_SRC_IMAGE,
174 E4210_SRC_LCD1, 174 E4210_SRC_LCD1,
175 E4210_SRC_MASK_LCD1, 175 E4210_SRC_MASK_LCD1,
@@ -181,7 +181,7 @@ static unsigned long exynos4210_clk_save[] __initdata = {
181 PWR_CTRL1, 181 PWR_CTRL1,
182}; 182};
183 183
184static unsigned long exynos4x12_clk_save[] __initdata = { 184static const unsigned long exynos4x12_clk_save[] __initconst = {
185 E4X12_GATE_IP_IMAGE, 185 E4X12_GATE_IP_IMAGE,
186 E4X12_GATE_IP_PERIR, 186 E4X12_GATE_IP_PERIR,
187 E4X12_SRC_CAM1, 187 E4X12_SRC_CAM1,
@@ -192,7 +192,7 @@ static unsigned long exynos4x12_clk_save[] __initdata = {
192 E4X12_PWR_CTRL2, 192 E4X12_PWR_CTRL2,
193}; 193};
194 194
195static unsigned long exynos4_clk_pll_regs[] __initdata = { 195static const unsigned long exynos4_clk_pll_regs[] __initconst = {
196 EPLL_LOCK, 196 EPLL_LOCK,
197 VPLL_LOCK, 197 VPLL_LOCK,
198 EPLL_CON0, 198 EPLL_CON0,
@@ -203,7 +203,7 @@ static unsigned long exynos4_clk_pll_regs[] __initdata = {
203 VPLL_CON2, 203 VPLL_CON2,
204}; 204};
205 205
206static unsigned long exynos4_clk_regs[] __initdata = { 206static const unsigned long exynos4_clk_regs[] __initconst = {
207 SRC_LEFTBUS, 207 SRC_LEFTBUS,
208 DIV_LEFTBUS, 208 DIV_LEFTBUS,
209 GATE_IP_LEFTBUS, 209 GATE_IP_LEFTBUS,
@@ -505,28 +505,28 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
505}; 505};
506 506
507/* fixed rate clocks generated inside the soc */ 507/* fixed rate clocks generated inside the soc */
508static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 508static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
509 FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000), 509 FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
510 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000), 510 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
511 FRATE(0, "sclk_usbphy0", NULL, 0, 48000000), 511 FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
512}; 512};
513 513
514static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 514static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
515 FRATE(0, "sclk_usbphy1", NULL, 0, 48000000), 515 FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
516}; 516};
517 517
518static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = { 518static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
519 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0), 519 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
520 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0), 520 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
521 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0), 521 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
522 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0), 522 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
523}; 523};
524 524
525static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = { 525static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
526 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0), 526 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
527}; 527};
528 528
529static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = { 529static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
530 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0), 530 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
531 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0), 531 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
532 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0), 532 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
@@ -534,7 +534,7 @@ static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initda
534}; 534};
535 535
536/* list of mux clocks supported in all exynos4 soc's */ 536/* list of mux clocks supported in all exynos4 soc's */
537static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 537static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
538 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 538 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
539 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0, 539 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
540 "mout_apll"), 540 "mout_apll"),
@@ -555,11 +555,11 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
555}; 555};
556 556
557/* list of mux clocks supported in exynos4210 soc */ 557/* list of mux clocks supported in exynos4210 soc */
558static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 558static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
559 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 559 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
560}; 560};
561 561
562static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 562static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
563 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1), 563 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
564 MUX(0, "mout_clkout_leftbus", clkout_left_p4210, 564 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
565 CLKOUT_CMU_LEFTBUS, 0, 5), 565 CLKOUT_CMU_LEFTBUS, 0, 5),
@@ -622,7 +622,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
622}; 622};
623 623
624/* list of mux clocks supported in exynos4x12 soc */ 624/* list of mux clocks supported in exynos4x12 soc */
625static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 625static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
626 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1), 626 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
627 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1), 627 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
628 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12, 628 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
@@ -705,7 +705,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
705}; 705};
706 706
707/* list of divider clocks supported in all exynos4 soc's */ 707/* list of divider clocks supported in all exynos4 soc's */
708static struct samsung_div_clock exynos4_div_clks[] __initdata = { 708static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
709 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 709 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
710 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 710 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
711 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", 711 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
@@ -795,7 +795,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
795}; 795};
796 796
797/* list of divider clocks supported in exynos4210 soc */ 797/* list of divider clocks supported in exynos4210 soc */
798static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 798static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
799 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 799 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
800 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 800 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
801 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 801 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
@@ -806,7 +806,7 @@ static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
806}; 806};
807 807
808/* list of divider clocks supported in exynos4x12 soc */ 808/* list of divider clocks supported in exynos4x12 soc */
809static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 809static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
810 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 810 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
811 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 811 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
812 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 812 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
@@ -837,7 +837,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
837}; 837};
838 838
839/* list of gate clocks supported in all exynos4 soc's */ 839/* list of gate clocks supported in all exynos4 soc's */
840static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 840static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
841 /* 841 /*
842 * After all Exynos4 based platforms are migrated to use device tree, 842 * After all Exynos4 based platforms are migrated to use device tree,
843 * the device name and clock alias names specified below for some 843 * the device name and clock alias names specified below for some
@@ -1043,7 +1043,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
1043}; 1043};
1044 1044
1045/* list of gate clocks supported in exynos4210 soc */ 1045/* list of gate clocks supported in exynos4210 soc */
1046static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 1046static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
1047 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 1047 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
1048 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 1048 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
1049 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 1049 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
@@ -1090,7 +1090,7 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
1090}; 1090};
1091 1091
1092/* list of gate clocks supported in exynos4x12 soc */ 1092/* list of gate clocks supported in exynos4x12 soc */
1093static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 1093static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
1094 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 1094 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
1095 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 1095 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
1096 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 1096 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
@@ -1190,17 +1190,17 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
1190 0), 1190 0),
1191}; 1191};
1192 1192
1193static struct samsung_clock_alias exynos4_aliases[] __initdata = { 1193static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
1194 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), 1194 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
1195 ALIAS(CLK_ARM_CLK, NULL, "armclk"), 1195 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
1196 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), 1196 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
1197}; 1197};
1198 1198
1199static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 1199static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
1200 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), 1200 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
1201}; 1201};
1202 1202
1203static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 1203static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
1204 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), 1204 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
1205}; 1205};
1206 1206
@@ -1211,7 +1211,7 @@ static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
1211 * controller is first remapped and the value of XOM[0] bit is read to 1211 * controller is first remapped and the value of XOM[0] bit is read to
1212 * determine the parent clock. 1212 * determine the parent clock.
1213 */ 1213 */
1214static unsigned long exynos4_get_xom(void) 1214static unsigned long __init exynos4_get_xom(void)
1215{ 1215{
1216 unsigned long xom = 0; 1216 unsigned long xom = 0;
1217 void __iomem *chipid_base; 1217 void __iomem *chipid_base;
@@ -1264,7 +1264,7 @@ static const struct of_device_id ext_clk_match[] __initconst = {
1264}; 1264};
1265 1265
1266/* PLLs PMS values */ 1266/* PLLs PMS values */
1267static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { 1267static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
1268 PLL_45XX_RATE(1200000000, 150, 3, 1, 28), 1268 PLL_45XX_RATE(1200000000, 150, 3, 1, 28),
1269 PLL_45XX_RATE(1000000000, 250, 6, 1, 28), 1269 PLL_45XX_RATE(1000000000, 250, 6, 1, 28),
1270 PLL_45XX_RATE( 800000000, 200, 6, 1, 28), 1270 PLL_45XX_RATE( 800000000, 200, 6, 1, 28),
@@ -1277,7 +1277,7 @@ static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {
1277 { /* sentinel */ } 1277 { /* sentinel */ }
1278}; 1278};
1279 1279
1280static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { 1280static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
1281 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), 1281 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0),
1282 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), 1282 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
1283 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), 1283 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0),
@@ -1288,7 +1288,7 @@ static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {
1288 { /* sentinel */ } 1288 { /* sentinel */ }
1289}; 1289};
1290 1290
1291static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { 1291static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
1292 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), 1292 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),
1293 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), 1293 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1),
1294 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), 1294 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
@@ -1297,7 +1297,7 @@ static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {
1297 { /* sentinel */ } 1297 { /* sentinel */ }
1298}; 1298};
1299 1299
1300static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { 1300static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
1301 PLL_35XX_RATE(1500000000, 250, 4, 0), 1301 PLL_35XX_RATE(1500000000, 250, 4, 0),
1302 PLL_35XX_RATE(1400000000, 175, 3, 0), 1302 PLL_35XX_RATE(1400000000, 175, 3, 0),
1303 PLL_35XX_RATE(1300000000, 325, 6, 0), 1303 PLL_35XX_RATE(1300000000, 325, 6, 0),
@@ -1315,7 +1315,7 @@ static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {
1315 { /* sentinel */ } 1315 { /* sentinel */ }
1316}; 1316};
1317 1317
1318static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { 1318static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
1319 PLL_36XX_RATE(192000000, 48, 3, 1, 0), 1319 PLL_36XX_RATE(192000000, 48, 3, 1, 0),
1320 PLL_36XX_RATE(180633605, 45, 3, 1, 10381), 1320 PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
1321 PLL_36XX_RATE(180000000, 45, 3, 1, 0), 1321 PLL_36XX_RATE(180000000, 45, 3, 1, 0),
@@ -1326,7 +1326,7 @@ static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {
1326 { /* sentinel */ } 1326 { /* sentinel */ }
1327}; 1327};
1328 1328
1329static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { 1329static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
1330 PLL_36XX_RATE(533000000, 133, 3, 1, 16384), 1330 PLL_36XX_RATE(533000000, 133, 3, 1, 16384),
1331 PLL_36XX_RATE(440000000, 110, 3, 1, 0), 1331 PLL_36XX_RATE(440000000, 110, 3, 1, 0),
1332 PLL_36XX_RATE(350000000, 175, 3, 2, 0), 1332 PLL_36XX_RATE(350000000, 175, 3, 2, 0),
@@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void)
1375 if (num_possible_cpus() == 4) 1375 if (num_possible_cpus() == 4)
1376 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | 1376 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1377 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; 1377 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1378 __raw_writel(tmp, reg_base + PWR_CTRL1); 1378 writel_relaxed(tmp, reg_base + PWR_CTRL1);
1379 1379
1380 /* 1380 /*
1381 * Disable the clock up feature in case it was enabled by bootloader. 1381 * Disable the clock up feature in case it was enabled by bootloader.
1382 */ 1382 */
1383 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2); 1383 writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
1384} 1384}
1385 1385
1386#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ 1386#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
@@ -1450,8 +1450,6 @@ static void __init exynos4_clk_init(struct device_node *np,
1450 panic("%s: failed to map registers\n", __func__); 1450 panic("%s: failed to map registers\n", __func__);
1451 1451
1452 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1452 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1453 if (!ctx)
1454 panic("%s: unable to allocate context.\n", __func__);
1455 1453
1456 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, 1454 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1457 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1455 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
index 86ee06b226bd..6c9063159717 100644
--- a/drivers/clk/samsung/clk-exynos4415.c
+++ b/drivers/clk/samsung/clk-exynos4415.c
@@ -111,7 +111,7 @@
111#define DIV_CPU0 0x14500 111#define DIV_CPU0 0x14500
112#define DIV_CPU1 0x14504 112#define DIV_CPU1 0x14504
113 113
114static unsigned long exynos4415_cmu_clk_regs[] __initdata = { 114static const unsigned long exynos4415_cmu_clk_regs[] __initconst = {
115 SRC_LEFTBUS, 115 SRC_LEFTBUS,
116 DIV_LEFTBUS, 116 DIV_LEFTBUS,
117 GATE_IP_LEFTBUS, 117 GATE_IP_LEFTBUS,
@@ -268,16 +268,16 @@ PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
268PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" }; 268PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
269PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" }; 269PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
270 270
271static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = { 271static const struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initconst = {
272 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ 272 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
273 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), 273 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
274}; 274};
275 275
276static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = { 276static const struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initconst = {
277 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000), 277 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
278}; 278};
279 279
280static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = { 280static const struct samsung_mux_clock exynos4415_mux_clks[] __initconst = {
281 /* 281 /*
282 * NOTE: Following table is sorted by register address in ascending 282 * NOTE: Following table is sorted by register address in ascending
283 * order and then bitfield shift in descending order, as it is done 283 * order and then bitfield shift in descending order, as it is done
@@ -427,7 +427,7 @@ static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
427 group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1), 427 group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
428}; 428};
429 429
430static struct samsung_div_clock exynos4415_div_clks[] __initdata = { 430static const struct samsung_div_clock exynos4415_div_clks[] __initconst = {
431 /* 431 /*
432 * NOTE: Following table is sorted by register address in ascending 432 * NOTE: Following table is sorted by register address in ascending
433 * order and then bitfield shift in descending order, as it is done 433 * order and then bitfield shift in descending order, as it is done
@@ -566,7 +566,7 @@ static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
566 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 566 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
567}; 567};
568 568
569static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = { 569static const struct samsung_gate_clock exynos4415_gate_clks[] __initconst = {
570 /* 570 /*
571 * NOTE: Following table is sorted by register address in ascending 571 * NOTE: Following table is sorted by register address in ascending
572 * order and then bitfield shift in descending order, as it is done 572 * order and then bitfield shift in descending order, as it is done
@@ -859,7 +859,7 @@ static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
859/* 859/*
860 * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL 860 * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
861 */ 861 */
862static struct samsung_pll_rate_table exynos4415_pll_rates[] = { 862static const struct samsung_pll_rate_table exynos4415_pll_rates[] __initconst = {
863 PLL_35XX_RATE(1600000000, 400, 3, 1), 863 PLL_35XX_RATE(1600000000, 400, 3, 1),
864 PLL_35XX_RATE(1500000000, 250, 2, 1), 864 PLL_35XX_RATE(1500000000, 250, 2, 1),
865 PLL_35XX_RATE(1400000000, 175, 3, 0), 865 PLL_35XX_RATE(1400000000, 175, 3, 0),
@@ -891,7 +891,7 @@ static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
891}; 891};
892 892
893/* EPLL */ 893/* EPLL */
894static struct samsung_pll_rate_table exynos4415_epll_rates[] = { 894static const struct samsung_pll_rate_table exynos4415_epll_rates[] __initconst = {
895 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 895 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
896 PLL_36XX_RATE(288000000, 96, 2, 2, 0), 896 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
897 PLL_36XX_RATE(192000000, 128, 2, 3, 0), 897 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
@@ -909,7 +909,7 @@ static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
909 { /* sentinel */ } 909 { /* sentinel */ }
910}; 910};
911 911
912static struct samsung_pll_clock exynos4415_plls[] __initdata = { 912static const struct samsung_pll_clock exynos4415_plls[] __initconst = {
913 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 913 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
914 APLL_LOCK, APLL_CON0, exynos4415_pll_rates), 914 APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
915 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 915 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
@@ -922,7 +922,7 @@ static struct samsung_pll_clock exynos4415_plls[] __initdata = {
922 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates), 922 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
923}; 923};
924 924
925static struct samsung_cmu_info cmu_info __initdata = { 925static const struct samsung_cmu_info cmu_info __initconst = {
926 .pll_clks = exynos4415_plls, 926 .pll_clks = exynos4415_plls,
927 .nr_pll_clks = ARRAY_SIZE(exynos4415_plls), 927 .nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
928 .mux_clks = exynos4415_mux_clks, 928 .mux_clks = exynos4415_mux_clks,
@@ -961,7 +961,7 @@ CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
961#define SRC_DMC 0x300 961#define SRC_DMC 0x300
962#define DIV_DMC1 0x504 962#define DIV_DMC1 0x504
963 963
964static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = { 964static const unsigned long exynos4415_cmu_dmc_clk_regs[] __initconst = {
965 MPLL_LOCK, 965 MPLL_LOCK,
966 MPLL_CON0, 966 MPLL_CON0,
967 MPLL_CON1, 967 MPLL_CON1,
@@ -978,14 +978,14 @@ PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
978PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 978PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
979PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", }; 979PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
980 980
981static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = { 981static const struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initconst = {
982 MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1), 982 MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
983 MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1), 983 MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
984 MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1), 984 MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
985 MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1), 985 MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
986}; 986};
987 987
988static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = { 988static const struct samsung_div_clock exynos4415_dmc_div_clks[] __initconst = {
989 DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3), 989 DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
990 DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3), 990 DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
991 DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", 991 DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
@@ -995,14 +995,14 @@ static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
995 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2), 995 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
996}; 996};
997 997
998static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = { 998static const struct samsung_pll_clock exynos4415_dmc_plls[] __initconst = {
999 PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll", 999 PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1000 MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates), 1000 MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
1001 PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll", 1001 PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1002 BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates), 1002 BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
1003}; 1003};
1004 1004
1005static struct samsung_cmu_info cmu_dmc_info __initdata = { 1005static const struct samsung_cmu_info cmu_dmc_info __initconst = {
1006 .pll_clks = exynos4415_dmc_plls, 1006 .pll_clks = exynos4415_dmc_plls,
1007 .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls), 1007 .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
1008 .mux_clks = exynos4415_dmc_mux_clks, 1008 .mux_clks = exynos4415_dmc_mux_clks,
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 837197db4ffb..27a227d6620c 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -117,7 +117,7 @@ static struct samsung_clk_reg_dump *exynos5250_save;
117 * list of controller registers to be saved and restored during a 117 * list of controller registers to be saved and restored during a
118 * suspend/resume cycle. 118 * suspend/resume cycle.
119 */ 119 */
120static unsigned long exynos5250_clk_regs[] __initdata = { 120static const unsigned long exynos5250_clk_regs[] __initconst = {
121 SRC_CPU, 121 SRC_CPU,
122 DIV_CPU0, 122 DIV_CPU0,
123 PWR_CTRL1, 123 PWR_CTRL1,
@@ -190,7 +190,7 @@ static struct syscore_ops exynos5250_clk_syscore_ops = {
190 .resume = exynos5250_clk_resume, 190 .resume = exynos5250_clk_resume,
191}; 191};
192 192
193static void exynos5250_clk_sleep_init(void) 193static void __init exynos5250_clk_sleep_init(void)
194{ 194{
195 exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs, 195 exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
196 ARRAY_SIZE(exynos5250_clk_regs)); 196 ARRAY_SIZE(exynos5250_clk_regs));
@@ -203,7 +203,7 @@ static void exynos5250_clk_sleep_init(void)
203 register_syscore_ops(&exynos5250_clk_syscore_ops); 203 register_syscore_ops(&exynos5250_clk_syscore_ops);
204} 204}
205#else 205#else
206static void exynos5250_clk_sleep_init(void) {} 206static void __init exynos5250_clk_sleep_init(void) {}
207#endif 207#endif
208 208
209/* list of all parent clock list */ 209/* list of all parent clock list */
@@ -266,23 +266,23 @@ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initda
266}; 266};
267 267
268/* fixed rate clocks generated inside the soc */ 268/* fixed rate clocks generated inside the soc */
269static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 269static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
270 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 270 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
271 FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000), 271 FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
272 FRATE(0, "sclk_dptxphy", NULL, 0, 24000000), 272 FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
273 FRATE(0, "sclk_uhostphy", NULL, 0, 48000000), 273 FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
274}; 274};
275 275
276static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 276static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
277 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 277 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
278 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 278 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
279}; 279};
280 280
281static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 281static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
282 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 282 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
283}; 283};
284 284
285static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 285static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
286 /* 286 /*
287 * NOTE: Following table is sorted by (clock domain, register address, 287 * NOTE: Following table is sorted by (clock domain, register address,
288 * bitfield shift) triplet in ascending order. When adding new entries, 288 * bitfield shift) triplet in ascending order. When adding new entries,
@@ -378,7 +378,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
378 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 378 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
379}; 379};
380 380
381static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 381static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
382 /* 382 /*
383 * NOTE: Following table is sorted by (clock domain, register address, 383 * NOTE: Following table is sorted by (clock domain, register address,
384 * bitfield shift) triplet in ascending order. When adding new entries, 384 * bitfield shift) triplet in ascending order. When adding new entries,
@@ -470,7 +470,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
470 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 470 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
471}; 471};
472 472
473static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 473static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
474 /* 474 /*
475 * NOTE: Following table is sorted by (clock domain, register address, 475 * NOTE: Following table is sorted by (clock domain, register address,
476 * bitfield shift) triplet in ascending order. When adding new entries, 476 * bitfield shift) triplet in ascending order. When adding new entries,
@@ -698,7 +698,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
698 GATE_IP_ISP1, 7, 0, 0), 698 GATE_IP_ISP1, 7, 0, 0),
699}; 699};
700 700
701static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 701static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
702 /* sorted in descending order */ 702 /* sorted in descending order */
703 /* PLL_36XX_RATE(rate, m, p, s, k) */ 703 /* PLL_36XX_RATE(rate, m, p, s, k) */
704 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 704 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
@@ -707,7 +707,7 @@ static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
707 { }, 707 { },
708}; 708};
709 709
710static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { 710static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
711 /* sorted in descending order */ 711 /* sorted in descending order */
712 /* PLL_36XX_RATE(rate, m, p, s, k) */ 712 /* PLL_36XX_RATE(rate, m, p, s, k) */
713 PLL_36XX_RATE(192000000, 64, 2, 2, 0), 713 PLL_36XX_RATE(192000000, 64, 2, 2, 0),
@@ -721,7 +721,7 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
721 { }, 721 { },
722}; 722};
723 723
724static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { 724static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
725 /* sorted in descending order */ 725 /* sorted in descending order */
726 /* PLL_35XX_RATE(rate, m, p, s) */ 726 /* PLL_35XX_RATE(rate, m, p, s) */
727 PLL_35XX_RATE(1700000000, 425, 6, 0), 727 PLL_35XX_RATE(1700000000, 425, 6, 0),
@@ -805,8 +805,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
805 } 805 }
806 806
807 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 807 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
808 if (!ctx) 808
809 panic("%s: unable to allocate context.\n", __func__);
810 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, 809 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
811 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 810 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
812 ext_clk_match); 811 ext_clk_match);
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index 7a7ed075a573..a43642c36039 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -22,7 +22,7 @@
22 * Applicable for all 2550 Type PLLS for Exynos5260, listed below 22 * Applicable for all 2550 Type PLLS for Exynos5260, listed below
23 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. 23 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
24 */ 24 */
25static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = { 25static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
26 PLL_35XX_RATE(1700000000, 425, 6, 0), 26 PLL_35XX_RATE(1700000000, 425, 6, 0),
27 PLL_35XX_RATE(1600000000, 200, 3, 0), 27 PLL_35XX_RATE(1600000000, 200, 3, 0),
28 PLL_35XX_RATE(1500000000, 250, 4, 0), 28 PLL_35XX_RATE(1500000000, 250, 4, 0),
@@ -55,7 +55,7 @@ static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = {
55/* 55/*
56 * Applicable for 2650 Type PLL for AUD_PLL. 56 * Applicable for 2650 Type PLL for AUD_PLL.
57 */ 57 */
58static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = { 58static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
59 PLL_36XX_RATE(1600000000, 200, 3, 0, 0), 59 PLL_36XX_RATE(1600000000, 200, 3, 0, 0),
60 PLL_36XX_RATE(1200000000, 100, 2, 0, 0), 60 PLL_36XX_RATE(1200000000, 100, 2, 0, 0),
61 PLL_36XX_RATE(1000000000, 250, 3, 1, 0), 61 PLL_36XX_RATE(1000000000, 250, 3, 1, 0),
@@ -78,7 +78,7 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
78 78
79/* CMU_AUD */ 79/* CMU_AUD */
80 80
81static unsigned long aud_clk_regs[] __initdata = { 81static const unsigned long aud_clk_regs[] __initconst = {
82 MUX_SEL_AUD, 82 MUX_SEL_AUD,
83 DIV_AUD0, 83 DIV_AUD0,
84 DIV_AUD1, 84 DIV_AUD1,
@@ -92,7 +92,7 @@ PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
92PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"}; 92PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
93PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"}; 93PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
94 94
95static struct samsung_mux_clock aud_mux_clks[] __initdata = { 95static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
96 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p, 96 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
97 MUX_SEL_AUD, 0, 1), 97 MUX_SEL_AUD, 0, 1),
98 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, 98 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
@@ -101,7 +101,7 @@ static struct samsung_mux_clock aud_mux_clks[] __initdata = {
101 MUX_SEL_AUD, 8, 1), 101 MUX_SEL_AUD, 8, 1),
102}; 102};
103 103
104static struct samsung_div_clock aud_div_clks[] __initdata = { 104static const struct samsung_div_clock aud_div_clks[] __initconst = {
105 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user", 105 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
106 DIV_AUD0, 0, 4), 106 DIV_AUD0, 0, 4),
107 107
@@ -113,7 +113,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = {
113 DIV_AUD1, 12, 4), 113 DIV_AUD1, 12, 4),
114}; 114};
115 115
116static struct samsung_gate_clock aud_gate_clks[] __initdata = { 116static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
117 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", 117 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
118 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0), 118 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
119 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", 119 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
@@ -154,7 +154,7 @@ CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
154 154
155/* CMU_DISP */ 155/* CMU_DISP */
156 156
157static unsigned long disp_clk_regs[] __initdata = { 157static const unsigned long disp_clk_regs[] __initconst = {
158 MUX_SEL_DISP0, 158 MUX_SEL_DISP0,
159 MUX_SEL_DISP1, 159 MUX_SEL_DISP1,
160 MUX_SEL_DISP2, 160 MUX_SEL_DISP2,
@@ -201,7 +201,7 @@ PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
201PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", 201PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
202 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 202 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
203 203
204static struct samsung_mux_clock disp_mux_clks[] __initdata = { 204static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
205 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 205 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
206 mout_aclk_disp_333_user_p, 206 mout_aclk_disp_333_user_p,
207 MUX_SEL_DISP0, 0, 1), 207 MUX_SEL_DISP0, 0, 1),
@@ -270,7 +270,7 @@ static struct samsung_mux_clock disp_mux_clks[] __initdata = {
270 MUX_SEL_DISP4, 4, 2), 270 MUX_SEL_DISP4, 4, 2),
271}; 271};
272 272
273static struct samsung_div_clock disp_div_clks[] __initdata = { 273static const struct samsung_div_clock disp_div_clks[] __initconst = {
274 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111", 274 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
275 "mout_aclk_disp_222_user", 275 "mout_aclk_disp_222_user",
276 DIV_DISP, 8, 4), 276 DIV_DISP, 8, 4),
@@ -283,7 +283,7 @@ static struct samsung_div_clock disp_div_clks[] __initdata = {
283 DIV_DISP, 16, 4), 283 DIV_DISP, 16, 4),
284}; 284};
285 285
286static struct samsung_gate_clock disp_gate_clks[] __initdata = { 286static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
287 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel", 287 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
288 "mout_phyclk_hdmi_phy_pixel_clko_user", 288 "mout_phyclk_hdmi_phy_pixel_clko_user",
289 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0), 289 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
@@ -344,7 +344,7 @@ CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
344 344
345/* CMU_EGL */ 345/* CMU_EGL */
346 346
347static unsigned long egl_clk_regs[] __initdata = { 347static const unsigned long egl_clk_regs[] __initconst = {
348 EGL_PLL_LOCK, 348 EGL_PLL_LOCK,
349 EGL_PLL_CON0, 349 EGL_PLL_CON0,
350 EGL_PLL_CON1, 350 EGL_PLL_CON1,
@@ -361,13 +361,13 @@ static unsigned long egl_clk_regs[] __initdata = {
361PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; 361PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
362PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; 362PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
363 363
364static struct samsung_mux_clock egl_mux_clks[] __initdata = { 364static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
365 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p, 365 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
366 MUX_SEL_EGL, 4, 1), 366 MUX_SEL_EGL, 4, 1),
367 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), 367 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
368}; 368};
369 369
370static struct samsung_div_clock egl_div_clks[] __initdata = { 370static const struct samsung_div_clock egl_div_clks[] __initconst = {
371 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), 371 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
372 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), 372 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
373 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), 373 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
@@ -379,7 +379,7 @@ static struct samsung_div_clock egl_div_clks[] __initdata = {
379 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), 379 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
380}; 380};
381 381
382static struct samsung_pll_clock egl_pll_clks[] __initdata = { 382static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
383 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", 383 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
384 EGL_PLL_LOCK, EGL_PLL_CON0, 384 EGL_PLL_LOCK, EGL_PLL_CON0,
385 pll2550_24mhz_tbl), 385 pll2550_24mhz_tbl),
@@ -408,7 +408,7 @@ CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
408 408
409/* CMU_FSYS */ 409/* CMU_FSYS */
410 410
411static unsigned long fsys_clk_regs[] __initdata = { 411static const unsigned long fsys_clk_regs[] __initconst = {
412 MUX_SEL_FSYS0, 412 MUX_SEL_FSYS0,
413 MUX_SEL_FSYS1, 413 MUX_SEL_FSYS1,
414 EN_ACLK_FSYS, 414 EN_ACLK_FSYS,
@@ -431,7 +431,7 @@ PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
431PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", 431PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
432 "phyclk_usbdrd30_udrd30_phyclock"}; 432 "phyclk_usbdrd30_udrd30_phyclock"};
433 433
434static struct samsung_mux_clock fsys_mux_clks[] __initdata = { 434static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
435 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER, 435 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
436 "mout_phyclk_usbdrd30_phyclock_user", 436 "mout_phyclk_usbdrd30_phyclock_user",
437 mout_phyclk_usbdrd30_phyclock_user_p, 437 mout_phyclk_usbdrd30_phyclock_user_p,
@@ -454,7 +454,7 @@ static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
454 MUX_SEL_FSYS1, 16, 1), 454 MUX_SEL_FSYS1, 16, 1),
455}; 455};
456 456
457static struct samsung_gate_clock fsys_gate_clks[] __initdata = { 457static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
458 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", 458 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
459 "mout_phyclk_usbdrd30_phyclock_user", 459 "mout_phyclk_usbdrd30_phyclock_user",
460 EN_SCLK_FSYS, 1, 0, 0), 460 EN_SCLK_FSYS, 1, 0, 0),
@@ -508,7 +508,7 @@ CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
508 508
509/* CMU_G2D */ 509/* CMU_G2D */
510 510
511static unsigned long g2d_clk_regs[] __initdata = { 511static const unsigned long g2d_clk_regs[] __initconst = {
512 MUX_SEL_G2D, 512 MUX_SEL_G2D,
513 MUX_STAT_G2D, 513 MUX_STAT_G2D,
514 DIV_G2D, 514 DIV_G2D,
@@ -535,18 +535,18 @@ static unsigned long g2d_clk_regs[] __initdata = {
535 535
536PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; 536PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
537 537
538static struct samsung_mux_clock g2d_mux_clks[] __initdata = { 538static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
539 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user", 539 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
540 mout_aclk_g2d_333_user_p, 540 mout_aclk_g2d_333_user_p,
541 MUX_SEL_G2D, 0, 1), 541 MUX_SEL_G2D, 0, 1),
542}; 542};
543 543
544static struct samsung_div_clock g2d_div_clks[] __initdata = { 544static const struct samsung_div_clock g2d_div_clks[] __initconst = {
545 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", 545 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
546 DIV_G2D, 0, 3), 546 DIV_G2D, 0, 3),
547}; 547};
548 548
549static struct samsung_gate_clock g2d_gate_clks[] __initdata = { 549static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
550 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", 550 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
551 EN_IP_G2D, 4, 0, 0), 551 EN_IP_G2D, 4, 0, 0),
552 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", 552 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
@@ -599,7 +599,7 @@ CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
599 599
600/* CMU_G3D */ 600/* CMU_G3D */
601 601
602static unsigned long g3d_clk_regs[] __initdata = { 602static const unsigned long g3d_clk_regs[] __initconst = {
603 G3D_PLL_LOCK, 603 G3D_PLL_LOCK,
604 G3D_PLL_CON0, 604 G3D_PLL_CON0,
605 G3D_PLL_CON1, 605 G3D_PLL_CON1,
@@ -615,23 +615,23 @@ static unsigned long g3d_clk_regs[] __initdata = {
615 615
616PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; 616PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
617 617
618static struct samsung_mux_clock g3d_mux_clks[] __initdata = { 618static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
619 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 619 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
620 MUX_SEL_G3D, 0, 1), 620 MUX_SEL_G3D, 0, 1),
621}; 621};
622 622
623static struct samsung_div_clock g3d_div_clks[] __initdata = { 623static const struct samsung_div_clock g3d_div_clks[] __initconst = {
624 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), 624 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
625 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), 625 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
626}; 626};
627 627
628static struct samsung_gate_clock g3d_gate_clks[] __initdata = { 628static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
629 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), 629 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
630 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", 630 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
631 EN_IP_G3D, 3, 0, 0), 631 EN_IP_G3D, 3, 0, 0),
632}; 632};
633 633
634static struct samsung_pll_clock g3d_pll_clks[] __initdata = { 634static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
635 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", 635 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
636 G3D_PLL_LOCK, G3D_PLL_CON0, 636 G3D_PLL_LOCK, G3D_PLL_CON0,
637 pll2550_24mhz_tbl), 637 pll2550_24mhz_tbl),
@@ -662,7 +662,7 @@ CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
662 662
663/* CMU_GSCL */ 663/* CMU_GSCL */
664 664
665static unsigned long gscl_clk_regs[] __initdata = { 665static const unsigned long gscl_clk_regs[] __initconst = {
666 MUX_SEL_GSCL, 666 MUX_SEL_GSCL,
667 DIV_GSCL, 667 DIV_GSCL,
668 EN_ACLK_GSCL, 668 EN_ACLK_GSCL,
@@ -692,7 +692,7 @@ PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
692PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 692PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
693PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; 693PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
694 694
695static struct samsung_mux_clock gscl_mux_clks[] __initdata = { 695static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
696 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 696 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
697 mout_aclk_gscl_333_user_p, 697 mout_aclk_gscl_333_user_p,
698 MUX_SEL_GSCL, 0, 1), 698 MUX_SEL_GSCL, 0, 1),
@@ -706,7 +706,7 @@ static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
706 MUX_SEL_GSCL, 24, 1), 706 MUX_SEL_GSCL, 24, 1),
707}; 707};
708 708
709static struct samsung_div_clock gscl_div_clks[] __initdata = { 709static const struct samsung_div_clock gscl_div_clks[] __initconst = {
710 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100", 710 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
711 "mout_aclk_m2m_400_user", 711 "mout_aclk_m2m_400_user",
712 DIV_GSCL, 0, 3), 712 DIV_GSCL, 0, 3),
@@ -715,7 +715,7 @@ static struct samsung_div_clock gscl_div_clks[] __initdata = {
715 DIV_GSCL, 4, 3), 715 DIV_GSCL, 4, 3),
716}; 716};
717 717
718static struct samsung_gate_clock gscl_gate_clks[] __initdata = { 718static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
719 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", 719 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
720 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0), 720 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
721 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", 721 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
@@ -795,7 +795,7 @@ CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
795 795
796/* CMU_ISP */ 796/* CMU_ISP */
797 797
798static unsigned long isp_clk_regs[] __initdata = { 798static const unsigned long isp_clk_regs[] __initconst = {
799 MUX_SEL_ISP0, 799 MUX_SEL_ISP0,
800 MUX_SEL_ISP1, 800 MUX_SEL_ISP1,
801 DIV_ISP, 801 DIV_ISP,
@@ -811,14 +811,14 @@ static unsigned long isp_clk_regs[] __initdata = {
811PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; 811PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
812PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; 812PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
813 813
814static struct samsung_mux_clock isp_mux_clks[] __initdata = { 814static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
815 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p, 815 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
816 MUX_SEL_ISP0, 0, 1), 816 MUX_SEL_ISP0, 0, 1),
817 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p, 817 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
818 MUX_SEL_ISP0, 4, 1), 818 MUX_SEL_ISP0, 4, 1),
819}; 819};
820 820
821static struct samsung_div_clock isp_div_clks[] __initdata = { 821static const struct samsung_div_clock isp_div_clks[] __initconst = {
822 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc", 822 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
823 DIV_ISP, 0, 3), 823 DIV_ISP, 0, 3),
824 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc", 824 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
@@ -830,7 +830,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = {
830 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), 830 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
831}; 831};
832 832
833static struct samsung_gate_clock isp_gate_clks[] __initdata = { 833static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
834 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", 834 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
835 EN_IP_ISP0, 15, 0, 0), 835 EN_IP_ISP0, 15, 0, 0),
836 836
@@ -914,7 +914,7 @@ CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
914 914
915/* CMU_KFC */ 915/* CMU_KFC */
916 916
917static unsigned long kfc_clk_regs[] __initdata = { 917static const unsigned long kfc_clk_regs[] __initconst = {
918 KFC_PLL_LOCK, 918 KFC_PLL_LOCK,
919 KFC_PLL_CON0, 919 KFC_PLL_CON0,
920 KFC_PLL_CON1, 920 KFC_PLL_CON1,
@@ -932,13 +932,13 @@ static unsigned long kfc_clk_regs[] __initdata = {
932PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; 932PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
933PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; 933PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
934 934
935static struct samsung_mux_clock kfc_mux_clks[] __initdata = { 935static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
936 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p, 936 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
937 MUX_SEL_KFC0, 0, 1), 937 MUX_SEL_KFC0, 0, 1),
938 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), 938 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
939}; 939};
940 940
941static struct samsung_div_clock kfc_div_clks[] __initdata = { 941static const struct samsung_div_clock kfc_div_clks[] __initconst = {
942 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), 942 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
943 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), 943 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
944 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), 944 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
@@ -949,7 +949,7 @@ static struct samsung_div_clock kfc_div_clks[] __initdata = {
949 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), 949 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
950}; 950};
951 951
952static struct samsung_pll_clock kfc_pll_clks[] __initdata = { 952static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
953 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", 953 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
954 KFC_PLL_LOCK, KFC_PLL_CON0, 954 KFC_PLL_LOCK, KFC_PLL_CON0,
955 pll2550_24mhz_tbl), 955 pll2550_24mhz_tbl),
@@ -978,7 +978,7 @@ CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
978 978
979/* CMU_MFC */ 979/* CMU_MFC */
980 980
981static unsigned long mfc_clk_regs[] __initdata = { 981static const unsigned long mfc_clk_regs[] __initconst = {
982 MUX_SEL_MFC, 982 MUX_SEL_MFC,
983 DIV_MFC, 983 DIV_MFC,
984 EN_ACLK_MFC, 984 EN_ACLK_MFC,
@@ -991,18 +991,18 @@ static unsigned long mfc_clk_regs[] __initdata = {
991 991
992PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; 992PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
993 993
994static struct samsung_mux_clock mfc_mux_clks[] __initdata = { 994static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
995 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user", 995 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
996 mout_aclk_mfc_333_user_p, 996 mout_aclk_mfc_333_user_p,
997 MUX_SEL_MFC, 0, 1), 997 MUX_SEL_MFC, 0, 1),
998}; 998};
999 999
1000static struct samsung_div_clock mfc_div_clks[] __initdata = { 1000static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1001 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", 1001 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
1002 DIV_MFC, 0, 3), 1002 DIV_MFC, 0, 3),
1003}; 1003};
1004 1004
1005static struct samsung_gate_clock mfc_gate_clks[] __initdata = { 1005static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
1006 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", 1006 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
1007 EN_IP_MFC, 1, 0, 0), 1007 EN_IP_MFC, 1, 0, 0),
1008 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", 1008 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
@@ -1034,7 +1034,7 @@ CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
1034 1034
1035/* CMU_MIF */ 1035/* CMU_MIF */
1036 1036
1037static unsigned long mif_clk_regs[] __initdata = { 1037static const unsigned long mif_clk_regs[] __initconst = {
1038 MEM_PLL_LOCK, 1038 MEM_PLL_LOCK,
1039 BUS_PLL_LOCK, 1039 BUS_PLL_LOCK,
1040 MEDIA_PLL_LOCK, 1040 MEDIA_PLL_LOCK,
@@ -1076,7 +1076,7 @@ PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
1076PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; 1076PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
1077PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; 1077PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
1078 1078
1079static struct samsung_mux_clock mif_mux_clks[] __initdata = { 1079static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1080 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p, 1080 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
1081 MUX_SEL_MIF, 0, 1), 1081 MUX_SEL_MIF, 0, 1),
1082 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, 1082 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
@@ -1093,7 +1093,7 @@ static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1093 MUX_SEL_MIF, 24, 1), 1093 MUX_SEL_MIF, 24, 1),
1094}; 1094};
1095 1095
1096static struct samsung_div_clock mif_div_clks[] __initdata = { 1096static const struct samsung_div_clock mif_div_clks[] __initconst = {
1097 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll", 1097 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
1098 DIV_MIF, 0, 3), 1098 DIV_MIF, 0, 3),
1099 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll", 1099 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
@@ -1112,7 +1112,7 @@ static struct samsung_div_clock mif_div_clks[] __initdata = {
1112 DIV_MIF, 28, 4), 1112 DIV_MIF, 28, 4),
1113}; 1113};
1114 1114
1115static struct samsung_gate_clock mif_gate_clks[] __initdata = { 1115static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1116 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", 1116 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
1117 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), 1117 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
1118 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", 1118 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
@@ -1146,7 +1146,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1146 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1146 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1147}; 1147};
1148 1148
1149static struct samsung_pll_clock mif_pll_clks[] __initdata = { 1149static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1150 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", 1150 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1151 MEM_PLL_LOCK, MEM_PLL_CON0, 1151 MEM_PLL_LOCK, MEM_PLL_CON0,
1152 pll2550_24mhz_tbl), 1152 pll2550_24mhz_tbl),
@@ -1183,7 +1183,7 @@ CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
1183 1183
1184/* CMU_PERI */ 1184/* CMU_PERI */
1185 1185
1186static unsigned long peri_clk_regs[] __initdata = { 1186static const unsigned long peri_clk_regs[] __initconst = {
1187 MUX_SEL_PERI, 1187 MUX_SEL_PERI,
1188 MUX_SEL_PERI1, 1188 MUX_SEL_PERI1,
1189 DIV_PERI, 1189 DIV_PERI,
@@ -1219,7 +1219,7 @@ PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
1219PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll", 1219PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
1220 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 1220 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
1221 1221
1222static struct samsung_mux_clock peri_mux_clks[] __initdata = { 1222static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1223 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p, 1223 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
1224 MUX_SEL_PERI1, 4, 2), 1224 MUX_SEL_PERI1, 4, 2),
1225 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p, 1225 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
@@ -1228,12 +1228,12 @@ static struct samsung_mux_clock peri_mux_clks[] __initdata = {
1228 MUX_SEL_PERI1, 20, 2), 1228 MUX_SEL_PERI1, 20, 2),
1229}; 1229};
1230 1230
1231static struct samsung_div_clock peri_div_clks[] __initdata = { 1231static const struct samsung_div_clock peri_div_clks[] __initconst = {
1232 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), 1232 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
1233 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6), 1233 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
1234}; 1234};
1235 1235
1236static struct samsung_gate_clock peri_gate_clks[] __initdata = { 1236static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
1237 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, 1237 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
1238 CLK_SET_RATE_PARENT, 0), 1238 CLK_SET_RATE_PARENT, 0),
1239 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, 1239 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
@@ -1389,7 +1389,7 @@ CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
1389 1389
1390/* CMU_TOP */ 1390/* CMU_TOP */
1391 1391
1392static unsigned long top_clk_regs[] __initdata = { 1392static const unsigned long top_clk_regs[] __initconst = {
1393 DISP_PLL_LOCK, 1393 DISP_PLL_LOCK,
1394 AUD_PLL_LOCK, 1394 AUD_PLL_LOCK,
1395 DISP_PLL_CON0, 1395 DISP_PLL_CON0,
@@ -1430,7 +1430,7 @@ static unsigned long top_clk_regs[] __initdata = {
1430}; 1430};
1431 1431
1432/* fixed rate clocks generated inside the soc */ 1432/* fixed rate clocks generated inside the soc */
1433static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = { 1433static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
1434 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, 1434 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
1435 0, 270000000), 1435 0, 270000000),
1436 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, 1436 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
@@ -1513,7 +1513,7 @@ PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
1513PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", 1513PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
1514 "mout_mediatop_pll_user"}; 1514 "mout_mediatop_pll_user"};
1515 1515
1516static struct samsung_mux_clock top_mux_clks[] __initdata = { 1516static const struct samsung_mux_clock top_mux_clks[] __initconst = {
1517 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user", 1517 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
1518 mout_mediatop_pll_user_p, 1518 mout_mediatop_pll_user_p,
1519 MUX_SEL_TOP_PLL0, 0, 1), 1519 MUX_SEL_TOP_PLL0, 0, 1),
@@ -1673,7 +1673,7 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
1673 MUX_SEL_TOP_GSCL, 20, 1), 1673 MUX_SEL_TOP_GSCL, 20, 1),
1674}; 1674};
1675 1675
1676static struct samsung_div_clock top_div_clks[] __initdata = { 1676static const struct samsung_div_clock top_div_clks[] __initconst = {
1677 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333", 1677 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
1678 DIV_TOP_G2D_MFC, 0, 3), 1678 DIV_TOP_G2D_MFC, 0, 3),
1679 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333", 1679 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
@@ -1794,7 +1794,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
1794 1794
1795}; 1795};
1796 1796
1797static struct samsung_gate_clock top_gate_clks[] __initdata = { 1797static const struct samsung_gate_clock top_gate_clks[] __initconst = {
1798 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", 1798 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
1799 "dout_sclk_fsys_mmc0_sdclkin_b", 1799 "dout_sclk_fsys_mmc0_sdclkin_b",
1800 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), 1800 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
@@ -1809,7 +1809,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
1809 CLK_SET_RATE_PARENT, 0), 1809 CLK_SET_RATE_PARENT, 0),
1810}; 1810};
1811 1811
1812static struct samsung_pll_clock top_pll_clks[] __initdata = { 1812static const struct samsung_pll_clock top_pll_clks[] __initconst = {
1813 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", 1813 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1814 DISP_PLL_LOCK, DISP_PLL_CON0, 1814 DISP_PLL_LOCK, DISP_PLL_CON0,
1815 pll2550_24mhz_tbl), 1815 pll2550_24mhz_tbl),
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d5d5dcabc4a9..54ec486a5e45 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -31,11 +31,14 @@
31#define SRC_CPU 0x200 31#define SRC_CPU 0x200
32#define DIV_CPU0 0x500 32#define DIV_CPU0 0x500
33#define SRC_CPERI1 0x4204 33#define SRC_CPERI1 0x4204
34#define GATE_IP_G2D 0x8800
34#define DIV_TOP0 0x10510 35#define DIV_TOP0 0x10510
35#define DIV_TOP1 0x10514 36#define DIV_TOP1 0x10514
37#define DIV_FSYS0 0x10548
36#define DIV_FSYS1 0x1054c 38#define DIV_FSYS1 0x1054c
37#define DIV_FSYS2 0x10550 39#define DIV_FSYS2 0x10550
38#define DIV_PERIC0 0x10558 40#define DIV_PERIC0 0x10558
41#define DIV_PERIC3 0x10564
39#define SRC_TOP0 0x10210 42#define SRC_TOP0 0x10210
40#define SRC_TOP1 0x10214 43#define SRC_TOP1 0x10214
41#define SRC_TOP2 0x10218 44#define SRC_TOP2 0x10218
@@ -44,6 +47,8 @@
44#define SRC_MASK_FSYS 0x10340 47#define SRC_MASK_FSYS 0x10340
45#define SRC_MASK_PERIC0 0x10350 48#define SRC_MASK_PERIC0 0x10350
46#define GATE_BUS_FSYS0 0x10740 49#define GATE_BUS_FSYS0 0x10740
50#define GATE_TOP_SCLK_FSYS 0x10840
51#define GATE_TOP_SCLK_PERIC 0x10850
47#define GATE_IP_FSYS 0x10944 52#define GATE_IP_FSYS 0x10944
48#define GATE_IP_PERIC 0x10950 53#define GATE_IP_PERIC 0x10950
49#define GATE_IP_PERIS 0x10960 54#define GATE_IP_PERIS 0x10960
@@ -71,12 +76,13 @@ PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
71PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", }; 76PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
72PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", }; 77PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
73PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", }; 78PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
79PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
74 80
75PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none", 81PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
76 "none", "none", "sclk_mpll_bpll", 82 "none", "none", "sclk_mpll_bpll",
77 "none", "none", "sclk_cpll" }; 83 "none", "none", "sclk_cpll" };
78 84
79static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = { 85static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = {
80 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 86 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
81 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 87 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
82 88
@@ -96,16 +102,20 @@ static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
96 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4), 102 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
97 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4), 103 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
98 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4), 104 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
105 MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
106 MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
99 107
100 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4), 108 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
101 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4), 109 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
102 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4), 110 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
111 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
112 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
103 113
104 MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1), 114 MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
105 MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1), 115 MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
106}; 116};
107 117
108static struct samsung_div_clock exynos5410_div_clks[] __initdata = { 118static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
109 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 119 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
110 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3), 120 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
111 121
@@ -121,6 +131,11 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
121 DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3), 131 DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
122 DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), 132 DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
123 133
134 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
135 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
136 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
137 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
138
124 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 139 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
125 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 140 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
126 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 141 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
@@ -137,12 +152,19 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
137 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 152 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
138 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 153 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
139 154
155 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
156
140 DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 157 DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
158 DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
141 DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3), 159 DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
142}; 160};
143 161
144static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = { 162static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
163 GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
145 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), 164 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
165 GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
166 GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
167 GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
146 168
147 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", 169 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
148 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 170 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
@@ -155,9 +177,31 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
155 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0), 177 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
156 GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0), 178 GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
157 179
180 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
181 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
182 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
183 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
184 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
185 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
186 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
187 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
188
189 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
190 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
191
158 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0), 192 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
159 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), 193 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
160 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), 194 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
195 GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
196 GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
197 GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
198 GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
199 GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
200 GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
201 GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
202 GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
203 GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
204 GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
161 205
162 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 206 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
163 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 207 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
@@ -165,9 +209,15 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
165 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 209 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
166 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", 210 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
167 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 211 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
212 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
213 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
214
215 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
216 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
217 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
168}; 218};
169 219
170static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = { 220static const struct samsung_pll_clock exynos5410_plls[nr_plls] __initconst = {
171 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 221 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
172 APLL_CON0, NULL), 222 APLL_CON0, NULL),
173 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 223 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 92382cef9f90..bb196ca21a77 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -160,7 +160,7 @@ static struct samsung_clk_reg_dump *exynos5800_save;
160 * list of controller registers to be saved and restored during a 160 * list of controller registers to be saved and restored during a
161 * suspend/resume cycle. 161 * suspend/resume cycle.
162 */ 162 */
163static unsigned long exynos5x_clk_regs[] __initdata = { 163static const unsigned long exynos5x_clk_regs[] __initconst = {
164 SRC_CPU, 164 SRC_CPU,
165 DIV_CPU0, 165 DIV_CPU0,
166 DIV_CPU1, 166 DIV_CPU1,
@@ -248,7 +248,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
248 DIV_KFC0, 248 DIV_KFC0,
249}; 249};
250 250
251static unsigned long exynos5800_clk_regs[] __initdata = { 251static const unsigned long exynos5800_clk_regs[] __initconst = {
252 SRC_TOP8, 252 SRC_TOP8,
253 SRC_TOP9, 253 SRC_TOP9,
254 SRC_CAM, 254 SRC_CAM,
@@ -306,7 +306,7 @@ static struct syscore_ops exynos5420_clk_syscore_ops = {
306 .resume = exynos5420_clk_resume, 306 .resume = exynos5420_clk_resume,
307}; 307};
308 308
309static void exynos5420_clk_sleep_init(void) 309static void __init exynos5420_clk_sleep_init(void)
310{ 310{
311 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 311 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
312 ARRAY_SIZE(exynos5x_clk_regs)); 312 ARRAY_SIZE(exynos5x_clk_regs));
@@ -333,7 +333,7 @@ err_soc:
333 return; 333 return;
334} 334}
335#else 335#else
336static void exynos5420_clk_sleep_init(void) {} 336static void __init exynos5420_clk_sleep_init(void) {}
337#endif 337#endif
338 338
339/* list of all parent clocks */ 339/* list of all parent clocks */
@@ -484,7 +484,7 @@ static struct samsung_fixed_rate_clock
484}; 484};
485 485
486/* fixed rate clocks generated inside the soc */ 486/* fixed rate clocks generated inside the soc */
487static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { 487static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
488 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 488 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
489 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 489 FRATE(0, "sclk_pwi", NULL, 0, 24000000),
490 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 490 FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
@@ -492,19 +492,19 @@ static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
492 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 492 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
493}; 493};
494 494
495static struct samsung_fixed_factor_clock 495static const struct samsung_fixed_factor_clock
496 exynos5x_fixed_factor_clks[] __initdata = { 496 exynos5x_fixed_factor_clks[] __initconst = {
497 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 497 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
498 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 498 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
499}; 499};
500 500
501static struct samsung_fixed_factor_clock 501static const struct samsung_fixed_factor_clock
502 exynos5800_fixed_factor_clks[] __initdata = { 502 exynos5800_fixed_factor_clks[] __initconst = {
503 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 503 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
504 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 504 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
505}; 505};
506 506
507static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { 507static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
508 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 508 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
509 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 509 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
510 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 510 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
@@ -553,7 +553,7 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
553 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 553 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
554}; 554};
555 555
556static struct samsung_div_clock exynos5800_div_clks[] __initdata = { 556static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
557 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 557 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
558 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 558 "mout_aclk400_wcore", DIV_TOP0, 16, 3),
559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
@@ -569,14 +569,14 @@ static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
569 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 569 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
570}; 570};
571 571
572static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { 572static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
573 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 573 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
574 GATE_BUS_TOP, 24, 0, 0), 574 GATE_BUS_TOP, 24, 0, 0),
575 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 575 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
576 GATE_BUS_TOP, 27, 0, 0), 576 GATE_BUS_TOP, 27, 0, 0),
577}; 577};
578 578
579static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 579static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
580 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 580 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
581 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 581 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
582 TOP_SPARE2, 4, 1), 582 TOP_SPARE2, 4, 1),
@@ -606,12 +606,12 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
606 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 606 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
607}; 607};
608 608
609static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 609static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
610 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 610 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
611 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 611 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
612}; 612};
613 613
614static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 614static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
615 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 615 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
616 SRC_TOP7, 4, 1), 616 SRC_TOP7, 4, 1),
617 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 617 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
@@ -778,7 +778,7 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
778 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 778 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
779}; 779};
780 780
781static struct samsung_div_clock exynos5x_div_clks[] __initdata = { 781static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
782 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 782 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
783 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 783 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
784 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 784 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
@@ -911,7 +911,7 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
911 CLK_SET_RATE_PARENT, 0), 911 CLK_SET_RATE_PARENT, 0),
912}; 912};
913 913
914static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { 914static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
915 /* G2D */ 915 /* G2D */
916 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 916 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
917 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 917 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
@@ -946,7 +946,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
946 GATE_BUS_TOP, 13, 0, 0), 946 GATE_BUS_TOP, 13, 0, 0),
947 GATE(0, "aclk166", "mout_user_aclk166", 947 GATE(0, "aclk166", "mout_user_aclk166",
948 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 948 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
949 GATE(0, "aclk333", "mout_user_aclk333", 949 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
950 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 950 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
951 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 951 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
952 GATE_BUS_TOP, 16, 0, 0), 952 GATE_BUS_TOP, 16, 0, 0),
@@ -1219,7 +1219,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
1219 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1219 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1220}; 1220};
1221 1221
1222static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = { 1222static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1223 PLL_35XX_RATE(2000000000, 250, 3, 0), 1223 PLL_35XX_RATE(2000000000, 250, 3, 0),
1224 PLL_35XX_RATE(1900000000, 475, 6, 0), 1224 PLL_35XX_RATE(1900000000, 475, 6, 0),
1225 PLL_35XX_RATE(1800000000, 225, 3, 0), 1225 PLL_35XX_RATE(1800000000, 225, 3, 0),
@@ -1356,8 +1356,6 @@ static void __init exynos5x_clk_init(struct device_node *np,
1356 exynos5x_soc = soc; 1356 exynos5x_soc = soc;
1357 1357
1358 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1358 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1359 if (!ctx)
1360 panic("%s: unable to allocate context.\n", __func__);
1361 1359
1362 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1360 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1363 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1361 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 128527b8fbeb..ea1608682d7f 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -11,10 +11,12 @@
11 11
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/of_address.h>
14 15
15#include <dt-bindings/clock/exynos5433.h> 16#include <dt-bindings/clock/exynos5433.h>
16 17
17#include "clk.h" 18#include "clk.h"
19#include "clk-cpu.h"
18#include "clk-pll.h" 20#include "clk-pll.h"
19 21
20/* 22/*
@@ -108,7 +110,7 @@
108#define ENABLE_CMU_TOP 0x0c00 110#define ENABLE_CMU_TOP 0x0c00
109#define ENABLE_CMU_TOP_DIV_STAT 0x0c04 111#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
110 112
111static unsigned long top_clk_regs[] __initdata = { 113static const unsigned long top_clk_regs[] __initconst = {
112 ISP_PLL_LOCK, 114 ISP_PLL_LOCK,
113 AUD_PLL_LOCK, 115 AUD_PLL_LOCK,
114 ISP_PLL_CON0, 116 ISP_PLL_CON0,
@@ -218,11 +220,11 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
218 220
219PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 221PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
220 222
221static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { 223static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
222 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 224 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
223}; 225};
224 226
225static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { 227static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
226 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 228 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
227 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 229 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
228 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 230 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
@@ -238,7 +240,7 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
238 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 240 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
239}; 241};
240 242
241static struct samsung_mux_clock top_mux_clks[] __initdata = { 243static const struct samsung_mux_clock top_mux_clks[] __initconst = {
242 /* MUX_SEL_TOP0 */ 244 /* MUX_SEL_TOP0 */
243 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 245 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
244 4, 1), 246 4, 1),
@@ -374,7 +376,7 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
374 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 376 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
375}; 377};
376 378
377static struct samsung_div_clock top_div_clks[] __initdata = { 379static const struct samsung_div_clock top_div_clks[] __initconst = {
378 /* DIV_TOP0 */ 380 /* DIV_TOP0 */
379 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 381 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
380 DIV_TOP0, 28, 3), 382 DIV_TOP0, 28, 3),
@@ -538,7 +540,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
538 DIV_TOP_PERIC4, 0, 4), 540 DIV_TOP_PERIC4, 0, 4),
539}; 541};
540 542
541static struct samsung_gate_clock top_gate_clks[] __initdata = { 543static const struct samsung_gate_clock top_gate_clks[] __initconst = {
542 /* ENABLE_ACLK_TOP */ 544 /* ENABLE_ACLK_TOP */
543 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 545 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
544 ENABLE_ACLK_TOP, 30, 0, 0), 546 ENABLE_ACLK_TOP, 30, 0, 0),
@@ -639,7 +641,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
639 641
640 /* ENABLE_SCLK_TOP_FSYS */ 642 /* ENABLE_SCLK_TOP_FSYS */
641 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 643 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
642 ENABLE_SCLK_TOP_FSYS, 7, 0, 0), 644 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
643 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 645 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
644 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 646 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
645 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 647 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
@@ -668,11 +670,14 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
668 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 670 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
669 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 671 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
670 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 672 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
671 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), 673 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
674 CLK_IGNORE_UNUSED, 0),
672 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 675 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
673 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), 676 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
677 CLK_IGNORE_UNUSED, 0),
674 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 678 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
675 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), 679 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
680 CLK_IGNORE_UNUSED, 0),
676 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 681 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
677 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 682 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
678 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 683 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
@@ -693,7 +698,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
693 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 698 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
694 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 699 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
695 */ 700 */
696static struct samsung_pll_rate_table exynos5443_pll_rates[] = { 701static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = {
697 PLL_35XX_RATE(2500000000U, 625, 6, 0), 702 PLL_35XX_RATE(2500000000U, 625, 6, 0),
698 PLL_35XX_RATE(2400000000U, 500, 5, 0), 703 PLL_35XX_RATE(2400000000U, 500, 5, 0),
699 PLL_35XX_RATE(2300000000U, 575, 6, 0), 704 PLL_35XX_RATE(2300000000U, 575, 6, 0),
@@ -744,7 +749,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
744}; 749};
745 750
746/* AUD_PLL */ 751/* AUD_PLL */
747static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { 752static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = {
748 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 753 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
749 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), 754 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
750 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 755 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
@@ -757,14 +762,14 @@ static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
757 { /* sentinel */ } 762 { /* sentinel */ }
758}; 763};
759 764
760static struct samsung_pll_clock top_pll_clks[] __initdata = { 765static const struct samsung_pll_clock top_pll_clks[] __initconst = {
761 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 766 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
762 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), 767 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
763 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 768 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
764 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), 769 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
765}; 770};
766 771
767static struct samsung_cmu_info top_cmu_info __initdata = { 772static const struct samsung_cmu_info top_cmu_info __initconst = {
768 .pll_clks = top_pll_clks, 773 .pll_clks = top_pll_clks,
769 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 774 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
770 .mux_clks = top_mux_clks, 775 .mux_clks = top_mux_clks,
@@ -800,7 +805,7 @@ CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
800#define DIV_CPIF 0x0600 805#define DIV_CPIF 0x0600
801#define ENABLE_SCLK_CPIF 0x0a00 806#define ENABLE_SCLK_CPIF 0x0a00
802 807
803static unsigned long cpif_clk_regs[] __initdata = { 808static const unsigned long cpif_clk_regs[] __initconst = {
804 MPHY_PLL_LOCK, 809 MPHY_PLL_LOCK,
805 MPHY_PLL_CON0, 810 MPHY_PLL_CON0,
806 MPHY_PLL_CON1, 811 MPHY_PLL_CON1,
@@ -813,32 +818,32 @@ static unsigned long cpif_clk_regs[] __initdata = {
813/* list of all parent clock list */ 818/* list of all parent clock list */
814PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 819PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
815 820
816static struct samsung_pll_clock cpif_pll_clks[] __initdata = { 821static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
817 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 822 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
818 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), 823 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
819}; 824};
820 825
821static struct samsung_mux_clock cpif_mux_clks[] __initdata = { 826static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
822 /* MUX_SEL_CPIF0 */ 827 /* MUX_SEL_CPIF0 */
823 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 828 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
824 0, 1), 829 0, 1),
825}; 830};
826 831
827static struct samsung_div_clock cpif_div_clks[] __initdata = { 832static const struct samsung_div_clock cpif_div_clks[] __initconst = {
828 /* DIV_CPIF */ 833 /* DIV_CPIF */
829 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 834 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
830 0, 6), 835 0, 6),
831}; 836};
832 837
833static struct samsung_gate_clock cpif_gate_clks[] __initdata = { 838static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
834 /* ENABLE_SCLK_CPIF */ 839 /* ENABLE_SCLK_CPIF */
835 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 840 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
836 ENABLE_SCLK_CPIF, 9, 0, 0), 841 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
837 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 842 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
838 ENABLE_SCLK_CPIF, 4, 0, 0), 843 ENABLE_SCLK_CPIF, 4, 0, 0),
839}; 844};
840 845
841static struct samsung_cmu_info cpif_cmu_info __initdata = { 846static const struct samsung_cmu_info cpif_cmu_info __initconst = {
842 .pll_clks = cpif_pll_clks, 847 .pll_clks = cpif_pll_clks,
843 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 848 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
844 .mux_clks = cpif_mux_clks, 849 .mux_clks = cpif_mux_clks,
@@ -939,7 +944,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
939#define PAUSE 0x1008 944#define PAUSE 0x1008
940#define DDRPHY_LOCK_CTRL 0x100c 945#define DDRPHY_LOCK_CTRL 0x100c
941 946
942static unsigned long mif_clk_regs[] __initdata = { 947static const unsigned long mif_clk_regs[] __initconst = {
943 MEM0_PLL_LOCK, 948 MEM0_PLL_LOCK,
944 MEM1_PLL_LOCK, 949 MEM1_PLL_LOCK,
945 BUS_PLL_LOCK, 950 BUS_PLL_LOCK,
@@ -1004,7 +1009,7 @@ static unsigned long mif_clk_regs[] __initdata = {
1004 DDRPHY_LOCK_CTRL, 1009 DDRPHY_LOCK_CTRL,
1005}; 1010};
1006 1011
1007static struct samsung_pll_clock mif_pll_clks[] __initdata = { 1012static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1008 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1013 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1009 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), 1014 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1010 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1015 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
@@ -1065,7 +1070,7 @@ PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1065PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1070PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1066PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1071PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1067 1072
1068static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { 1073static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1069 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1074 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1070 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1075 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1071 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1076 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
@@ -1073,7 +1078,7 @@ static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1073 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1078 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1074}; 1079};
1075 1080
1076static struct samsung_mux_clock mif_mux_clks[] __initdata = { 1081static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1077 /* MUX_SEL_MIF0 */ 1082 /* MUX_SEL_MIF0 */
1078 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1083 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1079 MUX_SEL_MIF0, 28, 1), 1084 MUX_SEL_MIF0, 28, 1),
@@ -1169,7 +1174,7 @@ static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1169 MUX_SEL_MIF7, 0, 1), 1174 MUX_SEL_MIF7, 0, 1),
1170}; 1175};
1171 1176
1172static struct samsung_div_clock mif_div_clks[] __initdata = { 1177static const struct samsung_div_clock mif_div_clks[] __initconst = {
1173 /* DIV_MIF1 */ 1178 /* DIV_MIF1 */
1174 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1179 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1175 DIV_MIF1, 16, 2), 1180 DIV_MIF1, 16, 2),
@@ -1223,7 +1228,7 @@ static struct samsung_div_clock mif_div_clks[] __initdata = {
1223 0, 3), 1228 0, 3),
1224}; 1229};
1225 1230
1226static struct samsung_gate_clock mif_gate_clks[] __initdata = { 1231static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1227 /* ENABLE_ACLK_MIF0 */ 1232 /* ENABLE_ACLK_MIF0 */
1228 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1233 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1229 19, CLK_IGNORE_UNUSED, 0), 1234 19, CLK_IGNORE_UNUSED, 0),
@@ -1440,11 +1445,13 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1440 1445
1441 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1446 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1442 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1447 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1443 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), 1448 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1449 CLK_IGNORE_UNUSED, 0),
1444 1450
1445 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1451 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1446 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1452 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1447 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), 1453 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1454 CLK_IGNORE_UNUSED, 0),
1448 1455
1449 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1456 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1450 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1457 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
@@ -1486,7 +1493,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1486 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1493 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1487}; 1494};
1488 1495
1489static struct samsung_cmu_info mif_cmu_info __initdata = { 1496static const struct samsung_cmu_info mif_cmu_info __initconst = {
1490 .pll_clks = mif_pll_clks, 1497 .pll_clks = mif_pll_clks,
1491 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1498 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1492 .mux_clks = mif_mux_clks, 1499 .mux_clks = mif_mux_clks,
@@ -1522,7 +1529,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1522#define ENABLE_IP_PERIC1 0x0B04 1529#define ENABLE_IP_PERIC1 0x0B04
1523#define ENABLE_IP_PERIC2 0x0B08 1530#define ENABLE_IP_PERIC2 0x0B08
1524 1531
1525static unsigned long peric_clk_regs[] __initdata = { 1532static const unsigned long peric_clk_regs[] __initconst = {
1526 DIV_PERIC, 1533 DIV_PERIC,
1527 ENABLE_ACLK_PERIC, 1534 ENABLE_ACLK_PERIC,
1528 ENABLE_PCLK_PERIC0, 1535 ENABLE_PCLK_PERIC0,
@@ -1533,13 +1540,13 @@ static unsigned long peric_clk_regs[] __initdata = {
1533 ENABLE_IP_PERIC2, 1540 ENABLE_IP_PERIC2,
1534}; 1541};
1535 1542
1536static struct samsung_div_clock peric_div_clks[] __initdata = { 1543static const struct samsung_div_clock peric_div_clks[] __initconst = {
1537 /* DIV_PERIC */ 1544 /* DIV_PERIC */
1538 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1545 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1539 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1546 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1540}; 1547};
1541 1548
1542static struct samsung_gate_clock peric_gate_clks[] __initdata = { 1549static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1543 /* ENABLE_ACLK_PERIC */ 1550 /* ENABLE_ACLK_PERIC */
1544 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1551 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1545 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1552 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
@@ -1654,8 +1661,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1654 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1661 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1655 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1662 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1663 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1657 ENABLE_SCLK_PERIC, 12, 1664 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1658 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1659 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1665 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1660 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1666 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1661 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1667 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
@@ -1670,18 +1676,21 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1670 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1676 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1671 5, CLK_SET_RATE_PARENT, 0), 1677 5, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1678 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1673 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1679 4, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1680 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1675 3, CLK_SET_RATE_PARENT, 0), 1681 3, CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1682 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1677 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1683 ENABLE_SCLK_PERIC, 2,
1684 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1678 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1685 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1679 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1686 ENABLE_SCLK_PERIC, 1,
1687 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1680 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1688 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1681 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1689 ENABLE_SCLK_PERIC, 0,
1690 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1682}; 1691};
1683 1692
1684static struct samsung_cmu_info peric_cmu_info __initdata = { 1693static const struct samsung_cmu_info peric_cmu_info __initconst = {
1685 .div_clks = peric_div_clks, 1694 .div_clks = peric_div_clks,
1686 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1695 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1687 .gate_clks = peric_gate_clks, 1696 .gate_clks = peric_gate_clks,
@@ -1728,7 +1737,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1728#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1737#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1729#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1738#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1730 1739
1731static unsigned long peris_clk_regs[] __initdata = { 1740static const unsigned long peris_clk_regs[] __initconst = {
1732 ENABLE_ACLK_PERIS, 1741 ENABLE_ACLK_PERIS,
1733 ENABLE_PCLK_PERIS, 1742 ENABLE_PCLK_PERIS,
1734 ENABLE_PCLK_PERIS_SECURE_TZPC, 1743 ENABLE_PCLK_PERIS_SECURE_TZPC,
@@ -1756,7 +1765,7 @@ static unsigned long peris_clk_regs[] __initdata = {
1756 ENABLE_IP_PERIS_SECURE_OTP_CON, 1765 ENABLE_IP_PERIS_SECURE_OTP_CON,
1757}; 1766};
1758 1767
1759static struct samsung_gate_clock peris_gate_clks[] __initdata = { 1768static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1760 /* ENABLE_ACLK_PERIS */ 1769 /* ENABLE_ACLK_PERIS */
1761 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1770 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1762 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1771 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
@@ -1875,7 +1884,7 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1875 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1884 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1876}; 1885};
1877 1886
1878static struct samsung_cmu_info peris_cmu_info __initdata = { 1887static const struct samsung_cmu_info peris_cmu_info __initconst = {
1879 .gate_clks = peris_gate_clks, 1888 .gate_clks = peris_gate_clks,
1880 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1889 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1881 .nr_clk_ids = PERIS_NR_CLK, 1890 .nr_clk_ids = PERIS_NR_CLK,
@@ -1959,7 +1968,7 @@ PNAME(mout_sclk_mphy_p)
1959 = { "mout_sclk_ufs_mphy_user", 1968 = { "mout_sclk_ufs_mphy_user",
1960 "mout_phyclk_lli_mphy_to_ufs_user", }; 1969 "mout_phyclk_lli_mphy_to_ufs_user", };
1961 1970
1962static unsigned long fsys_clk_regs[] __initdata = { 1971static const unsigned long fsys_clk_regs[] __initconst = {
1963 MUX_SEL_FSYS0, 1972 MUX_SEL_FSYS0,
1964 MUX_SEL_FSYS1, 1973 MUX_SEL_FSYS1,
1965 MUX_SEL_FSYS2, 1974 MUX_SEL_FSYS2,
@@ -1980,7 +1989,7 @@ static unsigned long fsys_clk_regs[] __initdata = {
1980 ENABLE_IP_FSYS1, 1989 ENABLE_IP_FSYS1,
1981}; 1990};
1982 1991
1983static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = { 1992static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
1984 /* PHY clocks from USBDRD30_PHY */ 1993 /* PHY clocks from USBDRD30_PHY */
1985 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 1994 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1986 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 1995 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
@@ -2020,7 +2029,7 @@ static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
2020 NULL, 0, 26000000), 2029 NULL, 0, 26000000),
2021}; 2030};
2022 2031
2023static struct samsung_mux_clock fsys_mux_clks[] __initdata = { 2032static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2024 /* MUX_SEL_FSYS0 */ 2033 /* MUX_SEL_FSYS0 */
2025 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2034 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2026 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2035 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
@@ -2104,7 +2113,7 @@ static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2104 MUX_SEL_FSYS4, 0, 1), 2113 MUX_SEL_FSYS4, 0, 1),
2105}; 2114};
2106 2115
2107static struct samsung_gate_clock fsys_gate_clks[] __initdata = { 2116static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2108 /* ENABLE_ACLK_FSYS0 */ 2117 /* ENABLE_ACLK_FSYS0 */
2109 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2118 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2110 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2119 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
@@ -2138,7 +2147,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2138 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2147 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2139 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2148 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2140 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2149 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2141 ENABLE_ACLK_FSYS1, 24, 0, 0), 2150 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2142 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2151 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2143 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2152 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2144 22, CLK_IGNORE_UNUSED, 0), 2153 22, CLK_IGNORE_UNUSED, 0),
@@ -2185,13 +2194,13 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2185 2194
2186 /* ENABLE_PCLK_FSYS */ 2195 /* ENABLE_PCLK_FSYS */
2187 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2196 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2188 ENABLE_PCLK_FSYS, 17, 0, 0), 2197 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2189 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2198 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2190 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2199 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2191 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2200 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2192 ENABLE_PCLK_FSYS, 14, 0, 0), 2201 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2193 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2202 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2194 ENABLE_PCLK_FSYS, 13, 0, 0), 2203 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2195 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2204 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2196 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2205 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2197 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2206 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
@@ -2270,11 +2279,12 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2270 ENABLE_SCLK_FSYS, 0, 0, 0), 2279 ENABLE_SCLK_FSYS, 0, 0, 0),
2271 2280
2272 /* ENABLE_IP_FSYS0 */ 2281 /* ENABLE_IP_FSYS0 */
2282 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2273 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2283 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2274 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2284 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2275}; 2285};
2276 2286
2277static struct samsung_cmu_info fsys_cmu_info __initdata = { 2287static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2278 .mux_clks = fsys_mux_clks, 2288 .mux_clks = fsys_mux_clks,
2279 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2289 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2280 .gate_clks = fsys_gate_clks, 2290 .gate_clks = fsys_gate_clks,
@@ -2310,7 +2320,7 @@ CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2310#define DIV_ENABLE_IP_G2D1 0x0b04 2320#define DIV_ENABLE_IP_G2D1 0x0b04
2311#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2321#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2312 2322
2313static unsigned long g2d_clk_regs[] __initdata = { 2323static const unsigned long g2d_clk_regs[] __initconst = {
2314 MUX_SEL_G2D0, 2324 MUX_SEL_G2D0,
2315 MUX_SEL_ENABLE_G2D0, 2325 MUX_SEL_ENABLE_G2D0,
2316 DIV_G2D, 2326 DIV_G2D,
@@ -2327,7 +2337,7 @@ static unsigned long g2d_clk_regs[] __initdata = {
2327PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2337PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2328PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2338PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2329 2339
2330static struct samsung_mux_clock g2d_mux_clks[] __initdata = { 2340static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2331 /* MUX_SEL_G2D0 */ 2341 /* MUX_SEL_G2D0 */
2332 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2342 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2333 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2343 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
@@ -2335,13 +2345,13 @@ static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2335 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2345 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2336}; 2346};
2337 2347
2338static struct samsung_div_clock g2d_div_clks[] __initdata = { 2348static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2339 /* DIV_G2D */ 2349 /* DIV_G2D */
2340 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2350 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2341 DIV_G2D, 0, 2), 2351 DIV_G2D, 0, 2),
2342}; 2352};
2343 2353
2344static struct samsung_gate_clock g2d_gate_clks[] __initdata = { 2354static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2345 /* DIV_ENABLE_ACLK_G2D */ 2355 /* DIV_ENABLE_ACLK_G2D */
2346 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2356 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2347 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2357 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
@@ -2398,7 +2408,7 @@ static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2398 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2408 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2399}; 2409};
2400 2410
2401static struct samsung_cmu_info g2d_cmu_info __initdata = { 2411static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2402 .mux_clks = g2d_mux_clks, 2412 .mux_clks = g2d_mux_clks,
2403 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2413 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2404 .div_clks = g2d_div_clks, 2414 .div_clks = g2d_div_clks,
@@ -2454,7 +2464,7 @@ CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2454#define CLKOUT_CMU_DISP 0x0c00 2464#define CLKOUT_CMU_DISP 0x0c00
2455#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2465#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2456 2466
2457static unsigned long disp_clk_regs[] __initdata = { 2467static const unsigned long disp_clk_regs[] __initconst = {
2458 DISP_PLL_LOCK, 2468 DISP_PLL_LOCK,
2459 DISP_PLL_CON0, 2469 DISP_PLL_CON0,
2460 DISP_PLL_CON1, 2470 DISP_PLL_CON1,
@@ -2527,12 +2537,12 @@ PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2527PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2537PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2528 "mout_sclk_decon_tv_vclk_user", }; 2538 "mout_sclk_decon_tv_vclk_user", };
2529 2539
2530static struct samsung_pll_clock disp_pll_clks[] __initdata = { 2540static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2531 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2541 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2532 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), 2542 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2533}; 2543};
2534 2544
2535static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { 2545static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2536 /* 2546 /*
2537 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2547 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2538 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2548 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
@@ -2544,7 +2554,7 @@ static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2544 1, 2, 0), 2554 1, 2, 0),
2545}; 2555};
2546 2556
2547static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { 2557static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2548 /* PHY clocks from MIPI_DPHY1 */ 2558 /* PHY clocks from MIPI_DPHY1 */
2549 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2559 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2550 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2560 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
@@ -2558,7 +2568,7 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2558 NULL, 0, 166000000), 2568 NULL, 0, 166000000),
2559}; 2569};
2560 2570
2561static struct samsung_mux_clock disp_mux_clks[] __initdata = { 2571static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2562 /* MUX_SEL_DISP0 */ 2572 /* MUX_SEL_DISP0 */
2563 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2573 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2564 0, 1), 2574 0, 1),
@@ -2633,7 +2643,7 @@ static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2633 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2643 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2634}; 2644};
2635 2645
2636static struct samsung_div_clock disp_div_clks[] __initdata = { 2646static const struct samsung_div_clock disp_div_clks[] __initconst = {
2637 /* DIV_DISP */ 2647 /* DIV_DISP */
2638 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2648 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2639 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2649 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
@@ -2651,7 +2661,7 @@ static struct samsung_div_clock disp_div_clks[] __initdata = {
2651 DIV_DISP, 0, 2), 2661 DIV_DISP, 0, 2),
2652}; 2662};
2653 2663
2654static struct samsung_gate_clock disp_gate_clks[] __initdata = { 2664static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2655 /* ENABLE_ACLK_DISP0 */ 2665 /* ENABLE_ACLK_DISP0 */
2656 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2666 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2657 ENABLE_ACLK_DISP0, 2, 0, 0), 2667 ENABLE_ACLK_DISP0, 2, 0, 0),
@@ -2811,7 +2821,7 @@ static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2811 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2821 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2812}; 2822};
2813 2823
2814static struct samsung_cmu_info disp_cmu_info __initdata = { 2824static const struct samsung_cmu_info disp_cmu_info __initconst = {
2815 .pll_clks = disp_pll_clks, 2825 .pll_clks = disp_pll_clks,
2816 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2826 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2817 .mux_clks = disp_mux_clks, 2827 .mux_clks = disp_mux_clks,
@@ -2856,7 +2866,7 @@ CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2856#define ENABLE_IP_AUD0 0x0b00 2866#define ENABLE_IP_AUD0 0x0b00
2857#define ENABLE_IP_AUD1 0x0b04 2867#define ENABLE_IP_AUD1 0x0b04
2858 2868
2859static unsigned long aud_clk_regs[] __initdata = { 2869static const unsigned long aud_clk_regs[] __initconst = {
2860 MUX_SEL_AUD0, 2870 MUX_SEL_AUD0,
2861 MUX_SEL_AUD1, 2871 MUX_SEL_AUD1,
2862 MUX_ENABLE_AUD0, 2872 MUX_ENABLE_AUD0,
@@ -2875,13 +2885,13 @@ static unsigned long aud_clk_regs[] __initdata = {
2875PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2885PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2876PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2886PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2877 2887
2878static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { 2888static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2879 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2889 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2880 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2890 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2881 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2891 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2882}; 2892};
2883 2893
2884static struct samsung_mux_clock aud_mux_clks[] __initdata = { 2894static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2885 /* MUX_SEL_AUD0 */ 2895 /* MUX_SEL_AUD0 */
2886 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2896 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2887 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2897 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
@@ -2893,7 +2903,7 @@ static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2893 MUX_SEL_AUD1, 0, 1), 2903 MUX_SEL_AUD1, 0, 1),
2894}; 2904};
2895 2905
2896static struct samsung_div_clock aud_div_clks[] __initdata = { 2906static const struct samsung_div_clock aud_div_clks[] __initconst = {
2897 /* DIV_AUD0 */ 2907 /* DIV_AUD0 */
2898 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2908 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2899 12, 4), 2909 12, 4),
@@ -2915,7 +2925,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = {
2915 DIV_AUD1, 0, 4), 2925 DIV_AUD1, 0, 4),
2916}; 2926};
2917 2927
2918static struct samsung_gate_clock aud_gate_clks[] __initdata = { 2928static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2919 /* ENABLE_ACLK_AUD */ 2929 /* ENABLE_ACLK_AUD */
2920 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 2930 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2921 ENABLE_ACLK_AUD, 12, 0, 0), 2931 ENABLE_ACLK_AUD, 12, 0, 0),
@@ -2962,7 +2972,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2962 2972
2963 /* ENABLE_SCLK_AUD0 */ 2973 /* ENABLE_SCLK_AUD0 */
2964 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 2974 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2965 2, 0, 0), 2975 2, CLK_IGNORE_UNUSED, 0),
2966 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 2976 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2967 ENABLE_SCLK_AUD0, 1, 0, 0), 2977 ENABLE_SCLK_AUD0, 1, 0, 0),
2968 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 2978 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
@@ -2976,7 +2986,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2976 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 2986 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2977 ENABLE_SCLK_AUD1, 4, 0, 0), 2987 ENABLE_SCLK_AUD1, 4, 0, 0),
2978 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 2988 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2979 ENABLE_SCLK_AUD1, 3, 0, 0), 2989 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
2980 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 2990 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2981 ENABLE_SCLK_AUD1, 2, 0, 0), 2991 ENABLE_SCLK_AUD1, 2, 0, 0),
2982 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 2992 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
@@ -2985,7 +2995,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2985 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 2995 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2986}; 2996};
2987 2997
2988static struct samsung_cmu_info aud_cmu_info __initdata = { 2998static const struct samsung_cmu_info aud_cmu_info __initconst = {
2989 .mux_clks = aud_mux_clks, 2999 .mux_clks = aud_mux_clks,
2990 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3000 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
2991 .div_clks = aud_div_clks, 3001 .div_clks = aud_div_clks,
@@ -3031,24 +3041,24 @@ PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3031 ENABLE_IP_BUS0, \ 3041 ENABLE_IP_BUS0, \
3032 ENABLE_IP_BUS1 3042 ENABLE_IP_BUS1
3033 3043
3034static unsigned long bus01_clk_regs[] __initdata = { 3044static const unsigned long bus01_clk_regs[] __initconst = {
3035 CMU_BUS_COMMON_CLK_REGS, 3045 CMU_BUS_COMMON_CLK_REGS,
3036}; 3046};
3037 3047
3038static unsigned long bus2_clk_regs[] __initdata = { 3048static const unsigned long bus2_clk_regs[] __initconst = {
3039 MUX_SEL_BUS2, 3049 MUX_SEL_BUS2,
3040 MUX_ENABLE_BUS2, 3050 MUX_ENABLE_BUS2,
3041 CMU_BUS_COMMON_CLK_REGS, 3051 CMU_BUS_COMMON_CLK_REGS,
3042}; 3052};
3043 3053
3044static struct samsung_div_clock bus0_div_clks[] __initdata = { 3054static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3045 /* DIV_BUS0 */ 3055 /* DIV_BUS0 */
3046 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3056 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3047 DIV_BUS, 0, 3), 3057 DIV_BUS, 0, 3),
3048}; 3058};
3049 3059
3050/* CMU_BUS0 clocks */ 3060/* CMU_BUS0 clocks */
3051static struct samsung_gate_clock bus0_gate_clks[] __initdata = { 3061static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3052 /* ENABLE_ACLK_BUS0 */ 3062 /* ENABLE_ACLK_BUS0 */
3053 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3063 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3054 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3064 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
@@ -3067,13 +3077,13 @@ static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3067}; 3077};
3068 3078
3069/* CMU_BUS1 clocks */ 3079/* CMU_BUS1 clocks */
3070static struct samsung_div_clock bus1_div_clks[] __initdata = { 3080static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3071 /* DIV_BUS1 */ 3081 /* DIV_BUS1 */
3072 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3082 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3073 DIV_BUS, 0, 3), 3083 DIV_BUS, 0, 3),
3074}; 3084};
3075 3085
3076static struct samsung_gate_clock bus1_gate_clks[] __initdata = { 3086static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3077 /* ENABLE_ACLK_BUS1 */ 3087 /* ENABLE_ACLK_BUS1 */
3078 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3088 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3079 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3089 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
@@ -3092,19 +3102,19 @@ static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3092}; 3102};
3093 3103
3094/* CMU_BUS2 clocks */ 3104/* CMU_BUS2 clocks */
3095static struct samsung_mux_clock bus2_mux_clks[] __initdata = { 3105static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3096 /* MUX_SEL_BUS2 */ 3106 /* MUX_SEL_BUS2 */
3097 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3107 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3098 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3108 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3099}; 3109};
3100 3110
3101static struct samsung_div_clock bus2_div_clks[] __initdata = { 3111static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3102 /* DIV_BUS2 */ 3112 /* DIV_BUS2 */
3103 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3113 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3104 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3114 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3105}; 3115};
3106 3116
3107static struct samsung_gate_clock bus2_gate_clks[] __initdata = { 3117static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3108 /* ENABLE_ACLK_BUS2 */ 3118 /* ENABLE_ACLK_BUS2 */
3109 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3119 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3110 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3120 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
@@ -3133,19 +3143,19 @@ static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3133 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3143 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3134 .nr_clk_ids = BUSx_NR_CLK 3144 .nr_clk_ids = BUSx_NR_CLK
3135 3145
3136static struct samsung_cmu_info bus0_cmu_info __initdata = { 3146static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3137 CMU_BUS_INFO_CLKS(0), 3147 CMU_BUS_INFO_CLKS(0),
3138 .clk_regs = bus01_clk_regs, 3148 .clk_regs = bus01_clk_regs,
3139 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3149 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3140}; 3150};
3141 3151
3142static struct samsung_cmu_info bus1_cmu_info __initdata = { 3152static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3143 CMU_BUS_INFO_CLKS(1), 3153 CMU_BUS_INFO_CLKS(1),
3144 .clk_regs = bus01_clk_regs, 3154 .clk_regs = bus01_clk_regs,
3145 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3155 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3146}; 3156};
3147 3157
3148static struct samsung_cmu_info bus2_cmu_info __initdata = { 3158static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3149 CMU_BUS_INFO_CLKS(2), 3159 CMU_BUS_INFO_CLKS(2),
3150 .mux_clks = bus2_mux_clks, 3160 .mux_clks = bus2_mux_clks,
3151 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3161 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
@@ -3189,7 +3199,7 @@ exynos5433_cmu_bus_init(2);
3189#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3199#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3190#define CLK_STOPCTRL 0x1000 3200#define CLK_STOPCTRL 0x1000
3191 3201
3192static unsigned long g3d_clk_regs[] __initdata = { 3202static const unsigned long g3d_clk_regs[] __initconst = {
3193 G3D_PLL_LOCK, 3203 G3D_PLL_LOCK,
3194 G3D_PLL_CON0, 3204 G3D_PLL_CON0,
3195 G3D_PLL_CON1, 3205 G3D_PLL_CON1,
@@ -3212,12 +3222,12 @@ static unsigned long g3d_clk_regs[] __initdata = {
3212PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3222PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3213PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3223PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3214 3224
3215static struct samsung_pll_clock g3d_pll_clks[] __initdata = { 3225static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3216 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3226 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3217 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), 3227 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3218}; 3228};
3219 3229
3220static struct samsung_mux_clock g3d_mux_clks[] __initdata = { 3230static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3221 /* MUX_SEL_G3D */ 3231 /* MUX_SEL_G3D */
3222 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3232 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3223 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3233 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
@@ -3225,7 +3235,7 @@ static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3225 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3235 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3226}; 3236};
3227 3237
3228static struct samsung_div_clock g3d_div_clks[] __initdata = { 3238static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3229 /* DIV_G3D */ 3239 /* DIV_G3D */
3230 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3240 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3231 8, 2), 3241 8, 2),
@@ -3235,7 +3245,7 @@ static struct samsung_div_clock g3d_div_clks[] __initdata = {
3235 0, 3, CLK_SET_RATE_PARENT, 0), 3245 0, 3, CLK_SET_RATE_PARENT, 0),
3236}; 3246};
3237 3247
3238static struct samsung_gate_clock g3d_gate_clks[] __initdata = { 3248static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3239 /* ENABLE_ACLK_G3D */ 3249 /* ENABLE_ACLK_G3D */
3240 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3250 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3241 ENABLE_ACLK_G3D, 7, 0, 0), 3251 ENABLE_ACLK_G3D, 7, 0, 0),
@@ -3269,7 +3279,7 @@ static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3269 ENABLE_SCLK_G3D, 0, 0, 0), 3279 ENABLE_SCLK_G3D, 0, 0, 0),
3270}; 3280};
3271 3281
3272static struct samsung_cmu_info g3d_cmu_info __initdata = { 3282static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3273 .pll_clks = g3d_pll_clks, 3283 .pll_clks = g3d_pll_clks,
3274 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3284 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3275 .mux_clks = g3d_mux_clks, 3285 .mux_clks = g3d_mux_clks,
@@ -3310,7 +3320,7 @@ CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3310#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3320#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3311#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3321#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3312 3322
3313static unsigned long gscl_clk_regs[] __initdata = { 3323static const unsigned long gscl_clk_regs[] __initconst = {
3314 MUX_SEL_GSCL, 3324 MUX_SEL_GSCL,
3315 MUX_ENABLE_GSCL, 3325 MUX_ENABLE_GSCL,
3316 ENABLE_ACLK_GSCL, 3326 ENABLE_ACLK_GSCL,
@@ -3332,7 +3342,7 @@ static unsigned long gscl_clk_regs[] __initdata = {
3332PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3342PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3333PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3343PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3334 3344
3335static struct samsung_mux_clock gscl_mux_clks[] __initdata = { 3345static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3336 /* MUX_SEL_GSCL */ 3346 /* MUX_SEL_GSCL */
3337 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3347 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3338 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3348 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
@@ -3340,7 +3350,7 @@ static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3340 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3350 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3341}; 3351};
3342 3352
3343static struct samsung_gate_clock gscl_gate_clks[] __initdata = { 3353static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3344 /* ENABLE_ACLK_GSCL */ 3354 /* ENABLE_ACLK_GSCL */
3345 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3355 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3346 ENABLE_ACLK_GSCL, 11, 0, 0), 3356 ENABLE_ACLK_GSCL, 11, 0, 0),
@@ -3356,9 +3366,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3356 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3366 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3357 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3367 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3358 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3368 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3359 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0), 3369 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3370 CLK_IGNORE_UNUSED, 0),
3360 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3371 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3361 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0), 3372 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3373 CLK_IGNORE_UNUSED, 0),
3362 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3374 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3363 ENABLE_ACLK_GSCL, 3, 0, 0), 3375 ENABLE_ACLK_GSCL, 3, 0, 0),
3364 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3376 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
@@ -3412,7 +3424,7 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3412 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3424 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3413}; 3425};
3414 3426
3415static struct samsung_cmu_info gscl_cmu_info __initdata = { 3427static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3416 .mux_clks = gscl_mux_clks, 3428 .mux_clks = gscl_mux_clks,
3417 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3429 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3418 .gate_clks = gscl_gate_clks, 3430 .gate_clks = gscl_gate_clks,
@@ -3465,7 +3477,7 @@ CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3465#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3477#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3466#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3478#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3467 3479
3468static unsigned long apollo_clk_regs[] __initdata = { 3480static const unsigned long apollo_clk_regs[] __initconst = {
3469 APOLLO_PLL_LOCK, 3481 APOLLO_PLL_LOCK,
3470 APOLLO_PLL_CON0, 3482 APOLLO_PLL_CON0,
3471 APOLLO_PLL_CON1, 3483 APOLLO_PLL_CON1,
@@ -3500,15 +3512,16 @@ PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3500PNAME(mout_apollo_p) = { "mout_apollo_pll", 3512PNAME(mout_apollo_p) = { "mout_apollo_pll",
3501 "mout_bus_pll_apollo_user", }; 3513 "mout_bus_pll_apollo_user", };
3502 3514
3503static struct samsung_pll_clock apollo_pll_clks[] __initdata = { 3515static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3504 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3516 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3505 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), 3517 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3506}; 3518};
3507 3519
3508static struct samsung_mux_clock apollo_mux_clks[] __initdata = { 3520static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3509 /* MUX_SEL_APOLLO0 */ 3521 /* MUX_SEL_APOLLO0 */
3510 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3522 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3511 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), 3523 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3524 CLK_RECALC_NEW_RATES, 0),
3512 3525
3513 /* MUX_SEL_APOLLO1 */ 3526 /* MUX_SEL_APOLLO1 */
3514 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3527 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
@@ -3519,7 +3532,7 @@ static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3519 0, 1, CLK_SET_RATE_PARENT, 0), 3532 0, 1, CLK_SET_RATE_PARENT, 0),
3520}; 3533};
3521 3534
3522static struct samsung_div_clock apollo_div_clks[] __initdata = { 3535static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3523 /* DIV_APOLLO0 */ 3536 /* DIV_APOLLO0 */
3524 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3537 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3525 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3538 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
@@ -3550,7 +3563,7 @@ static struct samsung_div_clock apollo_div_clks[] __initdata = {
3550 CLK_DIVIDER_READ_ONLY), 3563 CLK_DIVIDER_READ_ONLY),
3551}; 3564};
3552 3565
3553static struct samsung_gate_clock apollo_gate_clks[] __initdata = { 3566static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3554 /* ENABLE_ACLK_APOLLO */ 3567 /* ENABLE_ACLK_APOLLO */
3555 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3568 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3556 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3569 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
@@ -3589,28 +3602,64 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3589 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3602 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3590 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3603 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3591 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3604 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3592 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2",
3593 ENABLE_SCLK_APOLLO, 0,
3594 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3595}; 3605};
3596 3606
3597static struct samsung_cmu_info apollo_cmu_info __initdata = { 3607#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3598 .pll_clks = apollo_pll_clks, 3608 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3599 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), 3609 ((pclk) << 12) | ((aclk) << 8))
3600 .mux_clks = apollo_mux_clks, 3610
3601 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), 3611#define E5433_APOLLO_DIV1(hpm, copy) \
3602 .div_clks = apollo_div_clks, 3612 (((hpm) << 4) | ((copy) << 0))
3603 .nr_div_clks = ARRAY_SIZE(apollo_div_clks), 3613
3604 .gate_clks = apollo_gate_clks, 3614static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3605 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), 3615 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3606 .nr_clk_ids = APOLLO_NR_CLK, 3616 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3607 .clk_regs = apollo_clk_regs, 3617 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3608 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), 3618 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3619 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3620 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3621 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3622 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3623 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3624 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3625 { 0 },
3609}; 3626};
3610 3627
3611static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3628static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3612{ 3629{
3613 samsung_cmu_register_one(np, &apollo_cmu_info); 3630 void __iomem *reg_base;
3631 struct samsung_clk_provider *ctx;
3632
3633 reg_base = of_iomap(np, 0);
3634 if (!reg_base) {
3635 panic("%s: failed to map registers\n", __func__);
3636 return;
3637 }
3638
3639 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3640 if (!ctx) {
3641 panic("%s: unable to allocate ctx\n", __func__);
3642 return;
3643 }
3644
3645 samsung_clk_register_pll(ctx, apollo_pll_clks,
3646 ARRAY_SIZE(apollo_pll_clks), reg_base);
3647 samsung_clk_register_mux(ctx, apollo_mux_clks,
3648 ARRAY_SIZE(apollo_mux_clks));
3649 samsung_clk_register_div(ctx, apollo_div_clks,
3650 ARRAY_SIZE(apollo_div_clks));
3651 samsung_clk_register_gate(ctx, apollo_gate_clks,
3652 ARRAY_SIZE(apollo_gate_clks));
3653
3654 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3655 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3656 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3657 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3658
3659 samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3660 ARRAY_SIZE(apollo_clk_regs));
3661
3662 samsung_clk_of_add_provider(np, ctx);
3614} 3663}
3615CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3664CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3616 exynos5433_cmu_apollo_init); 3665 exynos5433_cmu_apollo_init);
@@ -3651,7 +3700,7 @@ CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3651#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3700#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3652#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3701#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3653 3702
3654static unsigned long atlas_clk_regs[] __initdata = { 3703static const unsigned long atlas_clk_regs[] __initconst = {
3655 ATLAS_PLL_LOCK, 3704 ATLAS_PLL_LOCK,
3656 ATLAS_PLL_CON0, 3705 ATLAS_PLL_CON0,
3657 ATLAS_PLL_CON1, 3706 ATLAS_PLL_CON1,
@@ -3686,15 +3735,16 @@ PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3686PNAME(mout_atlas_p) = { "mout_atlas_pll", 3735PNAME(mout_atlas_p) = { "mout_atlas_pll",
3687 "mout_bus_pll_atlas_user", }; 3736 "mout_bus_pll_atlas_user", };
3688 3737
3689static struct samsung_pll_clock atlas_pll_clks[] __initdata = { 3738static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3690 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3739 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3691 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), 3740 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3692}; 3741};
3693 3742
3694static struct samsung_mux_clock atlas_mux_clks[] __initdata = { 3743static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3695 /* MUX_SEL_ATLAS0 */ 3744 /* MUX_SEL_ATLAS0 */
3696 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3745 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3697 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), 3746 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3747 CLK_RECALC_NEW_RATES, 0),
3698 3748
3699 /* MUX_SEL_ATLAS1 */ 3749 /* MUX_SEL_ATLAS1 */
3700 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3750 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
@@ -3705,7 +3755,7 @@ static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3705 0, 1, CLK_SET_RATE_PARENT, 0), 3755 0, 1, CLK_SET_RATE_PARENT, 0),
3706}; 3756};
3707 3757
3708static struct samsung_div_clock atlas_div_clks[] __initdata = { 3758static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3709 /* DIV_ATLAS0 */ 3759 /* DIV_ATLAS0 */
3710 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3760 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3711 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3761 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
@@ -3736,7 +3786,7 @@ static struct samsung_div_clock atlas_div_clks[] __initdata = {
3736 CLK_DIVIDER_READ_ONLY), 3786 CLK_DIVIDER_READ_ONLY),
3737}; 3787};
3738 3788
3739static struct samsung_gate_clock atlas_gate_clks[] __initdata = { 3789static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3740 /* ENABLE_ACLK_ATLAS */ 3790 /* ENABLE_ACLK_ATLAS */
3741 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3791 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3742 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3792 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
@@ -3801,28 +3851,69 @@ static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3801 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3851 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3802 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3852 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3803 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3853 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3804 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3805 ENABLE_SCLK_ATLAS, 0,
3806 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3807}; 3854};
3808 3855
3809static struct samsung_cmu_info atlas_cmu_info __initdata = { 3856#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3810 .pll_clks = atlas_pll_clks, 3857 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3811 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), 3858 ((pclk) << 12) | ((aclk) << 8))
3812 .mux_clks = atlas_mux_clks, 3859
3813 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks), 3860#define E5433_ATLAS_DIV1(hpm, copy) \
3814 .div_clks = atlas_div_clks, 3861 (((hpm) << 4) | ((copy) << 0))
3815 .nr_div_clks = ARRAY_SIZE(atlas_div_clks), 3862
3816 .gate_clks = atlas_gate_clks, 3863static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3817 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), 3864 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3818 .nr_clk_ids = ATLAS_NR_CLK, 3865 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3819 .clk_regs = atlas_clk_regs, 3866 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3820 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), 3867 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3868 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3869 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3870 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3871 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3872 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3873 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3874 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3875 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3876 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3877 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3878 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3879 { 0 },
3821}; 3880};
3822 3881
3823static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3882static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3824{ 3883{
3825 samsung_cmu_register_one(np, &atlas_cmu_info); 3884 void __iomem *reg_base;
3885 struct samsung_clk_provider *ctx;
3886
3887 reg_base = of_iomap(np, 0);
3888 if (!reg_base) {
3889 panic("%s: failed to map registers\n", __func__);
3890 return;
3891 }
3892
3893 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3894 if (!ctx) {
3895 panic("%s: unable to allocate ctx\n", __func__);
3896 return;
3897 }
3898
3899 samsung_clk_register_pll(ctx, atlas_pll_clks,
3900 ARRAY_SIZE(atlas_pll_clks), reg_base);
3901 samsung_clk_register_mux(ctx, atlas_mux_clks,
3902 ARRAY_SIZE(atlas_mux_clks));
3903 samsung_clk_register_div(ctx, atlas_div_clks,
3904 ARRAY_SIZE(atlas_div_clks));
3905 samsung_clk_register_gate(ctx, atlas_gate_clks,
3906 ARRAY_SIZE(atlas_gate_clks));
3907
3908 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3909 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3910 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3911 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3912
3913 samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3914 ARRAY_SIZE(atlas_clk_regs));
3915
3916 samsung_clk_of_add_provider(np, ctx);
3826} 3917}
3827CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3918CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3828 exynos5433_cmu_atlas_init); 3919 exynos5433_cmu_atlas_init);
@@ -3853,7 +3944,7 @@ CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3853#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3944#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3854#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3945#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3855 3946
3856static unsigned long mscl_clk_regs[] __initdata = { 3947static const unsigned long mscl_clk_regs[] __initconst = {
3857 MUX_SEL_MSCL0, 3948 MUX_SEL_MSCL0,
3858 MUX_SEL_MSCL1, 3949 MUX_SEL_MSCL1,
3859 MUX_ENABLE_MSCL0, 3950 MUX_ENABLE_MSCL0,
@@ -3881,7 +3972,7 @@ PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3881PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 3972PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3882 "mout_aclk_mscl_400_user", }; 3973 "mout_aclk_mscl_400_user", };
3883 3974
3884static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 3975static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
3885 /* MUX_SEL_MSCL0 */ 3976 /* MUX_SEL_MSCL0 */
3886 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 3977 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3887 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 3978 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
@@ -3893,13 +3984,13 @@ static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3893 MUX_SEL_MSCL1, 0, 1), 3984 MUX_SEL_MSCL1, 0, 1),
3894}; 3985};
3895 3986
3896static struct samsung_div_clock mscl_div_clks[] __initdata = { 3987static const struct samsung_div_clock mscl_div_clks[] __initconst = {
3897 /* DIV_MSCL */ 3988 /* DIV_MSCL */
3898 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 3989 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3899 DIV_MSCL, 0, 3), 3990 DIV_MSCL, 0, 3),
3900}; 3991};
3901 3992
3902static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 3993static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
3903 /* ENABLE_ACLK_MSCL */ 3994 /* ENABLE_ACLK_MSCL */
3904 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 3995 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3905 ENABLE_ACLK_MSCL, 9, 0, 0), 3996 ENABLE_ACLK_MSCL, 9, 0, 0),
@@ -3977,7 +4068,7 @@ static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3977 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4068 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3978}; 4069};
3979 4070
3980static struct samsung_cmu_info mscl_cmu_info __initdata = { 4071static const struct samsung_cmu_info mscl_cmu_info __initconst = {
3981 .mux_clks = mscl_mux_clks, 4072 .mux_clks = mscl_mux_clks,
3982 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4073 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
3983 .div_clks = mscl_div_clks, 4074 .div_clks = mscl_div_clks,
@@ -4012,7 +4103,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4012#define ENABLE_IP_MFC1 0x0b04 4103#define ENABLE_IP_MFC1 0x0b04
4013#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4104#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4014 4105
4015static unsigned long mfc_clk_regs[] __initdata = { 4106static const unsigned long mfc_clk_regs[] __initconst = {
4016 MUX_SEL_MFC, 4107 MUX_SEL_MFC,
4017 MUX_ENABLE_MFC, 4108 MUX_ENABLE_MFC,
4018 DIV_MFC, 4109 DIV_MFC,
@@ -4027,19 +4118,19 @@ static unsigned long mfc_clk_regs[] __initdata = {
4027 4118
4028PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4119PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4029 4120
4030static struct samsung_mux_clock mfc_mux_clks[] __initdata = { 4121static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4031 /* MUX_SEL_MFC */ 4122 /* MUX_SEL_MFC */
4032 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4123 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4033 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4124 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4034}; 4125};
4035 4126
4036static struct samsung_div_clock mfc_div_clks[] __initdata = { 4127static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4037 /* DIV_MFC */ 4128 /* DIV_MFC */
4038 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4129 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4039 DIV_MFC, 0, 2), 4130 DIV_MFC, 0, 2),
4040}; 4131};
4041 4132
4042static struct samsung_gate_clock mfc_gate_clks[] __initdata = { 4133static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4043 /* ENABLE_ACLK_MFC */ 4134 /* ENABLE_ACLK_MFC */
4044 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4135 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4045 ENABLE_ACLK_MFC, 6, 0, 0), 4136 ENABLE_ACLK_MFC, 6, 0, 0),
@@ -4085,7 +4176,7 @@ static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4085 0, CLK_IGNORE_UNUSED, 0), 4176 0, CLK_IGNORE_UNUSED, 0),
4086}; 4177};
4087 4178
4088static struct samsung_cmu_info mfc_cmu_info __initdata = { 4179static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4089 .mux_clks = mfc_mux_clks, 4180 .mux_clks = mfc_mux_clks,
4090 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4181 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4091 .div_clks = mfc_div_clks, 4182 .div_clks = mfc_div_clks,
@@ -4120,7 +4211,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4120#define ENABLE_IP_HEVC1 0x0b04 4211#define ENABLE_IP_HEVC1 0x0b04
4121#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4212#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4122 4213
4123static unsigned long hevc_clk_regs[] __initdata = { 4214static const unsigned long hevc_clk_regs[] __initconst = {
4124 MUX_SEL_HEVC, 4215 MUX_SEL_HEVC,
4125 MUX_ENABLE_HEVC, 4216 MUX_ENABLE_HEVC,
4126 DIV_HEVC, 4217 DIV_HEVC,
@@ -4135,19 +4226,19 @@ static unsigned long hevc_clk_regs[] __initdata = {
4135 4226
4136PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4227PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4137 4228
4138static struct samsung_mux_clock hevc_mux_clks[] __initdata = { 4229static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4139 /* MUX_SEL_HEVC */ 4230 /* MUX_SEL_HEVC */
4140 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4231 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4141 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4232 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4142}; 4233};
4143 4234
4144static struct samsung_div_clock hevc_div_clks[] __initdata = { 4235static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4145 /* DIV_HEVC */ 4236 /* DIV_HEVC */
4146 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4237 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4147 DIV_HEVC, 0, 2), 4238 DIV_HEVC, 0, 2),
4148}; 4239};
4149 4240
4150static struct samsung_gate_clock hevc_gate_clks[] __initdata = { 4241static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4151 /* ENABLE_ACLK_HEVC */ 4242 /* ENABLE_ACLK_HEVC */
4152 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4243 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4153 ENABLE_ACLK_HEVC, 6, 0, 0), 4244 ENABLE_ACLK_HEVC, 6, 0, 0),
@@ -4195,7 +4286,7 @@ static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4195 0, CLK_IGNORE_UNUSED, 0), 4286 0, CLK_IGNORE_UNUSED, 0),
4196}; 4287};
4197 4288
4198static struct samsung_cmu_info hevc_cmu_info __initdata = { 4289static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4199 .mux_clks = hevc_mux_clks, 4290 .mux_clks = hevc_mux_clks,
4200 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4291 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4201 .div_clks = hevc_div_clks, 4292 .div_clks = hevc_div_clks,
@@ -4232,7 +4323,7 @@ CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4232#define ENABLE_IP_ISP2 0x0b08 4323#define ENABLE_IP_ISP2 0x0b08
4233#define ENABLE_IP_ISP3 0x0b0c 4324#define ENABLE_IP_ISP3 0x0b0c
4234 4325
4235static unsigned long isp_clk_regs[] __initdata = { 4326static const unsigned long isp_clk_regs[] __initconst = {
4236 MUX_SEL_ISP, 4327 MUX_SEL_ISP,
4237 MUX_ENABLE_ISP, 4328 MUX_ENABLE_ISP,
4238 DIV_ISP, 4329 DIV_ISP,
@@ -4250,7 +4341,7 @@ static unsigned long isp_clk_regs[] __initdata = {
4250PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4341PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4251PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4342PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4252 4343
4253static struct samsung_mux_clock isp_mux_clks[] __initdata = { 4344static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4254 /* MUX_SEL_ISP */ 4345 /* MUX_SEL_ISP */
4255 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4346 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4256 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4347 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
@@ -4258,7 +4349,7 @@ static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4258 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4349 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4259}; 4350};
4260 4351
4261static struct samsung_div_clock isp_div_clks[] __initdata = { 4352static const struct samsung_div_clock isp_div_clks[] __initconst = {
4262 /* DIV_ISP */ 4353 /* DIV_ISP */
4263 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4354 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4264 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4355 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
@@ -4270,7 +4361,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = {
4270 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4361 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4271}; 4362};
4272 4363
4273static struct samsung_gate_clock isp_gate_clks[] __initdata = { 4364static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4274 /* ENABLE_ACLK_ISP0 */ 4365 /* ENABLE_ACLK_ISP0 */
4275 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4366 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4276 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4367 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
@@ -4448,7 +4539,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4448 0, CLK_IGNORE_UNUSED, 0), 4539 0, CLK_IGNORE_UNUSED, 0),
4449}; 4540};
4450 4541
4451static struct samsung_cmu_info isp_cmu_info __initdata = { 4542static const struct samsung_cmu_info isp_cmu_info __initconst = {
4452 .mux_clks = isp_mux_clks, 4543 .mux_clks = isp_mux_clks,
4453 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4544 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4454 .div_clks = isp_div_clks, 4545 .div_clks = isp_div_clks,
@@ -4504,7 +4595,7 @@ CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4504#define ENABLE_IP_CAM02 0X0b08 4595#define ENABLE_IP_CAM02 0X0b08
4505#define ENABLE_IP_CAM03 0X0b0C 4596#define ENABLE_IP_CAM03 0X0b0C
4506 4597
4507static unsigned long cam0_clk_regs[] __initdata = { 4598static const unsigned long cam0_clk_regs[] __initconst = {
4508 MUX_SEL_CAM00, 4599 MUX_SEL_CAM00,
4509 MUX_SEL_CAM01, 4600 MUX_SEL_CAM01,
4510 MUX_SEL_CAM02, 4601 MUX_SEL_CAM02,
@@ -4588,14 +4679,14 @@ PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4588 "mout_aclk_cam0_552_user", 4679 "mout_aclk_cam0_552_user",
4589 "mout_aclk_cam0_400_user", }; 4680 "mout_aclk_cam0_400_user", };
4590 4681
4591static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = { 4682static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4592 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4683 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4593 NULL, 0, 100000000), 4684 NULL, 0, 100000000),
4594 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4685 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4595 NULL, 0, 100000000), 4686 NULL, 0, 100000000),
4596}; 4687};
4597 4688
4598static struct samsung_mux_clock cam0_mux_clks[] __initdata = { 4689static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4599 /* MUX_SEL_CAM00 */ 4690 /* MUX_SEL_CAM00 */
4600 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4691 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4601 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4692 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
@@ -4669,7 +4760,7 @@ static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4669 MUX_SEL_CAM04, 0, 1), 4760 MUX_SEL_CAM04, 0, 1),
4670}; 4761};
4671 4762
4672static struct samsung_div_clock cam0_div_clks[] __initdata = { 4763static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4673 /* DIV_CAM00 */ 4764 /* DIV_CAM00 */
4674 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4765 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4675 DIV_CAM00, 8, 2), 4766 DIV_CAM00, 8, 2),
@@ -4716,7 +4807,7 @@ static struct samsung_div_clock cam0_div_clks[] __initdata = {
4716 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4807 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4717}; 4808};
4718 4809
4719static struct samsung_gate_clock cam0_gate_clks[] __initdata = { 4810static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4720 /* ENABLE_ACLK_CAM00 */ 4811 /* ENABLE_ACLK_CAM00 */
4721 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4812 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4722 6, 0, 0), 4813 6, 0, 0),
@@ -4923,7 +5014,7 @@ static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
4923 ENABLE_SCLK_CAM0, 0, 0, 0), 5014 ENABLE_SCLK_CAM0, 0, 0, 0),
4924}; 5015};
4925 5016
4926static struct samsung_cmu_info cam0_cmu_info __initdata = { 5017static const struct samsung_cmu_info cam0_cmu_info __initconst = {
4927 .mux_clks = cam0_mux_clks, 5018 .mux_clks = cam0_mux_clks,
4928 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5019 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
4929 .div_clks = cam0_div_clks, 5020 .div_clks = cam0_div_clks,
@@ -4970,7 +5061,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
4970#define ENABLE_IP_CAM11 0X0b04 5061#define ENABLE_IP_CAM11 0X0b04
4971#define ENABLE_IP_CAM12 0X0b08 5062#define ENABLE_IP_CAM12 0X0b08
4972 5063
4973static unsigned long cam1_clk_regs[] __initdata = { 5064static const unsigned long cam1_clk_regs[] __initconst = {
4974 MUX_SEL_CAM10, 5065 MUX_SEL_CAM10,
4975 MUX_SEL_CAM11, 5066 MUX_SEL_CAM11,
4976 MUX_SEL_CAM12, 5067 MUX_SEL_CAM12,
@@ -5016,12 +5107,12 @@ PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5016PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5107PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5017 "mout_aclk_cam1_400_user", }; 5108 "mout_aclk_cam1_400_user", };
5018 5109
5019static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = { 5110static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5020 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5111 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5021 0, 100000000), 5112 0, 100000000),
5022}; 5113};
5023 5114
5024static struct samsung_mux_clock cam1_mux_clks[] __initdata = { 5115static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5025 /* MUX_SEL_CAM10 */ 5116 /* MUX_SEL_CAM10 */
5026 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5117 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5027 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5118 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
@@ -5057,7 +5148,7 @@ static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
5057 MUX_SEL_CAM12, 0, 1), 5148 MUX_SEL_CAM12, 0, 1),
5058}; 5149};
5059 5150
5060static struct samsung_div_clock cam1_div_clks[] __initdata = { 5151static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5061 /* DIV_CAM10 */ 5152 /* DIV_CAM10 */
5062 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5153 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5063 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5154 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
@@ -5081,7 +5172,7 @@ static struct samsung_div_clock cam1_div_clks[] __initdata = {
5081 DIV_CAM11, 0, 3), 5172 DIV_CAM11, 0, 3),
5082}; 5173};
5083 5174
5084static struct samsung_gate_clock cam1_gate_clks[] __initdata = { 5175static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5085 /* ENABLE_ACLK_CAM10 */ 5176 /* ENABLE_ACLK_CAM10 */
5086 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5177 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5087 ENABLE_ACLK_CAM10, 4, 0, 0), 5178 ENABLE_ACLK_CAM10, 4, 0, 0),
@@ -5296,7 +5387,7 @@ static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
5296 ENABLE_SCLK_CAM1, 0, 0, 0), 5387 ENABLE_SCLK_CAM1, 0, 0, 0),
5297}; 5388};
5298 5389
5299static struct samsung_cmu_info cam1_cmu_info __initdata = { 5390static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5300 .mux_clks = cam1_mux_clks, 5391 .mux_clks = cam1_mux_clks,
5301 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5392 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5302 .div_clks = cam1_div_clks, 5393 .div_clks = cam1_div_clks,
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index c57cff1e1798..a57d01b99b76 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -35,7 +35,7 @@ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initda
35}; 35};
36 36
37/* fixed rate clocks */ 37/* fixed rate clocks */
38static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { 38static const struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initconst = {
39 FRATE(0, "ppll", NULL, 0, 1000000000), 39 FRATE(0, "ppll", NULL, 0, 1000000000),
40 FRATE(0, "usb_phy0", NULL, 0, 60000000), 40 FRATE(0, "usb_phy0", NULL, 0, 60000000),
41 FRATE(0, "usb_phy1", NULL, 0, 60000000), 41 FRATE(0, "usb_phy1", NULL, 0, 60000000),
@@ -44,26 +44,26 @@ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata =
44}; 44};
45 45
46/* fixed factor clocks */ 46/* fixed factor clocks */
47static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { 47static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initconst = {
48 FFACTOR(0, "div250", "ppll", 1, 4, 0), 48 FFACTOR(0, "div250", "ppll", 1, 4, 0),
49 FFACTOR(0, "div200", "ppll", 1, 5, 0), 49 FFACTOR(0, "div200", "ppll", 1, 5, 0),
50 FFACTOR(0, "div125", "div250", 1, 2, 0), 50 FFACTOR(0, "div125", "div250", 1, 2, 0),
51}; 51};
52 52
53/* mux clocks */ 53/* mux clocks */
54static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { 54static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
55 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), 55 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
56 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, 56 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
57 CPU_CLK_STATUS, 0, 1, "armclk"), 57 CPU_CLK_STATUS, 0, 1, "armclk"),
58}; 58};
59 59
60/* divider clocks */ 60/* divider clocks */
61static struct samsung_div_clock exynos5440_div_clks[] __initdata = { 61static const struct samsung_div_clock exynos5440_div_clks[] __initconst = {
62 DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), 62 DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
63}; 63};
64 64
65/* gate clocks */ 65/* gate clocks */
66static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { 66static const struct samsung_gate_clock exynos5440_gate_clks[] __initconst = {
67 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), 67 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
68 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), 68 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
69 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), 69 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
@@ -125,8 +125,6 @@ static void __init exynos5440_clk_init(struct device_node *np)
125 } 125 }
126 126
127 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 127 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
128 if (!ctx)
129 panic("%s: unable to allocate context.\n", __func__);
130 128
131 samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, 129 samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
132 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); 130 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index ad68d463b12c..5931a4140c3d 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -36,7 +36,7 @@
36#define ENABLE_ACLK_TOPC1 0x0804 36#define ENABLE_ACLK_TOPC1 0x0804
37#define ENABLE_SCLK_TOPC1 0x0A04 37#define ENABLE_SCLK_TOPC1 0x0A04
38 38
39static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 39static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), 40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
41 FFACTOR(0, "ffac_topc_bus0_pll_div4", 41 FFACTOR(0, "ffac_topc_bus0_pll_div4",
42 "ffac_topc_bus0_pll_div2", 1, 2, 0), 42 "ffac_topc_bus0_pll_div2", 1, 2, 0),
@@ -69,7 +69,7 @@ PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
69PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", 69PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
70 "ffac_topc_bus0_pll_div2"}; 70 "ffac_topc_bus0_pll_div2"};
71 71
72static unsigned long topc_clk_regs[] __initdata = { 72static const unsigned long topc_clk_regs[] __initconst = {
73 CC_PLL_LOCK, 73 CC_PLL_LOCK,
74 BUS0_PLL_LOCK, 74 BUS0_PLL_LOCK,
75 BUS1_DPLL_LOCK, 75 BUS1_DPLL_LOCK,
@@ -89,7 +89,7 @@ static unsigned long topc_clk_regs[] __initdata = {
89 DIV_TOPC3, 89 DIV_TOPC3,
90}; 90};
91 91
92static struct samsung_mux_clock topc_mux_clks[] __initdata = { 92static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, 93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
94 MUX_SEL_TOPC0, 0, 1), 94 MUX_SEL_TOPC0, 0, 1),
95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, 95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
@@ -118,7 +118,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
119}; 119};
120 120
121static struct samsung_div_clock topc_div_clks[] __initdata = { 121static const struct samsung_div_clock topc_div_clks[] __initconst = {
122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
123 DIV_TOPC0, 4, 4), 123 DIV_TOPC0, 4, 4),
124 124
@@ -139,14 +139,14 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
139 DIV_TOPC3, 28, 4), 139 DIV_TOPC3, 28, 4),
140}; 140};
141 141
142static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 142static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
143 PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 143 PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
144 {}, 144 {},
145}; 145};
146 146
147static struct samsung_gate_clock topc_gate_clks[] __initdata = { 147static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", 148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
149 ENABLE_ACLK_TOPC0, 4, 0, 0), 149 ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
150 150
151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
152 ENABLE_ACLK_TOPC1, 20, 0, 0), 152 ENABLE_ACLK_TOPC1, 20, 0, 0),
@@ -174,7 +174,7 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
174 ENABLE_SCLK_TOPC1, 0, 0, 0), 174 ENABLE_SCLK_TOPC1, 0, 0, 0),
175}; 175};
176 176
177static struct samsung_pll_clock topc_pll_clks[] __initdata = { 177static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
179 BUS0_PLL_CON0, NULL), 179 BUS0_PLL_CON0, NULL),
180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
@@ -187,7 +187,7 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = {
187 AUD_PLL_CON0, pll1460x_24mhz_tbl), 187 AUD_PLL_CON0, pll1460x_24mhz_tbl),
188}; 188};
189 189
190static struct samsung_cmu_info topc_cmu_info __initdata = { 190static const struct samsung_cmu_info topc_cmu_info __initconst = {
191 .pll_clks = topc_pll_clks, 191 .pll_clks = topc_pll_clks,
192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
193 .mux_clks = topc_mux_clks, 193 .mux_clks = topc_mux_clks,
@@ -256,7 +256,7 @@ PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
256PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", 256PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
257 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; 257 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
258 258
259static unsigned long top0_clk_regs[] __initdata = { 259static const unsigned long top0_clk_regs[] __initconst = {
260 MUX_SEL_TOP00, 260 MUX_SEL_TOP00,
261 MUX_SEL_TOP01, 261 MUX_SEL_TOP01,
262 MUX_SEL_TOP03, 262 MUX_SEL_TOP03,
@@ -275,7 +275,7 @@ static unsigned long top0_clk_regs[] __initdata = {
275 ENABLE_SCLK_TOP0_PERIC3, 275 ENABLE_SCLK_TOP0_PERIC3,
276}; 276};
277 277
278static struct samsung_mux_clock top0_mux_clks[] __initdata = { 278static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
279 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, 279 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
280 MUX_SEL_TOP00, 0, 1), 280 MUX_SEL_TOP00, 0, 1),
281 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, 281 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
@@ -315,7 +315,7 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
315 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 315 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
316}; 316};
317 317
318static struct samsung_div_clock top0_div_clks[] __initdata = { 318static const struct samsung_div_clock top0_div_clks[] __initconst = {
319 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 319 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
320 DIV_TOP03, 12, 6), 320 DIV_TOP03, 12, 6),
321 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 321 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
@@ -338,7 +338,7 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
338 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 338 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
339}; 339};
340 340
341static struct samsung_gate_clock top0_gate_clks[] __initdata = { 341static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
342 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", 342 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), 343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
344 GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", 344 GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
@@ -372,7 +372,7 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
372 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 372 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
373}; 373};
374 374
375static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 375static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
376 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 376 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
377 1, 2, 0), 377 1, 2, 0),
378 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", 378 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
@@ -381,7 +381,7 @@ static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
381 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), 381 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
382}; 382};
383 383
384static struct samsung_cmu_info top0_cmu_info __initdata = { 384static const struct samsung_cmu_info top0_cmu_info __initconst = {
385 .mux_clks = top0_mux_clks, 385 .mux_clks = top0_mux_clks,
386 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 386 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
387 .div_clks = top0_div_clks, 387 .div_clks = top0_div_clks,
@@ -438,7 +438,7 @@ PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
438 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", 438 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
439 "mout_top1_mfc_pll_half"}; 439 "mout_top1_mfc_pll_half"};
440 440
441static unsigned long top1_clk_regs[] __initdata = { 441static const unsigned long top1_clk_regs[] __initconst = {
442 MUX_SEL_TOP10, 442 MUX_SEL_TOP10,
443 MUX_SEL_TOP11, 443 MUX_SEL_TOP11,
444 MUX_SEL_TOP13, 444 MUX_SEL_TOP13,
@@ -455,7 +455,7 @@ static unsigned long top1_clk_regs[] __initdata = {
455 ENABLE_SCLK_TOP1_FSYS11, 455 ENABLE_SCLK_TOP1_FSYS11,
456}; 456};
457 457
458static struct samsung_mux_clock top1_mux_clks[] __initdata = { 458static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
459 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, 459 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
460 MUX_SEL_TOP10, 4, 1), 460 MUX_SEL_TOP10, 4, 1),
461 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, 461 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
@@ -494,7 +494,7 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
494 MUX_SEL_TOP1_FSYS11, 24, 2), 494 MUX_SEL_TOP1_FSYS11, 24, 2),
495}; 495};
496 496
497static struct samsung_div_clock top1_div_clks[] __initdata = { 497static const struct samsung_div_clock top1_div_clks[] __initconst = {
498 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 498 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
499 DIV_TOP13, 24, 4), 499 DIV_TOP13, 24, 4),
500 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 500 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
@@ -521,7 +521,7 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
521 "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6), 521 "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
522}; 522};
523 523
524static struct samsung_gate_clock top1_gate_clks[] __initdata = { 524static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
525 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 525 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
526 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 526 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
527 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 527 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
@@ -539,7 +539,8 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
539 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 539 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
540 540
541 GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", 541 GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
542 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), 542 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
543 CLK_IS_CRITICAL, 0),
543 GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", 544 GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
544 ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), 545 ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
545 546
@@ -548,7 +549,7 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
548 24, CLK_SET_RATE_PARENT, 0), 549 24, CLK_SET_RATE_PARENT, 0),
549}; 550};
550 551
551static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 552static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
552 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 553 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
553 1, 2, 0), 554 1, 2, 0),
554 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", 555 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
@@ -557,7 +558,7 @@ static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
557 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), 558 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
558}; 559};
559 560
560static struct samsung_cmu_info top1_cmu_info __initdata = { 561static const struct samsung_cmu_info top1_cmu_info __initconst = {
561 .mux_clks = top1_mux_clks, 562 .mux_clks = top1_mux_clks,
562 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 563 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
563 .div_clks = top1_div_clks, 564 .div_clks = top1_div_clks,
@@ -591,22 +592,22 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
591 */ 592 */
592PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; 593PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
593 594
594static unsigned long ccore_clk_regs[] __initdata = { 595static const unsigned long ccore_clk_regs[] __initconst = {
595 MUX_SEL_CCORE, 596 MUX_SEL_CCORE,
596 ENABLE_PCLK_CCORE, 597 ENABLE_PCLK_CCORE,
597}; 598};
598 599
599static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 600static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
600 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, 601 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
601 MUX_SEL_CCORE, 1, 1), 602 MUX_SEL_CCORE, 1, 1),
602}; 603};
603 604
604static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 605static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
605 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 606 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
606 ENABLE_PCLK_CCORE, 8, 0, 0), 607 ENABLE_PCLK_CCORE, 8, 0, 0),
607}; 608};
608 609
609static struct samsung_cmu_info ccore_cmu_info __initdata = { 610static const struct samsung_cmu_info ccore_cmu_info __initconst = {
610 .mux_clks = ccore_mux_clks, 611 .mux_clks = ccore_mux_clks,
611 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 612 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
612 .gate_clks = ccore_gate_clks, 613 .gate_clks = ccore_gate_clks,
@@ -633,20 +634,20 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
633PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; 634PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
634PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; 635PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
635 636
636static unsigned long peric0_clk_regs[] __initdata = { 637static const unsigned long peric0_clk_regs[] __initconst = {
637 MUX_SEL_PERIC0, 638 MUX_SEL_PERIC0,
638 ENABLE_PCLK_PERIC0, 639 ENABLE_PCLK_PERIC0,
639 ENABLE_SCLK_PERIC0, 640 ENABLE_SCLK_PERIC0,
640}; 641};
641 642
642static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 643static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
643 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, 644 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
644 MUX_SEL_PERIC0, 0, 1), 645 MUX_SEL_PERIC0, 0, 1),
645 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, 646 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
646 MUX_SEL_PERIC0, 16, 1), 647 MUX_SEL_PERIC0, 16, 1),
647}; 648};
648 649
649static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 650static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
650 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 651 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
651 ENABLE_PCLK_PERIC0, 8, 0, 0), 652 ENABLE_PCLK_PERIC0, 8, 0, 0),
652 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 653 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
@@ -673,7 +674,7 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
673 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 674 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
674}; 675};
675 676
676static struct samsung_cmu_info peric0_cmu_info __initdata = { 677static const struct samsung_cmu_info peric0_cmu_info __initconst = {
677 .mux_clks = peric0_mux_clks, 678 .mux_clks = peric0_mux_clks,
678 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 679 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
679 .gate_clks = peric0_gate_clks, 680 .gate_clks = peric0_gate_clks,
@@ -709,7 +710,7 @@ PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
709PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; 710PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
710PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; 711PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
711 712
712static unsigned long peric1_clk_regs[] __initdata = { 713static const unsigned long peric1_clk_regs[] __initconst = {
713 MUX_SEL_PERIC10, 714 MUX_SEL_PERIC10,
714 MUX_SEL_PERIC11, 715 MUX_SEL_PERIC11,
715 MUX_SEL_PERIC12, 716 MUX_SEL_PERIC12,
@@ -717,7 +718,7 @@ static unsigned long peric1_clk_regs[] __initdata = {
717 ENABLE_SCLK_PERIC10, 718 ENABLE_SCLK_PERIC10,
718}; 719};
719 720
720static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 721static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
721 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, 722 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
722 MUX_SEL_PERIC10, 0, 1), 723 MUX_SEL_PERIC10, 0, 1),
723 724
@@ -739,7 +740,7 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
739 MUX_SEL_PERIC11, 28, 1), 740 MUX_SEL_PERIC11, 28, 1),
740}; 741};
741 742
742static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 743static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
743 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 744 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
744 ENABLE_PCLK_PERIC1, 4, 0, 0), 745 ENABLE_PCLK_PERIC1, 4, 0, 0),
745 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 746 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
@@ -797,7 +798,7 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
797 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 798 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
798}; 799};
799 800
800static struct samsung_cmu_info peric1_cmu_info __initdata = { 801static const struct samsung_cmu_info peric1_cmu_info __initconst = {
801 .mux_clks = peric1_mux_clks, 802 .mux_clks = peric1_mux_clks,
802 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 803 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
803 .gate_clks = peric1_gate_clks, 804 .gate_clks = peric1_gate_clks,
@@ -825,7 +826,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
825/* List of parent clocks for Muxes in CMU_PERIS */ 826/* List of parent clocks for Muxes in CMU_PERIS */
826PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; 827PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
827 828
828static unsigned long peris_clk_regs[] __initdata = { 829static const unsigned long peris_clk_regs[] __initconst = {
829 MUX_SEL_PERIS, 830 MUX_SEL_PERIS,
830 ENABLE_PCLK_PERIS, 831 ENABLE_PCLK_PERIS,
831 ENABLE_PCLK_PERIS_SECURE_CHIPID, 832 ENABLE_PCLK_PERIS_SECURE_CHIPID,
@@ -833,12 +834,12 @@ static unsigned long peris_clk_regs[] __initdata = {
833 ENABLE_SCLK_PERIS_SECURE_CHIPID, 834 ENABLE_SCLK_PERIS_SECURE_CHIPID,
834}; 835};
835 836
836static struct samsung_mux_clock peris_mux_clks[] __initdata = { 837static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
837 MUX(0, "mout_aclk_peris_66_user", 838 MUX(0, "mout_aclk_peris_66_user",
838 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), 839 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
839}; 840};
840 841
841static struct samsung_gate_clock peris_gate_clks[] __initdata = { 842static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
842 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 843 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
843 ENABLE_PCLK_PERIS, 6, 0, 0), 844 ENABLE_PCLK_PERIS, 6, 0, 0),
844 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 845 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
@@ -852,7 +853,7 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = {
852 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 853 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
853}; 854};
854 855
855static struct samsung_cmu_info peris_cmu_info __initdata = { 856static const struct samsung_cmu_info peris_cmu_info __initconst = {
856 .mux_clks = peris_mux_clks, 857 .mux_clks = peris_mux_clks,
857 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 858 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
858 .gate_clks = peris_gate_clks, 859 .gate_clks = peris_gate_clks,
@@ -893,12 +894,12 @@ PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
893 "phyclk_usbdrd300_udrd30_pipe_pclk" }; 894 "phyclk_usbdrd300_udrd30_pipe_pclk" };
894 895
895/* fixed rate clocks used in the FSYS0 block */ 896/* fixed rate clocks used in the FSYS0 block */
896static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 897static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
897 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), 898 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
898 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), 899 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
899}; 900};
900 901
901static unsigned long fsys0_clk_regs[] __initdata = { 902static const unsigned long fsys0_clk_regs[] __initconst = {
902 MUX_SEL_FSYS00, 903 MUX_SEL_FSYS00,
903 MUX_SEL_FSYS01, 904 MUX_SEL_FSYS01,
904 MUX_SEL_FSYS02, 905 MUX_SEL_FSYS02,
@@ -909,7 +910,7 @@ static unsigned long fsys0_clk_regs[] __initdata = {
909 ENABLE_SCLK_FSYS04, 910 ENABLE_SCLK_FSYS04,
910}; 911};
911 912
912static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 913static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
913 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, 914 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
914 MUX_SEL_FSYS00, 24, 1), 915 MUX_SEL_FSYS00, 24, 1),
915 916
@@ -926,7 +927,7 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
926 MUX_SEL_FSYS02, 28, 1), 927 MUX_SEL_FSYS02, 28, 1),
927}; 928};
928 929
929static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 930static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
930 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 931 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
931 ENABLE_ACLK_FSYS00, 3, 0, 0), 932 ENABLE_ACLK_FSYS00, 3, 0, 0),
932 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 933 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
@@ -960,7 +961,7 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
960 ENABLE_SCLK_FSYS04, 28, 0, 0), 961 ENABLE_SCLK_FSYS04, 28, 0, 0),
961}; 962};
962 963
963static struct samsung_cmu_info fsys0_cmu_info __initdata = { 964static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
964 .fixed_clks = fixed_rate_clks_fsys0, 965 .fixed_clks = fixed_rate_clks_fsys0,
965 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), 966 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
966 .mux_clks = fsys0_mux_clks, 967 .mux_clks = fsys0_mux_clks,
@@ -1005,7 +1006,7 @@ PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
1005PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; 1006PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
1006 1007
1007/* fixed rate clocks used in the FSYS1 block */ 1008/* fixed rate clocks used in the FSYS1 block */
1008static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { 1009static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
1009 FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, 1010 FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
1010 0, 300000000), 1011 0, 300000000),
1011 FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, 1012 FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
@@ -1014,7 +1015,7 @@ static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
1014 0, 300000000), 1015 0, 300000000),
1015}; 1016};
1016 1017
1017static unsigned long fsys1_clk_regs[] __initdata = { 1018static const unsigned long fsys1_clk_regs[] __initconst = {
1018 MUX_SEL_FSYS10, 1019 MUX_SEL_FSYS10,
1019 MUX_SEL_FSYS11, 1020 MUX_SEL_FSYS11,
1020 MUX_SEL_FSYS12, 1021 MUX_SEL_FSYS12,
@@ -1026,7 +1027,7 @@ static unsigned long fsys1_clk_regs[] __initdata = {
1026 ENABLE_SCLK_FSYS13, 1027 ENABLE_SCLK_FSYS13,
1027}; 1028};
1028 1029
1029static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 1030static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1030 MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1", 1031 MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
1031 mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2), 1032 mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
1032 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p, 1033 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
@@ -1049,12 +1050,12 @@ static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
1049 mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1), 1050 mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
1050}; 1051};
1051 1052
1052static struct samsung_div_clock fsys1_div_clks[] __initdata = { 1053static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1053 DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", 1054 DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
1054 DIV_FSYS1, 0, 2), 1055 DIV_FSYS1, 0, 2),
1055}; 1056};
1056 1057
1057static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 1058static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1058 GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user", 1059 GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
1059 "mout_sclk_ufsunipro20_user", 1060 "mout_sclk_ufsunipro20_user",
1060 ENABLE_SCLK_FSYS11, 20, 0, 0), 1061 ENABLE_SCLK_FSYS11, 20, 0, 0),
@@ -1089,7 +1090,7 @@ static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
1089 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), 1090 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
1090}; 1091};
1091 1092
1092static struct samsung_cmu_info fsys1_cmu_info __initdata = { 1093static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1093 .fixed_clks = fixed_rate_clks_fsys1, 1094 .fixed_clks = fixed_rate_clks_fsys1,
1094 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), 1095 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
1095 .mux_clks = fsys1_mux_clks, 1096 .mux_clks = fsys1_mux_clks,
@@ -1119,22 +1120,22 @@ CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
1119/* List of parent clocks for Muxes in CMU_MSCL */ 1120/* List of parent clocks for Muxes in CMU_MSCL */
1120PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 1121PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
1121 1122
1122static unsigned long mscl_clk_regs[] __initdata = { 1123static const unsigned long mscl_clk_regs[] __initconst = {
1123 MUX_SEL_MSCL, 1124 MUX_SEL_MSCL,
1124 DIV_MSCL, 1125 DIV_MSCL,
1125 ENABLE_ACLK_MSCL, 1126 ENABLE_ACLK_MSCL,
1126 ENABLE_PCLK_MSCL, 1127 ENABLE_PCLK_MSCL,
1127}; 1128};
1128 1129
1129static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 1130static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
1130 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 1131 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
1131 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 1132 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
1132}; 1133};
1133static struct samsung_div_clock mscl_div_clks[] __initdata = { 1134static const struct samsung_div_clock mscl_div_clks[] __initconst = {
1134 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 1135 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
1135 DIV_MSCL, 0, 3), 1136 DIV_MSCL, 0, 3),
1136}; 1137};
1137static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 1138static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
1138 1139
1139 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 1140 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
1140 ENABLE_ACLK_MSCL, 31, 0, 0), 1141 ENABLE_ACLK_MSCL, 31, 0, 0),
@@ -1204,7 +1205,7 @@ static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
1204 ENABLE_PCLK_MSCL, 20, 0, 0), 1205 ENABLE_PCLK_MSCL, 20, 0, 0),
1205}; 1206};
1206 1207
1207static struct samsung_cmu_info mscl_cmu_info __initdata = { 1208static const struct samsung_cmu_info mscl_cmu_info __initconst = {
1208 .mux_clks = mscl_mux_clks, 1209 .mux_clks = mscl_mux_clks,
1209 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 1210 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
1210 .div_clks = mscl_div_clks, 1211 .div_clks = mscl_div_clks,
@@ -1238,7 +1239,7 @@ CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1238PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1239PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1239PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1240PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1240 1241
1241static unsigned long aud_clk_regs[] __initdata = { 1242static const unsigned long aud_clk_regs[] __initconst = {
1242 MUX_SEL_AUD, 1243 MUX_SEL_AUD,
1243 DIV_AUD0, 1244 DIV_AUD0,
1244 DIV_AUD1, 1245 DIV_AUD1,
@@ -1247,13 +1248,13 @@ static unsigned long aud_clk_regs[] __initdata = {
1247 ENABLE_SCLK_AUD, 1248 ENABLE_SCLK_AUD,
1248}; 1249};
1249 1250
1250static struct samsung_mux_clock aud_mux_clks[] __initdata = { 1251static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
1251 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1252 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1252 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1253 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1253 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1254 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1254}; 1255};
1255 1256
1256static struct samsung_div_clock aud_div_clks[] __initdata = { 1257static const struct samsung_div_clock aud_div_clks[] __initconst = {
1257 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1258 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1258 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1259 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1259 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1260 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
@@ -1265,7 +1266,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = {
1265 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1266 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1266}; 1267};
1267 1268
1268static struct samsung_gate_clock aud_gate_clks[] __initdata = { 1269static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
1269 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1270 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1270 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1271 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1271 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1272 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
@@ -1293,7 +1294,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
1293 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1294 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1294}; 1295};
1295 1296
1296static struct samsung_cmu_info aud_cmu_info __initdata = { 1297static const struct samsung_cmu_info aud_cmu_info __initconst = {
1297 .mux_clks = aud_mux_clks, 1298 .mux_clks = aud_mux_clks,
1298 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1299 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
1299 .div_clks = aud_div_clks, 1300 .div_clks = aud_div_clks,
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b7dd396100d8..48139bd510f1 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -79,7 +79,7 @@ static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
79 u32 pll_con, mdiv, pdiv, sdiv; 79 u32 pll_con, mdiv, pdiv, sdiv;
80 u64 fvco = parent_rate; 80 u64 fvco = parent_rate;
81 81
82 pll_con = __raw_readl(pll->con_reg); 82 pll_con = readl_relaxed(pll->con_reg);
83 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; 83 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
84 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; 84 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
85 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; 85 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
@@ -112,7 +112,7 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
112 u32 pll_con, mdiv, pdiv, sdiv; 112 u32 pll_con, mdiv, pdiv, sdiv;
113 u64 fvco = parent_rate; 113 u64 fvco = parent_rate;
114 114
115 pll_con = __raw_readl(pll->con_reg); 115 pll_con = readl_relaxed(pll->con_reg);
116 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; 116 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
117 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; 117 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
118 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; 118 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
@@ -149,7 +149,7 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
149 u32 mdiv, pdiv, sdiv, pll_con; 149 u32 mdiv, pdiv, sdiv, pll_con;
150 u64 fvco = parent_rate; 150 u64 fvco = parent_rate;
151 151
152 pll_con = __raw_readl(pll->con_reg); 152 pll_con = readl_relaxed(pll->con_reg);
153 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 153 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
154 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 154 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
155 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; 155 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -186,19 +186,19 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
186 return -EINVAL; 186 return -EINVAL;
187 } 187 }
188 188
189 tmp = __raw_readl(pll->con_reg); 189 tmp = readl_relaxed(pll->con_reg);
190 190
191 if (!(samsung_pll35xx_mp_change(rate, tmp))) { 191 if (!(samsung_pll35xx_mp_change(rate, tmp))) {
192 /* If only s change, change just s value only*/ 192 /* If only s change, change just s value only*/
193 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); 193 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
194 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; 194 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
195 __raw_writel(tmp, pll->con_reg); 195 writel_relaxed(tmp, pll->con_reg);
196 196
197 return 0; 197 return 0;
198 } 198 }
199 199
200 /* Set PLL lock time. */ 200 /* Set PLL lock time. */
201 __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, 201 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
202 pll->lock_reg); 202 pll->lock_reg);
203 203
204 /* Change PLL PMS values */ 204 /* Change PLL PMS values */
@@ -208,12 +208,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
208 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | 208 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
209 (rate->pdiv << PLL35XX_PDIV_SHIFT) | 209 (rate->pdiv << PLL35XX_PDIV_SHIFT) |
210 (rate->sdiv << PLL35XX_SDIV_SHIFT); 210 (rate->sdiv << PLL35XX_SDIV_SHIFT);
211 __raw_writel(tmp, pll->con_reg); 211 writel_relaxed(tmp, pll->con_reg);
212 212
213 /* wait_lock_time */ 213 /* wait_lock_time */
214 do { 214 do {
215 cpu_relax(); 215 cpu_relax();
216 tmp = __raw_readl(pll->con_reg); 216 tmp = readl_relaxed(pll->con_reg);
217 } while (!(tmp & (PLL35XX_LOCK_STAT_MASK 217 } while (!(tmp & (PLL35XX_LOCK_STAT_MASK
218 << PLL35XX_LOCK_STAT_SHIFT))); 218 << PLL35XX_LOCK_STAT_SHIFT)));
219 return 0; 219 return 0;
@@ -253,8 +253,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
253 s16 kdiv; 253 s16 kdiv;
254 u64 fvco = parent_rate; 254 u64 fvco = parent_rate;
255 255
256 pll_con0 = __raw_readl(pll->con_reg); 256 pll_con0 = readl_relaxed(pll->con_reg);
257 pll_con1 = __raw_readl(pll->con_reg + 4); 257 pll_con1 = readl_relaxed(pll->con_reg + 4);
258 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 258 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
259 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 259 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
260 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; 260 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -294,20 +294,20 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
294 return -EINVAL; 294 return -EINVAL;
295 } 295 }
296 296
297 pll_con0 = __raw_readl(pll->con_reg); 297 pll_con0 = readl_relaxed(pll->con_reg);
298 pll_con1 = __raw_readl(pll->con_reg + 4); 298 pll_con1 = readl_relaxed(pll->con_reg + 4);
299 299
300 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { 300 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
301 /* If only s change, change just s value only*/ 301 /* If only s change, change just s value only*/
302 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); 302 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
303 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); 303 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
304 __raw_writel(pll_con0, pll->con_reg); 304 writel_relaxed(pll_con0, pll->con_reg);
305 305
306 return 0; 306 return 0;
307 } 307 }
308 308
309 /* Set PLL lock time. */ 309 /* Set PLL lock time. */
310 __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); 310 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
311 311
312 /* Change PLL PMS values */ 312 /* Change PLL PMS values */
313 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | 313 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
@@ -316,16 +316,16 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
316 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | 316 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
317 (rate->pdiv << PLL36XX_PDIV_SHIFT) | 317 (rate->pdiv << PLL36XX_PDIV_SHIFT) |
318 (rate->sdiv << PLL36XX_SDIV_SHIFT); 318 (rate->sdiv << PLL36XX_SDIV_SHIFT);
319 __raw_writel(pll_con0, pll->con_reg); 319 writel_relaxed(pll_con0, pll->con_reg);
320 320
321 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); 321 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
322 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; 322 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
323 __raw_writel(pll_con1, pll->con_reg + 4); 323 writel_relaxed(pll_con1, pll->con_reg + 4);
324 324
325 /* wait_lock_time */ 325 /* wait_lock_time */
326 do { 326 do {
327 cpu_relax(); 327 cpu_relax();
328 tmp = __raw_readl(pll->con_reg); 328 tmp = readl_relaxed(pll->con_reg);
329 } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); 329 } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
330 330
331 return 0; 331 return 0;
@@ -366,7 +366,7 @@ static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
366 u32 mdiv, pdiv, sdiv, pll_con; 366 u32 mdiv, pdiv, sdiv, pll_con;
367 u64 fvco = parent_rate; 367 u64 fvco = parent_rate;
368 368
369 pll_con = __raw_readl(pll->con_reg); 369 pll_con = readl_relaxed(pll->con_reg);
370 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 370 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
371 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 371 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
372 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; 372 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
@@ -409,14 +409,14 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
409 return -EINVAL; 409 return -EINVAL;
410 } 410 }
411 411
412 con0 = __raw_readl(pll->con_reg); 412 con0 = readl_relaxed(pll->con_reg);
413 con1 = __raw_readl(pll->con_reg + 0x4); 413 con1 = readl_relaxed(pll->con_reg + 0x4);
414 414
415 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { 415 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
416 /* If only s change, change just s value only*/ 416 /* If only s change, change just s value only*/
417 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); 417 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
418 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; 418 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
419 __raw_writel(con0, pll->con_reg); 419 writel_relaxed(con0, pll->con_reg);
420 420
421 return 0; 421 return 0;
422 } 422 }
@@ -430,29 +430,29 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
430 (rate->sdiv << PLL45XX_SDIV_SHIFT); 430 (rate->sdiv << PLL45XX_SDIV_SHIFT);
431 431
432 /* Set PLL AFC value. */ 432 /* Set PLL AFC value. */
433 con1 = __raw_readl(pll->con_reg + 0x4); 433 con1 = readl_relaxed(pll->con_reg + 0x4);
434 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); 434 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
435 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); 435 con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
436 436
437 /* Set PLL lock time. */ 437 /* Set PLL lock time. */
438 switch (pll->type) { 438 switch (pll->type) {
439 case pll_4502: 439 case pll_4502:
440 __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); 440 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
441 break; 441 break;
442 case pll_4508: 442 case pll_4508:
443 __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); 443 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
444 break; 444 break;
445 default: 445 default:
446 break; 446 break;
447 } 447 }
448 448
449 /* Set new configuration. */ 449 /* Set new configuration. */
450 __raw_writel(con1, pll->con_reg + 0x4); 450 writel_relaxed(con1, pll->con_reg + 0x4);
451 __raw_writel(con0, pll->con_reg); 451 writel_relaxed(con0, pll->con_reg);
452 452
453 /* Wait for locking. */ 453 /* Wait for locking. */
454 start = ktime_get(); 454 start = ktime_get();
455 while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) { 455 while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) {
456 ktime_t delta = ktime_sub(ktime_get(), start); 456 ktime_t delta = ktime_sub(ktime_get(), start);
457 457
458 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { 458 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -513,8 +513,8 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
513 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; 513 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
514 u64 fvco = parent_rate; 514 u64 fvco = parent_rate;
515 515
516 pll_con0 = __raw_readl(pll->con_reg); 516 pll_con0 = readl_relaxed(pll->con_reg);
517 pll_con1 = __raw_readl(pll->con_reg + 4); 517 pll_con1 = readl_relaxed(pll->con_reg + 4);
518 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? 518 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
519 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); 519 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
520 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 520 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
@@ -560,14 +560,14 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
560 return -EINVAL; 560 return -EINVAL;
561 } 561 }
562 562
563 con0 = __raw_readl(pll->con_reg); 563 con0 = readl_relaxed(pll->con_reg);
564 con1 = __raw_readl(pll->con_reg + 0x4); 564 con1 = readl_relaxed(pll->con_reg + 0x4);
565 565
566 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { 566 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
567 /* If only s change, change just s value only*/ 567 /* If only s change, change just s value only*/
568 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); 568 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
569 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; 569 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
570 __raw_writel(con0, pll->con_reg); 570 writel_relaxed(con0, pll->con_reg);
571 571
572 return 0; 572 return 0;
573 } 573 }
@@ -596,7 +596,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
596 (rate->sdiv << PLL46XX_SDIV_SHIFT); 596 (rate->sdiv << PLL46XX_SDIV_SHIFT);
597 597
598 /* Set PLL K, MFR and MRR values. */ 598 /* Set PLL K, MFR and MRR values. */
599 con1 = __raw_readl(pll->con_reg + 0x4); 599 con1 = readl_relaxed(pll->con_reg + 0x4);
600 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | 600 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
601 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | 601 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
602 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); 602 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
@@ -605,13 +605,13 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
605 (rate->mrr << PLL46XX_MRR_SHIFT); 605 (rate->mrr << PLL46XX_MRR_SHIFT);
606 606
607 /* Write configuration to PLL */ 607 /* Write configuration to PLL */
608 __raw_writel(lock, pll->lock_reg); 608 writel_relaxed(lock, pll->lock_reg);
609 __raw_writel(con0, pll->con_reg); 609 writel_relaxed(con0, pll->con_reg);
610 __raw_writel(con1, pll->con_reg + 0x4); 610 writel_relaxed(con1, pll->con_reg + 0x4);
611 611
612 /* Wait for locking. */ 612 /* Wait for locking. */
613 start = ktime_get(); 613 start = ktime_get();
614 while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) { 614 while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) {
615 ktime_t delta = ktime_sub(ktime_get(), start); 615 ktime_t delta = ktime_sub(ktime_get(), start);
616 616
617 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { 617 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -656,7 +656,7 @@ static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
656 u32 mdiv, pdiv, sdiv, pll_con; 656 u32 mdiv, pdiv, sdiv, pll_con;
657 u64 fvco = parent_rate; 657 u64 fvco = parent_rate;
658 658
659 pll_con = __raw_readl(pll->con_reg); 659 pll_con = readl_relaxed(pll->con_reg);
660 if (pll->type == pll_6552_s3c2416) { 660 if (pll->type == pll_6552_s3c2416) {
661 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; 661 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
662 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; 662 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
@@ -696,8 +696,8 @@ static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
696 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; 696 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
697 u64 fvco = parent_rate; 697 u64 fvco = parent_rate;
698 698
699 pll_con0 = __raw_readl(pll->con_reg); 699 pll_con0 = readl_relaxed(pll->con_reg);
700 pll_con1 = __raw_readl(pll->con_reg + 0x4); 700 pll_con1 = readl_relaxed(pll->con_reg + 0x4);
701 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; 701 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
702 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; 702 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
703 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; 703 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
@@ -734,7 +734,7 @@ static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
734 u32 pll_con, mdiv, pdiv, sdiv; 734 u32 pll_con, mdiv, pdiv, sdiv;
735 u64 fvco = parent_rate; 735 u64 fvco = parent_rate;
736 736
737 pll_con = __raw_readl(pll->con_reg); 737 pll_con = readl_relaxed(pll->con_reg);
738 mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK; 738 mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
739 pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK; 739 pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
740 sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; 740 sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
@@ -752,7 +752,7 @@ static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
752 u32 pll_con, mdiv, pdiv, sdiv; 752 u32 pll_con, mdiv, pdiv, sdiv;
753 u64 fvco = parent_rate; 753 u64 fvco = parent_rate;
754 754
755 pll_con = __raw_readl(pll->con_reg); 755 pll_con = readl_relaxed(pll->con_reg);
756 mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK; 756 mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
757 pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK; 757 pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
758 sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK; 758 sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
@@ -778,7 +778,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
778 return -EINVAL; 778 return -EINVAL;
779 } 779 }
780 780
781 tmp = __raw_readl(pll->con_reg); 781 tmp = readl_relaxed(pll->con_reg);
782 782
783 /* Change PLL PMS values */ 783 /* Change PLL PMS values */
784 tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) | 784 tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
@@ -787,7 +787,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
787 tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) | 787 tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
788 (rate->pdiv << PLLS3C2410_PDIV_SHIFT) | 788 (rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
789 (rate->sdiv << PLLS3C2410_SDIV_SHIFT); 789 (rate->sdiv << PLLS3C2410_SDIV_SHIFT);
790 __raw_writel(tmp, pll->con_reg); 790 writel_relaxed(tmp, pll->con_reg);
791 791
792 /* Time to settle according to the manual */ 792 /* Time to settle according to the manual */
793 udelay(300); 793 udelay(300);
@@ -798,7 +798,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
798static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable) 798static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
799{ 799{
800 struct samsung_clk_pll *pll = to_clk_pll(hw); 800 struct samsung_clk_pll *pll = to_clk_pll(hw);
801 u32 pll_en = __raw_readl(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); 801 u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
802 u32 pll_en_orig = pll_en; 802 u32 pll_en_orig = pll_en;
803 803
804 if (enable) 804 if (enable)
@@ -806,7 +806,7 @@ static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
806 else 806 else
807 pll_en |= BIT(bit); 807 pll_en |= BIT(bit);
808 808
809 __raw_writel(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); 809 writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
810 810
811 /* if we started the UPLL, then allow to settle */ 811 /* if we started the UPLL, then allow to settle */
812 if (enable && (pll_en_orig & BIT(bit))) 812 if (enable && (pll_en_orig & BIT(bit)))
@@ -905,7 +905,7 @@ static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
905 u32 r, p, m, s, pll_stat; 905 u32 r, p, m, s, pll_stat;
906 u64 fvco = parent_rate; 906 u64 fvco = parent_rate;
907 907
908 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3); 908 pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3);
909 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; 909 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
910 if (!r) 910 if (!r)
911 return 0; 911 return 0;
@@ -983,7 +983,7 @@ static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
983 u32 mdiv, pdiv, sdiv, pll_con; 983 u32 mdiv, pdiv, sdiv, pll_con;
984 u64 fvco = parent_rate; 984 u64 fvco = parent_rate;
985 985
986 pll_con = __raw_readl(pll->con_reg); 986 pll_con = readl_relaxed(pll->con_reg);
987 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 987 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
988 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 988 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
989 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; 989 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
@@ -1019,19 +1019,19 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
1019 return -EINVAL; 1019 return -EINVAL;
1020 } 1020 }
1021 1021
1022 tmp = __raw_readl(pll->con_reg); 1022 tmp = readl_relaxed(pll->con_reg);
1023 1023
1024 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { 1024 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
1025 /* If only s change, change just s value only*/ 1025 /* If only s change, change just s value only*/
1026 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); 1026 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
1027 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; 1027 tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
1028 __raw_writel(tmp, pll->con_reg); 1028 writel_relaxed(tmp, pll->con_reg);
1029 1029
1030 return 0; 1030 return 0;
1031 } 1031 }
1032 1032
1033 /* Set PLL lock time. */ 1033 /* Set PLL lock time. */
1034 __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); 1034 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
1035 1035
1036 /* Change PLL PMS values */ 1036 /* Change PLL PMS values */
1037 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | 1037 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
@@ -1040,12 +1040,12 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
1040 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | 1040 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
1041 (rate->pdiv << PLL2550XX_P_SHIFT) | 1041 (rate->pdiv << PLL2550XX_P_SHIFT) |
1042 (rate->sdiv << PLL2550XX_S_SHIFT); 1042 (rate->sdiv << PLL2550XX_S_SHIFT);
1043 __raw_writel(tmp, pll->con_reg); 1043 writel_relaxed(tmp, pll->con_reg);
1044 1044
1045 /* wait_lock_time */ 1045 /* wait_lock_time */
1046 do { 1046 do {
1047 cpu_relax(); 1047 cpu_relax();
1048 tmp = __raw_readl(pll->con_reg); 1048 tmp = readl_relaxed(pll->con_reg);
1049 } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK 1049 } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
1050 << PLL2550XX_LOCK_STAT_SHIFT))); 1050 << PLL2550XX_LOCK_STAT_SHIFT)));
1051 1051
@@ -1089,8 +1089,8 @@ static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
1089 s16 kdiv; 1089 s16 kdiv;
1090 u64 fvco = parent_rate; 1090 u64 fvco = parent_rate;
1091 1091
1092 pll_con0 = __raw_readl(pll->con_reg); 1092 pll_con0 = readl_relaxed(pll->con_reg);
1093 pll_con2 = __raw_readl(pll->con_reg + 8); 1093 pll_con2 = readl_relaxed(pll->con_reg + 8);
1094 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; 1094 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
1095 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; 1095 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
1096 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; 1096 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
@@ -1117,8 +1117,8 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
1117 return -EINVAL; 1117 return -EINVAL;
1118 } 1118 }
1119 1119
1120 pll_con0 = __raw_readl(pll->con_reg); 1120 pll_con0 = readl_relaxed(pll->con_reg);
1121 pll_con2 = __raw_readl(pll->con_reg + 8); 1121 pll_con2 = readl_relaxed(pll->con_reg + 8);
1122 1122
1123 /* Change PLL PMS values */ 1123 /* Change PLL PMS values */
1124 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | 1124 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
@@ -1135,13 +1135,13 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
1135 << PLL2650XX_KDIV_SHIFT; 1135 << PLL2650XX_KDIV_SHIFT;
1136 1136
1137 /* Set PLL lock time. */ 1137 /* Set PLL lock time. */
1138 __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); 1138 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
1139 1139
1140 __raw_writel(pll_con0, pll->con_reg); 1140 writel_relaxed(pll_con0, pll->con_reg);
1141 __raw_writel(pll_con2, pll->con_reg + 8); 1141 writel_relaxed(pll_con2, pll->con_reg + 8);
1142 1142
1143 do { 1143 do {
1144 tmp = __raw_readl(pll->con_reg); 1144 tmp = readl_relaxed(pll->con_reg);
1145 } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); 1145 } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
1146 1146
1147 return 0; 1147 return 0;
diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c
index ec6fb14d951c..ae9a595c72d0 100644
--- a/drivers/clk/samsung/clk-s3c2410-dclk.c
+++ b/drivers/clk/samsung/clk-s3c2410-dclk.c
@@ -428,8 +428,9 @@ MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
428 428
429static struct platform_driver s3c24xx_dclk_driver = { 429static struct platform_driver s3c24xx_dclk_driver = {
430 .driver = { 430 .driver = {
431 .name = "s3c24xx-dclk", 431 .name = "s3c24xx-dclk",
432 .pm = &s3c24xx_dclk_pm_ops, 432 .pm = &s3c24xx_dclk_pm_ops,
433 .suppress_bind_attrs = true,
433 }, 434 },
434 .probe = s3c24xx_dclk_probe, 435 .probe = s3c24xx_dclk_probe,
435 .remove = s3c24xx_dclk_remove, 436 .remove = s3c24xx_dclk_remove,
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index d7b011c1fcf8..d7a1e772d95a 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -374,8 +374,6 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
374 } 374 }
375 375
376 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 376 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
377 if (!ctx)
378 panic("%s: unable to allocate context.\n", __func__);
379 377
380 /* Register external clocks only in non-dt cases */ 378 /* Register external clocks only in non-dt cases */
381 if (!np) 379 if (!np)
diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
index effe3736ec6b..ec873ee15d37 100644
--- a/drivers/clk/samsung/clk-s3c2412.c
+++ b/drivers/clk/samsung/clk-s3c2412.c
@@ -265,8 +265,6 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
265 } 265 }
266 266
267 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 267 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
268 if (!ctx)
269 panic("%s: unable to allocate context.\n", __func__);
270 268
271 /* Register external clocks only in non-dt cases */ 269 /* Register external clocks only in non-dt cases */
272 if (!np) 270 if (!np)
diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index 37562783b25e..5e24a17e10e6 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -400,8 +400,6 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
400 } 400 }
401 401
402 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 402 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
403 if (!ctx)
404 panic("%s: unable to allocate context.\n", __func__);
405 403
406 /* Register external clocks only in non-dt cases */ 404 /* Register external clocks only in non-dt cases */
407 if (!np) 405 if (!np)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 60aa775bd374..a48bd5f17330 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -471,8 +471,6 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
471 } 471 }
472 472
473 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 473 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
474 if (!ctx)
475 panic("%s: unable to allocate context.\n", __func__);
476 474
477 /* Register external clocks. */ 475 /* Register external clocks. */
478 if (!np) 476 if (!np)
diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c
index eefb84b22566..c66ed2d1450e 100644
--- a/drivers/clk/samsung/clk-s5pv210-audss.c
+++ b/drivers/clk/samsung/clk-s5pv210-audss.c
@@ -18,7 +18,7 @@
18#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/syscore_ops.h> 20#include <linux/syscore_ops.h>
21#include <linux/module.h> 21#include <linux/init.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23 23
24#include <dt-bindings/clock/s5pv210-audss.h> 24#include <dt-bindings/clock/s5pv210-audss.h>
@@ -194,20 +194,6 @@ unregister:
194 return ret; 194 return ret;
195} 195}
196 196
197static int s5pv210_audss_clk_remove(struct platform_device *pdev)
198{
199 int i;
200
201 of_clk_del_provider(pdev->dev.of_node);
202
203 for (i = 0; i < clk_data.clk_num; i++) {
204 if (!IS_ERR(clk_table[i]))
205 clk_unregister(clk_table[i]);
206 }
207
208 return 0;
209}
210
211static const struct of_device_id s5pv210_audss_clk_of_match[] = { 197static const struct of_device_id s5pv210_audss_clk_of_match[] = {
212 { .compatible = "samsung,s5pv210-audss-clock", }, 198 { .compatible = "samsung,s5pv210-audss-clock", },
213 {}, 199 {},
@@ -216,10 +202,10 @@ static const struct of_device_id s5pv210_audss_clk_of_match[] = {
216static struct platform_driver s5pv210_audss_clk_driver = { 202static struct platform_driver s5pv210_audss_clk_driver = {
217 .driver = { 203 .driver = {
218 .name = "s5pv210-audss-clk", 204 .name = "s5pv210-audss-clk",
205 .suppress_bind_attrs = true,
219 .of_match_table = s5pv210_audss_clk_of_match, 206 .of_match_table = s5pv210_audss_clk_of_match,
220 }, 207 },
221 .probe = s5pv210_audss_clk_probe, 208 .probe = s5pv210_audss_clk_probe,
222 .remove = s5pv210_audss_clk_remove,
223}; 209};
224 210
225static int __init s5pv210_audss_clk_init(void) 211static int __init s5pv210_audss_clk_init(void)
@@ -227,14 +213,3 @@ static int __init s5pv210_audss_clk_init(void)
227 return platform_driver_register(&s5pv210_audss_clk_driver); 213 return platform_driver_register(&s5pv210_audss_clk_driver);
228} 214}
229core_initcall(s5pv210_audss_clk_init); 215core_initcall(s5pv210_audss_clk_init);
230
231static void __exit s5pv210_audss_clk_exit(void)
232{
233 platform_driver_unregister(&s5pv210_audss_clk_driver);
234}
235module_exit(s5pv210_audss_clk_exit);
236
237MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
238MODULE_DESCRIPTION("S5PV210 Audio Subsystem Clock Controller");
239MODULE_LICENSE("GPL v2");
240MODULE_ALIAS("platform:s5pv210-audss-clk");
diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c
index 52302262045d..fd2725710a6f 100644
--- a/drivers/clk/samsung/clk-s5pv210.c
+++ b/drivers/clk/samsung/clk-s5pv210.c
@@ -784,8 +784,6 @@ static void __init __s5pv210_clk_init(struct device_node *np,
784 struct samsung_clk_provider *ctx; 784 struct samsung_clk_provider *ctx;
785 785
786 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 786 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
787 if (!ctx)
788 panic("%s: unable to allocate context.\n", __func__);
789 787
790 samsung_clk_register_mux(ctx, early_mux_clks, 788 samsung_clk_register_mux(ctx, early_mux_clks,
791 ARRAY_SIZE(early_mux_clks)); 789 ARRAY_SIZE(early_mux_clks));
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index f38a6c49f744..b7d87d6db9dc 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -346,9 +346,9 @@ static struct syscore_ops samsung_clk_syscore_ops = {
346 .resume = samsung_clk_resume, 346 .resume = samsung_clk_resume,
347}; 347};
348 348
349static void samsung_clk_sleep_init(void __iomem *reg_base, 349void samsung_clk_sleep_init(void __iomem *reg_base,
350 const unsigned long *rdump, 350 const unsigned long *rdump,
351 unsigned long nr_rdump) 351 unsigned long nr_rdump)
352{ 352{
353 struct samsung_clock_reg_cache *reg_cache; 353 struct samsung_clock_reg_cache *reg_cache;
354 354
@@ -370,9 +370,9 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
370} 370}
371 371
372#else 372#else
373static void samsung_clk_sleep_init(void __iomem *reg_base, 373void samsung_clk_sleep_init(void __iomem *reg_base,
374 const unsigned long *rdump, 374 const unsigned long *rdump,
375 unsigned long nr_rdump) {} 375 unsigned long nr_rdump) {}
376#endif 376#endif
377 377
378/* 378/*
@@ -381,7 +381,7 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
381 */ 381 */
382struct samsung_clk_provider * __init samsung_cmu_register_one( 382struct samsung_clk_provider * __init samsung_cmu_register_one(
383 struct device_node *np, 383 struct device_node *np,
384 struct samsung_cmu_info *cmu) 384 const struct samsung_cmu_info *cmu)
385{ 385{
386 void __iomem *reg_base; 386 void __iomem *reg_base;
387 struct samsung_clk_provider *ctx; 387 struct samsung_clk_provider *ctx;
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index aa872d2c5105..da3bdebabf1e 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -261,7 +261,7 @@ struct samsung_gate_clock {
261#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \ 261#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
262 __GATE(_id, dname, cname, pname, o, b, f, gf, a) 262 __GATE(_id, dname, cname, pname, o, b, f, gf, a)
263 263
264#define PNAME(x) static const char *x[] __initdata 264#define PNAME(x) static const char * const x[] __initconst
265 265
266/** 266/**
267 * struct samsung_clk_reg_dump: register dump of clock controller registers. 267 * struct samsung_clk_reg_dump: register dump of clock controller registers.
@@ -330,28 +330,28 @@ struct samsung_clock_reg_cache {
330 330
331struct samsung_cmu_info { 331struct samsung_cmu_info {
332 /* list of pll clocks and respective count */ 332 /* list of pll clocks and respective count */
333 struct samsung_pll_clock *pll_clks; 333 const struct samsung_pll_clock *pll_clks;
334 unsigned int nr_pll_clks; 334 unsigned int nr_pll_clks;
335 /* list of mux clocks and respective count */ 335 /* list of mux clocks and respective count */
336 struct samsung_mux_clock *mux_clks; 336 const struct samsung_mux_clock *mux_clks;
337 unsigned int nr_mux_clks; 337 unsigned int nr_mux_clks;
338 /* list of div clocks and respective count */ 338 /* list of div clocks and respective count */
339 struct samsung_div_clock *div_clks; 339 const struct samsung_div_clock *div_clks;
340 unsigned int nr_div_clks; 340 unsigned int nr_div_clks;
341 /* list of gate clocks and respective count */ 341 /* list of gate clocks and respective count */
342 struct samsung_gate_clock *gate_clks; 342 const struct samsung_gate_clock *gate_clks;
343 unsigned int nr_gate_clks; 343 unsigned int nr_gate_clks;
344 /* list of fixed clocks and respective count */ 344 /* list of fixed clocks and respective count */
345 struct samsung_fixed_rate_clock *fixed_clks; 345 const struct samsung_fixed_rate_clock *fixed_clks;
346 unsigned int nr_fixed_clks; 346 unsigned int nr_fixed_clks;
347 /* list of fixed factor clocks and respective count */ 347 /* list of fixed factor clocks and respective count */
348 struct samsung_fixed_factor_clock *fixed_factor_clks; 348 const struct samsung_fixed_factor_clock *fixed_factor_clks;
349 unsigned int nr_fixed_factor_clks; 349 unsigned int nr_fixed_factor_clks;
350 /* total number of clocks with IDs assigned*/ 350 /* total number of clocks with IDs assigned*/
351 unsigned int nr_clk_ids; 351 unsigned int nr_clk_ids;
352 352
353 /* list and number of clocks registers */ 353 /* list and number of clocks registers */
354 unsigned long *clk_regs; 354 const unsigned long *clk_regs;
355 unsigned int nr_clk_regs; 355 unsigned int nr_clk_regs;
356}; 356};
357 357
@@ -395,10 +395,14 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
395 395
396extern struct samsung_clk_provider __init *samsung_cmu_register_one( 396extern struct samsung_clk_provider __init *samsung_cmu_register_one(
397 struct device_node *, 397 struct device_node *,
398 struct samsung_cmu_info *); 398 const struct samsung_cmu_info *);
399 399
400extern unsigned long _get_rate(const char *clk_name); 400extern unsigned long _get_rate(const char *clk_name);
401 401
402extern void samsung_clk_sleep_init(void __iomem *reg_base,
403 const unsigned long *rdump,
404 unsigned long nr_rdump);
405
402extern void samsung_clk_save(void __iomem *base, 406extern void samsung_clk_save(void __iomem *base,
403 struct samsung_clk_reg_dump *rd, 407 struct samsung_clk_reg_dump *rd,
404 unsigned int num_regs); 408 unsigned int num_regs);
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 627267c7ec5c..546bd79c8e3a 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -267,7 +267,6 @@ static void __init st_of_flexgen_setup(struct device_node *np)
267 const char **parents; 267 const char **parents;
268 int num_parents, i; 268 int num_parents, i;
269 spinlock_t *rlock = NULL; 269 spinlock_t *rlock = NULL;
270 unsigned long flex_flags = 0;
271 int ret; 270 int ret;
272 271
273 pnode = of_get_parent(np); 272 pnode = of_get_parent(np);
@@ -308,12 +307,15 @@ static void __init st_of_flexgen_setup(struct device_node *np)
308 for (i = 0; i < clk_data->clk_num; i++) { 307 for (i = 0; i < clk_data->clk_num; i++) {
309 struct clk *clk; 308 struct clk *clk;
310 const char *clk_name; 309 const char *clk_name;
310 unsigned long flex_flags = 0;
311 311
312 if (of_property_read_string_index(np, "clock-output-names", 312 if (of_property_read_string_index(np, "clock-output-names",
313 i, &clk_name)) { 313 i, &clk_name)) {
314 break; 314 break;
315 } 315 }
316 316
317 of_clk_detect_critical(np, i, &flex_flags);
318
317 /* 319 /*
318 * If we read an empty clock name then the output is unused 320 * If we read an empty clock name then the output is unused
319 */ 321 */
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dec4eaaecc00..09afeb85109c 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -1027,7 +1027,7 @@ static const struct clk_ops st_quadfs_ops = {
1027static struct clk * __init st_clk_register_quadfs_fsynth( 1027static struct clk * __init st_clk_register_quadfs_fsynth(
1028 const char *name, const char *parent_name, 1028 const char *name, const char *parent_name,
1029 struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, 1029 struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan,
1030 spinlock_t *lock) 1030 unsigned long flags, spinlock_t *lock)
1031{ 1031{
1032 struct st_clk_quadfs_fsynth *fs; 1032 struct st_clk_quadfs_fsynth *fs;
1033 struct clk *clk; 1033 struct clk *clk;
@@ -1045,7 +1045,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
1045 1045
1046 init.name = name; 1046 init.name = name;
1047 init.ops = &st_quadfs_ops; 1047 init.ops = &st_quadfs_ops;
1048 init.flags = CLK_GET_RATE_NOCACHE | CLK_IS_BASIC; 1048 init.flags = flags | CLK_GET_RATE_NOCACHE | CLK_IS_BASIC;
1049 init.parent_names = &parent_name; 1049 init.parent_names = &parent_name;
1050 init.num_parents = 1; 1050 init.num_parents = 1;
1051 1051
@@ -1115,6 +1115,7 @@ static void __init st_of_create_quadfs_fsynths(
1115 for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { 1115 for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) {
1116 struct clk *clk; 1116 struct clk *clk;
1117 const char *clk_name; 1117 const char *clk_name;
1118 unsigned long flags = 0;
1118 1119
1119 if (of_property_read_string_index(np, "clock-output-names", 1120 if (of_property_read_string_index(np, "clock-output-names",
1120 fschan, &clk_name)) { 1121 fschan, &clk_name)) {
@@ -1127,8 +1128,11 @@ static void __init st_of_create_quadfs_fsynths(
1127 if (*clk_name == '\0') 1128 if (*clk_name == '\0')
1128 continue; 1129 continue;
1129 1130
1131 of_clk_detect_critical(np, fschan, &flags);
1132
1130 clk = st_clk_register_quadfs_fsynth(clk_name, pll_name, 1133 clk = st_clk_register_quadfs_fsynth(clk_name, pll_name,
1131 quadfs, reg, fschan, lock); 1134 quadfs, reg, fschan,
1135 flags, lock);
1132 1136
1133 /* 1137 /*
1134 * If there was an error registering this clock output, clean 1138 * If there was an error registering this clock output, clean
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 38f6f3a9098e..0b5990e82e0d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -840,7 +840,7 @@ static const struct clk_ops stm_pll4600c28_ops = {
840 840
841static struct clk * __init clkgen_pll_register(const char *parent_name, 841static struct clk * __init clkgen_pll_register(const char *parent_name,
842 struct clkgen_pll_data *pll_data, 842 struct clkgen_pll_data *pll_data,
843 void __iomem *reg, 843 void __iomem *reg, unsigned long pll_flags,
844 const char *clk_name, spinlock_t *lock) 844 const char *clk_name, spinlock_t *lock)
845{ 845{
846 struct clkgen_pll *pll; 846 struct clkgen_pll *pll;
@@ -854,7 +854,7 @@ static struct clk * __init clkgen_pll_register(const char *parent_name,
854 init.name = clk_name; 854 init.name = clk_name;
855 init.ops = pll_data->ops; 855 init.ops = pll_data->ops;
856 856
857 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE; 857 init.flags = pll_flags | CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
858 init.parent_names = &parent_name; 858 init.parent_names = &parent_name;
859 init.num_parents = 1; 859 init.num_parents = 1;
860 860
@@ -948,7 +948,7 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
948 */ 948 */
949 clk_data->clks[0] = clkgen_pll_register(parent_name, 949 clk_data->clks[0] = clkgen_pll_register(parent_name,
950 (struct clkgen_pll_data *) &st_pll1600c65_ax, 950 (struct clkgen_pll_data *) &st_pll1600c65_ax,
951 reg + CLKGENAx_PLL0_OFFSET, clk_name, NULL); 951 reg + CLKGENAx_PLL0_OFFSET, 0, clk_name, NULL);
952 952
953 if (IS_ERR(clk_data->clks[0])) 953 if (IS_ERR(clk_data->clks[0]))
954 goto err; 954 goto err;
@@ -977,7 +977,7 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
977 */ 977 */
978 clk_data->clks[2] = clkgen_pll_register(parent_name, 978 clk_data->clks[2] = clkgen_pll_register(parent_name,
979 (struct clkgen_pll_data *) &st_pll800c65_ax, 979 (struct clkgen_pll_data *) &st_pll800c65_ax,
980 reg + CLKGENAx_PLL1_OFFSET, clk_name, NULL); 980 reg + CLKGENAx_PLL1_OFFSET, 0, clk_name, NULL);
981 981
982 if (IS_ERR(clk_data->clks[2])) 982 if (IS_ERR(clk_data->clks[2]))
983 goto err; 983 goto err;
@@ -995,7 +995,7 @@ CLK_OF_DECLARE(clkgena_c65_plls,
995static struct clk * __init clkgen_odf_register(const char *parent_name, 995static struct clk * __init clkgen_odf_register(const char *parent_name,
996 void __iomem *reg, 996 void __iomem *reg,
997 struct clkgen_pll_data *pll_data, 997 struct clkgen_pll_data *pll_data,
998 int odf, 998 unsigned long pll_flags, int odf,
999 spinlock_t *odf_lock, 999 spinlock_t *odf_lock,
1000 const char *odf_name) 1000 const char *odf_name)
1001{ 1001{
@@ -1004,7 +1004,7 @@ static struct clk * __init clkgen_odf_register(const char *parent_name,
1004 struct clk_gate *gate; 1004 struct clk_gate *gate;
1005 struct clk_divider *div; 1005 struct clk_divider *div;
1006 1006
1007 flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT; 1007 flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT;
1008 1008
1009 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 1009 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1010 if (!gate) 1010 if (!gate)
@@ -1099,6 +1099,7 @@ static void __init clkgen_c32_pll_setup(struct device_node *np)
1099 int num_odfs, odf; 1099 int num_odfs, odf;
1100 struct clk_onecell_data *clk_data; 1100 struct clk_onecell_data *clk_data;
1101 struct clkgen_pll_data *data; 1101 struct clkgen_pll_data *data;
1102 unsigned long pll_flags = 0;
1102 1103
1103 match = of_match_node(c32_pll_of_match, np); 1104 match = of_match_node(c32_pll_of_match, np);
1104 if (!match) { 1105 if (!match) {
@@ -1116,8 +1117,10 @@ static void __init clkgen_c32_pll_setup(struct device_node *np)
1116 if (!pll_base) 1117 if (!pll_base)
1117 return; 1118 return;
1118 1119
1119 clk = clkgen_pll_register(parent_name, data, pll_base, np->name, 1120 of_clk_detect_critical(np, 0, &pll_flags);
1120 data->lock); 1121
1122 clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
1123 np->name, data->lock);
1121 if (IS_ERR(clk)) 1124 if (IS_ERR(clk))
1122 return; 1125 return;
1123 1126
@@ -1139,12 +1142,15 @@ static void __init clkgen_c32_pll_setup(struct device_node *np)
1139 for (odf = 0; odf < num_odfs; odf++) { 1142 for (odf = 0; odf < num_odfs; odf++) {
1140 struct clk *clk; 1143 struct clk *clk;
1141 const char *clk_name; 1144 const char *clk_name;
1145 unsigned long odf_flags = 0;
1142 1146
1143 if (of_property_read_string_index(np, "clock-output-names", 1147 if (of_property_read_string_index(np, "clock-output-names",
1144 odf, &clk_name)) 1148 odf, &clk_name))
1145 return; 1149 return;
1146 1150
1147 clk = clkgen_odf_register(pll_name, pll_base, data, 1151 of_clk_detect_critical(np, odf, &odf_flags);
1152
1153 clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
1148 odf, &clkgena_c32_odf_lock, clk_name); 1154 odf, &clkgena_c32_odf_lock, clk_name);
1149 if (IS_ERR(clk)) 1155 if (IS_ERR(clk))
1150 goto err; 1156 goto err;
@@ -1206,7 +1212,8 @@ static void __init clkgengpu_c32_pll_setup(struct device_node *np)
1206 /* 1212 /*
1207 * PLL 1200MHz output 1213 * PLL 1200MHz output
1208 */ 1214 */
1209 clk = clkgen_pll_register(parent_name, data, reg, clk_name, data->lock); 1215 clk = clkgen_pll_register(parent_name, data, reg,
1216 0, clk_name, data->lock);
1210 1217
1211 if (!IS_ERR(clk)) 1218 if (!IS_ERR(clk))
1212 of_clk_add_provider(np, of_clk_src_simple_get, clk); 1219 of_clk_add_provider(np, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
new file mode 100644
index 000000000000..2afcbd39e41e
--- /dev/null
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -0,0 +1,65 @@
1config SUNXI_CCU
2 bool "Clock support for Allwinner SoCs"
3 default ARCH_SUNXI
4
5if SUNXI_CCU
6
7# Base clock types
8
9config SUNXI_CCU_DIV
10 bool
11 select SUNXI_CCU_MUX
12
13config SUNXI_CCU_FRAC
14 bool
15
16config SUNXI_CCU_GATE
17 bool
18
19config SUNXI_CCU_MUX
20 bool
21
22config SUNXI_CCU_PHASE
23 bool
24
25# Multi-factor clocks
26
27config SUNXI_CCU_NK
28 bool
29 select SUNXI_CCU_GATE
30
31config SUNXI_CCU_NKM
32 bool
33 select RATIONAL
34 select SUNXI_CCU_GATE
35
36config SUNXI_CCU_NKMP
37 bool
38 select RATIONAL
39 select SUNXI_CCU_GATE
40
41config SUNXI_CCU_NM
42 bool
43 select RATIONAL
44 select SUNXI_CCU_FRAC
45 select SUNXI_CCU_GATE
46
47config SUNXI_CCU_MP
48 bool
49 select SUNXI_CCU_GATE
50 select SUNXI_CCU_MUX
51
52# SoC Drivers
53
54config SUN8I_H3_CCU
55 bool "Support for the Allwinner H3 CCU"
56 select SUNXI_CCU_DIV
57 select SUNXI_CCU_NK
58 select SUNXI_CCU_NKM
59 select SUNXI_CCU_NKMP
60 select SUNXI_CCU_NM
61 select SUNXI_CCU_MP
62 select SUNXI_CCU_PHASE
63 default MACH_SUN8I
64
65endif
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
new file mode 100644
index 000000000000..633ce642ffae
--- /dev/null
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -0,0 +1,20 @@
1# Common objects
2obj-$(CONFIG_SUNXI_CCU) += ccu_common.o
3obj-$(CONFIG_SUNXI_CCU) += ccu_reset.o
4
5# Base clock types
6obj-$(CONFIG_SUNXI_CCU_DIV) += ccu_div.o
7obj-$(CONFIG_SUNXI_CCU_FRAC) += ccu_frac.o
8obj-$(CONFIG_SUNXI_CCU_GATE) += ccu_gate.o
9obj-$(CONFIG_SUNXI_CCU_MUX) += ccu_mux.o
10obj-$(CONFIG_SUNXI_CCU_PHASE) += ccu_phase.o
11
12# Multi-factor clocks
13obj-$(CONFIG_SUNXI_CCU_NK) += ccu_nk.o
14obj-$(CONFIG_SUNXI_CCU_NKM) += ccu_nkm.o
15obj-$(CONFIG_SUNXI_CCU_NKMP) += ccu_nkmp.o
16obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o
17obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
18
19# SoC support
20obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
new file mode 100644
index 000000000000..9af359544110
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -0,0 +1,826 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16
17#include "ccu_common.h"
18#include "ccu_reset.h"
19
20#include "ccu_div.h"
21#include "ccu_gate.h"
22#include "ccu_mp.h"
23#include "ccu_mult.h"
24#include "ccu_nk.h"
25#include "ccu_nkm.h"
26#include "ccu_nkmp.h"
27#include "ccu_nm.h"
28#include "ccu_phase.h"
29
30#include "ccu-sun8i-h3.h"
31
32static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
33 "osc24M", 0x000,
34 8, 5, /* N */
35 4, 2, /* K */
36 0, 2, /* M */
37 16, 2, /* P */
38 BIT(31), /* gate */
39 BIT(28), /* lock */
40 0);
41
42/*
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * the base (2x, 4x and 8x), and one variable divider (the one true
45 * pll audio).
46 *
47 * We don't have any need for the variable divider for now, so we just
48 * hardcode it to match with the clock names
49 */
50#define SUN8I_H3_PLL_AUDIO_REG 0x008
51
52static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
53 "osc24M", 0x008,
54 8, 7, /* N */
55 0, 5, /* M */
56 BIT(31), /* gate */
57 BIT(28), /* lock */
58 0);
59
60static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
61 "osc24M", 0x0010,
62 8, 7, /* N */
63 0, 4, /* M */
64 BIT(24), /* frac enable */
65 BIT(25), /* frac select */
66 270000000, /* frac rate 0 */
67 297000000, /* frac rate 1 */
68 BIT(31), /* gate */
69 BIT(28), /* lock */
70 0);
71
72static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
73 "osc24M", 0x0018,
74 8, 7, /* N */
75 0, 4, /* M */
76 BIT(24), /* frac enable */
77 BIT(25), /* frac select */
78 270000000, /* frac rate 0 */
79 297000000, /* frac rate 1 */
80 BIT(31), /* gate */
81 BIT(28), /* lock */
82 0);
83
84static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
85 "osc24M", 0x020,
86 8, 5, /* N */
87 4, 2, /* K */
88 0, 2, /* M */
89 BIT(31), /* gate */
90 BIT(28), /* lock */
91 0);
92
93static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
94 "osc24M", 0x028,
95 8, 5, /* N */
96 4, 2, /* K */
97 BIT(31), /* gate */
98 BIT(28), /* lock */
99 2, /* post-div */
100 0);
101
102static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
103 "osc24M", 0x0038,
104 8, 7, /* N */
105 0, 4, /* M */
106 BIT(24), /* frac enable */
107 BIT(25), /* frac select */
108 270000000, /* frac rate 0 */
109 297000000, /* frac rate 1 */
110 BIT(31), /* gate */
111 BIT(28), /* lock */
112 0);
113
114static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
115 "osc24M", 0x044,
116 8, 5, /* N */
117 4, 2, /* K */
118 BIT(31), /* gate */
119 BIT(28), /* lock */
120 2, /* post-div */
121 0);
122
123static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
124 "osc24M", 0x0048,
125 8, 7, /* N */
126 0, 4, /* M */
127 BIT(24), /* frac enable */
128 BIT(25), /* frac select */
129 270000000, /* frac rate 0 */
130 297000000, /* frac rate 1 */
131 BIT(31), /* gate */
132 BIT(28), /* lock */
133 0);
134
135static const char * const cpux_parents[] = { "osc32k", "osc24M",
136 "pll-cpux" , "pll-cpux" };
137static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
138 0x050, 16, 2, CLK_IS_CRITICAL);
139
140static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
141
142static const char * const ahb1_parents[] = { "osc32k", "osc24M",
143 "axi" , "pll-periph0" };
144static struct ccu_div ahb1_clk = {
145 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
146
147 .mux = {
148 .shift = 12,
149 .width = 2,
150
151 .variable_prediv = {
152 .index = 3,
153 .shift = 6,
154 .width = 2,
155 },
156 },
157
158 .common = {
159 .reg = 0x054,
160 .features = CCU_FEATURE_VARIABLE_PREDIV,
161 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
162 ahb1_parents,
163 &ccu_div_ops,
164 0),
165 },
166};
167
168static struct clk_div_table apb1_div_table[] = {
169 { .val = 0, .div = 2 },
170 { .val = 1, .div = 2 },
171 { .val = 2, .div = 4 },
172 { .val = 3, .div = 8 },
173 { /* Sentinel */ },
174};
175static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
176 0x054, 8, 2, apb1_div_table, 0);
177
178static const char * const apb2_parents[] = { "osc32k", "osc24M",
179 "pll-periph0" , "pll-periph0" };
180static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
181 0, 5, /* M */
182 16, 2, /* P */
183 24, 2, /* mux */
184 0);
185
186static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
187static struct ccu_mux ahb2_clk = {
188 .mux = {
189 .shift = 0,
190 .width = 1,
191
192 .fixed_prediv = {
193 .index = 1,
194 .div = 2,
195 },
196 },
197
198 .common = {
199 .reg = 0x05c,
200 .features = CCU_FEATURE_FIXED_PREDIV,
201 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
202 ahb2_parents,
203 &ccu_mux_ops,
204 0),
205 },
206};
207
208static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
209 0x060, BIT(5), 0);
210static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
211 0x060, BIT(6), 0);
212static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
213 0x060, BIT(8), 0);
214static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
215 0x060, BIT(9), 0);
216static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
217 0x060, BIT(10), 0);
218static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
219 0x060, BIT(13), 0);
220static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
221 0x060, BIT(14), 0);
222static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
223 0x060, BIT(17), 0);
224static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
225 0x060, BIT(18), 0);
226static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
227 0x060, BIT(19), 0);
228static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
229 0x060, BIT(20), 0);
230static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
231 0x060, BIT(21), 0);
232static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
233 0x060, BIT(23), 0);
234static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
235 0x060, BIT(24), 0);
236static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
237 0x060, BIT(25), 0);
238static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",
239 0x060, BIT(26), 0);
240static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",
241 0x060, BIT(27), 0);
242static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
243 0x060, BIT(28), 0);
244static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
245 0x060, BIT(29), 0);
246static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",
247 0x060, BIT(30), 0);
248static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",
249 0x060, BIT(31), 0);
250
251static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
252 0x064, BIT(0), 0);
253static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
254 0x064, BIT(3), 0);
255static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
256 0x064, BIT(4), 0);
257static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
258 0x064, BIT(5), 0);
259static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
260 0x064, BIT(8), 0);
261static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",
262 0x064, BIT(9), 0);
263static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
264 0x064, BIT(11), 0);
265static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
266 0x064, BIT(12), 0);
267static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
268 0x064, BIT(20), 0);
269static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
270 0x064, BIT(21), 0);
271static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
272 0x064, BIT(22), 0);
273
274static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
275 0x068, BIT(0), 0);
276static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
277 0x068, BIT(1), 0);
278static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
279 0x068, BIT(5), 0);
280static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
281 0x068, BIT(8), 0);
282static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
283 0x068, BIT(12), 0);
284static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
285 0x068, BIT(13), 0);
286static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
287 0x068, BIT(14), 0);
288
289static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
290 0x06c, BIT(0), 0);
291static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
292 0x06c, BIT(1), 0);
293static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
294 0x06c, BIT(2), 0);
295static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
296 0x06c, BIT(16), 0);
297static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
298 0x06c, BIT(17), 0);
299static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
300 0x06c, BIT(18), 0);
301static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
302 0x06c, BIT(19), 0);
303static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
304 0x06c, BIT(20), 0);
305
306static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
307 0x070, BIT(0), 0);
308static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
309 0x070, BIT(7), 0);
310
311static struct clk_div_table ths_div_table[] = {
312 { .val = 0, .div = 1 },
313 { .val = 1, .div = 2 },
314 { .val = 2, .div = 4 },
315 { .val = 3, .div = 6 },
316};
317static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
318 0x074, 0, 2, ths_div_table, BIT(31), 0);
319
320static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
321 "pll-periph1" };
322static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
323 0, 4, /* M */
324 16, 2, /* P */
325 24, 2, /* mux */
326 BIT(31), /* gate */
327 0);
328
329static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
330 0, 4, /* M */
331 16, 2, /* P */
332 24, 2, /* mux */
333 BIT(31), /* gate */
334 0);
335
336static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
337 0x088, 20, 3, 0);
338static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
339 0x088, 8, 3, 0);
340
341static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
342 0, 4, /* M */
343 16, 2, /* P */
344 24, 2, /* mux */
345 BIT(31), /* gate */
346 0);
347
348static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
349 0x08c, 20, 3, 0);
350static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
351 0x08c, 8, 3, 0);
352
353static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
354 0, 4, /* M */
355 16, 2, /* P */
356 24, 2, /* mux */
357 BIT(31), /* gate */
358 0);
359
360static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
361 0x090, 20, 3, 0);
362static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
363 0x090, 8, 3, 0);
364
365static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
366static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
367 0, 4, /* M */
368 16, 2, /* P */
369 24, 2, /* mux */
370 BIT(31), /* gate */
371 0);
372
373static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
374 0, 4, /* M */
375 16, 2, /* P */
376 24, 2, /* mux */
377 BIT(31), /* gate */
378 0);
379
380static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
381 0, 4, /* M */
382 16, 2, /* P */
383 24, 2, /* mux */
384 BIT(31), /* gate */
385 0);
386
387static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
388 0, 4, /* M */
389 16, 2, /* P */
390 24, 2, /* mux */
391 BIT(31), /* gate */
392 0);
393
394static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
395 "pll-audio-2x", "pll-audio" };
396static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
397 0x0b0, 16, 2, BIT(31), 0);
398
399static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
400 0x0b4, 16, 2, BIT(31), 0);
401
402static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
403 0x0b8, 16, 2, BIT(31), 0);
404
405static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
406 0x0c0, 0, 4, BIT(31), 0);
407
408static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
409 0x0cc, BIT(8), 0);
410static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
411 0x0cc, BIT(9), 0);
412static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
413 0x0cc, BIT(10), 0);
414static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M",
415 0x0cc, BIT(11), 0);
416static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
417 0x0cc, BIT(16), 0);
418static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
419 0x0cc, BIT(17), 0);
420static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
421 0x0cc, BIT(18), 0);
422static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
423 0x0cc, BIT(19), 0);
424
425static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
426static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
427 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
428
429static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
430 0x100, BIT(0), 0);
431static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
432 0x100, BIT(1), 0);
433static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
434 0x100, BIT(2), 0);
435static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
436 0x100, BIT(3), 0);
437
438static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
439static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
440 0x104, 0, 4, 24, 3, BIT(31), 0);
441
442static const char * const tcon_parents[] = { "pll-video" };
443static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
444 0x118, 0, 4, 24, 3, BIT(31), 0);
445
446static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
447static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
448 0x120, 0, 4, 24, 3, BIT(31), 0);
449
450static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
451static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
452 0x124, 0, 4, 24, 3, BIT(31), 0);
453
454static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
455 0x130, BIT(31), 0);
456
457static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
458static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
459 0x134, 16, 4, 24, 3, BIT(31), 0);
460
461static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
462static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
463 0x134, 0, 5, 8, 3, BIT(15), 0);
464
465static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
466 0x13c, 16, 3, BIT(31), 0);
467
468static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
469 0x140, BIT(31), 0);
470static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
471 0x144, BIT(31), 0);
472
473static const char * const hdmi_parents[] = { "pll-video" };
474static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
475 0x150, 0, 4, 24, 2, BIT(31), 0);
476
477static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
478 0x154, BIT(31), 0);
479
480static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
481static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
482 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
483
484static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
485 0x1a0, 0, 3, BIT(31), 0);
486
487static struct ccu_common *sun8i_h3_ccu_clks[] = {
488 &pll_cpux_clk.common,
489 &pll_audio_base_clk.common,
490 &pll_video_clk.common,
491 &pll_ve_clk.common,
492 &pll_ddr_clk.common,
493 &pll_periph0_clk.common,
494 &pll_gpu_clk.common,
495 &pll_periph1_clk.common,
496 &pll_de_clk.common,
497 &cpux_clk.common,
498 &axi_clk.common,
499 &ahb1_clk.common,
500 &apb1_clk.common,
501 &apb2_clk.common,
502 &ahb2_clk.common,
503 &bus_ce_clk.common,
504 &bus_dma_clk.common,
505 &bus_mmc0_clk.common,
506 &bus_mmc1_clk.common,
507 &bus_mmc2_clk.common,
508 &bus_nand_clk.common,
509 &bus_dram_clk.common,
510 &bus_emac_clk.common,
511 &bus_ts_clk.common,
512 &bus_hstimer_clk.common,
513 &bus_spi0_clk.common,
514 &bus_spi1_clk.common,
515 &bus_otg_clk.common,
516 &bus_ehci0_clk.common,
517 &bus_ehci1_clk.common,
518 &bus_ehci2_clk.common,
519 &bus_ehci3_clk.common,
520 &bus_ohci0_clk.common,
521 &bus_ohci1_clk.common,
522 &bus_ohci2_clk.common,
523 &bus_ohci3_clk.common,
524 &bus_ve_clk.common,
525 &bus_tcon0_clk.common,
526 &bus_tcon1_clk.common,
527 &bus_deinterlace_clk.common,
528 &bus_csi_clk.common,
529 &bus_tve_clk.common,
530 &bus_hdmi_clk.common,
531 &bus_de_clk.common,
532 &bus_gpu_clk.common,
533 &bus_msgbox_clk.common,
534 &bus_spinlock_clk.common,
535 &bus_codec_clk.common,
536 &bus_spdif_clk.common,
537 &bus_pio_clk.common,
538 &bus_ths_clk.common,
539 &bus_i2s0_clk.common,
540 &bus_i2s1_clk.common,
541 &bus_i2s2_clk.common,
542 &bus_i2c0_clk.common,
543 &bus_i2c1_clk.common,
544 &bus_i2c2_clk.common,
545 &bus_uart0_clk.common,
546 &bus_uart1_clk.common,
547 &bus_uart2_clk.common,
548 &bus_uart3_clk.common,
549 &bus_scr_clk.common,
550 &bus_ephy_clk.common,
551 &bus_dbg_clk.common,
552 &ths_clk.common,
553 &nand_clk.common,
554 &mmc0_clk.common,
555 &mmc0_sample_clk.common,
556 &mmc0_output_clk.common,
557 &mmc1_clk.common,
558 &mmc1_sample_clk.common,
559 &mmc1_output_clk.common,
560 &mmc2_clk.common,
561 &mmc2_sample_clk.common,
562 &mmc2_output_clk.common,
563 &ts_clk.common,
564 &ce_clk.common,
565 &spi0_clk.common,
566 &spi1_clk.common,
567 &i2s0_clk.common,
568 &i2s1_clk.common,
569 &i2s2_clk.common,
570 &spdif_clk.common,
571 &usb_phy0_clk.common,
572 &usb_phy1_clk.common,
573 &usb_phy2_clk.common,
574 &usb_phy3_clk.common,
575 &usb_ohci0_clk.common,
576 &usb_ohci1_clk.common,
577 &usb_ohci2_clk.common,
578 &usb_ohci3_clk.common,
579 &dram_clk.common,
580 &dram_ve_clk.common,
581 &dram_csi_clk.common,
582 &dram_deinterlace_clk.common,
583 &dram_ts_clk.common,
584 &de_clk.common,
585 &tcon_clk.common,
586 &tve_clk.common,
587 &deinterlace_clk.common,
588 &csi_misc_clk.common,
589 &csi_sclk_clk.common,
590 &csi_mclk_clk.common,
591 &ve_clk.common,
592 &ac_dig_clk.common,
593 &avs_clk.common,
594 &hdmi_clk.common,
595 &hdmi_ddc_clk.common,
596 &mbus_clk.common,
597 &gpu_clk.common,
598};
599
600/* We hardcode the divider to 4 for now */
601static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
602 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
603static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
604 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
605static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
606 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
607static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
608 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
609static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
610 "pll-periph0", 1, 2, 0);
611
612static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
613 .hws = {
614 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
615 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
616 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
617 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
618 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
619 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
620 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
621 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
622 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
623 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
624 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
625 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
626 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
627 [CLK_PLL_DE] = &pll_de_clk.common.hw,
628 [CLK_CPUX] = &cpux_clk.common.hw,
629 [CLK_AXI] = &axi_clk.common.hw,
630 [CLK_AHB1] = &ahb1_clk.common.hw,
631 [CLK_APB1] = &apb1_clk.common.hw,
632 [CLK_APB2] = &apb2_clk.common.hw,
633 [CLK_AHB2] = &ahb2_clk.common.hw,
634 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
635 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
636 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
637 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
638 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
639 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
640 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
641 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
642 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
643 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
644 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
645 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
646 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
647 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
648 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
649 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
650 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
651 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
652 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
653 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
654 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
655 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
656 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
657 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
658 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
659 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
660 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
661 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
662 [CLK_BUS_DE] = &bus_de_clk.common.hw,
663 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
664 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
665 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
666 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
667 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
668 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
669 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
670 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
671 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
672 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
673 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
674 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
675 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
676 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
677 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
678 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
679 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
680 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
681 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
682 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
683 [CLK_THS] = &ths_clk.common.hw,
684 [CLK_NAND] = &nand_clk.common.hw,
685 [CLK_MMC0] = &mmc0_clk.common.hw,
686 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
687 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
688 [CLK_MMC1] = &mmc1_clk.common.hw,
689 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
690 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
691 [CLK_MMC2] = &mmc2_clk.common.hw,
692 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
693 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
694 [CLK_TS] = &ts_clk.common.hw,
695 [CLK_CE] = &ce_clk.common.hw,
696 [CLK_SPI0] = &spi0_clk.common.hw,
697 [CLK_SPI1] = &spi1_clk.common.hw,
698 [CLK_I2S0] = &i2s0_clk.common.hw,
699 [CLK_I2S1] = &i2s1_clk.common.hw,
700 [CLK_I2S2] = &i2s2_clk.common.hw,
701 [CLK_SPDIF] = &spdif_clk.common.hw,
702 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
703 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
704 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
705 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
706 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
707 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
708 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
709 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
710 [CLK_DRAM] = &dram_clk.common.hw,
711 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
712 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
713 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
714 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
715 [CLK_DE] = &de_clk.common.hw,
716 [CLK_TCON0] = &tcon_clk.common.hw,
717 [CLK_TVE] = &tve_clk.common.hw,
718 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
719 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
720 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
721 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
722 [CLK_VE] = &ve_clk.common.hw,
723 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
724 [CLK_AVS] = &avs_clk.common.hw,
725 [CLK_HDMI] = &hdmi_clk.common.hw,
726 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
727 [CLK_MBUS] = &mbus_clk.common.hw,
728 [CLK_GPU] = &gpu_clk.common.hw,
729 },
730 .num = CLK_NUMBER,
731};
732
733static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
734 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
735 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
736 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
737 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
738
739 [RST_MBUS] = { 0x0fc, BIT(31) },
740
741 [RST_BUS_CE] = { 0x2c0, BIT(5) },
742 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
743 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
744 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
745 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
746 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
747 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
748 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
749 [RST_BUS_TS] = { 0x2c0, BIT(18) },
750 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
751 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
752 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
753 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
754 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
755 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
756 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
757 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
758 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
759 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
760 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
761 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
762
763 [RST_BUS_VE] = { 0x2c4, BIT(0) },
764 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
765 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
766 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
767 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
768 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
769 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
770 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
771 [RST_BUS_DE] = { 0x2c4, BIT(12) },
772 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
773 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
774 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
775 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
776
777 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
778
779 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
780 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
781 [RST_BUS_THS] = { 0x2d0, BIT(8) },
782 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
783 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
784 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
785
786 [RST_BUS_I2C0] = { 0x2d4, BIT(0) },
787 [RST_BUS_I2C1] = { 0x2d4, BIT(1) },
788 [RST_BUS_I2C2] = { 0x2d4, BIT(2) },
789 [RST_BUS_UART0] = { 0x2d4, BIT(16) },
790 [RST_BUS_UART1] = { 0x2d4, BIT(17) },
791 [RST_BUS_UART2] = { 0x2d4, BIT(18) },
792 [RST_BUS_UART3] = { 0x2d4, BIT(19) },
793 [RST_BUS_SCR] = { 0x2d4, BIT(20) },
794};
795
796static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
797 .ccu_clks = sun8i_h3_ccu_clks,
798 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
799
800 .hw_clks = &sun8i_h3_hw_clks,
801
802 .resets = sun8i_h3_ccu_resets,
803 .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
804};
805
806static void __init sun8i_h3_ccu_setup(struct device_node *node)
807{
808 void __iomem *reg;
809 u32 val;
810
811 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
812 if (IS_ERR(reg)) {
813 pr_err("%s: Could not map the clock registers\n",
814 of_node_full_name(node));
815 return;
816 }
817
818 /* Force the PLL-Audio-1x divider to 4 */
819 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
820 val &= ~GENMASK(19, 16);
821 writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
822
823 sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
824}
825CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
826 sun8i_h3_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
new file mode 100644
index 000000000000..78be712c7487
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2016 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _CCU_SUN8I_H3_H_
18#define _CCU_SUN8I_H3_H_
19
20#include <dt-bindings/clock/sun8i-h3-ccu.h>
21#include <dt-bindings/reset/sun8i-h3-ccu.h>
22
23#define CLK_PLL_CPUX 0
24#define CLK_PLL_AUDIO_BASE 1
25#define CLK_PLL_AUDIO 2
26#define CLK_PLL_AUDIO_2X 3
27#define CLK_PLL_AUDIO_4X 4
28#define CLK_PLL_AUDIO_8X 5
29#define CLK_PLL_VIDEO 6
30#define CLK_PLL_VE 7
31#define CLK_PLL_DDR 8
32#define CLK_PLL_PERIPH0 9
33#define CLK_PLL_PERIPH0_2X 10
34#define CLK_PLL_GPU 11
35#define CLK_PLL_PERIPH1 12
36#define CLK_PLL_DE 13
37
38/* The CPUX clock is exported */
39
40#define CLK_AXI 15
41#define CLK_AHB1 16
42#define CLK_APB1 17
43#define CLK_APB2 18
44#define CLK_AHB2 19
45
46/* All the bus gates are exported */
47
48/* The first bunch of module clocks are exported */
49
50#define CLK_DRAM 96
51
52/* All the DRAM gates are exported */
53
54/* Some more module clocks are exported */
55
56#define CLK_MBUS 113
57
58/* And the GPU module clock is exported */
59
60#define CLK_NUMBER (CLK_GPU + 1)
61
62#endif /* _CCU_SUN8I_H3_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
new file mode 100644
index 000000000000..fc17b5295e16
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -0,0 +1,90 @@
1/*
2 * Copyright 2016 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/iopoll.h>
19#include <linux/slab.h>
20
21#include "ccu_common.h"
22#include "ccu_reset.h"
23
24static DEFINE_SPINLOCK(ccu_lock);
25
26void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
27{
28 u32 reg;
29
30 if (!lock)
31 return;
32
33 WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
34 !(reg & lock), 100, 70000));
35}
36
37int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
38 const struct sunxi_ccu_desc *desc)
39{
40 struct ccu_reset *reset;
41 int i, ret;
42
43 for (i = 0; i < desc->num_ccu_clks; i++) {
44 struct ccu_common *cclk = desc->ccu_clks[i];
45
46 if (!cclk)
47 continue;
48
49 cclk->base = reg;
50 cclk->lock = &ccu_lock;
51 }
52
53 for (i = 0; i < desc->hw_clks->num ; i++) {
54 struct clk_hw *hw = desc->hw_clks->hws[i];
55
56 if (!hw)
57 continue;
58
59 ret = clk_hw_register(NULL, hw);
60 if (ret) {
61 pr_err("Couldn't register clock %s\n",
62 clk_hw_get_name(hw));
63 goto err_clk_unreg;
64 }
65 }
66
67 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
68 desc->hw_clks);
69 if (ret)
70 goto err_clk_unreg;
71
72 reset = kzalloc(sizeof(*reset), GFP_KERNEL);
73 reset->rcdev.of_node = node;
74 reset->rcdev.ops = &ccu_reset_ops;
75 reset->rcdev.owner = THIS_MODULE;
76 reset->rcdev.nr_resets = desc->num_resets;
77 reset->base = reg;
78 reset->lock = &ccu_lock;
79 reset->reset_map = desc->resets;
80
81 ret = reset_controller_register(&reset->rcdev);
82 if (ret)
83 goto err_of_clk_unreg;
84
85 return 0;
86
87err_of_clk_unreg:
88err_clk_unreg:
89 return ret;
90}
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
new file mode 100644
index 000000000000..b3d9abfbd721
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _COMMON_H_
15#define _COMMON_H_
16
17#include <linux/compiler.h>
18#include <linux/clk-provider.h>
19
20#define CCU_FEATURE_FRACTIONAL BIT(0)
21#define CCU_FEATURE_VARIABLE_PREDIV BIT(1)
22#define CCU_FEATURE_FIXED_PREDIV BIT(2)
23#define CCU_FEATURE_FIXED_POSTDIV BIT(3)
24
25struct device_node;
26
27#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
28 &(struct clk_init_data) { \
29 .flags = _flags, \
30 .name = _name, \
31 .parent_names = (const char *[]) { _parent }, \
32 .num_parents = 1, \
33 .ops = _ops, \
34 }
35
36#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
37 &(struct clk_init_data) { \
38 .flags = _flags, \
39 .name = _name, \
40 .parent_names = _parents, \
41 .num_parents = ARRAY_SIZE(_parents), \
42 .ops = _ops, \
43 }
44
45#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
46 _div, _mult, _flags) \
47 struct clk_fixed_factor _struct = { \
48 .div = _div, \
49 .mult = _mult, \
50 .hw.init = CLK_HW_INIT(_name, \
51 _parent, \
52 &clk_fixed_factor_ops, \
53 _flags), \
54 }
55
56struct ccu_common {
57 void __iomem *base;
58 u16 reg;
59
60 unsigned long features;
61 spinlock_t *lock;
62 struct clk_hw hw;
63};
64
65static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
66{
67 return container_of(hw, struct ccu_common, hw);
68}
69
70struct sunxi_ccu_desc {
71 struct ccu_common **ccu_clks;
72 unsigned long num_ccu_clks;
73
74 struct clk_hw_onecell_data *hw_clks;
75
76 struct ccu_reset_map *resets;
77 unsigned long num_resets;
78};
79
80void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
81
82int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
83 const struct sunxi_ccu_desc *desc);
84
85#endif /* _COMMON_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
new file mode 100644
index 000000000000..8659b4cb6c20
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12
13#include "ccu_gate.h"
14#include "ccu_div.h"
15
16static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
17 unsigned long parent_rate,
18 unsigned long rate,
19 void *data)
20{
21 struct ccu_div *cd = data;
22 unsigned long val;
23
24 /*
25 * We can't use divider_round_rate that assumes that there's
26 * several parents, while we might be called to evaluate
27 * several different parents.
28 */
29 val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
30 cd->div.flags);
31
32 return divider_recalc_rate(&cd->common.hw, parent_rate, val,
33 cd->div.table, cd->div.flags);
34}
35
36static void ccu_div_disable(struct clk_hw *hw)
37{
38 struct ccu_div *cd = hw_to_ccu_div(hw);
39
40 return ccu_gate_helper_disable(&cd->common, cd->enable);
41}
42
43static int ccu_div_enable(struct clk_hw *hw)
44{
45 struct ccu_div *cd = hw_to_ccu_div(hw);
46
47 return ccu_gate_helper_enable(&cd->common, cd->enable);
48}
49
50static int ccu_div_is_enabled(struct clk_hw *hw)
51{
52 struct ccu_div *cd = hw_to_ccu_div(hw);
53
54 return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
55}
56
57static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
58 unsigned long parent_rate)
59{
60 struct ccu_div *cd = hw_to_ccu_div(hw);
61 unsigned long val;
62 u32 reg;
63
64 reg = readl(cd->common.base + cd->common.reg);
65 val = reg >> cd->div.shift;
66 val &= (1 << cd->div.width) - 1;
67
68 ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
69 &parent_rate);
70
71 return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
72 cd->div.flags);
73}
74
75static int ccu_div_determine_rate(struct clk_hw *hw,
76 struct clk_rate_request *req)
77{
78 struct ccu_div *cd = hw_to_ccu_div(hw);
79
80 return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
81 req, ccu_div_round_rate, cd);
82}
83
84static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
85 unsigned long parent_rate)
86{
87 struct ccu_div *cd = hw_to_ccu_div(hw);
88 unsigned long flags;
89 unsigned long val;
90 u32 reg;
91
92 ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
93 &parent_rate);
94
95 val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
96 cd->div.flags);
97
98 spin_lock_irqsave(cd->common.lock, flags);
99
100 reg = readl(cd->common.base + cd->common.reg);
101 reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
102
103 writel(reg | (val << cd->div.shift),
104 cd->common.base + cd->common.reg);
105
106 spin_unlock_irqrestore(cd->common.lock, flags);
107
108 return 0;
109}
110
111static u8 ccu_div_get_parent(struct clk_hw *hw)
112{
113 struct ccu_div *cd = hw_to_ccu_div(hw);
114
115 return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
116}
117
118static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
119{
120 struct ccu_div *cd = hw_to_ccu_div(hw);
121
122 return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
123}
124
125const struct clk_ops ccu_div_ops = {
126 .disable = ccu_div_disable,
127 .enable = ccu_div_enable,
128 .is_enabled = ccu_div_is_enabled,
129
130 .get_parent = ccu_div_get_parent,
131 .set_parent = ccu_div_set_parent,
132
133 .determine_rate = ccu_div_determine_rate,
134 .recalc_rate = ccu_div_recalc_rate,
135 .set_rate = ccu_div_set_rate,
136};
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
new file mode 100644
index 000000000000..653ade5769b3
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -0,0 +1,133 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_DIV_H_
15#define _CCU_DIV_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20#include "ccu_mux.h"
21
22struct _ccu_div {
23 u8 shift;
24 u8 width;
25
26 u32 flags;
27
28 struct clk_div_table *table;
29};
30
31#define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \
32 { \
33 .shift = _shift, \
34 .width = _width, \
35 .flags = _flags, \
36 .table = _table, \
37 }
38
39#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
40 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, _flags)
41
42#define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
43 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
44
45#define _SUNXI_CCU_DIV(_shift, _width) \
46 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, 0)
47
48struct ccu_div {
49 u32 enable;
50
51 struct _ccu_div div;
52 struct ccu_mux_internal mux;
53 struct ccu_common common;
54};
55
56#define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
57 _shift, _width, \
58 _table, _gate, _flags) \
59 struct ccu_div _struct = { \
60 .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
61 _table), \
62 .enable = _gate, \
63 .common = { \
64 .reg = _reg, \
65 .hw.init = CLK_HW_INIT(_name, \
66 _parent, \
67 &ccu_div_ops, \
68 _flags), \
69 } \
70 }
71
72
73#define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \
74 _shift, _width, \
75 _table, _flags) \
76 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
77 _shift, _width, _table, 0, \
78 _flags)
79
80#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
81 _mshift, _mwidth, _muxshift, _muxwidth, \
82 _gate, _flags) \
83 struct ccu_div _struct = { \
84 .enable = _gate, \
85 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
86 .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
87 .common = { \
88 .reg = _reg, \
89 .hw.init = CLK_HW_INIT_PARENTS(_name, \
90 _parents, \
91 &ccu_div_ops, \
92 _flags), \
93 }, \
94 }
95
96#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
97 _mshift, _mwidth, _muxshift, _muxwidth, \
98 _flags) \
99 SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
100 _mshift, _mwidth, _muxshift, _muxwidth, \
101 0, _flags)
102
103
104#define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
105 _mshift, _mwidth, _gate, \
106 _flags) \
107 struct ccu_div _struct = { \
108 .enable = _gate, \
109 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
110 .common = { \
111 .reg = _reg, \
112 .hw.init = CLK_HW_INIT(_name, \
113 _parent, \
114 &ccu_div_ops, \
115 _flags), \
116 }, \
117 }
118
119#define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \
120 _flags) \
121 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
122 _mshift, _mwidth, 0, _flags)
123
124static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
125{
126 struct ccu_common *common = hw_to_ccu_common(hw);
127
128 return container_of(common, struct ccu_div, common);
129}
130
131extern const struct clk_ops ccu_div_ops;
132
133#endif /* _CCU_DIV_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
new file mode 100644
index 000000000000..5c4b10cd15b5
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_frac.c
@@ -0,0 +1,110 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/spinlock.h>
13
14#include "ccu_frac.h"
15
16bool ccu_frac_helper_is_enabled(struct ccu_common *common,
17 struct _ccu_frac *cf)
18{
19 if (!(common->features & CCU_FEATURE_FRACTIONAL))
20 return false;
21
22 return !(readl(common->base + common->reg) & cf->enable);
23}
24
25void ccu_frac_helper_enable(struct ccu_common *common,
26 struct _ccu_frac *cf)
27{
28 unsigned long flags;
29 u32 reg;
30
31 if (!(common->features & CCU_FEATURE_FRACTIONAL))
32 return;
33
34 spin_lock_irqsave(common->lock, flags);
35 reg = readl(common->base + common->reg);
36 writel(reg & ~cf->enable, common->base + common->reg);
37 spin_unlock_irqrestore(common->lock, flags);
38}
39
40void ccu_frac_helper_disable(struct ccu_common *common,
41 struct _ccu_frac *cf)
42{
43 unsigned long flags;
44 u32 reg;
45
46 if (!(common->features & CCU_FEATURE_FRACTIONAL))
47 return;
48
49 spin_lock_irqsave(common->lock, flags);
50 reg = readl(common->base + common->reg);
51 writel(reg | cf->enable, common->base + common->reg);
52 spin_unlock_irqrestore(common->lock, flags);
53}
54
55bool ccu_frac_helper_has_rate(struct ccu_common *common,
56 struct _ccu_frac *cf,
57 unsigned long rate)
58{
59 if (!(common->features & CCU_FEATURE_FRACTIONAL))
60 return false;
61
62 return (cf->rates[0] == rate) || (cf->rates[1] == rate);
63}
64
65unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
66 struct _ccu_frac *cf)
67{
68 u32 reg;
69
70 printk("%s: Read fractional\n", clk_hw_get_name(&common->hw));
71
72 if (!(common->features & CCU_FEATURE_FRACTIONAL))
73 return 0;
74
75 printk("%s: clock is fractional (rates %lu and %lu)\n",
76 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
77
78 reg = readl(common->base + common->reg);
79
80 printk("%s: clock reg is 0x%x (select is 0x%x)\n",
81 clk_hw_get_name(&common->hw), reg, cf->select);
82
83 return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
84}
85
86int ccu_frac_helper_set_rate(struct ccu_common *common,
87 struct _ccu_frac *cf,
88 unsigned long rate)
89{
90 unsigned long flags;
91 u32 reg, sel;
92
93 if (!(common->features & CCU_FEATURE_FRACTIONAL))
94 return -EINVAL;
95
96 if (cf->rates[0] == rate)
97 sel = 0;
98 else if (cf->rates[1] == rate)
99 sel = cf->select;
100 else
101 return -EINVAL;
102
103 spin_lock_irqsave(common->lock, flags);
104 reg = readl(common->base + common->reg);
105 reg &= ~cf->select;
106 writel(reg | sel, common->base + common->reg);
107 spin_unlock_irqrestore(common->lock, flags);
108
109 return 0;
110}
diff --git a/drivers/clk/sunxi-ng/ccu_frac.h b/drivers/clk/sunxi-ng/ccu_frac.h
new file mode 100644
index 000000000000..e4c670b1cdfe
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_frac.h
@@ -0,0 +1,53 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_FRAC_H_
15#define _CCU_FRAC_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20
21struct _ccu_frac {
22 u32 enable;
23 u32 select;
24
25 unsigned long rates[2];
26};
27
28#define _SUNXI_CCU_FRAC(_enable, _select, _rate1, _rate2) \
29 { \
30 .enable = _enable, \
31 .select = _select, \
32 .rates = { _rate1, _rate2 }, \
33 }
34
35bool ccu_frac_helper_is_enabled(struct ccu_common *common,
36 struct _ccu_frac *cf);
37void ccu_frac_helper_enable(struct ccu_common *common,
38 struct _ccu_frac *cf);
39void ccu_frac_helper_disable(struct ccu_common *common,
40 struct _ccu_frac *cf);
41
42bool ccu_frac_helper_has_rate(struct ccu_common *common,
43 struct _ccu_frac *cf,
44 unsigned long rate);
45
46unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
47 struct _ccu_frac *cf);
48
49int ccu_frac_helper_set_rate(struct ccu_common *common,
50 struct _ccu_frac *cf,
51 unsigned long rate);
52
53#endif /* _CCU_FRAC_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_gate.c b/drivers/clk/sunxi-ng/ccu_gate.c
new file mode 100644
index 000000000000..8a81f9d4a89f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_gate.c
@@ -0,0 +1,82 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12
13#include "ccu_gate.h"
14
15void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
16{
17 unsigned long flags;
18 u32 reg;
19
20 if (!gate)
21 return;
22
23 spin_lock_irqsave(common->lock, flags);
24
25 reg = readl(common->base + common->reg);
26 writel(reg & ~gate, common->base + common->reg);
27
28 spin_unlock_irqrestore(common->lock, flags);
29}
30
31static void ccu_gate_disable(struct clk_hw *hw)
32{
33 struct ccu_gate *cg = hw_to_ccu_gate(hw);
34
35 return ccu_gate_helper_disable(&cg->common, cg->enable);
36}
37
38int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
39{
40 unsigned long flags;
41 u32 reg;
42
43 if (!gate)
44 return 0;
45
46 spin_lock_irqsave(common->lock, flags);
47
48 reg = readl(common->base + common->reg);
49 writel(reg | gate, common->base + common->reg);
50
51 spin_unlock_irqrestore(common->lock, flags);
52
53 return 0;
54}
55
56static int ccu_gate_enable(struct clk_hw *hw)
57{
58 struct ccu_gate *cg = hw_to_ccu_gate(hw);
59
60 return ccu_gate_helper_enable(&cg->common, cg->enable);
61}
62
63int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate)
64{
65 if (!gate)
66 return 1;
67
68 return readl(common->base + common->reg) & gate;
69}
70
71static int ccu_gate_is_enabled(struct clk_hw *hw)
72{
73 struct ccu_gate *cg = hw_to_ccu_gate(hw);
74
75 return ccu_gate_helper_is_enabled(&cg->common, cg->enable);
76}
77
78const struct clk_ops ccu_gate_ops = {
79 .disable = ccu_gate_disable,
80 .enable = ccu_gate_enable,
81 .is_enabled = ccu_gate_is_enabled,
82};
diff --git a/drivers/clk/sunxi-ng/ccu_gate.h b/drivers/clk/sunxi-ng/ccu_gate.h
new file mode 100644
index 000000000000..4466169bd2d7
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_gate.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_GATE_H_
15#define _CCU_GATE_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20
21struct ccu_gate {
22 u32 enable;
23
24 struct ccu_common common;
25};
26
27#define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \
28 struct ccu_gate _struct = { \
29 .enable = _gate, \
30 .common = { \
31 .reg = _reg, \
32 .hw.init = CLK_HW_INIT(_name, \
33 _parent, \
34 &ccu_gate_ops, \
35 _flags), \
36 } \
37 }
38
39static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw)
40{
41 struct ccu_common *common = hw_to_ccu_common(hw);
42
43 return container_of(common, struct ccu_gate, common);
44}
45
46void ccu_gate_helper_disable(struct ccu_common *common, u32 gate);
47int ccu_gate_helper_enable(struct ccu_common *common, u32 gate);
48int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate);
49
50extern const struct clk_ops ccu_gate_ops;
51
52#endif /* _CCU_GATE_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
new file mode 100644
index 000000000000..cbf33ef5faa9
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -0,0 +1,158 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12
13#include "ccu_gate.h"
14#include "ccu_mp.h"
15
16static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
17 unsigned int max_m, unsigned int max_p,
18 unsigned int *m, unsigned int *p)
19{
20 unsigned long best_rate = 0;
21 unsigned int best_m = 0, best_p = 0;
22 unsigned int _m, _p;
23
24 for (_p = 0; _p <= max_p; _p++) {
25 for (_m = 1; _m <= max_m; _m++) {
26 unsigned long tmp_rate = (parent >> _p) / _m;
27
28 if (tmp_rate > rate)
29 continue;
30
31 if ((rate - tmp_rate) < (rate - best_rate)) {
32 best_rate = tmp_rate;
33 best_m = _m;
34 best_p = _p;
35 }
36 }
37 }
38
39 *m = best_m;
40 *p = best_p;
41}
42
43static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
44 unsigned long parent_rate,
45 unsigned long rate,
46 void *data)
47{
48 struct ccu_mp *cmp = data;
49 unsigned int m, p;
50
51 ccu_mp_find_best(parent_rate, rate,
52 1 << cmp->m.width, (1 << cmp->p.width) - 1,
53 &m, &p);
54
55 return (parent_rate >> p) / m;
56}
57
58static void ccu_mp_disable(struct clk_hw *hw)
59{
60 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
61
62 return ccu_gate_helper_disable(&cmp->common, cmp->enable);
63}
64
65static int ccu_mp_enable(struct clk_hw *hw)
66{
67 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
68
69 return ccu_gate_helper_enable(&cmp->common, cmp->enable);
70}
71
72static int ccu_mp_is_enabled(struct clk_hw *hw)
73{
74 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
75
76 return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
77}
78
79static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
80 unsigned long parent_rate)
81{
82 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
83 unsigned int m, p;
84 u32 reg;
85
86 reg = readl(cmp->common.base + cmp->common.reg);
87
88 m = reg >> cmp->m.shift;
89 m &= (1 << cmp->m.width) - 1;
90
91 p = reg >> cmp->p.shift;
92 p &= (1 << cmp->p.width) - 1;
93
94 return (parent_rate >> p) / (m + 1);
95}
96
97static int ccu_mp_determine_rate(struct clk_hw *hw,
98 struct clk_rate_request *req)
99{
100 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
101
102 return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
103 req, ccu_mp_round_rate, cmp);
104}
105
106static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
107 unsigned long parent_rate)
108{
109 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
110 unsigned long flags;
111 unsigned int m, p;
112 u32 reg;
113
114 ccu_mp_find_best(parent_rate, rate,
115 1 << cmp->m.width, (1 << cmp->p.width) - 1,
116 &m, &p);
117
118
119 spin_lock_irqsave(cmp->common.lock, flags);
120
121 reg = readl(cmp->common.base + cmp->common.reg);
122 reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
123 reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
124
125 writel(reg | (p << cmp->p.shift) | ((m - 1) << cmp->m.shift),
126 cmp->common.base + cmp->common.reg);
127
128 spin_unlock_irqrestore(cmp->common.lock, flags);
129
130 return 0;
131}
132
133static u8 ccu_mp_get_parent(struct clk_hw *hw)
134{
135 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
136
137 return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
138}
139
140static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
141{
142 struct ccu_mp *cmp = hw_to_ccu_mp(hw);
143
144 return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
145}
146
147const struct clk_ops ccu_mp_ops = {
148 .disable = ccu_mp_disable,
149 .enable = ccu_mp_enable,
150 .is_enabled = ccu_mp_is_enabled,
151
152 .get_parent = ccu_mp_get_parent,
153 .set_parent = ccu_mp_set_parent,
154
155 .determine_rate = ccu_mp_determine_rate,
156 .recalc_rate = ccu_mp_recalc_rate,
157 .set_rate = ccu_mp_set_rate,
158};
diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h
new file mode 100644
index 000000000000..3cf12bf95962
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_mp.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_MP_H_
15#define _CCU_MP_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20#include "ccu_div.h"
21#include "ccu_mult.h"
22#include "ccu_mux.h"
23
24/*
25 * struct ccu_mp - Definition of an M-P clock
26 *
27 * Clocks based on the formula parent >> P / M
28 */
29struct ccu_mp {
30 u32 enable;
31
32 struct _ccu_div m;
33 struct _ccu_div p;
34 struct ccu_mux_internal mux;
35 struct ccu_common common;
36};
37
38#define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
39 _mshift, _mwidth, \
40 _pshift, _pwidth, \
41 _muxshift, _muxwidth, \
42 _gate, _flags) \
43 struct ccu_mp _struct = { \
44 .enable = _gate, \
45 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
46 .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
47 .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \
48 .common = { \
49 .reg = _reg, \
50 .hw.init = CLK_HW_INIT_PARENTS(_name, \
51 _parents, \
52 &ccu_mp_ops, \
53 _flags), \
54 } \
55 }
56
57#define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \
58 _mshift, _mwidth, \
59 _pshift, _pwidth, \
60 _muxshift, _muxwidth, \
61 _flags) \
62 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
63 _mshift, _mwidth, \
64 _pshift, _pwidth, \
65 _muxshift, _muxwidth, \
66 0, _flags)
67
68static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw)
69{
70 struct ccu_common *common = hw_to_ccu_common(hw);
71
72 return container_of(common, struct ccu_mp, common);
73}
74
75extern const struct clk_ops ccu_mp_ops;
76
77#endif /* _CCU_MP_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
new file mode 100644
index 000000000000..609db6610880
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_mult.h
@@ -0,0 +1,15 @@
1#ifndef _CCU_MULT_H_
2#define _CCU_MULT_H_
3
4struct _ccu_mult {
5 u8 shift;
6 u8 width;
7};
8
9#define _SUNXI_CCU_MULT(_shift, _width) \
10 { \
11 .shift = _shift, \
12 .width = _width, \
13 }
14
15#endif /* _CCU_MULT_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
new file mode 100644
index 000000000000..58fc36e7dcce
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -0,0 +1,187 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12
13#include "ccu_gate.h"
14#include "ccu_mux.h"
15
16void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
17 struct ccu_mux_internal *cm,
18 int parent_index,
19 unsigned long *parent_rate)
20{
21 u8 prediv = 1;
22 u32 reg;
23
24 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
25 (common->features & CCU_FEATURE_VARIABLE_PREDIV)))
26 return;
27
28 reg = readl(common->base + common->reg);
29 if (parent_index < 0) {
30 parent_index = reg >> cm->shift;
31 parent_index &= (1 << cm->width) - 1;
32 }
33
34 if (common->features & CCU_FEATURE_FIXED_PREDIV)
35 if (parent_index == cm->fixed_prediv.index)
36 prediv = cm->fixed_prediv.div;
37
38 if (common->features & CCU_FEATURE_VARIABLE_PREDIV)
39 if (parent_index == cm->variable_prediv.index) {
40 u8 div;
41
42 div = reg >> cm->variable_prediv.shift;
43 div &= (1 << cm->variable_prediv.width) - 1;
44 prediv = div + 1;
45 }
46
47 *parent_rate = *parent_rate / prediv;
48}
49
50int ccu_mux_helper_determine_rate(struct ccu_common *common,
51 struct ccu_mux_internal *cm,
52 struct clk_rate_request *req,
53 unsigned long (*round)(struct ccu_mux_internal *,
54 unsigned long,
55 unsigned long,
56 void *),
57 void *data)
58{
59 unsigned long best_parent_rate = 0, best_rate = 0;
60 struct clk_hw *best_parent, *hw = &common->hw;
61 unsigned int i;
62
63 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
64 unsigned long tmp_rate, parent_rate;
65 struct clk_hw *parent;
66
67 parent = clk_hw_get_parent_by_index(hw, i);
68 if (!parent)
69 continue;
70
71 parent_rate = clk_hw_get_rate(parent);
72 ccu_mux_helper_adjust_parent_for_prediv(common, cm, i,
73 &parent_rate);
74
75 tmp_rate = round(cm, clk_hw_get_rate(parent), req->rate, data);
76 if (tmp_rate == req->rate) {
77 best_parent = parent;
78 best_parent_rate = parent_rate;
79 best_rate = tmp_rate;
80 goto out;
81 }
82
83 if ((req->rate - tmp_rate) < (req->rate - best_rate)) {
84 best_rate = tmp_rate;
85 best_parent_rate = parent_rate;
86 best_parent = parent;
87 }
88 }
89
90 if (best_rate == 0)
91 return -EINVAL;
92
93out:
94 req->best_parent_hw = best_parent;
95 req->best_parent_rate = best_parent_rate;
96 req->rate = best_rate;
97 return 0;
98}
99
100u8 ccu_mux_helper_get_parent(struct ccu_common *common,
101 struct ccu_mux_internal *cm)
102{
103 u32 reg;
104 u8 parent;
105
106 reg = readl(common->base + common->reg);
107 parent = reg >> cm->shift;
108 parent &= (1 << cm->width) - 1;
109
110 return parent;
111}
112
113int ccu_mux_helper_set_parent(struct ccu_common *common,
114 struct ccu_mux_internal *cm,
115 u8 index)
116{
117 unsigned long flags;
118 u32 reg;
119
120 spin_lock_irqsave(common->lock, flags);
121
122 reg = readl(common->base + common->reg);
123 reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
124 writel(reg | (index << cm->shift), common->base + common->reg);
125
126 spin_unlock_irqrestore(common->lock, flags);
127
128 return 0;
129}
130
131static void ccu_mux_disable(struct clk_hw *hw)
132{
133 struct ccu_mux *cm = hw_to_ccu_mux(hw);
134
135 return ccu_gate_helper_disable(&cm->common, cm->enable);
136}
137
138static int ccu_mux_enable(struct clk_hw *hw)
139{
140 struct ccu_mux *cm = hw_to_ccu_mux(hw);
141
142 return ccu_gate_helper_enable(&cm->common, cm->enable);
143}
144
145static int ccu_mux_is_enabled(struct clk_hw *hw)
146{
147 struct ccu_mux *cm = hw_to_ccu_mux(hw);
148
149 return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
150}
151
152static u8 ccu_mux_get_parent(struct clk_hw *hw)
153{
154 struct ccu_mux *cm = hw_to_ccu_mux(hw);
155
156 return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
157}
158
159static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
160{
161 struct ccu_mux *cm = hw_to_ccu_mux(hw);
162
163 return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
164}
165
166static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
167 unsigned long parent_rate)
168{
169 struct ccu_mux *cm = hw_to_ccu_mux(hw);
170
171 ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
172 &parent_rate);
173
174 return parent_rate;
175}
176
177const struct clk_ops ccu_mux_ops = {
178 .disable = ccu_mux_disable,
179 .enable = ccu_mux_enable,
180 .is_enabled = ccu_mux_is_enabled,
181
182 .get_parent = ccu_mux_get_parent,
183 .set_parent = ccu_mux_set_parent,
184
185 .determine_rate = __clk_mux_determine_rate,
186 .recalc_rate = ccu_mux_recalc_rate,
187};
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
new file mode 100644
index 000000000000..945082631e7d
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -0,0 +1,91 @@
1#ifndef _CCU_MUX_H_
2#define _CCU_MUX_H_
3
4#include <linux/clk-provider.h>
5
6#include "ccu_common.h"
7
8struct ccu_mux_internal {
9 u8 shift;
10 u8 width;
11
12 struct {
13 u8 index;
14 u8 div;
15 } fixed_prediv;
16
17 struct {
18 u8 index;
19 u8 shift;
20 u8 width;
21 } variable_prediv;
22};
23
24#define SUNXI_CLK_MUX(_shift, _width) \
25 { \
26 .shift = _shift, \
27 .width = _width, \
28 }
29
30struct ccu_mux {
31 u16 reg;
32 u32 enable;
33
34 struct ccu_mux_internal mux;
35 struct ccu_common common;
36};
37
38#define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, _flags) \
39 struct ccu_mux _struct = { \
40 .mux = SUNXI_CLK_MUX(_shift, _width), \
41 .common = { \
42 .reg = _reg, \
43 .hw.init = CLK_HW_INIT_PARENTS(_name, \
44 _parents, \
45 &ccu_mux_ops, \
46 _flags), \
47 } \
48 }
49
50#define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
51 _shift, _width, _gate, _flags) \
52 struct ccu_mux _struct = { \
53 .enable = _gate, \
54 .mux = SUNXI_CLK_MUX(_shift, _width), \
55 .common = { \
56 .reg = _reg, \
57 .hw.init = CLK_HW_INIT_PARENTS(_name, \
58 _parents, \
59 &ccu_mux_ops, \
60 _flags), \
61 } \
62 }
63
64static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw)
65{
66 struct ccu_common *common = hw_to_ccu_common(hw);
67
68 return container_of(common, struct ccu_mux, common);
69}
70
71extern const struct clk_ops ccu_mux_ops;
72
73void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
74 struct ccu_mux_internal *cm,
75 int parent_index,
76 unsigned long *parent_rate);
77int ccu_mux_helper_determine_rate(struct ccu_common *common,
78 struct ccu_mux_internal *cm,
79 struct clk_rate_request *req,
80 unsigned long (*round)(struct ccu_mux_internal *,
81 unsigned long,
82 unsigned long,
83 void *),
84 void *data);
85u8 ccu_mux_helper_get_parent(struct ccu_common *common,
86 struct ccu_mux_internal *cm);
87int ccu_mux_helper_set_parent(struct ccu_common *common,
88 struct ccu_mux_internal *cm,
89 u8 index);
90
91#endif /* _CCU_MUX_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
new file mode 100644
index 000000000000..4470ffc8cf0d
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/rational.h>
13
14#include "ccu_gate.h"
15#include "ccu_nk.h"
16
17void ccu_nk_find_best(unsigned long parent, unsigned long rate,
18 unsigned int max_n, unsigned int max_k,
19 unsigned int *n, unsigned int *k)
20{
21 unsigned long best_rate = 0;
22 unsigned int best_k = 0, best_n = 0;
23 unsigned int _k, _n;
24
25 for (_k = 1; _k <= max_k; _k++) {
26 for (_n = 1; _n <= max_n; _n++) {
27 unsigned long tmp_rate = parent * _n * _k;
28
29 if (tmp_rate > rate)
30 continue;
31
32 if ((rate - tmp_rate) < (rate - best_rate)) {
33 best_rate = tmp_rate;
34 best_k = _k;
35 best_n = _n;
36 }
37 }
38 }
39
40 *k = best_k;
41 *n = best_n;
42}
43
44static void ccu_nk_disable(struct clk_hw *hw)
45{
46 struct ccu_nk *nk = hw_to_ccu_nk(hw);
47
48 return ccu_gate_helper_disable(&nk->common, nk->enable);
49}
50
51static int ccu_nk_enable(struct clk_hw *hw)
52{
53 struct ccu_nk *nk = hw_to_ccu_nk(hw);
54
55 return ccu_gate_helper_enable(&nk->common, nk->enable);
56}
57
58static int ccu_nk_is_enabled(struct clk_hw *hw)
59{
60 struct ccu_nk *nk = hw_to_ccu_nk(hw);
61
62 return ccu_gate_helper_is_enabled(&nk->common, nk->enable);
63}
64
65static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
66 unsigned long parent_rate)
67{
68 struct ccu_nk *nk = hw_to_ccu_nk(hw);
69 unsigned long rate, n, k;
70 u32 reg;
71
72 reg = readl(nk->common.base + nk->common.reg);
73
74 n = reg >> nk->n.shift;
75 n &= (1 << nk->n.width) - 1;
76
77 k = reg >> nk->k.shift;
78 k &= (1 << nk->k.width) - 1;
79
80 rate = parent_rate * (n + 1) * (k + 1);
81
82 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
83 rate /= nk->fixed_post_div;
84
85 return rate;
86}
87
88static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
89 unsigned long *parent_rate)
90{
91 struct ccu_nk *nk = hw_to_ccu_nk(hw);
92 unsigned int n, k;
93
94 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
95 rate *= nk->fixed_post_div;
96
97 ccu_nk_find_best(*parent_rate, rate,
98 1 << nk->n.width, 1 << nk->k.width,
99 &n, &k);
100
101 rate = *parent_rate * n * k;
102 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
103 rate = rate / nk->fixed_post_div;
104
105 return rate;
106}
107
108static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
109 unsigned long parent_rate)
110{
111 struct ccu_nk *nk = hw_to_ccu_nk(hw);
112 unsigned long flags;
113 unsigned int n, k;
114 u32 reg;
115
116 if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
117 rate = rate * nk->fixed_post_div;
118
119 ccu_nk_find_best(parent_rate, rate,
120 1 << nk->n.width, 1 << nk->k.width,
121 &n, &k);
122
123 spin_lock_irqsave(nk->common.lock, flags);
124
125 reg = readl(nk->common.base + nk->common.reg);
126 reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
127 reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
128
129 writel(reg | ((k - 1) << nk->k.shift) | ((n - 1) << nk->n.shift),
130 nk->common.base + nk->common.reg);
131
132 spin_unlock_irqrestore(nk->common.lock, flags);
133
134 ccu_helper_wait_for_lock(&nk->common, nk->lock);
135
136 return 0;
137}
138
139const struct clk_ops ccu_nk_ops = {
140 .disable = ccu_nk_disable,
141 .enable = ccu_nk_enable,
142 .is_enabled = ccu_nk_is_enabled,
143
144 .recalc_rate = ccu_nk_recalc_rate,
145 .round_rate = ccu_nk_round_rate,
146 .set_rate = ccu_nk_set_rate,
147};
diff --git a/drivers/clk/sunxi-ng/ccu_nk.h b/drivers/clk/sunxi-ng/ccu_nk.h
new file mode 100644
index 000000000000..4b52da0c29fe
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nk.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_NK_H_
15#define _CCU_NK_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20#include "ccu_div.h"
21#include "ccu_mult.h"
22
23/*
24 * struct ccu_nk - Definition of an N-K clock
25 *
26 * Clocks based on the formula parent * N * K
27 */
28struct ccu_nk {
29 u16 reg;
30 u32 enable;
31 u32 lock;
32
33 struct _ccu_mult n;
34 struct _ccu_mult k;
35
36 unsigned int fixed_post_div;
37
38 struct ccu_common common;
39};
40
41#define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \
42 _nshift, _nwidth, \
43 _kshift, _kwidth, \
44 _gate, _lock, _postdiv, \
45 _flags) \
46 struct ccu_nk _struct = { \
47 .enable = _gate, \
48 .lock = _lock, \
49 .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
50 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
51 .fixed_post_div = _postdiv, \
52 .common = { \
53 .reg = _reg, \
54 .features = CCU_FEATURE_FIXED_POSTDIV, \
55 .hw.init = CLK_HW_INIT(_name, \
56 _parent, \
57 &ccu_nk_ops, \
58 _flags), \
59 }, \
60 }
61
62static inline struct ccu_nk *hw_to_ccu_nk(struct clk_hw *hw)
63{
64 struct ccu_common *common = hw_to_ccu_common(hw);
65
66 return container_of(common, struct ccu_nk, common);
67}
68
69extern const struct clk_ops ccu_nk_ops;
70
71#endif /* _CCU_NK_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
new file mode 100644
index 000000000000..2071822b1e9c
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -0,0 +1,153 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/rational.h>
13
14#include "ccu_gate.h"
15#include "ccu_nkm.h"
16
17struct _ccu_nkm {
18 unsigned long n, max_n;
19 unsigned long k, max_k;
20 unsigned long m, max_m;
21};
22
23static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
24 struct _ccu_nkm *nkm)
25{
26 unsigned long best_rate = 0;
27 unsigned long best_n = 0, best_k = 0, best_m = 0;
28 unsigned long _n, _k, _m;
29
30 for (_k = 1; _k <= nkm->max_k; _k++) {
31 unsigned long tmp_rate;
32
33 rational_best_approximation(rate / _k, parent,
34 nkm->max_n, nkm->max_m, &_n, &_m);
35
36 tmp_rate = parent * _n * _k / _m;
37
38 if (tmp_rate > rate)
39 continue;
40
41 if ((rate - tmp_rate) < (rate - best_rate)) {
42 best_rate = tmp_rate;
43 best_n = _n;
44 best_k = _k;
45 best_m = _m;
46 }
47 }
48
49 nkm->n = best_n;
50 nkm->k = best_k;
51 nkm->m = best_m;
52}
53
54static void ccu_nkm_disable(struct clk_hw *hw)
55{
56 struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
57
58 return ccu_gate_helper_disable(&nkm->common, nkm->enable);
59}
60
61static int ccu_nkm_enable(struct clk_hw *hw)
62{
63 struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
64
65 return ccu_gate_helper_enable(&nkm->common, nkm->enable);
66}
67
68static int ccu_nkm_is_enabled(struct clk_hw *hw)
69{
70 struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
71
72 return ccu_gate_helper_is_enabled(&nkm->common, nkm->enable);
73}
74
75static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
76 unsigned long parent_rate)
77{
78 struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
79 unsigned long n, m, k;
80 u32 reg;
81
82 reg = readl(nkm->common.base + nkm->common.reg);
83
84 n = reg >> nkm->n.shift;
85 n &= (1 << nkm->n.width) - 1;
86
87 k = reg >> nkm->k.shift;
88 k &= (1 << nkm->k.width) - 1;
89
90 m = reg >> nkm->m.shift;
91 m &= (1 << nkm->m.width) - 1;
92
93 return parent_rate * (n + 1) * (k + 1) / (m + 1);
94}
95
96static long ccu_nkm_round_rate(struct clk_hw *hw, unsigned long rate,
97 unsigned long *parent_rate)
98{
99 struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
100 struct _ccu_nkm _nkm;
101
102 _nkm.max_n = 1 << nkm->n.width;
103 _nkm.max_k = 1 << nkm->k.width;
104 _nkm.max_m = 1 << nkm->m.width;
105
106 ccu_nkm_find_best(*parent_rate, rate, &_nkm);
107
108 return *parent_rate * _nkm.n * _nkm.k / _nkm.m;
109}
110
111static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
112 unsigned long parent_rate)
113{
114 struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
115 struct _ccu_nkm _nkm;
116 unsigned long flags;
117 u32 reg;
118
119 _nkm.max_n = 1 << nkm->n.width;
120 _nkm.max_k = 1 << nkm->k.width;
121 _nkm.max_m = 1 << nkm->m.width;
122
123 ccu_nkm_find_best(parent_rate, rate, &_nkm);
124
125 spin_lock_irqsave(nkm->common.lock, flags);
126
127 reg = readl(nkm->common.base + nkm->common.reg);
128 reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift);
129 reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
130 reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);
131
132 reg |= (_nkm.n - 1) << nkm->n.shift;
133 reg |= (_nkm.k - 1) << nkm->k.shift;
134 reg |= (_nkm.m - 1) << nkm->m.shift;
135
136 writel(reg, nkm->common.base + nkm->common.reg);
137
138 spin_unlock_irqrestore(nkm->common.lock, flags);
139
140 ccu_helper_wait_for_lock(&nkm->common, nkm->lock);
141
142 return 0;
143}
144
145const struct clk_ops ccu_nkm_ops = {
146 .disable = ccu_nkm_disable,
147 .enable = ccu_nkm_enable,
148 .is_enabled = ccu_nkm_is_enabled,
149
150 .recalc_rate = ccu_nkm_recalc_rate,
151 .round_rate = ccu_nkm_round_rate,
152 .set_rate = ccu_nkm_set_rate,
153};
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
new file mode 100644
index 000000000000..1936ac1c6b37
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -0,0 +1,68 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_NKM_H_
15#define _CCU_NKM_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20#include "ccu_div.h"
21#include "ccu_mult.h"
22
23/*
24 * struct ccu_nkm - Definition of an N-K-M clock
25 *
26 * Clocks based on the formula parent * N * K / M
27 */
28struct ccu_nkm {
29 u32 enable;
30 u32 lock;
31
32 struct _ccu_mult n;
33 struct _ccu_mult k;
34 struct _ccu_div m;
35
36 struct ccu_common common;
37};
38
39#define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
40 _nshift, _nwidth, \
41 _kshift, _kwidth, \
42 _mshift, _mwidth, \
43 _gate, _lock, _flags) \
44 struct ccu_nkm _struct = { \
45 .enable = _gate, \
46 .lock = _lock, \
47 .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
48 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
49 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
50 .common = { \
51 .reg = _reg, \
52 .hw.init = CLK_HW_INIT(_name, \
53 _parent, \
54 &ccu_nkm_ops, \
55 _flags), \
56 }, \
57 }
58
59static inline struct ccu_nkm *hw_to_ccu_nkm(struct clk_hw *hw)
60{
61 struct ccu_common *common = hw_to_ccu_common(hw);
62
63 return container_of(common, struct ccu_nkm, common);
64}
65
66extern const struct clk_ops ccu_nkm_ops;
67
68#endif /* _CCU_NKM_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
new file mode 100644
index 000000000000..9f2b98e19dc9
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -0,0 +1,167 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/rational.h>
13
14#include "ccu_gate.h"
15#include "ccu_nkmp.h"
16
17struct _ccu_nkmp {
18 unsigned long n, max_n;
19 unsigned long k, max_k;
20 unsigned long m, max_m;
21 unsigned long p, max_p;
22};
23
24static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
25 struct _ccu_nkmp *nkmp)
26{
27 unsigned long best_rate = 0;
28 unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
29 unsigned long _n, _k, _m, _p;
30
31 for (_k = 1; _k <= nkmp->max_k; _k++) {
32 for (_p = 0; _p <= nkmp->max_p; _p++) {
33 unsigned long tmp_rate;
34
35 rational_best_approximation(rate / _k, parent >> _p,
36 nkmp->max_n, nkmp->max_m,
37 &_n, &_m);
38
39 tmp_rate = (parent * _n * _k >> _p) / _m;
40
41 if (tmp_rate > rate)
42 continue;
43
44 if ((rate - tmp_rate) < (rate - best_rate)) {
45 best_rate = tmp_rate;
46 best_n = _n;
47 best_k = _k;
48 best_m = _m;
49 best_p = _p;
50 }
51 }
52 }
53
54 nkmp->n = best_n;
55 nkmp->k = best_k;
56 nkmp->m = best_m;
57 nkmp->p = best_p;
58}
59
60static void ccu_nkmp_disable(struct clk_hw *hw)
61{
62 struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
63
64 return ccu_gate_helper_disable(&nkmp->common, nkmp->enable);
65}
66
67static int ccu_nkmp_enable(struct clk_hw *hw)
68{
69 struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
70
71 return ccu_gate_helper_enable(&nkmp->common, nkmp->enable);
72}
73
74static int ccu_nkmp_is_enabled(struct clk_hw *hw)
75{
76 struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
77
78 return ccu_gate_helper_is_enabled(&nkmp->common, nkmp->enable);
79}
80
81static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
82 unsigned long parent_rate)
83{
84 struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
85 unsigned long n, m, k, p;
86 u32 reg;
87
88 reg = readl(nkmp->common.base + nkmp->common.reg);
89
90 n = reg >> nkmp->n.shift;
91 n &= (1 << nkmp->n.width) - 1;
92
93 k = reg >> nkmp->k.shift;
94 k &= (1 << nkmp->k.width) - 1;
95
96 m = reg >> nkmp->m.shift;
97 m &= (1 << nkmp->m.width) - 1;
98
99 p = reg >> nkmp->p.shift;
100 p &= (1 << nkmp->p.width) - 1;
101
102 return (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
103}
104
105static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *parent_rate)
107{
108 struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
109 struct _ccu_nkmp _nkmp;
110
111 _nkmp.max_n = 1 << nkmp->n.width;
112 _nkmp.max_k = 1 << nkmp->k.width;
113 _nkmp.max_m = 1 << nkmp->m.width;
114 _nkmp.max_p = (1 << nkmp->p.width) - 1;
115
116 ccu_nkmp_find_best(*parent_rate, rate,
117 &_nkmp);
118
119 return (*parent_rate * _nkmp.n * _nkmp.k >> _nkmp.p) / _nkmp.m;
120}
121
122static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
123 unsigned long parent_rate)
124{
125 struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
126 struct _ccu_nkmp _nkmp;
127 unsigned long flags;
128 u32 reg;
129
130 _nkmp.max_n = 1 << nkmp->n.width;
131 _nkmp.max_k = 1 << nkmp->k.width;
132 _nkmp.max_m = 1 << nkmp->m.width;
133 _nkmp.max_p = (1 << nkmp->p.width) - 1;
134
135 ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
136
137 spin_lock_irqsave(nkmp->common.lock, flags);
138
139 reg = readl(nkmp->common.base + nkmp->common.reg);
140 reg &= ~GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift);
141 reg &= ~GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
142 reg &= ~GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
143 reg &= ~GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
144
145 reg |= (_nkmp.n - 1) << nkmp->n.shift;
146 reg |= (_nkmp.k - 1) << nkmp->k.shift;
147 reg |= (_nkmp.m - 1) << nkmp->m.shift;
148 reg |= _nkmp.p << nkmp->p.shift;
149
150 writel(reg, nkmp->common.base + nkmp->common.reg);
151
152 spin_unlock_irqrestore(nkmp->common.lock, flags);
153
154 ccu_helper_wait_for_lock(&nkmp->common, nkmp->lock);
155
156 return 0;
157}
158
159const struct clk_ops ccu_nkmp_ops = {
160 .disable = ccu_nkmp_disable,
161 .enable = ccu_nkmp_enable,
162 .is_enabled = ccu_nkmp_is_enabled,
163
164 .recalc_rate = ccu_nkmp_recalc_rate,
165 .round_rate = ccu_nkmp_round_rate,
166 .set_rate = ccu_nkmp_set_rate,
167};
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
new file mode 100644
index 000000000000..5adb0c92a614
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_NKMP_H_
15#define _CCU_NKMP_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20#include "ccu_div.h"
21#include "ccu_mult.h"
22
23/*
24 * struct ccu_nkmp - Definition of an N-K-M-P clock
25 *
26 * Clocks based on the formula parent * N * K >> P / M
27 */
28struct ccu_nkmp {
29 u32 enable;
30 u32 lock;
31
32 struct _ccu_mult n;
33 struct _ccu_mult k;
34 struct _ccu_div m;
35 struct _ccu_div p;
36
37 struct ccu_common common;
38};
39
40#define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
41 _nshift, _nwidth, \
42 _kshift, _kwidth, \
43 _mshift, _mwidth, \
44 _pshift, _pwidth, \
45 _gate, _lock, _flags) \
46 struct ccu_nkmp _struct = { \
47 .enable = _gate, \
48 .lock = _lock, \
49 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
50 .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \
51 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
52 .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
53 .common = { \
54 .reg = _reg, \
55 .hw.init = CLK_HW_INIT(_name, \
56 _parent, \
57 &ccu_nkmp_ops, \
58 _flags), \
59 }, \
60 }
61
62static inline struct ccu_nkmp *hw_to_ccu_nkmp(struct clk_hw *hw)
63{
64 struct ccu_common *common = hw_to_ccu_common(hw);
65
66 return container_of(common, struct ccu_nkmp, common);
67}
68
69extern const struct clk_ops ccu_nkmp_ops;
70
71#endif /* _CCU_NKMP_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
new file mode 100644
index 000000000000..e35ddd8eec8b
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -0,0 +1,114 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/rational.h>
13
14#include "ccu_frac.h"
15#include "ccu_gate.h"
16#include "ccu_nm.h"
17
18static void ccu_nm_disable(struct clk_hw *hw)
19{
20 struct ccu_nm *nm = hw_to_ccu_nm(hw);
21
22 return ccu_gate_helper_disable(&nm->common, nm->enable);
23}
24
25static int ccu_nm_enable(struct clk_hw *hw)
26{
27 struct ccu_nm *nm = hw_to_ccu_nm(hw);
28
29 return ccu_gate_helper_enable(&nm->common, nm->enable);
30}
31
32static int ccu_nm_is_enabled(struct clk_hw *hw)
33{
34 struct ccu_nm *nm = hw_to_ccu_nm(hw);
35
36 return ccu_gate_helper_is_enabled(&nm->common, nm->enable);
37}
38
39static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
40 unsigned long parent_rate)
41{
42 struct ccu_nm *nm = hw_to_ccu_nm(hw);
43 unsigned long n, m;
44 u32 reg;
45
46 if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac))
47 return ccu_frac_helper_read_rate(&nm->common, &nm->frac);
48
49 reg = readl(nm->common.base + nm->common.reg);
50
51 n = reg >> nm->n.shift;
52 n &= (1 << nm->n.width) - 1;
53
54 m = reg >> nm->m.shift;
55 m &= (1 << nm->m.width) - 1;
56
57 return parent_rate * (n + 1) / (m + 1);
58}
59
60static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
61 unsigned long *parent_rate)
62{
63 struct ccu_nm *nm = hw_to_ccu_nm(hw);
64 unsigned long n, m;
65
66 rational_best_approximation(rate, *parent_rate,
67 1 << nm->n.width, 1 << nm->m.width,
68 &n, &m);
69
70 return *parent_rate * n / m;
71}
72
73static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
74 unsigned long parent_rate)
75{
76 struct ccu_nm *nm = hw_to_ccu_nm(hw);
77 unsigned long flags;
78 unsigned long n, m;
79 u32 reg;
80
81 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
82 return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate);
83 else
84 ccu_frac_helper_disable(&nm->common, &nm->frac);
85
86 rational_best_approximation(rate, parent_rate,
87 1 << nm->n.width, 1 << nm->m.width,
88 &n, &m);
89
90 spin_lock_irqsave(nm->common.lock, flags);
91
92 reg = readl(nm->common.base + nm->common.reg);
93 reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
94 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
95
96 writel(reg | ((m - 1) << nm->m.shift) | ((n - 1) << nm->n.shift),
97 nm->common.base + nm->common.reg);
98
99 spin_unlock_irqrestore(nm->common.lock, flags);
100
101 ccu_helper_wait_for_lock(&nm->common, nm->lock);
102
103 return 0;
104}
105
106const struct clk_ops ccu_nm_ops = {
107 .disable = ccu_nm_disable,
108 .enable = ccu_nm_enable,
109 .is_enabled = ccu_nm_is_enabled,
110
111 .recalc_rate = ccu_nm_recalc_rate,
112 .round_rate = ccu_nm_round_rate,
113 .set_rate = ccu_nm_set_rate,
114};
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
new file mode 100644
index 000000000000..0b7bcd33a2df
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_NM_H_
15#define _CCU_NM_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20#include "ccu_div.h"
21#include "ccu_frac.h"
22#include "ccu_mult.h"
23
24/*
25 * struct ccu_nm - Definition of an N-M clock
26 *
27 * Clocks based on the formula parent * N / M
28 */
29struct ccu_nm {
30 u32 enable;
31 u32 lock;
32
33 struct _ccu_mult n;
34 struct _ccu_div m;
35 struct _ccu_frac frac;
36
37 struct ccu_common common;
38};
39
40#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
41 _nshift, _nwidth, \
42 _mshift, _mwidth, \
43 _frac_en, _frac_sel, \
44 _frac_rate_0, _frac_rate_1, \
45 _gate, _lock, _flags) \
46 struct ccu_nm _struct = { \
47 .enable = _gate, \
48 .lock = _lock, \
49 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
50 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
51 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
52 _frac_rate_0, \
53 _frac_rate_1), \
54 .common = { \
55 .reg = _reg, \
56 .features = CCU_FEATURE_FRACTIONAL, \
57 .hw.init = CLK_HW_INIT(_name, \
58 _parent, \
59 &ccu_nm_ops, \
60 _flags), \
61 }, \
62 }
63
64#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
65 _nshift, _nwidth, \
66 _mshift, _mwidth, \
67 _gate, _lock, _flags) \
68 struct ccu_nm _struct = { \
69 .enable = _gate, \
70 .lock = _lock, \
71 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
72 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
73 .common = { \
74 .reg = _reg, \
75 .hw.init = CLK_HW_INIT(_name, \
76 _parent, \
77 &ccu_nm_ops, \
78 _flags), \
79 }, \
80 }
81
82static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw)
83{
84 struct ccu_common *common = hw_to_ccu_common(hw);
85
86 return container_of(common, struct ccu_nm, common);
87}
88
89extern const struct clk_ops ccu_nm_ops;
90
91#endif /* _CCU_NM_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_phase.c b/drivers/clk/sunxi-ng/ccu_phase.c
new file mode 100644
index 000000000000..400c58ad72fd
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_phase.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/spinlock.h>
13
14#include "ccu_phase.h"
15
16static int ccu_phase_get_phase(struct clk_hw *hw)
17{
18 struct ccu_phase *phase = hw_to_ccu_phase(hw);
19 struct clk_hw *parent, *grandparent;
20 unsigned int parent_rate, grandparent_rate;
21 u16 step, parent_div;
22 u32 reg;
23 u8 delay;
24
25 reg = readl(phase->common.base + phase->common.reg);
26 delay = (reg >> phase->shift);
27 delay &= (1 << phase->width) - 1;
28
29 if (!delay)
30 return 180;
31
32 /* Get our parent clock, it's the one that can adjust its rate */
33 parent = clk_hw_get_parent(hw);
34 if (!parent)
35 return -EINVAL;
36
37 /* And its rate */
38 parent_rate = clk_hw_get_rate(parent);
39 if (!parent_rate)
40 return -EINVAL;
41
42 /* Now, get our parent's parent (most likely some PLL) */
43 grandparent = clk_hw_get_parent(parent);
44 if (!grandparent)
45 return -EINVAL;
46
47 /* And its rate */
48 grandparent_rate = clk_hw_get_rate(grandparent);
49 if (!grandparent_rate)
50 return -EINVAL;
51
52 /* Get our parent clock divider */
53 parent_div = grandparent_rate / parent_rate;
54
55 step = DIV_ROUND_CLOSEST(360, parent_div);
56 return delay * step;
57}
58
59static int ccu_phase_set_phase(struct clk_hw *hw, int degrees)
60{
61 struct ccu_phase *phase = hw_to_ccu_phase(hw);
62 struct clk_hw *parent, *grandparent;
63 unsigned int parent_rate, grandparent_rate;
64 unsigned long flags;
65 u32 reg;
66 u8 delay;
67
68 /* Get our parent clock, it's the one that can adjust its rate */
69 parent = clk_hw_get_parent(hw);
70 if (!parent)
71 return -EINVAL;
72
73 /* And its rate */
74 parent_rate = clk_hw_get_rate(parent);
75 if (!parent_rate)
76 return -EINVAL;
77
78 /* Now, get our parent's parent (most likely some PLL) */
79 grandparent = clk_hw_get_parent(parent);
80 if (!grandparent)
81 return -EINVAL;
82
83 /* And its rate */
84 grandparent_rate = clk_hw_get_rate(grandparent);
85 if (!grandparent_rate)
86 return -EINVAL;
87
88 if (degrees != 180) {
89 u16 step, parent_div;
90
91 /* Get our parent divider */
92 parent_div = grandparent_rate / parent_rate;
93
94 /*
95 * We can only outphase the clocks by multiple of the
96 * PLL's period.
97 *
98 * Since our parent clock is only a divider, and the
99 * formula to get the outphasing in degrees is deg =
100 * 360 * delta / period
101 *
102 * If we simplify this formula, we can see that the
103 * only thing that we're concerned about is the number
104 * of period we want to outphase our clock from, and
105 * the divider set by our parent clock.
106 */
107 step = DIV_ROUND_CLOSEST(360, parent_div);
108 delay = DIV_ROUND_CLOSEST(degrees, step);
109 } else {
110 delay = 0;
111 }
112
113 spin_lock_irqsave(phase->common.lock, flags);
114 reg = readl(phase->common.base + phase->common.reg);
115 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
116 writel(reg | (delay << phase->shift),
117 phase->common.base + phase->common.reg);
118 spin_unlock_irqrestore(phase->common.lock, flags);
119
120 return 0;
121}
122
123const struct clk_ops ccu_phase_ops = {
124 .get_phase = ccu_phase_get_phase,
125 .set_phase = ccu_phase_set_phase,
126};
diff --git a/drivers/clk/sunxi-ng/ccu_phase.h b/drivers/clk/sunxi-ng/ccu_phase.h
new file mode 100644
index 000000000000..75a091a4c565
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_phase.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_PHASE_H_
15#define _CCU_PHASE_H_
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20
21struct ccu_phase {
22 u8 shift;
23 u8 width;
24
25 struct ccu_common common;
26};
27
28#define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \
29 struct ccu_phase _struct = { \
30 .shift = _shift, \
31 .width = _width, \
32 .common = { \
33 .reg = _reg, \
34 .hw.init = CLK_HW_INIT(_name, \
35 _parent, \
36 &ccu_phase_ops, \
37 _flags), \
38 } \
39 }
40
41static inline struct ccu_phase *hw_to_ccu_phase(struct clk_hw *hw)
42{
43 struct ccu_common *common = hw_to_ccu_common(hw);
44
45 return container_of(common, struct ccu_phase, common);
46}
47
48extern const struct clk_ops ccu_phase_ops;
49
50#endif /* _CCU_PHASE_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_reset.c b/drivers/clk/sunxi-ng/ccu_reset.c
new file mode 100644
index 000000000000..6c31d48783a7
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_reset.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#include <linux/io.h>
12#include <linux/reset-controller.h>
13
14#include "ccu_reset.h"
15
16static int ccu_reset_assert(struct reset_controller_dev *rcdev,
17 unsigned long id)
18{
19 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
20 const struct ccu_reset_map *map = &ccu->reset_map[id];
21 unsigned long flags;
22 u32 reg;
23
24 spin_lock_irqsave(ccu->lock, flags);
25
26 reg = readl(ccu->base + map->reg);
27 writel(reg & ~map->bit, ccu->base + map->reg);
28
29 spin_unlock_irqrestore(ccu->lock, flags);
30
31 return 0;
32}
33
34static int ccu_reset_deassert(struct reset_controller_dev *rcdev,
35 unsigned long id)
36{
37 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
38 const struct ccu_reset_map *map = &ccu->reset_map[id];
39 unsigned long flags;
40 u32 reg;
41
42 spin_lock_irqsave(ccu->lock, flags);
43
44 reg = readl(ccu->base + map->reg);
45 writel(reg | map->bit, ccu->base + map->reg);
46
47 spin_unlock_irqrestore(ccu->lock, flags);
48
49 return 0;
50}
51
52const struct reset_control_ops ccu_reset_ops = {
53 .assert = ccu_reset_assert,
54 .deassert = ccu_reset_deassert,
55};
diff --git a/drivers/clk/sunxi-ng/ccu_reset.h b/drivers/clk/sunxi-ng/ccu_reset.h
new file mode 100644
index 000000000000..36a4679210bd
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_reset.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_RESET_H_
15#define _CCU_RESET_H_
16
17#include <linux/reset-controller.h>
18
19struct ccu_reset_map {
20 u16 reg;
21 u32 bit;
22};
23
24
25struct ccu_reset {
26 void __iomem *base;
27 struct ccu_reset_map *reset_map;
28 spinlock_t *lock;
29
30 struct reset_controller_dev rcdev;
31};
32
33static inline struct ccu_reset *rcdev_to_ccu_reset(struct reset_controller_dev *rcdev)
34{
35 return container_of(rcdev, struct ccu_reset, rcdev);
36}
37
38extern const struct reset_control_ops ccu_reset_ops;
39
40#endif /* _CCU_RESET_H_ */
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index ddefe9668863..dfe5e3e32d28 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -12,7 +12,6 @@
12#include <linux/delay.h> 12#include <linux/delay.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of_address.h> 15#include <linux/of_address.h>
17#include <linux/slab.h> 16#include <linux/slab.h>
18#include <linux/string.h> 17#include <linux/string.h>
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index 68021fa5ecd9..09cdb9874636 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/module.h> 12#include <linux/init.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/of_device.h> 14#include <linux/of_device.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
@@ -33,7 +33,6 @@ static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
33 { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates }, 33 { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
34 { /* sentinel */ } 34 { /* sentinel */ }
35}; 35};
36MODULE_DEVICE_TABLE(of, sun6i_a31_apb0_gates_clk_dt_ids);
37 36
38static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) 37static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
39{ 38{
@@ -102,8 +101,4 @@ static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
102 }, 101 },
103 .probe = sun6i_a31_apb0_gates_clk_probe, 102 .probe = sun6i_a31_apb0_gates_clk_probe,
104}; 103};
105module_platform_driver(sun6i_a31_apb0_gates_clk_driver); 104builtin_platform_driver(sun6i_a31_apb0_gates_clk_driver);
106
107MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
108MODULE_DESCRIPTION("Allwinner A31 APB0 gate clocks driver");
109MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c
index e703e1895b76..b9c8d359288c 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0.c
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/module.h> 12#include <linux/init.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15
@@ -61,7 +61,6 @@ static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
61 { .compatible = "allwinner,sun6i-a31-apb0-clk" }, 61 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
62 { /* sentinel */ } 62 { /* sentinel */ }
63}; 63};
64MODULE_DEVICE_TABLE(of, sun6i_a31_apb0_clk_dt_ids);
65 64
66static struct platform_driver sun6i_a31_apb0_clk_driver = { 65static struct platform_driver sun6i_a31_apb0_clk_driver = {
67 .driver = { 66 .driver = {
@@ -70,8 +69,4 @@ static struct platform_driver sun6i_a31_apb0_clk_driver = {
70 }, 69 },
71 .probe = sun6i_a31_apb0_clk_probe, 70 .probe = sun6i_a31_apb0_clk_probe,
72}; 71};
73module_platform_driver(sun6i_a31_apb0_clk_driver); 72builtin_platform_driver(sun6i_a31_apb0_clk_driver);
74
75MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
76MODULE_DESCRIPTION("Allwinner A31 APB0 clock Driver");
77MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index 84a187e55360..64ca3e9e38e6 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -10,7 +10,7 @@
10 10
11#include <linux/bitops.h> 11#include <linux/bitops.h>
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/module.h> 13#include <linux/init.h>
14#include <linux/of.h> 14#include <linux/of.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/spinlock.h> 16#include <linux/spinlock.h>
@@ -91,32 +91,17 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
91 return 0; 91 return 0;
92} 92}
93 93
94static int sun6i_a31_ar100_clk_remove(struct platform_device *pdev)
95{
96 struct device_node *np = pdev->dev.of_node;
97 struct clk *clk = platform_get_drvdata(pdev);
98
99 sunxi_factors_unregister(np, clk);
100
101 return 0;
102}
103
104static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = { 94static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
105 { .compatible = "allwinner,sun6i-a31-ar100-clk" }, 95 { .compatible = "allwinner,sun6i-a31-ar100-clk" },
106 { /* sentinel */ } 96 { /* sentinel */ }
107}; 97};
108MODULE_DEVICE_TABLE(of, sun6i_a31_ar100_clk_dt_ids);
109 98
110static struct platform_driver sun6i_a31_ar100_clk_driver = { 99static struct platform_driver sun6i_a31_ar100_clk_driver = {
111 .driver = { 100 .driver = {
112 .name = "sun6i-a31-ar100-clk", 101 .name = "sun6i-a31-ar100-clk",
113 .of_match_table = sun6i_a31_ar100_clk_dt_ids, 102 .of_match_table = sun6i_a31_ar100_clk_dt_ids,
103 .suppress_bind_attrs = true,
114 }, 104 },
115 .probe = sun6i_a31_ar100_clk_probe, 105 .probe = sun6i_a31_ar100_clk_probe,
116 .remove = sun6i_a31_ar100_clk_remove,
117}; 106};
118module_platform_driver(sun6i_a31_ar100_clk_driver); 107builtin_platform_driver(sun6i_a31_ar100_clk_driver);
119
120MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
121MODULE_DESCRIPTION("Allwinner A31 AR100 clock Driver");
122MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 2ea61debffc1..a5666e1d0ce7 100644
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -15,7 +15,7 @@
15 */ 15 */
16 16
17#include <linux/clk-provider.h> 17#include <linux/clk-provider.h>
18#include <linux/module.h> 18#include <linux/init.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/of_address.h> 20#include <linux/of_address.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
@@ -108,7 +108,6 @@ static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
108 { .compatible = "allwinner,sun8i-a23-apb0-clk" }, 108 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
109 { /* sentinel */ } 109 { /* sentinel */ }
110}; 110};
111MODULE_DEVICE_TABLE(of, sun8i_a23_apb0_clk_dt_ids);
112 111
113static struct platform_driver sun8i_a23_apb0_clk_driver = { 112static struct platform_driver sun8i_a23_apb0_clk_driver = {
114 .driver = { 113 .driver = {
@@ -117,8 +116,4 @@ static struct platform_driver sun8i_a23_apb0_clk_driver = {
117 }, 116 },
118 .probe = sun8i_a23_apb0_clk_probe, 117 .probe = sun8i_a23_apb0_clk_probe,
119}; 118};
120module_platform_driver(sun8i_a23_apb0_clk_driver); 119builtin_platform_driver(sun8i_a23_apb0_clk_driver);
121
122MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
123MODULE_DESCRIPTION("Allwinner A23 APB0 clock Driver");
124MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
index 716737388b7d..6041bdba2e97 100644
--- a/drivers/clk/sunxi/clk-sun9i-mmc.c
+++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
@@ -16,7 +16,7 @@
16 16
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
19#include <linux/module.h> 19#include <linux/init.h>
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_device.h> 21#include <linux/of_device.h>
22#include <linux/reset.h> 22#include <linux/reset.h>
@@ -183,39 +183,17 @@ err_clk_register:
183 return ret; 183 return ret;
184} 184}
185 185
186static int sun9i_a80_mmc_config_clk_remove(struct platform_device *pdev)
187{
188 struct device_node *np = pdev->dev.of_node;
189 struct sun9i_mmc_clk_data *data = platform_get_drvdata(pdev);
190 struct clk_onecell_data *clk_data = &data->clk_data;
191 int i;
192
193 reset_controller_unregister(&data->rcdev);
194 of_clk_del_provider(np);
195 for (i = 0; i < clk_data->clk_num; i++)
196 clk_unregister(clk_data->clks[i]);
197
198 reset_control_assert(data->reset);
199
200 return 0;
201}
202
203static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = { 186static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
204 { .compatible = "allwinner,sun9i-a80-mmc-config-clk" }, 187 { .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
205 { /* sentinel */ } 188 { /* sentinel */ }
206}; 189};
207MODULE_DEVICE_TABLE(of, sun9i_a80_mmc_config_clk_dt_ids);
208 190
209static struct platform_driver sun9i_a80_mmc_config_clk_driver = { 191static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
210 .driver = { 192 .driver = {
211 .name = "sun9i-a80-mmc-config-clk", 193 .name = "sun9i-a80-mmc-config-clk",
194 .suppress_bind_attrs = true,
212 .of_match_table = sun9i_a80_mmc_config_clk_dt_ids, 195 .of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
213 }, 196 },
214 .probe = sun9i_a80_mmc_config_clk_probe, 197 .probe = sun9i_a80_mmc_config_clk_probe,
215 .remove = sun9i_a80_mmc_config_clk_remove,
216}; 198};
217module_platform_driver(sun9i_a80_mmc_config_clk_driver); 199builtin_platform_driver(sun9i_a80_mmc_config_clk_driver);
218
219MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
220MODULE_DESCRIPTION("Allwinner A80 MMC clock/reset Driver");
221MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 36c974916d4f..5738635c5274 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -238,7 +238,6 @@ enum clk_id {
238 tegra_clk_sor0, 238 tegra_clk_sor0,
239 tegra_clk_sor0_lvds, 239 tegra_clk_sor0_lvds,
240 tegra_clk_sor1, 240 tegra_clk_sor1,
241 tegra_clk_sor1_brick,
242 tegra_clk_sor1_src, 241 tegra_clk_sor1_src,
243 tegra_clk_spdif, 242 tegra_clk_spdif,
244 tegra_clk_spdif_2x, 243 tegra_clk_spdif_2x,
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 4e194ecc8d5e..b3855360d6bc 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -191,6 +191,53 @@
191#define PLLSS_REF_SRC_SEL_SHIFT 25 191#define PLLSS_REF_SRC_SEL_SHIFT 25
192#define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT) 192#define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
193 193
194#define UTMIP_PLL_CFG1 0x484
195#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
196#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
197#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
198#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
199#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
200#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
201#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
202
203#define UTMIP_PLL_CFG2 0x488
204#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
205#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
206#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
207#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
208#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
209#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
210#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
211#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
212#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
213#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
214#define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
215
216#define UTMIPLL_HW_PWRDN_CFG0 0x52c
217#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
218#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
219#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
220#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
221#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
222#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
223#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
224#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
225
226#define PLLU_HW_PWRDN_CFG0 0x530
227#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
228#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
229#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
230#define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
231#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
232#define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
233
234#define XUSB_PLL_CFG0 0x534
235#define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
236#define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
237
238#define PLLU_BASE_CLKENABLE_USB BIT(21)
239#define PLLU_BASE_OVERRIDE BIT(24)
240
194#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 241#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
195#define pll_readl_base(p) pll_readl(p->params->base_reg, p) 242#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
196#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 243#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
@@ -973,6 +1020,133 @@ const struct clk_ops tegra_clk_plle_ops = {
973 .enable = clk_plle_enable, 1020 .enable = clk_plle_enable,
974}; 1021};
975 1022
1023/*
1024 * Structure defining the fields for USB UTMI clocks Parameters.
1025 */
1026struct utmi_clk_param {
1027 /* Oscillator Frequency in Hz */
1028 u32 osc_frequency;
1029 /* UTMIP PLL Enable Delay Count */
1030 u8 enable_delay_count;
1031 /* UTMIP PLL Stable count */
1032 u8 stable_count;
1033 /* UTMIP PLL Active delay count */
1034 u8 active_delay_count;
1035 /* UTMIP PLL Xtal frequency count */
1036 u8 xtal_freq_count;
1037};
1038
1039static const struct utmi_clk_param utmi_parameters[] = {
1040 {
1041 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1042 .stable_count = 0x33, .active_delay_count = 0x05,
1043 .xtal_freq_count = 0x7f
1044 }, {
1045 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1046 .stable_count = 0x4b, .active_delay_count = 0x06,
1047 .xtal_freq_count = 0xbb
1048 }, {
1049 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1050 .stable_count = 0x2f, .active_delay_count = 0x04,
1051 .xtal_freq_count = 0x76
1052 }, {
1053 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1054 .stable_count = 0x66, .active_delay_count = 0x09,
1055 .xtal_freq_count = 0xfe
1056 }, {
1057 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1058 .stable_count = 0x41, .active_delay_count = 0x0a,
1059 .xtal_freq_count = 0xa4
1060 }, {
1061 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1062 .stable_count = 0x0, .active_delay_count = 0x6,
1063 .xtal_freq_count = 0x80
1064 },
1065};
1066
1067static int clk_pllu_enable(struct clk_hw *hw)
1068{
1069 struct tegra_clk_pll *pll = to_clk_pll(hw);
1070 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1071 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1072 const struct utmi_clk_param *params = NULL;
1073 unsigned long flags = 0, input_rate;
1074 unsigned int i;
1075 int ret = 0;
1076 u32 value;
1077
1078 if (!osc) {
1079 pr_err("%s: failed to get OSC clock\n", __func__);
1080 return -EINVAL;
1081 }
1082
1083 input_rate = clk_hw_get_rate(osc);
1084
1085 if (pll->lock)
1086 spin_lock_irqsave(pll->lock, flags);
1087
1088 _clk_pll_enable(hw);
1089
1090 ret = clk_pll_wait_for_lock(pll);
1091 if (ret < 0)
1092 goto out;
1093
1094 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1095 if (input_rate == utmi_parameters[i].osc_frequency) {
1096 params = &utmi_parameters[i];
1097 break;
1098 }
1099 }
1100
1101 if (!params) {
1102 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1103 input_rate);
1104 ret = -EINVAL;
1105 goto out;
1106 }
1107
1108 value = pll_readl_base(pll);
1109 value &= ~PLLU_BASE_OVERRIDE;
1110 pll_writel_base(value, pll);
1111
1112 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1113 /* Program UTMIP PLL stable and active counts */
1114 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1115 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1116 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1117 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1118 /* Remove power downs from UTMIP PLL control bits */
1119 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1120 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1121 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1122 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1123
1124 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1125 /* Program UTMIP PLL delay and oscillator frequency counts */
1126 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1127 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1128 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1129 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1130 /* Remove power downs from UTMIP PLL control bits */
1131 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1132 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1133 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1134 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1135
1136out:
1137 if (pll->lock)
1138 spin_unlock_irqrestore(pll->lock, flags);
1139
1140 return ret;
1141}
1142
1143static const struct clk_ops tegra_clk_pllu_ops = {
1144 .is_enabled = clk_pll_is_enabled,
1145 .enable = clk_pllu_enable,
1146 .disable = clk_pll_disable,
1147 .recalc_rate = clk_pll_recalc_rate,
1148};
1149
976static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 1150static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
977 unsigned long parent_rate) 1151 unsigned long parent_rate)
978{ 1152{
@@ -1505,6 +1679,112 @@ static void clk_plle_tegra114_disable(struct clk_hw *hw)
1505 if (pll->lock) 1679 if (pll->lock)
1506 spin_unlock_irqrestore(pll->lock, flags); 1680 spin_unlock_irqrestore(pll->lock, flags);
1507} 1681}
1682
1683static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1684{
1685 struct tegra_clk_pll *pll = to_clk_pll(hw);
1686 const struct utmi_clk_param *params = NULL;
1687 struct clk *osc = __clk_lookup("osc");
1688 unsigned long flags = 0, input_rate;
1689 unsigned int i;
1690 int ret = 0;
1691 u32 value;
1692
1693 if (!osc) {
1694 pr_err("%s: failed to get OSC clock\n", __func__);
1695 return -EINVAL;
1696 }
1697
1698 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1699
1700 if (pll->lock)
1701 spin_lock_irqsave(pll->lock, flags);
1702
1703 _clk_pll_enable(hw);
1704
1705 ret = clk_pll_wait_for_lock(pll);
1706 if (ret < 0)
1707 goto out;
1708
1709 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1710 if (input_rate == utmi_parameters[i].osc_frequency) {
1711 params = &utmi_parameters[i];
1712 break;
1713 }
1714 }
1715
1716 if (!params) {
1717 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1718 input_rate);
1719 ret = -EINVAL;
1720 goto out;
1721 }
1722
1723 value = pll_readl_base(pll);
1724 value &= ~PLLU_BASE_OVERRIDE;
1725 pll_writel_base(value, pll);
1726
1727 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1728 /* Program UTMIP PLL stable and active counts */
1729 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1730 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1731 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1732 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1733 /* Remove power downs from UTMIP PLL control bits */
1734 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1735 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1736 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1737 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1738
1739 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1740 /* Program UTMIP PLL delay and oscillator frequency counts */
1741 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1742 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1743 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1744 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1745 /* Remove power downs from UTMIP PLL control bits */
1746 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1747 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1748 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1749 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1750 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1751
1752 /* Setup HW control of UTMIPLL */
1753 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1754 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1755 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1756 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1757 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1758
1759 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1760 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1761 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1762 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1763
1764 udelay(1);
1765
1766 /*
1767 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1768 * to USB2
1769 */
1770 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1771 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1772 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1773 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1774
1775 udelay(1);
1776
1777 /* Enable HW control of UTMIPLL */
1778 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1779 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1780 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1781
1782out:
1783 if (pll->lock)
1784 spin_unlock_irqrestore(pll->lock, flags);
1785
1786 return ret;
1787}
1508#endif 1788#endif
1509 1789
1510static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1790static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
@@ -1614,6 +1894,27 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1614 return clk; 1894 return clk;
1615} 1895}
1616 1896
1897struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1898 void __iomem *clk_base, unsigned long flags,
1899 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1900{
1901 struct tegra_clk_pll *pll;
1902 struct clk *clk;
1903
1904 pll_params->flags |= TEGRA_PLLU;
1905
1906 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1907 if (IS_ERR(pll))
1908 return ERR_CAST(pll);
1909
1910 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1911 &tegra_clk_pllu_ops);
1912 if (IS_ERR(clk))
1913 kfree(pll);
1914
1915 return clk;
1916}
1917
1617#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 1918#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1618 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 1919 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1619 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 1920 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
@@ -1652,6 +1953,12 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1652 .recalc_rate = clk_pll_recalc_rate, 1953 .recalc_rate = clk_pll_recalc_rate,
1653}; 1954};
1654 1955
1956static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1957 .is_enabled = clk_pll_is_enabled,
1958 .enable = clk_pllu_tegra114_enable,
1959 .disable = clk_pll_disable,
1960 .recalc_rate = clk_pll_recalc_rate,
1961};
1655 1962
1656struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1963struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1657 void __iomem *clk_base, void __iomem *pmc, 1964 void __iomem *clk_base, void __iomem *pmc,
@@ -1919,6 +2226,29 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1919 2226
1920 return clk; 2227 return clk;
1921} 2228}
2229
2230struct clk *
2231tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2232 void __iomem *clk_base, unsigned long flags,
2233 struct tegra_clk_pll_params *pll_params,
2234 spinlock_t *lock)
2235{
2236 struct tegra_clk_pll *pll;
2237 struct clk *clk;
2238
2239 pll_params->flags |= TEGRA_PLLU;
2240
2241 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2242 if (IS_ERR(pll))
2243 return ERR_CAST(pll);
2244
2245 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2246 &tegra_clk_pllu_tegra114_ops);
2247 if (IS_ERR(clk))
2248 kfree(pll);
2249
2250 return clk;
2251}
1922#endif 2252#endif
1923 2253
1924#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) 2254#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
@@ -2187,6 +2517,152 @@ static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2187 return val & PLLE_BASE_ENABLE ? 1 : 0; 2517 return val & PLLE_BASE_ENABLE ? 1 : 0;
2188} 2518}
2189 2519
2520static int clk_pllu_tegra210_enable(struct clk_hw *hw)
2521{
2522 struct tegra_clk_pll *pll = to_clk_pll(hw);
2523 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
2524 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
2525 const struct utmi_clk_param *params = NULL;
2526 unsigned long flags = 0, input_rate;
2527 unsigned int i;
2528 int ret = 0;
2529 u32 value;
2530
2531 if (!osc) {
2532 pr_err("%s: failed to get OSC clock\n", __func__);
2533 return -EINVAL;
2534 }
2535
2536 input_rate = clk_hw_get_rate(osc);
2537
2538 if (pll->lock)
2539 spin_lock_irqsave(pll->lock, flags);
2540
2541 _clk_pll_enable(hw);
2542
2543 ret = clk_pll_wait_for_lock(pll);
2544 if (ret < 0)
2545 goto out;
2546
2547 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2548 if (input_rate == utmi_parameters[i].osc_frequency) {
2549 params = &utmi_parameters[i];
2550 break;
2551 }
2552 }
2553
2554 if (!params) {
2555 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2556 input_rate);
2557 ret = -EINVAL;
2558 goto out;
2559 }
2560
2561 value = pll_readl_base(pll);
2562 value &= ~PLLU_BASE_OVERRIDE;
2563 pll_writel_base(value, pll);
2564
2565 /* Put PLLU under HW control */
2566 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2567 value |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2568 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2569 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2570 value &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2571 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2572 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2573
2574 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2575 value &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY;
2576 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2577
2578 udelay(1);
2579
2580 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2581 value |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2582 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2583
2584 udelay(1);
2585
2586 /* Disable PLLU clock branch to UTMIPLL since it uses OSC */
2587 value = pll_readl_base(pll);
2588 value &= ~PLLU_BASE_CLKENABLE_USB;
2589 pll_writel_base(value, pll);
2590
2591 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2592 if (value & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE) {
2593 pr_debug("UTMIPLL already enabled\n");
2594 goto out;
2595 }
2596
2597 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2598 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2599
2600 /* Program UTMIP PLL stable and active counts */
2601 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2602 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2603 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
2604 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2605 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
2606 value |= UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN;
2607 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2608
2609 /* Program UTMIP PLL delay and oscillator frequency counts */
2610 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2611 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2612 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
2613 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2614 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
2615 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2616
2617 /* Remove power downs from UTMIP PLL control bits */
2618 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2619 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2620 value |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2621 writel(value, pll->clk_base + UTMIP_PLL_CFG1);
2622
2623 udelay(1);
2624
2625 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2626 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2627 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2628 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2629 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2630 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2631 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2632 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2633 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2634
2635 /* Setup HW control of UTMIPLL */
2636 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2637 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2638 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2639 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2640
2641 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2642 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2643 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2644 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2645
2646 udelay(1);
2647
2648 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2649 value &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2650 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2651
2652 udelay(1);
2653
2654 /* Enable HW control of UTMIPLL */
2655 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2656 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2657 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2658
2659out:
2660 if (pll->lock)
2661 spin_unlock_irqrestore(pll->lock, flags);
2662
2663 return ret;
2664}
2665
2190static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2666static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2191 .is_enabled = clk_plle_tegra210_is_enabled, 2667 .is_enabled = clk_plle_tegra210_is_enabled,
2192 .enable = clk_plle_tegra210_enable, 2668 .enable = clk_plle_tegra210_enable,
@@ -2194,6 +2670,13 @@ static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2194 .recalc_rate = clk_pll_recalc_rate, 2670 .recalc_rate = clk_pll_recalc_rate,
2195}; 2671};
2196 2672
2673static const struct clk_ops tegra_clk_pllu_tegra210_ops = {
2674 .is_enabled = clk_pll_is_enabled,
2675 .enable = clk_pllu_tegra210_enable,
2676 .disable = clk_pll_disable,
2677 .recalc_rate = clk_pllre_recalc_rate,
2678};
2679
2197struct clk *tegra_clk_register_plle_tegra210(const char *name, 2680struct clk *tegra_clk_register_plle_tegra210(const char *name,
2198 const char *parent_name, 2681 const char *parent_name,
2199 void __iomem *clk_base, unsigned long flags, 2682 void __iomem *clk_base, unsigned long flags,
@@ -2434,4 +2917,26 @@ struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2434 2917
2435 return clk; 2918 return clk;
2436} 2919}
2920
2921struct clk *tegra_clk_register_pllu_tegra210(const char *name,
2922 const char *parent_name, void __iomem *clk_base,
2923 unsigned long flags, struct tegra_clk_pll_params *pll_params,
2924 spinlock_t *lock)
2925{
2926 struct tegra_clk_pll *pll;
2927 struct clk *clk;
2928
2929 pll_params->flags |= TEGRA_PLLU;
2930
2931 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2932 if (IS_ERR(pll))
2933 return ERR_CAST(pll);
2934
2935 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2936 &tegra_clk_pllu_tegra210_ops);
2937 if (IS_ERR(clk))
2938 kfree(pll);
2939
2940 return clk;
2941}
2437#endif 2942#endif
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 29d04c663abf..4ce4e7fb1124 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -594,15 +594,17 @@ static u32 mux_pllp_plld_plld2_clkm_idx[] = {
594 [0] = 0, [1] = 2, [2] = 5, [3] = 6 594 [0] = 0, [1] = 2, [2] = 5, [3] = 6
595}; 595};
596 596
597static const char *mux_plldp_sor1_src[] = { 597static const char *mux_sor_safe_sor1_brick_sor1_src[] = {
598 "pll_dp", "clk_sor1_src" 598 /*
599}; 599 * Bit 0 of the mux selects sor1_brick, irrespective of bit 1, so the
600#define mux_plldp_sor1_src_idx NULL 600 * sor1_brick parent appears twice in the list below. This is merely
601 601 * to support clk_get_parent() if firmware happened to set these bits
602static const char *mux_clkm_sor1_brick_sor1_src[] = { 602 * to 0b11. While not an invalid setting, code should always set the
603 "clk_m", "sor1_brick", "sor1_src", "sor1_brick" 603 * bits to 0b01 to select sor1_brick.
604}; 604 */
605#define mux_clkm_sor1_brick_sor1_src_idx NULL 605 "sor_safe", "sor1_brick", "sor1_src", "sor1_brick"
606};
607#define mux_sor_safe_sor1_brick_sor1_src_idx NULL
606 608
607static const char *mux_pllp_pllre_clkm[] = { 609static const char *mux_pllp_pllre_clkm[] = {
608 "pll_p", "pll_re_out1", "clk_m" 610 "pll_p", "pll_re_out1", "clk_m"
@@ -778,8 +780,7 @@ static struct tegra_periph_init_data periph_clks[] = {
778 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), 780 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
779 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), 781 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
780 MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock), 782 MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
781 NODIV("sor1_brick", mux_plldp_sor1_src, CLK_SOURCE_SOR1, 14, MASK(1), 183, 0, tegra_clk_sor1_brick, &sor1_lock), 783 NODIV("sor1", mux_sor_safe_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 14, MASK(2), 183, 0, tegra_clk_sor1, &sor1_lock),
782 NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
783 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), 784 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
784 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), 785 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
785 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c), 786 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
@@ -791,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = {
791 792
792static struct tegra_periph_init_data gate_clks[] = { 793static struct tegra_periph_init_data gate_clks[] = {
793 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), 794 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
794 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), 795 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
795 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), 796 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
796 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), 797 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
797 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), 798 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index b78054fac0a8..64da7b79a6e4 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -113,32 +113,6 @@
113 113
114#define CCLKG_BURST_POLICY 0x368 114#define CCLKG_BURST_POLICY 0x368
115 115
116#define UTMIP_PLL_CFG2 0x488
117#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
118#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
119#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
120#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
121#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
122
123#define UTMIP_PLL_CFG1 0x484
124#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
125#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
126#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
127#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
128#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
129#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
130#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
131
132#define UTMIPLL_HW_PWRDN_CFG0 0x52c
133#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
134#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
135#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
136#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
137#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
138#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
139#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
140#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
141
142#define CLK_SOURCE_CSITE 0x1d4 116#define CLK_SOURCE_CSITE 0x1d4
143#define CLK_SOURCE_EMC 0x19c 117#define CLK_SOURCE_EMC 0x19c
144 118
@@ -649,43 +623,6 @@ static unsigned long tegra114_input_freq[] = {
649 623
650#define MASK(x) (BIT(x) - 1) 624#define MASK(x) (BIT(x) - 1)
651 625
652struct utmi_clk_param {
653 /* Oscillator Frequency in KHz */
654 u32 osc_frequency;
655 /* UTMIP PLL Enable Delay Count */
656 u8 enable_delay_count;
657 /* UTMIP PLL Stable count */
658 u8 stable_count;
659 /* UTMIP PLL Active delay count */
660 u8 active_delay_count;
661 /* UTMIP PLL Xtal frequency count */
662 u8 xtal_freq_count;
663};
664
665static const struct utmi_clk_param utmi_parameters[] = {
666 {
667 .osc_frequency = 13000000, .enable_delay_count = 0x02,
668 .stable_count = 0x33, .active_delay_count = 0x05,
669 .xtal_freq_count = 0x7f
670 }, {
671 .osc_frequency = 19200000, .enable_delay_count = 0x03,
672 .stable_count = 0x4b, .active_delay_count = 0x06,
673 .xtal_freq_count = 0xbb
674 }, {
675 .osc_frequency = 12000000, .enable_delay_count = 0x02,
676 .stable_count = 0x2f, .active_delay_count = 0x04,
677 .xtal_freq_count = 0x76
678 }, {
679 .osc_frequency = 26000000, .enable_delay_count = 0x04,
680 .stable_count = 0x66, .active_delay_count = 0x09,
681 .xtal_freq_count = 0xfe
682 }, {
683 .osc_frequency = 16800000, .enable_delay_count = 0x03,
684 .stable_count = 0x41, .active_delay_count = 0x0a,
685 .xtal_freq_count = 0xa4
686 },
687};
688
689/* peripheral mux definitions */ 626/* peripheral mux definitions */
690 627
691static const char *mux_plld_out0_plld2_out0[] = { 628static const char *mux_plld_out0_plld2_out0[] = {
@@ -986,92 +923,9 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
986 923
987} 924}
988 925
989static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
990{
991 unsigned int i;
992 u32 reg;
993
994 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
995 if (osc_freq == utmi_parameters[i].osc_frequency)
996 break;
997 }
998
999 if (i >= ARRAY_SIZE(utmi_parameters)) {
1000 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1001 osc_freq);
1002 return;
1003 }
1004
1005 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1006
1007 /* Program UTMIP PLL stable and active counts */
1008 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1009 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1010 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1011
1012 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1013
1014 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1015 active_delay_count);
1016
1017 /* Remove power downs from UTMIP PLL control bits */
1018 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1019 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1020 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1021
1022 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1023
1024 /* Program UTMIP PLL delay and oscillator frequency counts */
1025 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1026 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1027
1028 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1029 enable_delay_count);
1030
1031 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1032 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1033 xtal_freq_count);
1034
1035 /* Remove power downs from UTMIP PLL control bits */
1036 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1037 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1038 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1039 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1040 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1041
1042 /* Setup HW control of UTMIPLL */
1043 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1044 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1045 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1046 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1047 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1048
1049 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1050 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1051 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1052 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1053
1054 udelay(1);
1055
1056 /* Setup SW override of UTMIPLL assuming USB2.0
1057 ports are assigned to USB2 */
1058 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1059 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1060 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1061 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1062
1063 udelay(1);
1064
1065 /* Enable HW control UTMIPLL */
1066 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1067 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1068 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1069}
1070
1071static void __init tegra114_pll_init(void __iomem *clk_base, 926static void __init tegra114_pll_init(void __iomem *clk_base,
1072 void __iomem *pmc) 927 void __iomem *pmc)
1073{ 928{
1074 u32 val;
1075 struct clk *clk; 929 struct clk *clk;
1076 930
1077 /* PLLC */ 931 /* PLLC */
@@ -1118,16 +972,10 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1118 CLK_SET_RATE_PARENT, 1, 1); 972 CLK_SET_RATE_PARENT, 1, 1);
1119 973
1120 /* PLLU */ 974 /* PLLU */
1121 val = readl(clk_base + pll_u_params.base_reg); 975 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
1122 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 976 &pll_u_params, &pll_u_lock);
1123 writel(val, clk_base + pll_u_params.base_reg);
1124
1125 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1126 &pll_u_params, &pll_u_lock);
1127 clks[TEGRA114_CLK_PLL_U] = clk; 977 clks[TEGRA114_CLK_PLL_U] = clk;
1128 978
1129 tegra114_utmi_param_configure(clk_base);
1130
1131 /* PLLU_480M */ 979 /* PLLU_480M */
1132 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 980 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1133 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 981 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index f4fbbf16a056..a112d3d2bff1 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -99,32 +99,6 @@
99 99
100#define CCLKG_BURST_POLICY 0x368 100#define CCLKG_BURST_POLICY 0x368
101 101
102#define UTMIP_PLL_CFG2 0x488
103#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
104#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
105#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
106#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
107#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
108
109#define UTMIP_PLL_CFG1 0x484
110#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
111#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
112#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
113#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
114#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
115#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
116#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
117
118#define UTMIPLL_HW_PWRDN_CFG0 0x52c
119#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
120#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
121#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
122#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
123#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
124#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
125#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
126#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
127
128/* Tegra CPU clock and reset control regs */ 102/* Tegra CPU clock and reset control regs */
129#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 103#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
130 104
@@ -764,43 +738,6 @@ static struct tegra_clk_pll_params pll_u_params = {
764 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 738 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
765}; 739};
766 740
767struct utmi_clk_param {
768 /* Oscillator Frequency in KHz */
769 u32 osc_frequency;
770 /* UTMIP PLL Enable Delay Count */
771 u8 enable_delay_count;
772 /* UTMIP PLL Stable count */
773 u8 stable_count;
774 /* UTMIP PLL Active delay count */
775 u8 active_delay_count;
776 /* UTMIP PLL Xtal frequency count */
777 u8 xtal_freq_count;
778};
779
780static const struct utmi_clk_param utmi_parameters[] = {
781 {
782 .osc_frequency = 13000000, .enable_delay_count = 0x02,
783 .stable_count = 0x33, .active_delay_count = 0x05,
784 .xtal_freq_count = 0x7f
785 }, {
786 .osc_frequency = 19200000, .enable_delay_count = 0x03,
787 .stable_count = 0x4b, .active_delay_count = 0x06,
788 .xtal_freq_count = 0xbb
789 }, {
790 .osc_frequency = 12000000, .enable_delay_count = 0x02,
791 .stable_count = 0x2f, .active_delay_count = 0x04,
792 .xtal_freq_count = 0x76
793 }, {
794 .osc_frequency = 26000000, .enable_delay_count = 0x04,
795 .stable_count = 0x66, .active_delay_count = 0x09,
796 .xtal_freq_count = 0xfe
797 }, {
798 .osc_frequency = 16800000, .enable_delay_count = 0x03,
799 .stable_count = 0x41, .active_delay_count = 0x0a,
800 .xtal_freq_count = 0xa4
801 },
802};
803
804static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 741static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
805 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, 742 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
806 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, 743 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
@@ -1063,88 +1000,6 @@ static struct tegra_devclk devclks[] __initdata = {
1063 1000
1064static struct clk **clks; 1001static struct clk **clks;
1065 1002
1066static void tegra124_utmi_param_configure(void __iomem *clk_base)
1067{
1068 unsigned int i;
1069 u32 reg;
1070
1071 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1072 if (osc_freq == utmi_parameters[i].osc_frequency)
1073 break;
1074 }
1075
1076 if (i >= ARRAY_SIZE(utmi_parameters)) {
1077 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1078 osc_freq);
1079 return;
1080 }
1081
1082 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1083
1084 /* Program UTMIP PLL stable and active counts */
1085 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1086 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1087 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1088
1089 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1090
1091 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1092 active_delay_count);
1093
1094 /* Remove power downs from UTMIP PLL control bits */
1095 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1096 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1097 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1098
1099 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1100
1101 /* Program UTMIP PLL delay and oscillator frequency counts */
1102 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1103 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1104
1105 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1106 enable_delay_count);
1107
1108 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1109 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1110 xtal_freq_count);
1111
1112 /* Remove power downs from UTMIP PLL control bits */
1113 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1114 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1115 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1116 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1117 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1118
1119 /* Setup HW control of UTMIPLL */
1120 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1121 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1122 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1123 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1124 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1125
1126 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1127 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1128 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1129 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1130
1131 udelay(1);
1132
1133 /* Setup SW override of UTMIPLL assuming USB2.0
1134 ports are assigned to USB2 */
1135 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1136 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1137 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1138 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1139
1140 udelay(1);
1141
1142 /* Enable HW control UTMIPLL */
1143 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1144 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1145 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1146}
1147
1148static __init void tegra124_periph_clk_init(void __iomem *clk_base, 1003static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1149 void __iomem *pmc_base) 1004 void __iomem *pmc_base)
1150{ 1005{
@@ -1195,7 +1050,6 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1195static void __init tegra124_pll_init(void __iomem *clk_base, 1050static void __init tegra124_pll_init(void __iomem *clk_base,
1196 void __iomem *pmc) 1051 void __iomem *pmc)
1197{ 1052{
1198 u32 val;
1199 struct clk *clk; 1053 struct clk *clk;
1200 1054
1201 /* PLLC */ 1055 /* PLLC */
@@ -1256,17 +1110,11 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
1256 clks[TEGRA124_CLK_PLL_M_UD] = clk; 1110 clks[TEGRA124_CLK_PLL_M_UD] = clk;
1257 1111
1258 /* PLLU */ 1112 /* PLLU */
1259 val = readl(clk_base + pll_u_params.base_reg); 1113 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
1260 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1114 &pll_u_params, &pll_u_lock);
1261 writel(val, clk_base + pll_u_params.base_reg);
1262
1263 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1264 &pll_u_params, &pll_u_lock);
1265 clk_register_clkdev(clk, "pll_u", NULL); 1115 clk_register_clkdev(clk, "pll_u", NULL);
1266 clks[TEGRA124_CLK_PLL_U] = clk; 1116 clks[TEGRA124_CLK_PLL_U] = clk;
1267 1117
1268 tegra124_utmi_param_configure(clk_base);
1269
1270 /* PLLU_480M */ 1118 /* PLLU_480M */
1271 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1119 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1272 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1120 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 456cf586d2c2..2896d2e783ce 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -155,27 +155,6 @@
155#define PMC_PLLM_WB0_OVERRIDE 0x1dc 155#define PMC_PLLM_WB0_OVERRIDE 0x1dc
156#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 156#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
157 157
158#define UTMIP_PLL_CFG2 0x488
159#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
160#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
161#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
162#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
163#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
164#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
165#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
166#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
167#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
168#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
169
170#define UTMIP_PLL_CFG1 0x484
171#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
172#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
173#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
174#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
175#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
176#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
177#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
178
179#define SATA_PLL_CFG0 0x490 158#define SATA_PLL_CFG0 0x490
180#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 159#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
181#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 160#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
@@ -1366,9 +1345,9 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1366 1345
1367static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 1346static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1368 /* 1 GHz */ 1347 /* 1 GHz */
1369 { 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */ 1348 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1370 { 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */ 1349 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1371 { 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */ 1350 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1372 { 0, 0, 0, 0, 0, 0 }, 1351 { 0, 0, 0, 0, 0, 0 },
1373}; 1352};
1374 1353
@@ -1417,9 +1396,9 @@ static struct div_nmp pllc_nmp = {
1417}; 1396};
1418 1397
1419static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 1398static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1420 { 12000000, 510000000, 85, 1, 1, 0 }, 1399 { 12000000, 510000000, 85, 1, 2, 0 },
1421 { 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */ 1400 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1422 { 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */ 1401 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1423 { 0, 0, 0, 0, 0, 0 }, 1402 { 0, 0, 0, 0, 0, 0 },
1424}; 1403};
1425 1404
@@ -1532,9 +1511,9 @@ static struct div_nmp pllss_nmp = {
1532}; 1511};
1533 1512
1534static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { 1513static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1535 { 12000000, 600000000, 50, 1, 0, 0 }, 1514 { 12000000, 600000000, 50, 1, 1, 0 },
1536 { 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */ 1515 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1537 { 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */ 1516 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1538 { 0, 0, 0, 0, 0, 0 }, 1517 { 0, 0, 0, 0, 0, 0 },
1539}; 1518};
1540 1519
@@ -1583,19 +1562,19 @@ static struct tegra_clk_pll_params pll_c4_vco_params = {
1583}; 1562};
1584 1563
1585static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 1564static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1586 { 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */ 1565 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1587 { 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */ 1566 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1588 { 38400000, 297600000, 93, 4, 2, 0 }, 1567 { 38400000, 297600000, 93, 4, 3, 0 },
1589 { 38400000, 400000000, 125, 4, 2, 0 }, 1568 { 38400000, 400000000, 125, 4, 3, 0 },
1590 { 38400000, 532800000, 111, 4, 1, 0 }, 1569 { 38400000, 532800000, 111, 4, 2, 0 },
1591 { 38400000, 665600000, 104, 3, 1, 0 }, 1570 { 38400000, 665600000, 104, 3, 2, 0 },
1592 { 38400000, 800000000, 125, 3, 1, 0 }, 1571 { 38400000, 800000000, 125, 3, 2, 0 },
1593 { 38400000, 931200000, 97, 4, 0, 0 }, 1572 { 38400000, 931200000, 97, 4, 1, 0 },
1594 { 38400000, 1065600000, 111, 4, 0, 0 }, 1573 { 38400000, 1065600000, 111, 4, 1, 0 },
1595 { 38400000, 1200000000, 125, 4, 0, 0 }, 1574 { 38400000, 1200000000, 125, 4, 1, 0 },
1596 { 38400000, 1331200000, 104, 3, 0, 0 }, 1575 { 38400000, 1331200000, 104, 3, 1, 0 },
1597 { 38400000, 1459200000, 76, 2, 0, 0 }, 1576 { 38400000, 1459200000, 76, 2, 1, 0 },
1598 { 38400000, 1600000000, 125, 3, 0, 0 }, 1577 { 38400000, 1600000000, 125, 3, 1, 0 },
1599 { 0, 0, 0, 0, 0, 0 }, 1578 { 0, 0, 0, 0, 0, 0 },
1600}; 1579};
1601 1580
@@ -1705,9 +1684,9 @@ static struct tegra_clk_pll_params pll_e_params = {
1705}; 1684};
1706 1685
1707static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = { 1686static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1708 { 12000000, 672000000, 56, 1, 0, 0 }, 1687 { 12000000, 672000000, 56, 1, 1, 0 },
1709 { 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */ 1688 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1710 { 38400000, 672000000, 70, 4, 0, 0 }, 1689 { 38400000, 672000000, 70, 4, 1, 0 },
1711 { 0, 0, 0, 0, 0, 0 }, 1690 { 0, 0, 0, 0, 0, 0 },
1712}; 1691};
1713 1692
@@ -1754,8 +1733,8 @@ static struct div_nmp pllp_nmp = {
1754}; 1733};
1755 1734
1756static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 1735static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1757 { 12000000, 408000000, 34, 1, 0, 0 }, 1736 { 12000000, 408000000, 34, 1, 1, 0 },
1758 { 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */ 1737 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1759 { 0, 0, 0, 0, 0, 0 }, 1738 { 0, 0, 0, 0, 0, 0 },
1760}; 1739};
1761 1740
@@ -1820,14 +1799,14 @@ static struct div_nmp plla_nmp = {
1820}; 1799};
1821 1800
1822static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 1801static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
1823 { 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */ 1802 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
1824 { 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */ 1803 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
1825 { 12000000, 240000000, 60, 1, 2, 1, 0 }, 1804 { 12000000, 240000000, 60, 1, 3, 1, 0 },
1826 { 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */ 1805 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
1827 { 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */ 1806 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
1828 { 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */ 1807 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
1829 { 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */ 1808 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
1830 { 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */ 1809 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
1831 { 38400000, 240000000, 75, 3, 3, 1, 0 }, 1810 { 38400000, 240000000, 75, 3, 3, 1, 0 },
1832 { 0, 0, 0, 0, 0, 0, 0 }, 1811 { 0, 0, 0, 0, 0, 0, 0 },
1833}; 1812};
@@ -1873,9 +1852,9 @@ static struct div_nmp plld_nmp = {
1873}; 1852};
1874 1853
1875static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 1854static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
1876 { 12000000, 594000000, 99, 1, 1, 0, 0 }, 1855 { 12000000, 594000000, 99, 1, 2, 0, 0 },
1877 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */ 1856 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
1878 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 }, 1857 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
1879 { 0, 0, 0, 0, 0, 0, 0 }, 1858 { 0, 0, 0, 0, 0, 0, 0 },
1880}; 1859};
1881 1860
@@ -1911,9 +1890,9 @@ static struct tegra_clk_pll_params pll_d_params = {
1911}; 1890};
1912 1891
1913static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = { 1892static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
1914 { 12000000, 594000000, 99, 1, 1, 0, 0xf000 }, 1893 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
1915 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */ 1894 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
1916 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 }, 1895 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
1917 { 0, 0, 0, 0, 0, 0, 0 }, 1896 { 0, 0, 0, 0, 0, 0, 0 },
1918}; 1897};
1919 1898
@@ -1935,8 +1914,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
1935 .sdm_din_mask = PLLA_SDM_DIN_MASK, 1914 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1936 .sdm_ctrl_reg = PLLD2_MISC1, 1915 .sdm_ctrl_reg = PLLD2_MISC1,
1937 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, 1916 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
1938 .ssc_ctrl_reg = PLLD2_MISC1, 1917 /* disable spread-spectrum for pll_d2 */
1939 .ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK, 1918 .ssc_ctrl_reg = 0,
1919 .ssc_ctrl_en_mask = 0,
1940 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1920 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1941 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1921 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1942 .div_nmp = &pllss_nmp, 1922 .div_nmp = &pllss_nmp,
@@ -1955,9 +1935,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
1955}; 1935};
1956 1936
1957static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 1937static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
1958 { 12000000, 270000000, 90, 1, 3, 0, 0xf000 }, 1938 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
1959 { 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */ 1939 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
1960 { 38400000, 270000000, 28, 1, 3, 0, 0xf400 }, 1940 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
1961 { 0, 0, 0, 0, 0, 0, 0 }, 1941 { 0, 0, 0, 0, 0, 0, 0 },
1962}; 1942};
1963 1943
@@ -2007,9 +1987,9 @@ static struct div_nmp pllu_nmp = {
2007}; 1987};
2008 1988
2009static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 1989static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2010 { 12000000, 480000000, 40, 1, 0, 0 }, 1990 { 12000000, 480000000, 40, 1, 1, 0 },
2011 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */ 1991 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2012 { 38400000, 480000000, 25, 2, 0, 0 }, 1992 { 38400000, 480000000, 25, 2, 1, 0 },
2013 { 0, 0, 0, 0, 0, 0 }, 1993 { 0, 0, 0, 0, 0, 0 },
2014}; 1994};
2015 1995
@@ -2037,47 +2017,6 @@ static struct tegra_clk_pll_params pll_u_vco_params = {
2037 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2017 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2038}; 2018};
2039 2019
2040struct utmi_clk_param {
2041 /* Oscillator Frequency in KHz */
2042 u32 osc_frequency;
2043 /* UTMIP PLL Enable Delay Count */
2044 u8 enable_delay_count;
2045 /* UTMIP PLL Stable count */
2046 u16 stable_count;
2047 /* UTMIP PLL Active delay count */
2048 u8 active_delay_count;
2049 /* UTMIP PLL Xtal frequency count */
2050 u16 xtal_freq_count;
2051};
2052
2053static const struct utmi_clk_param utmi_parameters[] = {
2054 {
2055 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2056 .stable_count = 0x0, .active_delay_count = 0x6,
2057 .xtal_freq_count = 0x80
2058 }, {
2059 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2060 .stable_count = 0x33, .active_delay_count = 0x05,
2061 .xtal_freq_count = 0x7f
2062 }, {
2063 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2064 .stable_count = 0x4b, .active_delay_count = 0x06,
2065 .xtal_freq_count = 0xbb
2066 }, {
2067 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2068 .stable_count = 0x2f, .active_delay_count = 0x08,
2069 .xtal_freq_count = 0x76
2070 }, {
2071 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2072 .stable_count = 0x66, .active_delay_count = 0x09,
2073 .xtal_freq_count = 0xfe
2074 }, {
2075 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2076 .stable_count = 0x41, .active_delay_count = 0x0a,
2077 .xtal_freq_count = 0xa4
2078 },
2079};
2080
2081static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 2020static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2082 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true }, 2021 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2083 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, 2022 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
@@ -2154,6 +2093,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2154 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true }, 2093 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2155 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, 2094 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2156 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true }, 2095 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2096 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2097 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
2157 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, 2098 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2158 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, 2099 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2159 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, 2100 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
@@ -2345,114 +2286,6 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2345 2286
2346static struct clk **clks; 2287static struct clk **clks;
2347 2288
2348static void tegra210_utmi_param_configure(void __iomem *clk_base)
2349{
2350 u32 reg;
2351 int i;
2352
2353 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2354 if (osc_freq == utmi_parameters[i].osc_frequency)
2355 break;
2356 }
2357
2358 if (i >= ARRAY_SIZE(utmi_parameters)) {
2359 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2360 osc_freq);
2361 return;
2362 }
2363
2364 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2365 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2366 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2367 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2368 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2369 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2370 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2371
2372 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2373 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2374 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2375 udelay(1);
2376
2377 reg = readl_relaxed(clk_base + PLLU_BASE);
2378 reg &= ~PLLU_BASE_CLKENABLE_USB;
2379 writel_relaxed(reg, clk_base + PLLU_BASE);
2380
2381 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2382 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2383 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2384
2385 udelay(10);
2386
2387 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2388
2389 /* Program UTMIP PLL stable and active counts */
2390 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2391 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2392 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2393
2394 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2395
2396 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
2397 active_delay_count);
2398 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2399
2400 /* Program UTMIP PLL delay and oscillator frequency counts */
2401 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2402 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2403
2404 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
2405 enable_delay_count);
2406
2407 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2408 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
2409 xtal_freq_count);
2410
2411 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2412 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2413
2414 /* Remove power downs from UTMIP PLL control bits */
2415 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2416 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2417 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2418 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2419 udelay(1);
2420
2421 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2422 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2423 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2424 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2425 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2426 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2427 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2428 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2429 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2430
2431 /* Setup HW control of UTMIPLL */
2432 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2433 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2434 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2435 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2436
2437 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2438 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2439 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2440 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2441
2442 udelay(1);
2443
2444 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2445 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2446 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2447
2448 udelay(1);
2449
2450 /* Enable HW control UTMIPLL */
2451 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2452 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2453 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2454}
2455
2456static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2289static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2457 void __iomem *pmc_base) 2290 void __iomem *pmc_base)
2458{ 2291{
@@ -2463,18 +2296,18 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2463 1, 2); 2296 1, 2);
2464 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; 2297 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2465 2298
2466 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, 2299 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2300 1, 17, 222);
2301 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2302
2303 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
2467 1, 17, 181); 2304 1, 17, 181);
2468 clks[TEGRA210_CLK_DPAUX] = clk; 2305 clks[TEGRA210_CLK_DPAUX] = clk;
2469 2306
2470 clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, 2307 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
2471 1, 17, 207); 2308 1, 17, 207);
2472 clks[TEGRA210_CLK_DPAUX1] = clk; 2309 clks[TEGRA210_CLK_DPAUX1] = clk;
2473 2310
2474 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2475 1, 17, 222);
2476 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2477
2478 /* pll_d_dsi_out */ 2311 /* pll_d_dsi_out */
2479 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 2312 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2480 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); 2313 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
@@ -2520,7 +2353,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2520static void __init tegra210_pll_init(void __iomem *clk_base, 2353static void __init tegra210_pll_init(void __iomem *clk_base,
2521 void __iomem *pmc) 2354 void __iomem *pmc)
2522{ 2355{
2523 u32 val;
2524 struct clk *clk; 2356 struct clk *clk;
2525 2357
2526 /* PLLC */ 2358 /* PLLC */
@@ -2580,12 +2412,9 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
2580 clks[TEGRA210_CLK_PLL_M_UD] = clk; 2412 clks[TEGRA210_CLK_PLL_M_UD] = clk;
2581 2413
2582 /* PLLU_VCO */ 2414 /* PLLU_VCO */
2583 val = readl(clk_base + pll_u_vco_params.base_reg); 2415 clk = tegra_clk_register_pllu_tegra210("pll_u_vco", "pll_ref",
2584 val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */ 2416 clk_base, 0, &pll_u_vco_params,
2585 writel(val, clk_base + pll_u_vco_params.base_reg); 2417 &pll_u_lock);
2586
2587 clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
2588 0, &pll_u_vco_params, &pll_u_lock, pll_ref_freq);
2589 clk_register_clkdev(clk, "pll_u_vco", NULL); 2418 clk_register_clkdev(clk, "pll_u_vco", NULL);
2590 clks[TEGRA210_CLK_PLL_U] = clk; 2419 clks[TEGRA210_CLK_PLL_U] = clk;
2591 2420
@@ -2618,8 +2447,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
2618 clk_register_clkdev(clk, "pll_u_out2", NULL); 2447 clk_register_clkdev(clk, "pll_u_out2", NULL);
2619 clks[TEGRA210_CLK_PLL_U_OUT2] = clk; 2448 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
2620 2449
2621 tegra210_utmi_param_configure(clk_base);
2622
2623 /* PLLU_480M */ 2450 /* PLLU_480M */
2624 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco", 2451 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
2625 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 2452 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 9396f4930da7..8e2db5ead8da 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -118,20 +118,6 @@
118 118
119#define AUDIO_SYNC_DOUBLER 0x49c 119#define AUDIO_SYNC_DOUBLER 0x49c
120 120
121#define UTMIP_PLL_CFG2 0x488
122#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
123#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
124#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
125#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
126#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
127
128#define UTMIP_PLL_CFG1 0x484
129#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
130#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
131#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
134
135/* Tegra CPU clock and reset control regs */ 121/* Tegra CPU clock and reset control regs */
136#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 122#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
137#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 123#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
@@ -207,46 +193,6 @@ static DEFINE_SPINLOCK(emc_lock);
207 193
208static struct clk **clks; 194static struct clk **clks;
209 195
210/*
211 * Structure defining the fields for USB UTMI clocks Parameters.
212 */
213struct utmi_clk_param {
214 /* Oscillator Frequency in KHz */
215 u32 osc_frequency;
216 /* UTMIP PLL Enable Delay Count */
217 u8 enable_delay_count;
218 /* UTMIP PLL Stable count */
219 u8 stable_count;
220 /* UTMIP PLL Active delay count */
221 u8 active_delay_count;
222 /* UTMIP PLL Xtal frequency count */
223 u8 xtal_freq_count;
224};
225
226static const struct utmi_clk_param utmi_parameters[] = {
227 {
228 .osc_frequency = 13000000, .enable_delay_count = 0x02,
229 .stable_count = 0x33, .active_delay_count = 0x05,
230 .xtal_freq_count = 0x7f
231 }, {
232 .osc_frequency = 19200000, .enable_delay_count = 0x03,
233 .stable_count = 0x4b, .active_delay_count = 0x06,
234 .xtal_freq_count = 0xbb
235 }, {
236 .osc_frequency = 12000000, .enable_delay_count = 0x02,
237 .stable_count = 0x2f, .active_delay_count = 0x04,
238 .xtal_freq_count = 0x76
239 }, {
240 .osc_frequency = 26000000, .enable_delay_count = 0x04,
241 .stable_count = 0x66, .active_delay_count = 0x09,
242 .xtal_freq_count = 0xfe
243 }, {
244 .osc_frequency = 16800000, .enable_delay_count = 0x03,
245 .stable_count = 0x41, .active_delay_count = 0x0a,
246 .xtal_freq_count = 0xa4
247 },
248};
249
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 196static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 1040000000, 520, 6, 1, 8 }, 197 { 12000000, 1040000000, 520, 6, 1, 8 },
252 { 13000000, 1040000000, 480, 6, 1, 8 }, 198 { 13000000, 1040000000, 480, 6, 1, 8 },
@@ -873,59 +819,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
873 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, 819 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
874}; 820};
875 821
876static void tegra30_utmi_param_configure(void)
877{
878 unsigned int i;
879 u32 reg;
880
881 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
882 if (input_freq == utmi_parameters[i].osc_frequency)
883 break;
884 }
885
886 if (i >= ARRAY_SIZE(utmi_parameters)) {
887 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
888 return;
889 }
890
891 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
892
893 /* Program UTMIP PLL stable and active counts */
894 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
895 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
896 utmi_parameters[i].stable_count);
897
898 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
899
900 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
901 utmi_parameters[i].active_delay_count);
902
903 /* Remove power downs from UTMIP PLL control bits */
904 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
905 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
906 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
907
908 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
909
910 /* Program UTMIP PLL delay and oscillator frequency counts */
911 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
912 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
913
914 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
915 utmi_parameters[i].enable_delay_count);
916
917 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
918 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
919 utmi_parameters[i].xtal_freq_count);
920
921 /* Remove power downs from UTMIP PLL control bits */
922 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
923 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
924 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
925
926 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
927}
928
929static const char *pll_e_parents[] = { "pll_ref", "pll_p" }; 822static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
930 823
931static void __init tegra30_pll_init(void) 824static void __init tegra30_pll_init(void)
@@ -972,12 +865,10 @@ static void __init tegra30_pll_init(void)
972 clks[TEGRA30_CLK_PLL_X_OUT0] = clk; 865 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
973 866
974 /* PLLU */ 867 /* PLLU */
975 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 868 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
976 &pll_u_params, NULL); 869 &pll_u_params, NULL);
977 clks[TEGRA30_CLK_PLL_U] = clk; 870 clks[TEGRA30_CLK_PLL_U] = clk;
978 871
979 tegra30_utmi_param_configure();
980
981 /* PLLD */ 872 /* PLLD */
982 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 873 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
983 &pll_d_params, &pll_d_lock); 874 &pll_d_params, &pll_d_lock);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 9421f0310999..6ba82ecffd4d 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -427,6 +427,23 @@ struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
427 struct tegra_clk_pll_params *pll_params, 427 struct tegra_clk_pll_params *pll_params,
428 spinlock_t *lock); 428 spinlock_t *lock);
429 429
430struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
431 void __iomem *clk_base, unsigned long flags,
432 struct tegra_clk_pll_params *pll_params,
433 spinlock_t *lock);
434
435struct clk *tegra_clk_register_pllu_tegra114(const char *name,
436 const char *parent_name,
437 void __iomem *clk_base, unsigned long flags,
438 struct tegra_clk_pll_params *pll_params,
439 spinlock_t *lock);
440
441struct clk *tegra_clk_register_pllu_tegra210(const char *name,
442 const char *parent_name,
443 void __iomem *clk_base, unsigned long flags,
444 struct tegra_clk_pll_params *pll_params,
445 spinlock_t *lock);
446
430/** 447/**
431 * struct tegra_clk_pll_out - PLL divider down clock 448 * struct tegra_clk_pll_out - PLL divider down clock
432 * 449 *
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 9b180f032e2d..85b467b3a207 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -1,33 +1,65 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2016 Krzysztof Kozlowski
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5421 clock controller.
10*/
11
1#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
2#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 13#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
3 14
4/* core clocks */ 15/* core clocks */
5#define CLK_FIN_PLL 1 16#define CLK_FIN_PLL 1
6#define CLK_FOUT_APLL 2 17#define CLK_FOUT_APLL 2
7#define CLK_FOUT_CPLL 3 18#define CLK_FOUT_CPLL 3
8#define CLK_FOUT_MPLL 4 19#define CLK_FOUT_MPLL 4
9#define CLK_FOUT_BPLL 5 20#define CLK_FOUT_BPLL 5
10#define CLK_FOUT_KPLL 6 21#define CLK_FOUT_KPLL 6
11 22
12/* gate for special clocks (sclk) */ 23/* gate for special clocks (sclk) */
13#define CLK_SCLK_UART0 128 24#define CLK_SCLK_UART0 128
14#define CLK_SCLK_UART1 129 25#define CLK_SCLK_UART1 129
15#define CLK_SCLK_UART2 130 26#define CLK_SCLK_UART2 130
16#define CLK_SCLK_UART3 131 27#define CLK_SCLK_UART3 131
17#define CLK_SCLK_MMC0 132 28#define CLK_SCLK_MMC0 132
18#define CLK_SCLK_MMC1 133 29#define CLK_SCLK_MMC1 133
19#define CLK_SCLK_MMC2 134 30#define CLK_SCLK_MMC2 134
31#define CLK_SCLK_USBD300 150
32#define CLK_SCLK_USBD301 151
33#define CLK_SCLK_USBPHY300 152
34#define CLK_SCLK_USBPHY301 153
35#define CLK_SCLK_PWM 155
20 36
21/* gate clocks */ 37/* gate clocks */
22#define CLK_UART0 257 38#define CLK_UART0 257
23#define CLK_UART1 258 39#define CLK_UART1 258
24#define CLK_UART2 259 40#define CLK_UART2 259
25#define CLK_UART3 260 41#define CLK_I2C0 261
26#define CLK_MCT 315 42#define CLK_I2C1 262
27#define CLK_MMC0 351 43#define CLK_I2C2 263
28#define CLK_MMC1 352 44#define CLK_I2C3 264
29#define CLK_MMC2 353 45#define CLK_USI0 265
46#define CLK_USI1 266
47#define CLK_USI2 267
48#define CLK_USI3 268
49#define CLK_UART3 260
50#define CLK_PWM 279
51#define CLK_MCT 315
52#define CLK_WDT 316
53#define CLK_RTC 317
54#define CLK_TMU 318
55#define CLK_MMC0 351
56#define CLK_MMC1 352
57#define CLK_MMC2 353
58#define CLK_USBH20 365
59#define CLK_USBD300 366
60#define CLK_USBD301 367
61#define CLK_SSS 471
30 62
31#define CLK_NR_CLKS 512 63#define CLK_NR_CLKS 512
32 64
33#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ 65#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 8e024fea26e7..4fa6bb2136e3 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -622,8 +622,9 @@
622#define CLK_SCLK_UFSUNIPRO 112 622#define CLK_SCLK_UFSUNIPRO 112
623#define CLK_SCLK_USBHOST30 113 623#define CLK_SCLK_USBHOST30 113
624#define CLK_SCLK_USBDRD30 114 624#define CLK_SCLK_USBDRD30 114
625#define CLK_PCIE 115
625 626
626#define FSYS_NR_CLK 115 627#define FSYS_NR_CLK 116
627 628
628/* CMU_G2D */ 629/* CMU_G2D */
629#define CLK_MUX_ACLK_G2D_266_USER 1 630#define CLK_MUX_ACLK_G2D_266_USER 1
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
new file mode 100644
index 000000000000..f889d80246cb
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -0,0 +1,12 @@
1/*
2 * GXBB clock tree IDs
3 */
4
5#ifndef __GXBB_CLKC_H
6#define __GXBB_CLKC_H
7
8#define CLKID_CPUCLK 1
9#define CLKID_CLK81 12
10#define CLKID_ETH 36
11
12#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
index 70ee3833a7a0..6b03c84f4278 100644
--- a/include/dt-bindings/clock/hi6220-clock.h
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -55,8 +55,9 @@
55#define HI6220_TIMER7_PCLK 34 55#define HI6220_TIMER7_PCLK 34
56#define HI6220_TIMER8_PCLK 35 56#define HI6220_TIMER8_PCLK 35
57#define HI6220_UART0_PCLK 36 57#define HI6220_UART0_PCLK 36
58 58#define HI6220_RTC0_PCLK 37
59#define HI6220_AO_NR_CLKS 37 59#define HI6220_RTC1_PCLK 38
60#define HI6220_AO_NR_CLKS 39
60 61
61/* clk in Hi6220 systrl */ 62/* clk in Hi6220 systrl */
62/* gate clock */ 63/* gate clock */
diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h
index d41b6fea1450..e624d3a52798 100644
--- a/include/dt-bindings/clock/lpc32xx-clock.h
+++ b/include/dt-bindings/clock/lpc32xx-clock.h
@@ -48,6 +48,7 @@
48#define LPC32XX_CLK_PWM2 33 48#define LPC32XX_CLK_PWM2 33
49#define LPC32XX_CLK_ADC 34 49#define LPC32XX_CLK_ADC 34
50#define LPC32XX_CLK_HCLK_PLL 35 50#define LPC32XX_CLK_HCLK_PLL 35
51#define LPC32XX_CLK_PERIPH 36
51 52
52/* LPC32XX USB clocks */ 53/* LPC32XX USB clocks */
53#define LPC32XX_USB_CLK_I2C 1 54#define LPC32XX_USB_CLK_I2C 1
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index bd2720d58e0c..595a58d0969a 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -19,7 +19,9 @@
19#define CLKID_MALI 11 19#define CLKID_MALI 11
20#define CLKID_CPUCLK 12 20#define CLKID_CPUCLK 12
21#define CLKID_ZERO 13 21#define CLKID_ZERO 13
22#define CLKID_MPEG_SEL 14
23#define CLKID_MPEG_DIV 15
22 24
23#define CLK_NR_CLKS (CLKID_ZERO + 1) 25#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1)
24 26
25#endif /* __MESON8B_CLKC_H */ 27#endif /* __MESON8B_CLKC_H */
diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
new file mode 100644
index 000000000000..1e5942695f0d
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 2016 Renesas Electronics Corp.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
11
12#include <dt-bindings/clock/renesas-cpg-mssr.h>
13
14/* r8a7796 CPG Core Clocks */
15#define R8A7796_CLK_Z 0
16#define R8A7796_CLK_Z2 1
17#define R8A7796_CLK_ZR 2
18#define R8A7796_CLK_ZG 3
19#define R8A7796_CLK_ZTR 4
20#define R8A7796_CLK_ZTRD2 5
21#define R8A7796_CLK_ZT 6
22#define R8A7796_CLK_ZX 7
23#define R8A7796_CLK_S0D1 8
24#define R8A7796_CLK_S0D2 9
25#define R8A7796_CLK_S0D3 10
26#define R8A7796_CLK_S0D4 11
27#define R8A7796_CLK_S0D6 12
28#define R8A7796_CLK_S0D8 13
29#define R8A7796_CLK_S0D12 14
30#define R8A7796_CLK_S1D1 15
31#define R8A7796_CLK_S1D2 16
32#define R8A7796_CLK_S1D4 17
33#define R8A7796_CLK_S2D1 18
34#define R8A7796_CLK_S2D2 19
35#define R8A7796_CLK_S2D4 20
36#define R8A7796_CLK_S3D1 21
37#define R8A7796_CLK_S3D2 22
38#define R8A7796_CLK_S3D4 23
39#define R8A7796_CLK_LB 24
40#define R8A7796_CLK_CL 25
41#define R8A7796_CLK_ZB3 26
42#define R8A7796_CLK_ZB3D2 27
43#define R8A7796_CLK_ZB3D4 28
44#define R8A7796_CLK_CR 29
45#define R8A7796_CLK_CRD2 30
46#define R8A7796_CLK_SD0H 31
47#define R8A7796_CLK_SD0 32
48#define R8A7796_CLK_SD1H 33
49#define R8A7796_CLK_SD1 34
50#define R8A7796_CLK_SD2H 35
51#define R8A7796_CLK_SD2 36
52#define R8A7796_CLK_SD3H 37
53#define R8A7796_CLK_SD3 38
54#define R8A7796_CLK_SSP2 39
55#define R8A7796_CLK_SSP1 40
56#define R8A7796_CLK_SSPRS 41
57#define R8A7796_CLK_RPC 42
58#define R8A7796_CLK_RPCD2 43
59#define R8A7796_CLK_MSO 44
60#define R8A7796_CLK_CANFD 45
61#define R8A7796_CLK_HDMI 46
62#define R8A7796_CLK_CSI0 47
63#define R8A7796_CLK_CSIREF 48
64#define R8A7796_CLK_CP 49
65#define R8A7796_CLK_CPEX 50
66#define R8A7796_CLK_R 51
67#define R8A7796_CLK_OSC 52
68
69#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index 5d43ed9b05ad..b27e2b1a65e3 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -52,6 +52,15 @@
52#define SCLK_EMMC_SAMPLE 121 52#define SCLK_EMMC_SAMPLE 121
53#define SCLK_VOP 122 53#define SCLK_VOP 122
54#define SCLK_HDMI_HDCP 123 54#define SCLK_HDMI_HDCP 123
55#define SCLK_MAC_SRC 124
56#define SCLK_MAC_EXTCLK 125
57#define SCLK_MAC 126
58#define SCLK_MAC_REFOUT 127
59#define SCLK_MAC_REF 128
60#define SCLK_MAC_RX 129
61#define SCLK_MAC_TX 130
62#define SCLK_MAC_PHY 131
63#define SCLK_MAC_OUT 132
55 64
56/* dclk gates */ 65/* dclk gates */
57#define DCLK_VOP 190 66#define DCLK_VOP 190
@@ -61,6 +70,7 @@
61#define ACLK_DMAC 194 70#define ACLK_DMAC 194
62#define ACLK_PERI 210 71#define ACLK_PERI 210
63#define ACLK_VOP 211 72#define ACLK_VOP 211
73#define ACLK_GMAC 212
64 74
65/* pclk gates */ 75/* pclk gates */
66#define PCLK_GPIO0 320 76#define PCLK_GPIO0 320
@@ -82,8 +92,13 @@
82#define PCLK_PERI 363 92#define PCLK_PERI 363
83#define PCLK_HDMI_CTRL 364 93#define PCLK_HDMI_CTRL 364
84#define PCLK_HDMI_PHY 365 94#define PCLK_HDMI_PHY 365
95#define PCLK_GMAC 367
85 96
86/* hclk gates */ 97/* hclk gates */
98#define HCLK_I2S0_8CH 442
99#define HCLK_I2S1_8CH 443
100#define HCLK_I2S2_2CH 444
101#define HCLK_SPDIF_8CH 445
87#define HCLK_VOP 452 102#define HCLK_VOP 452
88#define HCLK_NANDC 453 103#define HCLK_NANDC 453
89#define HCLK_SDMMC 456 104#define HCLK_SDMMC 456
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
new file mode 100644
index 000000000000..efb7ba2bd515
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
44#define _DT_BINDINGS_CLK_SUN8I_H3_H_
45
46#define CLK_CPUX 14
47
48#define CLK_BUS_CE 20
49#define CLK_BUS_DMA 21
50#define CLK_BUS_MMC0 22
51#define CLK_BUS_MMC1 23
52#define CLK_BUS_MMC2 24
53#define CLK_BUS_NAND 25
54#define CLK_BUS_DRAM 26
55#define CLK_BUS_EMAC 27
56#define CLK_BUS_TS 28
57#define CLK_BUS_HSTIMER 29
58#define CLK_BUS_SPI0 30
59#define CLK_BUS_SPI1 31
60#define CLK_BUS_OTG 32
61#define CLK_BUS_EHCI0 33
62#define CLK_BUS_EHCI1 34
63#define CLK_BUS_EHCI2 35
64#define CLK_BUS_EHCI3 36
65#define CLK_BUS_OHCI0 37
66#define CLK_BUS_OHCI1 38
67#define CLK_BUS_OHCI2 39
68#define CLK_BUS_OHCI3 40
69#define CLK_BUS_VE 41
70#define CLK_BUS_TCON0 42
71#define CLK_BUS_TCON1 43
72#define CLK_BUS_DEINTERLACE 44
73#define CLK_BUS_CSI 45
74#define CLK_BUS_TVE 46
75#define CLK_BUS_HDMI 47
76#define CLK_BUS_DE 48
77#define CLK_BUS_GPU 49
78#define CLK_BUS_MSGBOX 50
79#define CLK_BUS_SPINLOCK 51
80#define CLK_BUS_CODEC 52
81#define CLK_BUS_SPDIF 53
82#define CLK_BUS_PIO 54
83#define CLK_BUS_THS 55
84#define CLK_BUS_I2S0 56
85#define CLK_BUS_I2S1 57
86#define CLK_BUS_I2S2 58
87#define CLK_BUS_I2C0 59
88#define CLK_BUS_I2C1 60
89#define CLK_BUS_I2C2 61
90#define CLK_BUS_UART0 62
91#define CLK_BUS_UART1 63
92#define CLK_BUS_UART2 64
93#define CLK_BUS_UART3 65
94#define CLK_BUS_SCR 66
95#define CLK_BUS_EPHY 67
96#define CLK_BUS_DBG 68
97
98#define CLK_THS 69
99#define CLK_NAND 70
100#define CLK_MMC0 71
101#define CLK_MMC0_SAMPLE 72
102#define CLK_MMC0_OUTPUT 73
103#define CLK_MMC1 74
104#define CLK_MMC1_SAMPLE 75
105#define CLK_MMC1_OUTPUT 76
106#define CLK_MMC2 77
107#define CLK_MMC2_SAMPLE 78
108#define CLK_MMC2_OUTPUT 79
109#define CLK_TS 80
110#define CLK_CE 81
111#define CLK_SPI0 82
112#define CLK_SPI1 83
113#define CLK_I2S0 84
114#define CLK_I2S1 85
115#define CLK_I2S2 86
116#define CLK_SPDIF 87
117#define CLK_USB_PHY0 88
118#define CLK_USB_PHY1 89
119#define CLK_USB_PHY2 90
120#define CLK_USB_PHY3 91
121#define CLK_USB_OHCI0 92
122#define CLK_USB_OHCI1 93
123#define CLK_USB_OHCI2 94
124#define CLK_USB_OHCI3 95
125
126#define CLK_DRAM_VE 97
127#define CLK_DRAM_CSI 98
128#define CLK_DRAM_DEINTERLACE 99
129#define CLK_DRAM_TS 100
130#define CLK_DE 101
131#define CLK_TCON0 102
132#define CLK_TVE 103
133#define CLK_DEINTERLACE 104
134#define CLK_CSI_MISC 105
135#define CLK_CSI_SCLK 106
136#define CLK_CSI_MCLK 107
137#define CLK_VE 108
138#define CLK_AC_DIG 109
139#define CLK_AVS 110
140#define CLK_HDMI 111
141#define CLK_HDMI_DDC 112
142
143#define CLK_GPU 114
144
145#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index bd3530e56d46..35288b20f2c9 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -308,7 +308,7 @@
308#define TEGRA210_CLK_CLK_OUT_3 279 308#define TEGRA210_CLK_CLK_OUT_3 279
309#define TEGRA210_CLK_BLINK 280 309#define TEGRA210_CLK_BLINK 280
310/* 281 */ 310/* 281 */
311/* 282 */ 311#define TEGRA210_CLK_SOR1_SRC 282
312/* 283 */ 312/* 283 */
313#define TEGRA210_CLK_XUSB_HOST_SRC 284 313#define TEGRA210_CLK_XUSB_HOST_SRC 284
314#define TEGRA210_CLK_XUSB_FALCON_SRC 285 314#define TEGRA210_CLK_XUSB_FALCON_SRC 285
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
new file mode 100644
index 000000000000..6b7af80c26ec
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-h3-ccu.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
44#define _DT_BINDINGS_RST_SUN8I_H3_H_
45
46#define RST_USB_PHY0 0
47#define RST_USB_PHY1 1
48#define RST_USB_PHY2 2
49#define RST_USB_PHY3 3
50
51#define RST_MBUS 4
52
53#define RST_BUS_CE 5
54#define RST_BUS_DMA 6
55#define RST_BUS_MMC0 7
56#define RST_BUS_MMC1 8
57#define RST_BUS_MMC2 9
58#define RST_BUS_NAND 10
59#define RST_BUS_DRAM 11
60#define RST_BUS_EMAC 12
61#define RST_BUS_TS 13
62#define RST_BUS_HSTIMER 14
63#define RST_BUS_SPI0 15
64#define RST_BUS_SPI1 16
65#define RST_BUS_OTG 17
66#define RST_BUS_EHCI0 18
67#define RST_BUS_EHCI1 19
68#define RST_BUS_EHCI2 20
69#define RST_BUS_EHCI3 21
70#define RST_BUS_OHCI0 22
71#define RST_BUS_OHCI1 23
72#define RST_BUS_OHCI2 24
73#define RST_BUS_OHCI3 25
74#define RST_BUS_VE 26
75#define RST_BUS_TCON0 27
76#define RST_BUS_TCON1 28
77#define RST_BUS_DEINTERLACE 29
78#define RST_BUS_CSI 30
79#define RST_BUS_TVE 31
80#define RST_BUS_HDMI0 32
81#define RST_BUS_HDMI1 33
82#define RST_BUS_DE 34
83#define RST_BUS_GPU 35
84#define RST_BUS_MSGBOX 36
85#define RST_BUS_SPINLOCK 37
86#define RST_BUS_DBG 38
87#define RST_BUS_EPHY 39
88#define RST_BUS_CODEC 40
89#define RST_BUS_SPDIF 41
90#define RST_BUS_THS 42
91#define RST_BUS_I2S0 43
92#define RST_BUS_I2S1 44
93#define RST_BUS_I2S2 45
94#define RST_BUS_I2C0 46
95#define RST_BUS_I2C1 47
96#define RST_BUS_I2C2 48
97#define RST_BUS_UART0 49
98#define RST_BUS_UART1 50
99#define RST_BUS_UART2 51
100#define RST_BUS_UART3 52
101#define RST_BUS_SCR 53
102
103#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index fb39d5add173..a39c0c530778 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -33,6 +33,8 @@
33#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 33#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
34#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 34#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
35#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 35#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
36/* parents need enable during gate/ungate, set rate and re-parent */
37#define CLK_OPS_PARENT_ENABLE BIT(12)
36 38
37struct clk; 39struct clk;
38struct clk_hw; 40struct clk_hw;
@@ -293,6 +295,7 @@ void clk_unregister_fixed_rate(struct clk *clk);
293struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, 295struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
294 const char *name, const char *parent_name, unsigned long flags, 296 const char *name, const char *parent_name, unsigned long flags,
295 unsigned long fixed_rate, unsigned long fixed_accuracy); 297 unsigned long fixed_rate, unsigned long fixed_accuracy);
298void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
296 299
297void of_fixed_clk_setup(struct device_node *np); 300void of_fixed_clk_setup(struct device_node *np);
298 301
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 834179f3fa72..123c02788807 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -20,8 +20,6 @@ struct device;
20 20
21struct clk; 21struct clk;
22 22
23#ifdef CONFIG_COMMON_CLK
24
25/** 23/**
26 * DOC: clk notifier callback types 24 * DOC: clk notifier callback types
27 * 25 *
@@ -78,6 +76,8 @@ struct clk_notifier_data {
78 unsigned long new_rate; 76 unsigned long new_rate;
79}; 77};
80 78
79#ifdef CONFIG_COMMON_CLK
80
81/** 81/**
82 * clk_notifier_register: register a clock rate-change notifier callback 82 * clk_notifier_register: register a clock rate-change notifier callback
83 * @clk: clock whose rate we are interested in 83 * @clk: clock whose rate we are interested in
@@ -140,6 +140,18 @@ bool clk_is_match(const struct clk *p, const struct clk *q);
140 140
141#else 141#else
142 142
143static inline int clk_notifier_register(struct clk *clk,
144 struct notifier_block *nb)
145{
146 return -ENOTSUPP;
147}
148
149static inline int clk_notifier_unregister(struct clk *clk,
150 struct notifier_block *nb)
151{
152 return -ENOTSUPP;
153}
154
143static inline long clk_get_accuracy(struct clk *clk) 155static inline long clk_get_accuracy(struct clk *clk)
144{ 156{
145 return -ENOTSUPP; 157 return -ENOTSUPP;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 07:45:20 -0500