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path: root/drivers/clk/samsung/clk-exynos5433.c
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Diffstat (limited to 'drivers/clk/samsung/clk-exynos5433.c')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c437
1 files changed, 264 insertions, 173 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 128527b8fbeb..ea1608682d7f 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -11,10 +11,12 @@
11 11
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/of_address.h>
14 15
15#include <dt-bindings/clock/exynos5433.h> 16#include <dt-bindings/clock/exynos5433.h>
16 17
17#include "clk.h" 18#include "clk.h"
19#include "clk-cpu.h"
18#include "clk-pll.h" 20#include "clk-pll.h"
19 21
20/* 22/*
@@ -108,7 +110,7 @@
108#define ENABLE_CMU_TOP 0x0c00 110#define ENABLE_CMU_TOP 0x0c00
109#define ENABLE_CMU_TOP_DIV_STAT 0x0c04 111#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
110 112
111static unsigned long top_clk_regs[] __initdata = { 113static const unsigned long top_clk_regs[] __initconst = {
112 ISP_PLL_LOCK, 114 ISP_PLL_LOCK,
113 AUD_PLL_LOCK, 115 AUD_PLL_LOCK,
114 ISP_PLL_CON0, 116 ISP_PLL_CON0,
@@ -218,11 +220,11 @@ PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
218 220
219PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 221PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
220 222
221static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { 223static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
222 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 224 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
223}; 225};
224 226
225static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { 227static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
226 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 228 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
227 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 229 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
228 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 230 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
@@ -238,7 +240,7 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
238 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 240 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
239}; 241};
240 242
241static struct samsung_mux_clock top_mux_clks[] __initdata = { 243static const struct samsung_mux_clock top_mux_clks[] __initconst = {
242 /* MUX_SEL_TOP0 */ 244 /* MUX_SEL_TOP0 */
243 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 245 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
244 4, 1), 246 4, 1),
@@ -374,7 +376,7 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
374 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 376 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
375}; 377};
376 378
377static struct samsung_div_clock top_div_clks[] __initdata = { 379static const struct samsung_div_clock top_div_clks[] __initconst = {
378 /* DIV_TOP0 */ 380 /* DIV_TOP0 */
379 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 381 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
380 DIV_TOP0, 28, 3), 382 DIV_TOP0, 28, 3),
@@ -538,7 +540,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
538 DIV_TOP_PERIC4, 0, 4), 540 DIV_TOP_PERIC4, 0, 4),
539}; 541};
540 542
541static struct samsung_gate_clock top_gate_clks[] __initdata = { 543static const struct samsung_gate_clock top_gate_clks[] __initconst = {
542 /* ENABLE_ACLK_TOP */ 544 /* ENABLE_ACLK_TOP */
543 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 545 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
544 ENABLE_ACLK_TOP, 30, 0, 0), 546 ENABLE_ACLK_TOP, 30, 0, 0),
@@ -639,7 +641,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
639 641
640 /* ENABLE_SCLK_TOP_FSYS */ 642 /* ENABLE_SCLK_TOP_FSYS */
641 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 643 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
642 ENABLE_SCLK_TOP_FSYS, 7, 0, 0), 644 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
643 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 645 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
644 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 646 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
645 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 647 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
@@ -668,11 +670,14 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
668 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 670 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
669 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 671 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
670 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 672 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
671 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), 673 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
674 CLK_IGNORE_UNUSED, 0),
672 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 675 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
673 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), 676 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
677 CLK_IGNORE_UNUSED, 0),
674 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 678 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
675 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), 679 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
680 CLK_IGNORE_UNUSED, 0),
676 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 681 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
677 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 682 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
678 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 683 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
@@ -693,7 +698,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
693 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 698 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
694 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 699 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
695 */ 700 */
696static struct samsung_pll_rate_table exynos5443_pll_rates[] = { 701static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = {
697 PLL_35XX_RATE(2500000000U, 625, 6, 0), 702 PLL_35XX_RATE(2500000000U, 625, 6, 0),
698 PLL_35XX_RATE(2400000000U, 500, 5, 0), 703 PLL_35XX_RATE(2400000000U, 500, 5, 0),
699 PLL_35XX_RATE(2300000000U, 575, 6, 0), 704 PLL_35XX_RATE(2300000000U, 575, 6, 0),
@@ -744,7 +749,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
744}; 749};
745 750
746/* AUD_PLL */ 751/* AUD_PLL */
747static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { 752static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = {
748 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 753 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
749 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), 754 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
750 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 755 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
@@ -757,14 +762,14 @@ static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
757 { /* sentinel */ } 762 { /* sentinel */ }
758}; 763};
759 764
760static struct samsung_pll_clock top_pll_clks[] __initdata = { 765static const struct samsung_pll_clock top_pll_clks[] __initconst = {
761 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 766 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
762 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), 767 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
763 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 768 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
764 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), 769 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
765}; 770};
766 771
767static struct samsung_cmu_info top_cmu_info __initdata = { 772static const struct samsung_cmu_info top_cmu_info __initconst = {
768 .pll_clks = top_pll_clks, 773 .pll_clks = top_pll_clks,
769 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 774 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
770 .mux_clks = top_mux_clks, 775 .mux_clks = top_mux_clks,
@@ -800,7 +805,7 @@ CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
800#define DIV_CPIF 0x0600 805#define DIV_CPIF 0x0600
801#define ENABLE_SCLK_CPIF 0x0a00 806#define ENABLE_SCLK_CPIF 0x0a00
802 807
803static unsigned long cpif_clk_regs[] __initdata = { 808static const unsigned long cpif_clk_regs[] __initconst = {
804 MPHY_PLL_LOCK, 809 MPHY_PLL_LOCK,
805 MPHY_PLL_CON0, 810 MPHY_PLL_CON0,
806 MPHY_PLL_CON1, 811 MPHY_PLL_CON1,
@@ -813,32 +818,32 @@ static unsigned long cpif_clk_regs[] __initdata = {
813/* list of all parent clock list */ 818/* list of all parent clock list */
814PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 819PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
815 820
816static struct samsung_pll_clock cpif_pll_clks[] __initdata = { 821static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
817 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 822 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
818 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), 823 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
819}; 824};
820 825
821static struct samsung_mux_clock cpif_mux_clks[] __initdata = { 826static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
822 /* MUX_SEL_CPIF0 */ 827 /* MUX_SEL_CPIF0 */
823 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 828 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
824 0, 1), 829 0, 1),
825}; 830};
826 831
827static struct samsung_div_clock cpif_div_clks[] __initdata = { 832static const struct samsung_div_clock cpif_div_clks[] __initconst = {
828 /* DIV_CPIF */ 833 /* DIV_CPIF */
829 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 834 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
830 0, 6), 835 0, 6),
831}; 836};
832 837
833static struct samsung_gate_clock cpif_gate_clks[] __initdata = { 838static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
834 /* ENABLE_SCLK_CPIF */ 839 /* ENABLE_SCLK_CPIF */
835 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 840 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
836 ENABLE_SCLK_CPIF, 9, 0, 0), 841 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
837 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 842 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
838 ENABLE_SCLK_CPIF, 4, 0, 0), 843 ENABLE_SCLK_CPIF, 4, 0, 0),
839}; 844};
840 845
841static struct samsung_cmu_info cpif_cmu_info __initdata = { 846static const struct samsung_cmu_info cpif_cmu_info __initconst = {
842 .pll_clks = cpif_pll_clks, 847 .pll_clks = cpif_pll_clks,
843 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 848 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
844 .mux_clks = cpif_mux_clks, 849 .mux_clks = cpif_mux_clks,
@@ -939,7 +944,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
939#define PAUSE 0x1008 944#define PAUSE 0x1008
940#define DDRPHY_LOCK_CTRL 0x100c 945#define DDRPHY_LOCK_CTRL 0x100c
941 946
942static unsigned long mif_clk_regs[] __initdata = { 947static const unsigned long mif_clk_regs[] __initconst = {
943 MEM0_PLL_LOCK, 948 MEM0_PLL_LOCK,
944 MEM1_PLL_LOCK, 949 MEM1_PLL_LOCK,
945 BUS_PLL_LOCK, 950 BUS_PLL_LOCK,
@@ -1004,7 +1009,7 @@ static unsigned long mif_clk_regs[] __initdata = {
1004 DDRPHY_LOCK_CTRL, 1009 DDRPHY_LOCK_CTRL,
1005}; 1010};
1006 1011
1007static struct samsung_pll_clock mif_pll_clks[] __initdata = { 1012static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1008 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1013 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1009 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), 1014 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1010 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1015 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
@@ -1065,7 +1070,7 @@ PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1065PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1070PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1066PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1071PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1067 1072
1068static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { 1073static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1069 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1074 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1070 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1075 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1071 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1076 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
@@ -1073,7 +1078,7 @@ static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1073 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1078 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1074}; 1079};
1075 1080
1076static struct samsung_mux_clock mif_mux_clks[] __initdata = { 1081static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1077 /* MUX_SEL_MIF0 */ 1082 /* MUX_SEL_MIF0 */
1078 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1083 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1079 MUX_SEL_MIF0, 28, 1), 1084 MUX_SEL_MIF0, 28, 1),
@@ -1169,7 +1174,7 @@ static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1169 MUX_SEL_MIF7, 0, 1), 1174 MUX_SEL_MIF7, 0, 1),
1170}; 1175};
1171 1176
1172static struct samsung_div_clock mif_div_clks[] __initdata = { 1177static const struct samsung_div_clock mif_div_clks[] __initconst = {
1173 /* DIV_MIF1 */ 1178 /* DIV_MIF1 */
1174 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1179 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1175 DIV_MIF1, 16, 2), 1180 DIV_MIF1, 16, 2),
@@ -1223,7 +1228,7 @@ static struct samsung_div_clock mif_div_clks[] __initdata = {
1223 0, 3), 1228 0, 3),
1224}; 1229};
1225 1230
1226static struct samsung_gate_clock mif_gate_clks[] __initdata = { 1231static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1227 /* ENABLE_ACLK_MIF0 */ 1232 /* ENABLE_ACLK_MIF0 */
1228 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1233 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1229 19, CLK_IGNORE_UNUSED, 0), 1234 19, CLK_IGNORE_UNUSED, 0),
@@ -1440,11 +1445,13 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1440 1445
1441 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1446 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1442 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1447 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1443 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), 1448 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1449 CLK_IGNORE_UNUSED, 0),
1444 1450
1445 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1451 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1446 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1452 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1447 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), 1453 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1454 CLK_IGNORE_UNUSED, 0),
1448 1455
1449 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1456 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1450 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1457 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
@@ -1486,7 +1493,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1486 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1493 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1487}; 1494};
1488 1495
1489static struct samsung_cmu_info mif_cmu_info __initdata = { 1496static const struct samsung_cmu_info mif_cmu_info __initconst = {
1490 .pll_clks = mif_pll_clks, 1497 .pll_clks = mif_pll_clks,
1491 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1498 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1492 .mux_clks = mif_mux_clks, 1499 .mux_clks = mif_mux_clks,
@@ -1522,7 +1529,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1522#define ENABLE_IP_PERIC1 0x0B04 1529#define ENABLE_IP_PERIC1 0x0B04
1523#define ENABLE_IP_PERIC2 0x0B08 1530#define ENABLE_IP_PERIC2 0x0B08
1524 1531
1525static unsigned long peric_clk_regs[] __initdata = { 1532static const unsigned long peric_clk_regs[] __initconst = {
1526 DIV_PERIC, 1533 DIV_PERIC,
1527 ENABLE_ACLK_PERIC, 1534 ENABLE_ACLK_PERIC,
1528 ENABLE_PCLK_PERIC0, 1535 ENABLE_PCLK_PERIC0,
@@ -1533,13 +1540,13 @@ static unsigned long peric_clk_regs[] __initdata = {
1533 ENABLE_IP_PERIC2, 1540 ENABLE_IP_PERIC2,
1534}; 1541};
1535 1542
1536static struct samsung_div_clock peric_div_clks[] __initdata = { 1543static const struct samsung_div_clock peric_div_clks[] __initconst = {
1537 /* DIV_PERIC */ 1544 /* DIV_PERIC */
1538 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1545 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1539 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1546 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1540}; 1547};
1541 1548
1542static struct samsung_gate_clock peric_gate_clks[] __initdata = { 1549static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1543 /* ENABLE_ACLK_PERIC */ 1550 /* ENABLE_ACLK_PERIC */
1544 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1551 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1545 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1552 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
@@ -1654,8 +1661,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1654 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1661 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1655 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1662 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1663 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1657 ENABLE_SCLK_PERIC, 12, 1664 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1658 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1659 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1665 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1660 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1666 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1661 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1667 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
@@ -1670,18 +1676,21 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1670 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1676 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1671 5, CLK_SET_RATE_PARENT, 0), 1677 5, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1678 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1673 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1679 4, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1680 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1675 3, CLK_SET_RATE_PARENT, 0), 1681 3, CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1682 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1677 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1683 ENABLE_SCLK_PERIC, 2,
1684 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1678 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1685 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1679 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1686 ENABLE_SCLK_PERIC, 1,
1687 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1680 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1688 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1681 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1689 ENABLE_SCLK_PERIC, 0,
1690 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1682}; 1691};
1683 1692
1684static struct samsung_cmu_info peric_cmu_info __initdata = { 1693static const struct samsung_cmu_info peric_cmu_info __initconst = {
1685 .div_clks = peric_div_clks, 1694 .div_clks = peric_div_clks,
1686 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1695 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1687 .gate_clks = peric_gate_clks, 1696 .gate_clks = peric_gate_clks,
@@ -1728,7 +1737,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1728#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1737#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1729#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1738#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1730 1739
1731static unsigned long peris_clk_regs[] __initdata = { 1740static const unsigned long peris_clk_regs[] __initconst = {
1732 ENABLE_ACLK_PERIS, 1741 ENABLE_ACLK_PERIS,
1733 ENABLE_PCLK_PERIS, 1742 ENABLE_PCLK_PERIS,
1734 ENABLE_PCLK_PERIS_SECURE_TZPC, 1743 ENABLE_PCLK_PERIS_SECURE_TZPC,
@@ -1756,7 +1765,7 @@ static unsigned long peris_clk_regs[] __initdata = {
1756 ENABLE_IP_PERIS_SECURE_OTP_CON, 1765 ENABLE_IP_PERIS_SECURE_OTP_CON,
1757}; 1766};
1758 1767
1759static struct samsung_gate_clock peris_gate_clks[] __initdata = { 1768static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1760 /* ENABLE_ACLK_PERIS */ 1769 /* ENABLE_ACLK_PERIS */
1761 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1770 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1762 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1771 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
@@ -1875,7 +1884,7 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1875 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1884 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1876}; 1885};
1877 1886
1878static struct samsung_cmu_info peris_cmu_info __initdata = { 1887static const struct samsung_cmu_info peris_cmu_info __initconst = {
1879 .gate_clks = peris_gate_clks, 1888 .gate_clks = peris_gate_clks,
1880 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1889 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1881 .nr_clk_ids = PERIS_NR_CLK, 1890 .nr_clk_ids = PERIS_NR_CLK,
@@ -1959,7 +1968,7 @@ PNAME(mout_sclk_mphy_p)
1959 = { "mout_sclk_ufs_mphy_user", 1968 = { "mout_sclk_ufs_mphy_user",
1960 "mout_phyclk_lli_mphy_to_ufs_user", }; 1969 "mout_phyclk_lli_mphy_to_ufs_user", };
1961 1970
1962static unsigned long fsys_clk_regs[] __initdata = { 1971static const unsigned long fsys_clk_regs[] __initconst = {
1963 MUX_SEL_FSYS0, 1972 MUX_SEL_FSYS0,
1964 MUX_SEL_FSYS1, 1973 MUX_SEL_FSYS1,
1965 MUX_SEL_FSYS2, 1974 MUX_SEL_FSYS2,
@@ -1980,7 +1989,7 @@ static unsigned long fsys_clk_regs[] __initdata = {
1980 ENABLE_IP_FSYS1, 1989 ENABLE_IP_FSYS1,
1981}; 1990};
1982 1991
1983static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = { 1992static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
1984 /* PHY clocks from USBDRD30_PHY */ 1993 /* PHY clocks from USBDRD30_PHY */
1985 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 1994 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1986 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 1995 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
@@ -2020,7 +2029,7 @@ static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
2020 NULL, 0, 26000000), 2029 NULL, 0, 26000000),
2021}; 2030};
2022 2031
2023static struct samsung_mux_clock fsys_mux_clks[] __initdata = { 2032static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2024 /* MUX_SEL_FSYS0 */ 2033 /* MUX_SEL_FSYS0 */
2025 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2034 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2026 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2035 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
@@ -2104,7 +2113,7 @@ static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2104 MUX_SEL_FSYS4, 0, 1), 2113 MUX_SEL_FSYS4, 0, 1),
2105}; 2114};
2106 2115
2107static struct samsung_gate_clock fsys_gate_clks[] __initdata = { 2116static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2108 /* ENABLE_ACLK_FSYS0 */ 2117 /* ENABLE_ACLK_FSYS0 */
2109 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2118 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2110 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2119 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
@@ -2138,7 +2147,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2138 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2147 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2139 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2148 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2140 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2149 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2141 ENABLE_ACLK_FSYS1, 24, 0, 0), 2150 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2142 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2151 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2143 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2152 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2144 22, CLK_IGNORE_UNUSED, 0), 2153 22, CLK_IGNORE_UNUSED, 0),
@@ -2185,13 +2194,13 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2185 2194
2186 /* ENABLE_PCLK_FSYS */ 2195 /* ENABLE_PCLK_FSYS */
2187 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2196 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2188 ENABLE_PCLK_FSYS, 17, 0, 0), 2197 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2189 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2198 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2190 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2199 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2191 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2200 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2192 ENABLE_PCLK_FSYS, 14, 0, 0), 2201 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2193 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2202 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2194 ENABLE_PCLK_FSYS, 13, 0, 0), 2203 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2195 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2204 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2196 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2205 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2197 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2206 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
@@ -2270,11 +2279,12 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2270 ENABLE_SCLK_FSYS, 0, 0, 0), 2279 ENABLE_SCLK_FSYS, 0, 0, 0),
2271 2280
2272 /* ENABLE_IP_FSYS0 */ 2281 /* ENABLE_IP_FSYS0 */
2282 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2273 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2283 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2274 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2284 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2275}; 2285};
2276 2286
2277static struct samsung_cmu_info fsys_cmu_info __initdata = { 2287static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2278 .mux_clks = fsys_mux_clks, 2288 .mux_clks = fsys_mux_clks,
2279 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2289 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2280 .gate_clks = fsys_gate_clks, 2290 .gate_clks = fsys_gate_clks,
@@ -2310,7 +2320,7 @@ CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2310#define DIV_ENABLE_IP_G2D1 0x0b04 2320#define DIV_ENABLE_IP_G2D1 0x0b04
2311#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2321#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2312 2322
2313static unsigned long g2d_clk_regs[] __initdata = { 2323static const unsigned long g2d_clk_regs[] __initconst = {
2314 MUX_SEL_G2D0, 2324 MUX_SEL_G2D0,
2315 MUX_SEL_ENABLE_G2D0, 2325 MUX_SEL_ENABLE_G2D0,
2316 DIV_G2D, 2326 DIV_G2D,
@@ -2327,7 +2337,7 @@ static unsigned long g2d_clk_regs[] __initdata = {
2327PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2337PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2328PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2338PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2329 2339
2330static struct samsung_mux_clock g2d_mux_clks[] __initdata = { 2340static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2331 /* MUX_SEL_G2D0 */ 2341 /* MUX_SEL_G2D0 */
2332 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2342 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2333 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2343 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
@@ -2335,13 +2345,13 @@ static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2335 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2345 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2336}; 2346};
2337 2347
2338static struct samsung_div_clock g2d_div_clks[] __initdata = { 2348static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2339 /* DIV_G2D */ 2349 /* DIV_G2D */
2340 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2350 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2341 DIV_G2D, 0, 2), 2351 DIV_G2D, 0, 2),
2342}; 2352};
2343 2353
2344static struct samsung_gate_clock g2d_gate_clks[] __initdata = { 2354static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2345 /* DIV_ENABLE_ACLK_G2D */ 2355 /* DIV_ENABLE_ACLK_G2D */
2346 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2356 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2347 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2357 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
@@ -2398,7 +2408,7 @@ static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2398 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2408 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2399}; 2409};
2400 2410
2401static struct samsung_cmu_info g2d_cmu_info __initdata = { 2411static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2402 .mux_clks = g2d_mux_clks, 2412 .mux_clks = g2d_mux_clks,
2403 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2413 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2404 .div_clks = g2d_div_clks, 2414 .div_clks = g2d_div_clks,
@@ -2454,7 +2464,7 @@ CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2454#define CLKOUT_CMU_DISP 0x0c00 2464#define CLKOUT_CMU_DISP 0x0c00
2455#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2465#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2456 2466
2457static unsigned long disp_clk_regs[] __initdata = { 2467static const unsigned long disp_clk_regs[] __initconst = {
2458 DISP_PLL_LOCK, 2468 DISP_PLL_LOCK,
2459 DISP_PLL_CON0, 2469 DISP_PLL_CON0,
2460 DISP_PLL_CON1, 2470 DISP_PLL_CON1,
@@ -2527,12 +2537,12 @@ PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2527PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2537PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2528 "mout_sclk_decon_tv_vclk_user", }; 2538 "mout_sclk_decon_tv_vclk_user", };
2529 2539
2530static struct samsung_pll_clock disp_pll_clks[] __initdata = { 2540static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2531 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2541 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2532 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), 2542 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2533}; 2543};
2534 2544
2535static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { 2545static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2536 /* 2546 /*
2537 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2547 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2538 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2548 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
@@ -2544,7 +2554,7 @@ static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2544 1, 2, 0), 2554 1, 2, 0),
2545}; 2555};
2546 2556
2547static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { 2557static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2548 /* PHY clocks from MIPI_DPHY1 */ 2558 /* PHY clocks from MIPI_DPHY1 */
2549 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2559 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2550 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2560 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
@@ -2558,7 +2568,7 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2558 NULL, 0, 166000000), 2568 NULL, 0, 166000000),
2559}; 2569};
2560 2570
2561static struct samsung_mux_clock disp_mux_clks[] __initdata = { 2571static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2562 /* MUX_SEL_DISP0 */ 2572 /* MUX_SEL_DISP0 */
2563 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2573 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2564 0, 1), 2574 0, 1),
@@ -2633,7 +2643,7 @@ static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2633 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2643 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2634}; 2644};
2635 2645
2636static struct samsung_div_clock disp_div_clks[] __initdata = { 2646static const struct samsung_div_clock disp_div_clks[] __initconst = {
2637 /* DIV_DISP */ 2647 /* DIV_DISP */
2638 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2648 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2639 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2649 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
@@ -2651,7 +2661,7 @@ static struct samsung_div_clock disp_div_clks[] __initdata = {
2651 DIV_DISP, 0, 2), 2661 DIV_DISP, 0, 2),
2652}; 2662};
2653 2663
2654static struct samsung_gate_clock disp_gate_clks[] __initdata = { 2664static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2655 /* ENABLE_ACLK_DISP0 */ 2665 /* ENABLE_ACLK_DISP0 */
2656 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2666 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2657 ENABLE_ACLK_DISP0, 2, 0, 0), 2667 ENABLE_ACLK_DISP0, 2, 0, 0),
@@ -2811,7 +2821,7 @@ static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2811 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2821 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2812}; 2822};
2813 2823
2814static struct samsung_cmu_info disp_cmu_info __initdata = { 2824static const struct samsung_cmu_info disp_cmu_info __initconst = {
2815 .pll_clks = disp_pll_clks, 2825 .pll_clks = disp_pll_clks,
2816 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2826 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2817 .mux_clks = disp_mux_clks, 2827 .mux_clks = disp_mux_clks,
@@ -2856,7 +2866,7 @@ CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2856#define ENABLE_IP_AUD0 0x0b00 2866#define ENABLE_IP_AUD0 0x0b00
2857#define ENABLE_IP_AUD1 0x0b04 2867#define ENABLE_IP_AUD1 0x0b04
2858 2868
2859static unsigned long aud_clk_regs[] __initdata = { 2869static const unsigned long aud_clk_regs[] __initconst = {
2860 MUX_SEL_AUD0, 2870 MUX_SEL_AUD0,
2861 MUX_SEL_AUD1, 2871 MUX_SEL_AUD1,
2862 MUX_ENABLE_AUD0, 2872 MUX_ENABLE_AUD0,
@@ -2875,13 +2885,13 @@ static unsigned long aud_clk_regs[] __initdata = {
2875PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2885PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2876PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2886PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2877 2887
2878static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { 2888static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2879 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2889 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2880 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2890 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2881 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2891 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2882}; 2892};
2883 2893
2884static struct samsung_mux_clock aud_mux_clks[] __initdata = { 2894static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2885 /* MUX_SEL_AUD0 */ 2895 /* MUX_SEL_AUD0 */
2886 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2896 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2887 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2897 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
@@ -2893,7 +2903,7 @@ static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2893 MUX_SEL_AUD1, 0, 1), 2903 MUX_SEL_AUD1, 0, 1),
2894}; 2904};
2895 2905
2896static struct samsung_div_clock aud_div_clks[] __initdata = { 2906static const struct samsung_div_clock aud_div_clks[] __initconst = {
2897 /* DIV_AUD0 */ 2907 /* DIV_AUD0 */
2898 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2908 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2899 12, 4), 2909 12, 4),
@@ -2915,7 +2925,7 @@ static struct samsung_div_clock aud_div_clks[] __initdata = {
2915 DIV_AUD1, 0, 4), 2925 DIV_AUD1, 0, 4),
2916}; 2926};
2917 2927
2918static struct samsung_gate_clock aud_gate_clks[] __initdata = { 2928static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2919 /* ENABLE_ACLK_AUD */ 2929 /* ENABLE_ACLK_AUD */
2920 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 2930 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2921 ENABLE_ACLK_AUD, 12, 0, 0), 2931 ENABLE_ACLK_AUD, 12, 0, 0),
@@ -2962,7 +2972,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2962 2972
2963 /* ENABLE_SCLK_AUD0 */ 2973 /* ENABLE_SCLK_AUD0 */
2964 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 2974 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2965 2, 0, 0), 2975 2, CLK_IGNORE_UNUSED, 0),
2966 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 2976 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2967 ENABLE_SCLK_AUD0, 1, 0, 0), 2977 ENABLE_SCLK_AUD0, 1, 0, 0),
2968 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 2978 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
@@ -2976,7 +2986,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2976 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 2986 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2977 ENABLE_SCLK_AUD1, 4, 0, 0), 2987 ENABLE_SCLK_AUD1, 4, 0, 0),
2978 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 2988 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2979 ENABLE_SCLK_AUD1, 3, 0, 0), 2989 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
2980 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 2990 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2981 ENABLE_SCLK_AUD1, 2, 0, 0), 2991 ENABLE_SCLK_AUD1, 2, 0, 0),
2982 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 2992 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
@@ -2985,7 +2995,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2985 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 2995 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2986}; 2996};
2987 2997
2988static struct samsung_cmu_info aud_cmu_info __initdata = { 2998static const struct samsung_cmu_info aud_cmu_info __initconst = {
2989 .mux_clks = aud_mux_clks, 2999 .mux_clks = aud_mux_clks,
2990 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3000 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
2991 .div_clks = aud_div_clks, 3001 .div_clks = aud_div_clks,
@@ -3031,24 +3041,24 @@ PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3031 ENABLE_IP_BUS0, \ 3041 ENABLE_IP_BUS0, \
3032 ENABLE_IP_BUS1 3042 ENABLE_IP_BUS1
3033 3043
3034static unsigned long bus01_clk_regs[] __initdata = { 3044static const unsigned long bus01_clk_regs[] __initconst = {
3035 CMU_BUS_COMMON_CLK_REGS, 3045 CMU_BUS_COMMON_CLK_REGS,
3036}; 3046};
3037 3047
3038static unsigned long bus2_clk_regs[] __initdata = { 3048static const unsigned long bus2_clk_regs[] __initconst = {
3039 MUX_SEL_BUS2, 3049 MUX_SEL_BUS2,
3040 MUX_ENABLE_BUS2, 3050 MUX_ENABLE_BUS2,
3041 CMU_BUS_COMMON_CLK_REGS, 3051 CMU_BUS_COMMON_CLK_REGS,
3042}; 3052};
3043 3053
3044static struct samsung_div_clock bus0_div_clks[] __initdata = { 3054static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3045 /* DIV_BUS0 */ 3055 /* DIV_BUS0 */
3046 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3056 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3047 DIV_BUS, 0, 3), 3057 DIV_BUS, 0, 3),
3048}; 3058};
3049 3059
3050/* CMU_BUS0 clocks */ 3060/* CMU_BUS0 clocks */
3051static struct samsung_gate_clock bus0_gate_clks[] __initdata = { 3061static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3052 /* ENABLE_ACLK_BUS0 */ 3062 /* ENABLE_ACLK_BUS0 */
3053 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3063 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3054 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3064 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
@@ -3067,13 +3077,13 @@ static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3067}; 3077};
3068 3078
3069/* CMU_BUS1 clocks */ 3079/* CMU_BUS1 clocks */
3070static struct samsung_div_clock bus1_div_clks[] __initdata = { 3080static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3071 /* DIV_BUS1 */ 3081 /* DIV_BUS1 */
3072 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3082 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3073 DIV_BUS, 0, 3), 3083 DIV_BUS, 0, 3),
3074}; 3084};
3075 3085
3076static struct samsung_gate_clock bus1_gate_clks[] __initdata = { 3086static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3077 /* ENABLE_ACLK_BUS1 */ 3087 /* ENABLE_ACLK_BUS1 */
3078 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3088 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3079 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3089 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
@@ -3092,19 +3102,19 @@ static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3092}; 3102};
3093 3103
3094/* CMU_BUS2 clocks */ 3104/* CMU_BUS2 clocks */
3095static struct samsung_mux_clock bus2_mux_clks[] __initdata = { 3105static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3096 /* MUX_SEL_BUS2 */ 3106 /* MUX_SEL_BUS2 */
3097 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3107 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3098 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3108 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3099}; 3109};
3100 3110
3101static struct samsung_div_clock bus2_div_clks[] __initdata = { 3111static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3102 /* DIV_BUS2 */ 3112 /* DIV_BUS2 */
3103 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3113 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3104 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3114 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3105}; 3115};
3106 3116
3107static struct samsung_gate_clock bus2_gate_clks[] __initdata = { 3117static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3108 /* ENABLE_ACLK_BUS2 */ 3118 /* ENABLE_ACLK_BUS2 */
3109 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3119 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3110 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3120 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
@@ -3133,19 +3143,19 @@ static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3133 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3143 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3134 .nr_clk_ids = BUSx_NR_CLK 3144 .nr_clk_ids = BUSx_NR_CLK
3135 3145
3136static struct samsung_cmu_info bus0_cmu_info __initdata = { 3146static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3137 CMU_BUS_INFO_CLKS(0), 3147 CMU_BUS_INFO_CLKS(0),
3138 .clk_regs = bus01_clk_regs, 3148 .clk_regs = bus01_clk_regs,
3139 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3149 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3140}; 3150};
3141 3151
3142static struct samsung_cmu_info bus1_cmu_info __initdata = { 3152static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3143 CMU_BUS_INFO_CLKS(1), 3153 CMU_BUS_INFO_CLKS(1),
3144 .clk_regs = bus01_clk_regs, 3154 .clk_regs = bus01_clk_regs,
3145 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3155 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3146}; 3156};
3147 3157
3148static struct samsung_cmu_info bus2_cmu_info __initdata = { 3158static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3149 CMU_BUS_INFO_CLKS(2), 3159 CMU_BUS_INFO_CLKS(2),
3150 .mux_clks = bus2_mux_clks, 3160 .mux_clks = bus2_mux_clks,
3151 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3161 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
@@ -3189,7 +3199,7 @@ exynos5433_cmu_bus_init(2);
3189#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3199#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3190#define CLK_STOPCTRL 0x1000 3200#define CLK_STOPCTRL 0x1000
3191 3201
3192static unsigned long g3d_clk_regs[] __initdata = { 3202static const unsigned long g3d_clk_regs[] __initconst = {
3193 G3D_PLL_LOCK, 3203 G3D_PLL_LOCK,
3194 G3D_PLL_CON0, 3204 G3D_PLL_CON0,
3195 G3D_PLL_CON1, 3205 G3D_PLL_CON1,
@@ -3212,12 +3222,12 @@ static unsigned long g3d_clk_regs[] __initdata = {
3212PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3222PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3213PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3223PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3214 3224
3215static struct samsung_pll_clock g3d_pll_clks[] __initdata = { 3225static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3216 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3226 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3217 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), 3227 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3218}; 3228};
3219 3229
3220static struct samsung_mux_clock g3d_mux_clks[] __initdata = { 3230static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3221 /* MUX_SEL_G3D */ 3231 /* MUX_SEL_G3D */
3222 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3232 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3223 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3233 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
@@ -3225,7 +3235,7 @@ static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3225 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3235 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3226}; 3236};
3227 3237
3228static struct samsung_div_clock g3d_div_clks[] __initdata = { 3238static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3229 /* DIV_G3D */ 3239 /* DIV_G3D */
3230 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3240 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3231 8, 2), 3241 8, 2),
@@ -3235,7 +3245,7 @@ static struct samsung_div_clock g3d_div_clks[] __initdata = {
3235 0, 3, CLK_SET_RATE_PARENT, 0), 3245 0, 3, CLK_SET_RATE_PARENT, 0),
3236}; 3246};
3237 3247
3238static struct samsung_gate_clock g3d_gate_clks[] __initdata = { 3248static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3239 /* ENABLE_ACLK_G3D */ 3249 /* ENABLE_ACLK_G3D */
3240 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3250 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3241 ENABLE_ACLK_G3D, 7, 0, 0), 3251 ENABLE_ACLK_G3D, 7, 0, 0),
@@ -3269,7 +3279,7 @@ static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3269 ENABLE_SCLK_G3D, 0, 0, 0), 3279 ENABLE_SCLK_G3D, 0, 0, 0),
3270}; 3280};
3271 3281
3272static struct samsung_cmu_info g3d_cmu_info __initdata = { 3282static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3273 .pll_clks = g3d_pll_clks, 3283 .pll_clks = g3d_pll_clks,
3274 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3284 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3275 .mux_clks = g3d_mux_clks, 3285 .mux_clks = g3d_mux_clks,
@@ -3310,7 +3320,7 @@ CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3310#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3320#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3311#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3321#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3312 3322
3313static unsigned long gscl_clk_regs[] __initdata = { 3323static const unsigned long gscl_clk_regs[] __initconst = {
3314 MUX_SEL_GSCL, 3324 MUX_SEL_GSCL,
3315 MUX_ENABLE_GSCL, 3325 MUX_ENABLE_GSCL,
3316 ENABLE_ACLK_GSCL, 3326 ENABLE_ACLK_GSCL,
@@ -3332,7 +3342,7 @@ static unsigned long gscl_clk_regs[] __initdata = {
3332PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3342PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3333PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3343PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3334 3344
3335static struct samsung_mux_clock gscl_mux_clks[] __initdata = { 3345static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3336 /* MUX_SEL_GSCL */ 3346 /* MUX_SEL_GSCL */
3337 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3347 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3338 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3348 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
@@ -3340,7 +3350,7 @@ static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3340 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3350 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3341}; 3351};
3342 3352
3343static struct samsung_gate_clock gscl_gate_clks[] __initdata = { 3353static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3344 /* ENABLE_ACLK_GSCL */ 3354 /* ENABLE_ACLK_GSCL */
3345 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3355 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3346 ENABLE_ACLK_GSCL, 11, 0, 0), 3356 ENABLE_ACLK_GSCL, 11, 0, 0),
@@ -3356,9 +3366,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3356 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3366 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3357 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3367 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3358 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3368 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3359 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0), 3369 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3370 CLK_IGNORE_UNUSED, 0),
3360 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3371 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3361 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0), 3372 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3373 CLK_IGNORE_UNUSED, 0),
3362 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3374 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3363 ENABLE_ACLK_GSCL, 3, 0, 0), 3375 ENABLE_ACLK_GSCL, 3, 0, 0),
3364 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3376 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
@@ -3412,7 +3424,7 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3412 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3424 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3413}; 3425};
3414 3426
3415static struct samsung_cmu_info gscl_cmu_info __initdata = { 3427static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3416 .mux_clks = gscl_mux_clks, 3428 .mux_clks = gscl_mux_clks,
3417 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3429 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3418 .gate_clks = gscl_gate_clks, 3430 .gate_clks = gscl_gate_clks,
@@ -3465,7 +3477,7 @@ CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3465#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3477#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3466#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3478#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3467 3479
3468static unsigned long apollo_clk_regs[] __initdata = { 3480static const unsigned long apollo_clk_regs[] __initconst = {
3469 APOLLO_PLL_LOCK, 3481 APOLLO_PLL_LOCK,
3470 APOLLO_PLL_CON0, 3482 APOLLO_PLL_CON0,
3471 APOLLO_PLL_CON1, 3483 APOLLO_PLL_CON1,
@@ -3500,15 +3512,16 @@ PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3500PNAME(mout_apollo_p) = { "mout_apollo_pll", 3512PNAME(mout_apollo_p) = { "mout_apollo_pll",
3501 "mout_bus_pll_apollo_user", }; 3513 "mout_bus_pll_apollo_user", };
3502 3514
3503static struct samsung_pll_clock apollo_pll_clks[] __initdata = { 3515static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3504 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3516 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3505 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), 3517 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3506}; 3518};
3507 3519
3508static struct samsung_mux_clock apollo_mux_clks[] __initdata = { 3520static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3509 /* MUX_SEL_APOLLO0 */ 3521 /* MUX_SEL_APOLLO0 */
3510 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3522 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3511 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), 3523 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3524 CLK_RECALC_NEW_RATES, 0),
3512 3525
3513 /* MUX_SEL_APOLLO1 */ 3526 /* MUX_SEL_APOLLO1 */
3514 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3527 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
@@ -3519,7 +3532,7 @@ static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3519 0, 1, CLK_SET_RATE_PARENT, 0), 3532 0, 1, CLK_SET_RATE_PARENT, 0),
3520}; 3533};
3521 3534
3522static struct samsung_div_clock apollo_div_clks[] __initdata = { 3535static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3523 /* DIV_APOLLO0 */ 3536 /* DIV_APOLLO0 */
3524 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3537 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3525 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3538 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
@@ -3550,7 +3563,7 @@ static struct samsung_div_clock apollo_div_clks[] __initdata = {
3550 CLK_DIVIDER_READ_ONLY), 3563 CLK_DIVIDER_READ_ONLY),
3551}; 3564};
3552 3565
3553static struct samsung_gate_clock apollo_gate_clks[] __initdata = { 3566static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3554 /* ENABLE_ACLK_APOLLO */ 3567 /* ENABLE_ACLK_APOLLO */
3555 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3568 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3556 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3569 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
@@ -3589,28 +3602,64 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3589 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3602 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3590 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3603 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3591 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3604 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3592 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2",
3593 ENABLE_SCLK_APOLLO, 0,
3594 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3595}; 3605};
3596 3606
3597static struct samsung_cmu_info apollo_cmu_info __initdata = { 3607#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3598 .pll_clks = apollo_pll_clks, 3608 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3599 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), 3609 ((pclk) << 12) | ((aclk) << 8))
3600 .mux_clks = apollo_mux_clks, 3610
3601 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), 3611#define E5433_APOLLO_DIV1(hpm, copy) \
3602 .div_clks = apollo_div_clks, 3612 (((hpm) << 4) | ((copy) << 0))
3603 .nr_div_clks = ARRAY_SIZE(apollo_div_clks), 3613
3604 .gate_clks = apollo_gate_clks, 3614static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3605 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), 3615 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3606 .nr_clk_ids = APOLLO_NR_CLK, 3616 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3607 .clk_regs = apollo_clk_regs, 3617 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3608 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), 3618 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3619 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3620 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3621 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3622 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3623 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3624 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3625 { 0 },
3609}; 3626};
3610 3627
3611static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3628static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3612{ 3629{
3613 samsung_cmu_register_one(np, &apollo_cmu_info); 3630 void __iomem *reg_base;
3631 struct samsung_clk_provider *ctx;
3632
3633 reg_base = of_iomap(np, 0);
3634 if (!reg_base) {
3635 panic("%s: failed to map registers\n", __func__);
3636 return;
3637 }
3638
3639 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3640 if (!ctx) {
3641 panic("%s: unable to allocate ctx\n", __func__);
3642 return;
3643 }
3644
3645 samsung_clk_register_pll(ctx, apollo_pll_clks,
3646 ARRAY_SIZE(apollo_pll_clks), reg_base);
3647 samsung_clk_register_mux(ctx, apollo_mux_clks,
3648 ARRAY_SIZE(apollo_mux_clks));
3649 samsung_clk_register_div(ctx, apollo_div_clks,
3650 ARRAY_SIZE(apollo_div_clks));
3651 samsung_clk_register_gate(ctx, apollo_gate_clks,
3652 ARRAY_SIZE(apollo_gate_clks));
3653
3654 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3655 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3656 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3657 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3658
3659 samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3660 ARRAY_SIZE(apollo_clk_regs));
3661
3662 samsung_clk_of_add_provider(np, ctx);
3614} 3663}
3615CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3664CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3616 exynos5433_cmu_apollo_init); 3665 exynos5433_cmu_apollo_init);
@@ -3651,7 +3700,7 @@ CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3651#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3700#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3652#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3701#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3653 3702
3654static unsigned long atlas_clk_regs[] __initdata = { 3703static const unsigned long atlas_clk_regs[] __initconst = {
3655 ATLAS_PLL_LOCK, 3704 ATLAS_PLL_LOCK,
3656 ATLAS_PLL_CON0, 3705 ATLAS_PLL_CON0,
3657 ATLAS_PLL_CON1, 3706 ATLAS_PLL_CON1,
@@ -3686,15 +3735,16 @@ PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3686PNAME(mout_atlas_p) = { "mout_atlas_pll", 3735PNAME(mout_atlas_p) = { "mout_atlas_pll",
3687 "mout_bus_pll_atlas_user", }; 3736 "mout_bus_pll_atlas_user", };
3688 3737
3689static struct samsung_pll_clock atlas_pll_clks[] __initdata = { 3738static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3690 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3739 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3691 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), 3740 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3692}; 3741};
3693 3742
3694static struct samsung_mux_clock atlas_mux_clks[] __initdata = { 3743static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3695 /* MUX_SEL_ATLAS0 */ 3744 /* MUX_SEL_ATLAS0 */
3696 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3745 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3697 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), 3746 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3747 CLK_RECALC_NEW_RATES, 0),
3698 3748
3699 /* MUX_SEL_ATLAS1 */ 3749 /* MUX_SEL_ATLAS1 */
3700 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3750 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
@@ -3705,7 +3755,7 @@ static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3705 0, 1, CLK_SET_RATE_PARENT, 0), 3755 0, 1, CLK_SET_RATE_PARENT, 0),
3706}; 3756};
3707 3757
3708static struct samsung_div_clock atlas_div_clks[] __initdata = { 3758static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3709 /* DIV_ATLAS0 */ 3759 /* DIV_ATLAS0 */
3710 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3760 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3711 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3761 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
@@ -3736,7 +3786,7 @@ static struct samsung_div_clock atlas_div_clks[] __initdata = {
3736 CLK_DIVIDER_READ_ONLY), 3786 CLK_DIVIDER_READ_ONLY),
3737}; 3787};
3738 3788
3739static struct samsung_gate_clock atlas_gate_clks[] __initdata = { 3789static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3740 /* ENABLE_ACLK_ATLAS */ 3790 /* ENABLE_ACLK_ATLAS */
3741 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3791 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3742 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3792 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
@@ -3801,28 +3851,69 @@ static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3801 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3851 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3802 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3852 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3803 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3853 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3804 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3805 ENABLE_SCLK_ATLAS, 0,
3806 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3807}; 3854};
3808 3855
3809static struct samsung_cmu_info atlas_cmu_info __initdata = { 3856#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3810 .pll_clks = atlas_pll_clks, 3857 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3811 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks), 3858 ((pclk) << 12) | ((aclk) << 8))
3812 .mux_clks = atlas_mux_clks, 3859
3813 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks), 3860#define E5433_ATLAS_DIV1(hpm, copy) \
3814 .div_clks = atlas_div_clks, 3861 (((hpm) << 4) | ((copy) << 0))
3815 .nr_div_clks = ARRAY_SIZE(atlas_div_clks), 3862
3816 .gate_clks = atlas_gate_clks, 3863static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3817 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks), 3864 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3818 .nr_clk_ids = ATLAS_NR_CLK, 3865 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3819 .clk_regs = atlas_clk_regs, 3866 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3820 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs), 3867 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3868 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3869 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3870 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3871 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3872 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3873 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3874 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3875 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3876 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3877 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3878 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3879 { 0 },
3821}; 3880};
3822 3881
3823static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3882static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3824{ 3883{
3825 samsung_cmu_register_one(np, &atlas_cmu_info); 3884 void __iomem *reg_base;
3885 struct samsung_clk_provider *ctx;
3886
3887 reg_base = of_iomap(np, 0);
3888 if (!reg_base) {
3889 panic("%s: failed to map registers\n", __func__);
3890 return;
3891 }
3892
3893 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3894 if (!ctx) {
3895 panic("%s: unable to allocate ctx\n", __func__);
3896 return;
3897 }
3898
3899 samsung_clk_register_pll(ctx, atlas_pll_clks,
3900 ARRAY_SIZE(atlas_pll_clks), reg_base);
3901 samsung_clk_register_mux(ctx, atlas_mux_clks,
3902 ARRAY_SIZE(atlas_mux_clks));
3903 samsung_clk_register_div(ctx, atlas_div_clks,
3904 ARRAY_SIZE(atlas_div_clks));
3905 samsung_clk_register_gate(ctx, atlas_gate_clks,
3906 ARRAY_SIZE(atlas_gate_clks));
3907
3908 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3909 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3910 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3911 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3912
3913 samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3914 ARRAY_SIZE(atlas_clk_regs));
3915
3916 samsung_clk_of_add_provider(np, ctx);
3826} 3917}
3827CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3918CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3828 exynos5433_cmu_atlas_init); 3919 exynos5433_cmu_atlas_init);
@@ -3853,7 +3944,7 @@ CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3853#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3944#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3854#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3945#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3855 3946
3856static unsigned long mscl_clk_regs[] __initdata = { 3947static const unsigned long mscl_clk_regs[] __initconst = {
3857 MUX_SEL_MSCL0, 3948 MUX_SEL_MSCL0,
3858 MUX_SEL_MSCL1, 3949 MUX_SEL_MSCL1,
3859 MUX_ENABLE_MSCL0, 3950 MUX_ENABLE_MSCL0,
@@ -3881,7 +3972,7 @@ PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3881PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 3972PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3882 "mout_aclk_mscl_400_user", }; 3973 "mout_aclk_mscl_400_user", };
3883 3974
3884static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 3975static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
3885 /* MUX_SEL_MSCL0 */ 3976 /* MUX_SEL_MSCL0 */
3886 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 3977 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3887 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 3978 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
@@ -3893,13 +3984,13 @@ static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3893 MUX_SEL_MSCL1, 0, 1), 3984 MUX_SEL_MSCL1, 0, 1),
3894}; 3985};
3895 3986
3896static struct samsung_div_clock mscl_div_clks[] __initdata = { 3987static const struct samsung_div_clock mscl_div_clks[] __initconst = {
3897 /* DIV_MSCL */ 3988 /* DIV_MSCL */
3898 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 3989 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3899 DIV_MSCL, 0, 3), 3990 DIV_MSCL, 0, 3),
3900}; 3991};
3901 3992
3902static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 3993static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
3903 /* ENABLE_ACLK_MSCL */ 3994 /* ENABLE_ACLK_MSCL */
3904 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 3995 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3905 ENABLE_ACLK_MSCL, 9, 0, 0), 3996 ENABLE_ACLK_MSCL, 9, 0, 0),
@@ -3977,7 +4068,7 @@ static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3977 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4068 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3978}; 4069};
3979 4070
3980static struct samsung_cmu_info mscl_cmu_info __initdata = { 4071static const struct samsung_cmu_info mscl_cmu_info __initconst = {
3981 .mux_clks = mscl_mux_clks, 4072 .mux_clks = mscl_mux_clks,
3982 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4073 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
3983 .div_clks = mscl_div_clks, 4074 .div_clks = mscl_div_clks,
@@ -4012,7 +4103,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4012#define ENABLE_IP_MFC1 0x0b04 4103#define ENABLE_IP_MFC1 0x0b04
4013#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4104#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4014 4105
4015static unsigned long mfc_clk_regs[] __initdata = { 4106static const unsigned long mfc_clk_regs[] __initconst = {
4016 MUX_SEL_MFC, 4107 MUX_SEL_MFC,
4017 MUX_ENABLE_MFC, 4108 MUX_ENABLE_MFC,
4018 DIV_MFC, 4109 DIV_MFC,
@@ -4027,19 +4118,19 @@ static unsigned long mfc_clk_regs[] __initdata = {
4027 4118
4028PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4119PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4029 4120
4030static struct samsung_mux_clock mfc_mux_clks[] __initdata = { 4121static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4031 /* MUX_SEL_MFC */ 4122 /* MUX_SEL_MFC */
4032 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4123 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4033 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4124 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4034}; 4125};
4035 4126
4036static struct samsung_div_clock mfc_div_clks[] __initdata = { 4127static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4037 /* DIV_MFC */ 4128 /* DIV_MFC */
4038 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4129 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4039 DIV_MFC, 0, 2), 4130 DIV_MFC, 0, 2),
4040}; 4131};
4041 4132
4042static struct samsung_gate_clock mfc_gate_clks[] __initdata = { 4133static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4043 /* ENABLE_ACLK_MFC */ 4134 /* ENABLE_ACLK_MFC */
4044 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4135 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4045 ENABLE_ACLK_MFC, 6, 0, 0), 4136 ENABLE_ACLK_MFC, 6, 0, 0),
@@ -4085,7 +4176,7 @@ static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4085 0, CLK_IGNORE_UNUSED, 0), 4176 0, CLK_IGNORE_UNUSED, 0),
4086}; 4177};
4087 4178
4088static struct samsung_cmu_info mfc_cmu_info __initdata = { 4179static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4089 .mux_clks = mfc_mux_clks, 4180 .mux_clks = mfc_mux_clks,
4090 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4181 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4091 .div_clks = mfc_div_clks, 4182 .div_clks = mfc_div_clks,
@@ -4120,7 +4211,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4120#define ENABLE_IP_HEVC1 0x0b04 4211#define ENABLE_IP_HEVC1 0x0b04
4121#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4212#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4122 4213
4123static unsigned long hevc_clk_regs[] __initdata = { 4214static const unsigned long hevc_clk_regs[] __initconst = {
4124 MUX_SEL_HEVC, 4215 MUX_SEL_HEVC,
4125 MUX_ENABLE_HEVC, 4216 MUX_ENABLE_HEVC,
4126 DIV_HEVC, 4217 DIV_HEVC,
@@ -4135,19 +4226,19 @@ static unsigned long hevc_clk_regs[] __initdata = {
4135 4226
4136PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4227PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4137 4228
4138static struct samsung_mux_clock hevc_mux_clks[] __initdata = { 4229static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4139 /* MUX_SEL_HEVC */ 4230 /* MUX_SEL_HEVC */
4140 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4231 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4141 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4232 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4142}; 4233};
4143 4234
4144static struct samsung_div_clock hevc_div_clks[] __initdata = { 4235static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4145 /* DIV_HEVC */ 4236 /* DIV_HEVC */
4146 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4237 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4147 DIV_HEVC, 0, 2), 4238 DIV_HEVC, 0, 2),
4148}; 4239};
4149 4240
4150static struct samsung_gate_clock hevc_gate_clks[] __initdata = { 4241static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4151 /* ENABLE_ACLK_HEVC */ 4242 /* ENABLE_ACLK_HEVC */
4152 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4243 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4153 ENABLE_ACLK_HEVC, 6, 0, 0), 4244 ENABLE_ACLK_HEVC, 6, 0, 0),
@@ -4195,7 +4286,7 @@ static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4195 0, CLK_IGNORE_UNUSED, 0), 4286 0, CLK_IGNORE_UNUSED, 0),
4196}; 4287};
4197 4288
4198static struct samsung_cmu_info hevc_cmu_info __initdata = { 4289static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4199 .mux_clks = hevc_mux_clks, 4290 .mux_clks = hevc_mux_clks,
4200 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4291 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4201 .div_clks = hevc_div_clks, 4292 .div_clks = hevc_div_clks,
@@ -4232,7 +4323,7 @@ CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4232#define ENABLE_IP_ISP2 0x0b08 4323#define ENABLE_IP_ISP2 0x0b08
4233#define ENABLE_IP_ISP3 0x0b0c 4324#define ENABLE_IP_ISP3 0x0b0c
4234 4325
4235static unsigned long isp_clk_regs[] __initdata = { 4326static const unsigned long isp_clk_regs[] __initconst = {
4236 MUX_SEL_ISP, 4327 MUX_SEL_ISP,
4237 MUX_ENABLE_ISP, 4328 MUX_ENABLE_ISP,
4238 DIV_ISP, 4329 DIV_ISP,
@@ -4250,7 +4341,7 @@ static unsigned long isp_clk_regs[] __initdata = {
4250PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4341PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4251PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4342PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4252 4343
4253static struct samsung_mux_clock isp_mux_clks[] __initdata = { 4344static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4254 /* MUX_SEL_ISP */ 4345 /* MUX_SEL_ISP */
4255 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4346 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4256 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4347 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
@@ -4258,7 +4349,7 @@ static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4258 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4349 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4259}; 4350};
4260 4351
4261static struct samsung_div_clock isp_div_clks[] __initdata = { 4352static const struct samsung_div_clock isp_div_clks[] __initconst = {
4262 /* DIV_ISP */ 4353 /* DIV_ISP */
4263 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4354 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4264 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4355 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
@@ -4270,7 +4361,7 @@ static struct samsung_div_clock isp_div_clks[] __initdata = {
4270 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4361 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4271}; 4362};
4272 4363
4273static struct samsung_gate_clock isp_gate_clks[] __initdata = { 4364static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4274 /* ENABLE_ACLK_ISP0 */ 4365 /* ENABLE_ACLK_ISP0 */
4275 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4366 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4276 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4367 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
@@ -4448,7 +4539,7 @@ static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4448 0, CLK_IGNORE_UNUSED, 0), 4539 0, CLK_IGNORE_UNUSED, 0),
4449}; 4540};
4450 4541
4451static struct samsung_cmu_info isp_cmu_info __initdata = { 4542static const struct samsung_cmu_info isp_cmu_info __initconst = {
4452 .mux_clks = isp_mux_clks, 4543 .mux_clks = isp_mux_clks,
4453 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4544 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4454 .div_clks = isp_div_clks, 4545 .div_clks = isp_div_clks,
@@ -4504,7 +4595,7 @@ CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4504#define ENABLE_IP_CAM02 0X0b08 4595#define ENABLE_IP_CAM02 0X0b08
4505#define ENABLE_IP_CAM03 0X0b0C 4596#define ENABLE_IP_CAM03 0X0b0C
4506 4597
4507static unsigned long cam0_clk_regs[] __initdata = { 4598static const unsigned long cam0_clk_regs[] __initconst = {
4508 MUX_SEL_CAM00, 4599 MUX_SEL_CAM00,
4509 MUX_SEL_CAM01, 4600 MUX_SEL_CAM01,
4510 MUX_SEL_CAM02, 4601 MUX_SEL_CAM02,
@@ -4588,14 +4679,14 @@ PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4588 "mout_aclk_cam0_552_user", 4679 "mout_aclk_cam0_552_user",
4589 "mout_aclk_cam0_400_user", }; 4680 "mout_aclk_cam0_400_user", };
4590 4681
4591static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = { 4682static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4592 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4683 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4593 NULL, 0, 100000000), 4684 NULL, 0, 100000000),
4594 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4685 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4595 NULL, 0, 100000000), 4686 NULL, 0, 100000000),
4596}; 4687};
4597 4688
4598static struct samsung_mux_clock cam0_mux_clks[] __initdata = { 4689static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4599 /* MUX_SEL_CAM00 */ 4690 /* MUX_SEL_CAM00 */
4600 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4691 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4601 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4692 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
@@ -4669,7 +4760,7 @@ static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4669 MUX_SEL_CAM04, 0, 1), 4760 MUX_SEL_CAM04, 0, 1),
4670}; 4761};
4671 4762
4672static struct samsung_div_clock cam0_div_clks[] __initdata = { 4763static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4673 /* DIV_CAM00 */ 4764 /* DIV_CAM00 */
4674 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4765 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4675 DIV_CAM00, 8, 2), 4766 DIV_CAM00, 8, 2),
@@ -4716,7 +4807,7 @@ static struct samsung_div_clock cam0_div_clks[] __initdata = {
4716 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4807 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4717}; 4808};
4718 4809
4719static struct samsung_gate_clock cam0_gate_clks[] __initdata = { 4810static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4720 /* ENABLE_ACLK_CAM00 */ 4811 /* ENABLE_ACLK_CAM00 */
4721 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4812 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4722 6, 0, 0), 4813 6, 0, 0),
@@ -4923,7 +5014,7 @@ static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
4923 ENABLE_SCLK_CAM0, 0, 0, 0), 5014 ENABLE_SCLK_CAM0, 0, 0, 0),
4924}; 5015};
4925 5016
4926static struct samsung_cmu_info cam0_cmu_info __initdata = { 5017static const struct samsung_cmu_info cam0_cmu_info __initconst = {
4927 .mux_clks = cam0_mux_clks, 5018 .mux_clks = cam0_mux_clks,
4928 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5019 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
4929 .div_clks = cam0_div_clks, 5020 .div_clks = cam0_div_clks,
@@ -4970,7 +5061,7 @@ CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
4970#define ENABLE_IP_CAM11 0X0b04 5061#define ENABLE_IP_CAM11 0X0b04
4971#define ENABLE_IP_CAM12 0X0b08 5062#define ENABLE_IP_CAM12 0X0b08
4972 5063
4973static unsigned long cam1_clk_regs[] __initdata = { 5064static const unsigned long cam1_clk_regs[] __initconst = {
4974 MUX_SEL_CAM10, 5065 MUX_SEL_CAM10,
4975 MUX_SEL_CAM11, 5066 MUX_SEL_CAM11,
4976 MUX_SEL_CAM12, 5067 MUX_SEL_CAM12,
@@ -5016,12 +5107,12 @@ PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5016PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5107PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5017 "mout_aclk_cam1_400_user", }; 5108 "mout_aclk_cam1_400_user", };
5018 5109
5019static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = { 5110static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5020 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5111 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5021 0, 100000000), 5112 0, 100000000),
5022}; 5113};
5023 5114
5024static struct samsung_mux_clock cam1_mux_clks[] __initdata = { 5115static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5025 /* MUX_SEL_CAM10 */ 5116 /* MUX_SEL_CAM10 */
5026 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5117 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5027 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5118 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
@@ -5057,7 +5148,7 @@ static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
5057 MUX_SEL_CAM12, 0, 1), 5148 MUX_SEL_CAM12, 0, 1),
5058}; 5149};
5059 5150
5060static struct samsung_div_clock cam1_div_clks[] __initdata = { 5151static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5061 /* DIV_CAM10 */ 5152 /* DIV_CAM10 */
5062 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5153 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5063 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5154 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
@@ -5081,7 +5172,7 @@ static struct samsung_div_clock cam1_div_clks[] __initdata = {
5081 DIV_CAM11, 0, 3), 5172 DIV_CAM11, 0, 3),
5082}; 5173};
5083 5174
5084static struct samsung_gate_clock cam1_gate_clks[] __initdata = { 5175static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5085 /* ENABLE_ACLK_CAM10 */ 5176 /* ENABLE_ACLK_CAM10 */
5086 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5177 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5087 ENABLE_ACLK_CAM10, 4, 0, 0), 5178 ENABLE_ACLK_CAM10, 4, 0, 0),
@@ -5296,7 +5387,7 @@ static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
5296 ENABLE_SCLK_CAM1, 0, 0, 0), 5387 ENABLE_SCLK_CAM1, 0, 0, 0),
5297}; 5388};
5298 5389
5299static struct samsung_cmu_info cam1_cmu_info __initdata = { 5390static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5300 .mux_clks = cam1_mux_clks, 5391 .mux_clks = cam1_mux_clks,
5301 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5392 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5302 .div_clks = cam1_div_clks, 5393 .div_clks = cam1_div_clks,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 11:50:33 -0500