1 files changed, 91 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
new file mode 100644
index 000000000000..0b7bcd33a2df
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2016 Maxime Ripard. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _CCU_NM_H_
+#define _CCU_NM_H_
+#include <linux/clk-provider.h>
+#include "ccu_common.h"
+#include "ccu_div.h"
+#include "ccu_frac.h"
+#include "ccu_mult.h"
+/*
+ * struct ccu_nm - Definition of an N-M clock
+ *
+ * Clocks based on the formula parent * N / M
+ */
+struct ccu_nm {
+        u32                     enable;
+        u32                     lock;
+        struct _ccu_mult        n;
+        struct _ccu_div         m;
+        struct _ccu_frac        frac;
+        struct ccu_common       common;
+};
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
+                                         _nshift, _nwidth,              \
+                                         _mshift, _mwidth,              \
+                                         _frac_en, _frac_sel,           \
+                                         _frac_rate_0, _frac_rate_1,    \
+                                         _gate, _lock, _flags)          \
+        struct ccu_nm _struct = {                                       \
+                .enable         = _gate,                                \
+                .lock           = _lock,                                \
+                .n              = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
+                .m              = _SUNXI_CCU_DIV(_mshift, _mwidth),     \
+                .frac           = _SUNXI_CCU_FRAC(_frac_en, _frac_sel,  \
+                                                  _frac_rate_0,         \
+                                                  _frac_rate_1),        \
+                .common         = {                                     \
+                        .reg            = _reg,                         \
+                        .features       = CCU_FEATURE_FRACTIONAL,       \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                      _parent,          \
+                                                      &ccu_nm_ops,      \
+                                                      _flags),          \
+                },                                                      \
+        }
+#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,      \
+                                    _nshift, _nwidth,                   \
+                                    _mshift, _mwidth,                   \
+                                    _gate, _lock, _flags)               \
+        struct ccu_nm _struct = {                                       \
+                .enable         = _gate,                                \
+                .lock           = _lock,                                \
+                .n              = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
+                .m              = _SUNXI_CCU_DIV(_mshift, _mwidth),     \
+                .common         = {                                     \
+                        .reg            = _reg,                         \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                      _parent,          \
+                                                      &ccu_nm_ops,      \
+                                                      _flags),          \
+                },                                                      \
+        }
+static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw)
+{
+        struct ccu_common *common = hw_to_ccu_common(hw);
+        return container_of(common, struct ccu_nm, common);
+}
+extern const struct clk_ops ccu_nm_ops;
+#endif /* _CCU_NM_H_ */

diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h new file mode 100644 index 000000000000..0b7bcd33a2df --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -0,0 +1,91 @@
	1	/*
	2	* Copyright (c) 2016 Maxime Ripard. All rights reserved.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#ifndef _CCU_NM_H_
	15	#define _CCU_NM_H_
	16
	17	#include <linux/clk-provider.h>
	18
	19	#include "ccu_common.h"
	20	#include "ccu_div.h"
	21	#include "ccu_frac.h"
	22	#include "ccu_mult.h"
	23
	24	/*
	25	* struct ccu_nm - Definition of an N-M clock
	26	*
	27	* Clocks based on the formula parent * N / M
	28	*/
	29	struct ccu_nm {
	30	u32 enable;
	31	u32 lock;
	32
	33	struct _ccu_mult n;
	34	struct _ccu_div m;
	35	struct _ccu_frac frac;
	36
	37	struct ccu_common common;
	38	};
	39
	40	#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
	41	_nshift, _nwidth, \
	42	_mshift, _mwidth, \
	43	_frac_en, _frac_sel, \
	44	_frac_rate_0, _frac_rate_1, \
	45	_gate, _lock, _flags) \
	46	struct ccu_nm _struct = { \
	47	.enable = _gate, \
	48	.lock = _lock, \
	49	.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
	50	.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
	51	.frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
	52	_frac_rate_0, \
	53	_frac_rate_1), \
	54	.common = { \
	55	.reg = _reg, \
	56	.features = CCU_FEATURE_FRACTIONAL, \
	57	.hw.init = CLK_HW_INIT(_name, \
	58	_parent, \
	59	&ccu_nm_ops, \
	60	_flags), \
	61	}, \
	62	}
	63
	64	#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
	65	_nshift, _nwidth, \
	66	_mshift, _mwidth, \
	67	_gate, _lock, _flags) \
	68	struct ccu_nm _struct = { \
	69	.enable = _gate, \
	70	.lock = _lock, \
	71	.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
	72	.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
	73	.common = { \
	74	.reg = _reg, \
	75	.hw.init = CLK_HW_INIT(_name, \
	76	_parent, \
	77	&ccu_nm_ops, \
	78	_flags), \
	79	}, \
	80	}
	81
	82	static inline struct ccu_nm hw_to_ccu_nm(struct clk_hw hw)
	83	{
	84	struct ccu_common *common = hw_to_ccu_common(hw);
	85
	86	return container_of(common, struct ccu_nm, common);
	87	}
	88
	89	extern const struct clk_ops ccu_nm_ops;
	90
	91	#endif /* _CCU_NM_H_ */