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-rw-r--r--include/nvgpu/pmuif/gpmu_super_surf_if.h77
-rw-r--r--include/nvgpu/pmuif/gpmuif_acr.h159
-rw-r--r--include/nvgpu/pmuif/gpmuif_ap.h256
-rw-r--r--include/nvgpu/pmuif/gpmuif_cmn.h142
-rw-r--r--include/nvgpu/pmuif/gpmuif_perfmon.h241
-rw-r--r--include/nvgpu/pmuif/gpmuif_pg.h412
-rw-r--r--include/nvgpu/pmuif/gpmuif_pg_rppg.h110
-rw-r--r--include/nvgpu/pmuif/gpmuif_pmu.h193
-rw-r--r--include/nvgpu/pmuif/gpmuifbios.h50
-rw-r--r--include/nvgpu/pmuif/gpmuifboardobj.h234
-rw-r--r--include/nvgpu/pmuif/gpmuifclk.h573
-rw-r--r--include/nvgpu/pmuif/gpmuifperf.h154
-rw-r--r--include/nvgpu/pmuif/gpmuifperfvfe.h206
-rw-r--r--include/nvgpu/pmuif/gpmuifpmgr.h443
-rw-r--r--include/nvgpu/pmuif/gpmuifseq.h82
-rw-r--r--include/nvgpu/pmuif/gpmuiftherm.h102
-rw-r--r--include/nvgpu/pmuif/gpmuifthermsensor.h105
-rw-r--r--include/nvgpu/pmuif/gpmuifvolt.h402
-rw-r--r--include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h143
19 files changed, 4084 insertions, 0 deletions
diff --git a/include/nvgpu/pmuif/gpmu_super_surf_if.h b/include/nvgpu/pmuif/gpmu_super_surf_if.h
new file mode 100644
index 0000000..b0f9e10
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmu_super_surf_if.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
23#define NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
24
25struct nv_pmu_super_surface_hdr {
26 u32 memberMask;
27 u16 dmemBufferSizeMax;
28};
29
30NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr,
31 sizeof(struct nv_pmu_super_surface_hdr));
32
33/*
34 * Global Super Surface structure for combined INIT data required by PMU.
35 * NOTE: Any new substructures or entries must be aligned.
36 */
37struct nv_pmu_super_surface {
38 union nv_pmu_super_surface_hdr_aligned hdr;
39
40 struct {
41 struct nv_pmu_volt_volt_device_boardobj_grp_set volt_device_grp_set;
42 struct nv_pmu_volt_volt_policy_boardobj_grp_set volt_policy_grp_set;
43 struct nv_pmu_volt_volt_rail_boardobj_grp_set volt_rail_grp_set;
44
45 struct nv_pmu_volt_volt_policy_boardobj_grp_get_status volt_policy_grp_get_status;
46 struct nv_pmu_volt_volt_rail_boardobj_grp_get_status volt_rail_grp_get_status;
47 struct nv_pmu_volt_volt_device_boardobj_grp_get_status volt_device_grp_get_status;
48 } volt;
49 struct {
50 struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set;
51 struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set;
52 struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set;
53 u8 clk_rsvd2[0x200];
54 struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set;
55 struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set;
56 struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set;
57 struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status;
58 struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status;
59 struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status;
60 u8 clk_rsvd[0x4660];
61 } clk;
62 struct {
63 struct nv_pmu_perf_vfe_equ_boardobj_grp_set vfe_equ_grp_set;
64 struct nv_pmu_perf_vfe_var_boardobj_grp_set vfe_var_grp_set;
65
66 struct nv_pmu_perf_vfe_var_boardobj_grp_get_status vfe_var_grp_get_status;
67 u8 perf_rsvd[0x40790];
68 u8 perfcf_rsvd[0x1eb0];
69 } perf;
70 struct {
71 struct nv_pmu_therm_therm_channel_boardobj_grp_set therm_channel_grp_set;
72 struct nv_pmu_therm_therm_device_boardobj_grp_set therm_device_grp_set;
73 u8 therm_rsvd[0x1460];
74 } therm;
75};
76
77#endif /* NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H */
diff --git a/include/nvgpu/pmuif/gpmuif_acr.h b/include/nvgpu/pmuif/gpmuif_acr.h
new file mode 100644
index 0000000..c305589
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_acr.h
@@ -0,0 +1,159 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_ACR_H
23#define NVGPU_PMUIF_GPMUIF_ACR_H
24
25/* ACR Commands/Message structures */
26
27enum {
28 PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0,
29 PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
30 PMU_ACR_CMD_ID_RESERVED,
31 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
32};
33
34/*
35 * Initializes the WPR region details
36 */
37struct pmu_acr_cmd_init_wpr_details {
38 u8 cmd_type;
39 u32 regionid;
40 u32 wproffset;
41
42};
43
44/*
45 * falcon ID to bootstrap
46 */
47struct pmu_acr_cmd_bootstrap_falcon {
48 u8 cmd_type;
49 u32 flags;
50 u32 falconid;
51};
52
53/*
54 * falcon ID to bootstrap
55 */
56struct pmu_acr_cmd_bootstrap_multiple_falcons {
57 u8 cmd_type;
58 u32 flags;
59 u32 falconidmask;
60 u32 usevamask;
61 struct falc_u64 wprvirtualbase;
62};
63
64#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1
65#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
66
67
68struct pmu_acr_cmd {
69 union {
70 u8 cmd_type;
71 struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
72 struct pmu_acr_cmd_init_wpr_details init_wpr;
73 struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
74 };
75};
76
77/* acr messages */
78
79/*
80 * returns the WPR region init information
81 */
82#define PMU_ACR_MSG_ID_INIT_WPR_REGION 0
83
84/*
85 * Returns the Bootstrapped falcon ID to RM
86 */
87#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1
88
89/*
90 * Returns the WPR init status
91 */
92#define PMU_ACR_SUCCESS 0
93#define PMU_ACR_ERROR 1
94
95/*
96 * PMU notifies about bootstrap status of falcon
97 */
98struct pmu_acr_msg_bootstrap_falcon {
99 u8 msg_type;
100 union {
101 u32 errorcode;
102 u32 falconid;
103 };
104};
105
106struct pmu_acr_msg {
107 union {
108 u8 msg_type;
109 struct pmu_acr_msg_bootstrap_falcon acrmsg;
110 };
111};
112
113/* ACR RPC */
114#define NV_PMU_RPC_ID_ACR_INIT_WPR_REGION 0x00
115#define NV_PMU_RPC_ID_ACR_WRITE_CBC_BASE 0x01
116#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_FALCON 0x02
117#define NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS 0x03
118#define NV_PMU_RPC_ID_ACR__COUNT 0x04
119
120/*
121 * structure that holds data used
122 * to execute INIT_WPR_REGION RPC.
123 */
124struct nv_pmu_rpc_struct_acr_init_wpr_region {
125 /*[IN/OUT] Must be first field in RPC structure */
126 struct nv_pmu_rpc_header hdr;
127 /*[IN] ACR region ID of WPR region */
128 u32 wpr_regionId;
129 /* [IN] WPR offset from startAddress */
130 u32 wpr_offset;
131 u32 scratch[1];
132};
133
134/*
135 * structure that holds data used to
136 * execute BOOTSTRAP_GR_FALCONS RPC.
137 */
138struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons {
139 /*[IN/OUT] Must be first field in RPC structure */
140 struct nv_pmu_rpc_header hdr;
141 /* [IN] Mask of falcon IDs @ref LSF_FALCON_ID_<XYZ> */
142 u32 falcon_id_mask;
143 /*
144 * [IN] Boostrapping flags @ref
145 * PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_<XYZ>
146 */
147 u32 flags;
148 /* [IN] Indicate whether the particular falon uses VA */
149 u32 falcon_va_mask;
150 /*
151 * [IN] WPR Base Address in VA. The Inst Block containing
152 * this VA should be bound to both PMU and GR falcons
153 * during the falcon boot
154 */
155 struct falc_u64 wpr_base_virtual;
156 u32 scratch[1];
157};
158
159#endif /* NVGPU_PMUIF_GPMUIF_ACR_H */
diff --git a/include/nvgpu/pmuif/gpmuif_ap.h b/include/nvgpu/pmuif/gpmuif_ap.h
new file mode 100644
index 0000000..776fce8
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_ap.h
@@ -0,0 +1,256 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_AP_H
23#define NVGPU_PMUIF_GPMUIF_AP_H
24
25/* PMU Command/Message Interfaces for Adaptive Power */
26/* Macro to get Histogram index */
27#define PMU_AP_HISTOGRAM(idx) (idx)
28#define PMU_AP_HISTOGRAM_CONT (4)
29
30/* Total number of histogram bins */
31#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
32
33/* Mapping between Idle counters and histograms */
34#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
35#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
36#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
37#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
38
39
40/* Mapping between AP_CTRLs and Histograms */
41#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
42
43/* Mapping between AP_CTRLs and Idle counters */
44#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
45
46/* Adaptive Power Controls (AP_CTRL) */
47enum {
48 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
49 PMU_AP_CTRL_ID_MAX,
50};
51
52/* AP_CTRL Statistics */
53struct pmu_ap_ctrl_stat {
54 /*
55 * Represents whether AP is active or not
56 */
57 u8 b_active;
58
59 /* Idle filter represented by histogram bin index */
60 u8 idle_filter_x;
61 u8 rsvd[2];
62
63 /* Total predicted power saving cycles. */
64 s32 power_saving_h_cycles;
65
66 /* Counts how many times AP gave us -ve power benefits. */
67 u32 bad_decision_count;
68
69 /*
70 * Number of times ap structure needs to skip AP iterations
71 * KICK_CTRL from kernel updates this parameter.
72 */
73 u32 skip_count;
74 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
75};
76
77/* Parameters initialized by INITn APCTRL command */
78struct pmu_ap_ctrl_init_params {
79 /* Minimum idle filter value in Us */
80 u32 min_idle_filter_us;
81
82 /*
83 * Minimum Targeted Saving in Us. AP will update idle thresholds only
84 * if power saving achieved by updating idle thresholds is greater than
85 * Minimum targeted saving.
86 */
87 u32 min_target_saving_us;
88
89 /* Minimum targeted residency of power feature in Us */
90 u32 power_break_even_us;
91
92 /*
93 * Maximum number of allowed power feature cycles per sample.
94 *
95 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
96 * AKA pgPerSampleMax in original algorithm.
97 */
98 u32 cycles_per_sample_max;
99};
100
101/* AP Commands/Message structures */
102
103/*
104 * Structure for Generic AP Commands
105 */
106struct pmu_ap_cmd_common {
107 u8 cmd_type;
108 u16 cmd_id;
109};
110
111/*
112 * Structure for INIT AP command
113 */
114struct pmu_ap_cmd_init {
115 u8 cmd_type;
116 u16 cmd_id;
117 u8 rsvd;
118 u32 pg_sampling_period_us;
119};
120
121/*
122 * Structure for Enable/Disable ApCtrl Commands
123 */
124struct pmu_ap_cmd_enable_ctrl {
125 u8 cmd_type;
126 u16 cmd_id;
127
128 u8 ctrl_id;
129};
130
131struct pmu_ap_cmd_disable_ctrl {
132 u8 cmd_type;
133 u16 cmd_id;
134
135 u8 ctrl_id;
136};
137
138/*
139 * Structure for INIT command
140 */
141struct pmu_ap_cmd_init_ctrl {
142 u8 cmd_type;
143 u16 cmd_id;
144 u8 ctrl_id;
145 struct pmu_ap_ctrl_init_params params;
146};
147
148struct pmu_ap_cmd_init_and_enable_ctrl {
149 u8 cmd_type;
150 u16 cmd_id;
151 u8 ctrl_id;
152 struct pmu_ap_ctrl_init_params params;
153};
154
155/*
156 * Structure for KICK_CTRL command
157 */
158struct pmu_ap_cmd_kick_ctrl {
159 u8 cmd_type;
160 u16 cmd_id;
161 u8 ctrl_id;
162
163 u32 skip_count;
164};
165
166/*
167 * Structure for PARAM command
168 */
169struct pmu_ap_cmd_param {
170 u8 cmd_type;
171 u16 cmd_id;
172 u8 ctrl_id;
173
174 u32 data;
175};
176
177/*
178 * Defines for AP commands
179 */
180enum {
181 PMU_AP_CMD_ID_INIT = 0x0,
182 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
183 PMU_AP_CMD_ID_ENABLE_CTRL,
184 PMU_AP_CMD_ID_DISABLE_CTRL,
185 PMU_AP_CMD_ID_KICK_CTRL,
186};
187
188/*
189 * AP Command
190 */
191union pmu_ap_cmd {
192 u8 cmd_type;
193 struct pmu_ap_cmd_common cmn;
194 struct pmu_ap_cmd_init init;
195 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
196 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
197 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
198 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
199};
200
201/*
202 * Structure for generic AP Message
203 */
204struct pmu_ap_msg_common {
205 u8 msg_type;
206 u16 msg_id;
207};
208
209/*
210 * Structure for INIT_ACK Message
211 */
212struct pmu_ap_msg_init_ack {
213 u8 msg_type;
214 u16 msg_id;
215 u8 ctrl_id;
216 u32 stats_dmem_offset;
217};
218
219/*
220 * Defines for AP messages
221 */
222enum {
223 PMU_AP_MSG_ID_INIT_ACK = 0x0,
224};
225
226/*
227 * AP Message
228 */
229union pmu_ap_msg {
230 u8 msg_type;
231 struct pmu_ap_msg_common cmn;
232 struct pmu_ap_msg_init_ack init_ack;
233};
234
235/*
236 * Adaptive Power Controller
237 */
238struct ap_ctrl {
239 u32 stats_dmem_offset;
240 u32 disable_reason_mask;
241 struct pmu_ap_ctrl_stat stat_cache;
242 u8 b_ready;
243};
244
245/*
246 * Adaptive Power structure
247 *
248 * ap structure provides generic infrastructure to make any power feature
249 * adaptive.
250 */
251struct pmu_ap {
252 u32 supported_mask;
253 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
254};
255
256#endif /* NVGPU_PMUIF_GPMUIF_AP_H*/
diff --git a/include/nvgpu/pmuif/gpmuif_cmn.h b/include/nvgpu/pmuif/gpmuif_cmn.h
new file mode 100644
index 0000000..0989754
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_cmn.h
@@ -0,0 +1,142 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_CMN_H
23#define NVGPU_PMUIF_GPMUIF_CMN_H
24
25/*
26 * Defines the logical queue IDs that must be used when submitting
27 * commands to the PMU
28 */
29/* write by sw, read by pmu, protected by sw mutex lock */
30#define PMU_COMMAND_QUEUE_HPQ 0U
31/* write by sw, read by pmu, protected by sw mutex lock */
32#define PMU_COMMAND_QUEUE_LPQ 1U
33/* write by pmu, read by sw, accessed by interrupt handler, no lock */
34#define PMU_MESSAGE_QUEUE 4U
35#define PMU_QUEUE_COUNT 5U
36
37#define PMU_IS_COMMAND_QUEUE(id) \
38 ((id) < PMU_MESSAGE_QUEUE)
39
40#define PMU_IS_SW_COMMAND_QUEUE(id) \
41 (((id) == PMU_COMMAND_QUEUE_HPQ) || \
42 ((id) == PMU_COMMAND_QUEUE_LPQ))
43
44#define PMU_IS_MESSAGE_QUEUE(id) \
45 ((id) == PMU_MESSAGE_QUEUE)
46
47#define OFLAG_READ 0U
48#define OFLAG_WRITE 1U
49
50#define QUEUE_SET (true)
51#define QUEUE_GET (false)
52
53#define QUEUE_ALIGNMENT (4U)
54
55/* An enumeration containing all valid logical mutex identifiers */
56enum {
57 PMU_MUTEX_ID_RSVD1 = 0,
58 PMU_MUTEX_ID_GPUSER,
59 PMU_MUTEX_ID_QUEUE_BIOS,
60 PMU_MUTEX_ID_QUEUE_SMI,
61 PMU_MUTEX_ID_GPMUTEX,
62 PMU_MUTEX_ID_I2C,
63 PMU_MUTEX_ID_RMLOCK,
64 PMU_MUTEX_ID_MSGBOX,
65 PMU_MUTEX_ID_FIFO,
66 PMU_MUTEX_ID_PG,
67 PMU_MUTEX_ID_GR,
68 PMU_MUTEX_ID_CLK,
69 PMU_MUTEX_ID_RSVD6,
70 PMU_MUTEX_ID_RSVD7,
71 PMU_MUTEX_ID_RSVD8,
72 PMU_MUTEX_ID_RSVD9,
73 PMU_MUTEX_ID_INVALID
74};
75
76#define PMU_MUTEX_ID_IS_VALID(id) \
77 ((id) < PMU_MUTEX_ID_INVALID)
78
79#define PMU_INVALID_MUTEX_OWNER_ID (0)
80
81/*
82 * The PMU's frame-buffer interface block has several slots/indices
83 * which can be bound to support DMA to various surfaces in memory
84 */
85enum {
86 PMU_DMAIDX_UCODE = 0,
87 PMU_DMAIDX_VIRT = 1,
88 PMU_DMAIDX_PHYS_VID = 2,
89 PMU_DMAIDX_PHYS_SYS_COH = 3,
90 PMU_DMAIDX_PHYS_SYS_NCOH = 4,
91 PMU_DMAIDX_RSVD = 5,
92 PMU_DMAIDX_PELPG = 6,
93 PMU_DMAIDX_END = 7
94};
95
96/*
97 * Falcon PMU DMA's minimum size in bytes.
98 */
99#define PMU_DMA_MIN_READ_SIZE_BYTES 16
100#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4
101
102#define PMU_FB_COPY_RW_ALIGNMENT \
103 ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \
104 PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
105
106/*
107 * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
108 * data structures to issue DMA read/write operations.
109 */
110#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \
111union name##_aligned { \
112 struct name data; \
113 u8 pad[ALIGN_UP(sizeof(struct name), \
114 (PMU_FB_COPY_RW_ALIGNMENT))]; \
115}
116
117#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \
118union name##_aligned { \
119 union name data; \
120 u8 pad[ALIGN_UP(sizeof(union name), \
121 (PMU_FB_COPY_RW_ALIGNMENT))]; \
122}
123
124/* RPC (Remote Procedure Call) header structure */
125#define NV_PMU_RPC_FLAGS_TYPE_SYNC 0x00000000
126
127struct nv_pmu_rpc_header {
128 /* Identifies the unit servicing requested RPC*/
129 u8 unit_id;
130 /* Identifies the requested RPC (within the unit)*/
131 u8 function;
132 /* RPC call flags (@see PMU_RPC_FLAGS) */
133 u8 flags;
134 /* Falcon's status code to describe failures*/
135 u8 flcn_status;
136 /* RPC's total exec. time (measured on nvgpu driver side)*/
137 u32 exec_time_nv_ns;
138 /* RPC's actual exec. time (measured on PMU side)*/
139 u32 exec_time_pmu_ns;
140};
141
142#endif /* NVGPU_PMUIF_GPMUIF_CMN_H*/
diff --git a/include/nvgpu/pmuif/gpmuif_perfmon.h b/include/nvgpu/pmuif/gpmuif_perfmon.h
new file mode 100644
index 0000000..8324e36
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_perfmon.h
@@ -0,0 +1,241 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_PERFMON_H
23#define NVGPU_PMUIF_GPMUIF_PERFMON_H
24
25/*perfmon task defines*/
26
27#define PMU_DOMAIN_GROUP_PSTATE 0
28#define PMU_DOMAIN_GROUP_GPC2CLK 1
29#define PMU_DOMAIN_GROUP_NUM 2
30
31#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001)
32#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002)
33#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
34
35#define NV_PMU_PERFMON_MAX_COUNTERS 10U
36
37enum pmu_perfmon_cmd_start_fields {
38 COUNTER_ALLOC
39};
40
41enum {
42 PMU_PERFMON_CMD_ID_START = 0,
43 PMU_PERFMON_CMD_ID_STOP = 1,
44 PMU_PERFMON_CMD_ID_INIT = 2
45};
46
47struct pmu_perfmon_counter_v2 {
48 u8 index;
49 u8 flags;
50 u8 group_id;
51 u8 valid;
52 u16 upper_threshold; /* units of 0.01% */
53 u16 lower_threshold; /* units of 0.01% */
54 u32 scale;
55};
56
57struct pmu_perfmon_counter_v3 {
58 u8 index;
59 u8 group_id;
60 u16 flags;
61 u16 upper_threshold; /* units of 0.01% */
62 u16 lower_threshold; /* units of 0.01% */
63 u32 scale;
64};
65
66struct pmu_perfmon_cmd_start_v3 {
67 u8 cmd_type;
68 u8 group_id;
69 u8 state_id;
70 u8 flags;
71 struct pmu_allocation_v3 counter_alloc;
72};
73
74struct pmu_perfmon_cmd_start_v2 {
75 u8 cmd_type;
76 u8 group_id;
77 u8 state_id;
78 u8 flags;
79 struct pmu_allocation_v2 counter_alloc;
80};
81
82struct pmu_perfmon_cmd_start_v1 {
83 u8 cmd_type;
84 u8 group_id;
85 u8 state_id;
86 u8 flags;
87 struct pmu_allocation_v1 counter_alloc;
88};
89
90struct pmu_perfmon_cmd_stop {
91 u8 cmd_type;
92};
93
94struct pmu_perfmon_cmd_init_v3 {
95 u8 cmd_type;
96 u8 to_decrease_count;
97 u8 base_counter_id;
98 u32 sample_period_us;
99 struct pmu_allocation_v3 counter_alloc;
100 u8 num_counters;
101 u8 samples_in_moving_avg;
102 u16 sample_buffer;
103};
104
105struct pmu_perfmon_cmd_init_v2 {
106 u8 cmd_type;
107 u8 to_decrease_count;
108 u8 base_counter_id;
109 u32 sample_period_us;
110 struct pmu_allocation_v2 counter_alloc;
111 u8 num_counters;
112 u8 samples_in_moving_avg;
113 u16 sample_buffer;
114};
115
116struct pmu_perfmon_cmd_init_v1 {
117 u8 cmd_type;
118 u8 to_decrease_count;
119 u8 base_counter_id;
120 u32 sample_period_us;
121 struct pmu_allocation_v1 counter_alloc;
122 u8 num_counters;
123 u8 samples_in_moving_avg;
124 u16 sample_buffer;
125};
126
127struct pmu_perfmon_cmd {
128 union {
129 u8 cmd_type;
130 struct pmu_perfmon_cmd_start_v1 start_v1;
131 struct pmu_perfmon_cmd_start_v2 start_v2;
132 struct pmu_perfmon_cmd_start_v3 start_v3;
133 struct pmu_perfmon_cmd_stop stop;
134 struct pmu_perfmon_cmd_init_v1 init_v1;
135 struct pmu_perfmon_cmd_init_v2 init_v2;
136 struct pmu_perfmon_cmd_init_v3 init_v3;
137 };
138};
139
140struct pmu_zbc_cmd {
141 u8 cmd_type;
142 u8 pad;
143 u16 entry_mask;
144};
145
146/* PERFMON MSG */
147enum {
148 PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
149 PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
150 PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
151 PMU_PERFMON_MSG_ID_ACK = 3
152};
153
154struct pmu_perfmon_msg_generic {
155 u8 msg_type;
156 u8 state_id;
157 u8 group_id;
158 u8 data;
159};
160
161struct pmu_perfmon_msg {
162 union {
163 u8 msg_type;
164 struct pmu_perfmon_msg_generic gen;
165 };
166};
167
168/* PFERMON RPC interface*/
169/*
170 * RPC calls serviced by PERFMON unit.
171 */
172#define NV_PMU_RPC_ID_PERFMON_T18X_INIT 0x00
173#define NV_PMU_RPC_ID_PERFMON_T18X_DEINIT 0x01
174#define NV_PMU_RPC_ID_PERFMON_T18X_START 0x02
175#define NV_PMU_RPC_ID_PERFMON_T18X_STOP 0x03
176#define NV_PMU_RPC_ID_PERFMON_T18X_QUERY 0x04
177#define NV_PMU_RPC_ID_PERFMON_T18X__COUNT 0x05
178
179/*
180 * structure that holds data used to
181 * execute Perfmon INIT RPC.
182 * hdr - RPC header
183 * sample_periodus - Desired period in between samples.
184 * to_decrease_count - Consecutive samples before decrease event.
185 * base_counter_id - Index of the base counter.
186 * samples_in_moving_avg - Number of values in moving average.
187 * num_counters - Num of counters PMU should use.
188 * counter - Counters.
189 */
190struct nv_pmu_rpc_struct_perfmon_init {
191 struct nv_pmu_rpc_header hdr;
192 u32 sample_periodus;
193 u8 to_decrease_count;
194 u8 base_counter_id;
195 u8 samples_in_moving_avg;
196 u8 num_counters;
197 struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS];
198 u32 scratch[1];
199};
200
201/*
202 * structure that holds data used to
203 * execute Perfmon START RPC.
204 * hdr - RPC header
205 * group_id - NV group ID
206 * state_id - NV state ID
207 * flags - PMU_PERFON flags
208 * counters - Counters.
209 */
210struct nv_pmu_rpc_struct_perfmon_start {
211 struct nv_pmu_rpc_header hdr;
212 u8 group_id;
213 u8 state_id;
214 u8 flags;
215 struct pmu_perfmon_counter_v3 counter[NV_PMU_PERFMON_MAX_COUNTERS];
216 u32 scratch[1];
217};
218
219/*
220 * structure that holds data used to
221 * execute Perfmon STOP RPC.
222 * hdr - RPC header
223 */
224struct nv_pmu_rpc_struct_perfmon_stop {
225 struct nv_pmu_rpc_header hdr;
226 u32 scratch[1];
227};
228
229/*
230 * structure that holds data used to
231 * execute QUERY RPC.
232 * hdr - RPC header
233 * sample_buffer - Output buffer from pmu containing utilization samples.
234 */
235struct nv_pmu_rpc_struct_perfmon_query {
236 struct nv_pmu_rpc_header hdr;
237 u16 sample_buffer[NV_PMU_PERFMON_MAX_COUNTERS];
238 u32 scratch[1];
239};
240
241#endif /* NVGPU_PMUIF_GPMUIF_PERFMON_H */
diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h
new file mode 100644
index 0000000..69a7ea4
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_pg.h
@@ -0,0 +1,412 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_PG_H
23#define NVGPU_PMUIF_GPMUIF_PG_H
24
25#include "gpmuif_ap.h"
26#include "gpmuif_pg_rppg.h"
27
28/*PG defines*/
29
30/* Identifier for each PG */
31#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000U)
32#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004U)
33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U)
34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
35
36/* PG message */
37enum {
38 PMU_PG_ELPG_MSG_INIT_ACK,
39 PMU_PG_ELPG_MSG_DISALLOW_ACK,
40 PMU_PG_ELPG_MSG_ALLOW_ACK,
41 PMU_PG_ELPG_MSG_FREEZE_ACK,
42 PMU_PG_ELPG_MSG_FREEZE_ABORT,
43 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
44};
45
46struct pmu_pg_msg_elpg_msg {
47 u8 msg_type;
48 u8 engine_id;
49 u16 msg;
50};
51
52enum {
53 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
54};
55
56struct pmu_pg_msg_stat {
57 u8 msg_type;
58 u8 engine_id;
59 u16 sub_msg_id;
60 u32 data;
61};
62
63enum {
64 PMU_PG_MSG_ENG_BUF_LOADED,
65 PMU_PG_MSG_ENG_BUF_UNLOADED,
66 PMU_PG_MSG_ENG_BUF_FAILED,
67};
68
69struct pmu_pg_msg_eng_buf_stat {
70 u8 msg_type;
71 u8 engine_id;
72 u8 buf_idx;
73 u8 status;
74};
75
76struct pmu_pg_msg {
77 union {
78 u8 msg_type;
79 struct pmu_pg_msg_elpg_msg elpg_msg;
80 struct pmu_pg_msg_stat stat;
81 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
82 /* TBD: other pg messages */
83 union pmu_ap_msg ap_msg;
84 struct nv_pmu_rppg_msg rppg_msg;
85 };
86};
87
88/* PG commands */
89enum {
90 PMU_PG_ELPG_CMD_INIT,
91 PMU_PG_ELPG_CMD_DISALLOW,
92 PMU_PG_ELPG_CMD_ALLOW,
93 PMU_PG_ELPG_CMD_FREEZE,
94 PMU_PG_ELPG_CMD_UNFREEZE,
95};
96
97enum {
98 PMU_PG_CMD_ID_ELPG_CMD = 0,
99 PMU_PG_CMD_ID_ENG_BUF_LOAD,
100 PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
101 PMU_PG_CMD_ID_PG_STAT,
102 PMU_PG_CMD_ID_PG_LOG_INIT,
103 PMU_PG_CMD_ID_PG_LOG_FLUSH,
104 PMU_PG_CMD_ID_PG_PARAM,
105 PMU_PG_CMD_ID_ELPG_INIT,
106 PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
107 PMU_PG_CMD_ID_ELPG_ABORT_POLL,
108 PMU_PG_CMD_ID_ELPG_PWR_UP,
109 PMU_PG_CMD_ID_ELPG_DISALLOW,
110 PMU_PG_CMD_ID_ELPG_ALLOW,
111 PMU_PG_CMD_ID_AP,
112 RM_PMU_PG_CMD_ID_PSI,
113 RM_PMU_PG_CMD_ID_CG,
114 PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
115 PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
116 PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
117 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
118 PMU_PMU_PG_CMD_ID_RPPG = 0x24,
119};
120
121enum {
122 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
123};
124
125enum {
126 SLOWDOWN_FACTOR_FPDIV_BY1 = 0,
127 SLOWDOWN_FACTOR_FPDIV_BY1P5,
128 SLOWDOWN_FACTOR_FPDIV_BY2,
129 SLOWDOWN_FACTOR_FPDIV_BY2P5,
130 SLOWDOWN_FACTOR_FPDIV_BY3,
131 SLOWDOWN_FACTOR_FPDIV_BY3P5,
132 SLOWDOWN_FACTOR_FPDIV_BY4,
133 SLOWDOWN_FACTOR_FPDIV_BY4P5,
134 SLOWDOWN_FACTOR_FPDIV_BY5,
135 SLOWDOWN_FACTOR_FPDIV_BY5P5,
136 SLOWDOWN_FACTOR_FPDIV_BY6,
137 SLOWDOWN_FACTOR_FPDIV_BY6P5,
138 SLOWDOWN_FACTOR_FPDIV_BY7,
139 SLOWDOWN_FACTOR_FPDIV_BY7P5,
140 SLOWDOWN_FACTOR_FPDIV_BY8,
141 SLOWDOWN_FACTOR_FPDIV_BY8P5,
142 SLOWDOWN_FACTOR_FPDIV_BY9,
143 SLOWDOWN_FACTOR_FPDIV_BY9P5,
144 SLOWDOWN_FACTOR_FPDIV_BY10,
145 SLOWDOWN_FACTOR_FPDIV_BY10P5,
146 SLOWDOWN_FACTOR_FPDIV_BY11,
147 SLOWDOWN_FACTOR_FPDIV_BY11P5,
148 SLOWDOWN_FACTOR_FPDIV_BY12,
149 SLOWDOWN_FACTOR_FPDIV_BY12P5,
150 SLOWDOWN_FACTOR_FPDIV_BY13,
151 SLOWDOWN_FACTOR_FPDIV_BY13P5,
152 SLOWDOWN_FACTOR_FPDIV_BY14,
153 SLOWDOWN_FACTOR_FPDIV_BY14P5,
154 SLOWDOWN_FACTOR_FPDIV_BY15,
155 SLOWDOWN_FACTOR_FPDIV_BY15P5,
156 SLOWDOWN_FACTOR_FPDIV_BY16,
157 SLOWDOWN_FACTOR_FPDIV_BY16P5,
158 SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20,
159 SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22,
160 SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24,
161 SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26,
162 SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28,
163 SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a,
164 SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c,
165 SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e,
166 SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30,
167 SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32,
168 SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34,
169 SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36,
170 SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38,
171 SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a,
172 SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c,
173 SLOWDOWN_FACTOR_FPDIV_BYMAX,
174};
175
176#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0U
177#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01U
178#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04U
179#define PMU_PG_PARAM_CMD_POST_INIT 0x06U
180#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07U
181
182#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN BIT32(0)
183#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING BIT32(2)
184#define NVGPU_PMU_GR_FEATURE_MASK_RPPG BIT32(3)
185#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING BIT32(5)
186#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND BIT32(6)
187#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7)
188#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY BIT32(8)
189#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE BIT32(9)
190#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM BIT32(10)
191#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC BIT32(11)
192#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG BIT32(12)
193
194#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
195 ( \
196 NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\
197 NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\
198 NVGPU_PMU_GR_FEATURE_MASK_RPPG |\
199 NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\
200 NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\
201 NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\
202 NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\
203 NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\
204 NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\
205 NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\
206 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \
207 )
208
209#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING BIT32(0)
210#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR BIT32(1)
211#define NVGPU_PMU_MS_FEATURE_MASK_RPPG BIT32(8)
212#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING BIT32(5)
213
214#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
215 ( \
216 NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
217 NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
218 NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
219 NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
220 )
221
222
223struct pmu_pg_cmd_elpg_cmd {
224 u8 cmd_type;
225 u8 engine_id;
226 u16 cmd;
227};
228
229struct pmu_pg_cmd_eng_buf_load_v0 {
230 u8 cmd_type;
231 u8 engine_id;
232 u8 buf_idx;
233 u8 pad;
234 u16 buf_size;
235 u32 dma_base;
236 u8 dma_offset;
237 u8 dma_idx;
238};
239
240struct pmu_pg_cmd_eng_buf_load_v1 {
241 u8 cmd_type;
242 u8 engine_id;
243 u8 buf_idx;
244 u8 pad;
245 struct flcn_mem_desc {
246 struct falc_u64 dma_addr;
247 u16 dma_size;
248 u8 dma_idx;
249 } dma_desc;
250};
251
252struct pmu_pg_cmd_eng_buf_load_v2 {
253 u8 cmd_type;
254 u8 engine_id;
255 u8 buf_idx;
256 u8 pad;
257 struct flcn_mem_desc_v0 dma_desc;
258};
259
260struct pmu_pg_cmd_gr_init_param {
261 u8 cmd_type;
262 u16 sub_cmd_id;
263 u8 featuremask;
264};
265
266struct pmu_pg_cmd_gr_init_param_v2 {
267 u8 cmd_type;
268 u16 sub_cmd_id;
269 u8 featuremask;
270 u8 ldiv_slowdown_factor;
271};
272
273struct pmu_pg_cmd_gr_init_param_v1 {
274 u8 cmd_type;
275 u16 sub_cmd_id;
276 u32 featuremask;
277};
278
279struct pmu_pg_cmd_sub_feature_mask_update {
280 u8 cmd_type;
281 u16 sub_cmd_id;
282 u8 ctrl_id;
283 u32 enabled_mask;
284};
285
286struct pmu_pg_cmd_ms_init_param {
287 u8 cmd_type;
288 u16 cmd_id;
289 u8 psi;
290 u8 idle_flipped_test_enabled;
291 u16 psiSettleTimeUs;
292 u8 rsvd[2];
293 u32 support_mask;
294 u32 abort_timeout_us;
295};
296
297struct pmu_pg_cmd_mclk_change {
298 u8 cmd_type;
299 u16 cmd_id;
300 u8 rsvd;
301 u32 data;
302};
303
304#define PG_VOLT_RAIL_IDX_MAX 2
305
306struct pmu_pg_volt_rail {
307 u8 volt_rail_idx;
308 u8 sleep_volt_dev_idx;
309 u8 sleep_vfe_idx;
310 u32 sleep_voltage_uv;
311 u32 therm_vid0_cache;
312 u32 therm_vid1_cache;
313};
314
315struct pmu_pg_cmd_post_init_param {
316 u8 cmd_type;
317 u16 cmd_id;
318 struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
319};
320
321struct pmu_pg_cmd_stat {
322 u8 cmd_type;
323 u8 engine_id;
324 u16 sub_cmd_id;
325 u32 data;
326};
327
328struct pmu_pg_cmd {
329 union {
330 u8 cmd_type;
331 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
332 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
333 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
334 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
335 struct pmu_pg_cmd_stat stat;
336 struct pmu_pg_cmd_gr_init_param gr_init_param;
337 struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1;
338 struct pmu_pg_cmd_gr_init_param_v2 gr_init_param_v2;
339 struct pmu_pg_cmd_ms_init_param ms_init_param;
340 struct pmu_pg_cmd_mclk_change mclk_change;
341 struct pmu_pg_cmd_post_init_param post_init;
342 /* TBD: other pg commands */
343 union pmu_ap_cmd ap_cmd;
344 struct nv_pmu_rppg_cmd rppg_cmd;
345 struct pmu_pg_cmd_sub_feature_mask_update sf_mask_update;
346 };
347};
348
349/* Statistics structure for PG features */
350struct pmu_pg_stats_v2 {
351 u32 entry_count;
352 u32 exit_count;
353 u32 abort_count;
354 u32 detection_count;
355 u32 prevention_activate_count;
356 u32 prevention_deactivate_count;
357 u32 powered_up_time_us;
358 u32 entry_latency_us;
359 u32 exit_latency_us;
360 u32 resident_time_us;
361 u32 entry_latency_avg_us;
362 u32 exit_latency_avg_us;
363 u32 entry_latency_max_us;
364 u32 exit_latency_max_us;
365 u32 total_sleep_time_us;
366 u32 total_non_sleep_time_us;
367};
368
369struct pmu_pg_stats_v1 {
370 /* Number of time PMU successfully engaged sleep state */
371 u32 entry_count;
372 /* Number of time PMU exit sleep state */
373 u32 exit_count;
374 /* Number of time PMU aborted in entry sequence */
375 u32 abort_count;
376 /*
377 * Time for which GPU was neither in Sleep state not
378 * executing sleep sequence.
379 */
380 u32 poweredup_timeus;
381 /* Entry and exit latency of current sleep cycle */
382 u32 entry_latency_us;
383 u32 exitlatencyus;
384 /* Resident time for current sleep cycle. */
385 u32 resident_timeus;
386 /* Rolling average entry and exit latencies */
387 u32 entrylatency_avgus;
388 u32 exitlatency_avgus;
389 /* Max entry and exit latencies */
390 u32 entrylatency_maxus;
391 u32 exitlatency_maxus;
392 /* Total time spent in sleep and non-sleep state */
393 u32 total_sleep_timeus;
394 u32 total_nonsleep_timeus;
395};
396
397struct pmu_pg_stats {
398 u64 pg_entry_start_timestamp;
399 u64 pg_ingating_start_timestamp;
400 u64 pg_exit_start_timestamp;
401 u64 pg_ungating_start_timestamp;
402 u32 pg_avg_entry_time_us;
403 u32 pg_ingating_cnt;
404 u32 pg_ingating_time_us;
405 u32 pg_avg_exit_time_us;
406 u32 pg_ungating_count;
407 u32 pg_ungating_time_us;
408 u32 pg_gating_cnt;
409 u32 pg_gating_deny_cnt;
410};
411
412#endif /* NVGPU_PMUIF_GPMUIF_PG_H*/
diff --git a/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/include/nvgpu/pmuif/gpmuif_pg_rppg.h
new file mode 100644
index 0000000..05445f6
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_pg_rppg.h
@@ -0,0 +1,110 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_PG_RPPG_H
23#define NVGPU_PMUIF_GPMUIF_PG_RPPG_H
24
25#define NV_PMU_RPPG_CTRL_ID_GR (0x0000)
26#define NV_PMU_RPPG_CTRL_ID_MS (0x0001)
27#define NV_PMU_RPPG_CTRL_ID_DI (0x0002)
28#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003)
29
30#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\
31 BIT(NV_PMU_RPPG_CTRL_ID_MS) |\
32 BIT(NV_PMU_RPPG_CTRL_ID_DI))
33
34#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0
35
36enum {
37 NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0,
38 NV_PMU_RPPG_DOMAIN_ID_NON_GFX,
39};
40
41struct nv_pmu_rppg_ctrl_stats {
42 u32 entry_count;
43 u32 exit_count;
44};
45
46struct nv_pmu_rppg_cmd_common {
47 u8 cmd_type;
48 u8 cmd_id;
49};
50
51struct nv_pmu_rppg_cmd_init {
52 u8 cmd_type;
53 u8 cmd_id;
54};
55
56struct nv_pmu_rppg_cmd_init_ctrl {
57 u8 cmd_type;
58 u8 cmd_id;
59 u8 ctrl_id;
60 u8 domain_id;
61};
62
63struct nv_pmu_rppg_cmd_stats_reset {
64 u8 cmd_type;
65 u8 cmd_id;
66 u8 ctrl_id;
67};
68
69struct nv_pmu_rppg_cmd {
70 union {
71 u8 cmd_type;
72 struct nv_pmu_rppg_cmd_common cmn;
73 struct nv_pmu_rppg_cmd_init init;
74 struct nv_pmu_rppg_cmd_init_ctrl init_ctrl;
75 struct nv_pmu_rppg_cmd_stats_reset stats_reset;
76 };
77};
78
79enum {
80 NV_PMU_RPPG_CMD_ID_INIT = 0x0,
81 NV_PMU_RPPG_CMD_ID_INIT_CTRL,
82 NV_PMU_RPPG_CMD_ID_STATS_RESET,
83};
84
85
86struct nv_pmu_rppg_msg_common {
87 u8 msg_type;
88 u8 msg_id;
89};
90
91struct nv_pmu_rppg_msg_init_ctrl_ack {
92 u8 msg_type;
93 u8 msg_id;
94 u8 ctrl_id;
95 u32 stats_dmem_offset;
96};
97
98struct nv_pmu_rppg_msg {
99 union {
100 u8 msg_type;
101 struct nv_pmu_rppg_msg_common cmn;
102 struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack;
103 };
104};
105
106enum {
107 NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0,
108};
109
110#endif /* NVGPU_PMUIF_GPMUIF_PG_RPPG_H */
diff --git a/include/nvgpu/pmuif/gpmuif_pmu.h b/include/nvgpu/pmuif/gpmuif_pmu.h
new file mode 100644
index 0000000..0528bd6
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_pmu.h
@@ -0,0 +1,193 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_PMU_H
23#define NVGPU_PMUIF_GPMUIF_PMU_H
24
25#include <nvgpu/flcnif_cmn.h>
26#include "gpmuif_cmn.h"
27
28/* Make sure size of this structure is a multiple of 4 bytes */
29struct pmu_cmdline_args_v3 {
30 u32 reserved;
31 u32 cpu_freq_hz;
32 u32 falc_trace_size;
33 u32 falc_trace_dma_base;
34 u32 falc_trace_dma_idx;
35 u8 secure_mode;
36 u8 raise_priv_sec;
37 struct pmu_mem_v1 gc6_ctx;
38};
39
40struct pmu_cmdline_args_v4 {
41 u32 reserved;
42 u32 cpu_freq_hz;
43 u32 falc_trace_size;
44 struct falc_dma_addr dma_addr;
45 u32 falc_trace_dma_idx;
46 u8 secure_mode;
47 u8 raise_priv_sec;
48 struct pmu_mem_desc_v0 gc6_ctx;
49 u8 pad;
50};
51
52struct pmu_cmdline_args_v5 {
53 u32 cpu_freq_hz;
54 struct flcn_mem_desc_v0 trace_buf;
55 u8 secure_mode;
56 u8 raise_priv_sec;
57 struct flcn_mem_desc_v0 gc6_ctx;
58 struct flcn_mem_desc_v0 init_data_dma_info;
59 u32 dummy;
60};
61
62struct pmu_cmdline_args_v6 {
63 u32 cpu_freq_hz;
64 struct flcn_mem_desc_v0 trace_buf;
65 u8 secure_mode;
66 u8 raise_priv_sec;
67 struct flcn_mem_desc_v0 gc6_ctx;
68 struct flcn_mem_desc_v0 gc6_bsod_ctx;
69 struct flcn_mem_desc_v0 super_surface;
70 u32 flags;
71};
72
73/* GPU ID */
74#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2
75#define PMU_SHA1_GID_SIGNATURE_SIZE 4
76
77#define PMU_SHA1_GID_SIZE 16
78
79struct pmu_sha1_gid {
80 bool valid;
81 u8 gid[PMU_SHA1_GID_SIZE];
82};
83
84struct pmu_sha1_gid_data {
85 u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE];
86 u8 gid[PMU_SHA1_GID_SIZE];
87};
88
89/* PMU INIT MSG */
90enum {
91 PMU_INIT_MSG_TYPE_PMU_INIT = 0,
92};
93
94struct pmu_init_msg_pmu_v1 {
95 u8 msg_type;
96 u8 pad;
97 u16 os_debug_entry_point;
98
99 struct {
100 u16 size;
101 u16 offset;
102 u8 index;
103 u8 pad;
104 } queue_info[PMU_QUEUE_COUNT];
105
106 u16 sw_managed_area_offset;
107 u16 sw_managed_area_size;
108};
109
110#define PMU_QUEUE_COUNT_FOR_V5 4
111#define PMU_QUEUE_COUNT_FOR_V4 5
112#define PMU_QUEUE_COUNT_FOR_V3 3
113#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
114#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
115#define PMU_QUEUE_MSG_IDX_FOR_V3 2
116#define PMU_QUEUE_MSG_IDX_FOR_V5 3
117struct pmu_init_msg_pmu_v3 {
118 u8 msg_type;
119 u8 queue_index[PMU_QUEUE_COUNT_FOR_V3];
120 u16 queue_size[PMU_QUEUE_COUNT_FOR_V3];
121 u16 queue_offset;
122
123 u16 sw_managed_area_offset;
124 u16 sw_managed_area_size;
125
126 u16 os_debug_entry_point;
127
128 u8 dummy[18];
129};
130
131struct pmu_init_msg_pmu_v4 {
132 u8 msg_type;
133 u8 queue_index[PMU_QUEUE_COUNT_FOR_V4];
134 u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
135 u16 queue_offset;
136
137 u16 sw_managed_area_offset;
138 u16 sw_managed_area_size;
139
140 u16 os_debug_entry_point;
141
142 u8 dummy[18];
143};
144
145struct pmu_init_msg_pmu_v5 {
146 u8 msg_type;
147 u8 flcn_status;
148 u8 queue_index[PMU_QUEUE_COUNT_FOR_V5];
149 u16 queue_size[PMU_QUEUE_COUNT_FOR_V5];
150 u16 queue_offset;
151
152 u16 sw_managed_area_offset;
153 u16 sw_managed_area_size;
154
155 u16 os_debug_entry_point;
156
157 u8 dummy[18];
158 u8 pad;
159};
160
161union pmu_init_msg_pmu {
162 struct pmu_init_msg_pmu_v1 v1;
163 struct pmu_init_msg_pmu_v3 v3;
164 struct pmu_init_msg_pmu_v4 v4;
165 struct pmu_init_msg_pmu_v5 v5;
166};
167
168struct pmu_init_msg {
169 union {
170 u8 msg_type;
171 struct pmu_init_msg_pmu_v1 pmu_init_v1;
172 struct pmu_init_msg_pmu_v3 pmu_init_v3;
173 struct pmu_init_msg_pmu_v4 pmu_init_v4;
174 struct pmu_init_msg_pmu_v5 pmu_init_v5;
175 };
176};
177
178/* robust channel (RC) messages */
179enum {
180 PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
181};
182
183struct pmu_rc_msg_unhandled_cmd {
184 u8 msg_type;
185 u8 unit_id;
186};
187
188struct pmu_rc_msg {
189 u8 msg_type;
190 struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
191};
192
193#endif /* NVGPU_PMUIF_GPMUIF_PMU_H*/
diff --git a/include/nvgpu/pmuif/gpmuifbios.h b/include/nvgpu/pmuif/gpmuifbios.h
new file mode 100644
index 0000000..e89fbc3
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifbios.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIFBIOS_H
23#define NVGPU_PMUIF_GPMUIFBIOS_H
24
25struct nv_pmu_bios_vfield_register_segment_super {
26 u8 type;
27 u8 low_bit;
28 u8 high_bit;
29};
30
31struct nv_pmu_bios_vfield_register_segment_reg {
32 struct nv_pmu_bios_vfield_register_segment_super super;
33 u32 addr;
34};
35
36struct nv_pmu_bios_vfield_register_segment_index_reg {
37 struct nv_pmu_bios_vfield_register_segment_super super;
38 u32 addr;
39 u32 reg_index;
40 u32 index;
41};
42
43union nv_pmu_bios_vfield_register_segment {
44 struct nv_pmu_bios_vfield_register_segment_super super;
45 struct nv_pmu_bios_vfield_register_segment_reg reg;
46 struct nv_pmu_bios_vfield_register_segment_index_reg index_reg;
47};
48
49
50#endif /* NVGPU_PMUIF_GPMUIFBIOS_H*/
diff --git a/include/nvgpu/pmuif/gpmuifboardobj.h b/include/nvgpu/pmuif/gpmuifboardobj.h
new file mode 100644
index 0000000..47226aa
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifboardobj.h
@@ -0,0 +1,234 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#ifndef NVGPU_PMUIF_GPMUIFBOARDOBJ_H
23#define NVGPU_PMUIF_GPMUIFBOARDOBJ_H
24
25#include <nvgpu/flcnif_cmn.h>
26#include "ctrl/ctrlboardobj.h"
27
28/* board object group command id's. */
29#define NV_PMU_BOARDOBJGRP_CMD_SET 0x00U
30#define NV_PMU_BOARDOBJGRP_CMD_GET_STATUS 0x01U
31
32#define NV_PMU_RPC_ID_CLK_BOARD_OBJ_GRP_CMD 0x00U
33#define NV_PMU_RPC_ID_FAN_BOARD_OBJ_GRP_CMD 0x00U
34#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U
35#define NV_PMU_RPC_ID_PERF_CF_BOARD_OBJ_GRP_CMD 0x00U
36#define NV_PMU_RPC_ID_PMGR_BOARD_OBJ_GRP_CMD 0x00U
37#define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00U
38#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U
39
40/*
41 * Base structure describing a BOARDOBJ for communication between Kernel and
42 * PMU.
43 */
44struct nv_pmu_boardobj {
45 u8 type;
46 u8 grp_idx;
47};
48
49/*
50 * Base structure describing a BOARDOBJ for Query interface between Kernel and
51 * PMU.
52 */
53struct nv_pmu_boardobj_query {
54 u8 type;
55 u8 grp_idx;
56};
57
58/*
59 * Virtual base structure describing a BOARDOBJGRP interface between Kernel and
60 * PMU.
61 */
62struct nv_pmu_boardobjgrp_super {
63 u8 type;
64 u8 class_id;
65 u8 obj_slots;
66 u8 flags;
67};
68
69struct nv_pmu_boardobjgrp {
70 struct nv_pmu_boardobjgrp_super super;
71 u32 obj_mask;
72};
73
74struct nv_pmu_boardobjgrp_e32 {
75 struct nv_pmu_boardobjgrp_super super;
76 struct ctrl_boardobjgrp_mask_e32 obj_mask;
77};
78
79struct nv_pmu_boardobjgrp_e255 {
80 struct nv_pmu_boardobjgrp_super super;
81 struct ctrl_boardobjgrp_mask_e255 obj_mask;
82};
83
84struct nv_pmu_boardobj_cmd_grp_payload {
85 struct pmu_allocation_v3 dmem_buf;
86 struct flcn_mem_desc_v0 fb;
87 u8 hdr_size;
88 u8 entry_size;
89};
90
91struct nv_pmu_boardobj_cmd_grp {
92 u8 cmd_type;
93 u8 pad[2];
94 u8 class_id;
95 struct nv_pmu_boardobj_cmd_grp_payload grp;
96};
97
98#define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \
99 (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp))
100
101struct nv_pmu_boardobj_cmd {
102 union {
103 u8 cmd_type;
104 struct nv_pmu_boardobj_cmd_grp grp;
105 struct nv_pmu_boardobj_cmd_grp grp_set;
106 struct nv_pmu_boardobj_cmd_grp grp_get_status;
107 };
108};
109
110struct nv_pmu_boardobj_msg_grp {
111 u8 msg_type;
112 bool b_success;
113 flcn_status flcn_status;
114 u8 class_id;
115};
116
117struct nv_pmu_boardobj_msg {
118 union {
119 u8 msg_type;
120 struct nv_pmu_boardobj_msg_grp grp;
121 struct nv_pmu_boardobj_msg_grp grp_set;
122 struct nv_pmu_boardobj_msg_grp grp_get_status;
123 };
124};
125
126/*
127* Macro generating structures describing classes which implement
128* NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface.
129*
130* @para _eng Name of implementing engine in which this structure is
131* found.
132* @param _class Class ID of Objects within Board Object Group.
133* @param _slots Max number of elements this group can contain.
134*/
135#define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \
136 NV_PMU_MAKE_ALIGNED_STRUCT( \
137 nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \
138 NV_PMU_MAKE_ALIGNED_UNION( \
139 nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \
140 struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \
141 union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \
142 union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\
143 }
144
145/*
146* Macro generating structures describing classes which implement
147* NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface.
148*
149* @para _eng Name of implementing engine in which this structure is
150* found.
151* @param _class Class ID of Objects within Board Object Group.
152*/
153#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \
154 NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \
155 CTRL_BOARDOBJGRP_E32_MAX_OBJECTS)
156
157/*
158* Macro generating structures describing classes which implement
159* NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface.
160*
161* @para _eng Name of implementing engine in which this structure is
162* found.
163* @param _class Class ID of Objects within Board Object Group.
164*/
165#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \
166 NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \
167 CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
168
169/*
170* Macro generating structures for querying dynamic state for classes which
171* implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS
172* interface.
173*
174* @para _eng Name of implementing engine in which this structure is
175* found.
176* @param _class Class ID of Objects within Board Object Group.
177* @param _slots Max number of elements this group can contain.
178*/
179#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \
180 NV_PMU_MAKE_ALIGNED_STRUCT( \
181 nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \
182 NV_PMU_MAKE_ALIGNED_UNION( \
183 nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \
184 struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \
185 union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \
186 hdr; \
187 union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \
188 objects[(_slots)]; \
189 }
190
191/*
192* Macro generating structures for querying dynamic state for classes which
193* implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS
194* interface.
195*
196* @para _eng Name of implementing engine in which this structure is
197* found.
198* @param _class Class ID of Objects within Board Object Group.
199*/
200#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \
201 NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \
202 CTRL_BOARDOBJGRP_E32_MAX_OBJECTS)
203
204/*
205* Macro generating structures for querying dynamic state for classes which
206* implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS
207* interface.
208*
209* @para _eng Name of implementing engine in which this structure is
210* found.
211* @param _class Class ID of Objects within Board Object Group.
212*/
213#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \
214 NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \
215 CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
216
217/* RPC */
218
219/*
220 * structure that holds data used to
221 * execute BOARD_OBJ_GRP_CMD RPC.
222 */
223struct nv_pmu_rpc_struct_board_obj_grp_cmd
224{
225 /* [IN/OUT] Must be first field in RPC structure */
226 struct nv_pmu_rpc_header hdr;
227 /* [IN] BOARDOBJGRP class IDs. */
228 u8 class_id;
229 /* [IN] Requested command ID (@ref NV_PMU_BOARDOBJGRP_CMD_***)*/
230 u8 command_id;
231 u32 scratch[1];
232};
233
234#endif /* NVGPU_PMUIF_GPMUIFBOARDOBJ_H */
diff --git a/include/nvgpu/pmuif/gpmuifclk.h b/include/nvgpu/pmuif/gpmuifclk.h
new file mode 100644
index 0000000..70a913b
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifclk.h
@@ -0,0 +1,573 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_PMUIF_GPMUIFCLK_H
24#define NVGPU_PMUIF_GPMUIFCLK_H
25
26#include "ctrl/ctrlboardobj.h"
27#include "ctrl/ctrlvolt.h"
28#include "ctrl/ctrlperf.h"
29#include "ctrl/ctrlclk.h"
30#include "gpmuifboardobj.h"
31#include "gpmuifvolt.h"
32#include <nvgpu/flcnif_cmn.h>
33
34
35/*
36 * Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
37 *
38 * mclk is same for both
39 * gpc2clk is 17 for Pascal and 13 for Volta, making it 17
40 * as volta uses gpcclk
41 * sys2clk is 20 in Pascal and 15 in Volta.
42 * Changing for Pascal would break nvdclk of Volta
43 * xbar2clk is 19 in Pascal and 14 in Volta
44 * Changing for Pascal would break pwrclk of Volta
45 */
46enum nv_pmu_clk_clkwhich {
47 clkwhich_gpcclk = 1,
48 clkwhich_xbarclk = 2,
49 clkwhich_sysclk = 3,
50 clkwhich_hubclk = 4,
51 clkwhich_mclk = 5,
52 clkwhich_hostclk = 6,
53 clkwhich_dispclk = 7,
54 clkwhich_xclk = 12,
55 clkwhich_gpc2clk = 17,
56 clkwhich_xbar2clk = 14,
57 clkwhich_sys2clk = 15,
58 clkwhich_hub2clk = 16,
59 clkwhich_pwrclk = 19,
60 clkwhich_nvdclk = 20,
61 clkwhich_pciegenclk = 26,
62};
63
64/*
65 * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId"
66 * argument for communications between Kernel and PMU via the various generic
67 * BOARDOBJGRP interfaces.
68 */
69#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00
70#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01
71#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02
72#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03
73#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04
74#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05
75
76/*!
77* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the
78* CLK_DOMAIN feature.
79*/
80struct nv_pmu_clk_clk_domain_boardobjgrp_set_header {
81 struct nv_pmu_boardobjgrp_e32 super;
82 u32 vbios_domains;
83 struct ctrl_boardobjgrp_mask_e32 prog_domains_mask;
84 struct ctrl_boardobjgrp_mask_e32 master_domains_mask;
85 u16 cntr_sampling_periodms;
86 u8 version;
87 bool b_override_o_v_o_c;
88 bool b_debug_mode;
89 bool b_enforce_vf_monotonicity;
90 bool b_enforce_vf_smoothening;
91 u8 volt_rails_max;
92 struct ctrl_clk_clk_delta deltas;
93};
94
95struct nv_pmu_clk_clk_domain_boardobj_set {
96 struct nv_pmu_boardobj super;
97 enum nv_pmu_clk_clkwhich domain;
98 u32 api_domain;
99 u8 perf_domain_grp_idx;
100};
101
102struct nv_pmu_clk_clk_domain_3x_boardobj_set {
103 struct nv_pmu_clk_clk_domain_boardobj_set super;
104 bool b_noise_aware_capable;
105};
106
107struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set {
108 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
109 u16 freq_mhz;
110};
111
112struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set {
113 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
114 u8 clk_prog_idx_first;
115 u8 clk_prog_idx_last;
116 bool b_force_noise_unaware_ordering;
117 struct ctrl_clk_freq_delta factory_delta;
118 short freq_delta_min_mhz;
119 short freq_delta_max_mhz;
120 struct ctrl_clk_clk_delta deltas;
121};
122
123struct nv_pmu_clk_clk_domain_30_prog_boardobj_set {
124 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
125 u8 noise_unaware_ordering_index;
126 u8 noise_aware_ordering_index;
127};
128
129struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
130 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
131 u32 slave_idxs_mask;
132};
133
134struct nv_pmu_clk_clk_domain_30_master_boardobj_set {
135 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
136 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
137};
138
139struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
140 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
141 u8 master_idx;
142};
143
144struct nv_pmu_clk_clk_domain_30_slave_boardobj_set {
145 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
146 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
147};
148
149struct nv_pmu_clk_clk_domain_35_prog_boardobj_set {
150 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
151 u8 pre_volt_ordering_index;
152 u8 post_volt_ordering_index;
153 u8 clk_pos;
154 u8 clk_vf_curve_count;
155};
156
157struct nv_pmu_clk_clk_domain_35_master_boardobj_set {
158 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
159 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
160 u32 master_slave_domains_grp_mask;
161};
162
163
164struct nv_pmu_clk_clk_domain_35_slave_boardobj_set {
165 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
166 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
167};
168
169union nv_pmu_clk_clk_domain_boardobj_set_union {
170 struct nv_pmu_boardobj board_obj;
171 struct nv_pmu_clk_clk_domain_boardobj_set super;
172 struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x;
173 struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed;
174 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
175 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set v30_prog;
176 struct nv_pmu_clk_clk_domain_30_master_boardobj_set v30_master;
177 struct nv_pmu_clk_clk_domain_30_slave_boardobj_set v30_slave;
178 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog;
179 struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master;
180 struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave;
181};
182
183NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
184
185struct nv_pmu_clk_clk_prog_boardobjgrp_set_header {
186 struct nv_pmu_boardobjgrp_e255 super;
187 u8 slave_entry_count;
188 u8 vf_entry_count;
189};
190
191struct nv_pmu_clk_clk_prog_boardobj_set {
192 struct nv_pmu_boardobj super;
193};
194
195struct nv_pmu_clk_clk_prog_1x_boardobj_set {
196 struct nv_pmu_clk_clk_prog_boardobj_set super;
197 u8 source;
198 u16 freq_max_mhz;
199 union ctrl_clk_clk_prog_1x_source_data source_data;
200};
201
202struct nv_pmu_clk_clk_prog_1x_master_boardobj_set {
203 struct nv_pmu_clk_clk_prog_1x_boardobj_set super;
204 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
205 bool b_o_c_o_v_enabled;
206 struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[
207 CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES];
208 struct ctrl_clk_clk_delta deltas;
209 union ctrl_clk_clk_prog_1x_master_source_data source_data;
210};
211
212struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set {
213 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
214 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
215 struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[
216 CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
217};
218
219struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set {
220 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
221 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
222 struct ctrl_clk_clk_prog_1x_master_table_slave_entry
223 slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
224};
225
226union nv_pmu_clk_clk_prog_boardobj_set_union {
227 struct nv_pmu_boardobj board_obj;
228 struct nv_pmu_clk_clk_prog_boardobj_set super;
229 struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x;
230 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master;
231 struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio;
232 struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table;
233};
234
235NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog);
236
237struct nv_pmu_clk_lut_device_desc {
238 u8 vselect_mode;
239 u16 hysteresis_threshold;
240};
241
242struct nv_pmu_clk_regime_desc {
243 u8 regime_id;
244 u8 target_regime_id_override;
245 u16 fixed_freq_regime_limit_mhz;
246};
247
248struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header {
249 struct nv_pmu_boardobjgrp_e32 super;
250 struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask;
251 u32 lut_step_size_uv;
252 u32 lut_min_voltage_uv;
253 u8 lut_num_entries;
254 u16 max_min_freq_mhz;
255};
256
257struct nv_pmu_clk_clk_fll_device_boardobj_set {
258 struct nv_pmu_boardobj super;
259 u8 id;
260 u8 mdiv;
261 u8 vin_idx_logic;
262 u8 vin_idx_sram;
263 u8 rail_idx_for_lut;
264 u16 input_freq_mhz;
265 u32 clk_domain;
266 struct nv_pmu_clk_lut_device_desc lut_device;
267 struct nv_pmu_clk_regime_desc regime_desc;
268 u8 min_freq_vfe_idx;
269 u8 freq_ctrl_idx;
270 bool b_skip_pldiv_below_dvco_min;
271 bool b_dvco_1x;
272 struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask;
273};
274
275union nv_pmu_clk_clk_fll_device_boardobj_set_union {
276 struct nv_pmu_boardobj board_obj;
277 struct nv_pmu_clk_clk_fll_device_boardobj_set super;
278};
279
280NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device);
281
282struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header {
283 struct nv_pmu_boardobjgrp_e32 super;
284 bool b_vin_is_disable_allowed;
285};
286
287struct nv_pmu_clk_clk_vin_device_boardobj_set {
288 struct nv_pmu_boardobj super;
289 u8 id;
290 u8 volt_domain;
291 u32 flls_shared_mask;
292};
293
294struct nv_pmu_clk_clk_vin_device_v10_boardobj_set {
295 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
296 struct ctrl_clk_vin_device_info_data_v10 data;
297};
298
299struct nv_pmu_clk_clk_vin_device_v20_boardobj_set {
300 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
301 struct ctrl_clk_vin_device_info_data_v20 data;
302};
303
304union nv_pmu_clk_clk_vin_device_boardobj_set_union {
305 struct nv_pmu_boardobj board_obj;
306 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
307 struct nv_pmu_clk_clk_vin_device_v10_boardobj_set v10;
308 struct nv_pmu_clk_clk_vin_device_v20_boardobj_set v20;
309};
310
311NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device);
312
313struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header {
314 struct nv_pmu_boardobjgrp_e255 super;
315};
316
317struct nv_pmu_clk_clk_vf_point_boardobj_set {
318 struct nv_pmu_boardobj super;
319 u8 vfe_equ_idx;
320 u8 volt_rail_idx;
321};
322
323struct nv_pmu_clk_clk_vf_point_freq_boardobj_set {
324 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
325 u16 freq_mhz;
326 int volt_delta_uv;
327};
328
329struct nv_pmu_clk_clk_vf_point_volt_boardobj_set {
330 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
331 u32 source_voltage_uv;
332 struct ctrl_clk_freq_delta freq_delta;
333};
334
335union nv_pmu_clk_clk_vf_point_boardobj_set_union {
336 struct nv_pmu_boardobj board_obj;
337 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
338 struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq;
339 struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt;
340};
341
342NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point);
343
344struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header {
345 struct nv_pmu_boardobjgrp_e255 super;
346 u32 vf_points_cahce_counter;
347};
348
349struct nv_pmu_clk_clk_vf_point_boardobj_get_status {
350 struct nv_pmu_boardobj super;
351 struct ctrl_clk_vf_pair pair;
352 u8 dummy[38];
353};
354
355struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status {
356 struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
357 u16 vf_gain_value;
358};
359
360union nv_pmu_clk_clk_vf_point_boardobj_get_status_union {
361 struct nv_pmu_boardobj board_obj;
362 struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
363 struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt;
364};
365
366NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point);
367
368#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12)
369
370struct nv_pmu_clk_clk_domain_list {
371 u8 num_domains;
372 struct ctrl_clk_clk_domain_list_item clk_domains[
373 NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
374};
375
376struct nv_pmu_clk_clk_domain_list_v1 {
377 u8 num_domains;
378 struct ctrl_clk_clk_domain_list_item_v1 clk_domains[
379 NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
380};
381
382struct nv_pmu_clk_vf_change_inject {
383 u8 flags;
384 struct nv_pmu_clk_clk_domain_list clk_list;
385 struct nv_pmu_volt_volt_rail_list volt_list;
386};
387
388struct nv_pmu_clk_vf_change_inject_v1 {
389 u8 flags;
390 struct nv_pmu_clk_clk_domain_list_v1 clk_list;
391 struct nv_pmu_volt_volt_rail_list_v1 volt_list;
392};
393
394#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002)
395#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001)
396
397struct nv_pmu_clk_load_payload_freq_controllers {
398 struct ctrl_boardobjgrp_mask_e32 load_mask;
399};
400
401struct nv_pmu_clk_load {
402 u8 feature;
403 u32 action_mask;
404 union {
405 struct nv_pmu_clk_load_payload_freq_controllers freq_controllers;
406 } payload;
407};
408
409struct nv_pmu_clk_freq_effective_avg {
410 u32 clkDomainMask;
411 u32 freqkHz[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
412};
413
414/* CLK_FREQ_CONTROLLER */
415#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003)
416
417#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000)
418#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002)
419
420struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header {
421 struct nv_pmu_boardobjgrp_e32 super;
422 u32 sampling_period_ms;
423 u8 volt_policy_idx;
424};
425
426struct nv_pmu_clk_clk_freq_controller_boardobj_set {
427 struct nv_pmu_boardobj super;
428 u8 controller_id;
429 u8 parts_freq_mode;
430 bool bdisable;
431 u32 clk_domain;
432 s16 freq_cap_noise_unaware_vmin_above;
433 s16 freq_cap_noise_unaware_vmin_below;
434 s16 freq_hyst_pos_mhz;
435 s16 freq_hyst_neg_mhz;
436};
437
438struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set {
439 struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
440 s32 prop_gain;
441 s32 integ_gain;
442 s32 integ_decay;
443 s32 volt_delta_min;
444 s32 volt_delta_max;
445 u8 slowdown_pct_min;
446 bool bpoison;
447};
448
449union nv_pmu_clk_clk_freq_controller_boardobj_set_union {
450 struct nv_pmu_boardobj board_obj;
451 struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
452 struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi;
453};
454
455NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller);
456
457#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_EFFECTIVE_AVG (0x00000004)
458#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO (0x00000000)
459#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES (0x00000004)
460
461/* CLK CMD ID definitions. */
462#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001)
463#define NV_PMU_CLK_CMD_ID_RPC (0x00000000)
464#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
465
466#define NV_PMU_CLK_RPC_ID_LOAD (0x00000001)
467#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000)
468#define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002)
469
470struct nv_pmu_clk_cmd_rpc {
471 u8 cmd_type;
472 u8 pad[3];
473 struct nv_pmu_allocation request;
474};
475
476struct nv_pmu_clk_cmd_generic {
477 u8 cmd_type;
478 bool b_perf_daemon_cmd;
479 u8 pad[2];
480};
481
482#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \
483 (offsetof(struct nv_pmu_clk_cmd_rpc, request))
484
485struct nv_pmu_clk_cmd {
486 union {
487 u8 cmd_type;
488 struct nv_pmu_boardobj_cmd_grp grp_set;
489 struct nv_pmu_clk_cmd_generic generic;
490 struct nv_pmu_clk_cmd_rpc rpc;
491 struct nv_pmu_boardobj_cmd_grp grp_get_status;
492 };
493};
494
495struct nv_pmu_clk_rpc {
496 u8 function;
497 bool b_supported;
498 bool b_success;
499 flcn_status flcn_status;
500 union {
501 struct nv_pmu_clk_vf_change_inject clk_vf_change_inject;
502 struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1;
503 struct nv_pmu_clk_load clk_load;
504 struct nv_pmu_clk_freq_effective_avg clk_freq_effective_avg;
505 } params;
506};
507
508/* CLK MSG ID definitions */
509#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000001)
510#define NV_PMU_CLK_MSG_ID_RPC (0x00000000)
511#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
512
513struct nv_pmu_clk_msg_rpc {
514 u8 msg_type;
515 u8 rsvd[3];
516 struct nv_pmu_allocation response;
517};
518
519#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \
520 offsetof(struct nv_pmu_clk_msg_rpc, response)
521
522struct nv_pmu_clk_msg {
523 union {
524 u8 msg_type;
525 struct nv_pmu_boardobj_msg_grp grp_set;
526 struct nv_pmu_clk_msg_rpc rpc;
527 struct nv_pmu_boardobj_msg_grp grp_get_status;
528 };
529};
530
531struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header {
532 struct nv_pmu_boardobjgrp_e32 super;
533};
534
535struct nv_pmu_clk_clk_vin_device_boardobj_get_status {
536 struct nv_pmu_boardobj_query super;
537 u32 actual_voltage_uv;
538 u32 corrected_voltage_uv;
539 u8 sampled_code;
540 u8 override_code;
541};
542
543union nv_pmu_clk_clk_vin_device_boardobj_get_status_union {
544 struct nv_pmu_boardobj_query board_obj;
545 struct nv_pmu_clk_clk_vin_device_boardobj_get_status super;
546};
547
548NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device);
549
550struct nv_pmu_clk_lut_vf_entry {
551 u32 entry;
552};
553
554struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header {
555 struct nv_pmu_boardobjgrp_e32 super;
556};
557
558struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
559 struct nv_pmu_boardobj_query super;
560 u8 current_regime_id;
561 bool b_dvco_min_reached;
562 u16 min_freq_mhz;
563 struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES_MAX, 2)];
564};
565
566union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {
567 struct nv_pmu_boardobj_query board_obj;
568 struct nv_pmu_clk_clk_fll_device_boardobj_get_status super;
569};
570
571NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device);
572
573#endif /*NVGPU_PMUIF_GPMUIFCLK_H*/
diff --git a/include/nvgpu/pmuif/gpmuifperf.h b/include/nvgpu/pmuif/gpmuifperf.h
new file mode 100644
index 0000000..70b93e1
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifperf.h
@@ -0,0 +1,154 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIFPERF_H
23#define NVGPU_PMUIF_GPMUIFPERF_H
24
25#include "gpmuifvolt.h"
26#include "gpmuifperfvfe.h"
27
28/*
29* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId"
30* argument for communications between Kernel and PMU via the various generic
31* BOARDOBJGRP interfaces.
32*/
33#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00U
34#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01U
35
36#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U)
37#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U)
38#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U)
39
40/*!
41 * RPC calls serviced by PERF unit.
42 */
43#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U
44#define NV_PMU_RPC_ID_PERF_LOAD 0x01U
45#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U
46#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U
47#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U
48#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U
49#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U
50#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07U
51#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08U
52#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09U
53#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU
54#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU
55#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU
56#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU
57#define NV_PMU_RPC_ID_PERF__COUNT 0x0EU
58/*
59 * Defines the structure that holds data
60 * used to execute LOAD RPC.
61 */
62struct nv_pmu_rpc_struct_perf_load {
63 /*[IN/OUT] Must be first field in RPC structure */
64 struct nv_pmu_rpc_header hdr;
65 u32 scratch[1];
66};
67
68struct nv_pmu_perf_cmd_set_object {
69 u8 cmd_type;
70 u8 pad[2];
71 u8 object_type;
72 struct nv_pmu_allocation object;
73};
74
75#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \
76 (offsetof(struct nv_pmu_perf_cmd_set_object, object))
77
78/* RPC IDs */
79#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001U)
80
81/*!
82* Command requesting execution of the perf RPC.
83*/
84struct nv_pmu_perf_cmd_rpc {
85 u8 cmd_type;
86 u8 pad[3];
87 struct nv_pmu_allocation request;
88};
89
90#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \
91 offsetof(struct nv_pmu_perf_cmd_rpc, request)
92
93/*!
94* Simply a union of all specific PERF commands. Forms the general packet
95* exchanged between the Kernel and PMU when sending and receiving PERF commands
96* (respectively).
97*/
98struct nv_pmu_perf_cmd {
99 union {
100 u8 cmd_type;
101 struct nv_pmu_perf_cmd_set_object set_object;
102 struct nv_pmu_boardobj_cmd_grp grp_set;
103 struct nv_pmu_boardobj_cmd_grp grp_get_status;
104 };
105};
106
107/*!
108* Defines the data structure used to invoke PMU perf RPCs. Same structure is
109* used to return the result of the RPC execution.
110*/
111struct nv_pmu_perf_rpc {
112 u8 function;
113 bool b_supported;
114 bool b_success;
115 flcn_status flcn_status;
116 union {
117 struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval;
118 struct nv_pmu_perf_rpc_vfe_load vfe_load;
119 } params;
120};
121
122
123/* PERF Message-type Definitions */
124#define NV_PMU_PERF_MSG_ID_RPC (0x00000003U)
125#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U)
126#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U)
127#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005U)
128
129/*!
130* Message carrying the result of the perf RPC execution.
131*/
132struct nv_pmu_perf_msg_rpc {
133 u8 msg_type;
134 u8 rsvd[3];
135 struct nv_pmu_allocation response;
136};
137
138#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \
139 (offsetof(struct nv_pmu_perf_msg_rpc, response))
140
141/*!
142* Simply a union of all specific PERF messages. Forms the general packet
143* exchanged between the Kernel and PMU when sending and receiving PERF messages
144* (respectively).
145*/
146struct nv_pmu_perf_msg {
147 union {
148 u8 msg_type;
149 struct nv_pmu_perf_msg_rpc rpc;
150 struct nv_pmu_boardobj_msg_grp grp_set;
151 };
152};
153
154#endif /* NVGPU_PMUIF_GPMUIFPERF_H*/
diff --git a/include/nvgpu/pmuif/gpmuifperfvfe.h b/include/nvgpu/pmuif/gpmuifperfvfe.h
new file mode 100644
index 0000000..d128c32
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifperfvfe.h
@@ -0,0 +1,206 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIFPERFVFE_H
23#define NVGPU_PMUIF_GPMUIFPERFVFE_H
24
25#include "gpmuifbios.h"
26#include "gpmuifboardobj.h"
27#include "ctrl/ctrlperf.h"
28
29#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03
30#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2
31#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16
32
33struct nv_pmu_perf_vfe_var_value {
34 u8 var_type;
35 u8 reserved[3];
36 u32 var_value;
37};
38
39union nv_pmu_perf_vfe_equ_result {
40 u32 freq_m_hz;
41 u32 voltu_v;
42 u32 vf_gain;
43 int volt_deltau_v;
44};
45
46struct nv_pmu_perf_rpc_vfe_equ_eval {
47 u8 equ_idx;
48 u8 var_count;
49 u8 output_type;
50 struct nv_pmu_perf_vfe_var_value var_values[
51 NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX];
52 union nv_pmu_perf_vfe_equ_result result;
53};
54
55struct nv_pmu_perf_rpc_vfe_load {
56 bool b_load;
57};
58
59struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header {
60 struct nv_pmu_boardobjgrp_e32 super;
61};
62
63struct nv_pmu_perf_vfe_var_get_status_super {
64 struct nv_pmu_boardobj_query board_obj;
65};
66
67struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status {
68 struct nv_pmu_perf_vfe_var_get_status_super super;
69 struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer;
70 struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_hw_integer;
71 u8 fuse_version;
72 bool b_version_check_failed;
73};
74
75union nv_pmu_perf_vfe_var_boardobj_get_status_union {
76 struct nv_pmu_boardobj_query board_obj;
77 struct nv_pmu_perf_vfe_var_get_status_super super;
78 struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status;
79};
80
81NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var);
82
83struct nv_pmu_vfe_var {
84 struct nv_pmu_boardobj super;
85 u32 out_range_min;
86 u32 out_range_max;
87 struct ctrl_boardobjgrp_mask_e32 mask_dependent_vars;
88 struct ctrl_boardobjgrp_mask_e255 mask_dependent_equs;
89};
90
91struct nv_pmu_vfe_var_derived {
92 struct nv_pmu_vfe_var super;
93};
94
95struct nv_pmu_vfe_var_derived_product {
96 struct nv_pmu_vfe_var_derived super;
97 u8 var_idx0;
98 u8 var_idx1;
99};
100
101struct nv_pmu_vfe_var_derived_sum {
102 struct nv_pmu_vfe_var_derived super;
103 u8 var_idx0;
104 u8 var_idx1;
105};
106
107struct nv_pmu_vfe_var_single {
108 struct nv_pmu_vfe_var super;
109 u8 override_type;
110 u32 override_value;
111};
112
113struct nv_pmu_vfe_var_single_frequency {
114 struct nv_pmu_vfe_var_single super;
115};
116
117struct nv_pmu_vfe_var_single_sensed {
118 struct nv_pmu_vfe_var_single super;
119};
120
121struct nv_pmu_vfe_var_single_sensed_fuse {
122 struct nv_pmu_vfe_var_single_sensed super;
123 struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info;
124 struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info;
125 struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info;
126 struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default;
127 bool b_fuse_value_signed;
128};
129
130struct nv_pmu_vfe_var_single_sensed_temp {
131 struct nv_pmu_vfe_var_single_sensed super;
132 u8 therm_channel_index;
133 int temp_hysteresis_positive;
134 int temp_hysteresis_negative;
135 int temp_default;
136};
137
138struct nv_pmu_vfe_var_single_voltage {
139 struct nv_pmu_vfe_var_single super;
140};
141
142struct nv_pmu_perf_vfe_var_boardobjgrp_set_header {
143 struct nv_pmu_boardobjgrp_e32 super;
144 u8 polling_periodms;
145};
146
147union nv_pmu_perf_vfe_var_boardobj_set_union {
148 struct nv_pmu_boardobj board_obj;
149 struct nv_pmu_vfe_var var;
150 struct nv_pmu_vfe_var_derived var_derived;
151 struct nv_pmu_vfe_var_derived_product var_derived_product;
152 struct nv_pmu_vfe_var_derived_sum var_derived_sum;
153 struct nv_pmu_vfe_var_single var_single;
154 struct nv_pmu_vfe_var_single_frequency var_single_frequiency;
155 struct nv_pmu_vfe_var_single_sensed var_single_sensed;
156 struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse;
157 struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp;
158 struct nv_pmu_vfe_var_single_voltage var_single_voltage;
159};
160
161NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var);
162
163struct nv_pmu_vfe_equ {
164 struct nv_pmu_boardobj super;
165 u8 var_idx;
166 u8 equ_idx_next;
167 u8 output_type;
168 u32 out_range_min;
169 u32 out_range_max;
170};
171
172struct nv_pmu_vfe_equ_compare {
173 struct nv_pmu_vfe_equ super;
174 u8 func_id;
175 u8 equ_idx_true;
176 u8 equ_idx_false;
177 u32 criteria;
178};
179
180struct nv_pmu_vfe_equ_minmax {
181 struct nv_pmu_vfe_equ super;
182 bool b_max;
183 u8 equ_idx0;
184 u8 equ_idx1;
185};
186
187struct nv_pmu_vfe_equ_quadratic {
188 struct nv_pmu_vfe_equ super;
189 u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT];
190};
191
192struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header {
193 struct nv_pmu_boardobjgrp_e255 super;
194};
195
196union nv_pmu_perf_vfe_equ_boardobj_set_union {
197 struct nv_pmu_boardobj board_obj;
198 struct nv_pmu_vfe_equ equ;
199 struct nv_pmu_vfe_equ_compare equ_comapre;
200 struct nv_pmu_vfe_equ_minmax equ_minmax;
201 struct nv_pmu_vfe_equ_quadratic equ_quadratic;
202};
203
204NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ);
205
206#endif /* NVGPU_PMUIF_GPMUIFPERFVFE_H*/
diff --git a/include/nvgpu/pmuif/gpmuifpmgr.h b/include/nvgpu/pmuif/gpmuifpmgr.h
new file mode 100644
index 0000000..a0e6c82
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifpmgr.h
@@ -0,0 +1,443 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_PMUIF_GPMUIFPMGR_H
24#define NVGPU_PMUIF_GPMUIFPMGR_H
25
26#include "ctrl/ctrlpmgr.h"
27#include "gpmuifboardobj.h"
28#include <nvgpu/flcnif_cmn.h>
29
30struct nv_pmu_pmgr_i2c_device_desc {
31 struct nv_pmu_boardobj super;
32 u8 dcb_index;
33 u16 i2c_address;
34 u32 i2c_flags;
35 u8 i2c_port;
36};
37
38#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32U)
39
40struct nv_pmu_pmgr_i2c_device_desc_table {
41 u32 dev_mask;
42 struct nv_pmu_pmgr_i2c_device_desc
43 devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES];
44};
45
46struct nv_pmu_pmgr_pwr_device_desc {
47 struct nv_pmu_boardobj super;
48 u32 power_corr_factor;
49};
50
51#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03U
52
53struct nv_pmu_pmgr_pwr_device_desc_ina3221 {
54 struct nv_pmu_pmgr_pwr_device_desc super;
55 u8 i2c_dev_idx;
56 struct ctrl_pmgr_pwr_device_info_rshunt
57 r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM];
58 u16 configuration;
59 u16 mask_enable;
60 u32 event_mask;
61 u16 curr_correct_m;
62 s16 curr_correct_b;
63};
64
65union nv_pmu_pmgr_pwr_device_desc_union {
66 struct nv_pmu_boardobj board_obj;
67 struct nv_pmu_pmgr_pwr_device_desc pwr_dev;
68 struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221;
69};
70
71struct nv_pmu_pmgr_pwr_device_ba_info {
72 bool b_initialized_and_used;
73};
74
75struct nv_pmu_pmgr_pwr_device_desc_table_header {
76 struct nv_pmu_boardobjgrp_e32 super;
77 struct nv_pmu_pmgr_pwr_device_ba_info ba_info;
78};
79
80NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header,
81 sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header));
82NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union,
83 sizeof(union nv_pmu_pmgr_pwr_device_desc_union));
84
85struct nv_pmu_pmgr_pwr_device_desc_table {
86 union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr;
87 union nv_pmu_pmgr_pwr_device_desc_union_aligned
88 devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES];
89};
90
91union nv_pmu_pmgr_pwr_device_dmem_size {
92 union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr;
93 union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device;
94};
95
96struct nv_pmu_pmgr_pwr_channel {
97 struct nv_pmu_boardobj super;
98 u8 pwr_rail;
99 u8 ch_idx;
100 u32 volt_fixedu_v;
101 u32 pwr_corr_slope;
102 s32 pwr_corr_offsetm_w;
103 u32 curr_corr_slope;
104 s32 curr_corr_offsetm_a;
105 u32 dependent_ch_mask;
106};
107
108#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16U
109
110#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16U
111
112struct nv_pmu_pmgr_pwr_channel_sensor {
113 struct nv_pmu_pmgr_pwr_channel super;
114 u8 pwr_dev_idx;
115 u8 pwr_dev_prov_idx;
116};
117
118struct nv_pmu_pmgr_pwr_channel_pmu_compactible {
119 u8 pmu_compactible_data[56];
120};
121
122union nv_pmu_pmgr_pwr_channel_union {
123 struct nv_pmu_boardobj board_obj;
124 struct nv_pmu_pmgr_pwr_channel pwr_channel;
125 struct nv_pmu_pmgr_pwr_channel_sensor sensor;
126 struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel;
127};
128
129#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02U
130
131struct nv_pmu_pmgr_pwr_monitor_pstate {
132 u32 hw_channel_mask;
133};
134
135union nv_pmu_pmgr_pwr_monitor_type_specific {
136 struct nv_pmu_pmgr_pwr_monitor_pstate pstate;
137};
138
139struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible {
140 u8 pmu_compactible_data[28];
141};
142
143union nv_pmu_pmgr_pwr_chrelationship_union {
144 struct nv_pmu_boardobj board_obj;
145 struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship;
146};
147
148struct nv_pmu_pmgr_pwr_channel_header {
149 struct nv_pmu_boardobjgrp_e32 super;
150 u8 type;
151 union nv_pmu_pmgr_pwr_monitor_type_specific type_specific;
152 u8 sample_count;
153 u16 sampling_periodms;
154 u16 sampling_period_low_powerms;
155 u32 total_gpu_power_channel_mask;
156 u32 physical_channel_mask;
157};
158
159struct nv_pmu_pmgr_pwr_chrelationship_header {
160 struct nv_pmu_boardobjgrp_e32 super;
161};
162
163NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header,
164 sizeof(struct nv_pmu_pmgr_pwr_channel_header));
165NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header,
166 sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header));
167NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union,
168 sizeof(union nv_pmu_pmgr_pwr_chrelationship_union));
169NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union,
170 sizeof(union nv_pmu_pmgr_pwr_channel_union));
171
172struct nv_pmu_pmgr_pwr_channel_desc {
173 union nv_pmu_pmgr_pwr_channel_header_aligned hdr;
174 union nv_pmu_pmgr_pwr_channel_union_aligned
175 channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS];
176};
177
178struct nv_pmu_pmgr_pwr_chrelationship_desc {
179 union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr;
180 union nv_pmu_pmgr_pwr_chrelationship_union_aligned
181 ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS];
182};
183
184union nv_pmu_pmgr_pwr_monitor_dmem_size {
185 union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr;
186 union nv_pmu_pmgr_pwr_channel_union_aligned channel;
187 union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr;
188 union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels;
189};
190
191struct nv_pmu_pmgr_pwr_monitor_pack {
192 struct nv_pmu_pmgr_pwr_channel_desc channels;
193 struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels;
194};
195
196#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32U
197
198#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32U
199
200struct nv_pmu_pmgr_pwr_policy {
201 struct nv_pmu_boardobj super;
202 u8 ch_idx;
203 u8 num_limit_inputs;
204 u8 limit_unit;
205 u8 sample_mult;
206 u32 limit_curr;
207 u32 limit_min;
208 u32 limit_max;
209 struct ctrl_pmgr_pwr_policy_info_integral integral;
210 enum ctrl_pmgr_pwr_policy_filter_type filter_type;
211 union ctrl_pmgr_pwr_policy_filter_param filter_param;
212};
213
214struct nv_pmu_pmgr_pwr_policy_hw_threshold {
215 struct nv_pmu_pmgr_pwr_policy super;
216 u8 threshold_idx;
217 u8 low_threshold_idx;
218 bool b_use_low_threshold;
219 u16 low_threshold_value;
220};
221
222struct nv_pmu_pmgr_pwr_policy_sw_threshold {
223 struct nv_pmu_pmgr_pwr_policy super;
224 u8 threshold_idx;
225 u8 low_threshold_idx;
226 bool b_use_low_threshold;
227 u16 low_threshold_value;
228 u8 event_id;
229};
230
231struct nv_pmu_pmgr_pwr_policy_pmu_compactible {
232 u8 pmu_compactible_data[68];
233};
234
235union nv_pmu_pmgr_pwr_policy_union {
236 struct nv_pmu_boardobj board_obj;
237 struct nv_pmu_pmgr_pwr_policy pwr_policy;
238 struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold;
239 struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold;
240 struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy;
241};
242
243struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible {
244 u8 pmu_compactible_data[24];
245};
246
247union nv_pmu_pmgr_pwr_policy_relationship_union {
248 struct nv_pmu_boardobj board_obj;
249 struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship;
250};
251
252struct nv_pmu_pmgr_pwr_violation_pmu_compactible {
253 u8 pmu_compactible_data[16];
254};
255
256union nv_pmu_pmgr_pwr_violation_union {
257 struct nv_pmu_boardobj board_obj;
258 struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation;
259};
260
261#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30U
262
263NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union,
264 sizeof(union nv_pmu_pmgr_pwr_policy_union));
265NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union,
266 sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union));
267
268#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2U
269
270struct nv_pmu_perf_domain_group_limits
271{
272 u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS];
273} ;
274
275#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6U
276
277struct nv_pmu_pmgr_pwr_policy_desc_header {
278 struct nv_pmu_boardobjgrp_e32 super;
279 u8 version;
280 bool b_enabled;
281 u8 low_sampling_mult;
282 u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
283 u16 base_sample_period;
284 u16 min_client_sample_period;
285 u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT];
286 struct nv_pmu_perf_domain_group_limits global_ceiling;
287};
288
289NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header ,
290 sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header ));
291
292struct nv_pmu_pmgr_pwr_policyrel_desc_header {
293 struct nv_pmu_boardobjgrp_e32 super;
294};
295
296NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header,
297 sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header));
298
299struct nv_pmu_pmgr_pwr_violation_desc_header {
300 struct nv_pmu_boardobjgrp_e32 super;
301};
302
303NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header,
304 sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header));
305NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union,
306 sizeof(union nv_pmu_pmgr_pwr_violation_union));
307
308struct nv_pmu_pmgr_pwr_policy_desc {
309 union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr;
310 union nv_pmu_pmgr_pwr_policy_union_aligned
311 policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES];
312};
313
314struct nv_pmu_pmgr_pwr_policyrel_desc {
315 union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr;
316 union nv_pmu_pmgr_pwr_policy_relationship_union_aligned
317 policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS];
318};
319
320struct nv_pmu_pmgr_pwr_violation_desc {
321 union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr;
322 union nv_pmu_pmgr_pwr_violation_union_aligned
323 violations[CTRL_PMGR_PWR_VIOLATION_MAX];
324};
325
326union nv_pmu_pmgr_pwr_policy_dmem_size {
327 union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr;
328 union nv_pmu_pmgr_pwr_policy_union_aligned policy;
329 union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr;
330 union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels;
331 union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr;
332 union nv_pmu_pmgr_pwr_violation_union_aligned violation;
333};
334
335struct nv_pmu_pmgr_pwr_policy_pack {
336 struct nv_pmu_pmgr_pwr_policy_desc policies;
337 struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels;
338 struct nv_pmu_pmgr_pwr_violation_desc violations;
339};
340
341#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000U)
342
343#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002U)
344
345#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001U)
346
347#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006U)
348
349#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007U)
350
351struct nv_pmu_pmgr_cmd_set_object {
352 u8 cmd_type;
353 u8 pad[2];
354 u8 object_type;
355 struct nv_pmu_allocation object;
356};
357
358#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04U)
359
360#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000U)
361
362#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001U)
363
364#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002U)
365
366#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005U)
367
368struct nv_pmu_pmgr_pwr_devices_query_payload {
369 struct {
370 u32 powerm_w;
371 u32 voltageu_v;
372 u32 currentm_a;
373 } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES];
374};
375
376struct nv_pmu_pmgr_cmd_pwr_devices_query {
377 u8 cmd_type;
378 u8 pad[3];
379 u32 dev_mask;
380 struct nv_pmu_allocation payload;
381};
382
383#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08U)
384
385struct nv_pmu_pmgr_cmd_load {
386 u8 cmd_type;
387};
388
389struct nv_pmu_pmgr_cmd_unload {
390 u8 cmd_type;
391};
392
393struct nv_pmu_pmgr_cmd {
394 union {
395 u8 cmd_type;
396 struct nv_pmu_pmgr_cmd_set_object set_object;
397 struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query;
398 struct nv_pmu_pmgr_cmd_load load;
399 struct nv_pmu_pmgr_cmd_unload unload;
400 };
401};
402
403#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000U)
404
405#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004U)
406
407#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005U)
408
409struct nv_pmu_pmgr_msg_set_object {
410 u8 msg_type;
411 bool b_success;
412 flcn_status flcnstatus;
413 u8 object_type;
414};
415
416struct nv_pmu_pmgr_msg_query {
417 u8 msg_type;
418 bool b_success;
419 flcn_status flcnstatus;
420 u8 cmd_type;
421};
422
423struct nv_pmu_pmgr_msg_load {
424 u8 msg_type;
425 bool b_success;
426 flcn_status flcnstatus;
427};
428
429struct nv_pmu_pmgr_msg_unload {
430 u8 msg_type;
431};
432
433struct nv_pmu_pmgr_msg {
434 union {
435 u8 msg_type;
436 struct nv_pmu_pmgr_msg_set_object set_object;
437 struct nv_pmu_pmgr_msg_query query;
438 struct nv_pmu_pmgr_msg_load load;
439 struct nv_pmu_pmgr_msg_unload unload;
440 };
441};
442
443#endif /* NVGPU_PMUIF_GPMUIFPMGR_H */
diff --git a/include/nvgpu/pmuif/gpmuifseq.h b/include/nvgpu/pmuif/gpmuifseq.h
new file mode 100644
index 0000000..af93a6e
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifseq.h
@@ -0,0 +1,82 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#ifndef NVGPU_PMUIF_GPMUIFSEQ_H
23#define NVGPU_PMUIF_GPMUIFSEQ_H
24
25#include <nvgpu/flcnif_cmn.h>
26
27#define PMU_UNIT_SEQ (0x02)
28
29/*!
30* @file gpmuifseq.h
31* @brief PMU Command/Message Interfaces - Sequencer
32*/
33
34/*!
35* Defines the identifiers various high-level types of sequencer commands.
36*
37* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT
38*/
39enum {
40 NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0,
41};
42
43struct nv_pmu_seq_cmd_run_script {
44 u8 cmd_type;
45 u8 pad[3];
46 struct pmu_allocation_v3 script_alloc;
47 struct pmu_allocation_v3 reg_alloc;
48};
49
50#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4
51
52#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \
53 (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE)
54
55struct nv_pmu_seq_cmd {
56 struct pmu_hdr hdr;
57 union {
58 u8 cmd_type;
59 struct nv_pmu_seq_cmd_run_script run_script;
60 };
61};
62
63enum {
64 NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0,
65};
66
67struct nv_pmu_seq_msg_run_script {
68 u8 msg_type;
69 u8 error_code;
70 u16 error_pc;
71 u32 timeout_stat;
72};
73
74struct nv_pmu_seq_msg {
75 struct pmu_hdr hdr;
76 union {
77 u8 msg_type;
78 struct nv_pmu_seq_msg_run_script run_script;
79 };
80};
81
82#endif /* NVGPU_PMUIF_GPMUIFSEQ_H */
diff --git a/include/nvgpu/pmuif/gpmuiftherm.h b/include/nvgpu/pmuif/gpmuiftherm.h
new file mode 100644
index 0000000..115e7ab
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuiftherm.h
@@ -0,0 +1,102 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_PMUIF_GPMUIFTHERM_H
24#define NVGPU_PMUIF_GPMUIFTHERM_H
25
26#include <nvgpu/flcnif_cmn.h>
27
28#define NV_PMU_THERM_CMD_ID_RPC 0x00000002
29#define NV_PMU_THERM_MSG_ID_RPC 0x00000002
30#define NV_PMU_THERM_RPC_ID_SLCT 0x00000000
31#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006
32#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004
33#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001
34#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001
35#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001
36
37struct nv_pmu_therm_rpc_slct_event_temp_th_set {
38 s32 temp_threshold;
39 u8 event_id;
40 flcn_status flcn_stat;
41};
42
43struct nv_pmu_therm_rpc_slct {
44 u32 mask_enabled;
45 flcn_status flcn_stat;
46};
47
48struct nv_pmu_therm_rpc {
49 u8 function;
50 bool b_supported;
51 union {
52 struct nv_pmu_therm_rpc_slct slct;
53 struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set;
54 } params;
55};
56
57struct nv_pmu_therm_cmd_rpc {
58 u8 cmd_type;
59 u8 pad[3];
60 struct nv_pmu_allocation request;
61};
62
63struct nv_pmu_therm_cmd_hw_slowdown_notification {
64 u8 cmd_type;
65 u8 request;
66};
67
68#define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET \
69 offsetof(struct nv_pmu_therm_cmd_rpc, request)
70
71struct nv_pmu_therm_cmd {
72 union {
73 u8 cmd_type;
74 struct nv_pmu_therm_cmd_rpc rpc;
75 struct nv_pmu_therm_cmd_hw_slowdown_notification hw_slct_notification;
76 };
77};
78
79struct nv_pmu_therm_msg_rpc {
80 u8 msg_type;
81 u8 rsvd[3];
82 struct nv_pmu_allocation response;
83};
84
85struct nv_pmu_therm_msg_event_hw_slowdown_notification {
86 u8 msg_type;
87 u32 mask;
88};
89
90#define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET \
91 offsetof(struct nv_pmu_therm_msg_rpc, response)
92
93struct nv_pmu_therm_msg {
94 union {
95 u8 msg_type;
96 struct nv_pmu_therm_msg_rpc rpc;
97 struct nv_pmu_therm_msg_event_hw_slowdown_notification hw_slct_msg;
98 };
99};
100
101#endif /* NVGPU_PMUIF_GPMUIFTHERM_H */
102
diff --git a/include/nvgpu/pmuif/gpmuifthermsensor.h b/include/nvgpu/pmuif/gpmuifthermsensor.h
new file mode 100644
index 0000000..47d35da
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifthermsensor.h
@@ -0,0 +1,105 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
24#define NVGPU_PMUIF_GPMUIFTHERMSENSOR_H
25
26#include "ctrl/ctrltherm.h"
27#include "gpmuifboardobj.h"
28#include <nvgpu/flcnif_cmn.h>
29
30#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00
31#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01
32
33#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B
34#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008
35
36struct nv_pmu_therm_therm_device_boardobjgrp_set_header {
37 struct nv_pmu_boardobjgrp_e32 super;
38};
39
40struct nv_pmu_therm_therm_device_boardobj_set {
41 struct nv_pmu_boardobj super;
42};
43
44struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set {
45 struct nv_pmu_therm_therm_device_boardobj_set super;
46 u8 gpc_tsosc_idx;
47};
48
49struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set {
50 struct nv_pmu_therm_therm_device_boardobj_set super;
51};
52
53struct nv_pmu_therm_therm_device_i2c_boardobj_set {
54 struct nv_pmu_therm_therm_device_boardobj_set super;
55 u8 i2c_dev_idx;
56};
57
58struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set {
59 struct nv_pmu_therm_therm_device_boardobj_set super;
60 u8 site_idx;
61};
62
63struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set {
64 struct nv_pmu_therm_therm_device_boardobj_set super;
65};
66
67union nv_pmu_therm_therm_device_boardobj_set_union {
68 struct nv_pmu_boardobj board_obj;
69 struct nv_pmu_therm_therm_device_boardobj_set therm_device;
70 struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set gpu_gpc_tsosc;
71 struct nv_pmu_therm_therm_device_gpu_sci_boardobj_set gpu_sci;
72 struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c;
73 struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set hbm2_site;
74 struct nv_pmu_therm_therm_device_hbm2_combined_boardobj_set hbm2_combined;
75};
76
77NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device);
78
79struct nv_pmu_therm_therm_channel_boardobjgrp_set_header {
80 struct nv_pmu_boardobjgrp_e32 super;
81};
82
83struct nv_pmu_therm_therm_channel_boardobj_set {
84 struct nv_pmu_boardobj super;
85 s16 scaling;
86 s16 offset;
87 s32 temp_min;
88 s32 temp_max;
89};
90
91struct nv_pmu_therm_therm_channel_device_boardobj_set {
92 struct nv_pmu_therm_therm_channel_boardobj_set super;
93 u8 therm_dev_idx;
94 u8 therm_dev_prov_idx;
95};
96
97union nv_pmu_therm_therm_channel_boardobj_set_union {
98 struct nv_pmu_boardobj board_obj;
99 struct nv_pmu_therm_therm_channel_boardobj_set therm_channel;
100 struct nv_pmu_therm_therm_channel_device_boardobj_set device;
101};
102
103NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel);
104
105#endif /* NVGPU_PMUIF_GPMUIFTHERMSENSOR_H */
diff --git a/include/nvgpu/pmuif/gpmuifvolt.h b/include/nvgpu/pmuif/gpmuifvolt.h
new file mode 100644
index 0000000..0161719
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuifvolt.h
@@ -0,0 +1,402 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#ifndef NVGPU_PMUIF_GPMUIFVOLT_H
23#define NVGPU_PMUIF_GPMUIFVOLT_H
24
25#include "gpmuifboardobj.h"
26#include <nvgpu/flcnif_cmn.h>
27#include "ctrl/ctrlvolt.h"
28
29#define NV_PMU_VOLT_VALUE_0V_IN_UV (0U)
30
31/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */
32
33#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00U
34#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01U
35#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02U
36
37
38struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
39 struct nv_pmu_boardobjgrp_e32 super;
40};
41
42struct nv_pmu_volt_volt_rail_boardobj_set {
43
44 struct nv_pmu_boardobj super;
45 u8 rel_limit_vfe_equ_idx;
46 u8 alt_rel_limit_vfe_equ_idx;
47 u8 ov_limit_vfe_equ_idx;
48 u8 vmin_limit_vfe_equ_idx;
49 u8 volt_margin_limit_vfe_equ_idx;
50 u8 pwr_equ_idx;
51 u8 volt_dev_idx_default;
52 u8 volt_dev_idx_ipc_vmin;
53 u8 volt_scale_exp_pwr_equ_idx;
54 struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
55 s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
56};
57
58union nv_pmu_volt_volt_rail_boardobj_set_union {
59 struct nv_pmu_boardobj board_obj;
60 struct nv_pmu_volt_volt_rail_boardobj_set super;
61};
62
63NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail);
64
65/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */
66
67struct nv_pmu_volt_volt_device_boardobjgrp_set_header {
68 struct nv_pmu_boardobjgrp_e32 super;
69};
70
71struct nv_pmu_volt_volt_device_boardobj_set {
72 struct nv_pmu_boardobj super;
73 u32 switch_delay_us;
74 u32 voltage_min_uv;
75 u32 voltage_max_uv;
76 u32 volt_step_uv;
77};
78
79struct nv_pmu_volt_volt_device_vid_boardobj_set {
80 struct nv_pmu_volt_volt_device_boardobj_set super;
81 s32 voltage_base_uv;
82 s32 voltage_offset_scale_uv;
83 u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES];
84 u8 vsel_mask;
85};
86
87struct nv_pmu_volt_volt_device_pwm_boardobj_set {
88 struct nv_pmu_volt_volt_device_boardobj_set super;
89 u32 raw_period;
90 s32 voltage_base_uv;
91 s32 voltage_offset_scale_uv;
92 enum nv_pmu_pmgr_pwm_source pwm_source;
93};
94
95union nv_pmu_volt_volt_device_boardobj_set_union {
96 struct nv_pmu_boardobj board_obj;
97 struct nv_pmu_volt_volt_device_boardobj_set super;
98 struct nv_pmu_volt_volt_device_vid_boardobj_set vid;
99 struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm;
100};
101
102NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
103
104/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
105struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
106 struct nv_pmu_boardobjgrp_e32 super;
107 u8 perf_core_vf_seq_policy_idx;
108};
109
110struct nv_pmu_volt_volt_policy_boardobj_set {
111 struct nv_pmu_boardobj super;
112};
113struct nv_pmu_volt_volt_policy_sr_boardobj_set {
114 struct nv_pmu_volt_volt_policy_boardobj_set super;
115 u8 rail_idx;
116};
117
118struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set {
119 struct nv_pmu_volt_volt_policy_sr_boardobj_set super;
120 u16 inter_switch_delay_us;
121 u32 ramp_up_step_size_uv;
122 u32 ramp_down_step_size_uv;
123};
124
125struct nv_pmu_volt_volt_policy_splt_r_boardobj_set {
126 struct nv_pmu_volt_volt_policy_boardobj_set super;
127 u8 rail_idx_master;
128 u8 rail_idx_slave;
129 u8 delta_min_vfe_equ_idx;
130 u8 delta_max_vfe_equ_idx;
131 s32 offset_delta_min_uv;
132 s32 offset_delta_max_uv;
133};
134
135struct nv_pmu_volt_volt_policy_srms_boardobj_set {
136 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
137 u16 inter_switch_delayus;
138};
139
140/* sr - > single_rail */
141struct nv_pmu_volt_volt_policy_srss_boardobj_set {
142 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
143};
144
145union nv_pmu_volt_volt_policy_boardobj_set_union {
146 struct nv_pmu_boardobj board_obj;
147 struct nv_pmu_volt_volt_policy_boardobj_set super;
148 struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail;
149 struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set
150 single_rail_ms;
151 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail;
152 struct nv_pmu_volt_volt_policy_srms_boardobj_set
153 split_rail_m_s;
154 struct nv_pmu_volt_volt_policy_srss_boardobj_set
155 split_rail_s_s;
156};
157
158NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy);
159
160/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */
161struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header {
162 struct nv_pmu_boardobjgrp_e32 super;
163};
164
165struct nv_pmu_volt_volt_rail_boardobj_get_status {
166 struct nv_pmu_boardobj_query super;
167 u32 curr_volt_defaultu_v;
168 u32 rel_limitu_v;
169 u32 alt_rel_limitu_v;
170 u32 ov_limitu_v;
171 u32 max_limitu_v;
172 u32 vmin_limitu_v;
173 s32 volt_margin_limitu_v;
174 u32 rsvd;
175};
176
177union nv_pmu_volt_volt_rail_boardobj_get_status_union {
178 struct nv_pmu_boardobj_query board_obj;
179 struct nv_pmu_volt_volt_rail_boardobj_get_status super;
180};
181
182NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail);
183
184/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */
185struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header {
186 struct nv_pmu_boardobjgrp_e32 super;
187};
188
189struct nv_pmu_volt_volt_device_boardobj_get_status {
190 struct nv_pmu_boardobj_query super;
191};
192
193union nv_pmu_volt_volt_device_boardobj_get_status_union {
194 struct nv_pmu_boardobj_query board_obj;
195 struct nv_pmu_volt_volt_device_boardobj_get_status super;
196};
197
198NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device);
199
200/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */
201struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header {
202 struct nv_pmu_boardobjgrp_e32 super;
203};
204
205struct nv_pmu_volt_volt_policy_boardobj_get_status {
206 struct nv_pmu_boardobj_query super;
207 u32 offset_volt_requ_v;
208 u32 offset_volt_curru_v;
209};
210
211struct nv_pmu_volt_volt_policy_sr_boardobj_get_status {
212 struct nv_pmu_volt_volt_policy_boardobj_get_status super;
213 u32 curr_voltu_v;
214};
215
216struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status {
217 struct nv_pmu_volt_volt_policy_boardobj_get_status super;
218 s32 delta_minu_v;
219 s32 delta_maxu_v;
220 s32 orig_delta_minu_v;
221 s32 orig_delta_maxu_v;
222 u32 curr_volt_masteru_v;
223 u32 curr_volt_slaveu_v;
224 bool b_violation;
225};
226
227/* srms -> split_rail_multi_step */
228struct nv_pmu_volt_volt_policy_srms_boardobj_get_status {
229 struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
230};
231
232/* srss -> split_rail_single_step */
233struct nv_pmu_volt_volt_policy_srss_boardobj_get_status {
234 struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
235};
236
237union nv_pmu_volt_volt_policy_boardobj_get_status_union {
238 struct nv_pmu_boardobj_query board_obj;
239 struct nv_pmu_volt_volt_policy_boardobj_get_status super;
240 struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail;
241 struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail;
242 struct nv_pmu_volt_volt_policy_srms_boardobj_get_status
243 split_rail_m_s;
244 struct nv_pmu_volt_volt_policy_srss_boardobj_get_status
245 split_rail_s_s;
246};
247
248NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy);
249
250struct nv_pmu_volt_policy_voltage_data {
251 u8 policy_idx;
252 struct ctrl_perf_volt_rail_list
253 rail_list;
254};
255
256struct nv_pmu_volt_rail_get_voltage {
257 u8 rail_idx;
258 u32 voltage_uv;
259};
260
261struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin {
262 u8 num_rails;
263 struct ctrl_volt_volt_rail_list
264 rail_list;
265};
266
267#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000U)
268#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001U)
269#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U)
270#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004U)
271
272/*!
273* PMU VOLT RPC calls.
274*/
275#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000U)
276#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002U)
277#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003U)
278
279struct nv_pmu_volt_cmd_rpc {
280 u8 cmd_type;
281 u8 pad[3];
282 struct nv_pmu_allocation request;
283};
284
285#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \
286 offsetof(struct nv_pmu_volt_cmd_rpc, request)
287
288struct nv_pmu_volt_cmd {
289 union {
290 u8 cmd_type;
291 struct nv_pmu_boardobj_cmd_grp grp_set;
292 struct nv_pmu_volt_cmd_rpc rpc;
293 struct nv_pmu_boardobj_cmd_grp grp_get_status;
294 };
295};
296
297struct nv_pmu_volt_rpc {
298 u8 function;
299 bool b_supported;
300 bool b_success;
301 flcn_status flcn_status;
302 union {
303 struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
304 struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;
305 struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin
306 volt_rail_set_noise_unaware_vmin;
307 } params;
308};
309
310/*!
311* VOLT MSG ID definitions
312*/
313#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000U)
314#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001U)
315#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U)
316
317/*!
318* Message carrying the result of the VOLT RPC execution.
319*/
320struct nv_pmu_volt_msg_rpc {
321 u8 msg_type;
322 u8 rsvd[3];
323 struct nv_pmu_allocation response;
324};
325
326#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \
327 offsetof(struct nv_pmu_volt_msg_rpc, response)
328
329struct nv_pmu_volt_msg {
330 union {
331 u8 msg_type;
332 struct nv_pmu_boardobj_msg_grp grp_set;
333 struct nv_pmu_volt_msg_rpc rpc;
334 struct nv_pmu_boardobj_msg_grp grp_get_status;
335 };
336};
337
338#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2U)
339
340struct nv_pmu_volt_volt_rail_list {
341 u8 num_rails;
342 struct ctrl_perf_volt_rail_list_item
343 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
344};
345
346struct nv_pmu_volt_volt_rail_list_v1 {
347 u8 num_rails;
348 struct ctrl_volt_volt_rail_list_item_v1
349 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
350};
351
352/* VOLT RPC */
353#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U
354#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01U
355#define NV_PMU_RPC_ID_VOLT_LOAD 0x02U
356#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03U
357#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04U
358#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05U
359#define NV_PMU_RPC_ID_VOLT__COUNT 0x06U
360
361/*
362 * Defines the structure that holds data
363 * used to execute LOAD RPC.
364 */
365struct nv_pmu_rpc_struct_volt_load {
366 /*[IN/OUT] Must be first field in RPC structure */
367 struct nv_pmu_rpc_header hdr;
368 u32 scratch[1];
369};
370
371/*
372 * Defines the structure that holds data
373 * used to execute VOLT_SET_VOLTAGE RPC.
374 */
375struct nv_pmu_rpc_struct_volt_volt_set_voltage {
376 /*[IN/OUT] Must be first field in RPC structure */
377 struct nv_pmu_rpc_header hdr;
378 /*[IN] ID of the client that wants to set the voltage */
379 u8 client_id;
380 /*
381 * [IN] The list containing target voltage and
382 * noise-unaware Vmin value for the VOLT_RAILs.
383 */
384 struct ctrl_volt_volt_rail_list_v1 rail_list;
385 u32 scratch[1];
386};
387
388/*
389 * Defines the structure that holds data
390 * used to execute VOLT_RAIL_GET_VOLTAGE RPC.
391 */
392struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage {
393 /*[IN/OUT] Must be first field in RPC structure */
394 struct nv_pmu_rpc_header hdr;
395 /* [OUT] Current voltage in uv */
396 u32 voltage_uv;
397 /* [IN] Voltage Rail Table Index */
398 u8 rail_idx;
399 u32 scratch[1];
400};
401
402#endif /* NVGPU_PMUIF_GPMUIFVOLT_H*/
diff --git a/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
new file mode 100644
index 0000000..ce55f67
--- /dev/null
+++ b/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
@@ -0,0 +1,143 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H
23#define NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H
24
25#include <nvgpu/flcnif_cmn.h>
26#include "gpmuif_cmn.h"
27#include "gpmuif_pmu.h"
28#include "gpmuif_ap.h"
29#include "gpmuif_pg.h"
30#include "gpmuif_perfmon.h"
31#include "gpmuif_acr.h"
32#include "gpmuifboardobj.h"
33#include "gpmuifclk.h"
34#include "gpmuifperf.h"
35#include "gpmuifperfvfe.h"
36#include "gpmuifpmgr.h"
37#include "gpmuifvolt.h"
38#include "gpmuiftherm.h"
39#include "gpmuifthermsensor.h"
40#include "gpmuifseq.h"
41#include "gpmu_super_surf_if.h"
42
43/*
44 * Command requesting execution of the RPC (Remote Procedure Call)
45 */
46struct nv_pmu_rpc_cmd {
47 /* Must be set to @ref NV_PMU_RPC_CMD_ID */
48 u8 cmd_type;
49 /* RPC call flags (@see PMU_RPC_FLAGS) */
50 u8 flags;
51 /* Size of RPC structure allocated
52 * within NV managed DMEM heap
53 */
54 u16 rpc_dmem_size;
55 /*
56 * DMEM pointer of RPC structure allocated
57 * within RM managed DMEM heap.
58 */
59 u32 rpc_dmem_ptr;
60};
61
62#define NV_PMU_RPC_CMD_ID 0x80U
63
64/* Message carrying the result of the RPC execution */
65struct nv_pmu_rpc_msg {
66 /* Must be set to @ref NV_PMU_RPC_MSG_ID */
67 u8 msg_type;
68 /* RPC call flags (@see PMU_RPC_FLAGS)*/
69 u8 flags;
70 /*
71 * Size of RPC structure allocated
72 * within NV managed DMEM heap.
73 */
74 u16 rpc_dmem_size;
75 /*
76 * DMEM pointer of RPC structure allocated
77 * within NV managed DMEM heap.
78 */
79 u32 rpc_dmem_ptr;
80};
81
82#define NV_PMU_RPC_MSG_ID 0x80U
83
84struct pmu_cmd {
85 struct pmu_hdr hdr;
86 union {
87 struct pmu_perfmon_cmd perfmon;
88 struct pmu_pg_cmd pg;
89 struct pmu_zbc_cmd zbc;
90 struct pmu_acr_cmd acr;
91 struct nv_pmu_boardobj_cmd boardobj;
92 struct nv_pmu_perf_cmd perf;
93 struct nv_pmu_volt_cmd volt;
94 struct nv_pmu_clk_cmd clk;
95 struct nv_pmu_pmgr_cmd pmgr;
96 struct nv_pmu_therm_cmd therm;
97 struct nv_pmu_rpc_cmd rpc;
98 } cmd;
99};
100
101struct pmu_msg {
102 struct pmu_hdr hdr;
103 union {
104 struct pmu_init_msg init;
105 struct pmu_perfmon_msg perfmon;
106 struct pmu_pg_msg pg;
107 struct pmu_rc_msg rc;
108 struct pmu_acr_msg acr;
109 struct nv_pmu_boardobj_msg boardobj;
110 struct nv_pmu_perf_msg perf;
111 struct nv_pmu_volt_msg volt;
112 struct nv_pmu_clk_msg clk;
113 struct nv_pmu_pmgr_msg pmgr;
114 struct nv_pmu_therm_msg therm;
115 struct nv_pmu_rpc_msg rpc;
116 } msg;
117};
118
119#define PMU_UNIT_REWIND (0x00U)
120#define PMU_UNIT_PG (0x03U)
121#define PMU_UNIT_INIT (0x07U)
122#define PMU_UNIT_ACR (0x0AU)
123#define PMU_UNIT_PERFMON_T18X (0x11U)
124#define PMU_UNIT_PERFMON (0x12U)
125#define PMU_UNIT_PERF (0x13U)
126#define PMU_UNIT_RC (0x1FU)
127#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1EU)
128#define PMU_UNIT_CLK (0x0DU)
129#define PMU_UNIT_THERM (0x14U)
130#define PMU_UNIT_PMGR (0x18U)
131#define PMU_UNIT_VOLT (0x0EU)
132
133#define PMU_UNIT_END (0x23U)
134#define PMU_UNIT_INVALID (0xFFU)
135
136#define PMU_UNIT_TEST_START (0xFEU)
137#define PMU_UNIT_END_SIM (0xFFU)
138#define PMU_UNIT_TEST_END (0xFFU)
139
140#define PMU_UNIT_ID_IS_VALID(id) \
141 (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))
142
143#endif /* NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2026-11-10 10:20:23 -0500