diff options
Diffstat (limited to 'include/nvgpu/pmuif/gpmu_super_surf_if.h')
-rw-r--r-- | include/nvgpu/pmuif/gpmu_super_surf_if.h | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/include/nvgpu/pmuif/gpmu_super_surf_if.h b/include/nvgpu/pmuif/gpmu_super_surf_if.h new file mode 100644 index 0000000..b0f9e10 --- /dev/null +++ b/include/nvgpu/pmuif/gpmu_super_surf_if.h | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H | ||
23 | #define NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H | ||
24 | |||
25 | struct nv_pmu_super_surface_hdr { | ||
26 | u32 memberMask; | ||
27 | u16 dmemBufferSizeMax; | ||
28 | }; | ||
29 | |||
30 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr, | ||
31 | sizeof(struct nv_pmu_super_surface_hdr)); | ||
32 | |||
33 | /* | ||
34 | * Global Super Surface structure for combined INIT data required by PMU. | ||
35 | * NOTE: Any new substructures or entries must be aligned. | ||
36 | */ | ||
37 | struct nv_pmu_super_surface { | ||
38 | union nv_pmu_super_surface_hdr_aligned hdr; | ||
39 | |||
40 | struct { | ||
41 | struct nv_pmu_volt_volt_device_boardobj_grp_set volt_device_grp_set; | ||
42 | struct nv_pmu_volt_volt_policy_boardobj_grp_set volt_policy_grp_set; | ||
43 | struct nv_pmu_volt_volt_rail_boardobj_grp_set volt_rail_grp_set; | ||
44 | |||
45 | struct nv_pmu_volt_volt_policy_boardobj_grp_get_status volt_policy_grp_get_status; | ||
46 | struct nv_pmu_volt_volt_rail_boardobj_grp_get_status volt_rail_grp_get_status; | ||
47 | struct nv_pmu_volt_volt_device_boardobj_grp_get_status volt_device_grp_get_status; | ||
48 | } volt; | ||
49 | struct { | ||
50 | struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set; | ||
51 | struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set; | ||
52 | struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set; | ||
53 | u8 clk_rsvd2[0x200]; | ||
54 | struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set; | ||
55 | struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set; | ||
56 | struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set; | ||
57 | struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status; | ||
58 | struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status; | ||
59 | struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status; | ||
60 | u8 clk_rsvd[0x4660]; | ||
61 | } clk; | ||
62 | struct { | ||
63 | struct nv_pmu_perf_vfe_equ_boardobj_grp_set vfe_equ_grp_set; | ||
64 | struct nv_pmu_perf_vfe_var_boardobj_grp_set vfe_var_grp_set; | ||
65 | |||
66 | struct nv_pmu_perf_vfe_var_boardobj_grp_get_status vfe_var_grp_get_status; | ||
67 | u8 perf_rsvd[0x40790]; | ||
68 | u8 perfcf_rsvd[0x1eb0]; | ||
69 | } perf; | ||
70 | struct { | ||
71 | struct nv_pmu_therm_therm_channel_boardobj_grp_set therm_channel_grp_set; | ||
72 | struct nv_pmu_therm_therm_device_boardobj_grp_set therm_device_grp_set; | ||
73 | u8 therm_rsvd[0x1460]; | ||
74 | } therm; | ||
75 | }; | ||
76 | |||
77 | #endif /* NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H */ | ||