Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

19 files changed, 4084 insertions, 0 deletions

diff --git a/include/nvgpu/pmuif/gpmu_super_surf_if.h b/include/nvgpu/pmuif/gpmu_super_surf_if.h
new file mode 100644
index 0000000..b0f9e10
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmu_super_surf_if.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
+#define NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
+
+struct nv_pmu_super_surface_hdr {
+    u32 memberMask;
+    u16 dmemBufferSizeMax;
+};
+
+NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr,
+                sizeof(struct nv_pmu_super_surface_hdr));
+
+/*
+ * Global Super Surface structure for combined INIT data required by PMU.
+ * NOTE: Any new substructures or entries must be aligned.
+ */
+struct nv_pmu_super_surface {
+        union nv_pmu_super_surface_hdr_aligned hdr;
+
+        struct {
+                struct nv_pmu_volt_volt_device_boardobj_grp_set volt_device_grp_set;
+                struct nv_pmu_volt_volt_policy_boardobj_grp_set volt_policy_grp_set;
+                struct nv_pmu_volt_volt_rail_boardobj_grp_set volt_rail_grp_set;
+
+                struct nv_pmu_volt_volt_policy_boardobj_grp_get_status  volt_policy_grp_get_status;
+                struct nv_pmu_volt_volt_rail_boardobj_grp_get_status    volt_rail_grp_get_status;
+                struct nv_pmu_volt_volt_device_boardobj_grp_get_status  volt_device_grp_get_status;
+        } volt;
+        struct  {
+                struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set;
+                struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set;
+                struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set;
+                u8 clk_rsvd2[0x200];
+                struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set;
+                struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set;
+                struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set;
+                struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status;
+                struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status;
+                struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status;
+                u8 clk_rsvd[0x4660];
+        } clk;
+        struct {
+                struct nv_pmu_perf_vfe_equ_boardobj_grp_set vfe_equ_grp_set;
+                struct nv_pmu_perf_vfe_var_boardobj_grp_set vfe_var_grp_set;
+
+                struct nv_pmu_perf_vfe_var_boardobj_grp_get_status vfe_var_grp_get_status;
+                u8 perf_rsvd[0x40790];
+                u8 perfcf_rsvd[0x1eb0];
+        } perf;
+        struct {
+                struct nv_pmu_therm_therm_channel_boardobj_grp_set therm_channel_grp_set;
+                struct nv_pmu_therm_therm_device_boardobj_grp_set therm_device_grp_set;
+                u8 therm_rsvd[0x1460];
+        } therm;
+};
+
+#endif /* NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H */
diff --git a/include/nvgpu/pmuif/gpmuif_acr.h b/include/nvgpu/pmuif/gpmuif_acr.h
new file mode 100644
index 0000000..c305589
--- /dev/null
+++ b/include/nvgpu/pmuif/gpmuif_acr.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PMUIF_GPMUIF_ACR_H
+#define NVGPU_PMUIF_GPMUIF_ACR_H
+
+/* ACR Commands/Message structures */
+
+enum {
+        PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0,
+        PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
+        PMU_ACR_CMD_ID_RESERVED,
+        PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
+};
+
+/*
+ * Initializes the WPR region details
+ */
+struct pmu_acr_cmd_init_wpr_details {
+        u8  cmd_type;
+        u32 regionid;
+        u32 wproffset;
+
+};
+
+/*
+ * falcon ID to bootstrap
+ */
+struct pmu_acr_cmd_bootstrap_falcon {
+        u8 cmd_type;
+        u32 flags;
+        u32 falconid;
+};
+
+/*
+ * falcon ID to bootstrap
+ */
+struct pmu_acr_cmd_bootstrap_multiple_falcons {
+        u8 cmd_type;
+        u32 flags;
+        u32 falconidmask;
+        u32 usevamask;
+        struct falc_u64 wprvirtualbase;
+};
+
+#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO  1
+#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
+
+
+struct pmu_acr_cmd {
+        union {
+                u8 cmd_type;
+                struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
+                struct pmu_acr_cmd_init_wpr_details init_wpr;
+                struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
+        };
+};
+
+/* acr messages */
+
+/*
+ * returns the WPR region init information
+ */
+#define PMU_ACR_MSG_ID_INIT_WPR_REGION   0
+
+/*
+ * Returns the Bootstrapped falcon ID to RM
+ */
+#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON  1
+
+/*
+ * Returns the WPR init status
+ */
+#define PMU_ACR_SUCCESS                  0
+#define PMU_ACR_ERROR                    1
+
+/*
+ * PMU notifies about bootstrap status of falcon
+ */
+struct pmu_acr_msg_bootstrap_falcon {
+        u8 msg_type;
+        union {
+                u32 errorcode;