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* Merge branch 'for-3.7/common-clk' into for-3.7/cleanup2Stephen Warren2012-09-14
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| * ARM: Tegra: Add smp_twd clock for Tegra20Prashant Gaikwad2012-09-13
| | | | | | | | | | | | | | | | | | | | Clockevent's frequency is changed upon cpufreq change notification. It fetches local timer's rate to update the clockevent frequency. This patch adds local timer clock for Tegra20. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: cpu-tegra: explicitly manage re-parentingStephen Warren2012-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When changing a PLL's rate, it must have no active children. The CPU clock cannot be stopped, and CPU clock's divider is not used. The old clock driver used to handle this by internally reparenting the CPU clock onto a different PLL when changing the CPU clock rate. However, the new common-clock based clock driver does not do this, and probably cannot do this due to the locking issues it would cause. To solve this, have the Tegra cpufreq driver explicitly perform the reparenting operations itself. This is probably reasonable anyway, since such reparenting is somewhat a matter of policy (e.g. which alternate clock source to use, whether to leave the CPU clock a child of the alternate clock source if it's running at the desired rate), and hence is something more appropriate for the cpufreq driver than the core clock driver anyway. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()Stephen Warren2012-09-11
| | | | | | | | | | | | | | | | 32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000. Use 64-bit math to prevent this. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Fix data type for io addressPrashant Gaikwad2012-09-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Warnings were generated because following commit changed data type for address pointer 195bbca ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors arch/arm/mach-tegra/tegra30_clocks.c: In function 'clk_measure_input_freq': arch/arm/mach-tegra/tegra30_clocks.c:418:2: warning: passing argument 2 of '__raw_writel' makes pointer from integer without a cast .../arch/arm/include/asm/io.h:88:20: note: expected 'volatile void *' but argument is of type 'unsigned int Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: remove tegra_timer from tegra_list_clksStephen Warren2012-09-06
| | | | | | | | | | | | | | tegra_time is a struct sys_timer, not a struct clk, so can't be included in an array of struct clk *. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops nameJoseph Lo2012-09-06
| | | | | | | | | | | | | | | | | | | | It should use tegra30_audio_sync_clk_ops for tegra30. It will cause the tegra30 use the wrong audio_sync_clk_ops when build a kernel with a tegra20 and tegra30 both supported kernel. And building error when a tegra30-only kernel. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30Joseph Lo2012-09-06
| | | | | | | | | | | | | | | | | | | | Currently the tegra20 and tegra30 share the same symbol for tegra_clk_32k_ops. This will cause a compile error when building a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and modify tegra30_clk_32k_ops for tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Remove duplicate codePrashant Gaikwad2012-09-06
| | | | | | | | | | | | | | Remove Tegra legacy clock framework code. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Port tegra to generic clock frameworkPrashant Gaikwad2012-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch converts tegra clock code to generic clock framework in following way: - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c) - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk. - Initialize all clock data statically. (tegraXX_clocks_data.c) Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions. Removed init function. It's functionality is splitted into recalc_rate and is_enabled. Static initialization is used since slab is not up in .init_early and clock is needed to be initialized before clockevent/clocksource initialization. Macros redefined for clk_tegra. Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This is to move quickly to generic common clock framework so that other dependent features will not be blocked (such as DT binding). Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20 and Tegra30. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Add clk_tegra structure and helper functionsPrashant Gaikwad2012-09-06
| | | | | | | | | | | | | | | | | | | | | | Add Tegra platform specific clock structure clk_tegra and some helper functions for generic clock framework. struct clk_tegra is the single strcture used for all types of clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Rename tegra20 clock filePrashant Gaikwad2012-09-06
| | | | | | | | | | | | | | | | Make the name consistent with other files. s/tegra2/tegra20 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra20: Separate out clk ops and clk dataPrashant Gaikwad2012-09-06
| | | | | | | | | | | | | | | | | | Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra30: Separate out clk ops and clk dataPrashant Gaikwad2012-09-06
| | | | | | | | | | | | | | | | | | Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix U16 divider range checkStephen Warren2012-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A U16 divider can divide a clock by 1..64K. However, the range-check in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check. In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: turn on UART A clock at bootStephen Warren2012-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | Some boards use UART D for the main serial console, and some use UART A. UART D's clock is listed in board-dt-tegra20.c's clock table, whereas UART A's clock is not. This causes the clock code to think UART A's clock is unsed. The common clock framework turns off unused clocks at boot time. This makes the kernel appear to hang. Add UART A's clock into the clock table to prevent this. Eventually, this requirement should be handled by the UART driver, and/or properties in a board-specific device tree file. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'for-3.7/board-removal' into for-3.7/cleanup2Stephen Warren2012-09-14
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| * | ARM: dt: tegra: harmony: configure power offStephen Warren2012-09-14
| | | | | | | | | | | | | | | | | | | | | Add DT property to tell the TPS6586x that it should provide the pm_power_off() implementation. This allows "shutdown" to work. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: dt: tegra: harmony: add regulatorsLaxman Dewangan2012-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Harmony uses a TPS6586x regulator. Instantiate this, and hook up a couple of fixed GPIO-controlled regulators too. Based on Ventana regulator patch by Stephen Warren <swarren@nvidia.com> and converted to Harmony. swarren made the following changes: * Added ldo0 regulator configuration to device tree, and updated board-harmony-pcie.c for the new regulator name. * Fixed vdd_1v05's voltage from 10.5V to 1.05V. * Modified board-harmony-pcie.c to obtain the en_vdd_1v05 GPIO number at run-time from device tree instead of hard-coding it. * Removed board-harmony{-power.c,.h} now that they're unused. * Disabled vdd_1v05 regulator; the code in board-harmony-pcie.c hijacks this GPIO for now. This will be fixed when the PCIe driver is re- written as a driver. The code can't regulator_get("vdd_1v05") right now, because the vdd_1v05 regulator's probe gets deferred due to its supply being the PMIC, which gets probed after the regulator the first time around, and this dependency is only resolved by repeated probing, which happens when deferred_probe_initcall() is called, which happens in a late initcall, whose runtime order relative to harmony_pcie_init() is undefined, since that's also called from a late initcall. * Removed unused harmony_pcie_initcall(). Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: remove board (but not DT) support for HarmonyStephen Warren2012-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Harmony can be booted using device tree with equal functionality as when booted using a board file. Remove as much of the board file as is possible, since it's no longer needed. Two special-cases are still left in board-dt-tegra20.c, since the Tegra PCIe driver doesn't support device tree yet, and the Harmony .dts file doesn't yet describe regulators which are needed for PCIe. This logic is now enabled unconditionally rather than via CONFIG_MACH_HARMONY. While this is more code than other boards, it's still unlikely to be much of a problem, and both regulators and PCIe should be supported via device tree in the near future, allowing the remaining code to be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: remove board (but not DT) support for Paz00Stephen Warren2012-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Paz00 (Toshiba AC100) can be booted using device tree with equal functionality as when booted using a board file. Remove as much of the board file as is possible, since it's no longer needed. One special-case is still left in board-dt-tegra20.c, since there is no way to create a WiFi rfkill device from device tree yet. This logic is now enabled unconditionally rather than via CONFIG_MACH_PAZ00. The extra cases where it's enabled (.configs which did not enable Paz00 support) shouldn't impact much since the amount of code is tiny. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Marc Dietrich <marvin24@gmx.de>
| * | ARM: tegra: remove board (but not DT) support for TrimSliceStephen Warren2012-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TrimSlice can be booted using device tree with equal functionality as when booted using a board file. Remove the board file since it's no longer needed. One special-case is still left in board-dt-tegra20.c, since the Tegra PCIe driver doesn't support device tree yet. This logic is now enabled by CONFIG_TEGRA_PCI rather than via CONFIG_MACH_TRIMSLICE. The extra cases where it's enabled (.configs which did not enable TrimSlice support) shouldn't impact much since the amount of code is tiny. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | Merge commit 'tps6589x-dt' into for-3.7/board-removalStephen Warren2012-09-14
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| | * regulator: tps6586x: add support for SYS railLaxman Dewangan2012-09-05
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Device have SYS rail which is always ON. It is system power bus. LDO5 and LDO_RTC get powered through this rail internally. Add support for this rail and make the LDO5/LDO_RTC supply by it. Update document accordingly. [swarren: Instantiate the sys regulator from board-harmony-power.c to avoid regression.] Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | mmc: tegra: remove useless include of <mach/*.h>Stephen Warren2012-09-06
| | | | | | | | | | | | | | | | | | Nothing from this file is needed, so remove the include. This helps single zImage work by reducing use of the mach-tegra/include/mach/ directory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Chris Ball <cjb@laptop.org>
* | gpio: tegra: remove useless includes of <mach/*.h>Stephen Warren2012-09-06
| | | | | | | | | | | | | | | | | | Nothing from these files is needed, so remove the includes. This helps single zImage work by reducing use of the mach-tegra/include/mach/ directory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: tegra: remove duplicate select USE_OFStephen Warren2012-09-06
| | | | | | | | | | | | | | ARCH_TEGRA (arch/arm/Kconfig) now selects USE_OF, so there's not need for ARCH_TEGRA_3x_SOC to do so too. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: use IO_ADDRESS for getting virtual addressLaxman Dewangan2012-09-06
|/ | | | | | | | | | | Use macro IO_ADDRESS for getting virtual address of corresponding physical address to make the consistency with rest of Tegra code-base. This macro calls the IO_TO_VIRT() which is defined in arch/arm/mach-tegra/include/mach/iomap.h Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Linux 3.6-rc4Linus Torvalds2012-09-01
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* time: Move ktime_t overflow checking into timespec_valid_strictJohn Stultz2012-09-01
| | | | | | | | | | | | | | | | | | | | | | | Andreas Bombe reported that the added ktime_t overflow checking added to timespec_valid in commit 4e8b14526ca7 ("time: Improve sanity checking of timekeeping inputs") was causing problems with X.org because it caused timeouts larger then KTIME_T to be invalid. Previously, these large timeouts would be clamped to KTIME_MAX and would never expire, which is valid. This patch splits the ktime_t overflow checking into a new timespec_valid_strict function, and converts the timekeeping codes internal checking to use this more strict function. Reported-and-tested-by: Andreas Bombe <aeb@debian.org> Cc: Zhouping Liu <zliu@redhat.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Prarit Bhargava <prarit@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2012-08-31
|\ | | | | | | | | | | | | | | Pull KVM bugfixes from Marcelo Tosatti. * git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: fix KVM_GET_MSR for PV EOI kvm: Fix nonsense handling of compat ioctl
| * KVM: x86: fix KVM_GET_MSR for PV EOIMichael S. Tsirkin2012-08-27
| | | | | | | | | | | | | | | | KVM_GET_MSR was missing support for PV EOI, which is needed for migration. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
| * kvm: Fix nonsense handling of compat ioctlAlan Cox2012-08-26
| | | | | | | | | | | | | | | | | | | | | | KVM_SET_SIGNAL_MASK passed a NULL argument leaves the on stack signal sets uninitialized. It then passes them through to kvm_vcpu_ioctl_set_sigmask. We should be passing a NULL in this case not translated garbage. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* | Merge tag 'parisc-fixes' of ↵Linus Torvalds2012-08-31
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6 Pull PARISC fixes from James Bottomley: "This is a set of two bug fixes. One is the ATOMIC problem which is now causing a compile failure in certain situations. The other is mishandling of PER_LINUX32 which may also cause user visible effects. Signed-off-by: James Bottomley <JBottomley@Parallels.com>" * tag 'parisc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6: [PARISC] fix personality flag check in copy_thread() [PARISC] Redefine ATOMIC_INIT and ATOMIC64_INIT to drop the casts
| * | [PARISC] fix personality flag check in copy_thread()Jiri Kosina2012-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directly comparing task_struct->personality against PER_* is not fully correct, as it doesn't take flags potentially stored in top three bytes into account. Analogically, directly forcefully setting personality to PER_LINUX32 or PER_LINUX discards any flags stored in the top three bytes. Signed-off-by: Jiri Kosina <jkosina@suse.cz> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
| * | [PARISC] Redefine ATOMIC_INIT and ATOMIC64_INIT to drop the castsMel Gorman2012-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following build error occured during a parisc build with swap-over-NFS patches applied. net/core/sock.c:274:36: error: initializer element is not constant net/core/sock.c:274:36: error: (near initialization for 'memalloc_socks') net/core/sock.c:274:36: error: initializer element is not constant Dave Anglin says: > Here is the line in sock.i: > > struct static_key memalloc_socks = ((struct static_key) { .enabled = > ((atomic_t) { (0) }) }); The above line contains two compound literals. It also uses a designated initializer to initialize the field enabled. A compound literal is not a constant expression. The location of the above statement isn't fully clear, but if a compound literal occurs outside the body of a function, the initializer list must consist of constant expressions. Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Mel Gorman <mgorman@suse.de> Cc: <stable@vger.kernel.org> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
* | | Merge branch 'for-linus' of ↵Linus Torvalds2012-08-31
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux Pull s390 fixes from Martin Schwidefsky: "A couple of s390 bug fixes for 3.5-rc4" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390/32: Don't clobber personality flags on exec s390/smp: add missing smp_store_status() for !SMP s390/dasd: fix ioctl return value s390: Always use "long" for ssize_t to match size_t
| * | | s390/32: Don't clobber personality flags on execHeiko Carstens2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In native 32 bit mode the personality flags were not correctly inherited. This is the s390 version of 59e4c3a2 "powerpc/32: Don't clobber personality flags on exec". Reported-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| * | | s390/smp: add missing smp_store_status() for !SMPHeiko Carstens2012-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix this compile error: arch/s390/kernel/machine_kexec.c: In function ‘setup_regs’: arch/s390/kernel/machine_kexec.c:63:3: error: implicit declaration of function ‘smp_store_status’ [-Werror=implicit-function-declaration] Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| * | | s390/dasd: fix ioctl return valueHeiko Carstens2012-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For unimplemented ioctls the dasd driver should return -ENOTTY. Reported-by: Wanlong Gao <gaowanlong@cn.fujitsu.com> Acked-by: Stefan Weinhuber <wein@de.ibm.com> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
| * | | s390: Always use "long" for ssize_t to match size_tGeert Uytterhoeven2012-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On s390x-linux-gcc, __SIZE_TYPE__ expands to "long unsigned int" for both 32-bit s390 and 64-bit s390x, as gcc-4.6.3-nolibc/s390x-linux/lib/gcc/s390x-linux/4.6.3/plugin/include/config/s390/linux.h has #define SIZE_TYPE (TARGET_64BIT ? "long unsigned int" : "long unsigned int") To match this, __kernel_size_t is always set to "long unsigned int". But while __kernel_ssize_t is "long" on 64-bit s390x, it is "int" on 32-bit s390, causing compiler warnings like: fs/quota/quota_tree.c:372:4: warning: format '%zd' expects argument of type 'signed size_t', but argument 4 has type 'ssize_t' [-Wformat] To fix this, __kernel_ssize_t should be "long", irrespective of word size. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* | | | Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2012-08-30
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm fixes from Dave Airlie: "A bunch of scattered fixes ati/intel/nouveau, couple of core ones, nothing too shocking or different." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222S gma500: Consider CRTC initially active. drm/radeon: fix dig encoder selection on DCE61 drm/radeon: fix double free in radeon_gpu_reset drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740 drm/radeon: rework panel mode setup drm/radeon/atom: powergating fixes for DCE6 drm/radeon/atom: rework DIG modesetting on DCE3+ drm/radeon: don't disable plls that are in use by other crtcs drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 drm/radeon: initialize tracked CS state drm/radeon: fix reading CB_COLORn_MASK from the CS drm/nvc0/copy: check PUNITS to determine which copy engines are disabled i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard drm/i915: Use the correct size of the GTT for placing the per-process entries drm: Check for invalid cursor flags drm: Initialize object type when using DRM_MODE() macro drm/i915: fix color order for BGR formats on IVB drm/i915: fix wrong order of parameters in port checking functions
| * | | | drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222SPaul Menzel2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Connecting an ASUS VW222S [1] over VGA a garbled screen is shown with vertical stripes in the top half. In commit bc42aabc [2] commit bc42aabc6a01b92b0f961d65671564e0e1cd7592 Author: Adam Jackson <ajax@redhat.com> Date: Wed May 23 16:26:54 2012 -0400 drm/edid/quirks: ViewSonic VA2026w Adam Jackson added the quirk `EDID_QUIRK_FORCE_REDUCED_BLANKING` which is also needed for this ASUS monitor. All log files and output from `xrandr` is included in the referenced Bugzilla report #17629. Please note that this monitor only has a VGA (D-Sub) connector [1]. [1] http://www.asus.com/Display/LCD_Monitors/VW222S/ [2] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=bc42aabc6a01b92b0f961d65671564e0e1cd7592 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=17629 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Cc: <dri-devel@lists.freedesktop.org> Cc: Adam Jackson <ajax@redhat.com> Cc: Ian Pilcher <arequipeno@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | | Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2012-08-29
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-fixes Alex writes: Highlights: - fix a gart regression on older IGP chips - more MSAA fixes - fix a double free in gpu reset code - modesetting fixes - trinity dig encoder fix. * 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: fix dig encoder selection on DCE61 drm/radeon: fix double free in radeon_gpu_reset drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740 drm/radeon: rework panel mode setup drm/radeon/atom: powergating fixes for DCE6 drm/radeon/atom: rework DIG modesetting on DCE3+ drm/radeon: don't disable plls that are in use by other crtcs drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 drm/radeon: initialize tracked CS state drm/radeon: fix reading CB_COLORn_MASK from the CS
| | * | | | drm/radeon: fix dig encoder selection on DCE61Alex Deucher2012-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Was using the DCE41 code which was wrong. Fixes blank displays on a number of Trinity systems. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | * | | | drm/radeon: fix double free in radeon_gpu_resetChristian König2012-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | radeon_ring_restore is freeing the memory for the saved ring data. We need to remember that, otherwise we try to restore the ring data again on the next try. Additional to that it shouldn't try the reset infinitely if we have saved ring data. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | | drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740Jerome Glisse2012-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems some of those IGP dislike non dma32 page despite what documentation says. Fix regression since we allowed non dma32 pages. It seems it only affect some revision of those IGP chips as we don't know which one just force dma32 for all of them. https://bugzilla.redhat.com/show_bug.cgi?id=785375 Signed-off-by: Jerome Glisse <jglisse@redhat.com> Cc: <stable@vger.kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | | drm/radeon: rework panel mode setupAlex Deucher2012-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the panel mode setup to match the behavior of the vbios. Rather than checking for specific bridge chip ids, just check the eDP configuration register. This saves extra aux transactions and works across DP bridge chips without requiring additional per chip id checking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | | drm/radeon/atom: powergating fixes for DCE6Alex Deucher2012-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power gating is per crtc pair, but the powergating registers should be called individually. The hw handles power up/down properly. The pair is powered up if either crtc in the pair is powered up and the pair is not powered down until both crtcs in the pair are powered down. This simplifies programming and should save additional power as the previous code never actually power gated the crtc pair. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | * | | | drm/radeon/atom: rework DIG modesetting on DCE3+Alex Deucher2012-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ordering is important and the current drm code wasn't cutting it for modern DIG encoders. We need to have information about crtc before setting up the encoders so I've shifted the ordering a bit. Probably we'll need a full rework akin to danvet's recent intel patchs. This patch fixes numerous issues with DP bridge chips and makes link training much more reliable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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