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authorPrashant Gaikwad <pgaikwad@nvidia.com>2012-08-06 02:27:40 -0400
committerStephen Warren <swarren@nvidia.com>2012-09-06 13:47:19 -0400
commit86edb87acbbdbddf62ad7b1c713891accb4dab33 (patch)
tree902b8e3431ddc3d0aa5072ea85f5a4c070763ed0
parent88e790a445b35cf137a62e590ced5315defad060 (diff)
ARM: tegra20: Separate out clk ops and clk data
Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat
-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.h37
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c941
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c1058
4 files changed, 995 insertions, 1042 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0b62a9b7297a..655fcfc4f12e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,6 +13,7 @@ obj-y += apbio.o
13obj-$(CONFIG_CPU_IDLE) += cpuidle.o 13obj-$(CONFIG_CPU_IDLE) += cpuidle.o
14obj-$(CONFIG_CPU_IDLE) += sleep.o 14obj-$(CONFIG_CPU_IDLE) += sleep.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o 19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 000000000000..167058c02e74
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,37 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA20_CLOCK_H
18#define __MACH_TEGRA20_CLOCK_H
19
20extern struct clk_ops tegra_pll_ops;
21extern struct clk_ops tegra_clk_m_ops;
22extern struct clk_ops tegra_pll_div_ops;
23extern struct clk_ops tegra_pllx_ops;
24extern struct clk_ops tegra_plle_ops;
25extern struct clk_ops tegra_clk_double_ops;
26extern struct clk_ops tegra_cdev_clk_ops;
27extern struct clk_ops tegra_audio_sync_clk_ops;
28extern struct clk_ops tegra_super_ops;
29extern struct clk_ops tegra_cpu_ops;
30extern struct clk_ops tegra_cop_ops;
31extern struct clk_ops tegra_bus_ops;
32extern struct clk_ops tegra_blink_clk_ops;
33extern struct clk_ops tegra_emc_clk_ops;
34extern struct clk_ops tegra_periph_clk_ops;
35extern struct clk_ops tegra_clk_shared_bus_ops;
36
37#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 000000000000..24f45ff516c3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,941 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/spinlock.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26#include <linux/clkdev.h>
27#include <linux/clk.h>
28
29#include <mach/iomap.h>
30#include <mach/suspend.h>
31
32#include "clock.h"
33#include "fuse.h"
34#include "tegra2_emc.h"
35#include "tegra20_clocks.h"
36
37/* Clock definitions */
38static struct clk tegra_clk_32k = {
39 .name = "clk_32k",
40 .rate = 32768,
41 .ops = NULL,
42 .max_rate = 32768,
43};
44
45static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
46 {32768, 12000000, 366, 1, 1, 0},
47 {32768, 13000000, 397, 1, 1, 0},
48 {32768, 19200000, 586, 1, 1, 0},
49 {32768, 26000000, 793, 1, 1, 0},
50 {0, 0, 0, 0, 0, 0},
51};
52
53static struct clk tegra_pll_s = {
54 .name = "pll_s",
55 .flags = PLL_ALT_MISC_REG,
56 .ops = &tegra_pll_ops,
57 .parent = &tegra_clk_32k,
58 .max_rate = 26000000,
59 .reg = 0xf0,
60 .u.pll = {
61 .input_min = 32768,
62 .input_max = 32768,
63 .cf_min = 0, /* FIXME */
64 .cf_max = 0, /* FIXME */
65 .vco_min = 12000000,
66 .vco_max = 26000000,
67 .freq_table = tegra_pll_s_freq_table,
68 .lock_delay = 300,
69 },
70};
71
72static struct clk_mux_sel tegra_clk_m_sel[] = {
73 { .input = &tegra_clk_32k, .value = 0},
74 { .input = &tegra_pll_s, .value = 1},
75 { NULL , 0},
76};
77
78static struct clk tegra_clk_m = {
79 .name = "clk_m",
80 .flags = ENABLE_ON_INIT,
81 .ops = &tegra_clk_m_ops,
82 .inputs = tegra_clk_m_sel,
83 .reg = 0x1fc,
84 .reg_shift = 28,
85 .max_rate = 26000000,
86};
87
88static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
89 { 12000000, 600000000, 600, 12, 1, 8 },
90 { 13000000, 600000000, 600, 13, 1, 8 },
91 { 19200000, 600000000, 500, 16, 1, 6 },
92 { 26000000, 600000000, 600, 26, 1, 8 },
93 { 0, 0, 0, 0, 0, 0 },
94};
95
96static struct clk tegra_pll_c = {
97 .name = "pll_c",
98 .flags = PLL_HAS_CPCON,
99 .ops = &tegra_pll_ops,
100 .reg = 0x80,
101 .parent = &tegra_clk_m,
102 .max_rate = 600000000,
103 .u.pll = {
104 .input_min = 2000000,
105 .input_max = 31000000,
106 .cf_min = 1000000,
107 .cf_max = 6000000,
108 .vco_min = 20000000,
109 .vco_max = 1400000000,
110 .freq_table = tegra_pll_c_freq_table,
111 .lock_delay = 300,
112 },
113};
114
115static struct clk tegra_pll_c_out1 = {
116 .name = "pll_c_out1",
117 .ops = &tegra_pll_div_ops,
118 .flags = DIV_U71,
119 .parent = &tegra_pll_c,
120 .reg = 0x84,
121 .reg_shift = 0,
122 .max_rate = 600000000,
123};
124
125static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
126 { 12000000, 666000000, 666, 12, 1, 8},
127 { 13000000, 666000000, 666, 13, 1, 8},
128 { 19200000, 666000000, 555, 16, 1, 8},
129 { 26000000, 666000000, 666, 26, 1, 8},
130 { 12000000, 600000000, 600, 12, 1, 8},
131 { 13000000, 600000000, 600, 13, 1, 8},
132 { 19200000, 600000000, 375, 12, 1, 6},
133 { 26000000, 600000000, 600, 26, 1, 8},
134 { 0, 0, 0, 0, 0, 0 },
135};
136
137static struct clk tegra_pll_m = {
138 .name = "pll_m",
139 .flags = PLL_HAS_CPCON,
140 .ops = &tegra_pll_ops,
141 .reg = 0x90,
142 .parent = &tegra_clk_m,
143 .max_rate = 800000000,
144 .u.pll = {
145 .input_min = 2000000,
146 .input_max = 31000000,
147 .cf_min = 1000000,
148 .cf_max = 6000000,
149 .vco_min = 20000000,
150 .vco_max = 1200000000,
151 .freq_table = tegra_pll_m_freq_table,
152 .lock_delay = 300,
153 },
154};
155
156static struct clk tegra_pll_m_out1 = {
157 .name = "pll_m_out1",
158 .ops = &tegra_pll_div_ops,
159 .flags = DIV_U71,
160 .parent = &tegra_pll_m,
161 .reg = 0x94,
162 .reg_shift = 0,
163 .max_rate = 600000000,
164};
165
166static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
167 { 12000000, 216000000, 432, 12, 2, 8},
168 { 13000000, 216000000, 432, 13, 2, 8},
169 { 19200000, 216000000, 90, 4, 2, 1},
170 { 26000000, 216000000, 432, 26, 2, 8},
171 { 12000000, 432000000, 432, 12, 1, 8},
172 { 13000000, 432000000, 432, 13, 1, 8},
173 { 19200000, 432000000, 90, 4, 1, 1},
174 { 26000000, 432000000, 432, 26, 1, 8},
175 { 0, 0, 0, 0, 0, 0 },
176};
177
178static struct clk tegra_pll_p = {
179 .name = "pll_p",
180 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
181 .ops = &tegra_pll_ops,
182 .reg = 0xa0,
183 .parent = &tegra_clk_m,
184 .max_rate = 432000000,
185 .u.pll = {
186 .input_min = 2000000,
187 .input_max = 31000000,
188 .cf_min = 1000000,
189 .cf_max = 6000000,
190 .vco_min = 20000000,
191 .vco_max = 1400000000,
192 .freq_table = tegra_pll_p_freq_table,
193 .lock_delay = 300,
194 },
195};
196
197static struct clk tegra_pll_p_out1 = {
198 .name = "pll_p_out1",
199 .ops = &tegra_pll_div_ops,
200 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
201 .parent = &tegra_pll_p,
202 .reg = 0xa4,
203 .reg_shift = 0,
204 .max_rate = 432000000,
205};
206
207static struct clk tegra_pll_p_out2 = {
208 .name = "pll_p_out2",
209 .ops = &tegra_pll_div_ops,
210 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
211 .parent = &tegra_pll_p,
212 .reg = 0xa4,
213 .reg_shift = 16,
214 .max_rate = 432000000,
215};
216
217static struct clk tegra_pll_p_out3 = {
218 .name = "pll_p_out3",
219 .ops = &tegra_pll_div_ops,
220 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
221 .parent = &tegra_pll_p,
222 .reg = 0xa8,
223 .reg_shift = 0,
224 .max_rate = 432000000,
225};
226
227static struct clk tegra_pll_p_out4 = {
228 .name = "pll_p_out4",
229 .ops = &tegra_pll_div_ops,
230 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
231 .parent = &tegra_pll_p,
232 .reg = 0xa8,
233 .reg_shift = 16,
234 .max_rate = 432000000,
235};
236
237static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
238 { 28800000, 56448000, 49, 25, 1, 1},
239 { 28800000, 73728000, 64, 25, 1, 1},
240 { 28800000, 24000000, 5, 6, 1, 1},
241 { 0, 0, 0, 0, 0, 0 },
242};
243
244static struct clk tegra_pll_a = {
245 .name = "pll_a",
246 .flags = PLL_HAS_CPCON,
247 .ops = &tegra_pll_ops,
248 .reg = 0xb0,
249 .parent = &tegra_pll_p_out1,
250 .max_rate = 73728000,
251 .u.pll = {
252 .input_min = 2000000,
253 .input_max = 31000000,
254 .cf_min = 1000000,
255 .cf_max = 6000000,
256 .vco_min = 20000000,
257 .vco_max = 1400000000,
258 .freq_table = tegra_pll_a_freq_table,
259 .lock_delay = 300,
260 },
261};
262
263static struct clk tegra_pll_a_out0 = {
264 .name = "pll_a_out0",
265 .ops = &tegra_pll_div_ops,
266 .flags = DIV_U71,
267 .parent = &tegra_pll_a,
268 .reg = 0xb4,
269 .reg_shift = 0,
270 .max_rate = 73728000,
271};
272
273static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
274 { 12000000, 216000000, 216, 12, 1, 4},
275 { 13000000, 216000000, 216, 13, 1, 4},
276 { 19200000, 216000000, 135, 12, 1, 3},
277 { 26000000, 216000000, 216, 26, 1, 4},
278
279 { 12000000, 594000000, 594, 12, 1, 8},
280 { 13000000, 594000000, 594, 13, 1, 8},
281 { 19200000, 594000000, 495, 16, 1, 8},
282 { 26000000, 594000000, 594, 26, 1, 8},
283
284 { 12000000, 1000000000, 1000, 12, 1, 12},
285 { 13000000, 1000000000, 1000, 13, 1, 12},
286 { 19200000, 1000000000, 625, 12, 1, 8},
287 { 26000000, 1000000000, 1000, 26, 1, 12},
288
289 { 0, 0, 0, 0, 0, 0 },
290};
291
292static struct clk tegra_pll_d = {
293 .name = "pll_d",
294 .flags = PLL_HAS_CPCON | PLLD,
295 .ops = &tegra_pll_ops,
296 .reg = 0xd0,
297 .parent = &tegra_clk_m,
298 .max_rate = 1000000000,
299 .u.pll = {
300 .input_min = 2000000,
301 .input_max = 40000000,
302 .cf_min = 1000000,
303 .cf_max = 6000000,
304 .vco_min = 40000000,
305 .vco_max = 1000000000,
306 .freq_table = tegra_pll_d_freq_table,
307 .lock_delay = 1000,
308 },
309};
310
311static struct clk tegra_pll_d_out0 = {
312 .name = "pll_d_out0",
313 .ops = &tegra_pll_div_ops,
314 .flags = DIV_2 | PLLD,
315 .parent = &tegra_pll_d,
316 .max_rate = 500000000,
317};
318
319static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
320 { 12000000, 480000000, 960, 12, 2, 0},
321 { 13000000, 480000000, 960, 13, 2, 0},
322 { 19200000, 480000000, 200, 4, 2, 0},
323 { 26000000, 480000000, 960, 26, 2, 0},
324 { 0, 0, 0, 0, 0, 0 },
325};
326
327static struct clk tegra_pll_u = {
328 .name = "pll_u",
329 .flags = PLLU,
330 .ops = &tegra_pll_ops,
331 .reg = 0xc0,
332 .parent = &tegra_clk_m,
333 .max_rate = 480000000,
334 .u.pll = {
335 .input_min = 2000000,
336 .input_max = 40000000,
337 .cf_min = 1000000,
338 .cf_max = 6000000,
339 .vco_min = 480000000,
340 .vco_max = 960000000,
341 .freq_table = tegra_pll_u_freq_table,
342 .lock_delay = 1000,
343 },
344};
345
346static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
347 /* 1 GHz */
348 { 12000000, 1000000000, 1000, 12, 1, 12},
349 { 13000000, 1000000000, 1000, 13, 1, 12},
350 { 19200000, 1000000000, 625, 12, 1, 8},
351 { 26000000, 1000000000, 1000, 26, 1, 12},
352
353 /* 912 MHz */
354 { 12000000, 912000000, 912, 12, 1, 12},
355 { 13000000, 912000000, 912, 13, 1, 12},
356 { 19200000, 912000000, 760, 16, 1, 8},
357 { 26000000, 912000000, 912, 26, 1, 12},
358
359 /* 816 MHz */
360 { 12000000, 816000000, 816, 12, 1, 12},
361 { 13000000, 816000000, 816, 13, 1, 12},
362 { 19200000, 816000000, 680, 16, 1, 8},
363 { 26000000, 816000000, 816, 26, 1, 12},
364
365 /* 760 MHz */
366 { 12000000, 760000000, 760, 12, 1, 12},
367 { 13000000, 760000000, 760, 13, 1, 12},
368 { 19200000, 760000000, 950, 24, 1, 8},
369 { 26000000, 760000000, 760, 26, 1, 12},
370
371 /* 750 MHz */
372 { 12000000, 750000000, 750, 12, 1, 12},
373 { 13000000, 750000000, 750, 13, 1, 12},
374 { 19200000, 750000000, 625, 16, 1, 8},
375 { 26000000, 750000000, 750, 26, 1, 12},
376
377 /* 608 MHz */
378 { 12000000, 608000000, 608, 12, 1, 12},
379 { 13000000, 608000000, 608, 13, 1, 12},
380 { 19200000, 608000000, 380, 12, 1, 8},
381 { 26000000, 608000000, 608, 26, 1, 12},
382
383 /* 456 MHz */
384 { 12000000, 456000000, 456, 12, 1, 12},
385 { 13000000, 456000000, 456, 13, 1, 12},
386 { 19200000, 456000000, 380, 16, 1, 8},
387 { 26000000, 456000000, 456, 26, 1, 12},
388
389 /* 312 MHz */
390 { 12000000, 312000000, 312, 12, 1, 12},
391 { 13000000, 312000000, 312, 13, 1, 12},
392 { 19200000, 312000000, 260, 16, 1, 8},
393 { 26000000, 312000000, 312, 26, 1, 12},
394
395 { 0, 0, 0, 0, 0, 0 },
396};
397
398static struct clk tegra_pll_x = {
399 .name = "pll_x",
400 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
401 .ops = &tegra_pllx_ops,
402 .reg = 0xe0,
403 .parent = &tegra_clk_m,
404 .max_rate = 1000000000,
405 .u.pll = {
406 .input_min = 2000000,
407 .input_max = 31000000,
408 .cf_min = 1000000,
409 .cf_max = 6000000,
410 .vco_min = 20000000,
411 .vco_max = 1200000000,
412 .freq_table = tegra_pll_x_freq_table,
413 .lock_delay = 300,
414 },
415};
416
417static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
418 { 12000000, 100000000, 200, 24, 1, 0 },
419 { 0, 0, 0, 0, 0, 0 },
420};
421
422static struct clk tegra_pll_e = {
423 .name = "pll_e",
424 .flags = PLL_ALT_MISC_REG,
425 .ops = &tegra_plle_ops,
426 .parent = &tegra_clk_m,
427 .reg = 0xe8,
428 .max_rate = 100000000,
429 .u.pll = {
430 .input_min = 12000000,
431 .input_max = 12000000,
432 .freq_table = tegra_pll_e_freq_table,
433 },
434};
435
436static struct clk tegra_clk_d = {
437 .name = "clk_d",
438 .flags = PERIPH_NO_RESET,
439 .ops = &tegra_clk_double_ops,
440 .reg = 0x34,
441 .reg_shift = 12,
442 .parent = &tegra_clk_m,
443 .max_rate = 52000000,
444 .u.periph = {
445 .clk_num = 90,
446 },
447};
448
449/* dap_mclk1, belongs to the cdev1 pingroup. */
450static struct clk tegra_clk_cdev1 = {
451 .name = "cdev1",
452 .ops = &tegra_cdev_clk_ops,
453 .rate = 26000000,
454 .max_rate = 26000000,
455 .u.periph = {
456 .clk_num = 94,
457 },
458};
459
460/* dap_mclk2, belongs to the cdev2 pingroup. */
461static struct clk tegra_clk_cdev2 = {
462 .name = "cdev2",
463 .ops = &tegra_cdev_clk_ops,
464 .rate = 26000000,
465 .max_rate = 26000000,
466 .u.periph = {
467 .clk_num = 93,
468 },
469};
470
471/* initialized before peripheral clocks */
472static struct clk_mux_sel mux_audio_sync_clk[8+1];
473static const struct audio_sources {
474 const char *name;
475 int value;
476} mux_audio_sync_clk_sources[] = {
477 { .name = "spdif_in", .value = 0 },
478 { .name = "i2s1", .value = 1 },
479 { .name = "i2s2", .value = 2 },
480 { .name = "pll_a_out0", .value = 4 },
481#if 0 /* FIXME: not implemented */
482 { .name = "ac97", .value = 3 },
483 { .name = "ext_audio_clk2", .value = 5 },
484 { .name = "ext_audio_clk1", .value = 6 },
485 { .name = "ext_vimclk", .value = 7 },
486#endif
487 { NULL, 0 }
488};
489
490static struct clk tegra_clk_audio = {
491 .name = "audio",
492 .inputs = mux_audio_sync_clk,
493 .reg = 0x38,
494 .max_rate = 73728000,
495 .ops = &tegra_audio_sync_clk_ops
496};
497
498static struct clk tegra_clk_audio_2x = {
499 .name = "audio_2x",
500 .flags = PERIPH_NO_RESET,
501 .max_rate = 48000000,
502 .ops = &tegra_clk_double_ops,
503 .reg = 0x34,
504 .reg_shift = 8,
505 .parent = &tegra_clk_audio,
506 .u.periph = {
507 .clk_num = 89,
508 },
509};
510
511static struct clk_lookup tegra_audio_clk_lookups[] = {
512 { .con_id = "audio", .clk = &tegra_clk_audio },
513 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
514};
515
516/* This is called after peripheral clocks are initialized, as the
517 * audio_sync clock depends on some of the peripheral clocks.
518 */
519
520static void init_audio_sync_clock_mux(void)
521{
522 int i;
523 struct clk_mux_sel *sel = mux_audio_sync_clk;
524 const struct audio_sources *src = mux_audio_sync_clk_sources;
525 struct clk_lookup *lookup;
526
527 for (i = 0; src->name; i++, sel++, src++) {
528 sel->input = tegra_get_clock_by_name(src->name);
529 if (!sel->input)
530 pr_err("%s: could not find clk %s\n", __func__,
531 src->name);
532 sel->value = src->value;
533 }
534
535 lookup = tegra_audio_clk_lookups;
536 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
537 clk_init(lookup->clk);
538 clkdev_add(lookup);
539 }
540}
541
542static struct clk_mux_sel mux_cclk[] = {
543 { .input = &tegra_clk_m, .value = 0},
544 { .input = &tegra_pll_c, .value = 1},
545 { .input = &tegra_clk_32k, .value = 2},
546 { .input = &tegra_pll_m, .value = 3},
547 { .input = &tegra_pll_p, .value = 4},
548 { .input = &tegra_pll_p_out4, .value = 5},
549 { .input = &tegra_pll_p_out3, .value = 6},
550 { .input = &tegra_clk_d, .value = 7},
551 { .input = &tegra_pll_x, .value = 8},
552 { NULL, 0},
553};
554
555static struct clk_mux_sel mux_sclk[] = {
556 { .input = &tegra_clk_m, .value = 0},
557 { .input = &tegra_pll_c_out1, .value = 1},
558 { .input = &tegra_pll_p_out4, .value = 2},
559 { .input = &tegra_pll_p_out3, .value = 3},
560 { .input = &tegra_pll_p_out2, .value = 4},
561 { .input = &tegra_clk_d, .value = 5},
562 { .input = &tegra_clk_32k, .value = 6},
563 { .input = &tegra_pll_m_out1, .value = 7},
564 { NULL, 0},
565};
566
567static struct clk tegra_clk_cclk = {
568 .name = "cclk",
569 .inputs = mux_cclk,
570 .reg = 0x20,
571 .ops = &tegra_super_ops,
572 .max_rate = 1000000000,
573};
574
575static struct clk tegra_clk_sclk = {
576 .name = "sclk",
577 .inputs = mux_sclk,
578 .reg = 0x28,
579 .ops = &tegra_super_ops,
580 .max_rate = 240000000,
581 .min_rate = 120000000,
582};
583
584static struct clk tegra_clk_virtual_cpu = {
585 .name = "cpu",
586 .parent = &tegra_clk_cclk,
587 .ops = &tegra_cpu_ops,
588 .max_rate = 1000000000,
589 .u.cpu = {
590 .main = &tegra_pll_x,
591 .backup = &tegra_pll_p,
592 },
593};
594
595static struct clk tegra_clk_cop = {
596 .name = "cop",
597 .parent = &tegra_clk_sclk,
598 .ops = &tegra_cop_ops,
599 .max_rate = 240000000,
600};
601
602static struct clk tegra_clk_hclk = {
603 .name = "hclk",
604 .flags = DIV_BUS,
605 .parent = &tegra_clk_sclk,
606 .reg = 0x30,
607 .reg_shift = 4,
608 .ops = &tegra_bus_ops,
609 .max_rate = 240000000,
610};
611
612static struct clk tegra_clk_pclk = {
613 .name = "pclk",
614 .flags = DIV_BUS,
615 .parent = &tegra_clk_hclk,
616 .reg = 0x30,
617 .reg_shift = 0,
618 .ops = &tegra_bus_ops,
619 .max_rate = 120000000,
620};
621
622static struct clk tegra_clk_blink = {
623 .name = "blink",
624 .parent = &tegra_clk_32k,
625 .reg = 0x40,
626 .ops = &tegra_blink_clk_ops,
627 .max_rate = 32768,
628};
629
630static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
631 { .input = &tegra_pll_m, .value = 0},
632 { .input = &tegra_pll_c, .value = 1},
633 { .input = &tegra_pll_p, .value = 2},
634 { .input = &tegra_pll_a_out0, .value = 3},
635 { NULL, 0},
636};
637
638static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
639 { .input = &tegra_pll_m, .value = 0},
640 { .input = &tegra_pll_c, .value = 1},
641 { .input = &tegra_pll_p, .value = 2},
642 { .input = &tegra_clk_m, .value = 3},
643 { NULL, 0},
644};
645
646static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
647 { .input = &tegra_pll_p, .value = 0},
648 { .input = &tegra_pll_c, .value = 1},
649 { .input = &tegra_pll_m, .value = 2},
650 { .input = &tegra_clk_m, .value = 3},
651 { NULL, 0},
652};
653
654static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
655 {.input = &tegra_pll_a_out0, .value = 0},
656 {.input = &tegra_clk_audio_2x, .value = 1},
657 {.input = &tegra_pll_p, .value = 2},
658 {.input = &tegra_clk_m, .value = 3},
659 { NULL, 0},
660};
661
662static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
663 {.input = &tegra_pll_p, .value = 0},
664 {.input = &tegra_pll_d_out0, .value = 1},
665 {.input = &tegra_pll_c, .value = 2},
666 {.input = &tegra_clk_m, .value = 3},
667 { NULL, 0},
668};
669
670static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
671 {.input = &tegra_pll_p, .value = 0},
672 {.input = &tegra_pll_c, .value = 1},
673 {.input = &tegra_clk_audio, .value = 2},
674 {.input = &tegra_clk_m, .value = 3},
675 {.input = &tegra_clk_32k, .value = 4},
676 { NULL, 0},
677};
678
679static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
680 {.input = &tegra_pll_p, .value = 0},
681 {.input = &tegra_pll_c, .value = 1},
682 {.input = &tegra_pll_m, .value = 2},
683 { NULL, 0},
684};
685
686static struct clk_mux_sel mux_clk_m[] = {
687 { .input = &tegra_clk_m, .value = 0},
688 { NULL, 0},
689};
690
691static struct clk_mux_sel mux_pllp_out3[] = {
692 { .input = &tegra_pll_p_out3, .value = 0},
693 { NULL, 0},
694};
695
696static struct clk_mux_sel mux_plld[] = {
697 { .input = &tegra_pll_d, .value = 0},
698 { NULL, 0},
699};
700
701static struct clk_mux_sel mux_clk_32k[] = {
702 { .input = &tegra_clk_32k, .value = 0},
703 { NULL, 0},
704};
705
706static struct clk_mux_sel mux_pclk[] = {
707 { .input = &tegra_clk_pclk, .value = 0},
708 { NULL, 0},
709};
710
711static struct clk tegra_clk_emc = {
712 .name = "emc",
713 .ops = &tegra_emc_clk_ops,
714 .reg = 0x19c,
715 .max_rate = 800000000,
716 .inputs = mux_pllm_pllc_pllp_clkm,
717 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
718 .u.periph = {
719 .clk_num = 57,
720 },
721};
722
723#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
724 { \
725 .name = _name, \
726 .lookup = { \
727 .dev_id = _dev, \
728 .con_id = _con, \
729 }, \
730 .ops = &tegra_periph_clk_ops, \
731 .reg = _reg, \
732 .inputs = _inputs, \
733 .flags = _flags, \
734 .max_rate = _max, \
735 .u.periph = { \
736 .clk_num = _clk_num, \
737 }, \
738 }
739
740#define SHARED_CLK(_name, _dev, _con, _parent) \
741 { \
742 .name = _name, \
743 .lookup = { \
744 .dev_id = _dev, \
745 .con_id = _con, \
746 }, \
747 .ops = &tegra_clk_shared_bus_ops, \
748 .parent = _parent, \
749 }
750
751static struct clk tegra_list_clks[] = {
752 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
753 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
754 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
755 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
756 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
757 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
758 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
759 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
760 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
761 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
762 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
763 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
764 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
765 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
766 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
767 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
768 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
769 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
770 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
771 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
772 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
773 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
774 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
775 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
776 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
777 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
778 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
779 /* FIXME: what is la? */
780 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
781 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
782 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
783 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
784 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
785 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
786 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
787 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
788 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
789 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
790 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
791 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
792 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
793 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
794 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
795 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
796 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
797 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
798 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
799 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
800 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
801 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
802 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
803 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
804 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
805 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
806 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
807 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
808 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
809 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
810 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
811 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
812 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
813 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
814 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
815 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
816 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
817 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
818 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
819 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
820
821 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
822 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
823 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
824 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
825 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
826 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
827 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
828 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
829 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
830 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
831 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
832};
833
834#define CLK_DUPLICATE(_name, _dev, _con) \
835 { \
836 .name = _name, \
837 .lookup = { \
838 .dev_id = _dev, \
839 .con_id = _con, \
840 }, \
841 }
842
843/* Some clocks may be used by different drivers depending on the board
844 * configuration. List those here to register them twice in the clock lookup
845 * table under two names.
846 */
847static struct clk_duplicate tegra_clk_duplicates[] = {
848 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
849 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
850 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
851 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
852 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
853 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
854 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
855 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
856 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
857 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
858 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
859 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
860 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
861 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
862 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
863 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
864 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
865};
866
867#define CLK(dev, con, ck) \
868 { \
869 .dev_id = dev, \
870 .con_id = con, \
871 .clk = ck, \
872 }
873
874static struct clk *tegra_ptr_clks[] = {
875 &tegra_clk_32k,
876 &tegra_pll_s,
877 &tegra_clk_m,
878 &tegra_pll_m,
879 &tegra_pll_m_out1,
880 &tegra_pll_c,
881 &tegra_pll_c_out1,
882 &tegra_pll_p,
883 &tegra_pll_p_out1,
884 &tegra_pll_p_out2,
885 &tegra_pll_p_out3,
886 &tegra_pll_p_out4,
887 &tegra_pll_a,
888 &tegra_pll_a_out0,
889 &tegra_pll_d,
890 &tegra_pll_d_out0,
891 &tegra_pll_u,
892 &tegra_pll_x,
893 &tegra_pll_e,
894 &tegra_clk_cclk,
895 &tegra_clk_sclk,
896 &tegra_clk_hclk,
897 &tegra_clk_pclk,
898 &tegra_clk_d,
899 &tegra_clk_cdev1,
900 &tegra_clk_cdev2,
901 &tegra_clk_virtual_cpu,
902 &tegra_clk_blink,
903 &tegra_clk_cop,
904 &tegra_clk_emc,
905};
906
907static void tegra2_init_one_clock(struct clk *c)
908{
909 clk_init(c);
910 INIT_LIST_HEAD(&c->shared_bus_list);
911 if (!c->lookup.dev_id && !c->lookup.con_id)
912 c->lookup.con_id = c->name;
913 c->lookup.clk = c;
914 clkdev_add(&c->lookup);
915}
916
917void __init tegra2_init_clocks(void)
918{
919 int i;
920 struct clk *c;
921
922 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
923 tegra2_init_one_clock(tegra_ptr_clks[i]);
924
925 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
926 tegra2_init_one_clock(&tegra_list_clks[i]);
927
928 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
929 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
930 if (!c) {
931 pr_err("%s: Unknown duplicate clock %s\n", __func__,
932 tegra_clk_duplicates[i].name);
933 continue;
934 }
935
936 tegra_clk_duplicates[i].lookup.clk = c;
937 clkdev_add(&tegra_clk_duplicates[i].lookup);
938 }
939
940 init_audio_sync_clock_mux();
941}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 83ccb85b9405..4a32030a4d96 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -274,7 +274,7 @@ static void tegra2_clk_m_disable(struct clk *c)
274 BUG(); 274 BUG();
275} 275}
276 276
277static struct clk_ops tegra_clk_m_ops = { 277struct clk_ops tegra_clk_m_ops = {
278 .init = tegra2_clk_m_init, 278 .init = tegra2_clk_m_init,
279 .enable = tegra2_clk_m_enable, 279 .enable = tegra2_clk_m_enable,
280 .disable = tegra2_clk_m_disable, 280 .disable = tegra2_clk_m_disable,
@@ -364,7 +364,7 @@ static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
364 return clk_set_rate(c->parent, rate); 364 return clk_set_rate(c->parent, rate);
365} 365}
366 366
367static struct clk_ops tegra_super_ops = { 367struct clk_ops tegra_super_ops = {
368 .init = tegra2_super_clk_init, 368 .init = tegra2_super_clk_init,
369 .enable = tegra2_super_clk_enable, 369 .enable = tegra2_super_clk_enable,
370 .disable = tegra2_super_clk_disable, 370 .disable = tegra2_super_clk_disable,
@@ -431,7 +431,7 @@ out:
431 return ret; 431 return ret;
432} 432}
433 433
434static struct clk_ops tegra_cpu_ops = { 434struct clk_ops tegra_cpu_ops = {
435 .init = tegra2_cpu_clk_init, 435 .init = tegra2_cpu_clk_init,
436 .enable = tegra2_cpu_clk_enable, 436 .enable = tegra2_cpu_clk_enable,
437 .disable = tegra2_cpu_clk_disable, 437 .disable = tegra2_cpu_clk_disable,
@@ -448,7 +448,7 @@ static void tegra2_cop_clk_reset(struct clk *c, bool assert)
448 clk_writel(1 << 1, reg); 448 clk_writel(1 << 1, reg);
449} 449}
450 450
451static struct clk_ops tegra_cop_ops = { 451struct clk_ops tegra_cop_ops = {
452 .reset = tegra2_cop_clk_reset, 452 .reset = tegra2_cop_clk_reset,
453}; 453};
454 454
@@ -519,7 +519,7 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
519 return ret; 519 return ret;
520} 520}
521 521
522static struct clk_ops tegra_bus_ops = { 522struct clk_ops tegra_bus_ops = {
523 .init = tegra2_bus_clk_init, 523 .init = tegra2_bus_clk_init,
524 .enable = tegra2_bus_clk_enable, 524 .enable = tegra2_bus_clk_enable,
525 .disable = tegra2_bus_clk_disable, 525 .disable = tegra2_bus_clk_disable,
@@ -601,7 +601,7 @@ static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
601 return 0; 601 return 0;
602} 602}
603 603
604static struct clk_ops tegra_blink_clk_ops = { 604struct clk_ops tegra_blink_clk_ops = {
605 .init = &tegra2_blink_clk_init, 605 .init = &tegra2_blink_clk_init,
606 .enable = &tegra2_blink_clk_enable, 606 .enable = &tegra2_blink_clk_enable,
607 .disable = &tegra2_blink_clk_disable, 607 .disable = &tegra2_blink_clk_disable,
@@ -711,7 +711,7 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
711 return -EINVAL; 711 return -EINVAL;
712} 712}
713 713
714static struct clk_ops tegra_pll_ops = { 714struct clk_ops tegra_pll_ops = {
715 .init = tegra2_pll_clk_init, 715 .init = tegra2_pll_clk_init,
716 .enable = tegra2_pll_clk_enable, 716 .enable = tegra2_pll_clk_enable,
717 .disable = tegra2_pll_clk_disable, 717 .disable = tegra2_pll_clk_disable,
@@ -726,7 +726,7 @@ static void tegra2_pllx_clk_init(struct clk *c)
726 c->max_rate = 750000000; 726 c->max_rate = 750000000;
727} 727}
728 728
729static struct clk_ops tegra_pllx_ops = { 729struct clk_ops tegra_pllx_ops = {
730 .init = tegra2_pllx_clk_init, 730 .init = tegra2_pllx_clk_init,
731 .enable = tegra2_pll_clk_enable, 731 .enable = tegra2_pll_clk_enable,
732 .disable = tegra2_pll_clk_disable, 732 .disable = tegra2_pll_clk_disable,
@@ -752,7 +752,7 @@ static int tegra2_plle_clk_enable(struct clk *c)
752 return 0; 752 return 0;
753} 753}
754 754
755static struct clk_ops tegra_plle_ops = { 755struct clk_ops tegra_plle_ops = {
756 .init = tegra2_pll_clk_init, 756 .init = tegra2_pll_clk_init,
757 .enable = tegra2_plle_clk_enable, 757 .enable = tegra2_plle_clk_enable,
758 .set_rate = tegra2_pll_clk_set_rate, 758 .set_rate = tegra2_pll_clk_set_rate,
@@ -895,7 +895,7 @@ static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
895 return -EINVAL; 895 return -EINVAL;
896} 896}
897 897
898static struct clk_ops tegra_pll_div_ops = { 898struct clk_ops tegra_pll_div_ops = {
899 .init = tegra2_pll_div_clk_init, 899 .init = tegra2_pll_div_clk_init,
900 .enable = tegra2_pll_div_clk_enable, 900 .enable = tegra2_pll_div_clk_enable,
901 .disable = tegra2_pll_div_clk_disable, 901 .disable = tegra2_pll_div_clk_disable,
@@ -1128,7 +1128,7 @@ static long tegra2_periph_clk_round_rate(struct clk *c,
1128 return -EINVAL; 1128 return -EINVAL;
1129} 1129}
1130 1130
1131static struct clk_ops tegra_periph_clk_ops = { 1131struct clk_ops tegra_periph_clk_ops = {
1132 .init = &tegra2_periph_clk_init, 1132 .init = &tegra2_periph_clk_init,
1133 .enable = &tegra2_periph_clk_enable, 1133 .enable = &tegra2_periph_clk_enable,
1134 .disable = &tegra2_periph_clk_disable, 1134 .disable = &tegra2_periph_clk_disable,
@@ -1217,7 +1217,7 @@ static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1217 return ret; 1217 return ret;
1218} 1218}
1219 1219
1220static struct clk_ops tegra_emc_clk_ops = { 1220struct clk_ops tegra_emc_clk_ops = {
1221 .init = &tegra2_emc_clk_init, 1221 .init = &tegra2_emc_clk_init,
1222 .enable = &tegra2_periph_clk_enable, 1222 .enable = &tegra2_periph_clk_enable,
1223 .disable = &tegra2_periph_clk_disable, 1223 .disable = &tegra2_periph_clk_disable,
@@ -1251,7 +1251,7 @@ static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1251 return 0; 1251 return 0;
1252} 1252}
1253 1253
1254static struct clk_ops tegra_clk_double_ops = { 1254struct clk_ops tegra_clk_double_ops = {
1255 .init = &tegra2_clk_double_init, 1255 .init = &tegra2_clk_double_init,
1256 .enable = &tegra2_periph_clk_enable, 1256 .enable = &tegra2_periph_clk_enable,
1257 .disable = &tegra2_periph_clk_disable, 1257 .disable = &tegra2_periph_clk_disable,
@@ -1310,7 +1310,7 @@ static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1310 return -EINVAL; 1310 return -EINVAL;
1311} 1311}
1312 1312
1313static struct clk_ops tegra_audio_sync_clk_ops = { 1313struct clk_ops tegra_audio_sync_clk_ops = {
1314 .init = tegra2_audio_sync_clk_init, 1314 .init = tegra2_audio_sync_clk_init,
1315 .enable = tegra2_audio_sync_clk_enable, 1315 .enable = tegra2_audio_sync_clk_enable,
1316 .disable = tegra2_audio_sync_clk_disable, 1316 .disable = tegra2_audio_sync_clk_disable,
@@ -1349,7 +1349,7 @@ static void tegra2_cdev_clk_disable(struct clk *c)
1349 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); 1349 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1350} 1350}
1351 1351
1352static struct clk_ops tegra_cdev_clk_ops = { 1352struct clk_ops tegra_cdev_clk_ops = {
1353 .init = &tegra2_cdev_clk_init, 1353 .init = &tegra2_cdev_clk_init,
1354 .enable = &tegra2_cdev_clk_enable, 1354 .enable = &tegra2_cdev_clk_enable,
1355 .disable = &tegra2_cdev_clk_disable, 1355 .disable = &tegra2_cdev_clk_disable,
@@ -1449,1036 +1449,10 @@ static void tegra_clk_shared_bus_disable(struct clk *c)
1449 spin_unlock_irqrestore(&c->parent->spinlock, flags); 1449 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1450} 1450}
1451 1451
1452static struct clk_ops tegra_clk_shared_bus_ops = { 1452struct clk_ops tegra_clk_shared_bus_ops = {
1453 .init = tegra_clk_shared_bus_init, 1453 .init = tegra_clk_shared_bus_init,
1454 .enable = tegra_clk_shared_bus_enable, 1454 .enable = tegra_clk_shared_bus_enable,
1455 .disable = tegra_clk_shared_bus_disable, 1455 .disable = tegra_clk_shared_bus_disable,
1456 .set_rate = tegra_clk_shared_bus_set_rate, 1456 .set_rate = tegra_clk_shared_bus_set_rate,
1457 .round_rate = tegra_clk_shared_bus_round_rate, 1457 .round_rate = tegra_clk_shared_bus_round_rate,
1458}; 1458};
1459
1460
1461/* Clock definitions */
1462static struct clk tegra_clk_32k = {
1463 .name = "clk_32k",
1464 .rate = 32768,
1465 .ops = NULL,
1466 .max_rate = 32768,
1467};
1468
1469static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1470 {32768, 12000000, 366, 1, 1, 0},
1471 {32768, 13000000, 397, 1, 1, 0},
1472 {32768, 19200000, 586, 1, 1, 0},
1473 {32768, 26000000, 793, 1, 1, 0},
1474 {0, 0, 0, 0, 0, 0},
1475};
1476
1477static struct clk tegra_pll_s = {
1478 .name = "pll_s",
1479 .flags = PLL_ALT_MISC_REG,
1480 .ops = &tegra_pll_ops,
1481 .parent = &tegra_clk_32k,
1482 .max_rate = 26000000,
1483 .reg = 0xf0,
1484 .u.pll = {
1485 .input_min = 32768,
1486 .input_max = 32768,
1487 .cf_min = 0, /* FIXME */
1488 .cf_max = 0, /* FIXME */
1489 .vco_min = 12000000,
1490 .vco_max = 26000000,
1491 .freq_table = tegra_pll_s_freq_table,
1492 .lock_delay = 300,
1493 },
1494};
1495
1496static struct clk_mux_sel tegra_clk_m_sel[] = {
1497 { .input = &tegra_clk_32k, .value = 0},
1498 { .input = &tegra_pll_s, .value = 1},
1499 { NULL , 0},
1500};
1501
1502static struct clk tegra_clk_m = {
1503 .name = "clk_m",
1504 .flags = ENABLE_ON_INIT,
1505 .ops = &tegra_clk_m_ops,
1506 .inputs = tegra_clk_m_sel,
1507 .reg = 0x1fc,
1508 .reg_shift = 28,
1509 .max_rate = 26000000,
1510};
1511
1512static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1513 { 12000000, 600000000, 600, 12, 1, 8 },
1514 { 13000000, 600000000, 600, 13, 1, 8 },
1515 { 19200000, 600000000, 500, 16, 1, 6 },
1516 { 26000000, 600000000, 600, 26, 1, 8 },
1517 { 0, 0, 0, 0, 0, 0 },
1518};
1519
1520static struct clk tegra_pll_c = {
1521 .name = "pll_c",
1522 .flags = PLL_HAS_CPCON,
1523 .ops = &tegra_pll_ops,
1524 .reg = 0x80,
1525 .parent = &tegra_clk_m,
1526 .max_rate = 600000000,
1527 .u.pll = {
1528 .input_min = 2000000,
1529 .input_max = 31000000,
1530 .cf_min = 1000000,
1531 .cf_max = 6000000,
1532 .vco_min = 20000000,
1533 .vco_max = 1400000000,
1534 .freq_table = tegra_pll_c_freq_table,
1535 .lock_delay = 300,
1536 },
1537};
1538
1539static struct clk tegra_pll_c_out1 = {
1540 .name = "pll_c_out1",
1541 .ops = &tegra_pll_div_ops,
1542 .flags = DIV_U71,
1543 .parent = &tegra_pll_c,
1544 .reg = 0x84,
1545 .reg_shift = 0,
1546 .max_rate = 600000000,
1547};
1548
1549static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1550 { 12000000, 666000000, 666, 12, 1, 8},
1551 { 13000000, 666000000, 666, 13, 1, 8},
1552 { 19200000, 666000000, 555, 16, 1, 8},
1553 { 26000000, 666000000, 666, 26, 1, 8},
1554 { 12000000, 600000000, 600, 12, 1, 8},
1555 { 13000000, 600000000, 600, 13, 1, 8},
1556 { 19200000, 600000000, 375, 12, 1, 6},
1557 { 26000000, 600000000, 600, 26, 1, 8},
1558 { 0, 0, 0, 0, 0, 0 },
1559};
1560
1561static struct clk tegra_pll_m = {
1562 .name = "pll_m",
1563 .flags = PLL_HAS_CPCON,
1564 .ops = &tegra_pll_ops,
1565 .reg = 0x90,
1566 .parent = &tegra_clk_m,
1567 .max_rate = 800000000,
1568 .u.pll = {
1569 .input_min = 2000000,
1570 .input_max = 31000000,
1571 .cf_min = 1000000,
1572 .cf_max = 6000000,
1573 .vco_min = 20000000,
1574 .vco_max = 1200000000,
1575 .freq_table = tegra_pll_m_freq_table,
1576 .lock_delay = 300,
1577 },
1578};
1579
1580static struct clk tegra_pll_m_out1 = {
1581 .name = "pll_m_out1",
1582 .ops = &tegra_pll_div_ops,
1583 .flags = DIV_U71,
1584 .parent = &tegra_pll_m,
1585 .reg = 0x94,
1586 .reg_shift = 0,
1587 .max_rate = 600000000,
1588};
1589
1590static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1591 { 12000000, 216000000, 432, 12, 2, 8},
1592 { 13000000, 216000000, 432, 13, 2, 8},
1593 { 19200000, 216000000, 90, 4, 2, 1},
1594 { 26000000, 216000000, 432, 26, 2, 8},
1595 { 12000000, 432000000, 432, 12, 1, 8},
1596 { 13000000, 432000000, 432, 13, 1, 8},
1597 { 19200000, 432000000, 90, 4, 1, 1},
1598 { 26000000, 432000000, 432, 26, 1, 8},
1599 { 0, 0, 0, 0, 0, 0 },
1600};
1601
1602static struct clk tegra_pll_p = {
1603 .name = "pll_p",
1604 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1605 .ops = &tegra_pll_ops,
1606 .reg = 0xa0,
1607 .parent = &tegra_clk_m,
1608 .max_rate = 432000000,
1609 .u.pll = {
1610 .input_min = 2000000,
1611 .input_max = 31000000,
1612 .cf_min = 1000000,
1613 .cf_max = 6000000,
1614 .vco_min = 20000000,
1615 .vco_max = 1400000000,
1616 .freq_table = tegra_pll_p_freq_table,
1617 .lock_delay = 300,
1618 },
1619};
1620
1621static struct clk tegra_pll_p_out1 = {
1622 .name = "pll_p_out1",
1623 .ops = &tegra_pll_div_ops,
1624 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1625 .parent = &tegra_pll_p,
1626 .reg = 0xa4,
1627 .reg_shift = 0,
1628 .max_rate = 432000000,
1629};
1630
1631static struct clk tegra_pll_p_out2 = {
1632 .name = "pll_p_out2",
1633 .ops = &tegra_pll_div_ops,
1634 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1635 .parent = &tegra_pll_p,
1636 .reg = 0xa4,
1637 .reg_shift = 16,
1638 .max_rate = 432000000,
1639};
1640
1641static struct clk tegra_pll_p_out3 = {
1642 .name = "pll_p_out3",
1643 .ops = &tegra_pll_div_ops,
1644 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1645 .parent = &tegra_pll_p,
1646 .reg = 0xa8,
1647 .reg_shift = 0,
1648 .max_rate = 432000000,
1649};
1650
1651static struct clk tegra_pll_p_out4 = {
1652 .name = "pll_p_out4",
1653 .ops = &tegra_pll_div_ops,
1654 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1655 .parent = &tegra_pll_p,
1656 .reg = 0xa8,
1657 .reg_shift = 16,
1658 .max_rate = 432000000,
1659};
1660
1661static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1662 { 28800000, 56448000, 49, 25, 1, 1},
1663 { 28800000, 73728000, 64, 25, 1, 1},
1664 { 28800000, 24000000, 5, 6, 1, 1},
1665 { 0, 0, 0, 0, 0, 0 },
1666};
1667
1668static struct clk tegra_pll_a = {
1669 .name = "pll_a",
1670 .flags = PLL_HAS_CPCON,
1671 .ops = &tegra_pll_ops,
1672 .reg = 0xb0,
1673 .parent = &tegra_pll_p_out1,
1674 .max_rate = 73728000,
1675 .u.pll = {
1676 .input_min = 2000000,
1677 .input_max = 31000000,
1678 .cf_min = 1000000,
1679 .cf_max = 6000000,
1680 .vco_min = 20000000,
1681 .vco_max = 1400000000,
1682 .freq_table = tegra_pll_a_freq_table,
1683 .lock_delay = 300,
1684 },
1685};
1686
1687static struct clk tegra_pll_a_out0 = {
1688 .name = "pll_a_out0",
1689 .ops = &tegra_pll_div_ops,
1690 .flags = DIV_U71,
1691 .parent = &tegra_pll_a,
1692 .reg = 0xb4,
1693 .reg_shift = 0,
1694 .max_rate = 73728000,
1695};
1696
1697static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1698 { 12000000, 216000000, 216, 12, 1, 4},
1699 { 13000000, 216000000, 216, 13, 1, 4},
1700 { 19200000, 216000000, 135, 12, 1, 3},
1701 { 26000000, 216000000, 216, 26, 1, 4},
1702
1703 { 12000000, 594000000, 594, 12, 1, 8},
1704 { 13000000, 594000000, 594, 13, 1, 8},
1705 { 19200000, 594000000, 495, 16, 1, 8},
1706 { 26000000, 594000000, 594, 26, 1, 8},
1707
1708 { 12000000, 1000000000, 1000, 12, 1, 12},
1709 { 13000000, 1000000000, 1000, 13, 1, 12},
1710 { 19200000, 1000000000, 625, 12, 1, 8},
1711 { 26000000, 1000000000, 1000, 26, 1, 12},
1712
1713 { 0, 0, 0, 0, 0, 0 },
1714};
1715
1716static struct clk tegra_pll_d = {
1717 .name = "pll_d",
1718 .flags = PLL_HAS_CPCON | PLLD,
1719 .ops = &tegra_pll_ops,
1720 .reg = 0xd0,
1721 .parent = &tegra_clk_m,
1722 .max_rate = 1000000000,
1723 .u.pll = {
1724 .input_min = 2000000,
1725 .input_max = 40000000,
1726 .cf_min = 1000000,
1727 .cf_max = 6000000,
1728 .vco_min = 40000000,
1729 .vco_max = 1000000000,
1730 .freq_table = tegra_pll_d_freq_table,
1731 .lock_delay = 1000,
1732 },
1733};
1734
1735static struct clk tegra_pll_d_out0 = {
1736 .name = "pll_d_out0",
1737 .ops = &tegra_pll_div_ops,
1738 .flags = DIV_2 | PLLD,
1739 .parent = &tegra_pll_d,
1740 .max_rate = 500000000,
1741};
1742
1743static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1744 { 12000000, 480000000, 960, 12, 2, 0},
1745 { 13000000, 480000000, 960, 13, 2, 0},
1746 { 19200000, 480000000, 200, 4, 2, 0},
1747 { 26000000, 480000000, 960, 26, 2, 0},
1748 { 0, 0, 0, 0, 0, 0 },
1749};
1750
1751static struct clk tegra_pll_u = {
1752 .name = "pll_u",
1753 .flags = PLLU,
1754 .ops = &tegra_pll_ops,
1755 .reg = 0xc0,
1756 .parent = &tegra_clk_m,
1757 .max_rate = 480000000,
1758 .u.pll = {
1759 .input_min = 2000000,
1760 .input_max = 40000000,
1761 .cf_min = 1000000,
1762 .cf_max = 6000000,
1763 .vco_min = 480000000,
1764 .vco_max = 960000000,
1765 .freq_table = tegra_pll_u_freq_table,
1766 .lock_delay = 1000,
1767 },
1768};
1769
1770static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1771 /* 1 GHz */
1772 { 12000000, 1000000000, 1000, 12, 1, 12},
1773 { 13000000, 1000000000, 1000, 13, 1, 12},
1774 { 19200000, 1000000000, 625, 12, 1, 8},
1775 { 26000000, 1000000000, 1000, 26, 1, 12},
1776
1777 /* 912 MHz */
1778 { 12000000, 912000000, 912, 12, 1, 12},
1779 { 13000000, 912000000, 912, 13, 1, 12},
1780 { 19200000, 912000000, 760, 16, 1, 8},
1781 { 26000000, 912000000, 912, 26, 1, 12},
1782
1783 /* 816 MHz */
1784 { 12000000, 816000000, 816, 12, 1, 12},
1785 { 13000000, 816000000, 816, 13, 1, 12},
1786 { 19200000, 816000000, 680, 16, 1, 8},
1787 { 26000000, 816000000, 816, 26, 1, 12},
1788
1789 /* 760 MHz */
1790 { 12000000, 760000000, 760, 12, 1, 12},
1791 { 13000000, 760000000, 760, 13, 1, 12},
1792 { 19200000, 760000000, 950, 24, 1, 8},
1793 { 26000000, 760000000, 760, 26, 1, 12},
1794
1795 /* 750 MHz */
1796 { 12000000, 750000000, 750, 12, 1, 12},
1797 { 13000000, 750000000, 750, 13, 1, 12},
1798 { 19200000, 750000000, 625, 16, 1, 8},
1799 { 26000000, 750000000, 750, 26, 1, 12},
1800
1801 /* 608 MHz */
1802 { 12000000, 608000000, 608, 12, 1, 12},
1803 { 13000000, 608000000, 608, 13, 1, 12},
1804 { 19200000, 608000000, 380, 12, 1, 8},
1805 { 26000000, 608000000, 608, 26, 1, 12},
1806
1807 /* 456 MHz */
1808 { 12000000, 456000000, 456, 12, 1, 12},
1809 { 13000000, 456000000, 456, 13, 1, 12},
1810 { 19200000, 456000000, 380, 16, 1, 8},
1811 { 26000000, 456000000, 456, 26, 1, 12},
1812
1813 /* 312 MHz */
1814 { 12000000, 312000000, 312, 12, 1, 12},
1815 { 13000000, 312000000, 312, 13, 1, 12},
1816 { 19200000, 312000000, 260, 16, 1, 8},
1817 { 26000000, 312000000, 312, 26, 1, 12},
1818
1819 { 0, 0, 0, 0, 0, 0 },
1820};
1821
1822static struct clk tegra_pll_x = {
1823 .name = "pll_x",
1824 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1825 .ops = &tegra_pllx_ops,
1826 .reg = 0xe0,
1827 .parent = &tegra_clk_m,
1828 .max_rate = 1000000000,
1829 .u.pll = {
1830 .input_min = 2000000,
1831 .input_max = 31000000,
1832 .cf_min = 1000000,
1833 .cf_max = 6000000,
1834 .vco_min = 20000000,
1835 .vco_max = 1200000000,
1836 .freq_table = tegra_pll_x_freq_table,
1837 .lock_delay = 300,
1838 },
1839};
1840
1841static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1842 { 12000000, 100000000, 200, 24, 1, 0 },
1843 { 0, 0, 0, 0, 0, 0 },
1844};
1845
1846static struct clk tegra_pll_e = {
1847 .name = "pll_e",
1848 .flags = PLL_ALT_MISC_REG,
1849 .ops = &tegra_plle_ops,
1850 .parent = &tegra_clk_m,
1851 .reg = 0xe8,
1852 .max_rate = 100000000,
1853 .u.pll = {
1854 .input_min = 12000000,
1855 .input_max = 12000000,
1856 .freq_table = tegra_pll_e_freq_table,
1857 },
1858};
1859
1860static struct clk tegra_clk_d = {
1861 .name = "clk_d",
1862 .flags = PERIPH_NO_RESET,
1863 .ops = &tegra_clk_double_ops,
1864 .reg = 0x34,
1865 .reg_shift = 12,
1866 .parent = &tegra_clk_m,
1867 .max_rate = 52000000,
1868 .u.periph = {
1869 .clk_num = 90,
1870 },
1871};
1872
1873/* dap_mclk1, belongs to the cdev1 pingroup. */
1874static struct clk tegra_clk_cdev1 = {
1875 .name = "cdev1",
1876 .ops = &tegra_cdev_clk_ops,
1877 .rate = 26000000,
1878 .max_rate = 26000000,
1879 .u.periph = {
1880 .clk_num = 94,
1881 },
1882};
1883
1884/* dap_mclk2, belongs to the cdev2 pingroup. */
1885static struct clk tegra_clk_cdev2 = {
1886 .name = "cdev2",
1887 .ops = &tegra_cdev_clk_ops,
1888 .rate = 26000000,
1889 .max_rate = 26000000,
1890 .u.periph = {
1891 .clk_num = 93,
1892 },
1893};
1894
1895/* initialized before peripheral clocks */
1896static struct clk_mux_sel mux_audio_sync_clk[8+1];
1897static const struct audio_sources {
1898 const char *name;
1899 int value;
1900} mux_audio_sync_clk_sources[] = {
1901 { .name = "spdif_in", .value = 0 },
1902 { .name = "i2s1", .value = 1 },
1903 { .name = "i2s2", .value = 2 },
1904 { .name = "pll_a_out0", .value = 4 },
1905#if 0 /* FIXME: not implemented */
1906 { .name = "ac97", .value = 3 },
1907 { .name = "ext_audio_clk2", .value = 5 },
1908 { .name = "ext_audio_clk1", .value = 6 },
1909 { .name = "ext_vimclk", .value = 7 },
1910#endif
1911 { NULL, 0 }
1912};
1913
1914static struct clk tegra_clk_audio = {
1915 .name = "audio",
1916 .inputs = mux_audio_sync_clk,
1917 .reg = 0x38,
1918 .max_rate = 73728000,
1919 .ops = &tegra_audio_sync_clk_ops
1920};
1921
1922static struct clk tegra_clk_audio_2x = {
1923 .name = "audio_2x",
1924 .flags = PERIPH_NO_RESET,
1925 .max_rate = 48000000,
1926 .ops = &tegra_clk_double_ops,
1927 .reg = 0x34,
1928 .reg_shift = 8,
1929 .parent = &tegra_clk_audio,
1930 .u.periph = {
1931 .clk_num = 89,
1932 },
1933};
1934
1935static struct clk_lookup tegra_audio_clk_lookups[] = {
1936 { .con_id = "audio", .clk = &tegra_clk_audio },
1937 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1938};
1939
1940/* This is called after peripheral clocks are initialized, as the
1941 * audio_sync clock depends on some of the peripheral clocks.
1942 */
1943
1944static void init_audio_sync_clock_mux(void)
1945{
1946 int i;
1947 struct clk_mux_sel *sel = mux_audio_sync_clk;
1948 const struct audio_sources *src = mux_audio_sync_clk_sources;
1949 struct clk_lookup *lookup;
1950
1951 for (i = 0; src->name; i++, sel++, src++) {
1952 sel->input = tegra_get_clock_by_name(src->name);
1953 if (!sel->input)
1954 pr_err("%s: could not find clk %s\n", __func__,
1955 src->name);
1956 sel->value = src->value;
1957 }
1958
1959 lookup = tegra_audio_clk_lookups;
1960 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1961 clk_init(lookup->clk);
1962 clkdev_add(lookup);
1963 }
1964}
1965
1966static struct clk_mux_sel mux_cclk[] = {
1967 { .input = &tegra_clk_m, .value = 0},
1968 { .input = &tegra_pll_c, .value = 1},
1969 { .input = &tegra_clk_32k, .value = 2},
1970 { .input = &tegra_pll_m, .value = 3},
1971 { .input = &tegra_pll_p, .value = 4},
1972 { .input = &tegra_pll_p_out4, .value = 5},
1973 { .input = &tegra_pll_p_out3, .value = 6},
1974 { .input = &tegra_clk_d, .value = 7},
1975 { .input = &tegra_pll_x, .value = 8},
1976 { NULL, 0},
1977};
1978
1979static struct clk_mux_sel mux_sclk[] = {
1980 { .input = &tegra_clk_m, .value = 0},
1981 { .input = &tegra_pll_c_out1, .value = 1},
1982 { .input = &tegra_pll_p_out4, .value = 2},
1983 { .input = &tegra_pll_p_out3, .value = 3},
1984 { .input = &tegra_pll_p_out2, .value = 4},
1985 { .input = &tegra_clk_d, .value = 5},
1986 { .input = &tegra_clk_32k, .value = 6},
1987 { .input = &tegra_pll_m_out1, .value = 7},
1988 { NULL, 0},
1989};
1990
1991static struct clk tegra_clk_cclk = {
1992 .name = "cclk",
1993 .inputs = mux_cclk,
1994 .reg = 0x20,
1995 .ops = &tegra_super_ops,
1996 .max_rate = 1000000000,
1997};
1998
1999static struct clk tegra_clk_sclk = {
2000 .name = "sclk",
2001 .inputs = mux_sclk,
2002 .reg = 0x28,
2003 .ops = &tegra_super_ops,
2004 .max_rate = 240000000,
2005 .min_rate = 120000000,
2006};
2007
2008static struct clk tegra_clk_virtual_cpu = {
2009 .name = "cpu",
2010 .parent = &tegra_clk_cclk,
2011 .ops = &tegra_cpu_ops,
2012 .max_rate = 1000000000,
2013 .u.cpu = {
2014 .main = &tegra_pll_x,
2015 .backup = &tegra_pll_p,
2016 },
2017};
2018
2019static struct clk tegra_clk_cop = {
2020 .name = "cop",
2021 .parent = &tegra_clk_sclk,
2022 .ops = &tegra_cop_ops,
2023 .max_rate = 240000000,
2024};
2025
2026static struct clk tegra_clk_hclk = {
2027 .name = "hclk",
2028 .flags = DIV_BUS,
2029 .parent = &tegra_clk_sclk,
2030 .reg = 0x30,
2031 .reg_shift = 4,
2032 .ops = &tegra_bus_ops,
2033 .max_rate = 240000000,
2034};
2035
2036static struct clk tegra_clk_pclk = {
2037 .name = "pclk",
2038 .flags = DIV_BUS,
2039 .parent = &tegra_clk_hclk,
2040 .reg = 0x30,
2041 .reg_shift = 0,
2042 .ops = &tegra_bus_ops,
2043 .max_rate = 120000000,
2044};
2045
2046static struct clk tegra_clk_blink = {
2047 .name = "blink",
2048 .parent = &tegra_clk_32k,
2049 .reg = 0x40,
2050 .ops = &tegra_blink_clk_ops,
2051 .max_rate = 32768,
2052};
2053
2054static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2055 { .input = &tegra_pll_m, .value = 0},
2056 { .input = &tegra_pll_c, .value = 1},
2057 { .input = &tegra_pll_p, .value = 2},
2058 { .input = &tegra_pll_a_out0, .value = 3},
2059 { NULL, 0},
2060};
2061
2062static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2063 { .input = &tegra_pll_m, .value = 0},
2064 { .input = &tegra_pll_c, .value = 1},
2065 { .input = &tegra_pll_p, .value = 2},
2066 { .input = &tegra_clk_m, .value = 3},
2067 { NULL, 0},
2068};
2069
2070static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2071 { .input = &tegra_pll_p, .value = 0},
2072 { .input = &tegra_pll_c, .value = 1},
2073 { .input = &tegra_pll_m, .value = 2},
2074 { .input = &tegra_clk_m, .value = 3},
2075 { NULL, 0},
2076};
2077
2078static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2079 {.input = &tegra_pll_a_out0, .value = 0},
2080 {.input = &tegra_clk_audio_2x, .value = 1},
2081 {.input = &tegra_pll_p, .value = 2},
2082 {.input = &tegra_clk_m, .value = 3},
2083 { NULL, 0},
2084};
2085
2086static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2087 {.input = &tegra_pll_p, .value = 0},
2088 {.input = &tegra_pll_d_out0, .value = 1},
2089 {.input = &tegra_pll_c, .value = 2},
2090 {.input = &tegra_clk_m, .value = 3},
2091 { NULL, 0},
2092};
2093
2094static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2095 {.input = &tegra_pll_p, .value = 0},
2096 {.input = &tegra_pll_c, .value = 1},
2097 {.input = &tegra_clk_audio, .value = 2},
2098 {.input = &tegra_clk_m, .value = 3},
2099 {.input = &tegra_clk_32k, .value = 4},
2100 { NULL, 0},
2101};
2102
2103static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2104 {.input = &tegra_pll_p, .value = 0},
2105 {.input = &tegra_pll_c, .value = 1},
2106 {.input = &tegra_pll_m, .value = 2},
2107 { NULL, 0},
2108};
2109
2110static struct clk_mux_sel mux_clk_m[] = {
2111 { .input = &tegra_clk_m, .value = 0},
2112 { NULL, 0},
2113};
2114
2115static struct clk_mux_sel mux_pllp_out3[] = {
2116 { .input = &tegra_pll_p_out3, .value = 0},
2117 { NULL, 0},
2118};
2119
2120static struct clk_mux_sel mux_plld[] = {
2121 { .input = &tegra_pll_d, .value = 0},
2122 { NULL, 0},
2123};
2124
2125static struct clk_mux_sel mux_clk_32k[] = {
2126 { .input = &tegra_clk_32k, .value = 0},
2127 { NULL, 0},
2128};
2129
2130static struct clk_mux_sel mux_pclk[] = {
2131 { .input = &tegra_clk_pclk, .value = 0},
2132 { NULL, 0},
2133};
2134
2135static struct clk tegra_clk_emc = {
2136 .name = "emc",
2137 .ops = &tegra_emc_clk_ops,
2138 .reg = 0x19c,
2139 .max_rate = 800000000,
2140 .inputs = mux_pllm_pllc_pllp_clkm,
2141 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2142 .u.periph = {
2143 .clk_num = 57,
2144 },
2145};
2146
2147#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2148 { \
2149 .name = _name, \
2150 .lookup = { \
2151 .dev_id = _dev, \
2152 .con_id = _con, \
2153 }, \
2154 .ops = &tegra_periph_clk_ops, \
2155 .reg = _reg, \
2156 .inputs = _inputs, \
2157 .flags = _flags, \
2158 .max_rate = _max, \
2159 .u.periph = { \
2160 .clk_num = _clk_num, \
2161 }, \
2162 }
2163
2164#define SHARED_CLK(_name, _dev, _con, _parent) \
2165 { \
2166 .name = _name, \
2167 .lookup = { \
2168 .dev_id = _dev, \
2169 .con_id = _con, \
2170 }, \
2171 .ops = &tegra_clk_shared_bus_ops, \
2172 .parent = _parent, \
2173 }
2174
2175static struct clk tegra_list_clks[] = {
2176 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
2177 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2178 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2179 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2187 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2188 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2189 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2190 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2191 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2192 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2193 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2194 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2195 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2196 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2197 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2198 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2199 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2200 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2201 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2202 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2203 /* FIXME: what is la? */
2204 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2205 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2206 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2207 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2208 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2209 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2210 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2211 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2212 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2213 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2214 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2215 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2216 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2217 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2218 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2219 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2220 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2221 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2222 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2223 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2224 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2225 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2226 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2227 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2228 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2229 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2230 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2231 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2232 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2233 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2234 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2235 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2236 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2237 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2238 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2239 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2240 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2241 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2242 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2243 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2244
2245 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2246 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2247 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2248 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2249 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2250 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2251 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2252 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2253 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2254 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2255 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2256};
2257
2258#define CLK_DUPLICATE(_name, _dev, _con) \
2259 { \
2260 .name = _name, \
2261 .lookup = { \
2262 .dev_id = _dev, \
2263 .con_id = _con, \
2264 }, \
2265 }
2266
2267/* Some clocks may be used by different drivers depending on the board
2268 * configuration. List those here to register them twice in the clock lookup
2269 * table under two names.
2270 */
2271static struct clk_duplicate tegra_clk_duplicates[] = {
2272 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2273 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2274 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2275 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2276 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2277 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2278 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2285 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2286 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2287 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2288 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2289};
2290
2291#define CLK(dev, con, ck) \
2292 { \
2293 .dev_id = dev, \
2294 .con_id = con, \
2295 .clk = ck, \
2296 }
2297
2298static struct clk *tegra_ptr_clks[] = {
2299 &tegra_clk_32k,
2300 &tegra_pll_s,
2301 &tegra_clk_m,
2302 &tegra_pll_m,
2303 &tegra_pll_m_out1,
2304 &tegra_pll_c,
2305 &tegra_pll_c_out1,
2306 &tegra_pll_p,
2307 &tegra_pll_p_out1,
2308 &tegra_pll_p_out2,
2309 &tegra_pll_p_out3,
2310 &tegra_pll_p_out4,
2311 &tegra_pll_a,
2312 &tegra_pll_a_out0,
2313 &tegra_pll_d,
2314 &tegra_pll_d_out0,
2315 &tegra_pll_u,
2316 &tegra_pll_x,
2317 &tegra_pll_e,
2318 &tegra_clk_cclk,
2319 &tegra_clk_sclk,
2320 &tegra_clk_hclk,
2321 &tegra_clk_pclk,
2322 &tegra_clk_d,
2323 &tegra_clk_cdev1,
2324 &tegra_clk_cdev2,
2325 &tegra_clk_virtual_cpu,
2326 &tegra_clk_blink,
2327 &tegra_clk_cop,
2328 &tegra_clk_emc,
2329};
2330
2331static void tegra2_init_one_clock(struct clk *c)
2332{
2333 clk_init(c);
2334 INIT_LIST_HEAD(&c->shared_bus_list);
2335 if (!c->lookup.dev_id && !c->lookup.con_id)
2336 c->lookup.con_id = c->name;
2337 c->lookup.clk = c;
2338 clkdev_add(&c->lookup);
2339}
2340
2341void __init tegra2_init_clocks(void)
2342{
2343 int i;
2344 struct clk *c;
2345
2346 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2347 tegra2_init_one_clock(tegra_ptr_clks[i]);
2348
2349 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2350 tegra2_init_one_clock(&tegra_list_clks[i]);
2351
2352 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2353 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2354 if (!c) {
2355 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2356 tegra_clk_duplicates[i].name);
2357 continue;
2358 }
2359
2360 tegra_clk_duplicates[i].lookup.clk = c;
2361 clkdev_add(&tegra_clk_duplicates[i].lookup);
2362 }
2363
2364 init_audio_sync_clock_mux();
2365}
2366
2367#ifdef CONFIG_PM
2368static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2369 PERIPH_CLK_SOURCE_NUM + 22];
2370
2371void tegra_clk_suspend(void)
2372{
2373 unsigned long off, i;
2374 u32 *ctx = clk_rst_suspend;
2375
2376 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2377 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2378 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2379 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2380 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2381 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2382 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2383 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2384 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2385 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2386 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2387
2388 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2389 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2390 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2391
2392 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2393 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2394
2395 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2396 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2397 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2398
2399 *ctx++ = clk_readl(tegra_clk_audio.reg);
2400
2401 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2402 off += 4) {
2403 if (off == PERIPH_CLK_SOURCE_EMC)
2404 continue;
2405 *ctx++ = clk_readl(off);
2406 }
2407
2408 off = RST_DEVICES;
2409 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2410 *ctx++ = clk_readl(off);
2411
2412 off = CLK_OUT_ENB;
2413 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2414 *ctx++ = clk_readl(off);
2415
2416 *ctx++ = clk_readl(MISC_CLK_ENB);
2417 *ctx++ = clk_readl(CLK_MASK_ARM);
2418
2419 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2420}
2421
2422void tegra_clk_resume(void)
2423{
2424 unsigned long off, i;
2425 const u32 *ctx = clk_rst_suspend;
2426 u32 val;
2427
2428 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2429 val |= *ctx++;
2430 clk_writel(val, OSC_CTRL);
2431
2432 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2433 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2434 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2435 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2436 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2437 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2438 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2439 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2440 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2441 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2442 udelay(1000);
2443
2444 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2445 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2446 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2447
2448 clk_writel(*ctx++, tegra_clk_cclk.reg);
2449 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2450
2451 clk_writel(*ctx++, tegra_clk_sclk.reg);
2452 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2453 clk_writel(*ctx++, tegra_clk_pclk.reg);
2454
2455 clk_writel(*ctx++, tegra_clk_audio.reg);
2456
2457 /* enable all clocks before configuring clock sources */
2458 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2459 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2460 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2461 wmb();
2462
2463 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2464 off += 4) {
2465 if (off == PERIPH_CLK_SOURCE_EMC)
2466 continue;
2467 clk_writel(*ctx++, off);
2468 }
2469 wmb();
2470
2471 off = RST_DEVICES;
2472 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2473 clk_writel(*ctx++, off);
2474 wmb();
2475
2476 off = CLK_OUT_ENB;
2477 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2478 clk_writel(*ctx++, off);
2479 wmb();
2480
2481 clk_writel(*ctx++, MISC_CLK_ENB);
2482 clk_writel(*ctx++, CLK_MASK_ARM);
2483}
2484#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 22:52:54 -0400