aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/ath/ath9k
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/ath/ath9k')
-rw-r--r--drivers/net/wireless/ath/ath9k/Kconfig20
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile34
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c54
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c141
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h291
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c162
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c383
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.h66
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c421
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/common.c299
-rw-r--r--drivers/net/wireless/ath/ath9k/common.h127
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c272
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h79
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h9
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c94
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c97
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c183
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c442
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1496
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h108
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c865
-rw-r--r--drivers/net/wireless/ath/ath9k/initvals.h101
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c200
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h63
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c1943
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c112
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c1036
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h45
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c572
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.h29
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c404
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h33
-rw-r--r--drivers/net/wireless/ath/ath9k/virtual.c114
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c465
36 files changed, 5990 insertions, 4780 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index ef5f59c4dd80..5774cea23a3b 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -1,9 +1,16 @@
1config ATH9K_HW
2 tristate
3config ATH9K_COMMON
4 tristate
5
1config ATH9K 6config ATH9K
2 tristate "Atheros 802.11n wireless cards support" 7 tristate "Atheros 802.11n wireless cards support"
3 depends on PCI && MAC80211 && WLAN_80211 8 depends on PCI && MAC80211
9 select ATH9K_HW
4 select MAC80211_LEDS 10 select MAC80211_LEDS
5 select LEDS_CLASS 11 select LEDS_CLASS
6 select NEW_LEDS 12 select NEW_LEDS
13 select ATH9K_COMMON
7 ---help--- 14 ---help---
8 This module adds support for wireless adapters based on 15 This module adds support for wireless adapters based on
9 Atheros IEEE 802.11n AR5008, AR9001 and AR9002 family 16 Atheros IEEE 802.11n AR5008, AR9001 and AR9002 family
@@ -16,13 +23,12 @@ config ATH9K
16 23
17 If you choose to build a module, it'll be called ath9k. 24 If you choose to build a module, it'll be called ath9k.
18 25
19config ATH9K_DEBUG 26config ATH9K_DEBUGFS
20 bool "Atheros ath9k debugging" 27 bool "Atheros ath9k debugging"
21 depends on ATH9K 28 depends on ATH9K && DEBUG_FS
22 ---help--- 29 ---help---
23 Say Y, if you need ath9k to display debug messages. 30 Say Y, if you need access to ath9k's statistics for
24 Pass the debug mask as a module parameter: 31 interrupts, rate control, etc.
25 32
26 modprobe ath9k debug=0x00000200 33 Also required for changing debug message flags at run time.
27 34
28 Look in ath9k/debug.h for possible debug masks
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index ff2c9a26c10c..6b50d5eb9ec3 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -1,22 +1,30 @@
1ath9k-y += hw.o \ 1ath9k-y += beacon.o \
2 eeprom.o \ 2 gpio.o \
3 eeprom_def.o \ 3 init.o \
4 eeprom_4k.o \
5 eeprom_9287.o \
6 mac.o \
7 calib.o \
8 ani.o \
9 phy.o \
10 beacon.o \
11 main.o \ 4 main.o \
12 recv.o \ 5 recv.o \
13 xmit.o \ 6 xmit.o \
14 virtual.o \ 7 virtual.o \
15 rc.o \ 8 rc.o
16 btcoex.o
17 9
18ath9k-$(CONFIG_PCI) += pci.o 10ath9k-$(CONFIG_PCI) += pci.o
19ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o 11ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o
20ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o 12ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
21 13
22obj-$(CONFIG_ATH9K) += ath9k.o 14obj-$(CONFIG_ATH9K) += ath9k.o
15
16ath9k_hw-y:= hw.o \
17 eeprom.o \
18 eeprom_def.o \
19 eeprom_4k.o \
20 eeprom_9287.o \
21 calib.o \
22 ani.o \
23 phy.o \
24 btcoex.o \
25 mac.o \
26
27obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
28
29obj-$(CONFIG_ATH9K_COMMON) += ath9k_common.o
30ath9k_common-y:= common.o
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 2ad7d0280f7a..ca4994f13151 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -22,27 +22,23 @@
22#include "ath9k.h" 22#include "ath9k.h"
23 23
24/* return bus cachesize in 4B word units */ 24/* return bus cachesize in 4B word units */
25static void ath_ahb_read_cachesize(struct ath_softc *sc, int *csz) 25static void ath_ahb_read_cachesize(struct ath_common *common, int *csz)
26{ 26{
27 *csz = L1_CACHE_BYTES >> 2; 27 *csz = L1_CACHE_BYTES >> 2;
28} 28}
29 29
30static void ath_ahb_cleanup(struct ath_softc *sc) 30static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
31{ 31{
32 iounmap(sc->mem); 32 struct ath_softc *sc = (struct ath_softc *)common->priv;
33}
34
35static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
36{
37 struct ath_softc *sc = ah->ah_sc;
38 struct platform_device *pdev = to_platform_device(sc->dev); 33 struct platform_device *pdev = to_platform_device(sc->dev);
39 struct ath9k_platform_data *pdata; 34 struct ath9k_platform_data *pdata;
40 35
41 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; 36 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
42 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 37 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
43 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 38 ath_print(common, ATH_DBG_FATAL,
44 "%s: flash read failed, offset %08x is out of range\n", 39 "%s: flash read failed, offset %08x "
45 __func__, off); 40 "is out of range\n",
41 __func__, off);
46 return false; 42 return false;
47 } 43 }
48 44
@@ -52,8 +48,6 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
52 48
53static struct ath_bus_ops ath_ahb_bus_ops = { 49static struct ath_bus_ops ath_ahb_bus_ops = {
54 .read_cachesize = ath_ahb_read_cachesize, 50 .read_cachesize = ath_ahb_read_cachesize,
55 .cleanup = ath_ahb_cleanup,
56
57 .eeprom_read = ath_ahb_eeprom_read, 51 .eeprom_read = ath_ahb_eeprom_read,
58}; 52};
59 53
@@ -67,6 +61,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
67 int irq; 61 int irq;
68 int ret = 0; 62 int ret = 0;
69 struct ath_hw *ah; 63 struct ath_hw *ah;
64 char hw_name[64];
70 65
71 if (!pdev->dev.platform_data) { 66 if (!pdev->dev.platform_data) {
72 dev_err(&pdev->dev, "no platform data specified\n"); 67 dev_err(&pdev->dev, "no platform data specified\n");
@@ -116,36 +111,35 @@ static int ath_ahb_probe(struct platform_device *pdev)
116 sc->hw = hw; 111 sc->hw = hw;
117 sc->dev = &pdev->dev; 112 sc->dev = &pdev->dev;
118 sc->mem = mem; 113 sc->mem = mem;
119 sc->bus_ops = &ath_ahb_bus_ops;
120 sc->irq = irq; 114 sc->irq = irq;
121 115
122 ret = ath_init_device(AR5416_AR9100_DEVID, sc, 0x0); 116 /* Will be cleared in ath9k_start() */
117 sc->sc_flags |= SC_OP_INVALID;
118
119 ret = request_irq(irq, ath_isr, IRQF_SHARED, "ath9k", sc);
123 if (ret) { 120 if (ret) {
124 dev_err(&pdev->dev, "failed to initialize device\n"); 121 dev_err(&pdev->dev, "request_irq failed\n");
125 goto err_free_hw; 122 goto err_free_hw;
126 } 123 }
127 124
128 ret = request_irq(irq, ath_isr, IRQF_SHARED, "ath9k", sc); 125 ret = ath9k_init_device(AR5416_AR9100_DEVID, sc, 0x0, &ath_ahb_bus_ops);
129 if (ret) { 126 if (ret) {
130 dev_err(&pdev->dev, "request_irq failed\n"); 127 dev_err(&pdev->dev, "failed to initialize device\n");
131 goto err_detach; 128 goto err_irq;
132 } 129 }
133 130
134 ah = sc->sc_ah; 131 ah = sc->sc_ah;
132 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
135 printk(KERN_INFO 133 printk(KERN_INFO
136 "%s: Atheros AR%s MAC/BB Rev:%x, " 134 "%s: %s mem=0x%lx, irq=%d\n",
137 "AR%s RF Rev:%x, mem=0x%lx, irq=%d\n",
138 wiphy_name(hw->wiphy), 135 wiphy_name(hw->wiphy),
139 ath_mac_bb_name(ah->hw_version.macVersion), 136 hw_name,
140 ah->hw_version.macRev,
141 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
142 ah->hw_version.phyRev,
143 (unsigned long)mem, irq); 137 (unsigned long)mem, irq);
144 138
145 return 0; 139 return 0;
146 140
147 err_detach: 141 err_irq:
148 ath_detach(sc); 142 free_irq(irq, sc);
149 err_free_hw: 143 err_free_hw:
150 ieee80211_free_hw(hw); 144 ieee80211_free_hw(hw);
151 platform_set_drvdata(pdev, NULL); 145 platform_set_drvdata(pdev, NULL);
@@ -162,8 +156,12 @@ static int ath_ahb_remove(struct platform_device *pdev)
162 if (hw) { 156 if (hw) {
163 struct ath_wiphy *aphy = hw->priv; 157 struct ath_wiphy *aphy = hw->priv;
164 struct ath_softc *sc = aphy->sc; 158 struct ath_softc *sc = aphy->sc;
159 void __iomem *mem = sc->mem;
165 160
166 ath_cleanup(sc); 161 ath9k_deinit_device(sc);
162 free_irq(sc->irq, sc);
163 ieee80211_free_hw(sc->hw);
164 iounmap(mem);
167 platform_set_drvdata(pdev, NULL); 165 platform_set_drvdata(pdev, NULL);
168 } 166 }
169 167
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 2b493742ef10..2a0cd64c2bfb 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, 19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
20 struct ath9k_channel *chan) 20 struct ath9k_channel *chan)
@@ -31,8 +31,8 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
31 } 31 }
32 } 32 }
33 33
34 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 34 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
35 "No more channel states left. Using channel 0\n"); 35 "No more channel states left. Using channel 0\n");
36 36
37 return 0; 37 return 0;
38} 38}
@@ -41,16 +41,17 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
41 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
42{ 42{
43 struct ar5416AniState *aniState = ah->curani; 43 struct ar5416AniState *aniState = ah->curani;
44 struct ath_common *common = ath9k_hw_common(ah);
44 45
45 switch (cmd & ah->ani_function) { 46 switch (cmd & ah->ani_function) {
46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 47 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
47 u32 level = param; 48 u32 level = param;
48 49
49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 50 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
50 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 51 ath_print(common, ATH_DBG_ANI,
51 "level out of range (%u > %u)\n", 52 "level out of range (%u > %u)\n",
52 level, 53 level,
53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); 54 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
54 return false; 55 return false;
55 } 56 }
56 57
@@ -152,10 +153,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
152 u32 level = param; 153 u32 level = param;
153 154
154 if (level >= ARRAY_SIZE(firstep)) { 155 if (level >= ARRAY_SIZE(firstep)) {
155 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 156 ath_print(common, ATH_DBG_ANI,
156 "level out of range (%u > %u)\n", 157 "level out of range (%u > %u)\n",
157 level, 158 level,
158 (unsigned) ARRAY_SIZE(firstep)); 159 (unsigned) ARRAY_SIZE(firstep));
159 return false; 160 return false;
160 } 161 }
161 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 162 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -174,11 +175,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
174 u32 level = param; 175 u32 level = param;
175 176
176 if (level >= ARRAY_SIZE(cycpwrThr1)) { 177 if (level >= ARRAY_SIZE(cycpwrThr1)) {
177 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 178 ath_print(common, ATH_DBG_ANI,
178 "level out of range (%u > %u)\n", 179 "level out of range (%u > %u)\n",
179 level, 180 level,
180 (unsigned) 181 (unsigned) ARRAY_SIZE(cycpwrThr1));
181 ARRAY_SIZE(cycpwrThr1));
182 return false; 182 return false;
183 } 183 }
184 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 184 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -194,25 +194,28 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
194 case ATH9K_ANI_PRESENT: 194 case ATH9K_ANI_PRESENT:
195 break; 195 break;
196 default: 196 default:
197 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 197 ath_print(common, ATH_DBG_ANI,
198 "invalid cmd %u\n", cmd); 198 "invalid cmd %u\n", cmd);
199 return false; 199 return false;
200 } 200 }
201 201
202 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n"); 202 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
203 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 203 ath_print(common, ATH_DBG_ANI,
204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, " 204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
205 "ofdmWeakSigDetectOff=%d\n", 205 "ofdmWeakSigDetectOff=%d\n",
206 aniState->noiseImmunityLevel, aniState->spurImmunityLevel, 206 aniState->noiseImmunityLevel,
207 !aniState->ofdmWeakSigDetectOff); 207 aniState->spurImmunityLevel,
208 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 208 !aniState->ofdmWeakSigDetectOff);
209 "cckWeakSigThreshold=%d, " 209 ath_print(common, ATH_DBG_ANI,
210 "firstepLevel=%d, listenTime=%d\n", 210 "cckWeakSigThreshold=%d, "
211 aniState->cckWeakSigThreshold, aniState->firstepLevel, 211 "firstepLevel=%d, listenTime=%d\n",
212 aniState->listenTime); 212 aniState->cckWeakSigThreshold,
213 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 213 aniState->firstepLevel,
214 aniState->listenTime);
215 ath_print(common, ATH_DBG_ANI,
214 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 216 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
215 aniState->cycleCount, aniState->ofdmPhyErrCount, 217 aniState->cycleCount,
218 aniState->ofdmPhyErrCount,
216 aniState->cckPhyErrCount); 219 aniState->cckPhyErrCount);
217 220
218 return true; 221 return true;
@@ -231,6 +234,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
231static void ath9k_ani_restart(struct ath_hw *ah) 234static void ath9k_ani_restart(struct ath_hw *ah)
232{ 235{
233 struct ar5416AniState *aniState; 236 struct ar5416AniState *aniState;
237 struct ath_common *common = ath9k_hw_common(ah);
234 238
235 if (!DO_ANI(ah)) 239 if (!DO_ANI(ah))
236 return; 240 return;
@@ -240,24 +244,24 @@ static void ath9k_ani_restart(struct ath_hw *ah)
240 244
241 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 245 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
242 aniState->ofdmPhyErrBase = 0; 246 aniState->ofdmPhyErrBase = 0;
243 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 247 ath_print(common, ATH_DBG_ANI,
244 "OFDM Trigger is too high for hw counters\n"); 248 "OFDM Trigger is too high for hw counters\n");
245 } else { 249 } else {
246 aniState->ofdmPhyErrBase = 250 aniState->ofdmPhyErrBase =
247 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh; 251 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
248 } 252 }
249 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { 253 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
250 aniState->cckPhyErrBase = 0; 254 aniState->cckPhyErrBase = 0;
251 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 255 ath_print(common, ATH_DBG_ANI,
252 "CCK Trigger is too high for hw counters\n"); 256 "CCK Trigger is too high for hw counters\n");
253 } else { 257 } else {
254 aniState->cckPhyErrBase = 258 aniState->cckPhyErrBase =
255 AR_PHY_COUNTMAX - aniState->cckTrigHigh; 259 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
256 } 260 }
257 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 261 ath_print(common, ATH_DBG_ANI,
258 "Writing ofdmbase=%u cckbase=%u\n", 262 "Writing ofdmbase=%u cckbase=%u\n",
259 aniState->ofdmPhyErrBase, 263 aniState->ofdmPhyErrBase,
260 aniState->cckPhyErrBase); 264 aniState->cckPhyErrBase);
261 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); 265 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
262 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); 266 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
263 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 267 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
@@ -271,7 +275,7 @@ static void ath9k_ani_restart(struct ath_hw *ah)
271 275
272static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) 276static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
273{ 277{
274 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 278 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
275 struct ar5416AniState *aniState; 279 struct ar5416AniState *aniState;
276 int32_t rssi; 280 int32_t rssi;
277 281
@@ -343,7 +347,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
343 347
344static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) 348static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
345{ 349{
346 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 350 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
347 struct ar5416AniState *aniState; 351 struct ar5416AniState *aniState;
348 int32_t rssi; 352 int32_t rssi;
349 353
@@ -464,6 +468,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
464{ 468{
465 struct ar5416AniState *aniState; 469 struct ar5416AniState *aniState;
466 struct ath9k_channel *chan = ah->curchan; 470 struct ath9k_channel *chan = ah->curchan;
471 struct ath_common *common = ath9k_hw_common(ah);
467 int index; 472 int index;
468 473
469 if (!DO_ANI(ah)) 474 if (!DO_ANI(ah))
@@ -475,8 +480,8 @@ void ath9k_ani_reset(struct ath_hw *ah)
475 480
476 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION 481 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
477 && ah->opmode != NL80211_IFTYPE_ADHOC) { 482 && ah->opmode != NL80211_IFTYPE_ADHOC) {
478 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 483 ath_print(common, ATH_DBG_ANI,
479 "Reset ANI state opmode %u\n", ah->opmode); 484 "Reset ANI state opmode %u\n", ah->opmode);
480 ah->stats.ast_ani_reset++; 485 ah->stats.ast_ani_reset++;
481 486
482 if (ah->opmode == NL80211_IFTYPE_AP) { 487 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -543,6 +548,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
543 struct ath9k_channel *chan) 548 struct ath9k_channel *chan)
544{ 549{
545 struct ar5416AniState *aniState; 550 struct ar5416AniState *aniState;
551 struct ath_common *common = ath9k_hw_common(ah);
546 int32_t listenTime; 552 int32_t listenTime;
547 u32 phyCnt1, phyCnt2; 553 u32 phyCnt1, phyCnt2;
548 u32 ofdmPhyErrCnt, cckPhyErrCnt; 554 u32 ofdmPhyErrCnt, cckPhyErrCnt;
@@ -569,20 +575,22 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
569 if (phyCnt1 < aniState->ofdmPhyErrBase || 575 if (phyCnt1 < aniState->ofdmPhyErrBase ||
570 phyCnt2 < aniState->cckPhyErrBase) { 576 phyCnt2 < aniState->cckPhyErrBase) {
571 if (phyCnt1 < aniState->ofdmPhyErrBase) { 577 if (phyCnt1 < aniState->ofdmPhyErrBase) {
572 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 578 ath_print(common, ATH_DBG_ANI,
573 "phyCnt1 0x%x, resetting " 579 "phyCnt1 0x%x, resetting "
574 "counter value to 0x%x\n", 580 "counter value to 0x%x\n",
575 phyCnt1, aniState->ofdmPhyErrBase); 581 phyCnt1,
582 aniState->ofdmPhyErrBase);
576 REG_WRITE(ah, AR_PHY_ERR_1, 583 REG_WRITE(ah, AR_PHY_ERR_1,
577 aniState->ofdmPhyErrBase); 584 aniState->ofdmPhyErrBase);
578 REG_WRITE(ah, AR_PHY_ERR_MASK_1, 585 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
579 AR_PHY_ERR_OFDM_TIMING); 586 AR_PHY_ERR_OFDM_TIMING);
580 } 587 }
581 if (phyCnt2 < aniState->cckPhyErrBase) { 588 if (phyCnt2 < aniState->cckPhyErrBase) {
582 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 589 ath_print(common, ATH_DBG_ANI,
583 "phyCnt2 0x%x, resetting " 590 "phyCnt2 0x%x, resetting "
584 "counter value to 0x%x\n", 591 "counter value to 0x%x\n",
585 phyCnt2, aniState->cckPhyErrBase); 592 phyCnt2,
593 aniState->cckPhyErrBase);
586 REG_WRITE(ah, AR_PHY_ERR_2, 594 REG_WRITE(ah, AR_PHY_ERR_2,
587 aniState->cckPhyErrBase); 595 aniState->cckPhyErrBase);
588 REG_WRITE(ah, AR_PHY_ERR_MASK_2, 596 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
@@ -621,10 +629,13 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
621 } 629 }
622 } 630 }
623} 631}
632EXPORT_SYMBOL(ath9k_hw_ani_monitor);
624 633
625void ath9k_enable_mib_counters(struct ath_hw *ah) 634void ath9k_enable_mib_counters(struct ath_hw *ah)
626{ 635{
627 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); 636 struct ath_common *common = ath9k_hw_common(ah);
637
638 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
628 639
629 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 640 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
630 641
@@ -640,7 +651,10 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
640/* Freeze the MIB counters, get the stats and then clear them */ 651/* Freeze the MIB counters, get the stats and then clear them */
641void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 652void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
642{ 653{
643 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); 654 struct ath_common *common = ath9k_hw_common(ah);
655
656 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
657
644 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 658 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
645 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 659 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
646 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 660 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
@@ -653,6 +667,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
653 u32 *rxf_pcnt, 667 u32 *rxf_pcnt,
654 u32 *txf_pcnt) 668 u32 *txf_pcnt)
655{ 669{
670 struct ath_common *common = ath9k_hw_common(ah);
656 static u32 cycles, rx_clear, rx_frame, tx_frame; 671 static u32 cycles, rx_clear, rx_frame, tx_frame;
657 u32 good = 1; 672 u32 good = 1;
658 673
@@ -662,8 +677,8 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
662 u32 cc = REG_READ(ah, AR_CCCNT); 677 u32 cc = REG_READ(ah, AR_CCCNT);
663 678
664 if (cycles == 0 || cycles > cc) { 679 if (cycles == 0 || cycles > cc) {
665 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 680 ath_print(common, ATH_DBG_ANI,
666 "cycle counter wrap. ExtBusy = 0\n"); 681 "cycle counter wrap. ExtBusy = 0\n");
667 good = 0; 682 good = 0;
668 } else { 683 } else {
669 u32 cc_d = cc - cycles; 684 u32 cc_d = cc - cycles;
@@ -742,6 +757,7 @@ void ath9k_hw_procmibevent(struct ath_hw *ah)
742 ath9k_ani_restart(ah); 757 ath9k_ani_restart(ah);
743 } 758 }
744} 759}
760EXPORT_SYMBOL(ath9k_hw_procmibevent);
745 761
746void ath9k_hw_ani_setup(struct ath_hw *ah) 762void ath9k_hw_ani_setup(struct ath_hw *ah)
747{ 763{
@@ -762,9 +778,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
762 778
763void ath9k_hw_ani_init(struct ath_hw *ah) 779void ath9k_hw_ani_init(struct ath_hw *ah)
764{ 780{
781 struct ath_common *common = ath9k_hw_common(ah);
765 int i; 782 int i;
766 783
767 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n"); 784 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
768 785
769 memset(ah->ani, 0, sizeof(ah->ani)); 786 memset(ah->ani, 0, sizeof(ah->ani));
770 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { 787 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
@@ -786,11 +803,11 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
786 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 803 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
787 } 804 }
788 805
789 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 806 ath_print(common, ATH_DBG_ANI,
790 "Setting OfdmErrBase = 0x%08x\n", 807 "Setting OfdmErrBase = 0x%08x\n",
791 ah->ani[0].ofdmPhyErrBase); 808 ah->ani[0].ofdmPhyErrBase);
792 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 809 ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
793 ah->ani[0].cckPhyErrBase); 810 ah->ani[0].cckPhyErrBase);
794 811
795 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); 812 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
796 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); 813 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
@@ -803,7 +820,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
803 820
804void ath9k_hw_ani_disable(struct ath_hw *ah) 821void ath9k_hw_ani_disable(struct ath_hw *ah)
805{ 822{
806 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n"); 823 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, "Disabling ANI\n");
807 824
808 ath9k_hw_disable_mib_counters(ah); 825 ath9k_hw_disable_mib_counters(ah);
809 REG_WRITE(ah, AR_PHY_ERR_1, 0); 826 REG_WRITE(ah, AR_PHY_ERR_1, 0);
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 1d59f10f68da..83c7ea4c007f 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -19,24 +19,25 @@
19 19
20#include <linux/etherdevice.h> 20#include <linux/etherdevice.h>
21#include <linux/device.h> 21#include <linux/device.h>
22#include <net/mac80211.h>
23#include <linux/leds.h> 22#include <linux/leds.h>
24 23
25#include "hw.h"
26#include "rc.h"
27#include "debug.h" 24#include "debug.h"
28#include "../ath.h" 25#include "common.h"
29#include "btcoex.h" 26
27/*
28 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
29 * should rely on this file or its contents.
30 */
30 31
31struct ath_node; 32struct ath_node;
32 33
33/* Macro to expand scalars to 64-bit objects */ 34/* Macro to expand scalars to 64-bit objects */
34 35
35#define ito64(x) (sizeof(x) == 8) ? \ 36#define ito64(x) (sizeof(x) == 1) ? \
36 (((unsigned long long int)(x)) & (0xff)) : \ 37 (((unsigned long long int)(x)) & (0xff)) : \
37 (sizeof(x) == 16) ? \ 38 (sizeof(x) == 2) ? \
38 (((unsigned long long int)(x)) & 0xffff) : \ 39 (((unsigned long long int)(x)) & 0xffff) : \
39 ((sizeof(x) == 32) ? \ 40 ((sizeof(x) == 4) ? \
40 (((unsigned long long int)(x)) & 0xffffffff) : \ 41 (((unsigned long long int)(x)) & 0xffffffff) : \
41 (unsigned long long int)(x)) 42 (unsigned long long int)(x))
42 43
@@ -54,15 +55,11 @@ struct ath_node;
54 55
55#define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 56#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
56 57
57#define ASSERT(exp) BUG_ON(!(exp))
58
59#define TSF_TO_TU(_h,_l) \ 58#define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 59 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
61 60
62#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 61#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
63 62
64static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
65
66struct ath_config { 63struct ath_config {
67 u32 ath_aggr_prot; 64 u32 ath_aggr_prot;
68 u16 txpowlimit; 65 u16 txpowlimit;
@@ -103,18 +100,6 @@ enum buffer_type {
103 BUF_XRETRY = BIT(5), 100 BUF_XRETRY = BIT(5),
104}; 101};
105 102
106struct ath_buf_state {
107 int bfs_nframes;
108 u16 bfs_al;
109 u16 bfs_frmlen;
110 int bfs_seqno;
111 int bfs_tidno;
112 int bfs_retries;
113 u8 bf_type;
114 u32 bfs_keyix;
115 enum ath9k_key_type bfs_keytype;
116};
117
118#define bf_nframes bf_state.bfs_nframes 103#define bf_nframes bf_state.bfs_nframes
119#define bf_al bf_state.bfs_al 104#define bf_al bf_state.bfs_al
120#define bf_frmlen bf_state.bfs_frmlen 105#define bf_frmlen bf_state.bfs_frmlen
@@ -129,21 +114,6 @@ struct ath_buf_state {
129#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 114#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
130#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 115#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
131 116
132struct ath_buf {
133 struct list_head list;
134 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
135 an aggregate) */
136 struct ath_buf *bf_next; /* next subframe in the aggregate */
137 struct sk_buff *bf_mpdu; /* enclosing frame structure */
138 struct ath_desc *bf_desc; /* virtual addr of desc */
139 dma_addr_t bf_daddr; /* physical addr of desc */
140 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
141 bool bf_stale;
142 u16 bf_flags;
143 struct ath_buf_state bf_state;
144 dma_addr_t bf_dmacontext;
145};
146
147struct ath_descdma { 117struct ath_descdma {
148 struct ath_desc *dd_desc; 118 struct ath_desc *dd_desc;
149 dma_addr_t dd_desc_paddr; 119 dma_addr_t dd_desc_paddr;
@@ -163,13 +133,9 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
163 133
164#define ATH_MAX_ANTENNA 3 134#define ATH_MAX_ANTENNA 3
165#define ATH_RXBUF 512 135#define ATH_RXBUF 512
166#define WME_NUM_TID 16
167#define ATH_TXBUF 512 136#define ATH_TXBUF 512
168#define ATH_TXMAXTRY 13 137#define ATH_TXMAXTRY 13
169#define ATH_MGT_TXMAXTRY 4 138#define ATH_MGT_TXMAXTRY 4
170#define WME_BA_BMP_SIZE 64
171#define WME_MAX_BA WME_BA_BMP_SIZE
172#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
173 139
174#define TID_TO_WME_AC(_tid) \ 140#define TID_TO_WME_AC(_tid) \
175 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 141 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
@@ -177,12 +143,6 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
177 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 143 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
178 WME_AC_VO) 144 WME_AC_VO)
179 145
180#define WME_AC_BE 0
181#define WME_AC_BK 1
182#define WME_AC_VI 2
183#define WME_AC_VO 3
184#define WME_NUM_AC 4
185
186#define ADDBA_EXCHANGE_ATTEMPTS 10 146#define ADDBA_EXCHANGE_ATTEMPTS 10
187#define ATH_AGGR_DELIM_SZ 4 147#define ATH_AGGR_DELIM_SZ 4
188#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 148#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
@@ -191,7 +151,6 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
191/* minimum h/w qdepth to be sustained to maximize aggregation */ 151/* minimum h/w qdepth to be sustained to maximize aggregation */
192#define ATH_AGGR_MIN_QDEPTH 2 152#define ATH_AGGR_MIN_QDEPTH 2
193#define ATH_AMPDU_SUBFRAME_DEFAULT 32 153#define ATH_AMPDU_SUBFRAME_DEFAULT 32
194#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
195 154
196#define IEEE80211_SEQ_SEQ_SHIFT 4 155#define IEEE80211_SEQ_SEQ_SHIFT 4
197#define IEEE80211_SEQ_MAX 4096 156#define IEEE80211_SEQ_MAX 4096
@@ -238,18 +197,8 @@ struct ath_txq {
238 struct list_head axq_q; 197 struct list_head axq_q;
239 spinlock_t axq_lock; 198 spinlock_t axq_lock;
240 u32 axq_depth; 199 u32 axq_depth;
241 u8 axq_aggr_depth;
242 bool stopped; 200 bool stopped;
243 bool axq_tx_inprogress; 201 bool axq_tx_inprogress;
244 struct ath_buf *axq_linkbuf;
245
246 /* first desc of the last descriptor that contains CTS */
247 struct ath_desc *axq_lastdsWithCTS;
248
249 /* final desc of the gating desc that determines whether
250 lastdsWithCTS has been DMA'ed or not */
251 struct ath_desc *axq_gatingds;
252
253 struct list_head axq_acq; 202 struct list_head axq_acq;
254}; 203};
255 204
@@ -257,30 +206,6 @@ struct ath_txq {
257#define AGGR_ADDBA_COMPLETE BIT(2) 206#define AGGR_ADDBA_COMPLETE BIT(2)
258#define AGGR_ADDBA_PROGRESS BIT(3) 207#define AGGR_ADDBA_PROGRESS BIT(3)
259 208
260struct ath_atx_tid {
261 struct list_head list;
262 struct list_head buf_q;
263 struct ath_node *an;
264 struct ath_atx_ac *ac;
265 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
266 u16 seq_start;
267 u16 seq_next;
268 u16 baw_size;
269 int tidno;
270 int baw_head; /* first un-acked tx buffer */
271 int baw_tail; /* next unused tx buffer slot */
272 int sched;
273 int paused;
274 u8 state;
275};
276
277struct ath_atx_ac {
278 int sched;
279 int qnum;
280 struct list_head list;
281 struct list_head tid_q;
282};
283
284struct ath_tx_control { 209struct ath_tx_control {
285 struct ath_txq *txq; 210 struct ath_txq *txq;
286 int if_id; 211 int if_id;
@@ -291,30 +216,6 @@ struct ath_tx_control {
291#define ATH_TX_XRETRY 0x02 216#define ATH_TX_XRETRY 0x02
292#define ATH_TX_BAR 0x04 217#define ATH_TX_BAR 0x04
293 218
294#define ATH_RSSI_LPF_LEN 10
295#define RSSI_LPF_THRESHOLD -20
296#define ATH9K_RSSI_BAD 0x80
297#define ATH_RSSI_EP_MULTIPLIER (1<<7)
298#define ATH_EP_MUL(x, mul) ((x) * (mul))
299#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
300#define ATH_LPF_RSSI(x, y, len) \
301 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
302#define ATH_RSSI_LPF(x, y) do { \
303 if ((y) >= RSSI_LPF_THRESHOLD) \
304 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
305} while (0)
306#define ATH_EP_RND(x, mul) \
307 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
308
309struct ath_node {
310 struct ath_softc *an_sc;
311 struct ath_atx_tid tid[WME_NUM_TID];
312 struct ath_atx_ac ac[WME_NUM_AC];
313 u16 maxampdu;
314 u8 mpdudensity;
315 int last_rssi;
316};
317
318struct ath_tx { 219struct ath_tx {
319 u16 seq_no; 220 u16 seq_no;
320 u32 txqsetup; 221 u32 txqsetup;
@@ -329,7 +230,6 @@ struct ath_rx {
329 u8 defant; 230 u8 defant;
330 u8 rxotherant; 231 u8 rxotherant;
331 u32 *rxlink; 232 u32 *rxlink;
332 int bufsize;
333 unsigned int rxfilter; 233 unsigned int rxfilter;
334 spinlock_t rxflushlock; 234 spinlock_t rxflushlock;
335 spinlock_t rxbuflock; 235 spinlock_t rxbuflock;
@@ -367,6 +267,7 @@ void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
367 u16 tid, u16 *ssn); 267 u16 tid, u16 *ssn);
368void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 268void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
369void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 269void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
270void ath9k_enable_ps(struct ath_softc *sc);
370 271
371/********/ 272/********/
372/* VIFs */ 273/* VIFs */
@@ -427,9 +328,9 @@ struct ath_beacon {
427 328
428void ath_beacon_tasklet(unsigned long data); 329void ath_beacon_tasklet(unsigned long data);
429void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 330void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
430int ath_beaconq_setup(struct ath_hw *ah);
431int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); 331int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
432void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 332void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
333int ath_beaconq_config(struct ath_softc *sc);
433 334
434/*******/ 335/*******/
435/* ANI */ 336/* ANI */
@@ -441,16 +342,37 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
441#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 342#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
442#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 343#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
443 344
444struct ath_ani { 345void ath_ani_calibrate(unsigned long data);
445 bool caldone; 346
446 int16_t noise_floor; 347/**********/
447 unsigned int longcal_timer; 348/* BTCOEX */
448 unsigned int shortcal_timer; 349/**********/
449 unsigned int resetcal_timer; 350
450 unsigned int checkani_timer; 351/* Defines the BT AR_BT_COEX_WGHT used */
451 struct timer_list timer; 352enum ath_stomp_type {
353 ATH_BTCOEX_NO_STOMP,
354 ATH_BTCOEX_STOMP_ALL,
355 ATH_BTCOEX_STOMP_LOW,
356 ATH_BTCOEX_STOMP_NONE
452}; 357};
453 358
359struct ath_btcoex {
360 bool hw_timer_enabled;
361 spinlock_t btcoex_lock;
362 struct timer_list period_timer; /* Timer for BT period */
363 u32 bt_priority_cnt;
364 unsigned long bt_priority_time;
365 int bt_stomp_type; /* Types of BT stomping */
366 u32 btcoex_no_stomp; /* in usec */
367 u32 btcoex_period; /* in usec */
368 u32 btscan_no_stomp; /* in usec */
369 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
370};
371
372int ath_init_btcoex_timer(struct ath_softc *sc);
373void ath9k_btcoex_timer_resume(struct ath_softc *sc);
374void ath9k_btcoex_timer_pause(struct ath_softc *sc);
375
454/********************/ 376/********************/
455/* LED Control */ 377/* LED Control */
456/********************/ 378/********************/
@@ -475,6 +397,9 @@ struct ath_led {
475 bool registered; 397 bool registered;
476}; 398};
477 399
400void ath_init_leds(struct ath_softc *sc);
401void ath_deinit_leds(struct ath_softc *sc);
402
478/********************/ 403/********************/
479/* Main driver core */ 404/* Main driver core */
480/********************/ 405/********************/
@@ -484,61 +409,46 @@ struct ath_led {
484 * Used when PCI device not fully initialized by bootrom/BIOS 409 * Used when PCI device not fully initialized by bootrom/BIOS
485*/ 410*/
486#define DEFAULT_CACHELINE 32 411#define DEFAULT_CACHELINE 32
487#define ATH_DEFAULT_NOISE_FLOOR -95
488#define ATH_REGCLASSIDS_MAX 10 412#define ATH_REGCLASSIDS_MAX 10
489#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 413#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
490#define ATH_MAX_SW_RETRIES 10 414#define ATH_MAX_SW_RETRIES 10
491#define ATH_CHAN_MAX 255 415#define ATH_CHAN_MAX 255
492#define IEEE80211_WEP_NKID 4 /* number of key ids */ 416#define IEEE80211_WEP_NKID 4 /* number of key ids */
493 417
494/*
495 * The key cache is used for h/w cipher state and also for
496 * tracking station state such as the current tx antenna.
497 * We also setup a mapping table between key cache slot indices
498 * and station state to short-circuit node lookups on rx.
499 * Different parts have different size key caches. We handle
500 * up to ATH_KEYMAX entries (could dynamically allocate state).
501 */
502#define ATH_KEYMAX 128 /* max key cache size we handle */
503
504#define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 418#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
505#define ATH_RSSI_DUMMY_MARKER 0x127
506#define ATH_RATE_DUMMY_MARKER 0 419#define ATH_RATE_DUMMY_MARKER 0
507 420
508#define SC_OP_INVALID BIT(0) 421#define SC_OP_INVALID BIT(0)
509#define SC_OP_BEACONS BIT(1) 422#define SC_OP_BEACONS BIT(1)
510#define SC_OP_RXAGGR BIT(2) 423#define SC_OP_RXAGGR BIT(2)
511#define SC_OP_TXAGGR BIT(3) 424#define SC_OP_TXAGGR BIT(3)
512#define SC_OP_FULL_RESET BIT(4) 425#define SC_OP_FULL_RESET BIT(4)
513#define SC_OP_PREAMBLE_SHORT BIT(5) 426#define SC_OP_PREAMBLE_SHORT BIT(5)
514#define SC_OP_PROTECT_ENABLE BIT(6) 427#define SC_OP_PROTECT_ENABLE BIT(6)
515#define SC_OP_RXFLUSH BIT(7) 428#define SC_OP_RXFLUSH BIT(7)
516#define SC_OP_LED_ASSOCIATED BIT(8) 429#define SC_OP_LED_ASSOCIATED BIT(8)
517#define SC_OP_WAIT_FOR_BEACON BIT(12) 430#define SC_OP_LED_ON BIT(9)
518#define SC_OP_LED_ON BIT(13) 431#define SC_OP_SCANNING BIT(10)
519#define SC_OP_SCANNING BIT(14) 432#define SC_OP_TSF_RESET BIT(11)
520#define SC_OP_TSF_RESET BIT(15) 433#define SC_OP_BT_PRIORITY_DETECTED BIT(12)
521#define SC_OP_WAIT_FOR_CAB BIT(16) 434#define SC_OP_BT_SCAN BIT(13)
522#define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17) 435
523#define SC_OP_WAIT_FOR_TX_ACK BIT(18) 436/* Powersave flags */
524#define SC_OP_BEACON_SYNC BIT(19) 437#define PS_WAIT_FOR_BEACON BIT(0)
525#define SC_OP_BTCOEX_ENABLED BIT(20) 438#define PS_WAIT_FOR_CAB BIT(1)
526#define SC_OP_BT_PRIORITY_DETECTED BIT(21) 439#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
527 440#define PS_WAIT_FOR_TX_ACK BIT(3)
528struct ath_bus_ops { 441#define PS_BEACON_SYNC BIT(4)
529 void (*read_cachesize)(struct ath_softc *sc, int *csz); 442#define PS_NULLFUNC_COMPLETED BIT(5)
530 void (*cleanup)(struct ath_softc *sc); 443#define PS_ENABLED BIT(6)
531 bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
532};
533 444
534struct ath_wiphy; 445struct ath_wiphy;
446struct ath_rate_table;
535 447
536struct ath_softc { 448struct ath_softc {
537 struct ieee80211_hw *hw; 449 struct ieee80211_hw *hw;
538 struct device *dev; 450 struct device *dev;
539 451
540 struct ath_common common;
541
542 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ 452 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
543 struct ath_wiphy *pri_wiphy; 453 struct ath_wiphy *pri_wiphy;
544 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may 454 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
@@ -561,36 +471,26 @@ struct ath_softc {
561 int irq; 471 int irq;
562 spinlock_t sc_resetlock; 472 spinlock_t sc_resetlock;
563 spinlock_t sc_serial_rw; 473 spinlock_t sc_serial_rw;
564 spinlock_t ani_lock;
565 spinlock_t sc_pm_lock; 474 spinlock_t sc_pm_lock;
566 struct mutex mutex; 475 struct mutex mutex;
567 476
568 u8 curbssid[ETH_ALEN];
569 u8 bssidmask[ETH_ALEN];
570 u32 intrstatus; 477 u32 intrstatus;
571 u32 sc_flags; /* SC_OP_* */ 478 u32 sc_flags; /* SC_OP_* */
479 u16 ps_flags; /* PS_* */
572 u16 curtxpow; 480 u16 curtxpow;
573 u16 curaid;
574 u8 nbcnvifs; 481 u8 nbcnvifs;
575 u16 nvifs; 482 u16 nvifs;
576 u8 tx_chainmask;
577 u8 rx_chainmask;
578 u32 keymax;
579 DECLARE_BITMAP(keymap, ATH_KEYMAX);
580 u8 splitmic;
581 bool ps_enabled; 483 bool ps_enabled;
484 bool ps_idle;
582 unsigned long ps_usecount; 485 unsigned long ps_usecount;
583 enum ath9k_int imask; 486 enum ath9k_int imask;
584 enum ath9k_ht_extprotspacing ht_extprotspacing;
585 enum ath9k_ht_macmode tx_chan_width;
586 487
587 struct ath_config config; 488 struct ath_config config;
588 struct ath_rx rx; 489 struct ath_rx rx;
589 struct ath_tx tx; 490 struct ath_tx tx;
590 struct ath_beacon beacon; 491 struct ath_beacon beacon;
591 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
592 const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
593 const struct ath_rate_table *cur_rate_table; 492 const struct ath_rate_table *cur_rate_table;
493 enum wireless_mode cur_rate_mode;
594 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 494 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
595 495
596 struct ath_led radio_led; 496 struct ath_led radio_led;
@@ -605,14 +505,12 @@ struct ath_softc {
605 505
606 int beacon_interval; 506 int beacon_interval;
607 507
608 struct ath_ani ani; 508#ifdef CONFIG_ATH9K_DEBUGFS
609#ifdef CONFIG_ATH9K_DEBUG
610 struct ath9k_debug debug; 509 struct ath9k_debug debug;
611#endif 510#endif
612 struct ath_bus_ops *bus_ops;
613 struct ath_beacon_config cur_beacon_conf; 511 struct ath_beacon_config cur_beacon_conf;
614 struct delayed_work tx_complete_work; 512 struct delayed_work tx_complete_work;
615 struct ath_btcoex_info btcoex_info; 513 struct ath_btcoex btcoex;
616}; 514};
617 515
618struct ath_wiphy { 516struct ath_wiphy {
@@ -625,51 +523,41 @@ struct ath_wiphy {
625 ATH_WIPHY_PAUSED, 523 ATH_WIPHY_PAUSED,
626 ATH_WIPHY_SCAN, 524 ATH_WIPHY_SCAN,
627 } state; 525 } state;
526 bool idle;
628 int chan_idx; 527 int chan_idx;
629 int chan_is_ht; 528 int chan_is_ht;
630}; 529};
631 530
531void ath9k_tasklet(unsigned long data);
632int ath_reset(struct ath_softc *sc, bool retry_tx); 532int ath_reset(struct ath_softc *sc, bool retry_tx);
633int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); 533int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
634int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); 534int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
635int ath_cabq_update(struct ath_softc *); 535int ath_cabq_update(struct ath_softc *);
636 536
637static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 537static inline void ath_read_cachesize(struct ath_common *common, int *csz)
638{ 538{
639 return &ah->ah_sc->common; 539 common->bus_ops->read_cachesize(common, csz);
640}
641
642static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
643{
644 return &(ath9k_hw_common(ah)->regulatory);
645}
646
647static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
648{
649 sc->bus_ops->read_cachesize(sc, csz);
650}
651
652static inline void ath_bus_cleanup(struct ath_softc *sc)
653{
654 sc->bus_ops->cleanup(sc);
655} 540}
656 541
657extern struct ieee80211_ops ath9k_ops; 542extern struct ieee80211_ops ath9k_ops;
543extern int modparam_nohwcrypt;
658 544
659irqreturn_t ath_isr(int irq, void *dev); 545irqreturn_t ath_isr(int irq, void *dev);
660void ath_cleanup(struct ath_softc *sc); 546int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
661int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid); 547 const struct ath_bus_ops *bus_ops);
662void ath_detach(struct ath_softc *sc); 548void ath9k_deinit_device(struct ath_softc *sc);
663const char *ath_mac_bb_name(u32 mac_bb_version); 549const char *ath_mac_bb_name(u32 mac_bb_version);
664const char *ath_rf_name(u16 rf_version); 550const char *ath_rf_name(u16 rf_version);
665void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 551void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
666void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 552void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
667 struct ath9k_channel *ichan); 553 struct ath9k_channel *ichan);
668void ath_update_chainmask(struct ath_softc *sc, int is_ht); 554void ath_update_chainmask(struct ath_softc *sc, int is_ht);
669int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 555int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
670 struct ath9k_channel *hchan); 556 struct ath9k_channel *hchan);
671void ath_radio_enable(struct ath_softc *sc); 557
672void ath_radio_disable(struct ath_softc *sc); 558void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
559void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
560bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
673 561
674#ifdef CONFIG_PCI 562#ifdef CONFIG_PCI
675int ath_pci_init(void); 563int ath_pci_init(void);
@@ -705,9 +593,14 @@ void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
705bool ath9k_wiphy_scanning(struct ath_softc *sc); 593bool ath9k_wiphy_scanning(struct ath_softc *sc);
706void ath9k_wiphy_work(struct work_struct *work); 594void ath9k_wiphy_work(struct work_struct *work);
707bool ath9k_all_wiphys_idle(struct ath_softc *sc); 595bool ath9k_all_wiphys_idle(struct ath_softc *sc);
596void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
708 597
709void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val); 598void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
710unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset); 599void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
711 600
712int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); 601int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
602
603void ath_start_rfkill_poll(struct ath_softc *sc);
604extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
605
713#endif /* ATH9K_H */ 606#endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 45c4ea57616b..b4a31a43a62c 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -23,10 +23,12 @@
23 * the operating mode of the station (AP or AdHoc). Parameters are AIFS 23 * the operating mode of the station (AP or AdHoc). Parameters are AIFS
24 * settings and channel width min/max 24 * settings and channel width min/max
25*/ 25*/
26static int ath_beaconq_config(struct ath_softc *sc) 26int ath_beaconq_config(struct ath_softc *sc)
27{ 27{
28 struct ath_hw *ah = sc->sc_ah; 28 struct ath_hw *ah = sc->sc_ah;
29 struct ath9k_tx_queue_info qi; 29 struct ath_common *common = ath9k_hw_common(ah);
30 struct ath9k_tx_queue_info qi, qi_be;
31 int qnum;
30 32
31 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); 33 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
32 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { 34 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
@@ -36,14 +38,17 @@ static int ath_beaconq_config(struct ath_softc *sc)
36 qi.tqi_cwmax = 0; 38 qi.tqi_cwmax = 0;
37 } else { 39 } else {
38 /* Adhoc mode; important thing is to use 2x cwmin. */ 40 /* Adhoc mode; important thing is to use 2x cwmin. */
39 qi.tqi_aifs = sc->beacon.beacon_qi.tqi_aifs; 41 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA,
40 qi.tqi_cwmin = 2*sc->beacon.beacon_qi.tqi_cwmin; 42 ATH9K_WME_AC_BE);
41 qi.tqi_cwmax = sc->beacon.beacon_qi.tqi_cwmax; 43 ath9k_hw_get_txq_props(ah, qnum, &qi_be);
44 qi.tqi_aifs = qi_be.tqi_aifs;
45 qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
46 qi.tqi_cwmax = qi_be.tqi_cwmax;
42 } 47 }
43 48
44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 49 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
45 DPRINTF(sc, ATH_DBG_FATAL, 50 ath_print(common, ATH_DBG_FATAL,
46 "Unable to update h/w beacon queue parameters\n"); 51 "Unable to update h/w beacon queue parameters\n");
47 return 0; 52 return 0;
48 } else { 53 } else {
49 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); 54 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -57,15 +62,16 @@ static int ath_beaconq_config(struct ath_softc *sc)
57 * Beacons are always sent out at the lowest rate, and are not retried. 62 * Beacons are always sent out at the lowest rate, and are not retried.
58*/ 63*/
59static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp, 64static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
60 struct ath_buf *bf) 65 struct ath_buf *bf, int rateidx)
61{ 66{
62 struct sk_buff *skb = bf->bf_mpdu; 67 struct sk_buff *skb = bf->bf_mpdu;
63 struct ath_hw *ah = sc->sc_ah; 68 struct ath_hw *ah = sc->sc_ah;
69 struct ath_common *common = ath9k_hw_common(ah);
64 struct ath_desc *ds; 70 struct ath_desc *ds;
65 struct ath9k_11n_rate_series series[4]; 71 struct ath9k_11n_rate_series series[4];
66 const struct ath_rate_table *rt;
67 int flags, antenna, ctsrate = 0, ctsduration = 0; 72 int flags, antenna, ctsrate = 0, ctsduration = 0;
68 u8 rate; 73 struct ieee80211_supported_band *sband;
74 u8 rate = 0;
69 75
70 ds = bf->bf_desc; 76 ds = bf->bf_desc;
71 flags = ATH9K_TXDESC_NOACK; 77 flags = ATH9K_TXDESC_NOACK;
@@ -89,10 +95,10 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
89 95
90 ds->ds_data = bf->bf_buf_addr; 96 ds->ds_data = bf->bf_buf_addr;
91 97
92 rt = sc->cur_rate_table; 98 sband = &sc->sbands[common->hw->conf.channel->band];
93 rate = rt->info[0].ratecode; 99 rate = sband->bitrates[rateidx].hw_value;
94 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 100 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
95 rate |= rt->info[0].short_preamble; 101 rate |= sband->bitrates[rateidx].hw_value_short;
96 102
97 ath9k_hw_set11n_txdesc(ah, ds, skb->len + FCS_LEN, 103 ath9k_hw_set11n_txdesc(ah, ds, skb->len + FCS_LEN,
98 ATH9K_PKT_TYPE_BEACON, 104 ATH9K_PKT_TYPE_BEACON,
@@ -108,7 +114,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
108 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); 114 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
109 series[0].Tries = 1; 115 series[0].Tries = 1;
110 series[0].Rate = rate; 116 series[0].Rate = rate;
111 series[0].ChSel = sc->tx_chainmask; 117 series[0].ChSel = common->tx_chainmask;
112 series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; 118 series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
113 ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration, 119 ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
114 series, 4, 0); 120 series, 4, 0);
@@ -119,6 +125,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
119{ 125{
120 struct ath_wiphy *aphy = hw->priv; 126 struct ath_wiphy *aphy = hw->priv;
121 struct ath_softc *sc = aphy->sc; 127 struct ath_softc *sc = aphy->sc;
128 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
122 struct ath_buf *bf; 129 struct ath_buf *bf;
123 struct ath_vif *avp; 130 struct ath_vif *avp;
124 struct sk_buff *skb; 131 struct sk_buff *skb;
@@ -172,7 +179,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
172 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 179 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
173 dev_kfree_skb_any(skb); 180 dev_kfree_skb_any(skb);
174 bf->bf_mpdu = NULL; 181 bf->bf_mpdu = NULL;
175 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n"); 182 ath_print(common, ATH_DBG_FATAL,
183 "dma_mapping_error on beaconing\n");
176 return NULL; 184 return NULL;
177 } 185 }
178 186
@@ -192,13 +200,13 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
192 200
193 if (skb && cabq_depth) { 201 if (skb && cabq_depth) {
194 if (sc->nvifs > 1) { 202 if (sc->nvifs > 1) {
195 DPRINTF(sc, ATH_DBG_BEACON, 203 ath_print(common, ATH_DBG_BEACON,
196 "Flushing previous cabq traffic\n"); 204 "Flushing previous cabq traffic\n");
197 ath_draintxq(sc, cabq, false); 205 ath_draintxq(sc, cabq, false);
198 } 206 }
199 } 207 }
200 208
201 ath_beacon_setup(sc, avp, bf); 209 ath_beacon_setup(sc, avp, bf, info->control.rates[0].idx);
202 210
203 while (skb) { 211 while (skb) {
204 ath_tx_cabq(hw, skb); 212 ath_tx_cabq(hw, skb);
@@ -216,6 +224,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
216 struct ieee80211_vif *vif) 224 struct ieee80211_vif *vif)
217{ 225{
218 struct ath_hw *ah = sc->sc_ah; 226 struct ath_hw *ah = sc->sc_ah;
227 struct ath_common *common = ath9k_hw_common(ah);
219 struct ath_buf *bf; 228 struct ath_buf *bf;
220 struct ath_vif *avp; 229 struct ath_vif *avp;
221 struct sk_buff *skb; 230 struct sk_buff *skb;
@@ -228,30 +237,19 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
228 bf = avp->av_bcbuf; 237 bf = avp->av_bcbuf;
229 skb = bf->bf_mpdu; 238 skb = bf->bf_mpdu;
230 239
231 ath_beacon_setup(sc, avp, bf); 240 ath_beacon_setup(sc, avp, bf, 0);
232 241
233 /* NB: caller is known to have already stopped tx dma */ 242 /* NB: caller is known to have already stopped tx dma */
234 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr); 243 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
235 ath9k_hw_txstart(ah, sc->beacon.beaconq); 244 ath9k_hw_txstart(ah, sc->beacon.beaconq);
236 DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", 245 ath_print(common, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
237 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); 246 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
238}
239
240int ath_beaconq_setup(struct ath_hw *ah)
241{
242 struct ath9k_tx_queue_info qi;
243
244 memset(&qi, 0, sizeof(qi));
245 qi.tqi_aifs = 1;
246 qi.tqi_cwmin = 0;
247 qi.tqi_cwmax = 0;
248 /* NB: don't enable any interrupts */
249 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
250} 247}
251 248
252int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) 249int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
253{ 250{
254 struct ath_softc *sc = aphy->sc; 251 struct ath_softc *sc = aphy->sc;
252 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
255 struct ath_vif *avp; 253 struct ath_vif *avp;
256 struct ath_buf *bf; 254 struct ath_buf *bf;
257 struct sk_buff *skb; 255 struct sk_buff *skb;
@@ -309,7 +307,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
309 /* NB: the beacon data buffer must be 32-bit aligned. */ 307 /* NB: the beacon data buffer must be 32-bit aligned. */
310 skb = ieee80211_beacon_get(sc->hw, vif); 308 skb = ieee80211_beacon_get(sc->hw, vif);
311 if (skb == NULL) { 309 if (skb == NULL) {
312 DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n"); 310 ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
313 return -ENOMEM; 311 return -ENOMEM;
314 } 312 }
315 313
@@ -333,9 +331,10 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
333 tsfadjust = intval * avp->av_bslot / ATH_BCBUF; 331 tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
334 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); 332 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
335 333
336 DPRINTF(sc, ATH_DBG_BEACON, 334 ath_print(common, ATH_DBG_BEACON,
337 "stagger beacons, bslot %d intval %u tsfadjust %llu\n", 335 "stagger beacons, bslot %d intval "
338 avp->av_bslot, intval, (unsigned long long)tsfadjust); 336 "%u tsfadjust %llu\n",
337 avp->av_bslot, intval, (unsigned long long)tsfadjust);
339 338
340 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = 339 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
341 avp->tsf_adjust; 340 avp->tsf_adjust;
@@ -349,8 +348,8 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
349 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 348 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
350 dev_kfree_skb_any(skb); 349 dev_kfree_skb_any(skb);
351 bf->bf_mpdu = NULL; 350 bf->bf_mpdu = NULL;
352 DPRINTF(sc, ATH_DBG_FATAL, 351 ath_print(common, ATH_DBG_FATAL,
353 "dma_mapping_error on beacon alloc\n"); 352 "dma_mapping_error on beacon alloc\n");
354 return -ENOMEM; 353 return -ENOMEM;
355 } 354 }
356 355
@@ -386,6 +385,7 @@ void ath_beacon_tasklet(unsigned long data)
386{ 385{
387 struct ath_softc *sc = (struct ath_softc *)data; 386 struct ath_softc *sc = (struct ath_softc *)data;
388 struct ath_hw *ah = sc->sc_ah; 387 struct ath_hw *ah = sc->sc_ah;
388 struct ath_common *common = ath9k_hw_common(ah);
389 struct ath_buf *bf = NULL; 389 struct ath_buf *bf = NULL;
390 struct ieee80211_vif *vif; 390 struct ieee80211_vif *vif;
391 struct ath_wiphy *aphy; 391 struct ath_wiphy *aphy;
@@ -405,12 +405,12 @@ void ath_beacon_tasklet(unsigned long data)
405 sc->beacon.bmisscnt++; 405 sc->beacon.bmisscnt++;
406 406
407 if (sc->beacon.bmisscnt < BSTUCK_THRESH) { 407 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
408 DPRINTF(sc, ATH_DBG_BEACON, 408 ath_print(common, ATH_DBG_BEACON,
409 "missed %u consecutive beacons\n", 409 "missed %u consecutive beacons\n",
410 sc->beacon.bmisscnt); 410 sc->beacon.bmisscnt);
411 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 411 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
412 DPRINTF(sc, ATH_DBG_BEACON, 412 ath_print(common, ATH_DBG_BEACON,
413 "beacon is officially stuck\n"); 413 "beacon is officially stuck\n");
414 sc->sc_flags |= SC_OP_TSF_RESET; 414 sc->sc_flags |= SC_OP_TSF_RESET;
415 ath_reset(sc, false); 415 ath_reset(sc, false);
416 } 416 }
@@ -419,9 +419,9 @@ void ath_beacon_tasklet(unsigned long data)
419 } 419 }
420 420
421 if (sc->beacon.bmisscnt != 0) { 421 if (sc->beacon.bmisscnt != 0) {
422 DPRINTF(sc, ATH_DBG_BEACON, 422 ath_print(common, ATH_DBG_BEACON,
423 "resume beacon xmit after %u misses\n", 423 "resume beacon xmit after %u misses\n",
424 sc->beacon.bmisscnt); 424 sc->beacon.bmisscnt);
425 sc->beacon.bmisscnt = 0; 425 sc->beacon.bmisscnt = 0;
426 } 426 }
427 427
@@ -447,9 +447,9 @@ void ath_beacon_tasklet(unsigned long data)
447 vif = sc->beacon.bslot[slot]; 447 vif = sc->beacon.bslot[slot];
448 aphy = sc->beacon.bslot_aphy[slot]; 448 aphy = sc->beacon.bslot_aphy[slot];
449 449
450 DPRINTF(sc, ATH_DBG_BEACON, 450 ath_print(common, ATH_DBG_BEACON,
451 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", 451 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
452 slot, tsf, tsftu, intval, vif); 452 slot, tsf, tsftu, intval, vif);
453 453
454 bfaddr = 0; 454 bfaddr = 0;
455 if (vif) { 455 if (vif) {
@@ -480,7 +480,8 @@ void ath_beacon_tasklet(unsigned long data)
480 sc->beacon.updateslot = COMMIT; /* commit next beacon */ 480 sc->beacon.updateslot = COMMIT; /* commit next beacon */
481 sc->beacon.slotupdate = slot; 481 sc->beacon.slotupdate = slot;
482 } else if (sc->beacon.updateslot == COMMIT && sc->beacon.slotupdate == slot) { 482 } else if (sc->beacon.updateslot == COMMIT && sc->beacon.slotupdate == slot) {
483 ath9k_hw_setslottime(sc->sc_ah, sc->beacon.slottime); 483 ah->slottime = sc->beacon.slottime;
484 ath9k_hw_init_global_settings(ah);
484 sc->beacon.updateslot = OK; 485 sc->beacon.updateslot = OK;
485 } 486 }
486 if (bfaddr != 0) { 487 if (bfaddr != 0) {
@@ -490,7 +491,7 @@ void ath_beacon_tasklet(unsigned long data)
490 * are still pending on the queue. 491 * are still pending on the queue.
491 */ 492 */
492 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { 493 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
493 DPRINTF(sc, ATH_DBG_FATAL, 494 ath_print(common, ATH_DBG_FATAL,
494 "beacon queue %u did not stop?\n", sc->beacon.beaconq); 495 "beacon queue %u did not stop?\n", sc->beacon.beaconq);
495 } 496 }
496 497
@@ -502,6 +503,19 @@ void ath_beacon_tasklet(unsigned long data)
502 } 503 }
503} 504}
504 505
506static void ath9k_beacon_init(struct ath_softc *sc,
507 u32 next_beacon,
508 u32 beacon_period)
509{
510 if (beacon_period & ATH9K_BEACON_RESET_TSF)
511 ath9k_ps_wakeup(sc);
512
513 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
514
515 if (beacon_period & ATH9K_BEACON_RESET_TSF)
516 ath9k_ps_restore(sc);
517}
518
505/* 519/*
506 * For multi-bss ap support beacons are either staggered evenly over N slots or 520 * For multi-bss ap support beacons are either staggered evenly over N slots or
507 * burst together. For the former arrange for the SWBA to be delivered for each 521 * burst together. For the former arrange for the SWBA to be delivered for each
@@ -512,16 +526,13 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
512{ 526{
513 u32 nexttbtt, intval; 527 u32 nexttbtt, intval;
514 528
515 /* Configure the timers only when the TSF has to be reset */
516
517 if (!(sc->sc_flags & SC_OP_TSF_RESET))
518 return;
519
520 /* NB: the beacon interval is kept internally in TU's */ 529 /* NB: the beacon interval is kept internally in TU's */
521 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD; 530 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
522 intval /= ATH_BCBUF; /* for staggered beacons */ 531 intval /= ATH_BCBUF; /* for staggered beacons */
523 nexttbtt = intval; 532 nexttbtt = intval;
524 intval |= ATH9K_BEACON_RESET_TSF; 533
534 if (sc->sc_flags & SC_OP_TSF_RESET)
535 intval |= ATH9K_BEACON_RESET_TSF;
525 536
526 /* 537 /*
527 * In AP mode we enable the beacon timers and SWBA interrupts to 538 * In AP mode we enable the beacon timers and SWBA interrupts to
@@ -534,7 +545,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
534 /* Set the computed AP beacon timers */ 545 /* Set the computed AP beacon timers */
535 546
536 ath9k_hw_set_interrupts(sc->sc_ah, 0); 547 ath9k_hw_set_interrupts(sc->sc_ah, 0);
537 ath9k_hw_beaconinit(sc->sc_ah, nexttbtt, intval); 548 ath9k_beacon_init(sc, nexttbtt, intval);
538 sc->beacon.bmisscnt = 0; 549 sc->beacon.bmisscnt = 0;
539 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 550 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
540 551
@@ -555,6 +566,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
555static void ath_beacon_config_sta(struct ath_softc *sc, 566static void ath_beacon_config_sta(struct ath_softc *sc,
556 struct ath_beacon_config *conf) 567 struct ath_beacon_config *conf)
557{ 568{
569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
558 struct ath9k_beacon_state bs; 570 struct ath9k_beacon_state bs;
559 int dtimperiod, dtimcount, sleepduration; 571 int dtimperiod, dtimcount, sleepduration;
560 int cfpperiod, cfpcount; 572 int cfpperiod, cfpcount;
@@ -562,6 +574,13 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
562 u64 tsf; 574 u64 tsf;
563 int num_beacons, offset, dtim_dec_count, cfp_dec_count; 575 int num_beacons, offset, dtim_dec_count, cfp_dec_count;
564 576
577 /* No need to configure beacon if we are not associated */
578 if (!common->curaid) {
579 ath_print(common, ATH_DBG_BEACON,
580 "STA is not yet associated..skipping beacon config\n");
581 return;
582 }
583
565 memset(&bs, 0, sizeof(bs)); 584 memset(&bs, 0, sizeof(bs));
566 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD; 585 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD;
567 586
@@ -651,11 +670,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
651 /* TSF out of range threshold fixed at 1 second */ 670 /* TSF out of range threshold fixed at 1 second */
652 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; 671 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
653 672
654 DPRINTF(sc, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); 673 ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
655 DPRINTF(sc, ATH_DBG_BEACON, 674 ath_print(common, ATH_DBG_BEACON,
656 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", 675 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
657 bs.bs_bmissthreshold, bs.bs_sleepduration, 676 bs.bs_bmissthreshold, bs.bs_sleepduration,
658 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); 677 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
659 678
660 /* Set the computed STA beacon timers */ 679 /* Set the computed STA beacon timers */
661 680
@@ -669,6 +688,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
669 struct ath_beacon_config *conf, 688 struct ath_beacon_config *conf,
670 struct ieee80211_vif *vif) 689 struct ieee80211_vif *vif)
671{ 690{
691 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
672 u64 tsf; 692 u64 tsf;
673 u32 tsftu, intval, nexttbtt; 693 u32 tsftu, intval, nexttbtt;
674 694
@@ -689,9 +709,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
689 nexttbtt += intval; 709 nexttbtt += intval;
690 } while (nexttbtt < tsftu); 710 } while (nexttbtt < tsftu);
691 711
692 DPRINTF(sc, ATH_DBG_BEACON, 712 ath_print(common, ATH_DBG_BEACON,
693 "IBSS nexttbtt %u intval %u (%u)\n", 713 "IBSS nexttbtt %u intval %u (%u)\n",
694 nexttbtt, intval, conf->beacon_interval); 714 nexttbtt, intval, conf->beacon_interval);
695 715
696 /* 716 /*
697 * In IBSS mode enable the beacon timers but only enable SWBA interrupts 717 * In IBSS mode enable the beacon timers but only enable SWBA interrupts
@@ -707,7 +727,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
707 /* Set the computed ADHOC beacon timers */ 727 /* Set the computed ADHOC beacon timers */
708 728
709 ath9k_hw_set_interrupts(sc->sc_ah, 0); 729 ath9k_hw_set_interrupts(sc->sc_ah, 0);
710 ath9k_hw_beaconinit(sc->sc_ah, nexttbtt, intval); 730 ath9k_beacon_init(sc, nexttbtt, intval);
711 sc->beacon.bmisscnt = 0; 731 sc->beacon.bmisscnt = 0;
712 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 732 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
713 733
@@ -719,10 +739,10 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
719void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) 739void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
720{ 740{
721 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 741 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
742 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
722 enum nl80211_iftype iftype; 743 enum nl80211_iftype iftype;
723 744
724 /* Setup the beacon configuration parameters */ 745 /* Setup the beacon configuration parameters */
725
726 if (vif) { 746 if (vif) {
727 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 747 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
728 748
@@ -759,8 +779,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
759 ath_beacon_config_sta(sc, cur_conf); 779 ath_beacon_config_sta(sc, cur_conf);
760 break; 780 break;
761 default: 781 default:
762 DPRINTF(sc, ATH_DBG_CONFIG, 782 ath_print(common, ATH_DBG_CONFIG,
763 "Unsupported beaconing mode\n"); 783 "Unsupported beaconing mode\n");
764 return; 784 return;
765 } 785 }
766 786
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 55f607b7699e..fb4ac15f3b93 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -14,10 +14,26 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static const struct ath_btcoex_config ath_bt_config = { 0, true, true, 19enum ath_bt_mode {
20 ATH_BT_COEX_MODE_SLOTTED, true, true, 2, 5, true }; 20 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
21 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
22 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
23 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
24};
25
26struct ath_btcoex_config {
27 u8 bt_time_extend;
28 bool bt_txstate_extend;
29 bool bt_txframe_extend;
30 enum ath_bt_mode bt_mode; /* coexistence mode */
31 bool bt_quiet_collision;
32 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
33 u8 bt_priority_time;
34 u8 bt_first_slot_time;
35 bool bt_hold_rx_clear;
36};
21 37
22static const u16 ath_subsysid_tbl[] = { 38static const u16 ath_subsysid_tbl[] = {
23 AR9280_COEX2WIRE_SUBSYSID, 39 AR9280_COEX2WIRE_SUBSYSID,
@@ -29,141 +45,38 @@ static const u16 ath_subsysid_tbl[] = {
29 * Checks the subsystem id of the device to see if it 45 * Checks the subsystem id of the device to see if it
30 * supports btcoex 46 * supports btcoex
31 */ 47 */
32bool ath_btcoex_supported(u16 subsysid) 48bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
33{ 49{
34 int i; 50 int i;
35 51
36 if (!subsysid) 52 if (!ah->hw_version.subsysid)
37 return false; 53 return false;
38 54
39 for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++) 55 for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
40 if (subsysid == ath_subsysid_tbl[i]) 56 if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
41 return true; 57 return true;
42 58
43 return false; 59 return false;
44} 60}
45 61
46/* 62void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
47 * Detects if there is any priority bt traffic
48 */
49static void ath_detect_bt_priority(struct ath_softc *sc)
50{
51 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
52
53 if (ath9k_hw_gpio_get(sc->sc_ah, btinfo->btpriority_gpio))
54 btinfo->bt_priority_cnt++;
55
56 if (time_after(jiffies, btinfo->bt_priority_time +
57 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
58 if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
59 DPRINTF(sc, ATH_DBG_BTCOEX,
60 "BT priority traffic detected");
61 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
62 } else {
63 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
64 }
65
66 btinfo->bt_priority_cnt = 0;
67 btinfo->bt_priority_time = jiffies;
68 }
69}
70
71/*
72 * Configures appropriate weight based on stomp type.
73 */
74static void ath_btcoex_bt_stomp(struct ath_softc *sc,
75 struct ath_btcoex_info *btinfo,
76 int stomp_type)
77{
78
79 switch (stomp_type) {
80 case ATH_BTCOEX_STOMP_ALL:
81 ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
82 AR_STOMP_ALL_WLAN_WGHT);
83 break;
84 case ATH_BTCOEX_STOMP_LOW:
85 ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
86 AR_STOMP_LOW_WLAN_WGHT);
87 break;
88 case ATH_BTCOEX_STOMP_NONE:
89 ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
90 AR_STOMP_NONE_WLAN_WGHT);
91 break;
92 default:
93 DPRINTF(sc, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
94 break;
95 }
96
97 ath9k_hw_btcoex_enable(sc->sc_ah);
98}
99
100/*
101 * This is the master bt coex timer which runs for every
102 * 45ms, bt traffic will be given priority during 55% of this
103 * period while wlan gets remaining 45%
104 */
105
106static void ath_btcoex_period_timer(unsigned long data)
107{
108 struct ath_softc *sc = (struct ath_softc *) data;
109 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
110
111 ath_detect_bt_priority(sc);
112
113 spin_lock_bh(&btinfo->btcoex_lock);
114
115 ath_btcoex_bt_stomp(sc, btinfo, btinfo->bt_stomp_type);
116
117 spin_unlock_bh(&btinfo->btcoex_lock);
118
119 if (btinfo->btcoex_period != btinfo->btcoex_no_stomp) {
120 if (btinfo->hw_timer_enabled)
121 ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
122
123 ath_gen_timer_start(sc->sc_ah,
124 btinfo->no_stomp_timer,
125 (ath9k_hw_gettsf32(sc->sc_ah) +
126 btinfo->btcoex_no_stomp),
127 btinfo->btcoex_no_stomp * 10);
128 btinfo->hw_timer_enabled = true;
129 }
130
131 mod_timer(&btinfo->period_timer, jiffies +
132 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
133}
134
135/*
136 * Generic tsf based hw timer which configures weight
137 * registers to time slice between wlan and bt traffic
138 */
139
140static void ath_btcoex_no_stomp_timer(void *arg)
141{
142 struct ath_softc *sc = (struct ath_softc *)arg;
143 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
144
145 DPRINTF(sc, ATH_DBG_BTCOEX, "no stomp timer running \n");
146
147 spin_lock_bh(&btinfo->btcoex_lock);
148
149 if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
150 ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_NONE);
151 else if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
152 ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_LOW);
153
154 spin_unlock_bh(&btinfo->btcoex_lock);
155}
156
157static int ath_init_btcoex_info(struct ath_hw *hw,
158 struct ath_btcoex_info *btcoex_info)
159{ 63{
64 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
65 const struct ath_btcoex_config ath_bt_config = {
66 .bt_time_extend = 0,
67 .bt_txstate_extend = true,
68 .bt_txframe_extend = true,
69 .bt_mode = ATH_BT_COEX_MODE_SLOTTED,
70 .bt_quiet_collision = true,
71 .bt_rxclear_polarity = true,
72 .bt_priority_time = 2,
73 .bt_first_slot_time = 5,
74 .bt_hold_rx_clear = true,
75 };
160 u32 i; 76 u32 i;
161 int qnum;
162 77
163 qnum = ath_tx_get_qnum(hw->ah_sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); 78 btcoex_hw->bt_coex_mode =
164 79 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
165 btcoex_info->bt_coex_mode =
166 (btcoex_info->bt_coex_mode & AR_BT_QCU_THRESH) |
167 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) | 80 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
168 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 81 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
169 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 82 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
@@ -174,167 +87,141 @@ static int ath_init_btcoex_info(struct ath_hw *hw,
174 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) | 87 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
175 SM(qnum, AR_BT_QCU_THRESH); 88 SM(qnum, AR_BT_QCU_THRESH);
176 89
177 btcoex_info->bt_coex_mode2 = 90 btcoex_hw->bt_coex_mode2 =
178 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | 91 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
179 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | 92 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
180 AR_BT_DISABLE_BT_ANT; 93 AR_BT_DISABLE_BT_ANT;
181 94
182 btcoex_info->bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 95 for (i = 0; i < 32; i++)
96 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
97}
98EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
183 99
184 btcoex_info->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000; 100void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
101{
102 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
185 103
186 btcoex_info->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 104 /* connect bt_active to baseband */
187 btcoex_info->btcoex_period / 100; 105 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
106 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
107 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
188 108
189 for (i = 0; i < 32; i++) 109 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
190 hw->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i; 110 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
191 111
192 setup_timer(&btcoex_info->period_timer, ath_btcoex_period_timer, 112 /* Set input mux for bt_active to gpio pin */
193 (unsigned long) hw->ah_sc); 113 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
114 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
115 btcoex_hw->btactive_gpio);
194 116
195 btcoex_info->no_stomp_timer = ath_gen_timer_alloc(hw, 117 /* Configure the desired gpio port for input */
196 ath_btcoex_no_stomp_timer, 118 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
197 ath_btcoex_no_stomp_timer, 119}
198 (void *)hw->ah_sc, AR_FIRST_NDP_TIMER); 120EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
121
122void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
123{
124 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
199 125
200 if (btcoex_info->no_stomp_timer == NULL) 126 /* btcoex 3-wire */
201 return -ENOMEM; 127 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
128 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
129 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
202 130
203 spin_lock_init(&btcoex_info->btcoex_lock); 131 /* Set input mux for bt_prority_async and
132 * bt_active_async to GPIO pins */
133 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
134 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
135 btcoex_hw->btactive_gpio);
204 136
205 return 0; 137 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
138 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
139 btcoex_hw->btpriority_gpio);
140
141 /* Configure the desired GPIO ports for input */
142
143 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
144 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
206} 145}
146EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
207 147
208int ath9k_hw_btcoex_init(struct ath_hw *ah) 148static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
209{ 149{
210 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 150 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
211 int ret = 0;
212
213 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
214 /* connect bt_active to baseband */
215 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
216 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
217 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
218
219 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
220 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
221
222 /* Set input mux for bt_active to gpio pin */
223 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
224 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
225 btcoex_info->btactive_gpio);
226
227 /* Configure the desired gpio port for input */
228 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
229 } else {
230 /* btcoex 3-wire */
231 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
232 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
233 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
234
235 /* Set input mux for bt_prority_async and
236 * bt_active_async to GPIO pins */
237 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
238 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
239 btcoex_info->btactive_gpio);
240
241 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
242 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
243 btcoex_info->btpriority_gpio);
244
245 /* Configure the desired GPIO ports for input */
246
247 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
248 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio);
249
250 ret = ath_init_btcoex_info(ah, btcoex_info);
251 }
252 151
253 return ret; 152 /* Configure the desired GPIO port for TX_FRAME output */
153 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
154 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
254} 155}
255 156
256void ath9k_hw_btcoex_enable(struct ath_hw *ah) 157void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
158 u32 bt_weight,
159 u32 wlan_weight)
257{ 160{
258 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 161 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
259
260 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
261 /* Configure the desired GPIO port for TX_FRAME output */
262 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
263 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
264 } else {
265 /*
266 * Program coex mode and weight registers to
267 * enable coex 3-wire
268 */
269 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_info->bt_coex_mode);
270 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_info->bt_coex_weights);
271 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_info->bt_coex_mode2);
272
273 REG_RMW_FIELD(ah, AR_QUIET1,
274 AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
275 REG_RMW_FIELD(ah, AR_PCU_MISC,
276 AR_PCU_BT_ANT_PREVENT_RX, 0);
277
278 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
279 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
280 }
281 162
282 REG_RMW(ah, AR_GPIO_PDPU, 163 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
283 (0x2 << (btcoex_info->btactive_gpio * 2)), 164 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
284 (0x3 << (btcoex_info->btactive_gpio * 2)));
285
286 ah->ah_sc->sc_flags |= SC_OP_BTCOEX_ENABLED;
287} 165}
166EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
288 167
289void ath9k_hw_btcoex_disable(struct ath_hw *ah) 168static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
290{ 169{
291 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 170 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
292 171
293 ath9k_hw_set_gpio(ah, btcoex_info->wlanactive_gpio, 0); 172 /*
173 * Program coex mode and weight registers to
174 * enable coex 3-wire
175 */
176 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
177 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
178 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
294 179
295 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio, 180 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
296 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 181 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
297 182
298 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) { 183 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
299 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 184 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
300 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
301 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
302 }
303
304 ah->ah_sc->sc_flags &= ~SC_OP_BTCOEX_ENABLED;
305} 185}
306 186
307/* 187void ath9k_hw_btcoex_enable(struct ath_hw *ah)
308 * Pause btcoex timer and bt duty cycle timer
309 */
310void ath_btcoex_timer_pause(struct ath_softc *sc,
311 struct ath_btcoex_info *btinfo)
312{ 188{
189 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
313 190
314 del_timer_sync(&btinfo->period_timer); 191 switch (btcoex_hw->scheme) {
192 case ATH_BTCOEX_CFG_NONE:
193 break;
194 case ATH_BTCOEX_CFG_2WIRE:
195 ath9k_hw_btcoex_enable_2wire(ah);
196 break;
197 case ATH_BTCOEX_CFG_3WIRE:
198 ath9k_hw_btcoex_enable_3wire(ah);
199 break;
200 }
315 201
316 if (btinfo->hw_timer_enabled) 202 REG_RMW(ah, AR_GPIO_PDPU,
317 ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer); 203 (0x2 << (btcoex_hw->btactive_gpio * 2)),
204 (0x3 << (btcoex_hw->btactive_gpio * 2)));
318 205
319 btinfo->hw_timer_enabled = false; 206 ah->btcoex_hw.enabled = true;
320} 207}
208EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
321 209
322/* 210void ath9k_hw_btcoex_disable(struct ath_hw *ah)
323 * (Re)start btcoex timers
324 */
325void ath_btcoex_timer_resume(struct ath_softc *sc,
326 struct ath_btcoex_info *btinfo)
327{ 211{
212 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
328 213
329 DPRINTF(sc, ATH_DBG_BTCOEX, "Starting btcoex timers"); 214 ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
330 215
331 /* make sure duty cycle timer is also stopped when resuming */ 216 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
332 if (btinfo->hw_timer_enabled) 217 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
333 ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
334 218
335 btinfo->bt_priority_cnt = 0; 219 if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
336 btinfo->bt_priority_time = jiffies; 220 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
337 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED; 221 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
222 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
223 }
338 224
339 mod_timer(&btinfo->period_timer, jiffies); 225 ah->btcoex_hw.enabled = false;
340} 226}
227EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 297b027fd3c3..1ee5a15ccbb1 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -17,16 +17,20 @@
17#ifndef BTCOEX_H 17#ifndef BTCOEX_H
18#define BTCOEX_H 18#define BTCOEX_H
19 19
20#include "hw.h"
21
20#define ATH_WLANACTIVE_GPIO 5 22#define ATH_WLANACTIVE_GPIO 5
21#define ATH_BTACTIVE_GPIO 6 23#define ATH_BTACTIVE_GPIO 6
22#define ATH_BTPRIORITY_GPIO 7 24#define ATH_BTPRIORITY_GPIO 7
23 25
24#define ATH_BTCOEX_DEF_BT_PERIOD 45 26#define ATH_BTCOEX_DEF_BT_PERIOD 45
25#define ATH_BTCOEX_DEF_DUTY_CYCLE 55 27#define ATH_BTCOEX_DEF_DUTY_CYCLE 55
28#define ATH_BTCOEX_BTSCAN_DUTY_CYCLE 90
26#define ATH_BTCOEX_BMISS_THRESH 50 29#define ATH_BTCOEX_BMISS_THRESH 50
27 30
28#define ATH_BT_PRIORITY_TIME_THRESHOLD 1000 /* ms */ 31#define ATH_BT_PRIORITY_TIME_THRESHOLD 1000 /* ms */
29#define ATH_BT_CNT_THRESHOLD 3 32#define ATH_BT_CNT_THRESHOLD 3
33#define ATH_BT_CNT_SCAN_THRESHOLD 15
30 34
31enum ath_btcoex_scheme { 35enum ath_btcoex_scheme {
32 ATH_BTCOEX_CFG_NONE, 36 ATH_BTCOEX_CFG_NONE,
@@ -34,67 +38,25 @@ enum ath_btcoex_scheme {
34 ATH_BTCOEX_CFG_3WIRE, 38 ATH_BTCOEX_CFG_3WIRE,
35}; 39};
36 40
37enum ath_stomp_type { 41struct ath_btcoex_hw {
38 ATH_BTCOEX_NO_STOMP, 42 enum ath_btcoex_scheme scheme;
39 ATH_BTCOEX_STOMP_ALL, 43 bool enabled;
40 ATH_BTCOEX_STOMP_LOW,
41 ATH_BTCOEX_STOMP_NONE
42};
43
44enum ath_bt_mode {
45 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
46 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
47 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
48 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
49};
50
51struct ath_btcoex_config {
52 u8 bt_time_extend;
53 bool bt_txstate_extend;
54 bool bt_txframe_extend;
55 enum ath_bt_mode bt_mode; /* coexistence mode */
56 bool bt_quiet_collision;
57 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
58 u8 bt_priority_time;
59 u8 bt_first_slot_time;
60 bool bt_hold_rx_clear;
61};
62
63struct ath_btcoex_info {
64 enum ath_btcoex_scheme btcoex_scheme;
65 u8 wlanactive_gpio; 44 u8 wlanactive_gpio;
66 u8 btactive_gpio; 45 u8 btactive_gpio;
67 u8 btpriority_gpio; 46 u8 btpriority_gpio;
68 u8 bt_duty_cycle; /* BT duty cycle in percentage */
69 int bt_stomp_type; /* Types of BT stomping */
70 u32 bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 47 u32 bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */
71 u32 bt_coex_weights; /* Register setting for AR_BT_COEX_WEIGHT */ 48 u32 bt_coex_weights; /* Register setting for AR_BT_COEX_WEIGHT */
72 u32 bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 49 u32 bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */
73 u32 btcoex_no_stomp; /* in usec */
74 u32 btcoex_period; /* in usec */
75 u32 bt_priority_cnt;
76 unsigned long bt_priority_time;
77 bool hw_timer_enabled;
78 spinlock_t btcoex_lock;
79 struct timer_list period_timer; /* Timer for BT period */
80 struct ath_gen_timer *no_stomp_timer; /*Timer for no BT stomping*/
81}; 50};
82 51
83bool ath_btcoex_supported(u16 subsysid); 52bool ath9k_hw_btcoex_supported(struct ath_hw *ah);
84int ath9k_hw_btcoex_init(struct ath_hw *ah); 53void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah);
54void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah);
55void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum);
56void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
57 u32 bt_weight,
58 u32 wlan_weight);
85void ath9k_hw_btcoex_enable(struct ath_hw *ah); 59void ath9k_hw_btcoex_enable(struct ath_hw *ah);
86void ath9k_hw_btcoex_disable(struct ath_hw *ah); 60void ath9k_hw_btcoex_disable(struct ath_hw *ah);
87void ath_btcoex_timer_resume(struct ath_softc *sc,
88 struct ath_btcoex_info *btinfo);
89void ath_btcoex_timer_pause(struct ath_softc *sc,
90 struct ath_btcoex_info *btinfo);
91
92static inline void ath_btcoex_set_weight(struct ath_btcoex_info *btcoex_info,
93 u32 bt_weight,
94 u32 wlan_weight)
95{
96 btcoex_info->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
97 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
98}
99 61
100#endif 62#endif
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 0ad6d0b76e9e..238a5744d8e9 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19/* We can tune this as we go by monitoring really low values */ 19/* We can tune this as we go by monitoring really low values */
20#define ATH9K_NF_TOO_LOW -60 20#define ATH9K_NF_TOO_LOW -60
@@ -26,11 +26,11 @@
26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) 26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
27{ 27{
28 if (nf > ATH9K_NF_TOO_LOW) { 28 if (nf > ATH9K_NF_TOO_LOW) {
29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 29 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
30 "noise floor value detected (%d) is " 30 "noise floor value detected (%d) is "
31 "lower than what we think is a " 31 "lower than what we think is a "
32 "reasonable value (%d)\n", 32 "reasonable value (%d)\n",
33 nf, ATH9K_NF_TOO_LOW); 33 nf, ATH9K_NF_TOO_LOW);
34 return false; 34 return false;
35 } 35 }
36 return true; 36 return true;
@@ -89,6 +89,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
89static void ath9k_hw_do_getnf(struct ath_hw *ah, 89static void ath9k_hw_do_getnf(struct ath_hw *ah,
90 int16_t nfarray[NUM_NF_READINGS]) 90 int16_t nfarray[NUM_NF_READINGS])
91{ 91{
92 struct ath_common *common = ath9k_hw_common(ah);
92 int16_t nf; 93 int16_t nf;
93 94
94 if (AR_SREV_9280_10_OR_LATER(ah)) 95 if (AR_SREV_9280_10_OR_LATER(ah))
@@ -98,8 +99,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
98 99
99 if (nf & 0x100) 100 if (nf & 0x100)
100 nf = 0 - ((nf ^ 0x1ff) + 1); 101 nf = 0 - ((nf ^ 0x1ff) + 1);
101 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 102 ath_print(common, ATH_DBG_CALIBRATE,
102 "NF calibrated [ctl] [chain 0] is %d\n", nf); 103 "NF calibrated [ctl] [chain 0] is %d\n", nf);
103 nfarray[0] = nf; 104 nfarray[0] = nf;
104 105
105 if (!AR_SREV_9285(ah)) { 106 if (!AR_SREV_9285(ah)) {
@@ -112,8 +113,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
112 113
113 if (nf & 0x100) 114 if (nf & 0x100)
114 nf = 0 - ((nf ^ 0x1ff) + 1); 115 nf = 0 - ((nf ^ 0x1ff) + 1);
115 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 116 ath_print(common, ATH_DBG_CALIBRATE,
116 "NF calibrated [ctl] [chain 1] is %d\n", nf); 117 "NF calibrated [ctl] [chain 1] is %d\n", nf);
117 nfarray[1] = nf; 118 nfarray[1] = nf;
118 119
119 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { 120 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
@@ -121,8 +122,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
121 AR_PHY_CH2_MINCCA_PWR); 122 AR_PHY_CH2_MINCCA_PWR);
122 if (nf & 0x100) 123 if (nf & 0x100)
123 nf = 0 - ((nf ^ 0x1ff) + 1); 124 nf = 0 - ((nf ^ 0x1ff) + 1);
124 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 125 ath_print(common, ATH_DBG_CALIBRATE,
125 "NF calibrated [ctl] [chain 2] is %d\n", nf); 126 "NF calibrated [ctl] [chain 2] is %d\n", nf);
126 nfarray[2] = nf; 127 nfarray[2] = nf;
127 } 128 }
128 } 129 }
@@ -136,8 +137,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
136 137
137 if (nf & 0x100) 138 if (nf & 0x100)
138 nf = 0 - ((nf ^ 0x1ff) + 1); 139 nf = 0 - ((nf ^ 0x1ff) + 1);
139 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 140 ath_print(common, ATH_DBG_CALIBRATE,
140 "NF calibrated [ext] [chain 0] is %d\n", nf); 141 "NF calibrated [ext] [chain 0] is %d\n", nf);
141 nfarray[3] = nf; 142 nfarray[3] = nf;
142 143
143 if (!AR_SREV_9285(ah)) { 144 if (!AR_SREV_9285(ah)) {
@@ -150,8 +151,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
150 151
151 if (nf & 0x100) 152 if (nf & 0x100)
152 nf = 0 - ((nf ^ 0x1ff) + 1); 153 nf = 0 - ((nf ^ 0x1ff) + 1);
153 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 154 ath_print(common, ATH_DBG_CALIBRATE,
154 "NF calibrated [ext] [chain 1] is %d\n", nf); 155 "NF calibrated [ext] [chain 1] is %d\n", nf);
155 nfarray[4] = nf; 156 nfarray[4] = nf;
156 157
157 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { 158 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
@@ -159,8 +160,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
159 AR_PHY_CH2_EXT_MINCCA_PWR); 160 AR_PHY_CH2_EXT_MINCCA_PWR);
160 if (nf & 0x100) 161 if (nf & 0x100)
161 nf = 0 - ((nf ^ 0x1ff) + 1); 162 nf = 0 - ((nf ^ 0x1ff) + 1);
162 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 163 ath_print(common, ATH_DBG_CALIBRATE,
163 "NF calibrated [ext] [chain 2] is %d\n", nf); 164 "NF calibrated [ext] [chain 2] is %d\n", nf);
164 nfarray[5] = nf; 165 nfarray[5] = nf;
165 } 166 }
166 } 167 }
@@ -188,6 +189,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
188static void ath9k_hw_setup_calibration(struct ath_hw *ah, 189static void ath9k_hw_setup_calibration(struct ath_hw *ah,
189 struct ath9k_cal_list *currCal) 190 struct ath9k_cal_list *currCal)
190{ 191{
192 struct ath_common *common = ath9k_hw_common(ah);
193
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), 194 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
192 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 195 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
193 currCal->calData->calCountMax); 196 currCal->calData->calCountMax);
@@ -195,23 +198,23 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
195 switch (currCal->calData->calType) { 198 switch (currCal->calData->calType) {
196 case IQ_MISMATCH_CAL: 199 case IQ_MISMATCH_CAL:
197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 200 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
198 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 201 ath_print(common, ATH_DBG_CALIBRATE,
199 "starting IQ Mismatch Calibration\n"); 202 "starting IQ Mismatch Calibration\n");
200 break; 203 break;
201 case ADC_GAIN_CAL: 204 case ADC_GAIN_CAL:
202 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 205 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
203 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 206 ath_print(common, ATH_DBG_CALIBRATE,
204 "starting ADC Gain Calibration\n"); 207 "starting ADC Gain Calibration\n");
205 break; 208 break;
206 case ADC_DC_CAL: 209 case ADC_DC_CAL:
207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 210 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
208 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 211 ath_print(common, ATH_DBG_CALIBRATE,
209 "starting ADC DC Calibration\n"); 212 "starting ADC DC Calibration\n");
210 break; 213 break;
211 case ADC_DC_INIT_CAL: 214 case ADC_DC_INIT_CAL:
212 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); 215 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
213 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 216 ath_print(common, ATH_DBG_CALIBRATE,
214 "starting Init ADC DC Calibration\n"); 217 "starting Init ADC DC Calibration\n");
215 break; 218 break;
216 } 219 }
217 220
@@ -278,7 +281,7 @@ static bool ath9k_hw_per_calibration(struct ath_hw *ah,
278static bool ath9k_hw_iscal_supported(struct ath_hw *ah, 281static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
279 enum ath9k_cal_types calType) 282 enum ath9k_cal_types calType)
280{ 283{
281 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 284 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
282 285
283 switch (calType & ah->supp_cals) { 286 switch (calType & ah->supp_cals) {
284 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ 287 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
@@ -304,11 +307,11 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
304 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 307 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
305 ah->totalIqCorrMeas[i] += 308 ah->totalIqCorrMeas[i] +=
306 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 309 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
307 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 310 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
308 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 311 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
309 ah->cal_samples, i, ah->totalPowerMeasI[i], 312 ah->cal_samples, i, ah->totalPowerMeasI[i],
310 ah->totalPowerMeasQ[i], 313 ah->totalPowerMeasQ[i],
311 ah->totalIqCorrMeas[i]); 314 ah->totalIqCorrMeas[i]);
312 } 315 }
313} 316}
314 317
@@ -326,14 +329,14 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
326 ah->totalAdcQEvenPhase[i] += 329 ah->totalAdcQEvenPhase[i] +=
327 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 330 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
328 331
329 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 332 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
330 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 333 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
331 "oddq=0x%08x; evenq=0x%08x;\n", 334 "oddq=0x%08x; evenq=0x%08x;\n",
332 ah->cal_samples, i, 335 ah->cal_samples, i,
333 ah->totalAdcIOddPhase[i], 336 ah->totalAdcIOddPhase[i],
334 ah->totalAdcIEvenPhase[i], 337 ah->totalAdcIEvenPhase[i],
335 ah->totalAdcQOddPhase[i], 338 ah->totalAdcQOddPhase[i],
336 ah->totalAdcQEvenPhase[i]); 339 ah->totalAdcQEvenPhase[i]);
337 } 340 }
338} 341}
339 342
@@ -351,19 +354,20 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
351 ah->totalAdcDcOffsetQEvenPhase[i] += 354 ah->totalAdcDcOffsetQEvenPhase[i] +=
352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 355 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
353 356
354 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 357 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
355 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 358 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
356 "oddq=0x%08x; evenq=0x%08x;\n", 359 "oddq=0x%08x; evenq=0x%08x;\n",
357 ah->cal_samples, i, 360 ah->cal_samples, i,
358 ah->totalAdcDcOffsetIOddPhase[i], 361 ah->totalAdcDcOffsetIOddPhase[i],
359 ah->totalAdcDcOffsetIEvenPhase[i], 362 ah->totalAdcDcOffsetIEvenPhase[i],
360 ah->totalAdcDcOffsetQOddPhase[i], 363 ah->totalAdcDcOffsetQOddPhase[i],
361 ah->totalAdcDcOffsetQEvenPhase[i]); 364 ah->totalAdcDcOffsetQEvenPhase[i]);
362 } 365 }
363} 366}
364 367
365static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 368static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
366{ 369{
370 struct ath_common *common = ath9k_hw_common(ah);
367 u32 powerMeasQ, powerMeasI, iqCorrMeas; 371 u32 powerMeasQ, powerMeasI, iqCorrMeas;
368 u32 qCoffDenom, iCoffDenom; 372 u32 qCoffDenom, iCoffDenom;
369 int32_t qCoff, iCoff; 373 int32_t qCoff, iCoff;
@@ -374,13 +378,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
374 powerMeasQ = ah->totalPowerMeasQ[i]; 378 powerMeasQ = ah->totalPowerMeasQ[i];
375 iqCorrMeas = ah->totalIqCorrMeas[i]; 379 iqCorrMeas = ah->totalIqCorrMeas[i];
376 380
377 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 381 ath_print(common, ATH_DBG_CALIBRATE,
378 "Starting IQ Cal and Correction for Chain %d\n", 382 "Starting IQ Cal and Correction for Chain %d\n",
379 i); 383 i);
380 384
381 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 385 ath_print(common, ATH_DBG_CALIBRATE,
382 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 386 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
383 i, ah->totalIqCorrMeas[i]); 387 i, ah->totalIqCorrMeas[i]);
384 388
385 iqCorrNeg = 0; 389 iqCorrNeg = 0;
386 390
@@ -389,27 +393,28 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
389 iqCorrNeg = 1; 393 iqCorrNeg = 1;
390 } 394 }
391 395
392 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 396 ath_print(common, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 397 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
394 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 398 ath_print(common, ATH_DBG_CALIBRATE,
395 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 399 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
396 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 400 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
397 iqCorrNeg); 401 iqCorrNeg);
398 402
399 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 403 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
400 qCoffDenom = powerMeasQ / 64; 404 qCoffDenom = powerMeasQ / 64;
401 405
402 if (powerMeasQ != 0) { 406 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
407 (qCoffDenom != 0)) {
403 iCoff = iqCorrMeas / iCoffDenom; 408 iCoff = iqCorrMeas / iCoffDenom;
404 qCoff = powerMeasI / qCoffDenom - 64; 409 qCoff = powerMeasI / qCoffDenom - 64;
405 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 410 ath_print(common, ATH_DBG_CALIBRATE,
406 "Chn %d iCoff = 0x%08x\n", i, iCoff); 411 "Chn %d iCoff = 0x%08x\n", i, iCoff);
407 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 412 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d qCoff = 0x%08x\n", i, qCoff); 413 "Chn %d qCoff = 0x%08x\n", i, qCoff);
409 414
410 iCoff = iCoff & 0x3f; 415 iCoff = iCoff & 0x3f;
411 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 416 ath_print(common, ATH_DBG_CALIBRATE,
412 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); 417 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
413 if (iqCorrNeg == 0x0) 418 if (iqCorrNeg == 0x0)
414 iCoff = 0x40 - iCoff; 419 iCoff = 0x40 - iCoff;
415 420
@@ -418,9 +423,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
418 else if (qCoff <= -16) 423 else if (qCoff <= -16)
419 qCoff = 16; 424 qCoff = 16;
420 425
421 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 426 ath_print(common, ATH_DBG_CALIBRATE,
422 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 427 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
423 i, iCoff, qCoff); 428 i, iCoff, qCoff);
424 429
425 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 430 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
426 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 431 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -428,9 +433,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
428 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 433 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
429 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 434 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
430 qCoff); 435 qCoff);
431 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 436 ath_print(common, ATH_DBG_CALIBRATE,
432 "IQ Cal and Correction done for Chain %d\n", 437 "IQ Cal and Correction done for Chain %d\n",
433 i); 438 i);
434 } 439 }
435 } 440 }
436 441
@@ -440,6 +445,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
440 445
441static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 446static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
442{ 447{
448 struct ath_common *common = ath9k_hw_common(ah);
443 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; 449 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
444 u32 qGainMismatch, iGainMismatch, val, i; 450 u32 qGainMismatch, iGainMismatch, val, i;
445 451
@@ -449,21 +455,21 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
449 qOddMeasOffset = ah->totalAdcQOddPhase[i]; 455 qOddMeasOffset = ah->totalAdcQOddPhase[i];
450 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; 456 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
451 457
452 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 458 ath_print(common, ATH_DBG_CALIBRATE,
453 "Starting ADC Gain Cal for Chain %d\n", i); 459 "Starting ADC Gain Cal for Chain %d\n", i);
454 460
455 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 461 ath_print(common, ATH_DBG_CALIBRATE,
456 "Chn %d pwr_meas_odd_i = 0x%08x\n", i, 462 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
457 iOddMeasOffset); 463 iOddMeasOffset);
458 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 464 ath_print(common, ATH_DBG_CALIBRATE,
459 "Chn %d pwr_meas_even_i = 0x%08x\n", i, 465 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
460 iEvenMeasOffset); 466 iEvenMeasOffset);
461 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 467 ath_print(common, ATH_DBG_CALIBRATE,
462 "Chn %d pwr_meas_odd_q = 0x%08x\n", i, 468 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
463 qOddMeasOffset); 469 qOddMeasOffset);
464 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 470 ath_print(common, ATH_DBG_CALIBRATE,
465 "Chn %d pwr_meas_even_q = 0x%08x\n", i, 471 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
466 qEvenMeasOffset); 472 qEvenMeasOffset);
467 473
468 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { 474 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
469 iGainMismatch = 475 iGainMismatch =
@@ -473,20 +479,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
473 ((qOddMeasOffset * 32) / 479 ((qOddMeasOffset * 32) /
474 qEvenMeasOffset) & 0x3f; 480 qEvenMeasOffset) & 0x3f;
475 481
476 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 482 ath_print(common, ATH_DBG_CALIBRATE,
477 "Chn %d gain_mismatch_i = 0x%08x\n", i, 483 "Chn %d gain_mismatch_i = 0x%08x\n", i,
478 iGainMismatch); 484 iGainMismatch);
479 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 485 ath_print(common, ATH_DBG_CALIBRATE,
480 "Chn %d gain_mismatch_q = 0x%08x\n", i, 486 "Chn %d gain_mismatch_q = 0x%08x\n", i,
481 qGainMismatch); 487 qGainMismatch);
482 488
483 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 489 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
484 val &= 0xfffff000; 490 val &= 0xfffff000;
485 val |= (qGainMismatch) | (iGainMismatch << 6); 491 val |= (qGainMismatch) | (iGainMismatch << 6);
486 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 492 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
487 493
488 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 494 ath_print(common, ATH_DBG_CALIBRATE,
489 "ADC Gain Cal done for Chain %d\n", i); 495 "ADC Gain Cal done for Chain %d\n", i);
490 } 496 }
491 } 497 }
492 498
@@ -497,6 +503,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
497 503
498static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 504static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
499{ 505{
506 struct ath_common *common = ath9k_hw_common(ah);
500 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 507 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
501 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 508 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
502 const struct ath9k_percal_data *calData = 509 const struct ath9k_percal_data *calData =
@@ -510,41 +517,41 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; 517 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
511 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; 518 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
512 519
513 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 520 ath_print(common, ATH_DBG_CALIBRATE,
514 "Starting ADC DC Offset Cal for Chain %d\n", i); 521 "Starting ADC DC Offset Cal for Chain %d\n", i);
515 522
516 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 523 ath_print(common, ATH_DBG_CALIBRATE,
517 "Chn %d pwr_meas_odd_i = %d\n", i, 524 "Chn %d pwr_meas_odd_i = %d\n", i,
518 iOddMeasOffset); 525 iOddMeasOffset);
519 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 526 ath_print(common, ATH_DBG_CALIBRATE,
520 "Chn %d pwr_meas_even_i = %d\n", i, 527 "Chn %d pwr_meas_even_i = %d\n", i,
521 iEvenMeasOffset); 528 iEvenMeasOffset);
522 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 529 ath_print(common, ATH_DBG_CALIBRATE,
523 "Chn %d pwr_meas_odd_q = %d\n", i, 530 "Chn %d pwr_meas_odd_q = %d\n", i,
524 qOddMeasOffset); 531 qOddMeasOffset);
525 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 532 ath_print(common, ATH_DBG_CALIBRATE,
526 "Chn %d pwr_meas_even_q = %d\n", i, 533 "Chn %d pwr_meas_even_q = %d\n", i,
527 qEvenMeasOffset); 534 qEvenMeasOffset);
528 535
529 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / 536 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
530 numSamples) & 0x1ff; 537 numSamples) & 0x1ff;
531 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 538 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
532 numSamples) & 0x1ff; 539 numSamples) & 0x1ff;
533 540
534 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 541 ath_print(common, ATH_DBG_CALIBRATE,
535 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, 542 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
536 iDcMismatch); 543 iDcMismatch);
537 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 544 ath_print(common, ATH_DBG_CALIBRATE,
538 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, 545 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
539 qDcMismatch); 546 qDcMismatch);
540 547
541 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 548 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
542 val &= 0xc0000fff; 549 val &= 0xc0000fff;
543 val |= (qDcMismatch << 12) | (iDcMismatch << 21); 550 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
544 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 551 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
545 552
546 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 553 ath_print(common, ATH_DBG_CALIBRATE,
547 "ADC DC Offset Cal done for Chain %d\n", i); 554 "ADC DC Offset Cal done for Chain %d\n", i);
548 } 555 }
549 556
550 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 557 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -555,7 +562,8 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
555/* This is done for the currently configured channel */ 562/* This is done for the currently configured channel */
556bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 563bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
557{ 564{
558 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 565 struct ath_common *common = ath9k_hw_common(ah);
566 struct ieee80211_conf *conf = &common->hw->conf;
559 struct ath9k_cal_list *currCal = ah->cal_list_curr; 567 struct ath9k_cal_list *currCal = ah->cal_list_curr;
560 568
561 if (!ah->curchan) 569 if (!ah->curchan)
@@ -568,24 +576,25 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
568 return true; 576 return true;
569 577
570 if (currCal->calState != CAL_DONE) { 578 if (currCal->calState != CAL_DONE) {
571 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 579 ath_print(common, ATH_DBG_CALIBRATE,
572 "Calibration state incorrect, %d\n", 580 "Calibration state incorrect, %d\n",
573 currCal->calState); 581 currCal->calState);
574 return true; 582 return true;
575 } 583 }
576 584
577 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) 585 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
578 return true; 586 return true;
579 587
580 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 588 ath_print(common, ATH_DBG_CALIBRATE,
581 "Resetting Cal %d state for channel %u\n", 589 "Resetting Cal %d state for channel %u\n",
582 currCal->calData->calType, conf->channel->center_freq); 590 currCal->calData->calType, conf->channel->center_freq);
583 591
584 ah->curchan->CalValid &= ~currCal->calData->calType; 592 ah->curchan->CalValid &= ~currCal->calData->calType;
585 currCal->calState = CAL_WAITING; 593 currCal->calState = CAL_WAITING;
586 594
587 return false; 595 return false;
588} 596}
597EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
589 598
590void ath9k_hw_start_nfcal(struct ath_hw *ah) 599void ath9k_hw_start_nfcal(struct ath_hw *ah)
591{ 600{
@@ -645,11 +654,11 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
645 AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 654 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
646 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 655 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
647 656
648 for (j = 0; j < 1000; j++) { 657 for (j = 0; j < 5; j++) {
649 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & 658 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
650 AR_PHY_AGC_CONTROL_NF) == 0) 659 AR_PHY_AGC_CONTROL_NF) == 0)
651 break; 660 break;
652 udelay(10); 661 udelay(50);
653 } 662 }
654 663
655 for (i = 0; i < NUM_NF_READINGS; i++) { 664 for (i = 0; i < NUM_NF_READINGS; i++) {
@@ -665,6 +674,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
665int16_t ath9k_hw_getnf(struct ath_hw *ah, 674int16_t ath9k_hw_getnf(struct ath_hw *ah,
666 struct ath9k_channel *chan) 675 struct ath9k_channel *chan)
667{ 676{
677 struct ath_common *common = ath9k_hw_common(ah);
668 int16_t nf, nfThresh; 678 int16_t nf, nfThresh;
669 int16_t nfarray[NUM_NF_READINGS] = { 0 }; 679 int16_t nfarray[NUM_NF_READINGS] = { 0 };
670 struct ath9k_nfcal_hist *h; 680 struct ath9k_nfcal_hist *h;
@@ -672,8 +682,8 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
672 682
673 chan->channelFlags &= (~CHANNEL_CW_INT); 683 chan->channelFlags &= (~CHANNEL_CW_INT);
674 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 684 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
675 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 685 ath_print(common, ATH_DBG_CALIBRATE,
676 "NF did not complete in calibration window\n"); 686 "NF did not complete in calibration window\n");
677 nf = 0; 687 nf = 0;
678 chan->rawNoiseFloor = nf; 688 chan->rawNoiseFloor = nf;
679 return chan->rawNoiseFloor; 689 return chan->rawNoiseFloor;
@@ -682,10 +692,10 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
682 nf = nfarray[0]; 692 nf = nfarray[0];
683 if (getNoiseFloorThresh(ah, c->band, &nfThresh) 693 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
684 && nf > nfThresh) { 694 && nf > nfThresh) {
685 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 695 ath_print(common, ATH_DBG_CALIBRATE,
686 "noise floor failed detected; " 696 "noise floor failed detected; "
687 "detected %d, threshold %d\n", 697 "detected %d, threshold %d\n",
688 nf, nfThresh); 698 nf, nfThresh);
689 chan->channelFlags |= CHANNEL_CW_INT; 699 chan->channelFlags |= CHANNEL_CW_INT;
690 } 700 }
691 } 701 }
@@ -737,51 +747,73 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
737 747
738 return nf; 748 return nf;
739} 749}
750EXPORT_SYMBOL(ath9k_hw_getchan_noise);
740 751
741static void ath9k_olc_temp_compensation(struct ath_hw *ah) 752static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
742{ 753{
743 u32 rddata, i; 754 u32 rddata;
744 int delta, currPDADC, regval, slope; 755 int32_t delta, currPDADC, slope;
745 756
746 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); 757 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
747 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 758 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
748 759
760 if (ah->initPDADC == 0 || currPDADC == 0) {
761 /*
762 * Zero value indicates that no frames have been transmitted yet,
763 * can't do temperature compensation until frames are transmitted.
764 */
765 return;
766 } else {
767 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
768
769 if (slope == 0) { /* to avoid divide by zero case */
770 delta = 0;
771 } else {
772 delta = ((currPDADC - ah->initPDADC)*4) / slope;
773 }
774 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
775 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
776 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
777 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
778 }
779}
780
781static void ath9k_olc_temp_compensation(struct ath_hw *ah)
782{
783 u32 rddata, i;
784 int delta, currPDADC, regval;
749 785
750 if (OLC_FOR_AR9287_10_LATER) { 786 if (OLC_FOR_AR9287_10_LATER) {
787 ath9k_olc_temp_compensation_9287(ah);
788 } else {
789 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
790 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
791
751 if (ah->initPDADC == 0 || currPDADC == 0) { 792 if (ah->initPDADC == 0 || currPDADC == 0) {
752 return; 793 return;
753 } else { 794 } else {
754 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); 795 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
755 if (slope == 0) 796 delta = (currPDADC - ah->initPDADC + 4) / 8;
756 delta = 0;
757 else 797 else
758 delta = ((currPDADC - ah->initPDADC)*4) / slope; 798 delta = (currPDADC - ah->initPDADC + 5) / 10;
759 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, 799
760 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); 800 if (delta != ah->PDADCdelta) {
761 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, 801 ah->PDADCdelta = delta;
762 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); 802 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
763 } 803 regval = ah->originalGain[i] - delta;
764 } else { 804 if (regval < 0)
765 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) 805 regval = 0;
766 delta = (currPDADC - ah->initPDADC + 4) / 8; 806
767 else 807 REG_RMW_FIELD(ah,
768 delta = (currPDADC - ah->initPDADC + 5) / 10; 808 AR_PHY_TX_GAIN_TBL1 + i * 4,
769 809 AR_PHY_TX_GAIN, regval);
770 if (delta != ah->PDADCdelta) { 810 }
771 ah->PDADCdelta = delta;
772 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
773 regval = ah->originalGain[i] - delta;
774 if (regval < 0)
775 regval = 0;
776
777 REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4,
778 AR_PHY_TX_GAIN, regval);
779 } 811 }
780 } 812 }
781 } 813 }
782} 814}
783 815
784static void ath9k_hw_9271_pa_cal(struct ath_hw *ah) 816static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
785{ 817{
786 u32 regVal; 818 u32 regVal;
787 unsigned int i; 819 unsigned int i;
@@ -845,7 +877,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
845 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); 877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
846 878
847 /* find off_6_1; */ 879 /* find off_6_1; */
848 for (i = 6; i >= 0; i--) { 880 for (i = 6; i > 0; i--) {
849 regVal = REG_READ(ah, 0x7834); 881 regVal = REG_READ(ah, 0x7834);
850 regVal |= (1 << (20 + i)); 882 regVal |= (1 << (20 + i));
851 REG_WRITE(ah, 0x7834, regVal); 883 REG_WRITE(ah, 0x7834, regVal);
@@ -857,10 +889,19 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
857 REG_WRITE(ah, 0x7834, regVal); 889 REG_WRITE(ah, 0x7834, regVal);
858 } 890 }
859 891
860 /* Empirical offset correction */ 892 regVal = (regVal >>20) & 0x7f;
861#if 0 893
862 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0x20); 894 /* Update PA cal info */
863#endif 895 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
896 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
897 ah->pacal_info.max_skipcount =
898 2 * ah->pacal_info.max_skipcount;
899 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
900 } else {
901 ah->pacal_info.max_skipcount = 1;
902 ah->pacal_info.skipcount = 0;
903 ah->pacal_info.prev_offset = regVal;
904 }
864 905
865 regVal = REG_READ(ah, 0x7834); 906 regVal = REG_READ(ah, 0x7834);
866 regVal |= 0x1; 907 regVal |= 0x1;
@@ -875,7 +916,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
875 916
876static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) 917static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
877{ 918{
878 919 struct ath_common *common = ath9k_hw_common(ah);
879 u32 regVal; 920 u32 regVal;
880 int i, offset, offs_6_1, offs_0; 921 int i, offset, offs_6_1, offs_0;
881 u32 ccomp_org, reg_field; 922 u32 ccomp_org, reg_field;
@@ -889,7 +930,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
889 { 0x7838, 0 }, 930 { 0x7838, 0 },
890 }; 931 };
891 932
892 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); 933 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
893 934
894 /* PA CAL is not needed for high power solution */ 935 /* PA CAL is not needed for high power solution */
895 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 936 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -1011,7 +1052,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1011 if (longcal) { 1052 if (longcal) {
1012 /* Do periodic PAOffset Cal */ 1053 /* Do periodic PAOffset Cal */
1013 if (AR_SREV_9271(ah)) 1054 if (AR_SREV_9271(ah))
1014 ath9k_hw_9271_pa_cal(ah); 1055 ath9k_hw_9271_pa_cal(ah, false);
1015 else if (AR_SREV_9285_11_OR_LATER(ah)) { 1056 else if (AR_SREV_9285_11_OR_LATER(ah)) {
1016 if (!ah->pacal_info.skipcount) 1057 if (!ah->pacal_info.skipcount)
1017 ath9k_hw_9285_pa_cal(ah, false); 1058 ath9k_hw_9285_pa_cal(ah, false);
@@ -1036,9 +1077,13 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1036 1077
1037 return iscaldone; 1078 return iscaldone;
1038} 1079}
1080EXPORT_SYMBOL(ath9k_hw_calibrate);
1039 1081
1082/* Carrier leakage Calibration fix */
1040static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) 1083static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1041{ 1084{
1085 struct ath_common *common = ath9k_hw_common(ah);
1086
1042 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 1087 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1043 if (IS_CHAN_HT20(chan)) { 1088 if (IS_CHAN_HT20(chan)) {
1044 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 1089 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
@@ -1049,9 +1094,9 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1049 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1094 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1050 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 1095 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1051 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { 1096 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1052 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset " 1097 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1053 "calibration failed to complete in " 1098 "calibration failed to complete in "
1054 "1ms; noisy ??\n"); 1099 "1ms; noisy ??\n");
1055 return false; 1100 return false;
1056 } 1101 }
1057 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 1102 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -1064,8 +1109,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1064 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1109 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1065 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1110 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1066 0, AH_WAIT_TIMEOUT)) { 1111 0, AH_WAIT_TIMEOUT)) {
1067 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration " 1112 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1068 "failed to complete in 1ms; noisy ??\n"); 1113 "failed to complete in 1ms; noisy ??\n");
1069 return false; 1114 return false;
1070 } 1115 }
1071 1116
@@ -1078,7 +1123,9 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1078 1123
1079bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 1124bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1080{ 1125{
1081 if (AR_SREV_9285_12_OR_LATER(ah)) { 1126 struct ath_common *common = ath9k_hw_common(ah);
1127
1128 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
1082 if (!ar9285_clc(ah, chan)) 1129 if (!ar9285_clc(ah, chan))
1083 return false; 1130 return false;
1084 } else { 1131 } else {
@@ -1098,9 +1145,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1098 /* Poll for offset calibration complete */ 1145 /* Poll for offset calibration complete */
1099 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1146 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1100 0, AH_WAIT_TIMEOUT)) { 1147 0, AH_WAIT_TIMEOUT)) {
1101 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1148 ath_print(common, ATH_DBG_CALIBRATE,
1102 "offset calibration failed to complete in 1ms; " 1149 "offset calibration failed to "
1103 "noisy environment?\n"); 1150 "complete in 1ms; noisy environment?\n");
1104 return false; 1151 return false;
1105 } 1152 }
1106 1153
@@ -1114,7 +1161,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1114 } 1161 }
1115 1162
1116 /* Do PA Calibration */ 1163 /* Do PA Calibration */
1117 if (AR_SREV_9285_11_OR_LATER(ah)) 1164 if (AR_SREV_9271(ah))
1165 ath9k_hw_9271_pa_cal(ah, true);
1166 else if (AR_SREV_9285_11_OR_LATER(ah))
1118 ath9k_hw_9285_pa_cal(ah, true); 1167 ath9k_hw_9285_pa_cal(ah, true);
1119 1168
1120 /* Do NF Calibration after DC offset and other calibrations */ 1169 /* Do NF Calibration after DC offset and other calibrations */
@@ -1128,20 +1177,20 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1128 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 1177 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1129 INIT_CAL(&ah->adcgain_caldata); 1178 INIT_CAL(&ah->adcgain_caldata);
1130 INSERT_CAL(ah, &ah->adcgain_caldata); 1179 INSERT_CAL(ah, &ah->adcgain_caldata);
1131 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1180 ath_print(common, ATH_DBG_CALIBRATE,
1132 "enabling ADC Gain Calibration.\n"); 1181 "enabling ADC Gain Calibration.\n");
1133 } 1182 }
1134 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 1183 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1135 INIT_CAL(&ah->adcdc_caldata); 1184 INIT_CAL(&ah->adcdc_caldata);
1136 INSERT_CAL(ah, &ah->adcdc_caldata); 1185 INSERT_CAL(ah, &ah->adcdc_caldata);
1137 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1186 ath_print(common, ATH_DBG_CALIBRATE,
1138 "enabling ADC DC Calibration.\n"); 1187 "enabling ADC DC Calibration.\n");
1139 } 1188 }
1140 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 1189 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1141 INIT_CAL(&ah->iq_caldata); 1190 INIT_CAL(&ah->iq_caldata);
1142 INSERT_CAL(ah, &ah->iq_caldata); 1191 INSERT_CAL(ah, &ah->iq_caldata);
1143 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1192 ath_print(common, ATH_DBG_CALIBRATE,
1144 "enabling IQ Calibration.\n"); 1193 "enabling IQ Calibration.\n");
1145 } 1194 }
1146 1195
1147 ah->cal_list_curr = ah->cal_list; 1196 ah->cal_list_curr = ah->cal_list;
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 9028ab193e42..b2c873e97485 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -17,6 +17,8 @@
17#ifndef CALIB_H 17#ifndef CALIB_H
18#define CALIB_H 18#define CALIB_H
19 19
20#include "hw.h"
21
20extern const struct ath9k_percal_data iq_cal_multi_sample; 22extern const struct ath9k_percal_data iq_cal_multi_sample;
21extern const struct ath9k_percal_data iq_cal_single_sample; 23extern const struct ath9k_percal_data iq_cal_single_sample;
22extern const struct ath9k_percal_data adc_gain_cal_multi_sample; 24extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
new file mode 100644
index 000000000000..4d775ae141db
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -0,0 +1,299 @@
1/*
2 * Copyright (c) 2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * Module for common driver code between ath9k and ath9k_htc
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23
24#include "common.h"
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Shared library for Atheros wireless 802.11n LAN cards.");
28MODULE_LICENSE("Dual BSD/GPL");
29
30/* Common RX processing */
31
32/* Assumes you've already done the endian to CPU conversion */
33static bool ath9k_rx_accept(struct ath_common *common,
34 struct sk_buff *skb,
35 struct ieee80211_rx_status *rxs,
36 struct ath_rx_status *rx_stats,
37 bool *decrypt_error)
38{
39 struct ath_hw *ah = common->ah;
40 struct ieee80211_hdr *hdr;
41 __le16 fc;
42
43 hdr = (struct ieee80211_hdr *) skb->data;
44 fc = hdr->frame_control;
45
46 if (!rx_stats->rs_datalen)
47 return false;
48 /*
49 * rs_status follows rs_datalen so if rs_datalen is too large
50 * we can take a hint that hardware corrupted it, so ignore
51 * those frames.
52 */
53 if (rx_stats->rs_datalen > common->rx_bufsize)
54 return false;
55
56 /*
57 * rs_more indicates chained descriptors which can be used
58 * to link buffers together for a sort of scatter-gather
59 * operation.
60 *
61 * The rx_stats->rs_status will not be set until the end of the
62 * chained descriptors so it can be ignored if rs_more is set. The
63 * rs_more will be false at the last element of the chained
64 * descriptors.
65 */
66 if (!rx_stats->rs_more && rx_stats->rs_status != 0) {
67 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
68 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
69 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
70 return false;
71
72 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
73 *decrypt_error = true;
74 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
75 if (ieee80211_is_ctl(fc))
76 /*
77 * Sometimes, we get invalid
78 * MIC failures on valid control frames.
79 * Remove these mic errors.
80 */
81 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
82 else
83 rxs->flag |= RX_FLAG_MMIC_ERROR;
84 }
85 /*
86 * Reject error frames with the exception of
87 * decryption and MIC failures. For monitor mode,
88 * we also ignore the CRC error.
89 */
90 if (ah->opmode == NL80211_IFTYPE_MONITOR) {
91 if (rx_stats->rs_status &
92 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
93 ATH9K_RXERR_CRC))
94 return false;
95 } else {
96 if (rx_stats->rs_status &
97 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
98 return false;
99 }
100 }
101 }
102 return true;
103}
104
105static u8 ath9k_process_rate(struct ath_common *common,
106 struct ieee80211_hw *hw,
107 struct ath_rx_status *rx_stats,
108 struct ieee80211_rx_status *rxs,
109 struct sk_buff *skb)
110{
111 struct ieee80211_supported_band *sband;
112 enum ieee80211_band band;
113 unsigned int i = 0;
114
115 band = hw->conf.channel->band;
116 sband = hw->wiphy->bands[band];
117
118 if (rx_stats->rs_rate & 0x80) {
119 /* HT rate */
120 rxs->flag |= RX_FLAG_HT;
121 if (rx_stats->rs_flags & ATH9K_RX_2040)
122 rxs->flag |= RX_FLAG_40MHZ;
123 if (rx_stats->rs_flags & ATH9K_RX_GI)
124 rxs->flag |= RX_FLAG_SHORT_GI;
125 return rx_stats->rs_rate & 0x7f;
126 }
127
128 for (i = 0; i < sband->n_bitrates; i++) {
129 if (sband->bitrates[i].hw_value == rx_stats->rs_rate)
130 return i;
131 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
132 rxs->flag |= RX_FLAG_SHORTPRE;
133 return i;
134 }
135 }
136
137 /* No valid hardware bitrate found -- we should not get here */
138 ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
139 "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
140 if ((common->debug_mask & ATH_DBG_XMIT))
141 print_hex_dump_bytes("", DUMP_PREFIX_NONE, skb->data, skb->len);
142
143 return 0;
144}
145
146static void ath9k_process_rssi(struct ath_common *common,
147 struct ieee80211_hw *hw,
148 struct sk_buff *skb,
149 struct ath_rx_status *rx_stats)
150{
151 struct ath_hw *ah = common->ah;
152 struct ieee80211_sta *sta;
153 struct ieee80211_hdr *hdr;
154 struct ath_node *an;
155 int last_rssi = ATH_RSSI_DUMMY_MARKER;
156 __le16 fc;
157
158 hdr = (struct ieee80211_hdr *)skb->data;
159 fc = hdr->frame_control;
160
161 rcu_read_lock();
162 /*
163 * XXX: use ieee80211_find_sta! This requires quite a bit of work
164 * under the current ath9k virtual wiphy implementation as we have
165 * no way of tying a vif to wiphy. Typically vifs are attached to
166 * at least one sdata of a wiphy on mac80211 but with ath9k virtual
167 * wiphy you'd have to iterate over every wiphy and each sdata.
168 */
169 sta = ieee80211_find_sta_by_hw(hw, hdr->addr2);
170 if (sta) {
171 an = (struct ath_node *) sta->drv_priv;
172 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
173 !rx_stats->rs_moreaggr)
174 ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
175 last_rssi = an->last_rssi;
176 }
177 rcu_read_unlock();
178
179 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
180 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
181 ATH_RSSI_EP_MULTIPLIER);
182 if (rx_stats->rs_rssi < 0)
183 rx_stats->rs_rssi = 0;
184
185 /* Update Beacon RSSI, this is used by ANI. */
186 if (ieee80211_is_beacon(fc))
187 ah->stats.avgbrssi = rx_stats->rs_rssi;
188}
189
190/*
191 * For Decrypt or Demic errors, we only mark packet status here and always push
192 * up the frame up to let mac80211 handle the actual error case, be it no
193 * decryption key or real decryption error. This let us keep statistics there.
194 */
195int ath9k_cmn_rx_skb_preprocess(struct ath_common *common,
196 struct ieee80211_hw *hw,
197 struct sk_buff *skb,
198 struct ath_rx_status *rx_stats,
199 struct ieee80211_rx_status *rx_status,
200 bool *decrypt_error)
201{
202 struct ath_hw *ah = common->ah;
203
204 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
205 if (!ath9k_rx_accept(common, skb, rx_status, rx_stats, decrypt_error))
206 return -EINVAL;
207
208 ath9k_process_rssi(common, hw, skb, rx_stats);
209
210 rx_status->rate_idx = ath9k_process_rate(common, hw,
211 rx_stats, rx_status, skb);
212 rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp);
213 rx_status->band = hw->conf.channel->band;
214 rx_status->freq = hw->conf.channel->center_freq;
215 rx_status->noise = common->ani.noise_floor;
216 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
217 rx_status->antenna = rx_stats->rs_antenna;
218 rx_status->flag |= RX_FLAG_TSFT;
219
220 return 0;
221}
222EXPORT_SYMBOL(ath9k_cmn_rx_skb_preprocess);
223
224void ath9k_cmn_rx_skb_postprocess(struct ath_common *common,
225 struct sk_buff *skb,
226 struct ath_rx_status *rx_stats,
227 struct ieee80211_rx_status *rxs,
228 bool decrypt_error)
229{
230 struct ath_hw *ah = common->ah;
231 struct ieee80211_hdr *hdr;
232 int hdrlen, padpos, padsize;
233 u8 keyix;
234 __le16 fc;
235
236 /* see if any padding is done by the hw and remove it */
237 hdr = (struct ieee80211_hdr *) skb->data;
238 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
239 fc = hdr->frame_control;
240 padpos = ath9k_cmn_padpos(hdr->frame_control);
241
242 /* The MAC header is padded to have 32-bit boundary if the
243 * packet payload is non-zero. The general calculation for
244 * padsize would take into account odd header lengths:
245 * padsize = (4 - padpos % 4) % 4; However, since only
246 * even-length headers are used, padding can only be 0 or 2
247 * bytes and we can optimize this a bit. In addition, we must
248 * not try to remove padding from short control frames that do
249 * not have payload. */
250 padsize = padpos & 3;
251 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
252 memmove(skb->data + padsize, skb->data, padpos);
253 skb_pull(skb, padsize);
254 }
255
256 keyix = rx_stats->rs_keyix;
257
258 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) {
259 rxs->flag |= RX_FLAG_DECRYPTED;
260 } else if (ieee80211_has_protected(fc)
261 && !decrypt_error && skb->len >= hdrlen + 4) {
262 keyix = skb->data[hdrlen + 3] >> 6;
263
264 if (test_bit(keyix, common->keymap))
265 rxs->flag |= RX_FLAG_DECRYPTED;
266 }
267 if (ah->sw_mgmt_crypto &&
268 (rxs->flag & RX_FLAG_DECRYPTED) &&
269 ieee80211_is_mgmt(fc))
270 /* Use software decrypt for management frames. */
271 rxs->flag &= ~RX_FLAG_DECRYPTED;
272}
273EXPORT_SYMBOL(ath9k_cmn_rx_skb_postprocess);
274
275int ath9k_cmn_padpos(__le16 frame_control)
276{
277 int padpos = 24;
278 if (ieee80211_has_a4(frame_control)) {
279 padpos += ETH_ALEN;
280 }
281 if (ieee80211_is_data_qos(frame_control)) {
282 padpos += IEEE80211_QOS_CTL_LEN;
283 }
284
285 return padpos;
286}
287EXPORT_SYMBOL(ath9k_cmn_padpos);
288
289static int __init ath9k_cmn_init(void)
290{
291 return 0;
292}
293module_init(ath9k_cmn_init);
294
295static void __exit ath9k_cmn_exit(void)
296{
297 return;
298}
299module_exit(ath9k_cmn_exit);
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
new file mode 100644
index 000000000000..042999c2fe9c
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -0,0 +1,127 @@
1/*
2 * Copyright (c) 2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <net/mac80211.h>
18
19#include "../ath.h"
20#include "../debug.h"
21
22#include "hw.h"
23
24/* Common header for Atheros 802.11n base driver cores */
25
26#define WME_NUM_TID 16
27#define WME_BA_BMP_SIZE 64
28#define WME_MAX_BA WME_BA_BMP_SIZE
29#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
30
31#define WME_AC_BE 0
32#define WME_AC_BK 1
33#define WME_AC_VI 2
34#define WME_AC_VO 3
35#define WME_NUM_AC 4
36
37#define ATH_RSSI_DUMMY_MARKER 0x127
38#define ATH_RSSI_LPF_LEN 10
39#define RSSI_LPF_THRESHOLD -20
40#define ATH_RSSI_EP_MULTIPLIER (1<<7)
41#define ATH_EP_MUL(x, mul) ((x) * (mul))
42#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
43#define ATH_LPF_RSSI(x, y, len) \
44 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
45#define ATH_RSSI_LPF(x, y) do { \
46 if ((y) >= RSSI_LPF_THRESHOLD) \
47 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
48} while (0)
49#define ATH_EP_RND(x, mul) \
50 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
51
52struct ath_atx_ac {
53 int sched;
54 int qnum;
55 struct list_head list;
56 struct list_head tid_q;
57};
58
59struct ath_buf_state {
60 int bfs_nframes;
61 u16 bfs_al;
62 u16 bfs_frmlen;
63 int bfs_seqno;
64 int bfs_tidno;
65 int bfs_retries;
66 u8 bf_type;
67 u32 bfs_keyix;
68 enum ath9k_key_type bfs_keytype;
69};
70
71struct ath_buf {
72 struct list_head list;
73 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
74 an aggregate) */
75 struct ath_buf *bf_next; /* next subframe in the aggregate */
76 struct sk_buff *bf_mpdu; /* enclosing frame structure */
77 struct ath_desc *bf_desc; /* virtual addr of desc */
78 dma_addr_t bf_daddr; /* physical addr of desc */
79 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
80 bool bf_stale;
81 bool bf_isnullfunc;
82 u16 bf_flags;
83 struct ath_buf_state bf_state;
84 dma_addr_t bf_dmacontext;
85 struct ath_wiphy *aphy;
86};
87
88struct ath_atx_tid {
89 struct list_head list;
90 struct list_head buf_q;
91 struct ath_node *an;
92 struct ath_atx_ac *ac;
93 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
94 u16 seq_start;
95 u16 seq_next;
96 u16 baw_size;
97 int tidno;
98 int baw_head; /* first un-acked tx buffer */
99 int baw_tail; /* next unused tx buffer slot */
100 int sched;
101 int paused;
102 u8 state;
103};
104
105struct ath_node {
106 struct ath_common *common;
107 struct ath_atx_tid tid[WME_NUM_TID];
108 struct ath_atx_ac ac[WME_NUM_AC];
109 u16 maxampdu;
110 u8 mpdudensity;
111 int last_rssi;
112};
113
114int ath9k_cmn_rx_skb_preprocess(struct ath_common *common,
115 struct ieee80211_hw *hw,
116 struct sk_buff *skb,
117 struct ath_rx_status *rx_stats,
118 struct ieee80211_rx_status *rx_status,
119 bool *decrypt_error);
120
121void ath9k_cmn_rx_skb_postprocess(struct ath_common *common,
122 struct sk_buff *skb,
123 struct ath_rx_status *rx_stats,
124 struct ieee80211_rx_status *rxs,
125 bool decrypt_error);
126
127int ath9k_cmn_padpos(__le16 frame_control);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 2be4c2252047..081e0085ed4c 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -14,44 +14,35 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <linux/slab.h>
17#include <asm/unaligned.h> 18#include <asm/unaligned.h>
18 19
19#include "ath9k.h" 20#include "ath9k.h"
20 21
21static unsigned int ath9k_debug = DBG_DEFAULT; 22#define REG_WRITE_D(_ah, _reg, _val) \
22module_param_named(debug, ath9k_debug, uint, 0); 23 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
24#define REG_READ_D(_ah, _reg) \
25 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
23 26
24static struct dentry *ath9k_debugfs_root; 27static struct dentry *ath9k_debugfs_root;
25 28
26void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...)
27{
28 if (!sc)
29 return;
30
31 if (sc->debug.debug_mask & dbg_mask) {
32 va_list args;
33
34 va_start(args, fmt);
35 printk(KERN_DEBUG "ath9k: ");
36 vprintk(fmt, args);
37 va_end(args);
38 }
39}
40
41static int ath9k_debugfs_open(struct inode *inode, struct file *file) 29static int ath9k_debugfs_open(struct inode *inode, struct file *file)
42{ 30{
43 file->private_data = inode->i_private; 31 file->private_data = inode->i_private;
44 return 0; 32 return 0;
45} 33}
46 34
35#ifdef CONFIG_ATH_DEBUG
36
47static ssize_t read_file_debug(struct file *file, char __user *user_buf, 37static ssize_t read_file_debug(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos) 38 size_t count, loff_t *ppos)
49{ 39{
50 struct ath_softc *sc = file->private_data; 40 struct ath_softc *sc = file->private_data;
41 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
51 char buf[32]; 42 char buf[32];
52 unsigned int len; 43 unsigned int len;
53 44
54 len = snprintf(buf, sizeof(buf), "0x%08x\n", sc->debug.debug_mask); 45 len = snprintf(buf, sizeof(buf), "0x%08x\n", common->debug_mask);
55 return simple_read_from_buffer(user_buf, count, ppos, buf, len); 46 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
56} 47}
57 48
@@ -59,6 +50,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
59 size_t count, loff_t *ppos) 50 size_t count, loff_t *ppos)
60{ 51{
61 struct ath_softc *sc = file->private_data; 52 struct ath_softc *sc = file->private_data;
53 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
62 unsigned long mask; 54 unsigned long mask;
63 char buf[32]; 55 char buf[32];
64 ssize_t len; 56 ssize_t len;
@@ -71,7 +63,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
71 if (strict_strtoul(buf, 0, &mask)) 63 if (strict_strtoul(buf, 0, &mask))
72 return -EINVAL; 64 return -EINVAL;
73 65
74 sc->debug.debug_mask = mask; 66 common->debug_mask = mask;
75 return count; 67 return count;
76} 68}
77 69
@@ -82,38 +74,47 @@ static const struct file_operations fops_debug = {
82 .owner = THIS_MODULE 74 .owner = THIS_MODULE
83}; 75};
84 76
77#endif
78
79#define DMA_BUF_LEN 1024
80
85static ssize_t read_file_dma(struct file *file, char __user *user_buf, 81static ssize_t read_file_dma(struct file *file, char __user *user_buf,
86 size_t count, loff_t *ppos) 82 size_t count, loff_t *ppos)
87{ 83{
88 struct ath_softc *sc = file->private_data; 84 struct ath_softc *sc = file->private_data;
89 struct ath_hw *ah = sc->sc_ah; 85 struct ath_hw *ah = sc->sc_ah;
90 char buf[1024]; 86 char *buf;
87 int retval;
91 unsigned int len = 0; 88 unsigned int len = 0;
92 u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; 89 u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
93 int i, qcuOffset = 0, dcuOffset = 0; 90 int i, qcuOffset = 0, dcuOffset = 0;
94 u32 *qcuBase = &val[0], *dcuBase = &val[4]; 91 u32 *qcuBase = &val[0], *dcuBase = &val[4];
95 92
93 buf = kmalloc(DMA_BUF_LEN, GFP_KERNEL);
94 if (!buf)
95 return 0;
96
96 ath9k_ps_wakeup(sc); 97 ath9k_ps_wakeup(sc);
97 98
98 REG_WRITE(ah, AR_MACMISC, 99 REG_WRITE_D(ah, AR_MACMISC,
99 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 100 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
100 (AR_MACMISC_MISC_OBS_BUS_1 << 101 (AR_MACMISC_MISC_OBS_BUS_1 <<
101 AR_MACMISC_MISC_OBS_BUS_MSB_S))); 102 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
102 103
103 len += snprintf(buf + len, sizeof(buf) - len, 104 len += snprintf(buf + len, DMA_BUF_LEN - len,
104 "Raw DMA Debug values:\n"); 105 "Raw DMA Debug values:\n");
105 106
106 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) { 107 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
107 if (i % 4 == 0) 108 if (i % 4 == 0)
108 len += snprintf(buf + len, sizeof(buf) - len, "\n"); 109 len += snprintf(buf + len, DMA_BUF_LEN - len, "\n");
109 110
110 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))); 111 val[i] = REG_READ_D(ah, AR_DMADBG_0 + (i * sizeof(u32)));
111 len += snprintf(buf + len, sizeof(buf) - len, "%d: %08x ", 112 len += snprintf(buf + len, DMA_BUF_LEN - len, "%d: %08x ",
112 i, val[i]); 113 i, val[i]);
113 } 114 }
114 115
115 len += snprintf(buf + len, sizeof(buf) - len, "\n\n"); 116 len += snprintf(buf + len, DMA_BUF_LEN - len, "\n\n");
116 len += snprintf(buf + len, sizeof(buf) - len, 117 len += snprintf(buf + len, DMA_BUF_LEN - len,
117 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 118 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
118 119
119 for (i = 0; i < ATH9K_NUM_QUEUES; i++, qcuOffset += 4, dcuOffset += 5) { 120 for (i = 0; i < ATH9K_NUM_QUEUES; i++, qcuOffset += 4, dcuOffset += 5) {
@@ -127,7 +128,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
127 dcuBase++; 128 dcuBase++;
128 } 129 }
129 130
130 len += snprintf(buf + len, sizeof(buf) - len, 131 len += snprintf(buf + len, DMA_BUF_LEN - len,
131 "%2d %2x %1x %2x %2x\n", 132 "%2d %2x %1x %2x %2x\n",
132 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset, 133 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
133 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + 3), 134 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + 3),
@@ -135,35 +136,37 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
135 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset); 136 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
136 } 137 }
137 138
138 len += snprintf(buf + len, sizeof(buf) - len, "\n"); 139 len += snprintf(buf + len, DMA_BUF_LEN - len, "\n");
139 140
140 len += snprintf(buf + len, sizeof(buf) - len, 141 len += snprintf(buf + len, DMA_BUF_LEN - len,
141 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 142 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
142 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 143 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
143 len += snprintf(buf + len, sizeof(buf) - len, 144 len += snprintf(buf + len, DMA_BUF_LEN - len,
144 "qcu_complete state: %2x dcu_complete state: %2x\n", 145 "qcu_complete state: %2x dcu_complete state: %2x\n",
145 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 146 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
146 len += snprintf(buf + len, sizeof(buf) - len, 147 len += snprintf(buf + len, DMA_BUF_LEN - len,
147 "dcu_arb state: %2x dcu_fp state: %2x\n", 148 "dcu_arb state: %2x dcu_fp state: %2x\n",
148 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 149 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
149 len += snprintf(buf + len, sizeof(buf) - len, 150 len += snprintf(buf + len, DMA_BUF_LEN - len,
150 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 151 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
151 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 152 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
152 len += snprintf(buf + len, sizeof(buf) - len, 153 len += snprintf(buf + len, DMA_BUF_LEN - len,
153 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 154 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
154 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 155 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
155 len += snprintf(buf + len, sizeof(buf) - len, 156 len += snprintf(buf + len, DMA_BUF_LEN - len,
156 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 157 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
157 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 158 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
158 159
159 len += snprintf(buf + len, sizeof(buf) - len, "pcu observe: 0x%x \n", 160 len += snprintf(buf + len, DMA_BUF_LEN - len, "pcu observe: 0x%x \n",
160 REG_READ(ah, AR_OBS_BUS_1)); 161 REG_READ_D(ah, AR_OBS_BUS_1));
161 len += snprintf(buf + len, sizeof(buf) - len, 162 len += snprintf(buf + len, DMA_BUF_LEN - len,
162 "AR_CR: 0x%x \n", REG_READ(ah, AR_CR)); 163 "AR_CR: 0x%x \n", REG_READ_D(ah, AR_CR));
163 164
164 ath9k_ps_restore(sc); 165 ath9k_ps_restore(sc);
165 166
166 return simple_read_from_buffer(user_buf, count, ppos, buf, len); 167 retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
168 kfree(buf);
169 return retval;
167} 170}
168 171
169static const struct file_operations fops_dma = { 172static const struct file_operations fops_dma = {
@@ -266,18 +269,11 @@ static const struct file_operations fops_interrupt = {
266 .owner = THIS_MODULE 269 .owner = THIS_MODULE
267}; 270};
268 271
269void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb) 272void ath_debug_stat_rc(struct ath_softc *sc, int final_rate)
270{ 273{
271 struct ath_tx_info_priv *tx_info_priv = NULL;
272 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
273 struct ieee80211_tx_rate *rates = tx_info->status.rates;
274 int final_ts_idx, idx;
275 struct ath_rc_stats *stats; 274 struct ath_rc_stats *stats;
276 275
277 tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 276 stats = &sc->debug.stats.rcstats[final_rate];
278 final_ts_idx = tx_info_priv->tx.ts_rateindex;
279 idx = rates[final_ts_idx].idx;
280 stats = &sc->debug.stats.rcstats[idx];
281 stats->success++; 277 stats->success++;
282} 278}
283 279
@@ -303,23 +299,49 @@ static ssize_t read_file_rcstat(struct file *file, char __user *user_buf,
303 if (sc->cur_rate_table == NULL) 299 if (sc->cur_rate_table == NULL)
304 return 0; 300 return 0;
305 301
306 max = 80 + sc->cur_rate_table->rate_cnt * 64; 302 max = 80 + sc->cur_rate_table->rate_cnt * 1024;
307 buf = kmalloc(max + 1, GFP_KERNEL); 303 buf = kmalloc(max + 1, GFP_KERNEL);
308 if (buf == NULL) 304 if (buf == NULL)
309 return 0; 305 return 0;
310 buf[max] = 0; 306 buf[max] = 0;
311 307
312 len += sprintf(buf, "%5s %15s %8s %9s %3s\n\n", "Rate", "Success", 308 len += sprintf(buf, "%6s %6s %6s "
313 "Retries", "XRetries", "PER"); 309 "%10s %10s %10s %10s\n",
310 "HT", "MCS", "Rate",
311 "Success", "Retries", "XRetries", "PER");
314 312
315 for (i = 0; i < sc->cur_rate_table->rate_cnt; i++) { 313 for (i = 0; i < sc->cur_rate_table->rate_cnt; i++) {
316 u32 ratekbps = sc->cur_rate_table->info[i].ratekbps; 314 u32 ratekbps = sc->cur_rate_table->info[i].ratekbps;
317 struct ath_rc_stats *stats = &sc->debug.stats.rcstats[i]; 315 struct ath_rc_stats *stats = &sc->debug.stats.rcstats[i];
316 char mcs[5];
317 char htmode[5];
318 int used_mcs = 0, used_htmode = 0;
319
320 if (WLAN_RC_PHY_HT(sc->cur_rate_table->info[i].phy)) {
321 used_mcs = snprintf(mcs, 5, "%d",
322 sc->cur_rate_table->info[i].ratecode);
323
324 if (WLAN_RC_PHY_40(sc->cur_rate_table->info[i].phy))
325 used_htmode = snprintf(htmode, 5, "HT40");
326 else if (WLAN_RC_PHY_20(sc->cur_rate_table->info[i].phy))
327 used_htmode = snprintf(htmode, 5, "HT20");
328 else
329 used_htmode = snprintf(htmode, 5, "????");
330 }
331
332 mcs[used_mcs] = '\0';
333 htmode[used_htmode] = '\0';
318 334
319 len += snprintf(buf + len, max - len, 335 len += snprintf(buf + len, max - len,
320 "%3u.%d: %8u %8u %8u %8u\n", ratekbps / 1000, 336 "%6s %6s %3u.%d: "
321 (ratekbps % 1000) / 100, stats->success, 337 "%10u %10u %10u %10u\n",
322 stats->retries, stats->xretries, 338 htmode,
339 mcs,
340 ratekbps / 1000,
341 (ratekbps % 1000) / 100,
342 stats->success,
343 stats->retries,
344 stats->xretries,
323 stats->per); 345 stats->per);
324 } 346 }
325 347
@@ -376,12 +398,12 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
376 aphy->chan_idx, aphy->chan_is_ht); 398 aphy->chan_idx, aphy->chan_is_ht);
377 } 399 }
378 400
379 put_unaligned_le32(REG_READ(sc->sc_ah, AR_STA_ID0), addr); 401 put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_STA_ID0), addr);
380 put_unaligned_le16(REG_READ(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4); 402 put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4);
381 len += snprintf(buf + len, sizeof(buf) - len, 403 len += snprintf(buf + len, sizeof(buf) - len,
382 "addr: %pM\n", addr); 404 "addr: %pM\n", addr);
383 put_unaligned_le32(REG_READ(sc->sc_ah, AR_BSSMSKL), addr); 405 put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_BSSMSKL), addr);
384 put_unaligned_le16(REG_READ(sc->sc_ah, AR_BSSMSKU) & 0xffff, addr + 4); 406 put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_BSSMSKU) & 0xffff, addr + 4);
385 len += snprintf(buf + len, sizeof(buf) - len, 407 len += snprintf(buf + len, sizeof(buf) - len,
386 "addrmask: %pM\n", addr); 408 "addrmask: %pM\n", addr);
387 409
@@ -568,9 +590,120 @@ static const struct file_operations fops_xmit = {
568 .owner = THIS_MODULE 590 .owner = THIS_MODULE
569}; 591};
570 592
571int ath9k_init_debug(struct ath_softc *sc) 593static ssize_t read_file_recv(struct file *file, char __user *user_buf,
594 size_t count, loff_t *ppos)
572{ 595{
573 sc->debug.debug_mask = ath9k_debug; 596#define PHY_ERR(s, p) \
597 len += snprintf(buf + len, size - len, "%18s : %10u\n", s, \
598 sc->debug.stats.rxstats.phy_err_stats[p]);
599
600 struct ath_softc *sc = file->private_data;
601 char *buf;
602 unsigned int len = 0, size = 1152;
603 ssize_t retval = 0;
604
605 buf = kzalloc(size, GFP_KERNEL);
606 if (buf == NULL)
607 return 0;
608
609 len += snprintf(buf + len, size - len,
610 "%18s : %10u\n", "CRC ERR",
611 sc->debug.stats.rxstats.crc_err);
612 len += snprintf(buf + len, size - len,
613 "%18s : %10u\n", "DECRYPT CRC ERR",
614 sc->debug.stats.rxstats.decrypt_crc_err);
615 len += snprintf(buf + len, size - len,
616 "%18s : %10u\n", "PHY ERR",
617 sc->debug.stats.rxstats.phy_err);
618 len += snprintf(buf + len, size - len,
619 "%18s : %10u\n", "MIC ERR",
620 sc->debug.stats.rxstats.mic_err);
621 len += snprintf(buf + len, size - len,
622 "%18s : %10u\n", "PRE-DELIM CRC ERR",
623 sc->debug.stats.rxstats.pre_delim_crc_err);
624 len += snprintf(buf + len, size - len,
625 "%18s : %10u\n", "POST-DELIM CRC ERR",
626 sc->debug.stats.rxstats.post_delim_crc_err);
627 len += snprintf(buf + len, size - len,
628 "%18s : %10u\n", "DECRYPT BUSY ERR",
629 sc->debug.stats.rxstats.decrypt_busy_err);
630
631 PHY_ERR("UNDERRUN", ATH9K_PHYERR_UNDERRUN);
632 PHY_ERR("TIMING", ATH9K_PHYERR_TIMING);
633 PHY_ERR("PARITY", ATH9K_PHYERR_PARITY);
634 PHY_ERR("RATE", ATH9K_PHYERR_RATE);
635 PHY_ERR("LENGTH", ATH9K_PHYERR_LENGTH);
636 PHY_ERR("RADAR", ATH9K_PHYERR_RADAR);
637 PHY_ERR("SERVICE", ATH9K_PHYERR_SERVICE);
638 PHY_ERR("TOR", ATH9K_PHYERR_TOR);
639 PHY_ERR("OFDM-TIMING", ATH9K_PHYERR_OFDM_TIMING);
640 PHY_ERR("OFDM-SIGNAL-PARITY", ATH9K_PHYERR_OFDM_SIGNAL_PARITY);
641 PHY_ERR("OFDM-RATE", ATH9K_PHYERR_OFDM_RATE_ILLEGAL);
642 PHY_ERR("OFDM-LENGTH", ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL);
643 PHY_ERR("OFDM-POWER-DROP", ATH9K_PHYERR_OFDM_POWER_DROP);
644 PHY_ERR("OFDM-SERVICE", ATH9K_PHYERR_OFDM_SERVICE);
645 PHY_ERR("OFDM-RESTART", ATH9K_PHYERR_OFDM_RESTART);
646 PHY_ERR("FALSE-RADAR-EXT", ATH9K_PHYERR_FALSE_RADAR_EXT);
647 PHY_ERR("CCK-TIMING", ATH9K_PHYERR_CCK_TIMING);
648 PHY_ERR("CCK-HEADER-CRC", ATH9K_PHYERR_CCK_HEADER_CRC);
649 PHY_ERR("CCK-RATE", ATH9K_PHYERR_CCK_RATE_ILLEGAL);
650 PHY_ERR("CCK-SERVICE", ATH9K_PHYERR_CCK_SERVICE);
651 PHY_ERR("CCK-RESTART", ATH9K_PHYERR_CCK_RESTART);
652 PHY_ERR("CCK-LENGTH", ATH9K_PHYERR_CCK_LENGTH_ILLEGAL);
653 PHY_ERR("CCK-POWER-DROP", ATH9K_PHYERR_CCK_POWER_DROP);
654 PHY_ERR("HT-CRC", ATH9K_PHYERR_HT_CRC_ERROR);
655 PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL);
656 PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL);
657
658 retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
659 kfree(buf);
660
661 return retval;
662
663#undef PHY_ERR
664}
665
666void ath_debug_stat_rx(struct ath_softc *sc, struct ath_buf *bf)
667{
668#define RX_STAT_INC(c) sc->debug.stats.rxstats.c++
669#define RX_PHY_ERR_INC(c) sc->debug.stats.rxstats.phy_err_stats[c]++
670
671 struct ath_desc *ds = bf->bf_desc;
672 u32 phyerr;
673
674 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
675 RX_STAT_INC(crc_err);
676 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT)
677 RX_STAT_INC(decrypt_crc_err);
678 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC)
679 RX_STAT_INC(mic_err);
680 if (ds->ds_rxstat.rs_status & ATH9K_RX_DELIM_CRC_PRE)
681 RX_STAT_INC(pre_delim_crc_err);
682 if (ds->ds_rxstat.rs_status & ATH9K_RX_DELIM_CRC_POST)
683 RX_STAT_INC(post_delim_crc_err);
684 if (ds->ds_rxstat.rs_status & ATH9K_RX_DECRYPT_BUSY)
685 RX_STAT_INC(decrypt_busy_err);
686
687 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) {
688 RX_STAT_INC(phy_err);
689 phyerr = ds->ds_rxstat.rs_phyerr & 0x24;
690 RX_PHY_ERR_INC(phyerr);
691 }
692
693#undef RX_STAT_INC
694#undef RX_PHY_ERR_INC
695}
696
697static const struct file_operations fops_recv = {
698 .read = read_file_recv,
699 .open = ath9k_debugfs_open,
700 .owner = THIS_MODULE
701};
702
703int ath9k_init_debug(struct ath_hw *ah)
704{
705 struct ath_common *common = ath9k_hw_common(ah);
706 struct ath_softc *sc = (struct ath_softc *) common->priv;
574 707
575 if (!ath9k_debugfs_root) 708 if (!ath9k_debugfs_root)
576 return -ENOENT; 709 return -ENOENT;
@@ -580,10 +713,12 @@ int ath9k_init_debug(struct ath_softc *sc)
580 if (!sc->debug.debugfs_phy) 713 if (!sc->debug.debugfs_phy)
581 goto err; 714 goto err;
582 715
716#ifdef CONFIG_ATH_DEBUG
583 sc->debug.debugfs_debug = debugfs_create_file("debug", 717 sc->debug.debugfs_debug = debugfs_create_file("debug",
584 S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, sc, &fops_debug); 718 S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, sc, &fops_debug);
585 if (!sc->debug.debugfs_debug) 719 if (!sc->debug.debugfs_debug)
586 goto err; 720 goto err;
721#endif
587 722
588 sc->debug.debugfs_dma = debugfs_create_file("dma", S_IRUSR, 723 sc->debug.debugfs_dma = debugfs_create_file("dma", S_IRUSR,
589 sc->debug.debugfs_phy, sc, &fops_dma); 724 sc->debug.debugfs_phy, sc, &fops_dma);
@@ -617,14 +752,25 @@ int ath9k_init_debug(struct ath_softc *sc)
617 if (!sc->debug.debugfs_xmit) 752 if (!sc->debug.debugfs_xmit)
618 goto err; 753 goto err;
619 754
755 sc->debug.debugfs_recv = debugfs_create_file("recv",
756 S_IRUSR,
757 sc->debug.debugfs_phy,
758 sc, &fops_recv);
759 if (!sc->debug.debugfs_recv)
760 goto err;
761
620 return 0; 762 return 0;
621err: 763err:
622 ath9k_exit_debug(sc); 764 ath9k_exit_debug(ah);
623 return -ENOMEM; 765 return -ENOMEM;
624} 766}
625 767
626void ath9k_exit_debug(struct ath_softc *sc) 768void ath9k_exit_debug(struct ath_hw *ah)
627{ 769{
770 struct ath_common *common = ath9k_hw_common(ah);
771 struct ath_softc *sc = (struct ath_softc *) common->priv;
772
773 debugfs_remove(sc->debug.debugfs_recv);
628 debugfs_remove(sc->debug.debugfs_xmit); 774 debugfs_remove(sc->debug.debugfs_xmit);
629 debugfs_remove(sc->debug.debugfs_wiphy); 775 debugfs_remove(sc->debug.debugfs_wiphy);
630 debugfs_remove(sc->debug.debugfs_rcstat); 776 debugfs_remove(sc->debug.debugfs_rcstat);
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 7241f4748338..86780e68b31e 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -17,36 +17,19 @@
17#ifndef DEBUG_H 17#ifndef DEBUG_H
18#define DEBUG_H 18#define DEBUG_H
19 19
20enum ATH_DEBUG { 20#include "hw.h"
21 ATH_DBG_RESET = 0x00000001, 21#include "rc.h"
22 ATH_DBG_QUEUE = 0x00000002,
23 ATH_DBG_EEPROM = 0x00000004,
24 ATH_DBG_CALIBRATE = 0x00000008,
25 ATH_DBG_INTERRUPT = 0x00000010,
26 ATH_DBG_REGULATORY = 0x00000020,
27 ATH_DBG_ANI = 0x00000040,
28 ATH_DBG_XMIT = 0x00000080,
29 ATH_DBG_BEACON = 0x00000100,
30 ATH_DBG_CONFIG = 0x00000200,
31 ATH_DBG_FATAL = 0x00000400,
32 ATH_DBG_PS = 0x00000800,
33 ATH_DBG_HWTIMER = 0x00001000,
34 ATH_DBG_BTCOEX = 0x00002000,
35 ATH_DBG_ANY = 0xffffffff
36};
37
38#define DBG_DEFAULT (ATH_DBG_FATAL)
39 22
40struct ath_txq; 23struct ath_txq;
41struct ath_buf; 24struct ath_buf;
42 25
43#ifdef CONFIG_ATH9K_DEBUG 26#ifdef CONFIG_ATH9K_DEBUGFS
44#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 27#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
45#else 28#else
46#define TX_STAT_INC(q, c) do { } while (0) 29#define TX_STAT_INC(q, c) do { } while (0)
47#endif 30#endif
48 31
49#ifdef CONFIG_ATH9K_DEBUG 32#ifdef CONFIG_ATH9K_DEBUGFS
50 33
51/** 34/**
52 * struct ath_interrupt_stats - Contains statistics about interrupts 35 * struct ath_interrupt_stats - Contains statistics about interrupts
@@ -133,14 +116,38 @@ struct ath_tx_stats {
133 u32 delim_underrun; 116 u32 delim_underrun;
134}; 117};
135 118
119/**
120 * struct ath_rx_stats - RX Statistics
121 * @crc_err: No. of frames with incorrect CRC value
122 * @decrypt_crc_err: No. of frames whose CRC check failed after
123 decryption process completed
124 * @phy_err: No. of frames whose reception failed because the PHY
125 encountered an error
126 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
127 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
128 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
129 * @decrypt_busy_err: Decryption interruptions counter
130 * @phy_err_stats: Individual PHY error statistics
131 */
132struct ath_rx_stats {
133 u32 crc_err;
134 u32 decrypt_crc_err;
135 u32 phy_err;
136 u32 mic_err;
137 u32 pre_delim_crc_err;
138 u32 post_delim_crc_err;
139 u32 decrypt_busy_err;
140 u32 phy_err_stats[ATH9K_PHYERR_MAX];
141};
142
136struct ath_stats { 143struct ath_stats {
137 struct ath_interrupt_stats istats; 144 struct ath_interrupt_stats istats;
138 struct ath_rc_stats rcstats[RATE_TABLE_SIZE]; 145 struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
139 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 146 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
147 struct ath_rx_stats rxstats;
140}; 148};
141 149
142struct ath9k_debug { 150struct ath9k_debug {
143 int debug_mask;
144 struct dentry *debugfs_phy; 151 struct dentry *debugfs_phy;
145 struct dentry *debugfs_debug; 152 struct dentry *debugfs_debug;
146 struct dentry *debugfs_dma; 153 struct dentry *debugfs_dma;
@@ -148,34 +155,31 @@ struct ath9k_debug {
148 struct dentry *debugfs_rcstat; 155 struct dentry *debugfs_rcstat;
149 struct dentry *debugfs_wiphy; 156 struct dentry *debugfs_wiphy;
150 struct dentry *debugfs_xmit; 157 struct dentry *debugfs_xmit;
158 struct dentry *debugfs_recv;
151 struct ath_stats stats; 159 struct ath_stats stats;
152}; 160};
153 161
154void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...); 162int ath9k_init_debug(struct ath_hw *ah);
155int ath9k_init_debug(struct ath_softc *sc); 163void ath9k_exit_debug(struct ath_hw *ah);
156void ath9k_exit_debug(struct ath_softc *sc); 164
157int ath9k_debug_create_root(void); 165int ath9k_debug_create_root(void);
158void ath9k_debug_remove_root(void); 166void ath9k_debug_remove_root(void);
159void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 167void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
160void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb); 168void ath_debug_stat_rc(struct ath_softc *sc, int final_rate);
161void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq, 169void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
162 struct ath_buf *bf); 170 struct ath_buf *bf);
171void ath_debug_stat_rx(struct ath_softc *sc, struct ath_buf *bf);
163void ath_debug_stat_retries(struct ath_softc *sc, int rix, 172void ath_debug_stat_retries(struct ath_softc *sc, int rix,
164 int xretries, int retries, u8 per); 173 int xretries, int retries, u8 per);
165 174
166#else 175#else
167 176
168static inline void DPRINTF(struct ath_softc *sc, int dbg_mask, 177static inline int ath9k_init_debug(struct ath_hw *ah)
169 const char *fmt, ...)
170{
171}
172
173static inline int ath9k_init_debug(struct ath_softc *sc)
174{ 178{
175 return 0; 179 return 0;
176} 180}
177 181
178static inline void ath9k_exit_debug(struct ath_softc *sc) 182static inline void ath9k_exit_debug(struct ath_hw *ah)
179{ 183{
180} 184}
181 185
@@ -194,7 +198,7 @@ static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
194} 198}
195 199
196static inline void ath_debug_stat_rc(struct ath_softc *sc, 200static inline void ath_debug_stat_rc(struct ath_softc *sc,
197 struct sk_buff *skb) 201 int final_rate)
198{ 202{
199} 203}
200 204
@@ -204,11 +208,16 @@ static inline void ath_debug_stat_tx(struct ath_softc *sc,
204{ 208{
205} 209}
206 210
211static inline void ath_debug_stat_rx(struct ath_softc *sc,
212 struct ath_buf *bf)
213{
214}
215
207static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix, 216static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
208 int xretries, int retries, u8 per) 217 int xretries, int retries, u8 per)
209{ 218{
210} 219}
211 220
212#endif /* CONFIG_ATH9K_DEBUG */ 221#endif /* CONFIG_ATH9K_DEBUGFS */
213 222
214#endif /* DEBUG_H */ 223#endif /* DEBUG_H */
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index b6e52d0f8c48..dacaae934148 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
20{ 20{
@@ -83,11 +83,9 @@ bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
83 return false; 83 return false;
84} 84}
85 85
86bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) 86bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
87{ 87{
88 struct ath_softc *sc = ah->ah_sc; 88 return common->bus_ops->eeprom_read(common, off, data);
89
90 return sc->bus_ops->eeprom_read(ah, off, data);
91} 89}
92 90
93void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 91void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 4fe33f7eee9d..2f2993b50e2f 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -17,6 +17,7 @@
17#ifndef EEPROM_H 17#ifndef EEPROM_H
18#define EEPROM_H 18#define EEPROM_H
19 19
20#include "../ath.h"
20#include <net/cfg80211.h> 21#include <net/cfg80211.h>
21 22
22#define AH_USE_EEPROM 0x1 23#define AH_USE_EEPROM 0x1
@@ -133,6 +134,7 @@
133#define AR5416_EEP_MINOR_VER_17 0x11 134#define AR5416_EEP_MINOR_VER_17 0x11
134#define AR5416_EEP_MINOR_VER_19 0x13 135#define AR5416_EEP_MINOR_VER_19 0x13
135#define AR5416_EEP_MINOR_VER_20 0x14 136#define AR5416_EEP_MINOR_VER_20 0x14
137#define AR5416_EEP_MINOR_VER_21 0x15
136#define AR5416_EEP_MINOR_VER_22 0x16 138#define AR5416_EEP_MINOR_VER_22 0x16
137 139
138#define AR5416_NUM_5G_CAL_PIERS 8 140#define AR5416_NUM_5G_CAL_PIERS 8
@@ -153,7 +155,7 @@
153#define AR5416_BCHAN_UNUSED 0xFF 155#define AR5416_BCHAN_UNUSED 0xFF
154#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
155#define AR5416_MAX_CHAINS 3 157#define AR5416_MAX_CHAINS 3
156#define AR5416_PWR_TABLE_OFFSET -5 158#define AR5416_PWR_TABLE_OFFSET_DB -5
157 159
158/* Rx gain type values */ 160/* Rx gain type values */
159#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 161#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
@@ -301,7 +303,7 @@ struct base_eep_header {
301 u8 txGainType; 303 u8 txGainType;
302 u8 rcChainMask; 304 u8 rcChainMask;
303 u8 desiredScaleCCK; 305 u8 desiredScaleCCK;
304 u8 power_table_offset; 306 u8 pwr_table_offset;
305 u8 frac_n_5g; 307 u8 frac_n_5g;
306 u8 futureBase_3[21]; 308 u8 futureBase_3[21];
307} __packed; 309} __packed;
@@ -638,6 +640,7 @@ struct ar9287_eeprom {
638} __packed; 640} __packed;
639 641
640enum reg_ext_bitmap { 642enum reg_ext_bitmap {
643 REG_EXT_FCC_MIDBAND = 0,
641 REG_EXT_JAPAN_MIDBAND = 1, 644 REG_EXT_JAPAN_MIDBAND = 1,
642 REG_EXT_FCC_DFS_HT40 = 2, 645 REG_EXT_FCC_DFS_HT40 = 2,
643 REG_EXT_JAPAN_NONDFS_HT40 = 3, 646 REG_EXT_JAPAN_NONDFS_HT40 = 3,
@@ -684,7 +687,7 @@ int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
684 int16_t targetRight); 687 int16_t targetRight);
685bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 688bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
686 u16 *indexL, u16 *indexR); 689 u16 *indexL, u16 *indexR);
687bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); 690bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
688void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 691void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
689 u8 *pVpdList, u16 numIntercepts, 692 u8 *pVpdList, u16 numIntercepts,
690 u8 *pRetVpdList); 693 u8 *pRetVpdList);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index b8eca7be5f3a..68db16690abf 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20{ 20{
@@ -29,20 +29,21 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
29static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 29static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
30{ 30{
31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
32 struct ath_common *common = ath9k_hw_common(ah);
32 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 33 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
33 int addr, eep_start_loc = 0; 34 int addr, eep_start_loc = 0;
34 35
35 eep_start_loc = 64; 36 eep_start_loc = 64;
36 37
37 if (!ath9k_hw_use_flash(ah)) { 38 if (!ath9k_hw_use_flash(ah)) {
38 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 39 ath_print(common, ATH_DBG_EEPROM,
39 "Reading from EEPROM, not flash\n"); 40 "Reading from EEPROM, not flash\n");
40 } 41 }
41 42
42 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 43 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 44 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 45 ath_print(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n"); 46 "Unable to read eeprom region \n");
46 return false; 47 return false;
47 } 48 }
48 eep_data++; 49 eep_data++;
@@ -55,6 +56,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
55static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) 56static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
56{ 57{
57#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 58#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
59 struct ath_common *common = ath9k_hw_common(ah);
58 struct ar5416_eeprom_4k *eep = 60 struct ar5416_eeprom_4k *eep =
59 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; 61 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
60 u16 *eepdata, temp, magic, magic2; 62 u16 *eepdata, temp, magic, magic2;
@@ -64,15 +66,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
64 66
65 67
66 if (!ath9k_hw_use_flash(ah)) { 68 if (!ath9k_hw_use_flash(ah)) {
67 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 69 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
68 &magic)) { 70 &magic)) {
69 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 71 ath_print(common, ATH_DBG_FATAL,
70 "Reading Magic # failed\n"); 72 "Reading Magic # failed\n");
71 return false; 73 return false;
72 } 74 }
73 75
74 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 76 ath_print(common, ATH_DBG_EEPROM,
75 "Read Magic = 0x%04X\n", magic); 77 "Read Magic = 0x%04X\n", magic);
76 78
77 if (magic != AR5416_EEPROM_MAGIC) { 79 if (magic != AR5416_EEPROM_MAGIC) {
78 magic2 = swab16(magic); 80 magic2 = swab16(magic);
@@ -87,16 +89,16 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
87 eepdata++; 89 eepdata++;
88 } 90 }
89 } else { 91 } else {
90 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 92 ath_print(common, ATH_DBG_FATAL,
91 "Invalid EEPROM Magic. " 93 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n"); 94 "endianness mismatch.\n");
93 return -EINVAL; 95 return -EINVAL;
94 } 96 }
95 } 97 }
96 } 98 }
97 99
98 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 100 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
99 need_swap ? "True" : "False"); 101 need_swap ? "True" : "False");
100 102
101 if (need_swap) 103 if (need_swap)
102 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 104 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -117,8 +119,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
117 u32 integer; 119 u32 integer;
118 u16 word; 120 u16 word;
119 121
120 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 122 ath_print(common, ATH_DBG_EEPROM,
121 "EEPROM Endianness is not native.. Changing\n"); 123 "EEPROM Endianness is not native.. Changing\n");
122 124
123 word = swab16(eep->baseEepHeader.length); 125 word = swab16(eep->baseEepHeader.length);
124 eep->baseEepHeader.length = word; 126 eep->baseEepHeader.length = word;
@@ -160,9 +162,9 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
160 162
161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 163 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
162 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 164 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 165 ath_print(common, ATH_DBG_FATAL,
164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 166 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
165 sum, ah->eep_ops->get_eeprom_ver(ah)); 167 sum, ah->eep_ops->get_eeprom_ver(ah));
166 return -EINVAL; 168 return -EINVAL;
167 } 169 }
168 170
@@ -208,6 +210,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
208 return pBase->rxMask; 210 return pBase->rxMask;
209 case EEP_FRAC_N_5G: 211 case EEP_FRAC_N_5G:
210 return 0; 212 return 0;
213 case EEP_PWR_TABLE_OFFSET:
214 return AR5416_PWR_TABLE_OFFSET_DB;
211 default: 215 default:
212 return 0; 216 return 0;
213 } 217 }
@@ -385,6 +389,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
385 struct ath9k_channel *chan, 389 struct ath9k_channel *chan,
386 int16_t *pTxPowerIndexOffset) 390 int16_t *pTxPowerIndexOffset)
387{ 391{
392 struct ath_common *common = ath9k_hw_common(ah);
388 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 393 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
389 struct cal_data_per_freq_4k *pRawDataset; 394 struct cal_data_per_freq_4k *pRawDataset;
390 u8 *pCalBChans = NULL; 395 u8 *pCalBChans = NULL;
@@ -470,21 +475,21 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
470 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 475 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
471 REG_WRITE(ah, regOffset, reg32); 476 REG_WRITE(ah, regOffset, reg32);
472 477
473 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 478 ath_print(common, ATH_DBG_EEPROM,
474 "PDADC (%d,%4x): %4.4x %8.8x\n", 479 "PDADC (%d,%4x): %4.4x %8.8x\n",
475 i, regChainOffset, regOffset, 480 i, regChainOffset, regOffset,
476 reg32); 481 reg32);
477 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 482 ath_print(common, ATH_DBG_EEPROM,
478 "PDADC: Chain %d | " 483 "PDADC: Chain %d | "
479 "PDADC %3d Value %3d | " 484 "PDADC %3d Value %3d | "
480 "PDADC %3d Value %3d | " 485 "PDADC %3d Value %3d | "
481 "PDADC %3d Value %3d | " 486 "PDADC %3d Value %3d | "
482 "PDADC %3d Value %3d |\n", 487 "PDADC %3d Value %3d |\n",
483 i, 4 * j, pdadcValues[4 * j], 488 i, 4 * j, pdadcValues[4 * j],
484 4 * j + 1, pdadcValues[4 * j + 1], 489 4 * j + 1, pdadcValues[4 * j + 1],
485 4 * j + 2, pdadcValues[4 * j + 2], 490 4 * j + 2, pdadcValues[4 * j + 2],
486 4 * j + 3, 491 4 * j + 3,
487 pdadcValues[4 * j + 3]); 492 pdadcValues[4 * j + 3]);
488 493
489 regOffset += 4; 494 regOffset += 4;
490 } 495 }
@@ -750,7 +755,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
750 755
751 if (AR_SREV_9280_10_OR_LATER(ah)) { 756 if (AR_SREV_9280_10_OR_LATER(ah)) {
752 for (i = 0; i < Ar5416RateSize; i++) 757 for (i = 0; i < Ar5416RateSize; i++)
753 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 758 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
754 } 759 }
755 760
756 /* OFDM power per rate */ 761 /* OFDM power per rate */
@@ -1107,6 +1112,10 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1107 1112
1108 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1113 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1109 pModal->txEndToRxOn); 1114 pModal->txEndToRxOn);
1115
1116 if (AR_SREV_9271_10(ah))
1117 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1118 pModal->txEndToRxOn);
1110 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1119 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1111 pModal->thresh62); 1120 pModal->thresh62);
1112 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1121 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
@@ -1148,20 +1157,21 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1148{ 1157{
1149#define EEP_MAP4K_SPURCHAN \ 1158#define EEP_MAP4K_SPURCHAN \
1150 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) 1159 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1160 struct ath_common *common = ath9k_hw_common(ah);
1151 1161
1152 u16 spur_val = AR_NO_SPUR; 1162 u16 spur_val = AR_NO_SPUR;
1153 1163
1154 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1164 ath_print(common, ATH_DBG_ANI,
1155 "Getting spur idx %d is2Ghz. %d val %x\n", 1165 "Getting spur idx %d is2Ghz. %d val %x\n",
1156 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1166 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1157 1167
1158 switch (ah->config.spurmode) { 1168 switch (ah->config.spurmode) {
1159 case SPUR_DISABLE: 1169 case SPUR_DISABLE:
1160 break; 1170 break;
1161 case SPUR_ENABLE_IOCTL: 1171 case SPUR_ENABLE_IOCTL:
1162 spur_val = ah->config.spurchans[i][is2GHz]; 1172 spur_val = ah->config.spurchans[i][is2GHz];
1163 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1173 ath_print(common, ATH_DBG_ANI,
1164 "Getting spur val from new loc. %d\n", spur_val); 1174 "Getting spur val from new loc. %d\n", spur_val);
1165 break; 1175 break;
1166 case SPUR_ENABLE_EEPROM: 1176 case SPUR_ENABLE_EEPROM:
1167 spur_val = EEP_MAP4K_SPURCHAN; 1177 spur_val = EEP_MAP4K_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index c20c21a79b21..839d05a1df29 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
20{ 20{
@@ -29,20 +29,22 @@ static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
29static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah) 29static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
30{ 30{
31 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 31 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
32 struct ath_common *common = ath9k_hw_common(ah);
32 u16 *eep_data; 33 u16 *eep_data;
33 int addr, eep_start_loc = AR9287_EEP_START_LOC; 34 int addr, eep_start_loc = AR9287_EEP_START_LOC;
34 eep_data = (u16 *)eep; 35 eep_data = (u16 *)eep;
35 36
36 if (!ath9k_hw_use_flash(ah)) { 37 if (!ath9k_hw_use_flash(ah)) {
37 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 38 ath_print(common, ATH_DBG_EEPROM,
38 "Reading from EEPROM, not flash\n"); 39 "Reading from EEPROM, not flash\n");
39 } 40 }
40 41
41 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); 42 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
42 addr++) { 43 addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 44 if (!ath9k_hw_nvram_read(common,
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 45 addr + eep_start_loc, eep_data)) {
45 "Unable to read eeprom region \n"); 46 ath_print(common, ATH_DBG_EEPROM,
47 "Unable to read eeprom region \n");
46 return false; 48 return false;
47 } 49 }
48 eep_data++; 50 eep_data++;
@@ -57,17 +59,18 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
57 int i, addr; 59 int i, addr;
58 bool need_swap = false; 60 bool need_swap = false;
59 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 61 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
62 struct ath_common *common = ath9k_hw_common(ah);
60 63
61 if (!ath9k_hw_use_flash(ah)) { 64 if (!ath9k_hw_use_flash(ah)) {
62 if (!ath9k_hw_nvram_read 65 if (!ath9k_hw_nvram_read(common,
63 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 66 AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
64 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 67 ath_print(common, ATH_DBG_FATAL,
65 "Reading Magic # failed\n"); 68 "Reading Magic # failed\n");
66 return false; 69 return false;
67 } 70 }
68 71
69 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 72 ath_print(common, ATH_DBG_EEPROM,
70 "Read Magic = 0x%04X\n", magic); 73 "Read Magic = 0x%04X\n", magic);
71 if (magic != AR5416_EEPROM_MAGIC) { 74 if (magic != AR5416_EEPROM_MAGIC) {
72 magic2 = swab16(magic); 75 magic2 = swab16(magic);
73 76
@@ -83,15 +86,15 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
83 eepdata++; 86 eepdata++;
84 } 87 }
85 } else { 88 } else {
86 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 89 ath_print(common, ATH_DBG_FATAL,
87 "Invalid EEPROM Magic. " 90 "Invalid EEPROM Magic. "
88 "endianness mismatch.\n"); 91 "endianness mismatch.\n");
89 return -EINVAL; 92 return -EINVAL;
90 } 93 }
91 } 94 }
92 } 95 }
93 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? 96 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
94 "True" : "False"); 97 "True" : "False");
95 98
96 if (need_swap) 99 if (need_swap)
97 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 100 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -148,9 +151,9 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
148 151
149 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 152 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
150 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 153 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
151 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 154 ath_print(common, ATH_DBG_FATAL,
152 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 155 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
153 sum, ah->eep_ops->get_eeprom_ver(ah)); 156 sum, ah->eep_ops->get_eeprom_ver(ah));
154 return -EINVAL; 157 return -EINVAL;
155 } 158 }
156 159
@@ -436,6 +439,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
436 struct ath9k_channel *chan, 439 struct ath9k_channel *chan,
437 int16_t *pTxPowerIndexOffset) 440 int16_t *pTxPowerIndexOffset)
438{ 441{
442 struct ath_common *common = ath9k_hw_common(ah);
439 struct cal_data_per_freq_ar9287 *pRawDataset; 443 struct cal_data_per_freq_ar9287 *pRawDataset;
440 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 444 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
441 u8 *pCalBChans = NULL; 445 u8 *pCalBChans = NULL;
@@ -564,24 +568,25 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
564 & 0xFF) << 24) ; 568 & 0xFF) << 24) ;
565 REG_WRITE(ah, regOffset, reg32); 569 REG_WRITE(ah, regOffset, reg32);
566 570
567 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 571 ath_print(common, ATH_DBG_EEPROM,
568 "PDADC (%d,%4x): %4.4x %8.8x\n", 572 "PDADC (%d,%4x): %4.4x "
569 i, regChainOffset, regOffset, 573 "%8.8x\n",
570 reg32); 574 i, regChainOffset, regOffset,
571 575 reg32);
572 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 576
573 "PDADC: Chain %d | " 577 ath_print(common, ATH_DBG_EEPROM,
574 "PDADC %3d Value %3d | " 578 "PDADC: Chain %d | "
575 "PDADC %3d Value %3d | " 579 "PDADC %3d Value %3d | "
576 "PDADC %3d Value %3d | " 580 "PDADC %3d Value %3d | "
577 "PDADC %3d Value %3d |\n", 581 "PDADC %3d Value %3d | "
578 i, 4 * j, pdadcValues[4 * j], 582 "PDADC %3d Value %3d |\n",
579 4 * j + 1, 583 i, 4 * j, pdadcValues[4 * j],
580 pdadcValues[4 * j + 1], 584 4 * j + 1,
581 4 * j + 2, 585 pdadcValues[4 * j + 1],
582 pdadcValues[4 * j + 2], 586 4 * j + 2,
583 4 * j + 3, 587 pdadcValues[4 * j + 2],
584 pdadcValues[4 * j + 3]); 588 4 * j + 3,
589 pdadcValues[4 * j + 3]);
585 590
586 regOffset += 4; 591 regOffset += 4;
587 } 592 }
@@ -831,6 +836,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
831{ 836{
832#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 837#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
833#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 838#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
839 struct ath_common *common = ath9k_hw_common(ah);
834 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 840 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
835 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 841 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
836 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 842 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
@@ -966,8 +972,8 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
966 INCREASE_MAXPOW_BY_THREE_CHAIN; 972 INCREASE_MAXPOW_BY_THREE_CHAIN;
967 break; 973 break;
968 default: 974 default:
969 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 975 ath_print(common, ATH_DBG_EEPROM,
970 "Invalid chainmask configuration\n"); 976 "Invalid chainmask configuration\n");
971 break; 977 break;
972 } 978 }
973} 979}
@@ -1138,19 +1144,20 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1138{ 1144{
1139#define EEP_MAP9287_SPURCHAN \ 1145#define EEP_MAP9287_SPURCHAN \
1140 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 1146 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1147 struct ath_common *common = ath9k_hw_common(ah);
1141 u16 spur_val = AR_NO_SPUR; 1148 u16 spur_val = AR_NO_SPUR;
1142 1149
1143 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1150 ath_print(common, ATH_DBG_ANI,
1144 "Getting spur idx %d is2Ghz. %d val %x\n", 1151 "Getting spur idx %d is2Ghz. %d val %x\n",
1145 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1152 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1146 1153
1147 switch (ah->config.spurmode) { 1154 switch (ah->config.spurmode) {
1148 case SPUR_DISABLE: 1155 case SPUR_DISABLE:
1149 break; 1156 break;
1150 case SPUR_ENABLE_IOCTL: 1157 case SPUR_ENABLE_IOCTL:
1151 spur_val = ah->config.spurchans[i][is2GHz]; 1158 spur_val = ah->config.spurchans[i][is2GHz];
1152 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1159 ath_print(common, ATH_DBG_ANI,
1153 "Getting spur val from new loc. %d\n", spur_val); 1160 "Getting spur val from new loc. %d\n", spur_val);
1154 break; 1161 break;
1155 case SPUR_ENABLE_EEPROM: 1162 case SPUR_ENABLE_EEPROM:
1156 spur_val = EEP_MAP9287_SPURCHAN; 1163 spur_val = EEP_MAP9287_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 4071fc91da0a..404a0341242c 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static void ath9k_get_txgain_index(struct ath_hw *ah, 19static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan, 20 struct ath9k_channel *chan,
@@ -89,14 +89,15 @@ static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
89static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) 89static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90{ 90{
91#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 91#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 struct ath_common *common = ath9k_hw_common(ah);
92 u16 *eep_data = (u16 *)&ah->eeprom.def; 93 u16 *eep_data = (u16 *)&ah->eeprom.def;
93 int addr, ar5416_eep_start_loc = 0x100; 94 int addr, ar5416_eep_start_loc = 0x100;
94 95
95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
97 eep_data)) { 98 eep_data)) {
98 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 99 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
99 "Unable to read eeprom region\n"); 100 "Unable to read eeprom region\n");
100 return false; 101 return false;
101 } 102 }
102 eep_data++; 103 eep_data++;
@@ -109,19 +110,20 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
109{ 110{
110 struct ar5416_eeprom_def *eep = 111 struct ar5416_eeprom_def *eep =
111 (struct ar5416_eeprom_def *) &ah->eeprom.def; 112 (struct ar5416_eeprom_def *) &ah->eeprom.def;
113 struct ath_common *common = ath9k_hw_common(ah);
112 u16 *eepdata, temp, magic, magic2; 114 u16 *eepdata, temp, magic, magic2;
113 u32 sum = 0, el; 115 u32 sum = 0, el;
114 bool need_swap = false; 116 bool need_swap = false;
115 int i, addr, size; 117 int i, addr, size;
116 118
117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n"); 120 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
119 return false; 121 return false;
120 } 122 }
121 123
122 if (!ath9k_hw_use_flash(ah)) { 124 if (!ath9k_hw_use_flash(ah)) {
123 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 125 ath_print(common, ATH_DBG_EEPROM,
124 "Read Magic = 0x%04X\n", magic); 126 "Read Magic = 0x%04X\n", magic);
125 127
126 if (magic != AR5416_EEPROM_MAGIC) { 128 if (magic != AR5416_EEPROM_MAGIC) {
127 magic2 = swab16(magic); 129 magic2 = swab16(magic);
@@ -137,16 +139,16 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
137 eepdata++; 139 eepdata++;
138 } 140 }
139 } else { 141 } else {
140 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 142 ath_print(common, ATH_DBG_FATAL,
141 "Invalid EEPROM Magic. " 143 "Invalid EEPROM Magic. "
142 "Endianness mismatch.\n"); 144 "Endianness mismatch.\n");
143 return -EINVAL; 145 return -EINVAL;
144 } 146 }
145 } 147 }
146 } 148 }
147 149
148 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 150 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
149 need_swap ? "True" : "False"); 151 need_swap ? "True" : "False");
150 152
151 if (need_swap) 153 if (need_swap)
152 el = swab16(ah->eeprom.def.baseEepHeader.length); 154 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -167,8 +169,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
167 u32 integer, j; 169 u32 integer, j;
168 u16 word; 170 u16 word;
169 171
170 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 172 ath_print(common, ATH_DBG_EEPROM,
171 "EEPROM Endianness is not native.. Changing.\n"); 173 "EEPROM Endianness is not native.. Changing.\n");
172 174
173 word = swab16(eep->baseEepHeader.length); 175 word = swab16(eep->baseEepHeader.length);
174 eep->baseEepHeader.length = word; 176 eep->baseEepHeader.length = word;
@@ -214,8 +216,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
214 216
215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 217 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 218 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 219 ath_print(common, ATH_DBG_FATAL,
218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 220 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah)); 221 sum, ah->eep_ops->get_eeprom_ver(ah));
220 return -EINVAL; 222 return -EINVAL;
221 } 223 }
@@ -289,6 +291,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
289 return pBase->frac_n_5g; 291 return pBase->frac_n_5g;
290 else 292 else
291 return 0; 293 return 0;
294 case EEP_PWR_TABLE_OFFSET:
295 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
296 return pBase->pwr_table_offset;
297 else
298 return AR5416_PWR_TABLE_OFFSET_DB;
292 default: 299 default:
293 return 0; 300 return 0;
294 } 301 }
@@ -739,6 +746,76 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
739 return; 746 return;
740} 747}
741 748
749static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
750 u16 *gb,
751 u16 numXpdGain,
752 u16 pdGainOverlap_t2,
753 int8_t pwr_table_offset,
754 int16_t *diff)
755
756{
757 u16 k;
758
759 /* Prior to writing the boundaries or the pdadc vs. power table
760 * into the chip registers the default starting point on the pdadc
761 * vs. power table needs to be checked and the curve boundaries
762 * adjusted accordingly
763 */
764 if (AR_SREV_9280_20_OR_LATER(ah)) {
765 u16 gb_limit;
766
767 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
768 /* get the difference in dB */
769 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
770 /* get the number of half dB steps */
771 *diff *= 2;
772 /* change the original gain boundary settings
773 * by the number of half dB steps
774 */
775 for (k = 0; k < numXpdGain; k++)
776 gb[k] = (u16)(gb[k] - *diff);
777 }
778 /* Because of a hardware limitation, ensure the gain boundary
779 * is not larger than (63 - overlap)
780 */
781 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
782
783 for (k = 0; k < numXpdGain; k++)
784 gb[k] = (u16)min(gb_limit, gb[k]);
785 }
786
787 return *diff;
788}
789
790static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
791 int8_t pwr_table_offset,
792 int16_t diff,
793 u8 *pdadcValues)
794{
795#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
796 u16 k;
797
798 /* If this is a board that has a pwrTableOffset that differs from
799 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
800 * pdadc vs pwr table needs to be adjusted prior to writing to the
801 * chip.
802 */
803 if (AR_SREV_9280_20_OR_LATER(ah)) {
804 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
805 /* shift the table to start at the new offset */
806 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
807 pdadcValues[k] = pdadcValues[k + diff];
808 }
809
810 /* fill the back of the table */
811 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
812 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
813 }
814 }
815 }
816#undef NUM_PDADC
817}
818
742static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 819static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
743 struct ath9k_channel *chan, 820 struct ath9k_channel *chan,
744 int16_t *pTxPowerIndexOffset) 821 int16_t *pTxPowerIndexOffset)
@@ -746,7 +823,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
746#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) 823#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
747#define SM_PDGAIN_B(x, y) \ 824#define SM_PDGAIN_B(x, y) \
748 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) 825 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
749 826 struct ath_common *common = ath9k_hw_common(ah);
750 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 827 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
751 struct cal_data_per_freq *pRawDataset; 828 struct cal_data_per_freq *pRawDataset;
752 u8 *pCalBChans = NULL; 829 u8 *pCalBChans = NULL;
@@ -754,15 +831,18 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
754 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 831 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
755 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 832 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
756 u16 numPiers, i, j; 833 u16 numPiers, i, j;
757 int16_t tMinCalPower; 834 int16_t tMinCalPower, diff = 0;
758 u16 numXpdGain, xpdMask; 835 u16 numXpdGain, xpdMask;
759 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; 836 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
760 u32 reg32, regOffset, regChainOffset; 837 u32 reg32, regOffset, regChainOffset;
761 int16_t modalIdx; 838 int16_t modalIdx;
839 int8_t pwr_table_offset;
762 840
763 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 841 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
764 xpdMask = pEepData->modalHeader[modalIdx].xpdGain; 842 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
765 843
844 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
845
766 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 846 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
767 AR5416_EEP_MINOR_VER_2) { 847 AR5416_EEP_MINOR_VER_2) {
768 pdGainOverlap_t2 = 848 pdGainOverlap_t2 =
@@ -842,6 +922,13 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
842 numXpdGain); 922 numXpdGain);
843 } 923 }
844 924
925 diff = ath9k_change_gain_boundary_setting(ah,
926 gainBoundaries,
927 numXpdGain,
928 pdGainOverlap_t2,
929 pwr_table_offset,
930 &diff);
931
845 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 932 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
846 if (OLC_FOR_AR9280_20_LATER) { 933 if (OLC_FOR_AR9280_20_LATER) {
847 REG_WRITE(ah, 934 REG_WRITE(ah,
@@ -862,6 +949,10 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
862 } 949 }
863 } 950 }
864 951
952
953 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
954 diff, pdadcValues);
955
865 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 956 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
866 for (j = 0; j < 32; j++) { 957 for (j = 0; j < 32; j++) {
867 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 958 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
@@ -870,20 +961,20 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
870 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 961 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
871 REG_WRITE(ah, regOffset, reg32); 962 REG_WRITE(ah, regOffset, reg32);
872 963
873 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 964 ath_print(common, ATH_DBG_EEPROM,
874 "PDADC (%d,%4x): %4.4x %8.8x\n", 965 "PDADC (%d,%4x): %4.4x %8.8x\n",
875 i, regChainOffset, regOffset, 966 i, regChainOffset, regOffset,
876 reg32); 967 reg32);
877 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 968 ath_print(common, ATH_DBG_EEPROM,
878 "PDADC: Chain %d | PDADC %3d " 969 "PDADC: Chain %d | PDADC %3d "
879 "Value %3d | PDADC %3d Value %3d | " 970 "Value %3d | PDADC %3d Value %3d | "
880 "PDADC %3d Value %3d | PDADC %3d " 971 "PDADC %3d Value %3d | PDADC %3d "
881 "Value %3d |\n", 972 "Value %3d |\n",
882 i, 4 * j, pdadcValues[4 * j], 973 i, 4 * j, pdadcValues[4 * j],
883 4 * j + 1, pdadcValues[4 * j + 1], 974 4 * j + 1, pdadcValues[4 * j + 1],
884 4 * j + 2, pdadcValues[4 * j + 2], 975 4 * j + 2, pdadcValues[4 * j + 2],
885 4 * j + 3, 976 4 * j + 3,
886 pdadcValues[4 * j + 3]); 977 pdadcValues[4 * j + 3]);
887 978
888 regOffset += 4; 979 regOffset += 4;
889 } 980 }
@@ -1197,8 +1288,13 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1197 } 1288 }
1198 1289
1199 if (AR_SREV_9280_10_OR_LATER(ah)) { 1290 if (AR_SREV_9280_10_OR_LATER(ah)) {
1200 for (i = 0; i < Ar5416RateSize; i++) 1291 for (i = 0; i < Ar5416RateSize; i++) {
1201 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 1292 int8_t pwr_table_offset;
1293
1294 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1295 EEP_PWR_TABLE_OFFSET);
1296 ratesArray[i] -= pwr_table_offset * 2;
1297 }
1202 } 1298 }
1203 1299
1204 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1300 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
@@ -1297,7 +1393,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1297 1393
1298 if (AR_SREV_9280_10_OR_LATER(ah)) 1394 if (AR_SREV_9280_10_OR_LATER(ah))
1299 regulatory->max_power_level = 1395 regulatory->max_power_level =
1300 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; 1396 ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
1301 else 1397 else
1302 regulatory->max_power_level = ratesArray[i]; 1398 regulatory->max_power_level = ratesArray[i];
1303 1399
@@ -1311,8 +1407,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1311 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 1407 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1312 break; 1408 break;
1313 default: 1409 default:
1314 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1410 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1315 "Invalid chainmask configuration\n"); 1411 "Invalid chainmask configuration\n");
1316 break; 1412 break;
1317 } 1413 }
1318} 1414}
@@ -1349,20 +1445,21 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1349{ 1445{
1350#define EEP_DEF_SPURCHAN \ 1446#define EEP_DEF_SPURCHAN \
1351 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 1447 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1448 struct ath_common *common = ath9k_hw_common(ah);
1352 1449
1353 u16 spur_val = AR_NO_SPUR; 1450 u16 spur_val = AR_NO_SPUR;
1354 1451
1355 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1452 ath_print(common, ATH_DBG_ANI,
1356 "Getting spur idx %d is2Ghz. %d val %x\n", 1453 "Getting spur idx %d is2Ghz. %d val %x\n",
1357 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1454 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1358 1455
1359 switch (ah->config.spurmode) { 1456 switch (ah->config.spurmode) {
1360 case SPUR_DISABLE: 1457 case SPUR_DISABLE:
1361 break; 1458 break;
1362 case SPUR_ENABLE_IOCTL: 1459 case SPUR_ENABLE_IOCTL:
1363 spur_val = ah->config.spurchans[i][is2GHz]; 1460 spur_val = ah->config.spurchans[i][is2GHz];
1364 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1461 ath_print(common, ATH_DBG_ANI,
1365 "Getting spur val from new loc. %d\n", spur_val); 1462 "Getting spur val from new loc. %d\n", spur_val);
1366 break; 1463 break;
1367 case SPUR_ENABLE_EEPROM: 1464 case SPUR_ENABLE_EEPROM:
1368 spur_val = EEP_DEF_SPURCHAN; 1465 spur_val = EEP_DEF_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
new file mode 100644
index 000000000000..deab8beb0680
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -0,0 +1,442 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19/********************************/
20/* LED functions */
21/********************************/
22
23static void ath_led_blink_work(struct work_struct *work)
24{
25 struct ath_softc *sc = container_of(work, struct ath_softc,
26 ath_led_blink_work.work);
27
28 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
29 return;
30
31 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
32 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
33 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
34 else
35 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
36 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
37
38 ieee80211_queue_delayed_work(sc->hw,
39 &sc->ath_led_blink_work,
40 (sc->sc_flags & SC_OP_LED_ON) ?
41 msecs_to_jiffies(sc->led_off_duration) :
42 msecs_to_jiffies(sc->led_on_duration));
43
44 sc->led_on_duration = sc->led_on_cnt ?
45 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
46 ATH_LED_ON_DURATION_IDLE;
47 sc->led_off_duration = sc->led_off_cnt ?
48 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
49 ATH_LED_OFF_DURATION_IDLE;
50 sc->led_on_cnt = sc->led_off_cnt = 0;
51 if (sc->sc_flags & SC_OP_LED_ON)
52 sc->sc_flags &= ~SC_OP_LED_ON;
53 else
54 sc->sc_flags |= SC_OP_LED_ON;
55}
56
57static void ath_led_brightness(struct led_classdev *led_cdev,
58 enum led_brightness brightness)
59{
60 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
61 struct ath_softc *sc = led->sc;
62
63 switch (brightness) {
64 case LED_OFF:
65 if (led->led_type == ATH_LED_ASSOC ||
66 led->led_type == ATH_LED_RADIO) {
67 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
68 (led->led_type == ATH_LED_RADIO));
69 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
70 if (led->led_type == ATH_LED_RADIO)
71 sc->sc_flags &= ~SC_OP_LED_ON;
72 } else {
73 sc->led_off_cnt++;
74 }
75 break;
76 case LED_FULL:
77 if (led->led_type == ATH_LED_ASSOC) {
78 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
79 ieee80211_queue_delayed_work(sc->hw,
80 &sc->ath_led_blink_work, 0);
81 } else if (led->led_type == ATH_LED_RADIO) {
82 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
83 sc->sc_flags |= SC_OP_LED_ON;
84 } else {
85 sc->led_on_cnt++;
86 }
87 break;
88 default:
89 break;
90 }
91}
92
93static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
94 char *trigger)
95{
96 int ret;
97
98 led->sc = sc;
99 led->led_cdev.name = led->name;
100 led->led_cdev.default_trigger = trigger;
101 led->led_cdev.brightness_set = ath_led_brightness;
102
103 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
104 if (ret)
105 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
106 "Failed to register led:%s", led->name);
107 else
108 led->registered = 1;
109 return ret;
110}
111
112static void ath_unregister_led(struct ath_led *led)
113{
114 if (led->registered) {
115 led_classdev_unregister(&led->led_cdev);
116 led->registered = 0;
117 }
118}
119
120void ath_deinit_leds(struct ath_softc *sc)
121{
122 ath_unregister_led(&sc->assoc_led);
123 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
124 ath_unregister_led(&sc->tx_led);
125 ath_unregister_led(&sc->rx_led);
126 ath_unregister_led(&sc->radio_led);
127 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
128}
129
130void ath_init_leds(struct ath_softc *sc)
131{
132 char *trigger;
133 int ret;
134
135 if (AR_SREV_9287(sc->sc_ah))
136 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
137 else
138 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
139
140 /* Configure gpio 1 for output */
141 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
142 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
143 /* LED off, active low */
144 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
145
146 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
147
148 trigger = ieee80211_get_radio_led_name(sc->hw);
149 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
150 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
151 ret = ath_register_led(sc, &sc->radio_led, trigger);
152 sc->radio_led.led_type = ATH_LED_RADIO;
153 if (ret)
154 goto fail;
155
156 trigger = ieee80211_get_assoc_led_name(sc->hw);
157 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
158 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
159 ret = ath_register_led(sc, &sc->assoc_led, trigger);
160 sc->assoc_led.led_type = ATH_LED_ASSOC;
161 if (ret)
162 goto fail;
163
164 trigger = ieee80211_get_tx_led_name(sc->hw);
165 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
166 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
167 ret = ath_register_led(sc, &sc->tx_led, trigger);
168 sc->tx_led.led_type = ATH_LED_TX;
169 if (ret)
170 goto fail;
171
172 trigger = ieee80211_get_rx_led_name(sc->hw);
173 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
174 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
175 ret = ath_register_led(sc, &sc->rx_led, trigger);
176 sc->rx_led.led_type = ATH_LED_RX;
177 if (ret)
178 goto fail;
179
180 return;
181
182fail:
183 cancel_delayed_work_sync(&sc->ath_led_blink_work);
184 ath_deinit_leds(sc);
185}
186
187/*******************/
188/* Rfkill */
189/*******************/
190
191static bool ath_is_rfkill_set(struct ath_softc *sc)
192{
193 struct ath_hw *ah = sc->sc_ah;
194
195 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
196 ah->rfkill_polarity;
197}
198
199void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
200{
201 struct ath_wiphy *aphy = hw->priv;
202 struct ath_softc *sc = aphy->sc;
203 bool blocked = !!ath_is_rfkill_set(sc);
204
205 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
206}
207
208void ath_start_rfkill_poll(struct ath_softc *sc)
209{
210 struct ath_hw *ah = sc->sc_ah;
211
212 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
213 wiphy_rfkill_start_polling(sc->hw->wiphy);
214}
215
216/******************/
217/* BTCOEX */
218/******************/
219
220/*
221 * Detects if there is any priority bt traffic
222 */
223static void ath_detect_bt_priority(struct ath_softc *sc)
224{
225 struct ath_btcoex *btcoex = &sc->btcoex;
226 struct ath_hw *ah = sc->sc_ah;
227
228 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
229 btcoex->bt_priority_cnt++;
230
231 if (time_after(jiffies, btcoex->bt_priority_time +
232 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
233 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
234 /* Detect if colocated bt started scanning */
235 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
236 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
237 "BT scan detected");
238 sc->sc_flags |= (SC_OP_BT_SCAN |
239 SC_OP_BT_PRIORITY_DETECTED);
240 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
241 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
242 "BT priority traffic detected");
243 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
244 }
245
246 btcoex->bt_priority_cnt = 0;
247 btcoex->bt_priority_time = jiffies;
248 }
249}
250
251/*
252 * Configures appropriate weight based on stomp type.
253 */
254static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
255 enum ath_stomp_type stomp_type)
256{
257 struct ath_hw *ah = sc->sc_ah;
258
259 switch (stomp_type) {
260 case ATH_BTCOEX_STOMP_ALL:
261 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
262 AR_STOMP_ALL_WLAN_WGHT);
263 break;
264 case ATH_BTCOEX_STOMP_LOW:
265 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
266 AR_STOMP_LOW_WLAN_WGHT);
267 break;
268 case ATH_BTCOEX_STOMP_NONE:
269 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
270 AR_STOMP_NONE_WLAN_WGHT);
271 break;
272 default:
273 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
274 "Invalid Stomptype\n");
275 break;
276 }
277
278 ath9k_hw_btcoex_enable(ah);
279}
280
281static void ath9k_gen_timer_start(struct ath_hw *ah,
282 struct ath_gen_timer *timer,
283 u32 timer_next,
284 u32 timer_period)
285{
286 struct ath_common *common = ath9k_hw_common(ah);
287 struct ath_softc *sc = (struct ath_softc *) common->priv;
288
289 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
290
291 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
292 ath9k_hw_set_interrupts(ah, 0);
293 sc->imask |= ATH9K_INT_GENTIMER;
294 ath9k_hw_set_interrupts(ah, sc->imask);
295 }
296}
297
298static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
299{
300 struct ath_common *common = ath9k_hw_common(ah);
301 struct ath_softc *sc = (struct ath_softc *) common->priv;
302 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
303
304 ath9k_hw_gen_timer_stop(ah, timer);
305
306 /* if no timer is enabled, turn off interrupt mask */
307 if (timer_table->timer_mask.val == 0) {
308 ath9k_hw_set_interrupts(ah, 0);
309 sc->imask &= ~ATH9K_INT_GENTIMER;
310 ath9k_hw_set_interrupts(ah, sc->imask);
311 }
312}
313
314/*
315 * This is the master bt coex timer which runs for every
316 * 45ms, bt traffic will be given priority during 55% of this
317 * period while wlan gets remaining 45%
318 */
319static void ath_btcoex_period_timer(unsigned long data)
320{
321 struct ath_softc *sc = (struct ath_softc *) data;
322 struct ath_hw *ah = sc->sc_ah;
323 struct ath_btcoex *btcoex = &sc->btcoex;
324 u32 timer_period;
325 bool is_btscan;
326
327 ath_detect_bt_priority(sc);
328
329 is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
330
331 spin_lock_bh(&btcoex->btcoex_lock);
332
333 ath9k_btcoex_bt_stomp(sc, is_btscan ? ATH_BTCOEX_STOMP_ALL :
334 btcoex->bt_stomp_type);
335
336 spin_unlock_bh(&btcoex->btcoex_lock);
337
338 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
339 if (btcoex->hw_timer_enabled)
340 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
341
342 timer_period = is_btscan ? btcoex->btscan_no_stomp :
343 btcoex->btcoex_no_stomp;
344 ath9k_gen_timer_start(ah,
345 btcoex->no_stomp_timer,
346 (ath9k_hw_gettsf32(ah) +
347 timer_period), timer_period * 10);
348 btcoex->hw_timer_enabled = true;
349 }
350
351 mod_timer(&btcoex->period_timer, jiffies +
352 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
353}
354
355/*
356 * Generic tsf based hw timer which configures weight
357 * registers to time slice between wlan and bt traffic
358 */
359static void ath_btcoex_no_stomp_timer(void *arg)
360{
361 struct ath_softc *sc = (struct ath_softc *)arg;
362 struct ath_hw *ah = sc->sc_ah;
363 struct ath_btcoex *btcoex = &sc->btcoex;
364 bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
365
366 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
367 "no stomp timer running \n");
368
369 spin_lock_bh(&btcoex->btcoex_lock);
370
371 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
372 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
373 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
374 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
375
376 spin_unlock_bh(&btcoex->btcoex_lock);
377}
378
379int ath_init_btcoex_timer(struct ath_softc *sc)
380{
381 struct ath_btcoex *btcoex = &sc->btcoex;
382
383 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
384 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
385 btcoex->btcoex_period / 100;
386 btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
387 btcoex->btcoex_period / 100;
388
389 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
390 (unsigned long) sc);
391
392 spin_lock_init(&btcoex->btcoex_lock);
393
394 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
395 ath_btcoex_no_stomp_timer,
396 ath_btcoex_no_stomp_timer,
397 (void *) sc, AR_FIRST_NDP_TIMER);
398
399 if (!btcoex->no_stomp_timer)
400 return -ENOMEM;
401
402 return 0;
403}
404
405/*
406 * (Re)start btcoex timers
407 */
408void ath9k_btcoex_timer_resume(struct ath_softc *sc)
409{
410 struct ath_btcoex *btcoex = &sc->btcoex;
411 struct ath_hw *ah = sc->sc_ah;
412
413 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
414 "Starting btcoex timers");
415
416 /* make sure duty cycle timer is also stopped when resuming */
417 if (btcoex->hw_timer_enabled)
418 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
419
420 btcoex->bt_priority_cnt = 0;
421 btcoex->bt_priority_time = jiffies;
422 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
423
424 mod_timer(&btcoex->period_timer, jiffies);
425}
426
427
428/*
429 * Pause btcoex timer and bt duty cycle timer
430 */
431void ath9k_btcoex_timer_pause(struct ath_softc *sc)
432{
433 struct ath_btcoex *btcoex = &sc->btcoex;
434 struct ath_hw *ah = sc->sc_ah;
435
436 del_timer_sync(&btcoex->period_timer);
437
438 if (btcoex->hw_timer_enabled)
439 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
440
441 btcoex->hw_timer_enabled = false;
442}
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index ca7694caf364..78b571129c92 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -15,10 +15,11 @@
15 */ 15 */
16 16
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/slab.h>
18#include <asm/unaligned.h> 19#include <asm/unaligned.h>
19#include <linux/pci.h>
20 20
21#include "ath9k.h" 21#include "hw.h"
22#include "rc.h"
22#include "initvals.h" 23#include "initvals.h"
23 24
24#define ATH9K_CLOCK_RATE_CCK 22 25#define ATH9K_CLOCK_RATE_CCK 22
@@ -26,43 +27,35 @@
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27 28
28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 30static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 enum ath9k_ht_macmode macmode);
31static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 31static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
32 struct ar5416_eeprom_def *pEepData, 32 struct ar5416_eeprom_def *pEepData,
33 u32 reg, u32 value); 33 u32 reg, u32 value);
34static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
36 34
37/********************/ 35MODULE_AUTHOR("Atheros Communications");
38/* Helper Functions */ 36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
39/********************/ 37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
40 39
41static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) 40static int __init ath9k_init(void)
42{ 41{
43 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 42 return 0;
44
45 if (!ah->curchan) /* should really check for CCK instead */
46 return clks / ATH9K_CLOCK_RATE_CCK;
47 if (conf->channel->band == IEEE80211_BAND_2GHZ)
48 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
49
50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
51} 43}
44module_init(ath9k_init);
52 45
53static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) 46static void __exit ath9k_exit(void)
54{ 47{
55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 48 return;
56
57 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else
60 return ath9k_hw_mac_usec(ah, clks);
61} 49}
50module_exit(ath9k_exit);
51
52/********************/
53/* Helper Functions */
54/********************/
62 55
63static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 56static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
64{ 57{
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 58 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
66 59
67 if (!ah->curchan) /* should really check for CCK instead */ 60 if (!ah->curchan) /* should really check for CCK instead */
68 return usecs *ATH9K_CLOCK_RATE_CCK; 61 return usecs *ATH9K_CLOCK_RATE_CCK;
@@ -73,7 +66,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
73 66
74static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 67static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
75{ 68{
76 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 69 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
77 70
78 if (conf_is_ht40(conf)) 71 if (conf_is_ht40(conf))
79 return ath9k_hw_mac_clks(ah, usecs) * 2; 72 return ath9k_hw_mac_clks(ah, usecs) * 2;
@@ -81,38 +74,6 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
81 return ath9k_hw_mac_clks(ah, usecs); 74 return ath9k_hw_mac_clks(ah, usecs);
82} 75}
83 76
84/*
85 * Read and write, they both share the same lock. We do this to serialize
86 * reads and writes on Atheros 802.11n PCI devices only. This is required
87 * as the FIFO on these devices can only accept sanely 2 requests. After
88 * that the device goes bananas. Serializing the reads/writes prevents this
89 * from happening.
90 */
91
92void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
93{
94 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
95 unsigned long flags;
96 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
97 iowrite32(val, ah->ah_sc->mem + reg_offset);
98 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
99 } else
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101}
102
103unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
104{
105 u32 val;
106 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
107 unsigned long flags;
108 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
109 val = ioread32(ah->ah_sc->mem + reg_offset);
110 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
111 } else
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 return val;
114}
115
116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
117{ 78{
118 int i; 79 int i;
@@ -126,12 +87,13 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
126 udelay(AH_TIME_QUANTUM); 87 udelay(AH_TIME_QUANTUM);
127 } 88 }
128 89
129 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 90 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val); 92 timeout, reg, REG_READ(ah, reg), mask, val);
132 93
133 return false; 94 return false;
134} 95}
96EXPORT_SYMBOL(ath9k_hw_wait);
135 97
136u32 ath9k_hw_reverse_bits(u32 val, u32 n) 98u32 ath9k_hw_reverse_bits(u32 val, u32 n)
137{ 99{
@@ -165,22 +127,19 @@ bool ath9k_get_channel_edges(struct ath_hw *ah,
165} 127}
166 128
167u16 ath9k_hw_computetxtime(struct ath_hw *ah, 129u16 ath9k_hw_computetxtime(struct ath_hw *ah,
168 const struct ath_rate_table *rates, 130 u8 phy, int kbps,
169 u32 frameLen, u16 rateix, 131 u32 frameLen, u16 rateix,
170 bool shortPreamble) 132 bool shortPreamble)
171{ 133{
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 134 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
173 u32 kbps;
174
175 kbps = rates->info[rateix].ratekbps;
176 135
177 if (kbps == 0) 136 if (kbps == 0)
178 return 0; 137 return 0;
179 138
180 switch (rates->info[rateix].phy) { 139 switch (phy) {
181 case WLAN_RC_PHY_CCK: 140 case WLAN_RC_PHY_CCK:
182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 141 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
183 if (shortPreamble && rates->info[rateix].short_preamble) 142 if (shortPreamble)
184 phyTime >>= 1; 143 phyTime >>= 1;
185 numBits = frameLen << 3; 144 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 145 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
@@ -210,15 +169,15 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
210 } 169 }
211 break; 170 break;
212 default: 171 default:
213 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 172 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
214 "Unknown phy %u (rate ix %u)\n", 173 "Unknown phy %u (rate ix %u)\n", phy, rateix);
215 rates->info[rateix].phy, rateix);
216 txTime = 0; 174 txTime = 0;
217 break; 175 break;
218 } 176 }
219 177
220 return txTime; 178 return txTime;
221} 179}
180EXPORT_SYMBOL(ath9k_hw_computetxtime);
222 181
223void ath9k_hw_get_channel_centers(struct ath_hw *ah, 182void ath9k_hw_get_channel_centers(struct ath_hw *ah,
224 struct ath9k_channel *chan, 183 struct ath9k_channel *chan,
@@ -245,10 +204,9 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
245 204
246 centers->ctl_center = 205 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 206 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
207 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center = 208 centers->ext_center =
249 centers->synth_center + (extoff * 209 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
250 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
251 HT40_CHANNEL_CENTER_SHIFT : 15));
252} 210}
253 211
254/******************/ 212/******************/
@@ -317,6 +275,7 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
317 275
318static bool ath9k_hw_chip_test(struct ath_hw *ah) 276static bool ath9k_hw_chip_test(struct ath_hw *ah)
319{ 277{
278 struct ath_common *common = ath9k_hw_common(ah);
320 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 279 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
321 u32 regHold[2]; 280 u32 regHold[2];
322 u32 patternData[4] = { 0x55555555, 281 u32 patternData[4] = { 0x55555555,
@@ -335,10 +294,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
335 REG_WRITE(ah, addr, wrData); 294 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr); 295 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) { 296 if (rdData != wrData) {
338 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 297 ath_print(common, ATH_DBG_FATAL,
339 "address test failed " 298 "address test failed "
340 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 299 "addr: 0x%08x - wr:0x%08x != "
341 addr, wrData, rdData); 300 "rd:0x%08x\n",
301 addr, wrData, rdData);
342 return false; 302 return false;
343 } 303 }
344 } 304 }
@@ -347,10 +307,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
347 REG_WRITE(ah, addr, wrData); 307 REG_WRITE(ah, addr, wrData);
348 rdData = REG_READ(ah, addr); 308 rdData = REG_READ(ah, addr);
349 if (wrData != rdData) { 309 if (wrData != rdData) {
350 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 310 ath_print(common, ATH_DBG_FATAL,
351 "address test failed " 311 "address test failed "
352 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 312 "addr: 0x%08x - wr:0x%08x != "
353 addr, wrData, rdData); 313 "rd:0x%08x\n",
314 addr, wrData, rdData);
354 return false; 315 return false;
355 } 316 }
356 } 317 }
@@ -361,30 +322,6 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
361 return true; 322 return true;
362} 323}
363 324
364static const char *ath9k_hw_devname(u16 devid)
365{
366 switch (devid) {
367 case AR5416_DEVID_PCI:
368 return "Atheros 5416";
369 case AR5416_DEVID_PCIE:
370 return "Atheros 5418";
371 case AR9160_DEVID_PCI:
372 return "Atheros 9160";
373 case AR5416_AR9100_DEVID:
374 return "Atheros 9100";
375 case AR9280_DEVID_PCI:
376 case AR9280_DEVID_PCIE:
377 return "Atheros 9280";
378 case AR9285_DEVID_PCIE:
379 return "Atheros 9285";
380 case AR5416_DEVID_AR9287_PCI:
381 case AR5416_DEVID_AR9287_PCIE:
382 return "Atheros 9287";
383 }
384
385 return NULL;
386}
387
388static void ath9k_hw_init_config(struct ath_hw *ah) 325static void ath9k_hw_init_config(struct ath_hw *ah)
389{ 326{
390 int i; 327 int i;
@@ -398,21 +335,23 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
398 ah->config.pcie_clock_req = 0; 335 ah->config.pcie_clock_req = 0;
399 ah->config.pcie_waen = 0; 336 ah->config.pcie_waen = 0;
400 ah->config.analog_shiftreg = 1; 337 ah->config.analog_shiftreg = 1;
401 ah->config.ht_enable = 1;
402 ah->config.ofdm_trig_low = 200; 338 ah->config.ofdm_trig_low = 200;
403 ah->config.ofdm_trig_high = 500; 339 ah->config.ofdm_trig_high = 500;
404 ah->config.cck_trig_high = 200; 340 ah->config.cck_trig_high = 200;
405 ah->config.cck_trig_low = 100; 341 ah->config.cck_trig_low = 100;
406 ah->config.enable_ani = 1; 342 ah->config.enable_ani = 1;
407 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
408 ah->config.antenna_switch_swap = 0;
409 343
410 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 344 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
411 ah->config.spurchans[i][0] = AR_NO_SPUR; 345 ah->config.spurchans[i][0] = AR_NO_SPUR;
412 ah->config.spurchans[i][1] = AR_NO_SPUR; 346 ah->config.spurchans[i][1] = AR_NO_SPUR;
413 } 347 }
414 348
415 ah->config.intr_mitigation = true; 349 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
350 ah->config.ht_enable = 1;
351 else
352 ah->config.ht_enable = 0;
353
354 ah->config.rx_intr_mitigation = true;
416 355
417 /* 356 /*
418 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 357 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
@@ -433,6 +372,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
433 if (num_possible_cpus() > 1) 372 if (num_possible_cpus() > 1)
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 373 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
435} 374}
375EXPORT_SYMBOL(ath9k_hw_init);
436 376
437static void ath9k_hw_init_defaults(struct ath_hw *ah) 377static void ath9k_hw_init_defaults(struct ath_hw *ah)
438{ 378{
@@ -456,30 +396,10 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
456 ah->beacon_interval = 100; 396 ah->beacon_interval = 100;
457 ah->enable_32kHz_clock = DONT_USE_32KHZ; 397 ah->enable_32kHz_clock = DONT_USE_32KHZ;
458 ah->slottime = (u32) -1; 398 ah->slottime = (u32) -1;
459 ah->acktimeout = (u32) -1;
460 ah->ctstimeout = (u32) -1;
461 ah->globaltxtimeout = (u32) -1; 399 ah->globaltxtimeout = (u32) -1;
462
463 ah->gbeacon_rate = 0;
464
465 ah->power_mode = ATH9K_PM_UNDEFINED; 400 ah->power_mode = ATH9K_PM_UNDEFINED;
466} 401}
467 402
468static int ath9k_hw_rfattach(struct ath_hw *ah)
469{
470 bool rfStatus = false;
471 int ecode = 0;
472
473 rfStatus = ath9k_hw_init_rf(ah, &ecode);
474 if (!rfStatus) {
475 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
476 "RF setup failed, status: %u\n", ecode);
477 return ecode;
478 }
479
480 return 0;
481}
482
483static int ath9k_hw_rf_claim(struct ath_hw *ah) 403static int ath9k_hw_rf_claim(struct ath_hw *ah)
484{ 404{
485 u32 val; 405 u32 val;
@@ -497,9 +417,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
497 case AR_RAD2122_SREV_MAJOR: 417 case AR_RAD2122_SREV_MAJOR:
498 break; 418 break;
499 default: 419 default:
500 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 420 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
501 "Radio Chip Rev 0x%02X not supported\n", 421 "Radio Chip Rev 0x%02X not supported\n",
502 val & AR_RADIO_SREV_MAJOR); 422 val & AR_RADIO_SREV_MAJOR);
503 return -EOPNOTSUPP; 423 return -EOPNOTSUPP;
504 } 424 }
505 425
@@ -510,6 +430,7 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
510 430
511static int ath9k_hw_init_macaddr(struct ath_hw *ah) 431static int ath9k_hw_init_macaddr(struct ath_hw *ah)
512{ 432{
433 struct ath_common *common = ath9k_hw_common(ah);
513 u32 sum; 434 u32 sum;
514 int i; 435 int i;
515 u16 eeval; 436 u16 eeval;
@@ -518,8 +439,8 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
518 for (i = 0; i < 3; i++) { 439 for (i = 0; i < 3; i++) {
519 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 440 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
520 sum += eeval; 441 sum += eeval;
521 ah->macaddr[2 * i] = eeval >> 8; 442 common->macaddr[2 * i] = eeval >> 8;
522 ah->macaddr[2 * i + 1] = eeval & 0xff; 443 common->macaddr[2 * i + 1] = eeval & 0xff;
523 } 444 }
524 if (sum == 0 || sum == 0xffff * 3) 445 if (sum == 0 || sum == 0xffff * 3)
525 return -EADDRNOTAVAIL; 446 return -EADDRNOTAVAIL;
@@ -590,12 +511,20 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
590 if (ecode != 0) 511 if (ecode != 0)
591 return ecode; 512 return ecode;
592 513
593 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n", 514 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); 515 "Eeprom VER: %d, REV: %d\n",
595 516 ah->eep_ops->get_eeprom_ver(ah),
596 ecode = ath9k_hw_rfattach(ah); 517 ah->eep_ops->get_eeprom_rev(ah));
597 if (ecode != 0) 518
598 return ecode; 519 if (!AR_SREV_9280_10_OR_LATER(ah)) {
520 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
521 if (ecode) {
522 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
523 "Failed allocating banks for "
524 "external radio\n");
525 return ecode;
526 }
527 }
599 528
600 if (!AR_SREV_9100(ah)) { 529 if (!AR_SREV_9100(ah)) {
601 ath9k_hw_ani_setup(ah); 530 ath9k_hw_ani_setup(ah);
@@ -617,6 +546,8 @@ static bool ath9k_hw_devid_supported(u16 devid)
617 case AR9285_DEVID_PCIE: 546 case AR9285_DEVID_PCIE:
618 case AR5416_DEVID_AR9287_PCI: 547 case AR5416_DEVID_AR9287_PCI:
619 case AR5416_DEVID_AR9287_PCIE: 548 case AR5416_DEVID_AR9287_PCIE:
549 case AR9271_USB:
550 case AR2427_DEVID_PCIE:
620 return true; 551 return true;
621 default: 552 default:
622 break; 553 break;
@@ -634,9 +565,8 @@ static bool ath9k_hw_macversion_supported(u32 macversion)
634 case AR_SREV_VERSION_9280: 565 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285: 566 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287: 567 case AR_SREV_VERSION_9287:
637 return true;
638 /* Not yet */
639 case AR_SREV_VERSION_9271: 568 case AR_SREV_VERSION_9271:
569 return true;
640 default: 570 default:
641 break; 571 break;
642 } 572 }
@@ -670,10 +600,13 @@ static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
670static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 600static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
671{ 601{
672 if (AR_SREV_9271(ah)) { 602 if (AR_SREV_9271(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0, 603 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
674 ARRAY_SIZE(ar9271Modes_9271_1_0), 6); 604 ARRAY_SIZE(ar9271Modes_9271), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0, 605 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
676 ARRAY_SIZE(ar9271Common_9271_1_0), 2); 606 ARRAY_SIZE(ar9271Common_9271), 2);
607 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
608 ar9271Modes_9271_1_0_only,
609 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
677 return; 610 return;
678 } 611 }
679 612
@@ -880,12 +813,11 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
880 } 813 }
881} 814}
882 815
883static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah) 816static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
884{ 817{
885 u32 i, j; 818 u32 i, j;
886 819
887 if ((ah->hw_version.devid == AR9280_DEVID_PCI) && 820 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
888 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
889 821
890 /* EEPROM Fixup */ 822 /* EEPROM Fixup */
891 for (i = 0; i < ah->iniModes.ia_rows; i++) { 823 for (i = 0; i < ah->iniModes.ia_rows; i++) {
@@ -905,21 +837,27 @@ static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
905 837
906int ath9k_hw_init(struct ath_hw *ah) 838int ath9k_hw_init(struct ath_hw *ah)
907{ 839{
840 struct ath_common *common = ath9k_hw_common(ah);
908 int r = 0; 841 int r = 0;
909 842
910 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) 843 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
844 ath_print(common, ATH_DBG_FATAL,
845 "Unsupported device ID: 0x%0x\n",
846 ah->hw_version.devid);
911 return -EOPNOTSUPP; 847 return -EOPNOTSUPP;
848 }
912 849
913 ath9k_hw_init_defaults(ah); 850 ath9k_hw_init_defaults(ah);
914 ath9k_hw_init_config(ah); 851 ath9k_hw_init_config(ah);
915 852
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 853 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
917 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n"); 854 ath_print(common, ATH_DBG_FATAL,
855 "Couldn't reset chip\n");
918 return -EIO; 856 return -EIO;
919 } 857 }
920 858
921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 859 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 860 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
923 return -EIO; 861 return -EIO;
924 } 862 }
925 863
@@ -934,14 +872,19 @@ int ath9k_hw_init(struct ath_hw *ah)
934 } 872 }
935 } 873 }
936 874
937 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n", 875 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
938 ah->config.serialize_regmode); 876 ah->config.serialize_regmode);
939 877
878 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
879 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
880 else
881 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
882
940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 883 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
941 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 884 ath_print(common, ATH_DBG_FATAL,
942 "Mac Chip Rev 0x%02x.%x is not supported by " 885 "Mac Chip Rev 0x%02x.%x is not supported by "
943 "this driver\n", ah->hw_version.macVersion, 886 "this driver\n", ah->hw_version.macVersion,
944 ah->hw_version.macRev); 887 ah->hw_version.macRev);
945 return -EOPNOTSUPP; 888 return -EOPNOTSUPP;
946 } 889 }
947 890
@@ -959,8 +902,14 @@ int ath9k_hw_init(struct ath_hw *ah)
959 ath9k_hw_init_cal_settings(ah); 902 ath9k_hw_init_cal_settings(ah);
960 903
961 ah->ani_function = ATH9K_ANI_ALL; 904 ah->ani_function = ATH9K_ANI_ALL;
962 if (AR_SREV_9280_10_OR_LATER(ah)) 905 if (AR_SREV_9280_10_OR_LATER(ah)) {
963 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 906 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
907 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
908 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
909 } else {
910 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
911 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
912 }
964 913
965 ath9k_hw_init_mode_regs(ah); 914 ath9k_hw_init_mode_regs(ah);
966 915
@@ -969,18 +918,31 @@ int ath9k_hw_init(struct ath_hw *ah)
969 else 918 else
970 ath9k_hw_disablepcie(ah); 919 ath9k_hw_disablepcie(ah);
971 920
921 /* Support for Japan ch.14 (2484) spread */
922 if (AR_SREV_9287_11_OR_LATER(ah)) {
923 INIT_INI_ARRAY(&ah->iniCckfirNormal,
924 ar9287Common_normal_cck_fir_coeff_92871_1,
925 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
926 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
927 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
928 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
929 }
930
972 r = ath9k_hw_post_init(ah); 931 r = ath9k_hw_post_init(ah);
973 if (r) 932 if (r)
974 return r; 933 return r;
975 934
976 ath9k_hw_init_mode_gain_regs(ah); 935 ath9k_hw_init_mode_gain_regs(ah);
977 ath9k_hw_fill_cap_info(ah); 936 r = ath9k_hw_fill_cap_info(ah);
978 ath9k_hw_init_11a_eeprom_fix(ah); 937 if (r)
938 return r;
939
940 ath9k_hw_init_eeprom_fix(ah);
979 941
980 r = ath9k_hw_init_macaddr(ah); 942 r = ath9k_hw_init_macaddr(ah);
981 if (r) { 943 if (r) {
982 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 944 ath_print(common, ATH_DBG_FATAL,
983 "Failed to initialize MAC address\n"); 945 "Failed to initialize MAC address\n");
984 return r; 946 return r;
985 } 947 }
986 948
@@ -991,6 +953,8 @@ int ath9k_hw_init(struct ath_hw *ah)
991 953
992 ath9k_init_nfcal_hist_buffer(ah); 954 ath9k_init_nfcal_hist_buffer(ah);
993 955
956 common->state = ATH_HW_INITIALIZED;
957
994 return 0; 958 return 0;
995} 959}
996 960
@@ -1027,6 +991,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
1027 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 991 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1028} 992}
1029 993
994static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
995{
996 u32 lcr;
997 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
998
999 lcr = REG_READ(ah , 0x5100c);
1000 lcr |= 0x80;
1001
1002 REG_WRITE(ah, 0x5100c, lcr);
1003 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1004 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1005
1006 lcr &= ~0x80;
1007 REG_WRITE(ah, 0x5100c, lcr);
1008}
1009
1030static void ath9k_hw_init_pll(struct ath_hw *ah, 1010static void ath9k_hw_init_pll(struct ath_hw *ah,
1031 struct ath9k_channel *chan) 1011 struct ath9k_channel *chan)
1032{ 1012{
@@ -1090,6 +1070,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1090 } 1070 }
1091 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1071 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1092 1072
1073 /* Switch the core clock for ar9271 to 117Mhz */
1074 if (AR_SREV_9271(ah)) {
1075 if ((pll == 0x142c) || (pll == 0x2850) ) {
1076 udelay(500);
1077 /* set CLKOBS to output AHB clock */
1078 REG_WRITE(ah, 0x7020, 0xe);
1079 /*
1080 * 0x304: 117Mhz, ahb_ratio: 1x1
1081 * 0x306: 40Mhz, ahb_ratio: 1x1
1082 */
1083 REG_WRITE(ah, 0x50040, 0x304);
1084 /*
1085 * makes adjustments for the baud dividor to keep the
1086 * targetted baud rate based on the used core clock.
1087 */
1088 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1089 AR9271_TARGET_BAUD_RATE);
1090 }
1091 }
1092
1093 udelay(RTC_PLL_SETTLE_DELAY); 1093 udelay(RTC_PLL_SETTLE_DELAY);
1094 1094
1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
@@ -1107,7 +1107,7 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108 AR_PHY_SWAP_ALT_CHAIN); 1108 AR_PHY_SWAP_ALT_CHAIN);
1109 case 0x3: 1109 case 0x3:
1110 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) { 1110 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113 break; 1113 break;
@@ -1141,7 +1141,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1141 AR_IMR_RXORN | 1141 AR_IMR_RXORN |
1142 AR_IMR_BCNMISC; 1142 AR_IMR_BCNMISC;
1143 1143
1144 if (ah->config.intr_mitigation) 1144 if (ah->config.rx_intr_mitigation)
1145 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1145 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1146 else 1146 else
1147 ah->mask_reg |= AR_IMR_RXOK; 1147 ah->mask_reg |= AR_IMR_RXOK;
@@ -1161,39 +1161,32 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1161 } 1161 }
1162} 1162}
1163 1163
1164static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1164static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1165{ 1165{
1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1166 u32 val = ath9k_hw_mac_to_clks(ah, us);
1167 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1167 val = min(val, (u32) 0xFFFF);
1168 ah->acktimeout = (u32) -1; 1168 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1169 return false;
1170 } else {
1171 REG_RMW_FIELD(ah, AR_TIME_OUT,
1172 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1173 ah->acktimeout = us;
1174 return true;
1175 }
1176} 1169}
1177 1170
1178static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1171static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1179{ 1172{
1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1173 u32 val = ath9k_hw_mac_to_clks(ah, us);
1181 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1174 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1182 ah->ctstimeout = (u32) -1; 1175 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1183 return false; 1176}
1184 } else { 1177
1185 REG_RMW_FIELD(ah, AR_TIME_OUT, 1178static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1186 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1179{
1187 ah->ctstimeout = us; 1180 u32 val = ath9k_hw_mac_to_clks(ah, us);
1188 return true; 1181 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1189 } 1182 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1190} 1183}
1191 1184
1192static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1185static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1193{ 1186{
1194 if (tu > 0xFFFF) { 1187 if (tu > 0xFFFF) {
1195 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1188 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1196 "bad global tx timeout %u\n", tu); 1189 "bad global tx timeout %u\n", tu);
1197 ah->globaltxtimeout = (u32) -1; 1190 ah->globaltxtimeout = (u32) -1;
1198 return false; 1191 return false;
1199 } else { 1192 } else {
@@ -1203,40 +1196,66 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1203 } 1196 }
1204} 1197}
1205 1198
1206static void ath9k_hw_init_user_settings(struct ath_hw *ah) 1199void ath9k_hw_init_global_settings(struct ath_hw *ah)
1207{ 1200{
1208 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1201 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1209 ah->misc_mode); 1202 int acktimeout;
1203 int slottime;
1204 int sifstime;
1205
1206 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1207 ah->misc_mode);
1210 1208
1211 if (ah->misc_mode != 0) 1209 if (ah->misc_mode != 0)
1212 REG_WRITE(ah, AR_PCU_MISC, 1210 REG_WRITE(ah, AR_PCU_MISC,
1213 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 1211 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1214 if (ah->slottime != (u32) -1) 1212
1215 ath9k_hw_setslottime(ah, ah->slottime); 1213 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1216 if (ah->acktimeout != (u32) -1) 1214 sifstime = 16;
1217 ath9k_hw_set_ack_timeout(ah, ah->acktimeout); 1215 else
1218 if (ah->ctstimeout != (u32) -1) 1216 sifstime = 10;
1219 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout); 1217
1218 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1219 slottime = ah->slottime + 3 * ah->coverage_class;
1220 acktimeout = slottime + sifstime;
1221
1222 /*
1223 * Workaround for early ACK timeouts, add an offset to match the
1224 * initval's 64us ack timeout value.
1225 * This was initially only meant to work around an issue with delayed
1226 * BA frames in some implementations, but it has been found to fix ACK
1227 * timeout issues in other cases as well.
1228 */
1229 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1230 acktimeout += 64 - sifstime - ah->slottime;
1231
1232 ath9k_hw_setslottime(ah, slottime);
1233 ath9k_hw_set_ack_timeout(ah, acktimeout);
1234 ath9k_hw_set_cts_timeout(ah, acktimeout);
1220 if (ah->globaltxtimeout != (u32) -1) 1235 if (ah->globaltxtimeout != (u32) -1)
1221 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1236 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1222} 1237}
1238EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1223 1239
1224const char *ath9k_hw_probe(u16 vendorid, u16 devid) 1240void ath9k_hw_deinit(struct ath_hw *ah)
1225{ 1241{
1226 return vendorid == ATHEROS_VENDOR_ID ? 1242 struct ath_common *common = ath9k_hw_common(ah);
1227 ath9k_hw_devname(devid) : NULL; 1243
1228} 1244 if (common->state <= ATH_HW_INITIALIZED)
1245 goto free_hw;
1229 1246
1230void ath9k_hw_detach(struct ath_hw *ah)
1231{
1232 if (!AR_SREV_9100(ah)) 1247 if (!AR_SREV_9100(ah))
1233 ath9k_hw_ani_disable(ah); 1248 ath9k_hw_ani_disable(ah);
1234 1249
1235 ath9k_hw_rf_free(ah);
1236 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1250 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1251
1252free_hw:
1253 if (!AR_SREV_9280_10_OR_LATER(ah))
1254 ath9k_hw_rf_free_ext_banks(ah);
1237 kfree(ah); 1255 kfree(ah);
1238 ah = NULL; 1256 ah = NULL;
1239} 1257}
1258EXPORT_SYMBOL(ath9k_hw_deinit);
1240 1259
1241/*******/ 1260/*******/
1242/* INI */ 1261/* INI */
@@ -1254,7 +1273,8 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
1254 * AR9271 1.1 1273 * AR9271 1.1
1255 */ 1274 */
1256 if (AR_SREV_9271_10(ah)) { 1275 if (AR_SREV_9271_10(ah)) {
1257 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE; 1276 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1277 AR_PHY_SPECTRAL_SCAN_ENABLE;
1258 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); 1278 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1259 } 1279 }
1260 else if (AR_SREV_9271_11(ah)) 1280 else if (AR_SREV_9271_11(ah))
@@ -1291,6 +1311,16 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
1291 * Necessary to avoid issues on AR5416 2.0 1311 * Necessary to avoid issues on AR5416 2.0
1292 */ 1312 */
1293 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1313 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1314
1315 /*
1316 * Disable RIFS search on some chips to avoid baseband
1317 * hang issues.
1318 */
1319 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1320 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1321 val &= ~AR_PHY_RIFS_INIT_DELAY;
1322 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1323 }
1294} 1324}
1295 1325
1296static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, 1326static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
@@ -1298,28 +1328,29 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1298 u32 reg, u32 value) 1328 u32 reg, u32 value)
1299{ 1329{
1300 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1330 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1331 struct ath_common *common = ath9k_hw_common(ah);
1301 1332
1302 switch (ah->hw_version.devid) { 1333 switch (ah->hw_version.devid) {
1303 case AR9280_DEVID_PCI: 1334 case AR9280_DEVID_PCI:
1304 if (reg == 0x7894) { 1335 if (reg == 0x7894) {
1305 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1336 ath_print(common, ATH_DBG_EEPROM,
1306 "ini VAL: %x EEPROM: %x\n", value, 1337 "ini VAL: %x EEPROM: %x\n", value,
1307 (pBase->version & 0xff)); 1338 (pBase->version & 0xff));
1308 1339
1309 if ((pBase->version & 0xff) > 0x0a) { 1340 if ((pBase->version & 0xff) > 0x0a) {
1310 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1341 ath_print(common, ATH_DBG_EEPROM,
1311 "PWDCLKIND: %d\n", 1342 "PWDCLKIND: %d\n",
1312 pBase->pwdclkind); 1343 pBase->pwdclkind);
1313 value &= ~AR_AN_TOP2_PWDCLKIND; 1344 value &= ~AR_AN_TOP2_PWDCLKIND;
1314 value |= AR_AN_TOP2_PWDCLKIND & 1345 value |= AR_AN_TOP2_PWDCLKIND &
1315 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1346 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1316 } else { 1347 } else {
1317 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1348 ath_print(common, ATH_DBG_EEPROM,
1318 "PWDCLKIND Earlier Rev\n"); 1349 "PWDCLKIND Earlier Rev\n");
1319 } 1350 }
1320 1351
1321 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1352 ath_print(common, ATH_DBG_EEPROM,
1322 "final ini VAL: %x\n", value); 1353 "final ini VAL: %x\n", value);
1323 } 1354 }
1324 break; 1355 break;
1325 } 1356 }
@@ -1374,8 +1405,7 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1374} 1405}
1375 1406
1376static int ath9k_hw_process_ini(struct ath_hw *ah, 1407static int ath9k_hw_process_ini(struct ath_hw *ah,
1377 struct ath9k_channel *chan, 1408 struct ath9k_channel *chan)
1378 enum ath9k_ht_macmode macmode)
1379{ 1409{
1380 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1410 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1381 int i, regWrites = 0; 1411 int i, regWrites = 0;
@@ -1469,7 +1499,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1469 DO_DELAY(regWrites); 1499 DO_DELAY(regWrites);
1470 } 1500 }
1471 1501
1472 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1502 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1503
1504 if (AR_SREV_9271_10(ah))
1505 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1506 modesIndex, regWrites);
1473 1507
1474 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1508 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1475 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1509 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
@@ -1477,7 +1511,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1477 } 1511 }
1478 1512
1479 ath9k_hw_override_ini(ah, chan); 1513 ath9k_hw_override_ini(ah, chan);
1480 ath9k_hw_set_regs(ah, chan, macmode); 1514 ath9k_hw_set_regs(ah, chan);
1481 ath9k_hw_init_chain_masks(ah); 1515 ath9k_hw_init_chain_masks(ah);
1482 1516
1483 if (OLC_FOR_AR9280_20_LATER) 1517 if (OLC_FOR_AR9280_20_LATER)
@@ -1491,8 +1525,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1491 (u32) regulatory->power_limit)); 1525 (u32) regulatory->power_limit));
1492 1526
1493 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1527 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1494 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1528 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1495 "ar5416SetRfRegs failed\n"); 1529 "ar5416SetRfRegs failed\n");
1496 return -EIO; 1530 return -EIO;
1497 } 1531 }
1498 1532
@@ -1697,16 +1731,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1697 1731
1698 REG_WRITE(ah, AR_RTC_RC, 0); 1732 REG_WRITE(ah, AR_RTC_RC, 0);
1699 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1733 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1700 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1734 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1701 "RTC stuck in MAC reset\n"); 1735 "RTC stuck in MAC reset\n");
1702 return false; 1736 return false;
1703 } 1737 }
1704 1738
1705 if (!AR_SREV_9100(ah)) 1739 if (!AR_SREV_9100(ah))
1706 REG_WRITE(ah, AR_RC, 0); 1740 REG_WRITE(ah, AR_RC, 0);
1707 1741
1708 ath9k_hw_init_pll(ah, NULL);
1709
1710 if (AR_SREV_9100(ah)) 1742 if (AR_SREV_9100(ah))
1711 udelay(50); 1743 udelay(50);
1712 1744
@@ -1734,7 +1766,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1734 AR_RTC_STATUS_M, 1766 AR_RTC_STATUS_M,
1735 AR_RTC_STATUS_ON, 1767 AR_RTC_STATUS_ON,
1736 AH_WAIT_TIMEOUT)) { 1768 AH_WAIT_TIMEOUT)) {
1737 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n"); 1769 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1770 "RTC not waking up\n");
1738 return false; 1771 return false;
1739 } 1772 }
1740 1773
@@ -1759,8 +1792,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1759 } 1792 }
1760} 1793}
1761 1794
1762static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 1795static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1763 enum ath9k_ht_macmode macmode)
1764{ 1796{
1765 u32 phymode; 1797 u32 phymode;
1766 u32 enableDacFifo = 0; 1798 u32 enableDacFifo = 0;
@@ -1779,12 +1811,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1779 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1811 (chan->chanmode == CHANNEL_G_HT40PLUS))
1780 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1812 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1781 1813
1782 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1783 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1784 } 1814 }
1785 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1815 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1786 1816
1787 ath9k_hw_set11nmac2040(ah, macmode); 1817 ath9k_hw_set11nmac2040(ah);
1788 1818
1789 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 1819 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1790 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1820 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
@@ -1810,17 +1840,19 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1810} 1840}
1811 1841
1812static bool ath9k_hw_channel_change(struct ath_hw *ah, 1842static bool ath9k_hw_channel_change(struct ath_hw *ah,
1813 struct ath9k_channel *chan, 1843 struct ath9k_channel *chan)
1814 enum ath9k_ht_macmode macmode)
1815{ 1844{
1816 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1845 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1846 struct ath_common *common = ath9k_hw_common(ah);
1817 struct ieee80211_channel *channel = chan->chan; 1847 struct ieee80211_channel *channel = chan->chan;
1818 u32 synthDelay, qnum; 1848 u32 synthDelay, qnum;
1849 int r;
1819 1850
1820 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1851 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1821 if (ath9k_hw_numtxpending(ah, qnum)) { 1852 if (ath9k_hw_numtxpending(ah, qnum)) {
1822 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1853 ath_print(common, ATH_DBG_QUEUE,
1823 "Transmit frames pending on queue %d\n", qnum); 1854 "Transmit frames pending on "
1855 "queue %d\n", qnum);
1824 return false; 1856 return false;
1825 } 1857 }
1826 } 1858 }
@@ -1828,21 +1860,18 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1828 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1860 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1829 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1861 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1830 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1862 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1831 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1863 ath_print(common, ATH_DBG_FATAL,
1832 "Could not kill baseband RX\n"); 1864 "Could not kill baseband RX\n");
1833 return false; 1865 return false;
1834 } 1866 }
1835 1867
1836 ath9k_hw_set_regs(ah, chan, macmode); 1868 ath9k_hw_set_regs(ah, chan);
1837 1869
1838 if (AR_SREV_9280_10_OR_LATER(ah)) { 1870 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1839 ath9k_hw_ar9280_set_channel(ah, chan); 1871 if (r) {
1840 } else { 1872 ath_print(common, ATH_DBG_FATAL,
1841 if (!(ath9k_hw_set_channel(ah, chan))) { 1873 "Failed to set channel\n");
1842 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1874 return false;
1843 "Failed to set channel\n");
1844 return false;
1845 }
1846 } 1875 }
1847 1876
1848 ah->eep_ops->set_txpower(ah, chan, 1877 ah->eep_ops->set_txpower(ah, chan,
@@ -1865,10 +1894,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1865 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1894 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1866 ath9k_hw_set_delta_slope(ah, chan); 1895 ath9k_hw_set_delta_slope(ah, chan);
1867 1896
1868 if (AR_SREV_9280_10_OR_LATER(ah)) 1897 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1869 ath9k_hw_9280_spur_mitigate(ah, chan);
1870 else
1871 ath9k_hw_spur_mitigate(ah, chan);
1872 1898
1873 if (!chan->oneTimeCalsDone) 1899 if (!chan->oneTimeCalsDone)
1874 chan->oneTimeCalsDone = true; 1900 chan->oneTimeCalsDone = true;
@@ -1876,457 +1902,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1876 return true; 1902 return true;
1877} 1903}
1878 1904
1879static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1880{
1881 int bb_spur = AR_NO_SPUR;
1882 int freq;
1883 int bin, cur_bin;
1884 int bb_spur_off, spur_subchannel_sd;
1885 int spur_freq_sd;
1886 int spur_delta_phase;
1887 int denominator;
1888 int upper, lower, cur_vit_mask;
1889 int tmp, newVal;
1890 int i;
1891 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1892 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1893 };
1894 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1895 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1896 };
1897 int inc[4] = { 0, 100, 0, 0 };
1898 struct chan_centers centers;
1899
1900 int8_t mask_m[123];
1901 int8_t mask_p[123];
1902 int8_t mask_amt;
1903 int tmp_mask;
1904 int cur_bb_spur;
1905 bool is2GHz = IS_CHAN_2GHZ(chan);
1906
1907 memset(&mask_m, 0, sizeof(int8_t) * 123);
1908 memset(&mask_p, 0, sizeof(int8_t) * 123);
1909
1910 ath9k_hw_get_channel_centers(ah, chan, &centers);
1911 freq = centers.synth_center;
1912
1913 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1914 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1915 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1916
1917 if (is2GHz)
1918 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1919 else
1920 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1921
1922 if (AR_NO_SPUR == cur_bb_spur)
1923 break;
1924 cur_bb_spur = cur_bb_spur - freq;
1925
1926 if (IS_CHAN_HT40(chan)) {
1927 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1928 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1929 bb_spur = cur_bb_spur;
1930 break;
1931 }
1932 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1933 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1934 bb_spur = cur_bb_spur;
1935 break;
1936 }
1937 }
1938
1939 if (AR_NO_SPUR == bb_spur) {
1940 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1941 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1942 return;
1943 } else {
1944 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1945 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1946 }
1947
1948 bin = bb_spur * 320;
1949
1950 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1951
1952 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1953 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1954 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1955 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1956 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1957
1958 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1959 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1960 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1961 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1962 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1963 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1964
1965 if (IS_CHAN_HT40(chan)) {
1966 if (bb_spur < 0) {
1967 spur_subchannel_sd = 1;
1968 bb_spur_off = bb_spur + 10;
1969 } else {
1970 spur_subchannel_sd = 0;
1971 bb_spur_off = bb_spur - 10;
1972 }
1973 } else {
1974 spur_subchannel_sd = 0;
1975 bb_spur_off = bb_spur;
1976 }
1977
1978 if (IS_CHAN_HT40(chan))
1979 spur_delta_phase =
1980 ((bb_spur * 262144) /
1981 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1982 else
1983 spur_delta_phase =
1984 ((bb_spur * 524288) /
1985 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1986
1987 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1988 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1989
1990 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1991 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1992 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1993 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1994
1995 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1996 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1997
1998 cur_bin = -6000;
1999 upper = bin + 100;
2000 lower = bin - 100;
2001
2002 for (i = 0; i < 4; i++) {
2003 int pilot_mask = 0;
2004 int chan_mask = 0;
2005 int bp = 0;
2006 for (bp = 0; bp < 30; bp++) {
2007 if ((cur_bin > lower) && (cur_bin < upper)) {
2008 pilot_mask = pilot_mask | 0x1 << bp;
2009 chan_mask = chan_mask | 0x1 << bp;
2010 }
2011 cur_bin += 100;
2012 }
2013 cur_bin += inc[i];
2014 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2015 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2016 }
2017
2018 cur_vit_mask = 6100;
2019 upper = bin + 120;
2020 lower = bin - 120;
2021
2022 for (i = 0; i < 123; i++) {
2023 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2024
2025 /* workaround for gcc bug #37014 */
2026 volatile int tmp_v = abs(cur_vit_mask - bin);
2027
2028 if (tmp_v < 75)
2029 mask_amt = 1;
2030 else
2031 mask_amt = 0;
2032 if (cur_vit_mask < 0)
2033 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2034 else
2035 mask_p[cur_vit_mask / 100] = mask_amt;
2036 }
2037 cur_vit_mask -= 100;
2038 }
2039
2040 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2041 | (mask_m[48] << 26) | (mask_m[49] << 24)
2042 | (mask_m[50] << 22) | (mask_m[51] << 20)
2043 | (mask_m[52] << 18) | (mask_m[53] << 16)
2044 | (mask_m[54] << 14) | (mask_m[55] << 12)
2045 | (mask_m[56] << 10) | (mask_m[57] << 8)
2046 | (mask_m[58] << 6) | (mask_m[59] << 4)
2047 | (mask_m[60] << 2) | (mask_m[61] << 0);
2048 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2049 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2050
2051 tmp_mask = (mask_m[31] << 28)
2052 | (mask_m[32] << 26) | (mask_m[33] << 24)
2053 | (mask_m[34] << 22) | (mask_m[35] << 20)
2054 | (mask_m[36] << 18) | (mask_m[37] << 16)
2055 | (mask_m[48] << 14) | (mask_m[39] << 12)
2056 | (mask_m[40] << 10) | (mask_m[41] << 8)
2057 | (mask_m[42] << 6) | (mask_m[43] << 4)
2058 | (mask_m[44] << 2) | (mask_m[45] << 0);
2059 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2060 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2061
2062 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2063 | (mask_m[18] << 26) | (mask_m[18] << 24)
2064 | (mask_m[20] << 22) | (mask_m[20] << 20)
2065 | (mask_m[22] << 18) | (mask_m[22] << 16)
2066 | (mask_m[24] << 14) | (mask_m[24] << 12)
2067 | (mask_m[25] << 10) | (mask_m[26] << 8)
2068 | (mask_m[27] << 6) | (mask_m[28] << 4)
2069 | (mask_m[29] << 2) | (mask_m[30] << 0);
2070 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2071 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2072
2073 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2074 | (mask_m[2] << 26) | (mask_m[3] << 24)
2075 | (mask_m[4] << 22) | (mask_m[5] << 20)
2076 | (mask_m[6] << 18) | (mask_m[7] << 16)
2077 | (mask_m[8] << 14) | (mask_m[9] << 12)
2078 | (mask_m[10] << 10) | (mask_m[11] << 8)
2079 | (mask_m[12] << 6) | (mask_m[13] << 4)
2080 | (mask_m[14] << 2) | (mask_m[15] << 0);
2081 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2082 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2083
2084 tmp_mask = (mask_p[15] << 28)
2085 | (mask_p[14] << 26) | (mask_p[13] << 24)
2086 | (mask_p[12] << 22) | (mask_p[11] << 20)
2087 | (mask_p[10] << 18) | (mask_p[9] << 16)
2088 | (mask_p[8] << 14) | (mask_p[7] << 12)
2089 | (mask_p[6] << 10) | (mask_p[5] << 8)
2090 | (mask_p[4] << 6) | (mask_p[3] << 4)
2091 | (mask_p[2] << 2) | (mask_p[1] << 0);
2092 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2093 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2094
2095 tmp_mask = (mask_p[30] << 28)
2096 | (mask_p[29] << 26) | (mask_p[28] << 24)
2097 | (mask_p[27] << 22) | (mask_p[26] << 20)
2098 | (mask_p[25] << 18) | (mask_p[24] << 16)
2099 | (mask_p[23] << 14) | (mask_p[22] << 12)
2100 | (mask_p[21] << 10) | (mask_p[20] << 8)
2101 | (mask_p[19] << 6) | (mask_p[18] << 4)
2102 | (mask_p[17] << 2) | (mask_p[16] << 0);
2103 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2104 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2105
2106 tmp_mask = (mask_p[45] << 28)
2107 | (mask_p[44] << 26) | (mask_p[43] << 24)
2108 | (mask_p[42] << 22) | (mask_p[41] << 20)
2109 | (mask_p[40] << 18) | (mask_p[39] << 16)
2110 | (mask_p[38] << 14) | (mask_p[37] << 12)
2111 | (mask_p[36] << 10) | (mask_p[35] << 8)
2112 | (mask_p[34] << 6) | (mask_p[33] << 4)
2113 | (mask_p[32] << 2) | (mask_p[31] << 0);
2114 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2115 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2116
2117 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2118 | (mask_p[59] << 26) | (mask_p[58] << 24)
2119 | (mask_p[57] << 22) | (mask_p[56] << 20)
2120 | (mask_p[55] << 18) | (mask_p[54] << 16)
2121 | (mask_p[53] << 14) | (mask_p[52] << 12)
2122 | (mask_p[51] << 10) | (mask_p[50] << 8)
2123 | (mask_p[49] << 6) | (mask_p[48] << 4)
2124 | (mask_p[47] << 2) | (mask_p[46] << 0);
2125 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2126 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2127}
2128
2129static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2130{
2131 int bb_spur = AR_NO_SPUR;
2132 int bin, cur_bin;
2133 int spur_freq_sd;
2134 int spur_delta_phase;
2135 int denominator;
2136 int upper, lower, cur_vit_mask;
2137 int tmp, new;
2138 int i;
2139 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2140 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2141 };
2142 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2143 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2144 };
2145 int inc[4] = { 0, 100, 0, 0 };
2146
2147 int8_t mask_m[123];
2148 int8_t mask_p[123];
2149 int8_t mask_amt;
2150 int tmp_mask;
2151 int cur_bb_spur;
2152 bool is2GHz = IS_CHAN_2GHZ(chan);
2153
2154 memset(&mask_m, 0, sizeof(int8_t) * 123);
2155 memset(&mask_p, 0, sizeof(int8_t) * 123);
2156
2157 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2158 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2159 if (AR_NO_SPUR == cur_bb_spur)
2160 break;
2161 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2162 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2163 bb_spur = cur_bb_spur;
2164 break;
2165 }
2166 }
2167
2168 if (AR_NO_SPUR == bb_spur)
2169 return;
2170
2171 bin = bb_spur * 32;
2172
2173 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2174 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2175 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2176 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2177 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2178
2179 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2180
2181 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2182 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2183 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2184 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2185 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2186 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2187
2188 spur_delta_phase = ((bb_spur * 524288) / 100) &
2189 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2190
2191 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2192 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2193
2194 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2195 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2196 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2197 REG_WRITE(ah, AR_PHY_TIMING11, new);
2198
2199 cur_bin = -6000;
2200 upper = bin + 100;
2201 lower = bin - 100;
2202
2203 for (i = 0; i < 4; i++) {
2204 int pilot_mask = 0;
2205 int chan_mask = 0;
2206 int bp = 0;
2207 for (bp = 0; bp < 30; bp++) {
2208 if ((cur_bin > lower) && (cur_bin < upper)) {
2209 pilot_mask = pilot_mask | 0x1 << bp;
2210 chan_mask = chan_mask | 0x1 << bp;
2211 }
2212 cur_bin += 100;
2213 }
2214 cur_bin += inc[i];
2215 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2216 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2217 }
2218
2219 cur_vit_mask = 6100;
2220 upper = bin + 120;
2221 lower = bin - 120;
2222
2223 for (i = 0; i < 123; i++) {
2224 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2225
2226 /* workaround for gcc bug #37014 */
2227 volatile int tmp_v = abs(cur_vit_mask - bin);
2228
2229 if (tmp_v < 75)
2230 mask_amt = 1;
2231 else
2232 mask_amt = 0;
2233 if (cur_vit_mask < 0)
2234 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2235 else
2236 mask_p[cur_vit_mask / 100] = mask_amt;
2237 }
2238 cur_vit_mask -= 100;
2239 }
2240
2241 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2242 | (mask_m[48] << 26) | (mask_m[49] << 24)
2243 | (mask_m[50] << 22) | (mask_m[51] << 20)
2244 | (mask_m[52] << 18) | (mask_m[53] << 16)
2245 | (mask_m[54] << 14) | (mask_m[55] << 12)
2246 | (mask_m[56] << 10) | (mask_m[57] << 8)
2247 | (mask_m[58] << 6) | (mask_m[59] << 4)
2248 | (mask_m[60] << 2) | (mask_m[61] << 0);
2249 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2250 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2251
2252 tmp_mask = (mask_m[31] << 28)
2253 | (mask_m[32] << 26) | (mask_m[33] << 24)
2254 | (mask_m[34] << 22) | (mask_m[35] << 20)
2255 | (mask_m[36] << 18) | (mask_m[37] << 16)
2256 | (mask_m[48] << 14) | (mask_m[39] << 12)
2257 | (mask_m[40] << 10) | (mask_m[41] << 8)
2258 | (mask_m[42] << 6) | (mask_m[43] << 4)
2259 | (mask_m[44] << 2) | (mask_m[45] << 0);
2260 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2261 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2262
2263 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2264 | (mask_m[18] << 26) | (mask_m[18] << 24)
2265 | (mask_m[20] << 22) | (mask_m[20] << 20)
2266 | (mask_m[22] << 18) | (mask_m[22] << 16)
2267 | (mask_m[24] << 14) | (mask_m[24] << 12)
2268 | (mask_m[25] << 10) | (mask_m[26] << 8)
2269 | (mask_m[27] << 6) | (mask_m[28] << 4)
2270 | (mask_m[29] << 2) | (mask_m[30] << 0);
2271 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2272 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2273
2274 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2275 | (mask_m[2] << 26) | (mask_m[3] << 24)
2276 | (mask_m[4] << 22) | (mask_m[5] << 20)
2277 | (mask_m[6] << 18) | (mask_m[7] << 16)
2278 | (mask_m[8] << 14) | (mask_m[9] << 12)
2279 | (mask_m[10] << 10) | (mask_m[11] << 8)
2280 | (mask_m[12] << 6) | (mask_m[13] << 4)
2281 | (mask_m[14] << 2) | (mask_m[15] << 0);
2282 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2283 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2284
2285 tmp_mask = (mask_p[15] << 28)
2286 | (mask_p[14] << 26) | (mask_p[13] << 24)
2287 | (mask_p[12] << 22) | (mask_p[11] << 20)
2288 | (mask_p[10] << 18) | (mask_p[9] << 16)
2289 | (mask_p[8] << 14) | (mask_p[7] << 12)
2290 | (mask_p[6] << 10) | (mask_p[5] << 8)
2291 | (mask_p[4] << 6) | (mask_p[3] << 4)
2292 | (mask_p[2] << 2) | (mask_p[1] << 0);
2293 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2294 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2295
2296 tmp_mask = (mask_p[30] << 28)
2297 | (mask_p[29] << 26) | (mask_p[28] << 24)
2298 | (mask_p[27] << 22) | (mask_p[26] << 20)
2299 | (mask_p[25] << 18) | (mask_p[24] << 16)
2300 | (mask_p[23] << 14) | (mask_p[22] << 12)
2301 | (mask_p[21] << 10) | (mask_p[20] << 8)
2302 | (mask_p[19] << 6) | (mask_p[18] << 4)
2303 | (mask_p[17] << 2) | (mask_p[16] << 0);
2304 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2305 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2306
2307 tmp_mask = (mask_p[45] << 28)
2308 | (mask_p[44] << 26) | (mask_p[43] << 24)
2309 | (mask_p[42] << 22) | (mask_p[41] << 20)
2310 | (mask_p[40] << 18) | (mask_p[39] << 16)
2311 | (mask_p[38] << 14) | (mask_p[37] << 12)
2312 | (mask_p[36] << 10) | (mask_p[35] << 8)
2313 | (mask_p[34] << 6) | (mask_p[33] << 4)
2314 | (mask_p[32] << 2) | (mask_p[31] << 0);
2315 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2316 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2317
2318 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2319 | (mask_p[59] << 26) | (mask_p[58] << 24)
2320 | (mask_p[57] << 22) | (mask_p[56] << 20)
2321 | (mask_p[55] << 18) | (mask_p[54] << 16)
2322 | (mask_p[53] << 14) | (mask_p[52] << 12)
2323 | (mask_p[51] << 10) | (mask_p[50] << 8)
2324 | (mask_p[49] << 6) | (mask_p[48] << 4)
2325 | (mask_p[47] << 2) | (mask_p[46] << 0);
2326 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2327 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2328}
2329
2330static void ath9k_enable_rfkill(struct ath_hw *ah) 1905static void ath9k_enable_rfkill(struct ath_hw *ah)
2331{ 1906{
2332 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1907 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -2342,17 +1917,16 @@ static void ath9k_enable_rfkill(struct ath_hw *ah)
2342int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1917int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2343 bool bChannelChange) 1918 bool bChannelChange)
2344{ 1919{
1920 struct ath_common *common = ath9k_hw_common(ah);
2345 u32 saveLedState; 1921 u32 saveLedState;
2346 struct ath_softc *sc = ah->ah_sc;
2347 struct ath9k_channel *curchan = ah->curchan; 1922 struct ath9k_channel *curchan = ah->curchan;
2348 u32 saveDefAntenna; 1923 u32 saveDefAntenna;
2349 u32 macStaId1; 1924 u32 macStaId1;
2350 u64 tsf = 0; 1925 u64 tsf = 0;
2351 int i, rx_chainmask, r; 1926 int i, rx_chainmask, r;
2352 1927
2353 ah->extprotspacing = sc->ht_extprotspacing; 1928 ah->txchainmask = common->tx_chainmask;
2354 ah->txchainmask = sc->tx_chainmask; 1929 ah->rxchainmask = common->rx_chainmask;
2355 ah->rxchainmask = sc->rx_chainmask;
2356 1930
2357 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1931 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2358 return -EIO; 1932 return -EIO;
@@ -2369,7 +1943,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2369 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || 1943 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2370 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { 1944 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2371 1945
2372 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { 1946 if (ath9k_hw_channel_change(ah, chan)) {
2373 ath9k_hw_loadnf(ah, ah->curchan); 1947 ath9k_hw_loadnf(ah, ah->curchan);
2374 ath9k_hw_start_nfcal(ah); 1948 ath9k_hw_start_nfcal(ah);
2375 return 0; 1949 return 0;
@@ -2400,7 +1974,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2400 } 1974 }
2401 1975
2402 if (!ath9k_hw_chip_reset(ah, chan)) { 1976 if (!ath9k_hw_chip_reset(ah, chan)) {
2403 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n"); 1977 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2404 return -EINVAL; 1978 return -EINVAL;
2405 } 1979 }
2406 1980
@@ -2429,7 +2003,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2429 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 2003 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2430 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 2004 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2431 } 2005 }
2432 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width); 2006 r = ath9k_hw_process_ini(ah, chan);
2433 if (r) 2007 if (r)
2434 return r; 2008 return r;
2435 2009
@@ -2453,17 +2027,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2453 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2027 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2454 ath9k_hw_set_delta_slope(ah, chan); 2028 ath9k_hw_set_delta_slope(ah, chan);
2455 2029
2456 if (AR_SREV_9280_10_OR_LATER(ah)) 2030 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2457 ath9k_hw_9280_spur_mitigate(ah, chan);
2458 else
2459 ath9k_hw_spur_mitigate(ah, chan);
2460
2461 ah->eep_ops->set_board_values(ah, chan); 2031 ah->eep_ops->set_board_values(ah, chan);
2462 2032
2463 ath9k_hw_decrease_chain_power(ah, chan); 2033 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2464 2034 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2465 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2466 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2467 | macStaId1 2035 | macStaId1
2468 | AR_STA_ID1_RTS_USE_DEF 2036 | AR_STA_ID1_RTS_USE_DEF
2469 | (ah->config. 2037 | (ah->config.
@@ -2471,24 +2039,19 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2471 | ah->sta_id1_defaults); 2039 | ah->sta_id1_defaults);
2472 ath9k_hw_set_operating_mode(ah, ah->opmode); 2040 ath9k_hw_set_operating_mode(ah, ah->opmode);
2473 2041
2474 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 2042 ath_hw_setbssidmask(common);
2475 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2476 2043
2477 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2044 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2478 2045
2479 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); 2046 ath9k_hw_write_associd(ah);
2480 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2481 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2482 2047
2483 REG_WRITE(ah, AR_ISR, ~0); 2048 REG_WRITE(ah, AR_ISR, ~0);
2484 2049
2485 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2050 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2486 2051
2487 if (AR_SREV_9280_10_OR_LATER(ah)) 2052 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2488 ath9k_hw_ar9280_set_channel(ah, chan); 2053 if (r)
2489 else 2054 return r;
2490 if (!(ath9k_hw_set_channel(ah, chan)))
2491 return -EIO;
2492 2055
2493 for (i = 0; i < AR_NUM_DCU; i++) 2056 for (i = 0; i < AR_NUM_DCU; i++)
2494 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2057 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
@@ -2503,7 +2066,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2503 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2066 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2504 ath9k_enable_rfkill(ah); 2067 ath9k_enable_rfkill(ah);
2505 2068
2506 ath9k_hw_init_user_settings(ah); 2069 ath9k_hw_init_global_settings(ah);
2507 2070
2508 if (AR_SREV_9287_12_OR_LATER(ah)) { 2071 if (AR_SREV_9287_12_OR_LATER(ah)) {
2509 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 2072 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
@@ -2533,7 +2096,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2533 2096
2534 REG_WRITE(ah, AR_OBS, 8); 2097 REG_WRITE(ah, AR_OBS, 8);
2535 2098
2536 if (ah->config.intr_mitigation) { 2099 if (ah->config.rx_intr_mitigation) {
2537 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2100 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2538 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2101 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2539 } 2102 }
@@ -2558,13 +2121,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2558 u32 mask; 2121 u32 mask;
2559 mask = REG_READ(ah, AR_CFG); 2122 mask = REG_READ(ah, AR_CFG);
2560 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2123 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2561 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2124 ath_print(common, ATH_DBG_RESET,
2562 "CFG Byte Swap Set 0x%x\n", mask); 2125 "CFG Byte Swap Set 0x%x\n", mask);
2563 } else { 2126 } else {
2564 mask = 2127 mask =
2565 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2128 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2566 REG_WRITE(ah, AR_CFG, mask); 2129 REG_WRITE(ah, AR_CFG, mask);
2567 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2130 ath_print(common, ATH_DBG_RESET,
2568 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2131 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2569 } 2132 }
2570 } else { 2133 } else {
@@ -2577,11 +2140,12 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2577#endif 2140#endif
2578 } 2141 }
2579 2142
2580 if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED) 2143 if (ah->btcoex_hw.enabled)
2581 ath9k_hw_btcoex_enable(ah); 2144 ath9k_hw_btcoex_enable(ah);
2582 2145
2583 return 0; 2146 return 0;
2584} 2147}
2148EXPORT_SYMBOL(ath9k_hw_reset);
2585 2149
2586/************************/ 2150/************************/
2587/* Key Cache Management */ 2151/* Key Cache Management */
@@ -2592,8 +2156,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2592 u32 keyType; 2156 u32 keyType;
2593 2157
2594 if (entry >= ah->caps.keycache_size) { 2158 if (entry >= ah->caps.keycache_size) {
2595 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2159 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2596 "keychache entry %u out of range\n", entry); 2160 "keychache entry %u out of range\n", entry);
2597 return false; 2161 return false;
2598 } 2162 }
2599 2163
@@ -2620,14 +2184,15 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2620 2184
2621 return true; 2185 return true;
2622} 2186}
2187EXPORT_SYMBOL(ath9k_hw_keyreset);
2623 2188
2624bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 2189bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2625{ 2190{
2626 u32 macHi, macLo; 2191 u32 macHi, macLo;
2627 2192
2628 if (entry >= ah->caps.keycache_size) { 2193 if (entry >= ah->caps.keycache_size) {
2629 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2194 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2630 "keychache entry %u out of range\n", entry); 2195 "keychache entry %u out of range\n", entry);
2631 return false; 2196 return false;
2632 } 2197 }
2633 2198
@@ -2648,18 +2213,20 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2648 2213
2649 return true; 2214 return true;
2650} 2215}
2216EXPORT_SYMBOL(ath9k_hw_keysetmac);
2651 2217
2652bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 2218bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2653 const struct ath9k_keyval *k, 2219 const struct ath9k_keyval *k,
2654 const u8 *mac) 2220 const u8 *mac)
2655{ 2221{
2656 const struct ath9k_hw_capabilities *pCap = &ah->caps; 2222 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2223 struct ath_common *common = ath9k_hw_common(ah);
2657 u32 key0, key1, key2, key3, key4; 2224 u32 key0, key1, key2, key3, key4;
2658 u32 keyType; 2225 u32 keyType;
2659 2226
2660 if (entry >= pCap->keycache_size) { 2227 if (entry >= pCap->keycache_size) {
2661 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2228 ath_print(common, ATH_DBG_FATAL,
2662 "keycache entry %u out of range\n", entry); 2229 "keycache entry %u out of range\n", entry);
2663 return false; 2230 return false;
2664 } 2231 }
2665 2232
@@ -2669,9 +2236,9 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2669 break; 2236 break;
2670 case ATH9K_CIPHER_AES_CCM: 2237 case ATH9K_CIPHER_AES_CCM:
2671 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2238 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2672 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2239 ath_print(common, ATH_DBG_ANY,
2673 "AES-CCM not supported by mac rev 0x%x\n", 2240 "AES-CCM not supported by mac rev 0x%x\n",
2674 ah->hw_version.macRev); 2241 ah->hw_version.macRev);
2675 return false; 2242 return false;
2676 } 2243 }
2677 keyType = AR_KEYTABLE_TYPE_CCM; 2244 keyType = AR_KEYTABLE_TYPE_CCM;
@@ -2680,15 +2247,15 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2680 keyType = AR_KEYTABLE_TYPE_TKIP; 2247 keyType = AR_KEYTABLE_TYPE_TKIP;
2681 if (ATH9K_IS_MIC_ENABLED(ah) 2248 if (ATH9K_IS_MIC_ENABLED(ah)
2682 && entry + 64 >= pCap->keycache_size) { 2249 && entry + 64 >= pCap->keycache_size) {
2683 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2250 ath_print(common, ATH_DBG_ANY,
2684 "entry %u inappropriate for TKIP\n", entry); 2251 "entry %u inappropriate for TKIP\n", entry);
2685 return false; 2252 return false;
2686 } 2253 }
2687 break; 2254 break;
2688 case ATH9K_CIPHER_WEP: 2255 case ATH9K_CIPHER_WEP:
2689 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 2256 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2690 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2257 ath_print(common, ATH_DBG_ANY,
2691 "WEP key length %u too small\n", k->kv_len); 2258 "WEP key length %u too small\n", k->kv_len);
2692 return false; 2259 return false;
2693 } 2260 }
2694 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 2261 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
@@ -2702,8 +2269,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2702 keyType = AR_KEYTABLE_TYPE_CLR; 2269 keyType = AR_KEYTABLE_TYPE_CLR;
2703 break; 2270 break;
2704 default: 2271 default:
2705 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2272 ath_print(common, ATH_DBG_FATAL,
2706 "cipher %u not supported\n", k->kv_type); 2273 "cipher %u not supported\n", k->kv_type);
2707 return false; 2274 return false;
2708 } 2275 }
2709 2276
@@ -2845,6 +2412,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2845 2412
2846 return true; 2413 return true;
2847} 2414}
2415EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2848 2416
2849bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 2417bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2850{ 2418{
@@ -2855,6 +2423,7 @@ bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2855 } 2423 }
2856 return false; 2424 return false;
2857} 2425}
2426EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2858 2427
2859/******************************/ 2428/******************************/
2860/* Power Management (Chipset) */ 2429/* Power Management (Chipset) */
@@ -2869,8 +2438,9 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2869 if (!AR_SREV_9100(ah)) 2438 if (!AR_SREV_9100(ah))
2870 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2439 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2871 2440
2872 REG_CLR_BIT(ah, (AR_RTC_RESET), 2441 if(!AR_SREV_5416(ah))
2873 AR_RTC_RESET_EN); 2442 REG_CLR_BIT(ah, (AR_RTC_RESET),
2443 AR_RTC_RESET_EN);
2874 } 2444 }
2875} 2445}
2876 2446
@@ -2902,6 +2472,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2902 ATH9K_RESET_POWER_ON) != true) { 2472 ATH9K_RESET_POWER_ON) != true) {
2903 return false; 2473 return false;
2904 } 2474 }
2475 ath9k_hw_init_pll(ah, NULL);
2905 } 2476 }
2906 if (AR_SREV_9100(ah)) 2477 if (AR_SREV_9100(ah))
2907 REG_SET_BIT(ah, AR_RTC_RESET, 2478 REG_SET_BIT(ah, AR_RTC_RESET,
@@ -2920,8 +2491,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2920 AR_RTC_FORCE_WAKE_EN); 2491 AR_RTC_FORCE_WAKE_EN);
2921 } 2492 }
2922 if (i == 0) { 2493 if (i == 0) {
2923 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2494 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2924 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2495 "Failed to wakeup in %uus\n",
2496 POWER_UP_TIME / 20);
2925 return false; 2497 return false;
2926 } 2498 }
2927 } 2499 }
@@ -2931,9 +2503,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2931 return true; 2503 return true;
2932} 2504}
2933 2505
2934static bool ath9k_hw_setpower_nolock(struct ath_hw *ah, 2506bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2935 enum ath9k_power_mode mode)
2936{ 2507{
2508 struct ath_common *common = ath9k_hw_common(ah);
2937 int status = true, setChip = true; 2509 int status = true, setChip = true;
2938 static const char *modes[] = { 2510 static const char *modes[] = {
2939 "AWAKE", 2511 "AWAKE",
@@ -2945,8 +2517,8 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2945 if (ah->power_mode == mode) 2517 if (ah->power_mode == mode)
2946 return status; 2518 return status;
2947 2519
2948 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n", 2520 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2949 modes[ah->power_mode], modes[mode]); 2521 modes[ah->power_mode], modes[mode]);
2950 2522
2951 switch (mode) { 2523 switch (mode) {
2952 case ATH9K_PM_AWAKE: 2524 case ATH9K_PM_AWAKE:
@@ -2960,59 +2532,15 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2960 ath9k_set_power_network_sleep(ah, setChip); 2532 ath9k_set_power_network_sleep(ah, setChip);
2961 break; 2533 break;
2962 default: 2534 default:
2963 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2535 ath_print(common, ATH_DBG_FATAL,
2964 "Unknown power mode %u\n", mode); 2536 "Unknown power mode %u\n", mode);
2965 return false; 2537 return false;
2966 } 2538 }
2967 ah->power_mode = mode; 2539 ah->power_mode = mode;
2968 2540
2969 return status; 2541 return status;
2970} 2542}
2971 2543EXPORT_SYMBOL(ath9k_hw_setpower);
2972bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2973{
2974 unsigned long flags;
2975 bool ret;
2976
2977 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2978 ret = ath9k_hw_setpower_nolock(ah, mode);
2979 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2980
2981 return ret;
2982}
2983
2984void ath9k_ps_wakeup(struct ath_softc *sc)
2985{
2986 unsigned long flags;
2987
2988 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2989 if (++sc->ps_usecount != 1)
2990 goto unlock;
2991
2992 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2993
2994 unlock:
2995 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2996}
2997
2998void ath9k_ps_restore(struct ath_softc *sc)
2999{
3000 unsigned long flags;
3001
3002 spin_lock_irqsave(&sc->sc_pm_lock, flags);
3003 if (--sc->ps_usecount != 0)
3004 goto unlock;
3005
3006 if (sc->ps_enabled &&
3007 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
3008 SC_OP_WAIT_FOR_CAB |
3009 SC_OP_WAIT_FOR_PSPOLL_DATA |
3010 SC_OP_WAIT_FOR_TX_ACK)))
3011 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
3012
3013 unlock:
3014 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3015}
3016 2544
3017/* 2545/*
3018 * Helper for ASPM support. 2546 * Helper for ASPM support.
@@ -3145,6 +2673,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
3145 } 2673 }
3146 } 2674 }
3147} 2675}
2676EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
3148 2677
3149/**********************/ 2678/**********************/
3150/* Interrupt Handling */ 2679/* Interrupt Handling */
@@ -3168,6 +2697,7 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
3168 2697
3169 return false; 2698 return false;
3170} 2699}
2700EXPORT_SYMBOL(ath9k_hw_intrpend);
3171 2701
3172bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) 2702bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3173{ 2703{
@@ -3176,6 +2706,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3176 struct ath9k_hw_capabilities *pCap = &ah->caps; 2706 struct ath9k_hw_capabilities *pCap = &ah->caps;
3177 u32 sync_cause = 0; 2707 u32 sync_cause = 0;
3178 bool fatal_int = false; 2708 bool fatal_int = false;
2709 struct ath_common *common = ath9k_hw_common(ah);
3179 2710
3180 if (!AR_SREV_9100(ah)) { 2711 if (!AR_SREV_9100(ah)) {
3181 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2712 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -3225,7 +2756,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3225 2756
3226 *masked = isr & ATH9K_INT_COMMON; 2757 *masked = isr & ATH9K_INT_COMMON;
3227 2758
3228 if (ah->config.intr_mitigation) { 2759 if (ah->config.rx_intr_mitigation) {
3229 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2760 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3230 *masked |= ATH9K_INT_RX; 2761 *masked |= ATH9K_INT_RX;
3231 } 2762 }
@@ -3249,8 +2780,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3249 } 2780 }
3250 2781
3251 if (isr & AR_ISR_RXORN) { 2782 if (isr & AR_ISR_RXORN) {
3252 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2783 ath_print(common, ATH_DBG_INTERRUPT,
3253 "receive FIFO overrun interrupt\n"); 2784 "receive FIFO overrun interrupt\n");
3254 } 2785 }
3255 2786
3256 if (!AR_SREV_9100(ah)) { 2787 if (!AR_SREV_9100(ah)) {
@@ -3292,25 +2823,25 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3292 2823
3293 if (fatal_int) { 2824 if (fatal_int) {
3294 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2825 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3295 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2826 ath_print(common, ATH_DBG_ANY,
3296 "received PCI FATAL interrupt\n"); 2827 "received PCI FATAL interrupt\n");
3297 } 2828 }
3298 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2829 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3299 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2830 ath_print(common, ATH_DBG_ANY,
3300 "received PCI PERR interrupt\n"); 2831 "received PCI PERR interrupt\n");
3301 } 2832 }
3302 *masked |= ATH9K_INT_FATAL; 2833 *masked |= ATH9K_INT_FATAL;
3303 } 2834 }
3304 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2835 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3305 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2836 ath_print(common, ATH_DBG_INTERRUPT,
3306 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 2837 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3307 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2838 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3308 REG_WRITE(ah, AR_RC, 0); 2839 REG_WRITE(ah, AR_RC, 0);
3309 *masked |= ATH9K_INT_FATAL; 2840 *masked |= ATH9K_INT_FATAL;
3310 } 2841 }
3311 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2842 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3312 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2843 ath_print(common, ATH_DBG_INTERRUPT,
3313 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 2844 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3314 } 2845 }
3315 2846
3316 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2847 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -3319,17 +2850,19 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3319 2850
3320 return true; 2851 return true;
3321} 2852}
2853EXPORT_SYMBOL(ath9k_hw_getisr);
3322 2854
3323enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 2855enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3324{ 2856{
3325 u32 omask = ah->mask_reg; 2857 u32 omask = ah->mask_reg;
3326 u32 mask, mask2; 2858 u32 mask, mask2;
3327 struct ath9k_hw_capabilities *pCap = &ah->caps; 2859 struct ath9k_hw_capabilities *pCap = &ah->caps;
2860 struct ath_common *common = ath9k_hw_common(ah);
3328 2861
3329 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 2862 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3330 2863
3331 if (omask & ATH9K_INT_GLOBAL) { 2864 if (omask & ATH9K_INT_GLOBAL) {
3332 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n"); 2865 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3333 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 2866 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3334 (void) REG_READ(ah, AR_IER); 2867 (void) REG_READ(ah, AR_IER);
3335 if (!AR_SREV_9100(ah)) { 2868 if (!AR_SREV_9100(ah)) {
@@ -3356,7 +2889,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3356 } 2889 }
3357 if (ints & ATH9K_INT_RX) { 2890 if (ints & ATH9K_INT_RX) {
3358 mask |= AR_IMR_RXERR; 2891 mask |= AR_IMR_RXERR;
3359 if (ah->config.intr_mitigation) 2892 if (ah->config.rx_intr_mitigation)
3360 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2893 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3361 else 2894 else
3362 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2895 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
@@ -3386,7 +2919,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3386 mask2 |= AR_IMR_S2_CST; 2919 mask2 |= AR_IMR_S2_CST;
3387 } 2920 }
3388 2921
3389 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 2922 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3390 REG_WRITE(ah, AR_IMR, mask); 2923 REG_WRITE(ah, AR_IMR, mask);
3391 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 2924 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3392 AR_IMR_S2_DTIM | 2925 AR_IMR_S2_DTIM |
@@ -3406,7 +2939,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3406 } 2939 }
3407 2940
3408 if (ints & ATH9K_INT_GLOBAL) { 2941 if (ints & ATH9K_INT_GLOBAL) {
3409 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n"); 2942 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3410 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 2943 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3411 if (!AR_SREV_9100(ah)) { 2944 if (!AR_SREV_9100(ah)) {
3412 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 2945 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -3419,12 +2952,13 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3419 REG_WRITE(ah, AR_INTR_SYNC_MASK, 2952 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3420 AR_INTR_SYNC_DEFAULT); 2953 AR_INTR_SYNC_DEFAULT);
3421 } 2954 }
3422 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 2955 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3423 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 2956 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3424 } 2957 }
3425 2958
3426 return omask; 2959 return omask;
3427} 2960}
2961EXPORT_SYMBOL(ath9k_hw_set_interrupts);
3428 2962
3429/*******************/ 2963/*******************/
3430/* Beacon Handling */ 2964/* Beacon Handling */
@@ -3467,9 +3001,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3467 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3001 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3468 break; 3002 break;
3469 default: 3003 default:
3470 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, 3004 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3471 "%s: unsupported opmode: %d\n", 3005 "%s: unsupported opmode: %d\n",
3472 __func__, ah->opmode); 3006 __func__, ah->opmode);
3473 return; 3007 return;
3474 break; 3008 break;
3475 } 3009 }
@@ -3481,18 +3015,19 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3481 3015
3482 beacon_period &= ~ATH9K_BEACON_ENA; 3016 beacon_period &= ~ATH9K_BEACON_ENA;
3483 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 3017 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3484 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3485 ath9k_hw_reset_tsf(ah); 3018 ath9k_hw_reset_tsf(ah);
3486 } 3019 }
3487 3020
3488 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3021 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3489} 3022}
3023EXPORT_SYMBOL(ath9k_hw_beaconinit);
3490 3024
3491void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 3025void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3492 const struct ath9k_beacon_state *bs) 3026 const struct ath9k_beacon_state *bs)
3493{ 3027{
3494 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3028 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3495 struct ath9k_hw_capabilities *pCap = &ah->caps; 3029 struct ath9k_hw_capabilities *pCap = &ah->caps;
3030 struct ath_common *common = ath9k_hw_common(ah);
3496 3031
3497 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3032 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3498 3033
@@ -3518,10 +3053,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3518 else 3053 else
3519 nextTbtt = bs->bs_nexttbtt; 3054 nextTbtt = bs->bs_nexttbtt;
3520 3055
3521 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3056 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3522 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3057 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3523 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3058 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3524 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3059 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3525 3060
3526 REG_WRITE(ah, AR_NEXT_DTIM, 3061 REG_WRITE(ah, AR_NEXT_DTIM,
3527 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3062 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -3549,16 +3084,18 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3549 /* TSF Out of Range Threshold */ 3084 /* TSF Out of Range Threshold */
3550 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 3085 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3551} 3086}
3087EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3552 3088
3553/*******************/ 3089/*******************/
3554/* HW Capabilities */ 3090/* HW Capabilities */
3555/*******************/ 3091/*******************/
3556 3092
3557void ath9k_hw_fill_cap_info(struct ath_hw *ah) 3093int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3558{ 3094{
3559 struct ath9k_hw_capabilities *pCap = &ah->caps; 3095 struct ath9k_hw_capabilities *pCap = &ah->caps;
3560 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3096 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3561 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 3097 struct ath_common *common = ath9k_hw_common(ah);
3098 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3562 3099
3563 u16 capField = 0, eeval; 3100 u16 capField = 0, eeval;
3564 3101
@@ -3579,11 +3116,17 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3579 regulatory->current_rd += 5; 3116 regulatory->current_rd += 5;
3580 else if (regulatory->current_rd == 0x41) 3117 else if (regulatory->current_rd == 0x41)
3581 regulatory->current_rd = 0x43; 3118 regulatory->current_rd = 0x43;
3582 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 3119 ath_print(common, ATH_DBG_REGULATORY,
3583 "regdomain mapped to 0x%x\n", regulatory->current_rd); 3120 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3584 } 3121 }
3585 3122
3586 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 3123 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3124 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3125 ath_print(common, ATH_DBG_FATAL,
3126 "no band has been marked as supported in EEPROM.\n");
3127 return -EINVAL;
3128 }
3129
3587 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 3130 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3588 3131
3589 if (eeval & AR5416_OPFLAGS_11A) { 3132 if (eeval & AR5416_OPFLAGS_11A) {
@@ -3670,7 +3213,11 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3670 pCap->keycache_size = AR_KEYTABLE_SIZE; 3213 pCap->keycache_size = AR_KEYTABLE_SIZE;
3671 3214
3672 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 3215 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3673 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 3216
3217 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3218 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3219 else
3220 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3674 3221
3675 if (AR_SREV_9285_10_OR_LATER(ah)) 3222 if (AR_SREV_9285_10_OR_LATER(ah))
3676 pCap->num_gpio_pins = AR9285_NUM_GPIO; 3223 pCap->num_gpio_pins = AR9285_NUM_GPIO;
@@ -3719,7 +3266,10 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3719 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3266 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3720 } 3267 }
3721 3268
3722 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3269 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3270 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3271 AR_SREV_5416(ah))
3272 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3723 3273
3724 pCap->num_antcfg_5ghz = 3274 pCap->num_antcfg_5ghz =
3725 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 3275 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
@@ -3727,19 +3277,21 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3727 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 3277 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3728 3278
3729 if (AR_SREV_9280_10_OR_LATER(ah) && 3279 if (AR_SREV_9280_10_OR_LATER(ah) &&
3730 ath_btcoex_supported(ah->hw_version.subsysid)) { 3280 ath9k_hw_btcoex_supported(ah)) {
3731 btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO; 3281 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3732 btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 3282 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3733 3283
3734 if (AR_SREV_9285(ah)) { 3284 if (AR_SREV_9285(ah)) {
3735 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE; 3285 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3736 btcoex_info->btpriority_gpio = ATH_BTPRIORITY_GPIO; 3286 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3737 } else { 3287 } else {
3738 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE; 3288 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3739 } 3289 }
3740 } else { 3290 } else {
3741 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE; 3291 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3742 } 3292 }
3293
3294 return 0;
3743} 3295}
3744 3296
3745bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3297bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
@@ -3812,6 +3364,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3812 return false; 3364 return false;
3813 } 3365 }
3814} 3366}
3367EXPORT_SYMBOL(ath9k_hw_getcapability);
3815 3368
3816bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3369bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3817 u32 capability, u32 setting, int *status) 3370 u32 capability, u32 setting, int *status)
@@ -3845,6 +3398,7 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3845 return false; 3398 return false;
3846 } 3399 }
3847} 3400}
3401EXPORT_SYMBOL(ath9k_hw_setcapability);
3848 3402
3849/****************************/ 3403/****************************/
3850/* GPIO / RFKILL / Antennae */ 3404/* GPIO / RFKILL / Antennae */
@@ -3882,7 +3436,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3882{ 3436{
3883 u32 gpio_shift; 3437 u32 gpio_shift;
3884 3438
3885 ASSERT(gpio < ah->caps.num_gpio_pins); 3439 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3886 3440
3887 gpio_shift = gpio << 1; 3441 gpio_shift = gpio << 1;
3888 3442
@@ -3891,6 +3445,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3891 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 3445 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3892 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3446 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3893} 3447}
3448EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3894 3449
3895u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 3450u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3896{ 3451{
@@ -3909,6 +3464,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3909 else 3464 else
3910 return MS_REG_READ(AR, gpio) != 0; 3465 return MS_REG_READ(AR, gpio) != 0;
3911} 3466}
3467EXPORT_SYMBOL(ath9k_hw_gpio_get);
3912 3468
3913void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 3469void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3914 u32 ah_signal_type) 3470 u32 ah_signal_type)
@@ -3924,67 +3480,26 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3924 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 3480 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3925 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3481 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3926} 3482}
3483EXPORT_SYMBOL(ath9k_hw_cfg_output);
3927 3484
3928void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 3485void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3929{ 3486{
3930 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3487 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3931 AR_GPIO_BIT(gpio)); 3488 AR_GPIO_BIT(gpio));
3932} 3489}
3490EXPORT_SYMBOL(ath9k_hw_set_gpio);
3933 3491
3934u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 3492u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3935{ 3493{
3936 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3494 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3937} 3495}
3496EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3938 3497
3939void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 3498void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3940{ 3499{
3941 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3500 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3942} 3501}
3943 3502EXPORT_SYMBOL(ath9k_hw_setantenna);
3944bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3945 enum ath9k_ant_setting settings,
3946 struct ath9k_channel *chan,
3947 u8 *tx_chainmask,
3948 u8 *rx_chainmask,
3949 u8 *antenna_cfgd)
3950{
3951 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3952
3953 if (AR_SREV_9280(ah)) {
3954 if (!tx_chainmask_cfg) {
3955
3956 tx_chainmask_cfg = *tx_chainmask;
3957 rx_chainmask_cfg = *rx_chainmask;
3958 }
3959
3960 switch (settings) {
3961 case ATH9K_ANT_FIXED_A:
3962 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3963 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3964 *antenna_cfgd = true;
3965 break;
3966 case ATH9K_ANT_FIXED_B:
3967 if (ah->caps.tx_chainmask >
3968 ATH9K_ANTENNA1_CHAINMASK) {
3969 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3970 }
3971 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3972 *antenna_cfgd = true;
3973 break;
3974 case ATH9K_ANT_VARIABLE:
3975 *tx_chainmask = tx_chainmask_cfg;
3976 *rx_chainmask = rx_chainmask_cfg;
3977 *antenna_cfgd = true;
3978 break;
3979 default:
3980 break;
3981 }
3982 } else {
3983 ah->config.diversity_control = settings;
3984 }
3985
3986 return true;
3987}
3988 3503
3989/*********************/ 3504/*********************/
3990/* General Operation */ 3505/* General Operation */
@@ -4002,6 +3517,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
4002 3517
4003 return bits; 3518 return bits;
4004} 3519}
3520EXPORT_SYMBOL(ath9k_hw_getrxfilter);
4005 3521
4006void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 3522void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4007{ 3523{
@@ -4023,19 +3539,30 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4023 REG_WRITE(ah, AR_RXCFG, 3539 REG_WRITE(ah, AR_RXCFG,
4024 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3540 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4025} 3541}
3542EXPORT_SYMBOL(ath9k_hw_setrxfilter);
4026 3543
4027bool ath9k_hw_phy_disable(struct ath_hw *ah) 3544bool ath9k_hw_phy_disable(struct ath_hw *ah)
4028{ 3545{
4029 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 3546 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3547 return false;
3548
3549 ath9k_hw_init_pll(ah, NULL);
3550 return true;
4030} 3551}
3552EXPORT_SYMBOL(ath9k_hw_phy_disable);
4031 3553
4032bool ath9k_hw_disable(struct ath_hw *ah) 3554bool ath9k_hw_disable(struct ath_hw *ah)
4033{ 3555{
4034 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3556 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
4035 return false; 3557 return false;
4036 3558
4037 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); 3559 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3560 return false;
3561
3562 ath9k_hw_init_pll(ah, NULL);
3563 return true;
4038} 3564}
3565EXPORT_SYMBOL(ath9k_hw_disable);
4039 3566
4040void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 3567void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4041{ 3568{
@@ -4052,35 +3579,36 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4052 min((u32) MAX_RATE_POWER, 3579 min((u32) MAX_RATE_POWER,
4053 (u32) regulatory->power_limit)); 3580 (u32) regulatory->power_limit));
4054} 3581}
3582EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
4055 3583
4056void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) 3584void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4057{ 3585{
4058 memcpy(ah->macaddr, mac, ETH_ALEN); 3586 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4059} 3587}
3588EXPORT_SYMBOL(ath9k_hw_setmac);
4060 3589
4061void ath9k_hw_setopmode(struct ath_hw *ah) 3590void ath9k_hw_setopmode(struct ath_hw *ah)
4062{ 3591{
4063 ath9k_hw_set_operating_mode(ah, ah->opmode); 3592 ath9k_hw_set_operating_mode(ah, ah->opmode);
4064} 3593}
3594EXPORT_SYMBOL(ath9k_hw_setopmode);
4065 3595
4066void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 3596void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4067{ 3597{
4068 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3598 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4069 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3599 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4070} 3600}
3601EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
4071 3602
4072void ath9k_hw_setbssidmask(struct ath_softc *sc) 3603void ath9k_hw_write_associd(struct ath_hw *ah)
4073{ 3604{
4074 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 3605 struct ath_common *common = ath9k_hw_common(ah);
4075 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
4076}
4077 3606
4078void ath9k_hw_write_associd(struct ath_softc *sc) 3607 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4079{ 3608 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4080 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); 3609 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4081 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
4082 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4083} 3610}
3611EXPORT_SYMBOL(ath9k_hw_write_associd);
4084 3612
4085u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3613u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4086{ 3614{
@@ -4091,24 +3619,25 @@ u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4091 3619
4092 return tsf; 3620 return tsf;
4093} 3621}
3622EXPORT_SYMBOL(ath9k_hw_gettsf64);
4094 3623
4095void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3624void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4096{ 3625{
4097 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3626 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4098 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3627 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4099} 3628}
3629EXPORT_SYMBOL(ath9k_hw_settsf64);
4100 3630
4101void ath9k_hw_reset_tsf(struct ath_hw *ah) 3631void ath9k_hw_reset_tsf(struct ath_hw *ah)
4102{ 3632{
4103 ath9k_ps_wakeup(ah->ah_sc);
4104 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3633 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4105 AH_TSF_WRITE_TIMEOUT)) 3634 AH_TSF_WRITE_TIMEOUT))
4106 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 3635 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4107 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3636 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4108 3637
4109 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3638 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4110 ath9k_ps_restore(ah->ah_sc);
4111} 3639}
3640EXPORT_SYMBOL(ath9k_hw_reset_tsf);
4112 3641
4113void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 3642void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4114{ 3643{
@@ -4117,26 +3646,29 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4117 else 3646 else
4118 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3647 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4119} 3648}
3649EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
4120 3650
4121bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 3651/*
3652 * Extend 15-bit time stamp from rx descriptor to
3653 * a full 64-bit TSF using the current h/w TSF.
3654*/
3655u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
4122{ 3656{
4123 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3657 u64 tsf;
4124 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3658
4125 ah->slottime = (u32) -1; 3659 tsf = ath9k_hw_gettsf64(ah);
4126 return false; 3660 if ((tsf & 0x7fff) < rstamp)
4127 } else { 3661 tsf -= 0x8000;
4128 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 3662 return (tsf & ~0x7fff) | rstamp;
4129 ah->slottime = us;
4130 return true;
4131 }
4132} 3663}
3664EXPORT_SYMBOL(ath9k_hw_extend_tsf);
4133 3665
4134void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) 3666void ath9k_hw_set11nmac2040(struct ath_hw *ah)
4135{ 3667{
3668 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
4136 u32 macmode; 3669 u32 macmode;
4137 3670
4138 if (mode == ATH9K_HT_MACMODE_2040 && 3671 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
4139 !ah->config.cwm_ignore_extcca)
4140 macmode = AR_2040_JOINED_RX_CLEAR; 3672 macmode = AR_2040_JOINED_RX_CLEAR;
4141 else 3673 else
4142 macmode = 0; 3674 macmode = 0;
@@ -4193,6 +3725,7 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4193{ 3725{
4194 return REG_READ(ah, AR_TSF_L32); 3726 return REG_READ(ah, AR_TSF_L32);
4195} 3727}
3728EXPORT_SYMBOL(ath9k_hw_gettsf32);
4196 3729
4197struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3730struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4198 void (*trigger)(void *), 3731 void (*trigger)(void *),
@@ -4206,8 +3739,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4206 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3739 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4207 3740
4208 if (timer == NULL) { 3741 if (timer == NULL) {
4209 printk(KERN_DEBUG "Failed to allocate memory" 3742 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4210 "for hw timer[%d]\n", timer_index); 3743 "Failed to allocate memory"
3744 "for hw timer[%d]\n", timer_index);
4211 return NULL; 3745 return NULL;
4212 } 3746 }
4213 3747
@@ -4220,10 +3754,12 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4220 3754
4221 return timer; 3755 return timer;
4222} 3756}
3757EXPORT_SYMBOL(ath_gen_timer_alloc);
4223 3758
4224void ath_gen_timer_start(struct ath_hw *ah, 3759void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4225 struct ath_gen_timer *timer, 3760 struct ath_gen_timer *timer,
4226 u32 timer_next, u32 timer_period) 3761 u32 timer_next,
3762 u32 timer_period)
4227{ 3763{
4228 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3764 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4229 u32 tsf; 3765 u32 tsf;
@@ -4234,8 +3770,9 @@ void ath_gen_timer_start(struct ath_hw *ah,
4234 3770
4235 tsf = ath9k_hw_gettsf32(ah); 3771 tsf = ath9k_hw_gettsf32(ah);
4236 3772
4237 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x" 3773 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4238 "timer_next %x\n", tsf, timer_period, timer_next); 3774 "curent tsf %x period %x"
3775 "timer_next %x\n", tsf, timer_period, timer_next);
4239 3776
4240 /* 3777 /*
4241 * Pull timer_next forward if the current TSF already passed it 3778 * Pull timer_next forward if the current TSF already passed it
@@ -4258,15 +3795,10 @@ void ath_gen_timer_start(struct ath_hw *ah,
4258 REG_SET_BIT(ah, AR_IMR_S5, 3795 REG_SET_BIT(ah, AR_IMR_S5,
4259 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3796 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4260 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3797 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4261
4262 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4263 ath9k_hw_set_interrupts(ah, 0);
4264 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4265 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4266 }
4267} 3798}
3799EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
4268 3800
4269void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3801void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4270{ 3802{
4271 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3803 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4272 3804
@@ -4285,14 +3817,8 @@ void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4285 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3817 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4286 3818
4287 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3819 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4288
4289 /* if no timer is enabled, turn off interrupt mask */
4290 if (timer_table->timer_mask.val == 0) {
4291 ath9k_hw_set_interrupts(ah, 0);
4292 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4293 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4294 }
4295} 3820}
3821EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
4296 3822
4297void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3823void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4298{ 3824{
@@ -4302,6 +3828,7 @@ void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4302 timer_table->timers[timer->index] = NULL; 3828 timer_table->timers[timer->index] = NULL;
4303 kfree(timer); 3829 kfree(timer);
4304} 3830}
3831EXPORT_SYMBOL(ath_gen_timer_free);
4305 3832
4306/* 3833/*
4307 * Generic Timer Interrupts handling 3834 * Generic Timer Interrupts handling
@@ -4310,6 +3837,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4310{ 3837{
4311 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3838 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4312 struct ath_gen_timer *timer; 3839 struct ath_gen_timer *timer;
3840 struct ath_common *common = ath9k_hw_common(ah);
4313 u32 trigger_mask, thresh_mask, index; 3841 u32 trigger_mask, thresh_mask, index;
4314 3842
4315 /* get hardware generic timer interrupt status */ 3843 /* get hardware generic timer interrupt status */
@@ -4324,8 +3852,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4324 index = rightmost_index(timer_table, &thresh_mask); 3852 index = rightmost_index(timer_table, &thresh_mask);
4325 timer = timer_table->timers[index]; 3853 timer = timer_table->timers[index];
4326 BUG_ON(!timer); 3854 BUG_ON(!timer);
4327 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, 3855 ath_print(common, ATH_DBG_HWTIMER,
4328 "TSF overflow for Gen timer %d\n", index); 3856 "TSF overflow for Gen timer %d\n", index);
4329 timer->overflow(timer->arg); 3857 timer->overflow(timer->arg);
4330 } 3858 }
4331 3859
@@ -4333,21 +3861,95 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4333 index = rightmost_index(timer_table, &trigger_mask); 3861 index = rightmost_index(timer_table, &trigger_mask);
4334 timer = timer_table->timers[index]; 3862 timer = timer_table->timers[index];
4335 BUG_ON(!timer); 3863 BUG_ON(!timer);
4336 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, 3864 ath_print(common, ATH_DBG_HWTIMER,
4337 "Gen timer[%d] trigger\n", index); 3865 "Gen timer[%d] trigger\n", index);
4338 timer->trigger(timer->arg); 3866 timer->trigger(timer->arg);
4339 } 3867 }
4340} 3868}
3869EXPORT_SYMBOL(ath_gen_timer_isr);
3870
3871static struct {
3872 u32 version;
3873 const char * name;
3874} ath_mac_bb_names[] = {
3875 /* Devices with external radios */
3876 { AR_SREV_VERSION_5416_PCI, "5416" },
3877 { AR_SREV_VERSION_5416_PCIE, "5418" },
3878 { AR_SREV_VERSION_9100, "9100" },
3879 { AR_SREV_VERSION_9160, "9160" },
3880 /* Single-chip solutions */
3881 { AR_SREV_VERSION_9280, "9280" },
3882 { AR_SREV_VERSION_9285, "9285" },
3883 { AR_SREV_VERSION_9287, "9287" },
3884 { AR_SREV_VERSION_9271, "9271" },
3885};
3886
3887/* For devices with external radios */
3888static struct {
3889 u16 version;
3890 const char * name;
3891} ath_rf_names[] = {
3892 { 0, "5133" },
3893 { AR_RAD5133_SREV_MAJOR, "5133" },
3894 { AR_RAD5122_SREV_MAJOR, "5122" },
3895 { AR_RAD2133_SREV_MAJOR, "2133" },
3896 { AR_RAD2122_SREV_MAJOR, "2122" }
3897};
3898
3899/*
3900 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3901 */
3902static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3903{
3904 int i;
3905
3906 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3907 if (ath_mac_bb_names[i].version == mac_bb_version) {
3908 return ath_mac_bb_names[i].name;
3909 }
3910 }
3911
3912 return "????";
3913}
4341 3914
4342/* 3915/*
4343 * Primitive to disable ASPM 3916 * Return the RF name. "????" is returned if the RF is unknown.
3917 * Used for devices with external radios.
4344 */ 3918 */
4345void ath_pcie_aspm_disable(struct ath_softc *sc) 3919static const char *ath9k_hw_rf_name(u16 rf_version)
4346{ 3920{
4347 struct pci_dev *pdev = to_pci_dev(sc->dev); 3921 int i;
4348 u8 aspm; 3922
3923 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3924 if (ath_rf_names[i].version == rf_version) {
3925 return ath_rf_names[i].name;
3926 }
3927 }
3928
3929 return "????";
3930}
3931
3932void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3933{
3934 int used;
3935
3936 /* chipsets >= AR9280 are single-chip */
3937 if (AR_SREV_9280_10_OR_LATER(ah)) {
3938 used = snprintf(hw_name, len,
3939 "Atheros AR%s Rev:%x",
3940 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3941 ah->hw_version.macRev);
3942 }
3943 else {
3944 used = snprintf(hw_name, len,
3945 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3946 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3947 ah->hw_version.macRev,
3948 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3949 AR_RADIO_SREV_MAJOR)),
3950 ah->hw_version.phyRev);
3951 }
4349 3952
4350 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm); 3953 hw_name[used] = '\0';
4351 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
4352 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
4353} 3954}
3955EXPORT_SYMBOL(ath9k_hw_name);
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index b89234571829..dbbf7ca5f97d 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -27,17 +27,25 @@
27#include "calib.h" 27#include "calib.h"
28#include "reg.h" 28#include "reg.h"
29#include "phy.h" 29#include "phy.h"
30#include "btcoex.h"
30 31
31#include "../regd.h" 32#include "../regd.h"
33#include "../debug.h"
32 34
33#define ATHEROS_VENDOR_ID 0x168c 35#define ATHEROS_VENDOR_ID 0x168c
36
34#define AR5416_DEVID_PCI 0x0023 37#define AR5416_DEVID_PCI 0x0023
35#define AR5416_DEVID_PCIE 0x0024 38#define AR5416_DEVID_PCIE 0x0024
36#define AR9160_DEVID_PCI 0x0027 39#define AR9160_DEVID_PCI 0x0027
37#define AR9280_DEVID_PCI 0x0029 40#define AR9280_DEVID_PCI 0x0029
38#define AR9280_DEVID_PCIE 0x002a 41#define AR9280_DEVID_PCIE 0x002a
39#define AR9285_DEVID_PCIE 0x002b 42#define AR9285_DEVID_PCIE 0x002b
43#define AR2427_DEVID_PCIE 0x002c
44
40#define AR5416_AR9100_DEVID 0x000b 45#define AR5416_AR9100_DEVID 0x000b
46
47#define AR9271_USB 0x9271
48
41#define AR_SUBVENDOR_ID_NOG 0x0e11 49#define AR_SUBVENDOR_ID_NOG 0x0e11
42#define AR_SUBVENDOR_ID_NEW_A 0x7065 50#define AR_SUBVENDOR_ID_NEW_A 0x7065
43#define AR5416_MAGIC 0x19641014 51#define AR5416_MAGIC 0x19641014
@@ -49,9 +57,18 @@
49#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 57#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
50#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 58#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
51 59
60#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
61
62#define ATH_DEFAULT_NOISE_FLOOR -95
63
64#define ATH9K_RSSI_BAD -128
65
52/* Register read/write primitives */ 66/* Register read/write primitives */
53#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val)) 67#define REG_WRITE(_ah, _reg, _val) \
54#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg)) 68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69
70#define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
55 72
56#define SM(_v, _f) (((_v) << _f##_S) & _f) 73#define SM(_v, _f) (((_v) << _f##_S) & _f)
57#define MS(_v, _f) (((_v) & _f) >> _f##_S) 74#define MS(_v, _f) (((_v) & _f) >> _f##_S)
@@ -91,7 +108,7 @@
91#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 108#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
92 109
93#define BASE_ACTIVATE_DELAY 100 110#define BASE_ACTIVATE_DELAY 100
94#define RTC_PLL_SETTLE_DELAY 1000 111#define RTC_PLL_SETTLE_DELAY 100
95#define COEF_SCALE_S 24 112#define COEF_SCALE_S 24
96#define HT40_CHANNEL_CENTER_SHIFT 10 113#define HT40_CHANNEL_CENTER_SHIFT 10
97 114
@@ -132,12 +149,6 @@ enum wireless_mode {
132 ATH9K_MODE_MAX, 149 ATH9K_MODE_MAX,
133}; 150};
134 151
135enum ath9k_ant_setting {
136 ATH9K_ANT_VARIABLE = 0,
137 ATH9K_ANT_FIXED_A,
138 ATH9K_ANT_FIXED_B
139};
140
141enum ath9k_hw_caps { 152enum ath9k_hw_caps {
142 ATH9K_HW_CAP_MIC_AESCCM = BIT(0), 153 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
143 ATH9K_HW_CAP_MIC_CKIP = BIT(1), 154 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
@@ -201,10 +212,8 @@ struct ath9k_ops_config {
201 u32 cck_trig_high; 212 u32 cck_trig_high;
202 u32 cck_trig_low; 213 u32 cck_trig_low;
203 u32 enable_ani; 214 u32 enable_ani;
204 enum ath9k_ant_setting diversity_control;
205 u16 antenna_switch_swap;
206 int serialize_regmode; 215 int serialize_regmode;
207 bool intr_mitigation; 216 bool rx_intr_mitigation;
208#define SPUR_DISABLE 0 217#define SPUR_DISABLE 0
209#define SPUR_ENABLE_IOCTL 1 218#define SPUR_ENABLE_IOCTL 1
210#define SPUR_ENABLE_EEPROM 2 219#define SPUR_ENABLE_EEPROM 2
@@ -218,6 +227,7 @@ struct ath9k_ops_config {
218#define AR_SPUR_FEEQ_BOUND_HT20 10 227#define AR_SPUR_FEEQ_BOUND_HT20 10
219 int spurmode; 228 int spurmode;
220 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 229 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
230 u8 max_txtrig_level;
221}; 231};
222 232
223enum ath9k_int { 233enum ath9k_int {
@@ -407,7 +417,7 @@ struct ath9k_hw_version {
407 * Using de Bruijin sequence to to look up 1's index in a 32 bit number 417 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
408 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 418 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
409 */ 419 */
410#define debruijn32 0x077CB531UL 420#define debruijn32 0x077CB531U
411 421
412struct ath_gen_timer_configuration { 422struct ath_gen_timer_configuration {
413 u32 next_addr; 423 u32 next_addr;
@@ -433,7 +443,8 @@ struct ath_gen_timer_table {
433}; 443};
434 444
435struct ath_hw { 445struct ath_hw {
436 struct ath_softc *ah_sc; 446 struct ieee80211_hw *hw;
447 struct ath_common common;
437 struct ath9k_hw_version hw_version; 448 struct ath9k_hw_version hw_version;
438 struct ath9k_ops_config config; 449 struct ath9k_ops_config config;
439 struct ath9k_hw_capabilities caps; 450 struct ath9k_hw_capabilities caps;
@@ -450,7 +461,6 @@ struct ath_hw {
450 461
451 bool sw_mgmt_crypto; 462 bool sw_mgmt_crypto;
452 bool is_pciexpress; 463 bool is_pciexpress;
453 u8 macaddr[ETH_ALEN];
454 u16 tx_trig_level; 464 u16 tx_trig_level;
455 u16 rfsilent; 465 u16 rfsilent;
456 u32 rfkill_gpio; 466 u32 rfkill_gpio;
@@ -523,7 +533,14 @@ struct ath_hw {
523 DONT_USE_32KHZ, 533 DONT_USE_32KHZ,
524 } enable_32kHz_clock; 534 } enable_32kHz_clock;
525 535
526 /* RF */ 536 /* Callback for radio frequency change */
537 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
538
539 /* Callback for baseband spur frequency */
540 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542
543 /* Used to program the radio on non single-chip devices */
527 u32 *analogBank0Data; 544 u32 *analogBank0Data;
528 u32 *analogBank1Data; 545 u32 *analogBank1Data;
529 u32 *analogBank2Data; 546 u32 *analogBank2Data;
@@ -535,12 +552,10 @@ struct ath_hw {
535 u32 *bank6Temp; 552 u32 *bank6Temp;
536 553
537 int16_t txpower_indexoffset; 554 int16_t txpower_indexoffset;
555 int coverage_class;
538 u32 beacon_interval; 556 u32 beacon_interval;
539 u32 slottime; 557 u32 slottime;
540 u32 acktimeout;
541 u32 ctstimeout;
542 u32 globaltxtimeout; 558 u32 globaltxtimeout;
543 u8 gbeacon_rate;
544 559
545 /* ANI */ 560 /* ANI */
546 u32 proc_phyerr; 561 u32 proc_phyerr;
@@ -553,8 +568,10 @@ struct ath_hw {
553 int firpwr[5]; 568 int firpwr[5];
554 enum ath9k_ani_cmd ani_function; 569 enum ath9k_ani_cmd ani_function;
555 570
571 /* Bluetooth coexistance */
572 struct ath_btcoex_hw btcoex_hw;
573
556 u32 intr_txqs; 574 u32 intr_txqs;
557 enum ath9k_ht_extprotspacing extprotspacing;
558 u8 txchainmask; 575 u8 txchainmask;
559 u8 rxchainmask; 576 u8 rxchainmask;
560 577
@@ -578,20 +595,32 @@ struct ath_hw {
578 struct ar5416IniArray iniModesAdditional; 595 struct ar5416IniArray iniModesAdditional;
579 struct ar5416IniArray iniModesRxGain; 596 struct ar5416IniArray iniModesRxGain;
580 struct ar5416IniArray iniModesTxGain; 597 struct ar5416IniArray iniModesTxGain;
598 struct ar5416IniArray iniModes_9271_1_0_only;
599 struct ar5416IniArray iniCckfirNormal;
600 struct ar5416IniArray iniCckfirJapan2484;
581 601
582 u32 intr_gen_timer_trigger; 602 u32 intr_gen_timer_trigger;
583 u32 intr_gen_timer_thresh; 603 u32 intr_gen_timer_thresh;
584 struct ath_gen_timer_table hw_gen_timers; 604 struct ath_gen_timer_table hw_gen_timers;
585}; 605};
586 606
607static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
608{
609 return &ah->common;
610}
611
612static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
613{
614 return &(ath9k_hw_common(ah)->regulatory);
615}
616
587/* Initialization, Detach, Reset */ 617/* Initialization, Detach, Reset */
588const char *ath9k_hw_probe(u16 vendorid, u16 devid); 618const char *ath9k_hw_probe(u16 vendorid, u16 devid);
589void ath9k_hw_detach(struct ath_hw *ah); 619void ath9k_hw_deinit(struct ath_hw *ah);
590int ath9k_hw_init(struct ath_hw *ah); 620int ath9k_hw_init(struct ath_hw *ah);
591void ath9k_hw_rf_free(struct ath_hw *ah);
592int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 621int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
593 bool bChannelChange); 622 bool bChannelChange);
594void ath9k_hw_fill_cap_info(struct ath_hw *ah); 623int ath9k_hw_fill_cap_info(struct ath_hw *ah);
595bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 624bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
596 u32 capability, u32 *result); 625 u32 capability, u32 *result);
597bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 626bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
@@ -613,18 +642,13 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
613void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 642void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
614u32 ath9k_hw_getdefantenna(struct ath_hw *ah); 643u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
615void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 644void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
616bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
617 enum ath9k_ant_setting settings,
618 struct ath9k_channel *chan,
619 u8 *tx_chainmask, u8 *rx_chainmask,
620 u8 *antenna_cfgd);
621 645
622/* General Operation */ 646/* General Operation */
623bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 647bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
624u32 ath9k_hw_reverse_bits(u32 val, u32 n); 648u32 ath9k_hw_reverse_bits(u32 val, u32 n);
625bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); 649bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
626u16 ath9k_hw_computetxtime(struct ath_hw *ah, 650u16 ath9k_hw_computetxtime(struct ath_hw *ah,
627 const struct ath_rate_table *rates, 651 u8 phy, int kbps,
628 u32 frameLen, u16 rateix, bool shortPreamble); 652 u32 frameLen, u16 rateix, bool shortPreamble);
629void ath9k_hw_get_channel_centers(struct ath_hw *ah, 653void ath9k_hw_get_channel_centers(struct ath_hw *ah,
630 struct ath9k_channel *chan, 654 struct ath9k_channel *chan,
@@ -637,19 +661,21 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
637void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); 661void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
638void ath9k_hw_setopmode(struct ath_hw *ah); 662void ath9k_hw_setopmode(struct ath_hw *ah);
639void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 663void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
640void ath9k_hw_setbssidmask(struct ath_softc *sc); 664void ath9k_hw_setbssidmask(struct ath_hw *ah);
641void ath9k_hw_write_associd(struct ath_softc *sc); 665void ath9k_hw_write_associd(struct ath_hw *ah);
642u64 ath9k_hw_gettsf64(struct ath_hw *ah); 666u64 ath9k_hw_gettsf64(struct ath_hw *ah);
643void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 667void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
644void ath9k_hw_reset_tsf(struct ath_hw *ah); 668void ath9k_hw_reset_tsf(struct ath_hw *ah);
645void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 669void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
646bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); 670u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
647void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); 671void ath9k_hw_init_global_settings(struct ath_hw *ah);
672void ath9k_hw_set11nmac2040(struct ath_hw *ah);
648void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 673void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
649void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 674void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
650 const struct ath9k_beacon_state *bs); 675 const struct ath9k_beacon_state *bs);
651bool ath9k_hw_setpower(struct ath_hw *ah, 676
652 enum ath9k_power_mode mode); 677bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
678
653void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off); 679void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
654 680
655/* Interrupt Handling */ 681/* Interrupt Handling */
@@ -663,16 +689,20 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
663 void (*overflow)(void *), 689 void (*overflow)(void *),
664 void *arg, 690 void *arg,
665 u8 timer_index); 691 u8 timer_index);
666void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer, 692void ath9k_hw_gen_timer_start(struct ath_hw *ah,
667 u32 timer_next, u32 timer_period); 693 struct ath_gen_timer *timer,
668void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 694 u32 timer_next,
695 u32 timer_period);
696void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
697
669void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 698void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
670void ath_gen_timer_isr(struct ath_hw *hw); 699void ath_gen_timer_isr(struct ath_hw *hw);
671u32 ath9k_hw_gettsf32(struct ath_hw *ah); 700u32 ath9k_hw_gettsf32(struct ath_hw *ah);
672 701
702void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
703
673#define ATH_PCIE_CAP_LINK_CTRL 0x70 704#define ATH_PCIE_CAP_LINK_CTRL 0x70
674#define ATH_PCIE_CAP_LINK_L0S 1 705#define ATH_PCIE_CAP_LINK_L0S 1
675#define ATH_PCIE_CAP_LINK_L1 2 706#define ATH_PCIE_CAP_LINK_L1 2
676 707
677void ath_pcie_aspm_disable(struct ath_softc *sc);
678#endif 708#endif
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
new file mode 100644
index 000000000000..3d4d897add6d
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -0,0 +1,865 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/slab.h>
18
19#include "ath9k.h"
20
21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
28static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
29module_param_named(debug, ath9k_debug, uint, 0);
30MODULE_PARM_DESC(debug, "Debugging mask");
31
32int modparam_nohwcrypt;
33module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
34MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
35
36/* We use the hw_value as an index into our private channel structure */
37
38#define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 20, \
42}
43
44#define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
48 .max_power = 20, \
49}
50
51/* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70};
71
72/* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105};
106
107/* Atheros hardware rate code addition for short premble */
108#define SHPCHECK(__hw_rate, __flags) \
109 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
110
111#define RATE(_bitrate, _hw_rate, _flags) { \
112 .bitrate = (_bitrate), \
113 .flags = (_flags), \
114 .hw_value = (_hw_rate), \
115 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
116}
117
118static struct ieee80211_rate ath9k_legacy_rates[] = {
119 RATE(10, 0x1b, 0),
120 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
122 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATE(60, 0x0b, 0),
124 RATE(90, 0x0f, 0),
125 RATE(120, 0x0a, 0),
126 RATE(180, 0x0e, 0),
127 RATE(240, 0x09, 0),
128 RATE(360, 0x0d, 0),
129 RATE(480, 0x08, 0),
130 RATE(540, 0x0c, 0),
131};
132
133static void ath9k_deinit_softc(struct ath_softc *sc);
134
135/*
136 * Read and write, they both share the same lock. We do this to serialize
137 * reads and writes on Atheros 802.11n PCI devices only. This is required
138 * as the FIFO on these devices can only accept sanely 2 requests.
139 */
140
141static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
142{
143 struct ath_hw *ah = (struct ath_hw *) hw_priv;
144 struct ath_common *common = ath9k_hw_common(ah);
145 struct ath_softc *sc = (struct ath_softc *) common->priv;
146
147 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
148 unsigned long flags;
149 spin_lock_irqsave(&sc->sc_serial_rw, flags);
150 iowrite32(val, sc->mem + reg_offset);
151 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
152 } else
153 iowrite32(val, sc->mem + reg_offset);
154}
155
156static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
157{
158 struct ath_hw *ah = (struct ath_hw *) hw_priv;
159 struct ath_common *common = ath9k_hw_common(ah);
160 struct ath_softc *sc = (struct ath_softc *) common->priv;
161 u32 val;
162
163 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
164 unsigned long flags;
165 spin_lock_irqsave(&sc->sc_serial_rw, flags);
166 val = ioread32(sc->mem + reg_offset);
167 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
168 } else
169 val = ioread32(sc->mem + reg_offset);
170 return val;
171}
172
173static const struct ath_ops ath9k_common_ops = {
174 .read = ath9k_ioread32,
175 .write = ath9k_iowrite32,
176};
177
178/**************************/
179/* Initialization */
180/**************************/
181
182static void setup_ht_cap(struct ath_softc *sc,
183 struct ieee80211_sta_ht_cap *ht_info)
184{
185 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
186 u8 tx_streams, rx_streams;
187
188 ht_info->ht_supported = true;
189 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
190 IEEE80211_HT_CAP_SM_PS |
191 IEEE80211_HT_CAP_SGI_40 |
192 IEEE80211_HT_CAP_DSSSCCK40;
193
194 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
195 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
196
197 /* set up supported mcs set */
198 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
199 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
200 1 : 2;
201 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
202 1 : 2;
203
204 if (tx_streams != rx_streams) {
205 ath_print(common, ATH_DBG_CONFIG,
206 "TX streams %d, RX streams: %d\n",
207 tx_streams, rx_streams);
208 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
209 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
210 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
211 }
212
213 ht_info->mcs.rx_mask[0] = 0xff;
214 if (rx_streams >= 2)
215 ht_info->mcs.rx_mask[1] = 0xff;
216
217 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
218}
219
220static int ath9k_reg_notifier(struct wiphy *wiphy,
221 struct regulatory_request *request)
222{
223 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
224 struct ath_wiphy *aphy = hw->priv;
225 struct ath_softc *sc = aphy->sc;
226 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
227
228 return ath_reg_notifier_apply(wiphy, request, reg);
229}
230
231/*
232 * This function will allocate both the DMA descriptor structure, and the
233 * buffers it contains. These are used to contain the descriptors used
234 * by the system.
235*/
236int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
237 struct list_head *head, const char *name,
238 int nbuf, int ndesc)
239{
240#define DS2PHYS(_dd, _ds) \
241 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
242#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
243#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
244 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
245 struct ath_desc *ds;
246 struct ath_buf *bf;
247 int i, bsize, error;
248
249 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
250 name, nbuf, ndesc);
251
252 INIT_LIST_HEAD(head);
253 /* ath_desc must be a multiple of DWORDs */
254 if ((sizeof(struct ath_desc) % 4) != 0) {
255 ath_print(common, ATH_DBG_FATAL,
256 "ath_desc not DWORD aligned\n");
257 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
258 error = -ENOMEM;
259 goto fail;
260 }
261
262 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
263
264 /*
265 * Need additional DMA memory because we can't use
266 * descriptors that cross the 4K page boundary. Assume
267 * one skipped descriptor per 4K page.
268 */
269 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
270 u32 ndesc_skipped =
271 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
272 u32 dma_len;
273
274 while (ndesc_skipped) {
275 dma_len = ndesc_skipped * sizeof(struct ath_desc);
276 dd->dd_desc_len += dma_len;
277
278 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
279 };
280 }
281
282 /* allocate descriptors */
283 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
284 &dd->dd_desc_paddr, GFP_KERNEL);
285 if (dd->dd_desc == NULL) {
286 error = -ENOMEM;
287 goto fail;
288 }
289 ds = dd->dd_desc;
290 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
291 name, ds, (u32) dd->dd_desc_len,
292 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
293
294 /* allocate buffers */
295 bsize = sizeof(struct ath_buf) * nbuf;
296 bf = kzalloc(bsize, GFP_KERNEL);
297 if (bf == NULL) {
298 error = -ENOMEM;
299 goto fail2;
300 }
301 dd->dd_bufptr = bf;
302
303 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
304 bf->bf_desc = ds;
305 bf->bf_daddr = DS2PHYS(dd, ds);
306
307 if (!(sc->sc_ah->caps.hw_caps &
308 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
309 /*
310 * Skip descriptor addresses which can cause 4KB
311 * boundary crossing (addr + length) with a 32 dword
312 * descriptor fetch.
313 */
314 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
315 BUG_ON((caddr_t) bf->bf_desc >=
316 ((caddr_t) dd->dd_desc +
317 dd->dd_desc_len));
318
319 ds += ndesc;
320 bf->bf_desc = ds;
321 bf->bf_daddr = DS2PHYS(dd, ds);
322 }
323 }
324 list_add_tail(&bf->list, head);
325 }
326 return 0;
327fail2:
328 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
329 dd->dd_desc_paddr);
330fail:
331 memset(dd, 0, sizeof(*dd));
332 return error;
333#undef ATH_DESC_4KB_BOUND_CHECK
334#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
335#undef DS2PHYS
336}
337
338static void ath9k_init_crypto(struct ath_softc *sc)
339{
340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
341 int i = 0;
342
343 /* Get the hardware key cache size. */
344 common->keymax = sc->sc_ah->caps.keycache_size;
345 if (common->keymax > ATH_KEYMAX) {
346 ath_print(common, ATH_DBG_ANY,
347 "Warning, using only %u entries in %u key cache\n",
348 ATH_KEYMAX, common->keymax);
349 common->keymax = ATH_KEYMAX;
350 }
351
352 /*
353 * Reset the key cache since some parts do not
354 * reset the contents on initial power up.
355 */
356 for (i = 0; i < common->keymax; i++)
357 ath9k_hw_keyreset(sc->sc_ah, (u16) i);
358
359 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
360 ATH9K_CIPHER_TKIP, NULL)) {
361 /*
362 * Whether we should enable h/w TKIP MIC.
363 * XXX: if we don't support WME TKIP MIC, then we wouldn't
364 * report WMM capable, so it's always safe to turn on
365 * TKIP MIC in this case.
366 */
367 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL);
368 }
369
370 /*
371 * Check whether the separate key cache entries
372 * are required to handle both tx+rx MIC keys.
373 * With split mic keys the number of stations is limited
374 * to 27 otherwise 59.
375 */
376 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
377 ATH9K_CIPHER_TKIP, NULL)
378 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_CIPHER,
379 ATH9K_CIPHER_MIC, NULL)
380 && ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_TKIP_SPLIT,
381 0, NULL))
382 common->splitmic = 1;
383
384 /* turn on mcast key search if possible */
385 if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
386 (void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
387 1, 1, NULL);
388
389}
390
391static int ath9k_init_btcoex(struct ath_softc *sc)
392{
393 int r, qnum;
394
395 switch (sc->sc_ah->btcoex_hw.scheme) {
396 case ATH_BTCOEX_CFG_NONE:
397 break;
398 case ATH_BTCOEX_CFG_2WIRE:
399 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
400 break;
401 case ATH_BTCOEX_CFG_3WIRE:
402 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
403 r = ath_init_btcoex_timer(sc);
404 if (r)
405 return -1;
406 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
407 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
408 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
409 break;
410 default:
411 WARN_ON(1);
412 break;
413 }
414
415 return 0;
416}
417
418static int ath9k_init_queues(struct ath_softc *sc)
419{
420 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
421 int i = 0;
422
423 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
424 sc->tx.hwq_map[i] = -1;
425
426 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
427 if (sc->beacon.beaconq == -1) {
428 ath_print(common, ATH_DBG_FATAL,
429 "Unable to setup a beacon xmit queue\n");
430 goto err;
431 }
432
433 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
434 if (sc->beacon.cabq == NULL) {
435 ath_print(common, ATH_DBG_FATAL,
436 "Unable to setup CAB xmit queue\n");
437 goto err;
438 }
439
440 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
441 ath_cabq_update(sc);
442
443 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
444 ath_print(common, ATH_DBG_FATAL,
445 "Unable to setup xmit queue for BK traffic\n");
446 goto err;
447 }
448
449 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
450 ath_print(common, ATH_DBG_FATAL,
451 "Unable to setup xmit queue for BE traffic\n");
452 goto err;
453 }
454 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
455 ath_print(common, ATH_DBG_FATAL,
456 "Unable to setup xmit queue for VI traffic\n");
457 goto err;
458 }
459 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
460 ath_print(common, ATH_DBG_FATAL,
461 "Unable to setup xmit queue for VO traffic\n");
462 goto err;
463 }
464
465 return 0;
466
467err:
468 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
469 if (ATH_TXQ_SETUP(sc, i))
470 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
471
472 return -EIO;
473}
474
475static void ath9k_init_channels_rates(struct ath_softc *sc)
476{
477 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
478 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
479 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
480 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
481 ARRAY_SIZE(ath9k_2ghz_chantable);
482 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
483 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
484 ARRAY_SIZE(ath9k_legacy_rates);
485 }
486
487 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
488 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
489 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
490 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
491 ARRAY_SIZE(ath9k_5ghz_chantable);
492 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
493 ath9k_legacy_rates + 4;
494 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
495 ARRAY_SIZE(ath9k_legacy_rates) - 4;
496 }
497}
498
499static void ath9k_init_misc(struct ath_softc *sc)
500{
501 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
502 int i = 0;
503
504 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
505 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
506
507 sc->config.txpowlimit = ATH_TXPOWER_MAX;
508
509 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
510 sc->sc_flags |= SC_OP_TXAGGR;
511 sc->sc_flags |= SC_OP_RXAGGR;
512 }
513
514 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
515 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
516
517 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
518 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
519
520 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
521 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
522
523 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
524
525 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
526 sc->beacon.bslot[i] = NULL;
527 sc->beacon.bslot_aphy[i] = NULL;
528 }
529}
530
531static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
532 const struct ath_bus_ops *bus_ops)
533{
534 struct ath_hw *ah = NULL;
535 struct ath_common *common;
536 int ret = 0, i;
537 int csz = 0;
538
539 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
540 if (!ah)
541 return -ENOMEM;
542
543 ah->hw_version.devid = devid;
544 ah->hw_version.subsysid = subsysid;
545 sc->sc_ah = ah;
546
547 common = ath9k_hw_common(ah);
548 common->ops = &ath9k_common_ops;
549 common->bus_ops = bus_ops;
550 common->ah = ah;
551 common->hw = sc->hw;
552 common->priv = sc;
553 common->debug_mask = ath9k_debug;
554
555 spin_lock_init(&sc->wiphy_lock);
556 spin_lock_init(&sc->sc_resetlock);
557 spin_lock_init(&sc->sc_serial_rw);
558 spin_lock_init(&sc->sc_pm_lock);
559 mutex_init(&sc->mutex);
560 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
561 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
562 (unsigned long)sc);
563
564 /*
565 * Cache line size is used to size and align various
566 * structures used to communicate with the hardware.
567 */
568 ath_read_cachesize(common, &csz);
569 common->cachelsz = csz << 2; /* convert to bytes */
570
571 ret = ath9k_hw_init(ah);
572 if (ret) {
573 ath_print(common, ATH_DBG_FATAL,
574 "Unable to initialize hardware; "
575 "initialization status: %d\n", ret);
576 goto err_hw;
577 }
578
579 ret = ath9k_init_debug(ah);
580 if (ret) {
581 ath_print(common, ATH_DBG_FATAL,
582 "Unable to create debugfs files\n");
583 goto err_debug;
584 }
585
586 ret = ath9k_init_queues(sc);
587 if (ret)
588 goto err_queues;
589
590 ret = ath9k_init_btcoex(sc);
591 if (ret)
592 goto err_btcoex;
593
594 ath9k_init_crypto(sc);
595 ath9k_init_channels_rates(sc);
596 ath9k_init_misc(sc);
597
598 return 0;
599
600err_btcoex:
601 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
602 if (ATH_TXQ_SETUP(sc, i))
603 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
604err_queues:
605 ath9k_exit_debug(ah);
606err_debug:
607 ath9k_hw_deinit(ah);
608err_hw:
609 tasklet_kill(&sc->intr_tq);
610 tasklet_kill(&sc->bcon_tasklet);
611
612 kfree(ah);
613 sc->sc_ah = NULL;
614
615 return ret;
616}
617
618void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
619{
620 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
621
622 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
623 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
624 IEEE80211_HW_SIGNAL_DBM |
625 IEEE80211_HW_SUPPORTS_PS |
626 IEEE80211_HW_PS_NULLFUNC_STACK |
627 IEEE80211_HW_SPECTRUM_MGMT |
628 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
629
630 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
631 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
632
633 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
634 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
635
636 hw->wiphy->interface_modes =
637 BIT(NL80211_IFTYPE_AP) |
638 BIT(NL80211_IFTYPE_STATION) |
639 BIT(NL80211_IFTYPE_ADHOC) |
640 BIT(NL80211_IFTYPE_MESH_POINT);
641
642 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
643
644 hw->queues = 4;
645 hw->max_rates = 4;
646 hw->channel_change_time = 5000;
647 hw->max_listen_interval = 10;
648 hw->max_rate_tries = 10;
649 hw->sta_data_size = sizeof(struct ath_node);
650 hw->vif_data_size = sizeof(struct ath_vif);
651
652 hw->rate_control_algorithm = "ath9k_rate_control";
653
654 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
655 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
656 &sc->sbands[IEEE80211_BAND_2GHZ];
657 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
658 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
659 &sc->sbands[IEEE80211_BAND_5GHZ];
660
661 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
662 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
663 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
664 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
665 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
666 }
667
668 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
669}
670
671int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
672 const struct ath_bus_ops *bus_ops)
673{
674 struct ieee80211_hw *hw = sc->hw;
675 struct ath_common *common;
676 struct ath_hw *ah;
677 int error = 0;
678 struct ath_regulatory *reg;
679
680 /* Bring up device */
681 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
682 if (error != 0)
683 goto error_init;
684
685 ah = sc->sc_ah;
686 common = ath9k_hw_common(ah);
687 ath9k_set_hw_capab(sc, hw);
688
689 /* Initialize regulatory */
690 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
691 ath9k_reg_notifier);
692 if (error)
693 goto error_regd;
694
695 reg = &common->regulatory;
696
697 /* Setup TX DMA */
698 error = ath_tx_init(sc, ATH_TXBUF);
699 if (error != 0)
700 goto error_tx;
701
702 /* Setup RX DMA */
703 error = ath_rx_init(sc, ATH_RXBUF);
704 if (error != 0)
705 goto error_rx;
706
707 /* Register with mac80211 */
708 error = ieee80211_register_hw(hw);
709 if (error)
710 goto error_register;
711
712 /* Handle world regulatory */
713 if (!ath_is_world_regd(reg)) {
714 error = regulatory_hint(hw->wiphy, reg->alpha2);
715 if (error)
716 goto error_world;
717 }
718
719 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
720 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
721 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
722
723 ath_init_leds(sc);
724 ath_start_rfkill_poll(sc);
725
726 return 0;
727
728error_world:
729 ieee80211_unregister_hw(hw);
730error_register:
731 ath_rx_cleanup(sc);
732error_rx:
733 ath_tx_cleanup(sc);
734error_tx:
735 /* Nothing */
736error_regd:
737 ath9k_deinit_softc(sc);
738error_init:
739 return error;
740}
741
742/*****************************/
743/* De-Initialization */
744/*****************************/
745
746static void ath9k_deinit_softc(struct ath_softc *sc)
747{
748 int i = 0;
749
750 if ((sc->btcoex.no_stomp_timer) &&
751 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
752 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
753
754 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
755 if (ATH_TXQ_SETUP(sc, i))
756 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
757
758 ath9k_exit_debug(sc->sc_ah);
759 ath9k_hw_deinit(sc->sc_ah);
760
761 tasklet_kill(&sc->intr_tq);
762 tasklet_kill(&sc->bcon_tasklet);
763}
764
765void ath9k_deinit_device(struct ath_softc *sc)
766{
767 struct ieee80211_hw *hw = sc->hw;
768 int i = 0;
769
770 ath9k_ps_wakeup(sc);
771
772 wiphy_rfkill_stop_polling(sc->hw->wiphy);
773 ath_deinit_leds(sc);
774
775 for (i = 0; i < sc->num_sec_wiphy; i++) {
776 struct ath_wiphy *aphy = sc->sec_wiphy[i];
777 if (aphy == NULL)
778 continue;
779 sc->sec_wiphy[i] = NULL;
780 ieee80211_unregister_hw(aphy->hw);
781 ieee80211_free_hw(aphy->hw);
782 }
783 kfree(sc->sec_wiphy);
784
785 ieee80211_unregister_hw(hw);
786 ath_rx_cleanup(sc);
787 ath_tx_cleanup(sc);
788 ath9k_deinit_softc(sc);
789}
790
791void ath_descdma_cleanup(struct ath_softc *sc,
792 struct ath_descdma *dd,
793 struct list_head *head)
794{
795 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
796 dd->dd_desc_paddr);
797
798 INIT_LIST_HEAD(head);
799 kfree(dd->dd_bufptr);
800 memset(dd, 0, sizeof(*dd));
801}
802
803/************************/
804/* Module Hooks */
805/************************/
806
807static int __init ath9k_init(void)
808{
809 int error;
810
811 /* Register rate control algorithm */
812 error = ath_rate_control_register();
813 if (error != 0) {
814 printk(KERN_ERR
815 "ath9k: Unable to register rate control "
816 "algorithm: %d\n",
817 error);
818 goto err_out;
819 }
820
821 error = ath9k_debug_create_root();
822 if (error) {
823 printk(KERN_ERR
824 "ath9k: Unable to create debugfs root: %d\n",
825 error);
826 goto err_rate_unregister;
827 }
828
829 error = ath_pci_init();
830 if (error < 0) {
831 printk(KERN_ERR
832 "ath9k: No PCI devices found, driver not installed.\n");
833 error = -ENODEV;
834 goto err_remove_root;
835 }
836
837 error = ath_ahb_init();
838 if (error < 0) {
839 error = -ENODEV;
840 goto err_pci_exit;
841 }
842
843 return 0;
844
845 err_pci_exit:
846 ath_pci_exit();
847
848 err_remove_root:
849 ath9k_debug_remove_root();
850 err_rate_unregister:
851 ath_rate_control_unregister();
852 err_out:
853 return error;
854}
855module_init(ath9k_init);
856
857static void __exit ath9k_exit(void)
858{
859 ath_ahb_exit();
860 ath_pci_exit();
861 ath9k_debug_remove_root();
862 ath_rate_control_unregister();
863 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
864}
865module_exit(ath9k_exit);
diff --git a/drivers/net/wireless/ath/ath9k/initvals.h b/drivers/net/wireless/ath/ath9k/initvals.h
index 8622265a030a..8a3bf3ab998d 100644
--- a/drivers/net/wireless/ath/ath9k/initvals.h
+++ b/drivers/net/wireless/ath/ath9k/initvals.h
@@ -21,6 +21,8 @@ static const u32 ar5416Modes[][6] = {
21 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, 21 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
22 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, 22 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
23 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf }, 23 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
25 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
24 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 26 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
25 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 27 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
26 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 28 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
@@ -31,11 +33,11 @@ static const u32 ar5416Modes[][6] = {
31 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 33 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
32 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 34 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
33 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 35 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
34 { 0x00009850, 0x6c48b4e0, 0x6c48b4e0, 0x6c48b0de, 0x6c48b0de, 0x6c48b0de }, 36 { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
35 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, 37 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
36 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e }, 38 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
37 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 }, 39 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
38 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 40 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
39 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 }, 41 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
40 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, 42 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
41 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 43 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
@@ -46,10 +48,10 @@ static const u32 ar5416Modes[][6] = {
46 { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, 48 { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
47 { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, 49 { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
48 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 }, 50 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
49 { 0x0000c9bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 }, 51 { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
50 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, 52 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
51 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 53 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
52 { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c }, 54 { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
53 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 55 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
54 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 56 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
55 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 57 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -199,7 +201,6 @@ static const u32 ar5416Common[][2] = {
199 { 0x00008110, 0x00000168 }, 201 { 0x00008110, 0x00000168 },
200 { 0x00008118, 0x000100aa }, 202 { 0x00008118, 0x000100aa },
201 { 0x0000811c, 0x00003210 }, 203 { 0x0000811c, 0x00003210 },
202 { 0x00008120, 0x08f04800 },
203 { 0x00008124, 0x00000000 }, 204 { 0x00008124, 0x00000000 },
204 { 0x00008128, 0x00000000 }, 205 { 0x00008128, 0x00000000 },
205 { 0x0000812c, 0x00000000 }, 206 { 0x0000812c, 0x00000000 },
@@ -215,7 +216,6 @@ static const u32 ar5416Common[][2] = {
215 { 0x00008178, 0x00000100 }, 216 { 0x00008178, 0x00000100 },
216 { 0x0000817c, 0x00000000 }, 217 { 0x0000817c, 0x00000000 },
217 { 0x000081c4, 0x00000000 }, 218 { 0x000081c4, 0x00000000 },
218 { 0x000081d0, 0x00003210 },
219 { 0x000081ec, 0x00000000 }, 219 { 0x000081ec, 0x00000000 },
220 { 0x000081f0, 0x00000000 }, 220 { 0x000081f0, 0x00000000 },
221 { 0x000081f4, 0x00000000 }, 221 { 0x000081f4, 0x00000000 },
@@ -246,6 +246,7 @@ static const u32 ar5416Common[][2] = {
246 { 0x00008258, 0x00000000 }, 246 { 0x00008258, 0x00000000 },
247 { 0x0000825c, 0x400000ff }, 247 { 0x0000825c, 0x400000ff },
248 { 0x00008260, 0x00080922 }, 248 { 0x00008260, 0x00080922 },
249 { 0x00008264, 0xa8000010 },
249 { 0x00008270, 0x00000000 }, 250 { 0x00008270, 0x00000000 },
250 { 0x00008274, 0x40000000 }, 251 { 0x00008274, 0x40000000 },
251 { 0x00008278, 0x003e4180 }, 252 { 0x00008278, 0x003e4180 },
@@ -406,9 +407,9 @@ static const u32 ar5416Common[][2] = {
406 { 0x0000a25c, 0x0f0f0f01 }, 407 { 0x0000a25c, 0x0f0f0f01 },
407 { 0x0000a260, 0xdfa91f01 }, 408 { 0x0000a260, 0xdfa91f01 },
408 { 0x0000a268, 0x00000000 }, 409 { 0x0000a268, 0x00000000 },
409 { 0x0000a26c, 0x0ebae9c6 }, 410 { 0x0000a26c, 0x0e79e5c6 },
410 { 0x0000b26c, 0x0ebae9c6 }, 411 { 0x0000b26c, 0x0e79e5c6 },
411 { 0x0000c26c, 0x0ebae9c6 }, 412 { 0x0000c26c, 0x0e79e5c6 },
412 { 0x0000d270, 0x00820820 }, 413 { 0x0000d270, 0x00820820 },
413 { 0x0000a278, 0x1ce739ce }, 414 { 0x0000a278, 0x1ce739ce },
414 { 0x0000a27c, 0x051701ce }, 415 { 0x0000a27c, 0x051701ce },
@@ -2551,26 +2552,27 @@ static const u32 ar9280Modes_9280_2[][6] = {
2551 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, 2552 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
2552 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 2553 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
2553 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 2554 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
2554 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 2555 { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
2555 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 2556 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
2556 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 2557 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2557 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 2558 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
2558 { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e }, 2559 { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
2559 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 }, 2560 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
2560 { 0x00009850, 0x6c4000e2, 0x6c4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 }, 2561 { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
2561 { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e }, 2562 { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
2562 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x3139605e, 0x31395d5e, 0x31395d5e }, 2563 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
2563 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 }, 2564 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
2564 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 2565 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
2565 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, 2566 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
2566 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, 2567 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
2567 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 2568 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
2568 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 2569 { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
2569 { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d }, 2570 { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
2570 { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 }, 2571 { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
2571 { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, 2572 { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
2572 { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, 2573 { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
2573 { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 }, 2574 { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
2575 { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
2574 { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c }, 2576 { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
2575 { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 }, 2577 { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
2576 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 2578 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
@@ -2585,8 +2587,10 @@ static const u32 ar9280Modes_9280_2[][6] = {
2585 { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 }, 2587 { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
2586 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, 2588 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
2587 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, 2589 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
2590 { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
2588 { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 }, 2591 { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
2589 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 2592 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
2593 { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
2590 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 2594 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2591 { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 }, 2595 { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
2592}; 2596};
@@ -2813,7 +2817,6 @@ static const u32 ar9280Common_9280_2[][2] = {
2813 { 0x00009958, 0x2108ecff }, 2817 { 0x00009958, 0x2108ecff },
2814 { 0x00009940, 0x14750604 }, 2818 { 0x00009940, 0x14750604 },
2815 { 0x0000c95c, 0x004b6a8e }, 2819 { 0x0000c95c, 0x004b6a8e },
2816 { 0x0000c968, 0x000003ce },
2817 { 0x00009970, 0x190fb515 }, 2820 { 0x00009970, 0x190fb515 },
2818 { 0x00009974, 0x00000000 }, 2821 { 0x00009974, 0x00000000 },
2819 { 0x00009978, 0x00000001 }, 2822 { 0x00009978, 0x00000001 },
@@ -2849,7 +2852,6 @@ static const u32 ar9280Common_9280_2[][2] = {
2849 { 0x0000a22c, 0x233f7180 }, 2852 { 0x0000a22c, 0x233f7180 },
2850 { 0x0000a234, 0x20202020 }, 2853 { 0x0000a234, 0x20202020 },
2851 { 0x0000a238, 0x20202020 }, 2854 { 0x0000a238, 0x20202020 },
2852 { 0x0000a23c, 0x13c88000 },
2853 { 0x0000a240, 0x38490a20 }, 2855 { 0x0000a240, 0x38490a20 },
2854 { 0x0000a244, 0x00007bb6 }, 2856 { 0x0000a244, 0x00007bb6 },
2855 { 0x0000a248, 0x0fff3ffc }, 2857 { 0x0000a248, 0x0fff3ffc },
@@ -2859,8 +2861,8 @@ static const u32 ar9280Common_9280_2[][2] = {
2859 { 0x0000a25c, 0x0f0f0f01 }, 2861 { 0x0000a25c, 0x0f0f0f01 },
2860 { 0x0000a260, 0xdfa91f01 }, 2862 { 0x0000a260, 0xdfa91f01 },
2861 { 0x0000a268, 0x00000000 }, 2863 { 0x0000a268, 0x00000000 },
2862 { 0x0000a26c, 0x0ebae9c6 }, 2864 { 0x0000a26c, 0x0e79e5c6 },
2863 { 0x0000b26c, 0x0ebae9c6 }, 2865 { 0x0000b26c, 0x0e79e5c6 },
2864 { 0x0000d270, 0x00820820 }, 2866 { 0x0000d270, 0x00820820 },
2865 { 0x0000a278, 0x1ce739ce }, 2867 { 0x0000a278, 0x1ce739ce },
2866 { 0x0000d35c, 0x07ffffef }, 2868 { 0x0000d35c, 0x07ffffef },
@@ -2874,7 +2876,6 @@ static const u32 ar9280Common_9280_2[][2] = {
2874 { 0x0000d37c, 0x7fffffe2 }, 2876 { 0x0000d37c, 0x7fffffe2 },
2875 { 0x0000d380, 0x7f3c7bba }, 2877 { 0x0000d380, 0x7f3c7bba },
2876 { 0x0000d384, 0xf3307ff0 }, 2878 { 0x0000d384, 0xf3307ff0 },
2877 { 0x0000a388, 0x0c000000 },
2878 { 0x0000a38c, 0x20202020 }, 2879 { 0x0000a38c, 0x20202020 },
2879 { 0x0000a390, 0x20202020 }, 2880 { 0x0000a390, 0x20202020 },
2880 { 0x0000a394, 0x1ce739ce }, 2881 { 0x0000a394, 0x1ce739ce },
@@ -2940,7 +2941,7 @@ static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
2940 { 0x0000801c, 0x148ec02b, 0x148ec057 }, 2941 { 0x0000801c, 0x148ec02b, 0x148ec057 },
2941 { 0x00008318, 0x000044c0, 0x00008980 }, 2942 { 0x00008318, 0x000044c0, 0x00008980 },
2942 { 0x00009820, 0x02020200, 0x02020200 }, 2943 { 0x00009820, 0x02020200, 0x02020200 },
2943 { 0x00009824, 0x00000f0f, 0x00000f0f }, 2944 { 0x00009824, 0x01000f0f, 0x01000f0f },
2944 { 0x00009828, 0x0b020001, 0x0b020001 }, 2945 { 0x00009828, 0x0b020001, 0x0b020001 },
2945 { 0x00009834, 0x00000f0f, 0x00000f0f }, 2946 { 0x00009834, 0x00000f0f, 0x00000f0f },
2946 { 0x00009844, 0x03721821, 0x03721821 }, 2947 { 0x00009844, 0x03721821, 0x03721821 },
@@ -3348,6 +3349,8 @@ static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
3348}; 3349};
3349 3350
3350static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = { 3351static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
3352 { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3353 { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
3351 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3354 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3352 { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 }, 3355 { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
3353 { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 }, 3356 { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
@@ -3376,11 +3379,11 @@ static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
3376 { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 }, 3379 { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
3377 { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 }, 3380 { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
3378 { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 }, 3381 { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
3379 { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3380 { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
3381}; 3382};
3382 3383
3383static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = { 3384static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
3385 { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3386 { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
3384 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3387 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3385 { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 }, 3388 { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
3386 { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 }, 3389 { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
@@ -3409,8 +3412,6 @@ static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
3409 { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 }, 3412 { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
3410 { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 }, 3413 { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
3411 { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 }, 3414 { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
3412 { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3413 { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
3414}; 3415};
3415 3416
3416static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = { 3417static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
@@ -5918,9 +5919,6 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
5918 { 0x000099ec, 0x0cc80caa }, 5919 { 0x000099ec, 0x0cc80caa },
5919 { 0x000099f0, 0x00000000 }, 5920 { 0x000099f0, 0x00000000 },
5920 { 0x000099fc, 0x00001042 }, 5921 { 0x000099fc, 0x00001042 },
5921 { 0x0000a1f4, 0x00fffeff },
5922 { 0x0000a1f8, 0x00f5f9ff },
5923 { 0x0000a1fc, 0xb79f6427 },
5924 { 0x0000a208, 0x803e4788 }, 5922 { 0x0000a208, 0x803e4788 },
5925 { 0x0000a210, 0x4080a333 }, 5923 { 0x0000a210, 0x4080a333 },
5926 { 0x0000a214, 0x40206c10 }, 5924 { 0x0000a214, 0x40206c10 },
@@ -5980,7 +5978,7 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
5980 { 0x0000b3f4, 0x00000000 }, 5978 { 0x0000b3f4, 0x00000000 },
5981 { 0x0000a7d8, 0x000003f1 }, 5979 { 0x0000a7d8, 0x000003f1 },
5982 { 0x00007800, 0x00000800 }, 5980 { 0x00007800, 0x00000800 },
5983 { 0x00007804, 0x6c35ffc2 }, 5981 { 0x00007804, 0x6c35ffd2 },
5984 { 0x00007808, 0x6db6c000 }, 5982 { 0x00007808, 0x6db6c000 },
5985 { 0x0000780c, 0x6db6cb30 }, 5983 { 0x0000780c, 0x6db6cb30 },
5986 { 0x00007810, 0x6db6cb6c }, 5984 { 0x00007810, 0x6db6cb6c },
@@ -6000,7 +5998,7 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
6000 { 0x00007848, 0x934934a8 }, 5998 { 0x00007848, 0x934934a8 },
6001 { 0x00007850, 0x00000000 }, 5999 { 0x00007850, 0x00000000 },
6002 { 0x00007854, 0x00000800 }, 6000 { 0x00007854, 0x00000800 },
6003 { 0x00007858, 0x6c35ffc2 }, 6001 { 0x00007858, 0x6c35ffd2 },
6004 { 0x0000785c, 0x6db6c000 }, 6002 { 0x0000785c, 0x6db6c000 },
6005 { 0x00007860, 0x6db6cb30 }, 6003 { 0x00007860, 0x6db6cb30 },
6006 { 0x00007864, 0x6db6cb6c }, 6004 { 0x00007864, 0x6db6cb6c },
@@ -6027,6 +6025,22 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
6027 { 0x000078b8, 0x2a850160 }, 6025 { 0x000078b8, 0x2a850160 },
6028}; 6026};
6029 6027
6028/*
6029 * For Japanese regulatory requirements, 2484 MHz requires the following three
6030 * registers be programmed differently from the channel between 2412 and 2472 MHz.
6031 */
6032static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
6033 { 0x0000a1f4, 0x00fffeff },
6034 { 0x0000a1f8, 0x00f5f9ff },
6035 { 0x0000a1fc, 0xb79f6427 },
6036};
6037
6038static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
6039 { 0x0000a1f4, 0x00000000 },
6040 { 0x0000a1f8, 0xefff0301 },
6041 { 0x0000a1fc, 0xca9228ee },
6042};
6043
6030static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = { 6044static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
6031 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 6045 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
6032 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 6046 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -6365,8 +6379,8 @@ static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
6365}; 6379};
6366 6380
6367 6381
6368/* AR9271 initialization values automaticaly created: 03/23/09 */ 6382/* AR9271 initialization values automaticaly created: 06/04/09 */
6369static const u_int32_t ar9271Modes_9271_1_0[][6] = { 6383static const u_int32_t ar9271Modes_9271[][6] = {
6370 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 6384 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6371 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 6385 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6372 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 6386 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -6376,8 +6390,8 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6376 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, 6390 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
6377 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 6391 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
6378 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 6392 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
6379 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6393 { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
6380 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 6394 { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
6381 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6395 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6382 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 6396 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
6383 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e }, 6397 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
@@ -6391,6 +6405,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6391 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 6405 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
6392 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, 6406 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
6393 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, 6407 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
6408 { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
6394 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 6409 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
6395 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 6410 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
6396 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d }, 6411 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
@@ -6401,7 +6416,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6401 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, 6416 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
6402 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 6417 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
6403 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 6418 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
6404 { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 }, 6419 { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
6405 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 6420 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
6406 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 6421 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
6407 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 6422 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -6690,7 +6705,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6690 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 6705 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6691}; 6706};
6692 6707
6693static const u_int32_t ar9271Common_9271_1_0[][2] = { 6708static const u_int32_t ar9271Common_9271[][2] = {
6694 { 0x0000000c, 0x00000000 }, 6709 { 0x0000000c, 0x00000000 },
6695 { 0x00000030, 0x00020045 }, 6710 { 0x00000030, 0x00020045 },
6696 { 0x00000034, 0x00000005 }, 6711 { 0x00000034, 0x00000005 },
@@ -6786,7 +6801,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6786 { 0x0000803c, 0x00000000 }, 6801 { 0x0000803c, 0x00000000 },
6787 { 0x00008048, 0x00000000 }, 6802 { 0x00008048, 0x00000000 },
6788 { 0x00008054, 0x00000000 }, 6803 { 0x00008054, 0x00000000 },
6789 { 0x00008058, 0x02000000 }, 6804 { 0x00008058, 0x00000000 },
6790 { 0x0000805c, 0x000fc78f }, 6805 { 0x0000805c, 0x000fc78f },
6791 { 0x00008060, 0x0000000f }, 6806 { 0x00008060, 0x0000000f },
6792 { 0x00008064, 0x00000000 }, 6807 { 0x00008064, 0x00000000 },
@@ -6817,7 +6832,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6817 { 0x00008110, 0x00000168 }, 6832 { 0x00008110, 0x00000168 },
6818 { 0x00008118, 0x000100aa }, 6833 { 0x00008118, 0x000100aa },
6819 { 0x0000811c, 0x00003210 }, 6834 { 0x0000811c, 0x00003210 },
6820 { 0x00008120, 0x08f04814 }, 6835 { 0x00008120, 0x08f04810 },
6821 { 0x00008124, 0x00000000 }, 6836 { 0x00008124, 0x00000000 },
6822 { 0x00008128, 0x00000000 }, 6837 { 0x00008128, 0x00000000 },
6823 { 0x0000812c, 0x00000000 }, 6838 { 0x0000812c, 0x00000000 },
@@ -6864,7 +6879,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6864 { 0x00008258, 0x00000000 }, 6879 { 0x00008258, 0x00000000 },
6865 { 0x0000825c, 0x400000ff }, 6880 { 0x0000825c, 0x400000ff },
6866 { 0x00008260, 0x00080922 }, 6881 { 0x00008260, 0x00080922 },
6867 { 0x00008264, 0xa8a00010 }, 6882 { 0x00008264, 0x88a00010 },
6868 { 0x00008270, 0x00000000 }, 6883 { 0x00008270, 0x00000000 },
6869 { 0x00008274, 0x40000000 }, 6884 { 0x00008274, 0x40000000 },
6870 { 0x00008278, 0x003e4180 }, 6885 { 0x00008278, 0x003e4180 },
@@ -6896,7 +6911,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6896 { 0x00007814, 0x924934a8 }, 6911 { 0x00007814, 0x924934a8 },
6897 { 0x0000781c, 0x00000000 }, 6912 { 0x0000781c, 0x00000000 },
6898 { 0x00007820, 0x00000c04 }, 6913 { 0x00007820, 0x00000c04 },
6899 { 0x00007824, 0x00d86bff }, 6914 { 0x00007824, 0x00d8abff },
6900 { 0x00007828, 0x66964300 }, 6915 { 0x00007828, 0x66964300 },
6901 { 0x0000782c, 0x8db6d961 }, 6916 { 0x0000782c, 0x8db6d961 },
6902 { 0x00007830, 0x8db6d96c }, 6917 { 0x00007830, 0x8db6d96c },
@@ -6930,7 +6945,6 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6930 { 0x00009904, 0x00000000 }, 6945 { 0x00009904, 0x00000000 },
6931 { 0x00009908, 0x00000000 }, 6946 { 0x00009908, 0x00000000 },
6932 { 0x0000990c, 0x00000000 }, 6947 { 0x0000990c, 0x00000000 },
6933 { 0x00009910, 0x30002310 },
6934 { 0x0000991c, 0x10000fff }, 6948 { 0x0000991c, 0x10000fff },
6935 { 0x00009920, 0x04900000 }, 6949 { 0x00009920, 0x04900000 },
6936 { 0x00009928, 0x00000001 }, 6950 { 0x00009928, 0x00000001 },
@@ -6944,7 +6958,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6944 { 0x00009954, 0x5f3ca3de }, 6958 { 0x00009954, 0x5f3ca3de },
6945 { 0x00009958, 0x0108ecff }, 6959 { 0x00009958, 0x0108ecff },
6946 { 0x00009968, 0x000003ce }, 6960 { 0x00009968, 0x000003ce },
6947 { 0x00009970, 0x192bb515 }, 6961 { 0x00009970, 0x192bb514 },
6948 { 0x00009974, 0x00000000 }, 6962 { 0x00009974, 0x00000000 },
6949 { 0x00009978, 0x00000001 }, 6963 { 0x00009978, 0x00000001 },
6950 { 0x0000997c, 0x00000000 }, 6964 { 0x0000997c, 0x00000000 },
@@ -7031,3 +7045,8 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
7031 { 0x0000d380, 0x7f3c7bba }, 7045 { 0x0000d380, 0x7f3c7bba },
7032 { 0x0000d384, 0xf3307ff0 }, 7046 { 0x0000d384, 0xf3307ff0 },
7033}; 7047};
7048
7049static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
7050 { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
7051 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7052};
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 800bfab94635..efc420cd42bf 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -14,16 +14,16 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
21{ 21{
22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 22 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->txurn_interrupt_mask); 26 ah->txurn_interrupt_mask);
27 27
28 REG_WRITE(ah, AR_IMR_S0, 28 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) 29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
@@ -39,17 +39,21 @@ u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
39{ 39{
40 return REG_READ(ah, AR_QTXDP(q)); 40 return REG_READ(ah, AR_QTXDP(q));
41} 41}
42EXPORT_SYMBOL(ath9k_hw_gettxbuf);
42 43
43void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) 44void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
44{ 45{
45 REG_WRITE(ah, AR_QTXDP(q), txdp); 46 REG_WRITE(ah, AR_QTXDP(q), txdp);
46} 47}
48EXPORT_SYMBOL(ath9k_hw_puttxbuf);
47 49
48void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 50void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
49{ 51{
50 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q); 52 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
53 "Enable TXE on queue: %u\n", q);
51 REG_WRITE(ah, AR_Q_TXE, 1 << q); 54 REG_WRITE(ah, AR_Q_TXE, 1 << q);
52} 55}
56EXPORT_SYMBOL(ath9k_hw_txstart);
53 57
54u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) 58u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
55{ 59{
@@ -64,13 +68,39 @@ u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
64 68
65 return npend; 69 return npend;
66} 70}
71EXPORT_SYMBOL(ath9k_hw_numtxpending);
67 72
73/**
74 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
75 *
76 * @ah: atheros hardware struct
77 * @bIncTrigLevel: whether or not the frame trigger level should be updated
78 *
79 * The frame trigger level specifies the minimum number of bytes,
80 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
81 * before the PCU will initiate sending the frame on the air. This can
82 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
83 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
84 * first)
85 *
86 * Caution must be taken to ensure to set the frame trigger level based
87 * on the DMA request size. For example if the DMA request size is set to
88 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
89 * there need to be enough space in the tx FIFO for the requested transfer
90 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
91 * the threshold to a value beyond 6, then the transmit will hang.
92 *
93 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
94 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
95 * there is a hardware issue which forces us to use 2 KB instead so the
96 * frame trigger level must not exceed 2 KB for these chipsets.
97 */
68bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) 98bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
69{ 99{
70 u32 txcfg, curLevel, newLevel; 100 u32 txcfg, curLevel, newLevel;
71 enum ath9k_int omask; 101 enum ath9k_int omask;
72 102
73 if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD) 103 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
74 return false; 104 return false;
75 105
76 omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL); 106 omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL);
@@ -79,7 +109,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
79 curLevel = MS(txcfg, AR_FTRIG); 109 curLevel = MS(txcfg, AR_FTRIG);
80 newLevel = curLevel; 110 newLevel = curLevel;
81 if (bIncTrigLevel) { 111 if (bIncTrigLevel) {
82 if (curLevel < MAX_TX_FIFO_THRESHOLD) 112 if (curLevel < ah->config.max_txtrig_level)
83 newLevel++; 113 newLevel++;
84 } else if (curLevel > MIN_TX_FIFO_THRESHOLD) 114 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
85 newLevel--; 115 newLevel--;
@@ -93,27 +123,28 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
93 123
94 return newLevel != curLevel; 124 return newLevel != curLevel;
95} 125}
126EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
96 127
97bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) 128bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
98{ 129{
99#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 130#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
100#define ATH9K_TIME_QUANTUM 100 /* usec */ 131#define ATH9K_TIME_QUANTUM 100 /* usec */
101 132 struct ath_common *common = ath9k_hw_common(ah);
102 struct ath9k_hw_capabilities *pCap = &ah->caps; 133 struct ath9k_hw_capabilities *pCap = &ah->caps;
103 struct ath9k_tx_queue_info *qi; 134 struct ath9k_tx_queue_info *qi;
104 u32 tsfLow, j, wait; 135 u32 tsfLow, j, wait;
105 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 136 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
106 137
107 if (q >= pCap->total_queues) { 138 if (q >= pCap->total_queues) {
108 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " 139 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
109 "invalid queue: %u\n", q); 140 "invalid queue: %u\n", q);
110 return false; 141 return false;
111 } 142 }
112 143
113 qi = &ah->txq[q]; 144 qi = &ah->txq[q];
114 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 145 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
115 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " 146 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
116 "inactive queue: %u\n", q); 147 "inactive queue: %u\n", q);
117 return false; 148 return false;
118 } 149 }
119 150
@@ -126,9 +157,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
126 } 157 }
127 158
128 if (ath9k_hw_numtxpending(ah, q)) { 159 if (ath9k_hw_numtxpending(ah, q)) {
129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 160 ath_print(common, ATH_DBG_QUEUE,
130 "%s: Num of pending TX Frames %d on Q %d\n", 161 "%s: Num of pending TX Frames %d on Q %d\n",
131 __func__, ath9k_hw_numtxpending(ah, q), q); 162 __func__, ath9k_hw_numtxpending(ah, q), q);
132 163
133 for (j = 0; j < 2; j++) { 164 for (j = 0; j < 2; j++) {
134 tsfLow = REG_READ(ah, AR_TSF_L32); 165 tsfLow = REG_READ(ah, AR_TSF_L32);
@@ -142,9 +173,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
142 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) 173 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
143 break; 174 break;
144 175
145 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 176 ath_print(common, ATH_DBG_QUEUE,
146 "TSF has moved while trying to set " 177 "TSF has moved while trying to set "
147 "quiet time TSF: 0x%08x\n", tsfLow); 178 "quiet time TSF: 0x%08x\n", tsfLow);
148 } 179 }
149 180
150 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 181 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -155,9 +186,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
155 wait = wait_time; 186 wait = wait_time;
156 while (ath9k_hw_numtxpending(ah, q)) { 187 while (ath9k_hw_numtxpending(ah, q)) {
157 if ((--wait) == 0) { 188 if ((--wait) == 0) {
158 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 189 ath_print(common, ATH_DBG_FATAL,
159 "Failed to stop TX DMA in 100 " 190 "Failed to stop TX DMA in 100 "
160 "msec after killing last frame\n"); 191 "msec after killing last frame\n");
161 break; 192 break;
162 } 193 }
163 udelay(ATH9K_TIME_QUANTUM); 194 udelay(ATH9K_TIME_QUANTUM);
@@ -172,6 +203,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
172#undef ATH9K_TX_STOP_DMA_TIMEOUT 203#undef ATH9K_TX_STOP_DMA_TIMEOUT
173#undef ATH9K_TIME_QUANTUM 204#undef ATH9K_TIME_QUANTUM
174} 205}
206EXPORT_SYMBOL(ath9k_hw_stoptxdma);
175 207
176void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, 208void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
177 u32 segLen, bool firstSeg, 209 u32 segLen, bool firstSeg,
@@ -198,6 +230,7 @@ void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
198 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 230 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
199 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 231 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
200} 232}
233EXPORT_SYMBOL(ath9k_hw_filltxdesc);
201 234
202void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds) 235void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
203{ 236{
@@ -209,6 +242,7 @@ void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
209 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 242 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
210 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 243 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
211} 244}
245EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
212 246
213int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds) 247int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
214{ 248{
@@ -222,6 +256,8 @@ int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
222 ds->ds_txstat.ts_status = 0; 256 ds->ds_txstat.ts_status = 0;
223 ds->ds_txstat.ts_flags = 0; 257 ds->ds_txstat.ts_flags = 0;
224 258
259 if (ads->ds_txstatus1 & AR_FrmXmitOK)
260 ds->ds_txstat.ts_status |= ATH9K_TX_ACKED;
225 if (ads->ds_txstatus1 & AR_ExcessiveRetries) 261 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
226 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY; 262 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
227 if (ads->ds_txstatus1 & AR_Filtered) 263 if (ads->ds_txstatus1 & AR_Filtered)
@@ -284,6 +320,7 @@ int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
284 320
285 return 0; 321 return 0;
286} 322}
323EXPORT_SYMBOL(ath9k_hw_txprocdesc);
287 324
288void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, 325void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
289 u32 pktLen, enum ath9k_pkt_type type, u32 txPower, 326 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
@@ -319,6 +356,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
319 ads->ds_ctl11 = 0; 356 ads->ds_ctl11 = 0;
320 } 357 }
321} 358}
359EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
322 360
323void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, 361void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
324 struct ath_desc *lastds, 362 struct ath_desc *lastds,
@@ -374,6 +412,7 @@ void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
374 last_ads->ds_ctl2 = ads->ds_ctl2; 412 last_ads->ds_ctl2 = ads->ds_ctl2;
375 last_ads->ds_ctl3 = ads->ds_ctl3; 413 last_ads->ds_ctl3 = ads->ds_ctl3;
376} 414}
415EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
377 416
378void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, 417void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
379 u32 aggrLen) 418 u32 aggrLen)
@@ -384,6 +423,7 @@ void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
384 ads->ds_ctl6 &= ~AR_AggrLen; 423 ads->ds_ctl6 &= ~AR_AggrLen;
385 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); 424 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
386} 425}
426EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
387 427
388void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, 428void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
389 u32 numDelims) 429 u32 numDelims)
@@ -398,6 +438,7 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
398 ctl6 |= SM(numDelims, AR_PadDelim); 438 ctl6 |= SM(numDelims, AR_PadDelim);
399 ads->ds_ctl6 = ctl6; 439 ads->ds_ctl6 = ctl6;
400} 440}
441EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
401 442
402void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds) 443void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
403{ 444{
@@ -407,6 +448,7 @@ void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
407 ads->ds_ctl1 &= ~AR_MoreAggr; 448 ads->ds_ctl1 &= ~AR_MoreAggr;
408 ads->ds_ctl6 &= ~AR_PadDelim; 449 ads->ds_ctl6 &= ~AR_PadDelim;
409} 450}
451EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
410 452
411void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds) 453void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
412{ 454{
@@ -414,6 +456,7 @@ void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
414 456
415 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 457 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
416} 458}
459EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
417 460
418void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, 461void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
419 u32 burstDuration) 462 u32 burstDuration)
@@ -423,6 +466,7 @@ void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
423 ads->ds_ctl2 &= ~AR_BurstDur; 466 ads->ds_ctl2 &= ~AR_BurstDur;
424 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); 467 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
425} 468}
469EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
426 470
427void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, 471void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
428 u32 vmf) 472 u32 vmf)
@@ -440,28 +484,30 @@ void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
440 *txqs &= ah->intr_txqs; 484 *txqs &= ah->intr_txqs;
441 ah->intr_txqs &= ~(*txqs); 485 ah->intr_txqs &= ~(*txqs);
442} 486}
487EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
443 488
444bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 489bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
445 const struct ath9k_tx_queue_info *qinfo) 490 const struct ath9k_tx_queue_info *qinfo)
446{ 491{
447 u32 cw; 492 u32 cw;
493 struct ath_common *common = ath9k_hw_common(ah);
448 struct ath9k_hw_capabilities *pCap = &ah->caps; 494 struct ath9k_hw_capabilities *pCap = &ah->caps;
449 struct ath9k_tx_queue_info *qi; 495 struct ath9k_tx_queue_info *qi;
450 496
451 if (q >= pCap->total_queues) { 497 if (q >= pCap->total_queues) {
452 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " 498 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
453 "invalid queue: %u\n", q); 499 "invalid queue: %u\n", q);
454 return false; 500 return false;
455 } 501 }
456 502
457 qi = &ah->txq[q]; 503 qi = &ah->txq[q];
458 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 504 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
459 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " 505 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
460 "inactive queue: %u\n", q); 506 "inactive queue: %u\n", q);
461 return false; 507 return false;
462 } 508 }
463 509
464 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); 510 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
465 511
466 qi->tqi_ver = qinfo->tqi_ver; 512 qi->tqi_ver = qinfo->tqi_ver;
467 qi->tqi_subtype = qinfo->tqi_subtype; 513 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -510,23 +556,25 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
510 556
511 return true; 557 return true;
512} 558}
559EXPORT_SYMBOL(ath9k_hw_set_txq_props);
513 560
514bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 561bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
515 struct ath9k_tx_queue_info *qinfo) 562 struct ath9k_tx_queue_info *qinfo)
516{ 563{
564 struct ath_common *common = ath9k_hw_common(ah);
517 struct ath9k_hw_capabilities *pCap = &ah->caps; 565 struct ath9k_hw_capabilities *pCap = &ah->caps;
518 struct ath9k_tx_queue_info *qi; 566 struct ath9k_tx_queue_info *qi;
519 567
520 if (q >= pCap->total_queues) { 568 if (q >= pCap->total_queues) {
521 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " 569 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
522 "invalid queue: %u\n", q); 570 "invalid queue: %u\n", q);
523 return false; 571 return false;
524 } 572 }
525 573
526 qi = &ah->txq[q]; 574 qi = &ah->txq[q];
527 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 575 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
528 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " 576 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
529 "inactive queue: %u\n", q); 577 "inactive queue: %u\n", q);
530 return false; 578 return false;
531 } 579 }
532 580
@@ -547,10 +595,12 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
547 595
548 return true; 596 return true;
549} 597}
598EXPORT_SYMBOL(ath9k_hw_get_txq_props);
550 599
551int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 600int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
552 const struct ath9k_tx_queue_info *qinfo) 601 const struct ath9k_tx_queue_info *qinfo)
553{ 602{
603 struct ath_common *common = ath9k_hw_common(ah);
554 struct ath9k_tx_queue_info *qi; 604 struct ath9k_tx_queue_info *qi;
555 struct ath9k_hw_capabilities *pCap = &ah->caps; 605 struct ath9k_hw_capabilities *pCap = &ah->caps;
556 int q; 606 int q;
@@ -574,23 +624,23 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
574 ATH9K_TX_QUEUE_INACTIVE) 624 ATH9K_TX_QUEUE_INACTIVE)
575 break; 625 break;
576 if (q == pCap->total_queues) { 626 if (q == pCap->total_queues) {
577 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 627 ath_print(common, ATH_DBG_FATAL,
578 "No available TX queue\n"); 628 "No available TX queue\n");
579 return -1; 629 return -1;
580 } 630 }
581 break; 631 break;
582 default: 632 default:
583 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Invalid TX queue type: %u\n", 633 ath_print(common, ATH_DBG_FATAL,
584 type); 634 "Invalid TX queue type: %u\n", type);
585 return -1; 635 return -1;
586 } 636 }
587 637
588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); 638 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
589 639
590 qi = &ah->txq[q]; 640 qi = &ah->txq[q];
591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 641 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
592 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 642 ath_print(common, ATH_DBG_FATAL,
593 "TX queue: %u already active\n", q); 643 "TX queue: %u already active\n", q);
594 return -1; 644 return -1;
595 } 645 }
596 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 646 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -613,25 +663,27 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
613 663
614 return q; 664 return q;
615} 665}
666EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
616 667
617bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 668bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
618{ 669{
619 struct ath9k_hw_capabilities *pCap = &ah->caps; 670 struct ath9k_hw_capabilities *pCap = &ah->caps;
671 struct ath_common *common = ath9k_hw_common(ah);
620 struct ath9k_tx_queue_info *qi; 672 struct ath9k_tx_queue_info *qi;
621 673
622 if (q >= pCap->total_queues) { 674 if (q >= pCap->total_queues) {
623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " 675 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
624 "invalid queue: %u\n", q); 676 "invalid queue: %u\n", q);
625 return false; 677 return false;
626 } 678 }
627 qi = &ah->txq[q]; 679 qi = &ah->txq[q];
628 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 680 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
629 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " 681 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
630 "inactive queue: %u\n", q); 682 "inactive queue: %u\n", q);
631 return false; 683 return false;
632 } 684 }
633 685
634 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); 686 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
635 687
636 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 688 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
637 ah->txok_interrupt_mask &= ~(1 << q); 689 ah->txok_interrupt_mask &= ~(1 << q);
@@ -643,28 +695,30 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
643 695
644 return true; 696 return true;
645} 697}
698EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
646 699
647bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 700bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
648{ 701{
649 struct ath9k_hw_capabilities *pCap = &ah->caps; 702 struct ath9k_hw_capabilities *pCap = &ah->caps;
703 struct ath_common *common = ath9k_hw_common(ah);
650 struct ath9k_channel *chan = ah->curchan; 704 struct ath9k_channel *chan = ah->curchan;
651 struct ath9k_tx_queue_info *qi; 705 struct ath9k_tx_queue_info *qi;
652 u32 cwMin, chanCwMin, value; 706 u32 cwMin, chanCwMin, value;
653 707
654 if (q >= pCap->total_queues) { 708 if (q >= pCap->total_queues) {
655 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " 709 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
656 "invalid queue: %u\n", q); 710 "invalid queue: %u\n", q);
657 return false; 711 return false;
658 } 712 }
659 713
660 qi = &ah->txq[q]; 714 qi = &ah->txq[q];
661 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 715 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " 716 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
663 "inactive queue: %u\n", q); 717 "inactive queue: %u\n", q);
664 return true; 718 return true;
665 } 719 }
666 720
667 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); 721 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
668 722
669 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 723 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
670 if (chan && IS_CHAN_B(chan)) 724 if (chan && IS_CHAN_B(chan))
@@ -799,6 +853,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
799 853
800 return true; 854 return true;
801} 855}
856EXPORT_SYMBOL(ath9k_hw_resettxqueue);
802 857
803int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 858int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
804 u32 pa, struct ath_desc *nds, u64 tsf) 859 u32 pa, struct ath_desc *nds, u64 tsf)
@@ -880,6 +935,7 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
880 935
881 return 0; 936 return 0;
882} 937}
938EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
883 939
884void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 940void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
885 u32 size, u32 flags) 941 u32 size, u32 flags)
@@ -895,7 +951,15 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
895 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 951 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
896 memset(&(ads->u), 0, sizeof(ads->u)); 952 memset(&(ads->u), 0, sizeof(ads->u));
897} 953}
954EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
898 955
956/*
957 * This can stop or re-enables RX.
958 *
959 * If bool is set this will kill any frame which is currently being
960 * transferred between the MAC and baseband and also prevent any new
961 * frames from getting started.
962 */
899bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) 963bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
900{ 964{
901 u32 reg; 965 u32 reg;
@@ -911,8 +975,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
911 AR_DIAG_RX_ABORT)); 975 AR_DIAG_RX_ABORT));
912 976
913 reg = REG_READ(ah, AR_OBS_BUS_1); 977 reg = REG_READ(ah, AR_OBS_BUS_1);
914 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 978 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
915 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); 979 "RX failed to go idle in 10 ms RXSM=0x%x\n",
980 reg);
916 981
917 return false; 982 return false;
918 } 983 }
@@ -923,16 +988,19 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
923 988
924 return true; 989 return true;
925} 990}
991EXPORT_SYMBOL(ath9k_hw_setrxabort);
926 992
927void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) 993void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
928{ 994{
929 REG_WRITE(ah, AR_RXDP, rxdp); 995 REG_WRITE(ah, AR_RXDP, rxdp);
930} 996}
997EXPORT_SYMBOL(ath9k_hw_putrxbuf);
931 998
932void ath9k_hw_rxena(struct ath_hw *ah) 999void ath9k_hw_rxena(struct ath_hw *ah)
933{ 1000{
934 REG_WRITE(ah, AR_CR, AR_CR_RXE); 1001 REG_WRITE(ah, AR_CR, AR_CR_RXE);
935} 1002}
1003EXPORT_SYMBOL(ath9k_hw_rxena);
936 1004
937void ath9k_hw_startpcureceive(struct ath_hw *ah) 1005void ath9k_hw_startpcureceive(struct ath_hw *ah)
938{ 1006{
@@ -942,6 +1010,7 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah)
942 1010
943 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 1011 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
944} 1012}
1013EXPORT_SYMBOL(ath9k_hw_startpcureceive);
945 1014
946void ath9k_hw_stoppcurecv(struct ath_hw *ah) 1015void ath9k_hw_stoppcurecv(struct ath_hw *ah)
947{ 1016{
@@ -949,12 +1018,13 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
949 1018
950 ath9k_hw_disable_mib_counters(ah); 1019 ath9k_hw_disable_mib_counters(ah);
951} 1020}
1021EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
952 1022
953bool ath9k_hw_stopdmarecv(struct ath_hw *ah) 1023bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
954{ 1024{
955#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 1025#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
956#define AH_RX_TIME_QUANTUM 100 /* usec */ 1026#define AH_RX_TIME_QUANTUM 100 /* usec */
957 1027 struct ath_common *common = ath9k_hw_common(ah);
958 int i; 1028 int i;
959 1029
960 REG_WRITE(ah, AR_CR, AR_CR_RXD); 1030 REG_WRITE(ah, AR_CR, AR_CR_RXD);
@@ -967,12 +1037,12 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
967 } 1037 }
968 1038
969 if (i == 0) { 1039 if (i == 0) {
970 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1040 ath_print(common, ATH_DBG_FATAL,
971 "DMA failed to stop in %d ms " 1041 "DMA failed to stop in %d ms "
972 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", 1042 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
973 AH_RX_STOP_DMA_TIMEOUT / 1000, 1043 AH_RX_STOP_DMA_TIMEOUT / 1000,
974 REG_READ(ah, AR_CR), 1044 REG_READ(ah, AR_CR),
975 REG_READ(ah, AR_DIAG_SW)); 1045 REG_READ(ah, AR_DIAG_SW));
976 return false; 1046 return false;
977 } else { 1047 } else {
978 return true; 1048 return true;
@@ -981,3 +1051,17 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
981#undef AH_RX_TIME_QUANTUM 1051#undef AH_RX_TIME_QUANTUM
982#undef AH_RX_STOP_DMA_TIMEOUT 1052#undef AH_RX_STOP_DMA_TIMEOUT
983} 1053}
1054EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
1055
1056int ath9k_hw_beaconq_setup(struct ath_hw *ah)
1057{
1058 struct ath9k_tx_queue_info qi;
1059
1060 memset(&qi, 0, sizeof(qi));
1061 qi.tqi_aifs = 1;
1062 qi.tqi_cwmin = 0;
1063 qi.tqi_cwmax = 0;
1064 /* NB: don't enable any interrupts */
1065 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
1066}
1067EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index f56e77da6c3e..29851e6376a9 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -76,6 +76,10 @@
76#define ATH9K_TXERR_FIFO 0x04 76#define ATH9K_TXERR_FIFO 0x04
77#define ATH9K_TXERR_XTXOP 0x08 77#define ATH9K_TXERR_XTXOP 0x08
78#define ATH9K_TXERR_TIMER_EXPIRED 0x10 78#define ATH9K_TXERR_TIMER_EXPIRED 0x10
79#define ATH9K_TX_ACKED 0x20
80#define ATH9K_TXERR_MASK \
81 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
82 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
79 83
80#define ATH9K_TX_BA 0x01 84#define ATH9K_TX_BA 0x01
81#define ATH9K_TX_PWRMGMT 0x02 85#define ATH9K_TX_PWRMGMT 0x02
@@ -85,9 +89,15 @@
85#define ATH9K_TX_SW_ABORTED 0x40 89#define ATH9K_TX_SW_ABORTED 0x40
86#define ATH9K_TX_SW_FILTERED 0x80 90#define ATH9K_TX_SW_FILTERED 0x80
87 91
92/* 64 bytes */
88#define MIN_TX_FIFO_THRESHOLD 0x1 93#define MIN_TX_FIFO_THRESHOLD 0x1
94
95/*
96 * Single stream device AR9285 and AR9271 require 2 KB
97 * to work around a hardware issue, all other devices
98 * have can use the max 4 KB limit.
99 */
89#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 100#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
90#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
91 101
92struct ath_tx_status { 102struct ath_tx_status {
93 u32 ts_tstamp; 103 u32 ts_tstamp;
@@ -157,6 +167,40 @@ struct ath_rx_status {
157#define ATH9K_RXKEYIX_INVALID ((u8)-1) 167#define ATH9K_RXKEYIX_INVALID ((u8)-1)
158#define ATH9K_TXKEYIX_INVALID ((u32)-1) 168#define ATH9K_TXKEYIX_INVALID ((u32)-1)
159 169
170enum ath9k_phyerr {
171 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */
172 ATH9K_PHYERR_TIMING = 1, /* Timing error */
173 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */
174 ATH9K_PHYERR_RATE = 3, /* Illegal rate */
175 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */
176 ATH9K_PHYERR_RADAR = 5, /* Radar detect */
177 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */
178 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */
179
180 ATH9K_PHYERR_OFDM_TIMING = 17,
181 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,
182 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,
183 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
184 ATH9K_PHYERR_OFDM_POWER_DROP = 21,
185 ATH9K_PHYERR_OFDM_SERVICE = 22,
186 ATH9K_PHYERR_OFDM_RESTART = 23,
187 ATH9K_PHYERR_FALSE_RADAR_EXT = 24,
188
189 ATH9K_PHYERR_CCK_TIMING = 25,
190 ATH9K_PHYERR_CCK_HEADER_CRC = 26,
191 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,
192 ATH9K_PHYERR_CCK_SERVICE = 30,
193 ATH9K_PHYERR_CCK_RESTART = 31,
194 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32,
195 ATH9K_PHYERR_CCK_POWER_DROP = 33,
196
197 ATH9K_PHYERR_HT_CRC_ERROR = 34,
198 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35,
199 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36,
200
201 ATH9K_PHYERR_MAX = 37,
202};
203
160struct ath_desc { 204struct ath_desc {
161 u32 ds_link; 205 u32 ds_link;
162 u32 ds_data; 206 u32 ds_data;
@@ -380,6 +424,11 @@ struct ar5416_desc {
380#define AR_TxBaStatus 0x40000000 424#define AR_TxBaStatus 0x40000000
381#define AR_TxStatusRsvd01 0x80000000 425#define AR_TxStatusRsvd01 0x80000000
382 426
427/*
428 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
429 * transmitted successfully. If clear, no ACK or BA was received to indicate
430 * successful transmission when we were expecting an ACK or BA.
431 */
383#define AR_FrmXmitOK 0x00000001 432#define AR_FrmXmitOK 0x00000001
384#define AR_ExcessiveRetries 0x00000002 433#define AR_ExcessiveRetries 0x00000002
385#define AR_FIFOUnderrun 0x00000004 434#define AR_FIFOUnderrun 0x00000004
@@ -614,19 +663,8 @@ enum ath9k_cipher {
614 ATH9K_CIPHER_MIC = 127 663 ATH9K_CIPHER_MIC = 127
615}; 664};
616 665
617enum ath9k_ht_macmode {
618 ATH9K_HT_MACMODE_20 = 0,
619 ATH9K_HT_MACMODE_2040 = 1,
620};
621
622enum ath9k_ht_extprotspacing {
623 ATH9K_HT_EXTPROTSPACING_20 = 0,
624 ATH9K_HT_EXTPROTSPACING_25 = 1,
625};
626
627struct ath_hw; 666struct ath_hw;
628struct ath9k_channel; 667struct ath9k_channel;
629struct ath_rate_table;
630 668
631u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 669u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
632void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 670void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
@@ -677,5 +715,6 @@ void ath9k_hw_rxena(struct ath_hw *ah);
677void ath9k_hw_startpcureceive(struct ath_hw *ah); 715void ath9k_hw_startpcureceive(struct ath_hw *ah);
678void ath9k_hw_stoppcurecv(struct ath_hw *ah); 716void ath9k_hw_stoppcurecv(struct ath_hw *ah);
679bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 717bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
718int ath9k_hw_beaconq_setup(struct ath_hw *ah);
680 719
681#endif /* MAC_H */ 720#endif /* MAC_H */
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 43d2be9867fc..115e1aeedb59 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -16,88 +16,7 @@
16 16
17#include <linux/nl80211.h> 17#include <linux/nl80211.h>
18#include "ath9k.h" 18#include "ath9k.h"
19 19#include "btcoex.h"
20static char *dev_info = "ath9k";
21
22MODULE_AUTHOR("Atheros Communications");
23MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25MODULE_LICENSE("Dual BSD/GPL");
26
27static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 20, \
37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 20, \
44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101 20
102static void ath_cache_conf_rate(struct ath_softc *sc, 21static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf) 22 struct ieee80211_conf *conf)
@@ -105,31 +24,23 @@ static void ath_cache_conf_rate(struct ath_softc *sc,
105 switch (conf->channel->band) { 24 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ: 25 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf)) 26 if (conf_is_ht20(conf))
108 sc->cur_rate_table = 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf)) 28 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table = 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf)) 30 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table = 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116 else 32 else
117 sc->cur_rate_table = 33 sc->cur_rate_mode = ATH9K_MODE_11G;
118 sc->hw_rate_table[ATH9K_MODE_11G];
119 break; 34 break;
120 case IEEE80211_BAND_5GHZ: 35 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf)) 36 if (conf_is_ht20(conf))
122 sc->cur_rate_table = 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf)) 38 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table = 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf)) 40 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table = 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else 42 else
131 sc->cur_rate_table = 43 sc->cur_rate_mode = ATH9K_MODE_11A;
132 sc->hw_rate_table[ATH9K_MODE_11A];
133 break; 44 break;
134 default: 45 default:
135 BUG_ON(1); 46 BUG_ON(1);
@@ -185,50 +96,6 @@ static u8 parse_mpdudensity(u8 mpdudensity)
185 } 96 }
186} 97}
187 98
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
190 const struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
225 sband->n_bitrates++;
226
227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
229 }
230}
231
232static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, 99static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw) 100 struct ieee80211_hw *hw)
234{ 101{
@@ -242,6 +109,53 @@ static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
242 return channel; 109 return channel;
243} 110}
244 111
112bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
113{
114 unsigned long flags;
115 bool ret;
116
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 ret = ath9k_hw_setpower(sc->sc_ah, mode);
119 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
120
121 return ret;
122}
123
124void ath9k_ps_wakeup(struct ath_softc *sc)
125{
126 unsigned long flags;
127
128 spin_lock_irqsave(&sc->sc_pm_lock, flags);
129 if (++sc->ps_usecount != 1)
130 goto unlock;
131
132 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
133
134 unlock:
135 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
136}
137
138void ath9k_ps_restore(struct ath_softc *sc)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
146 if (sc->ps_idle)
147 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
148 else if (sc->ps_enabled &&
149 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
150 PS_WAIT_FOR_CAB |
151 PS_WAIT_FOR_PSPOLL_DATA |
152 PS_WAIT_FOR_TX_ACK)))
153 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
154
155 unlock:
156 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
157}
158
245/* 159/*
246 * Set/change channels. If the channel is really being changed, it's done 160 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending 161 * by reseting the chip. To accomplish this we must first cleanup any pending
@@ -251,6 +165,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan) 165 struct ath9k_channel *hchan)
252{ 166{
253 struct ath_hw *ah = sc->sc_ah; 167 struct ath_hw *ah = sc->sc_ah;
168 struct ath_common *common = ath9k_hw_common(ah);
169 struct ieee80211_conf *conf = &common->hw->conf;
254 bool fastcc = true, stopped; 170 bool fastcc = true, stopped;
255 struct ieee80211_channel *channel = hw->conf.channel; 171 struct ieee80211_channel *channel = hw->conf.channel;
256 int r; 172 int r;
@@ -280,19 +196,19 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) 196 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false; 197 fastcc = false;
282 198
283 DPRINTF(sc, ATH_DBG_CONFIG, 199 ath_print(common, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n", 200 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
285 sc->sc_ah->curchan->channel, 201 sc->sc_ah->curchan->channel,
286 channel->center_freq, sc->tx_chan_width); 202 channel->center_freq, conf_is_ht40(conf));
287 203
288 spin_lock_bh(&sc->sc_resetlock); 204 spin_lock_bh(&sc->sc_resetlock);
289 205
290 r = ath9k_hw_reset(ah, hchan, fastcc); 206 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) { 207 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL, 208 ath_print(common, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) " 209 "Unable to reset channel (%u MHz), "
294 "reset status %d\n", 210 "reset status %d\n",
295 channel->center_freq, r); 211 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock); 212 spin_unlock_bh(&sc->sc_resetlock);
297 goto ps_restore; 213 goto ps_restore;
298 } 214 }
@@ -301,8 +217,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
301 sc->sc_flags &= ~SC_OP_FULL_RESET; 217 sc->sc_flags &= ~SC_OP_FULL_RESET;
302 218
303 if (ath_startrecv(sc) != 0) { 219 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL, 220 ath_print(common, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n"); 221 "Unable to restart recv logic\n");
306 r = -EIO; 222 r = -EIO;
307 goto ps_restore; 223 goto ps_restore;
308 } 224 }
@@ -323,10 +239,11 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
323 * When the task is complete, it reschedules itself depending on the 239 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated. 240 * appropriate interval that was calculated.
325 */ 241 */
326static void ath_ani_calibrate(unsigned long data) 242void ath_ani_calibrate(unsigned long data)
327{ 243{
328 struct ath_softc *sc = (struct ath_softc *)data; 244 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah; 245 struct ath_hw *ah = sc->sc_ah;
246 struct ath_common *common = ath9k_hw_common(ah);
330 bool longcal = false; 247 bool longcal = false;
331 bool shortcal = false; 248 bool shortcal = false;
332 bool aniflag = false; 249 bool aniflag = false;
@@ -336,14 +253,6 @@ static void ath_ani_calibrate(unsigned long data)
336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? 253 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; 254 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
338 255
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
343 spin_lock(&sc->ani_lock);
344 if (sc->sc_flags & SC_OP_SCANNING)
345 goto set_timer;
346
347 /* Only calibrate if awake */ 256 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) 257 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer; 258 goto set_timer;
@@ -351,33 +260,34 @@ static void ath_ani_calibrate(unsigned long data)
351 ath9k_ps_wakeup(sc); 260 ath9k_ps_wakeup(sc);
352 261
353 /* Long calibration runs independently of short calibration. */ 262 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 263 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true; 264 longcal = true;
356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 265 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357 sc->ani.longcal_timer = timestamp; 266 common->ani.longcal_timer = timestamp;
358 } 267 }
359 268
360 /* Short calibration applies only while caldone is false */ 269 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) { 270 if (!common->ani.caldone) {
362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { 271 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
363 shortcal = true; 272 shortcal = true;
364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); 273 ath_print(common, ATH_DBG_ANI,
365 sc->ani.shortcal_timer = timestamp; 274 "shortcal @%lu\n", jiffies);
366 sc->ani.resetcal_timer = timestamp; 275 common->ani.shortcal_timer = timestamp;
276 common->ani.resetcal_timer = timestamp;
367 } 277 }
368 } else { 278 } else {
369 if ((timestamp - sc->ani.resetcal_timer) >= 279 if ((timestamp - common->ani.resetcal_timer) >=
370 ATH_RESTART_CALINTERVAL) { 280 ATH_RESTART_CALINTERVAL) {
371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah); 281 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone) 282 if (common->ani.caldone)
373 sc->ani.resetcal_timer = timestamp; 283 common->ani.resetcal_timer = timestamp;
374 } 284 }
375 } 285 }
376 286
377 /* Verify whether we must check ANI */ 287 /* Verify whether we must check ANI */
378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { 288 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
379 aniflag = true; 289 aniflag = true;
380 sc->ani.checkani_timer = timestamp; 290 common->ani.checkani_timer = timestamp;
381 } 291 }
382 292
383 /* Skip all processing if there's nothing to do. */ 293 /* Skip all processing if there's nothing to do. */
@@ -388,23 +298,27 @@ static void ath_ani_calibrate(unsigned long data)
388 298
389 /* Perform calibration if necessary */ 299 /* Perform calibration if necessary */
390 if (longcal || shortcal) { 300 if (longcal || shortcal) {
391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan, 301 common->ani.caldone =
392 sc->rx_chainmask, longcal); 302 ath9k_hw_calibrate(ah,
303 ah->curchan,
304 common->rx_chainmask,
305 longcal);
393 306
394 if (longcal) 307 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, 308 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan); 309 ah->curchan);
397 310
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", 311 ath_print(common, ATH_DBG_ANI,
399 ah->curchan->channel, ah->curchan->channelFlags, 312 " calibrate chan %u/%x nf: %d\n",
400 sc->ani.noise_floor); 313 ah->curchan->channel,
314 ah->curchan->channelFlags,
315 common->ani.noise_floor);
401 } 316 }
402 } 317 }
403 318
404 ath9k_ps_restore(sc); 319 ath9k_ps_restore(sc);
405 320
406set_timer: 321set_timer:
407 spin_unlock(&sc->ani_lock);
408 /* 322 /*
409 * Set timer interval based on previous results. 323 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI, 324 * The interval must be the shortest necessary to satisfy ANI,
@@ -413,21 +327,21 @@ set_timer:
413 cal_interval = ATH_LONG_CALINTERVAL; 327 cal_interval = ATH_LONG_CALINTERVAL;
414 if (sc->sc_ah->config.enable_ani) 328 if (sc->sc_ah->config.enable_ani)
415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); 329 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
416 if (!sc->ani.caldone) 330 if (!common->ani.caldone)
417 cal_interval = min(cal_interval, (u32)short_cal_interval); 331 cal_interval = min(cal_interval, (u32)short_cal_interval);
418 332
419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); 333 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
420} 334}
421 335
422static void ath_start_ani(struct ath_softc *sc) 336static void ath_start_ani(struct ath_common *common)
423{ 337{
424 unsigned long timestamp = jiffies_to_msecs(jiffies); 338 unsigned long timestamp = jiffies_to_msecs(jiffies);
425 339
426 sc->ani.longcal_timer = timestamp; 340 common->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp; 341 common->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp; 342 common->ani.checkani_timer = timestamp;
429 343
430 mod_timer(&sc->ani.timer, 344 mod_timer(&common->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); 345 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432} 346}
433 347
@@ -439,17 +353,22 @@ static void ath_start_ani(struct ath_softc *sc)
439 */ 353 */
440void ath_update_chainmask(struct ath_softc *sc, int is_ht) 354void ath_update_chainmask(struct ath_softc *sc, int is_ht)
441{ 355{
356 struct ath_hw *ah = sc->sc_ah;
357 struct ath_common *common = ath9k_hw_common(ah);
358
442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || 359 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
443 (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE)) { 360 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; 361 common->tx_chainmask = ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; 362 common->rx_chainmask = ah->caps.rx_chainmask;
446 } else { 363 } else {
447 sc->tx_chainmask = 1; 364 common->tx_chainmask = 1;
448 sc->rx_chainmask = 1; 365 common->rx_chainmask = 1;
449 } 366 }
450 367
451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", 368 ath_print(common, ATH_DBG_CONFIG,
452 sc->tx_chainmask, sc->rx_chainmask); 369 "tx chmask: %d, rx chmask: %d\n",
370 common->tx_chainmask,
371 common->rx_chainmask);
453} 372}
454 373
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 374static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
@@ -475,9 +394,12 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
475 ath_tx_node_cleanup(sc, an); 394 ath_tx_node_cleanup(sc, an);
476} 395}
477 396
478static void ath9k_tasklet(unsigned long data) 397void ath9k_tasklet(unsigned long data)
479{ 398{
480 struct ath_softc *sc = (struct ath_softc *)data; 399 struct ath_softc *sc = (struct ath_softc *)data;
400 struct ath_hw *ah = sc->sc_ah;
401 struct ath_common *common = ath9k_hw_common(ah);
402
481 u32 status = sc->intrstatus; 403 u32 status = sc->intrstatus;
482 404
483 ath9k_ps_wakeup(sc); 405 ath9k_ps_wakeup(sc);
@@ -502,16 +424,17 @@ static void ath9k_tasklet(unsigned long data)
502 * TSF sync does not look correct; remain awake to sync with 424 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon. 425 * the next Beacon.
504 */ 426 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); 427 ath_print(common, ATH_DBG_PS,
506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; 428 "TSFOOR - Sync with next Beacon\n");
429 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
507 } 430 }
508 431
509 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 432 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
510 if (status & ATH9K_INT_GENTIMER) 433 if (status & ATH9K_INT_GENTIMER)
511 ath_gen_timer_isr(sc->sc_ah); 434 ath_gen_timer_isr(sc->sc_ah);
512 435
513 /* re-enable hardware interrupt */ 436 /* re-enable hardware interrupt */
514 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 437 ath9k_hw_set_interrupts(ah, sc->imask);
515 ath9k_ps_restore(sc); 438 ath9k_ps_restore(sc);
516} 439}
517 440
@@ -602,9 +525,9 @@ irqreturn_t ath_isr(int irq, void *dev)
602 if (status & ATH9K_INT_TIM_TIMER) { 525 if (status & ATH9K_INT_TIM_TIMER) {
603 /* Clear RxAbort bit so that we can 526 /* Clear RxAbort bit so that we can
604 * receive frames */ 527 * receive frames */
605 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 528 ath9k_setpower(sc, ATH9K_PM_AWAKE);
606 ath9k_hw_setrxabort(sc->sc_ah, 0); 529 ath9k_hw_setrxabort(sc->sc_ah, 0);
607 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON; 530 sc->ps_flags |= PS_WAIT_FOR_BEACON;
608 } 531 }
609 532
610chip_reset: 533chip_reset:
@@ -664,10 +587,11 @@ static u32 ath_get_extchanmode(struct ath_softc *sc,
664 return chanmode; 587 return chanmode;
665} 588}
666 589
667static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key, 590static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
668 struct ath9k_keyval *hk, const u8 *addr, 591 struct ath9k_keyval *hk, const u8 *addr,
669 bool authenticator) 592 bool authenticator)
670{ 593{
594 struct ath_hw *ah = common->ah;
671 const u8 *key_rxmic; 595 const u8 *key_rxmic;
672 const u8 *key_txmic; 596 const u8 *key_txmic;
673 597
@@ -687,42 +611,42 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 611 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); 612 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
689 } 613 }
690 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); 614 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
691 } 615 }
692 if (!sc->splitmic) { 616 if (!common->splitmic) {
693 /* TX and RX keys share the same key cache entry. */ 617 /* TX and RX keys share the same key cache entry. */
694 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 618 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
695 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); 619 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
696 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); 620 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
697 } 621 }
698 622
699 /* Separate key cache entries for TX and RX */ 623 /* Separate key cache entries for TX and RX */
700 624
701 /* TX key goes at first index, RX key at +32. */ 625 /* TX key goes at first index, RX key at +32. */
702 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 626 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
703 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { 627 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
704 /* TX MIC entry failed. No need to proceed further */ 628 /* TX MIC entry failed. No need to proceed further */
705 DPRINTF(sc, ATH_DBG_FATAL, 629 ath_print(common, ATH_DBG_FATAL,
706 "Setting TX MIC Key Failed\n"); 630 "Setting TX MIC Key Failed\n");
707 return 0; 631 return 0;
708 } 632 }
709 633
710 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 634 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
711 /* XXX delete tx key on failure? */ 635 /* XXX delete tx key on failure? */
712 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr); 636 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
713} 637}
714 638
715static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc) 639static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
716{ 640{
717 int i; 641 int i;
718 642
719 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { 643 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
720 if (test_bit(i, sc->keymap) || 644 if (test_bit(i, common->keymap) ||
721 test_bit(i + 64, sc->keymap)) 645 test_bit(i + 64, common->keymap))
722 continue; /* At least one part of TKIP key allocated */ 646 continue; /* At least one part of TKIP key allocated */
723 if (sc->splitmic && 647 if (common->splitmic &&
724 (test_bit(i + 32, sc->keymap) || 648 (test_bit(i + 32, common->keymap) ||
725 test_bit(i + 64 + 32, sc->keymap))) 649 test_bit(i + 64 + 32, common->keymap)))
726 continue; /* At least one part of TKIP key allocated */ 650 continue; /* At least one part of TKIP key allocated */
727 651
728 /* Found a free slot for a TKIP key */ 652 /* Found a free slot for a TKIP key */
@@ -731,60 +655,60 @@ static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
731 return -1; 655 return -1;
732} 656}
733 657
734static int ath_reserve_key_cache_slot(struct ath_softc *sc) 658static int ath_reserve_key_cache_slot(struct ath_common *common)
735{ 659{
736 int i; 660 int i;
737 661
738 /* First, try to find slots that would not be available for TKIP. */ 662 /* First, try to find slots that would not be available for TKIP. */
739 if (sc->splitmic) { 663 if (common->splitmic) {
740 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) { 664 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
741 if (!test_bit(i, sc->keymap) && 665 if (!test_bit(i, common->keymap) &&
742 (test_bit(i + 32, sc->keymap) || 666 (test_bit(i + 32, common->keymap) ||
743 test_bit(i + 64, sc->keymap) || 667 test_bit(i + 64, common->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap))) 668 test_bit(i + 64 + 32, common->keymap)))
745 return i; 669 return i;
746 if (!test_bit(i + 32, sc->keymap) && 670 if (!test_bit(i + 32, common->keymap) &&
747 (test_bit(i, sc->keymap) || 671 (test_bit(i, common->keymap) ||
748 test_bit(i + 64, sc->keymap) || 672 test_bit(i + 64, common->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap))) 673 test_bit(i + 64 + 32, common->keymap)))
750 return i + 32; 674 return i + 32;
751 if (!test_bit(i + 64, sc->keymap) && 675 if (!test_bit(i + 64, common->keymap) &&
752 (test_bit(i , sc->keymap) || 676 (test_bit(i , common->keymap) ||
753 test_bit(i + 32, sc->keymap) || 677 test_bit(i + 32, common->keymap) ||
754 test_bit(i + 64 + 32, sc->keymap))) 678 test_bit(i + 64 + 32, common->keymap)))
755 return i + 64; 679 return i + 64;
756 if (!test_bit(i + 64 + 32, sc->keymap) && 680 if (!test_bit(i + 64 + 32, common->keymap) &&
757 (test_bit(i, sc->keymap) || 681 (test_bit(i, common->keymap) ||
758 test_bit(i + 32, sc->keymap) || 682 test_bit(i + 32, common->keymap) ||
759 test_bit(i + 64, sc->keymap))) 683 test_bit(i + 64, common->keymap)))
760 return i + 64 + 32; 684 return i + 64 + 32;
761 } 685 }
762 } else { 686 } else {
763 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { 687 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
764 if (!test_bit(i, sc->keymap) && 688 if (!test_bit(i, common->keymap) &&
765 test_bit(i + 64, sc->keymap)) 689 test_bit(i + 64, common->keymap))
766 return i; 690 return i;
767 if (test_bit(i, sc->keymap) && 691 if (test_bit(i, common->keymap) &&
768 !test_bit(i + 64, sc->keymap)) 692 !test_bit(i + 64, common->keymap))
769 return i + 64; 693 return i + 64;
770 } 694 }
771 } 695 }
772 696
773 /* No partially used TKIP slots, pick any available slot */ 697 /* No partially used TKIP slots, pick any available slot */
774 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) { 698 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
775 /* Do not allow slots that could be needed for TKIP group keys 699 /* Do not allow slots that could be needed for TKIP group keys
776 * to be used. This limitation could be removed if we know that 700 * to be used. This limitation could be removed if we know that
777 * TKIP will not be used. */ 701 * TKIP will not be used. */
778 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) 702 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
779 continue; 703 continue;
780 if (sc->splitmic) { 704 if (common->splitmic) {
781 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) 705 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
782 continue; 706 continue;
783 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) 707 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
784 continue; 708 continue;
785 } 709 }
786 710
787 if (!test_bit(i, sc->keymap)) 711 if (!test_bit(i, common->keymap))
788 return i; /* Found a free slot for a key */ 712 return i; /* Found a free slot for a key */
789 } 713 }
790 714
@@ -792,11 +716,12 @@ static int ath_reserve_key_cache_slot(struct ath_softc *sc)
792 return -1; 716 return -1;
793} 717}
794 718
795static int ath_key_config(struct ath_softc *sc, 719static int ath_key_config(struct ath_common *common,
796 struct ieee80211_vif *vif, 720 struct ieee80211_vif *vif,
797 struct ieee80211_sta *sta, 721 struct ieee80211_sta *sta,
798 struct ieee80211_key_conf *key) 722 struct ieee80211_key_conf *key)
799{ 723{
724 struct ath_hw *ah = common->ah;
800 struct ath9k_keyval hk; 725 struct ath9k_keyval hk;
801 const u8 *mac = NULL; 726 const u8 *mac = NULL;
802 int ret = 0; 727 int ret = 0;
@@ -842,104 +767,76 @@ static int ath_key_config(struct ath_softc *sc,
842 mac = sta->addr; 767 mac = sta->addr;
843 768
844 if (key->alg == ALG_TKIP) 769 if (key->alg == ALG_TKIP)
845 idx = ath_reserve_key_cache_slot_tkip(sc); 770 idx = ath_reserve_key_cache_slot_tkip(common);
846 else 771 else
847 idx = ath_reserve_key_cache_slot(sc); 772 idx = ath_reserve_key_cache_slot(common);
848 if (idx < 0) 773 if (idx < 0)
849 return -ENOSPC; /* no free key cache entries */ 774 return -ENOSPC; /* no free key cache entries */
850 } 775 }
851 776
852 if (key->alg == ALG_TKIP) 777 if (key->alg == ALG_TKIP)
853 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac, 778 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
854 vif->type == NL80211_IFTYPE_AP); 779 vif->type == NL80211_IFTYPE_AP);
855 else 780 else
856 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac); 781 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
857 782
858 if (!ret) 783 if (!ret)
859 return -EIO; 784 return -EIO;
860 785
861 set_bit(idx, sc->keymap); 786 set_bit(idx, common->keymap);
862 if (key->alg == ALG_TKIP) { 787 if (key->alg == ALG_TKIP) {
863 set_bit(idx + 64, sc->keymap); 788 set_bit(idx + 64, common->keymap);
864 if (sc->splitmic) { 789 if (common->splitmic) {
865 set_bit(idx + 32, sc->keymap); 790 set_bit(idx + 32, common->keymap);
866 set_bit(idx + 64 + 32, sc->keymap); 791 set_bit(idx + 64 + 32, common->keymap);
867 } 792 }
868 } 793 }
869 794
870 return idx; 795 return idx;
871} 796}
872 797
873static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) 798static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
874{ 799{
875 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx); 800 struct ath_hw *ah = common->ah;
801
802 ath9k_hw_keyreset(ah, key->hw_key_idx);
876 if (key->hw_key_idx < IEEE80211_WEP_NKID) 803 if (key->hw_key_idx < IEEE80211_WEP_NKID)
877 return; 804 return;
878 805
879 clear_bit(key->hw_key_idx, sc->keymap); 806 clear_bit(key->hw_key_idx, common->keymap);
880 if (key->alg != ALG_TKIP) 807 if (key->alg != ALG_TKIP)
881 return; 808 return;
882 809
883 clear_bit(key->hw_key_idx + 64, sc->keymap); 810 clear_bit(key->hw_key_idx + 64, common->keymap);
884 if (sc->splitmic) { 811 if (common->splitmic) {
885 clear_bit(key->hw_key_idx + 32, sc->keymap); 812 ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
886 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap); 813 clear_bit(key->hw_key_idx + 32, common->keymap);
814 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
887 } 815 }
888} 816}
889 817
890static void setup_ht_cap(struct ath_softc *sc,
891 struct ieee80211_sta_ht_cap *ht_info)
892{
893 u8 tx_streams, rx_streams;
894
895 ht_info->ht_supported = true;
896 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
897 IEEE80211_HT_CAP_SM_PS |
898 IEEE80211_HT_CAP_SGI_40 |
899 IEEE80211_HT_CAP_DSSSCCK40;
900
901 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
902 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
903
904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908
909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
915 }
916
917 ht_info->mcs.rx_mask[0] = 0xff;
918 if (rx_streams >= 2)
919 ht_info->mcs.rx_mask[1] = 0xff;
920
921 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
922}
923
924static void ath9k_bss_assoc_info(struct ath_softc *sc, 818static void ath9k_bss_assoc_info(struct ath_softc *sc,
925 struct ieee80211_vif *vif, 819 struct ieee80211_vif *vif,
926 struct ieee80211_bss_conf *bss_conf) 820 struct ieee80211_bss_conf *bss_conf)
927{ 821{
822 struct ath_hw *ah = sc->sc_ah;
823 struct ath_common *common = ath9k_hw_common(ah);
928 824
929 if (bss_conf->assoc) { 825 if (bss_conf->assoc) {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", 826 ath_print(common, ATH_DBG_CONFIG,
931 bss_conf->aid, sc->curbssid); 827 "Bss Info ASSOC %d, bssid: %pM\n",
828 bss_conf->aid, common->curbssid);
932 829
933 /* New association, store aid */ 830 /* New association, store aid */
934 sc->curaid = bss_conf->aid; 831 common->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc); 832 ath9k_hw_write_associd(ah);
936 833
937 /* 834 /*
938 * Request a re-configuration of Beacon related timers 835 * Request a re-configuration of Beacon related timers
939 * on the receipt of the first Beacon frame (i.e., 836 * on the receipt of the first Beacon frame (i.e.,
940 * after time sync with the AP). 837 * after time sync with the AP).
941 */ 838 */
942 sc->sc_flags |= SC_OP_BEACON_SYNC; 839 sc->ps_flags |= PS_BEACON_SYNC;
943 840
944 /* Configure the beacon */ 841 /* Configure the beacon */
945 ath_beacon_config(sc, vif); 842 ath_beacon_config(sc, vif);
@@ -947,187 +844,20 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
947 /* Reset rssi stats */ 844 /* Reset rssi stats */
948 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 845 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
949 846
950 ath_start_ani(sc); 847 ath_start_ani(common);
951 } else { 848 } else {
952 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 849 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
953 sc->curaid = 0; 850 common->curaid = 0;
954 /* Stop ANI */ 851 /* Stop ANI */
955 del_timer_sync(&sc->ani.timer); 852 del_timer_sync(&common->ani.timer);
956 } 853 }
957} 854}
958 855
959/********************************/ 856void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
960/* LED functions */
961/********************************/
962
963static void ath_led_blink_work(struct work_struct *work)
964{
965 struct ath_softc *sc = container_of(work, struct ath_softc,
966 ath_led_blink_work.work);
967
968 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
969 return;
970
971 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
972 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
973 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
974 else
975 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
976 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
977
978 ieee80211_queue_delayed_work(sc->hw,
979 &sc->ath_led_blink_work,
980 (sc->sc_flags & SC_OP_LED_ON) ?
981 msecs_to_jiffies(sc->led_off_duration) :
982 msecs_to_jiffies(sc->led_on_duration));
983
984 sc->led_on_duration = sc->led_on_cnt ?
985 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
986 ATH_LED_ON_DURATION_IDLE;
987 sc->led_off_duration = sc->led_off_cnt ?
988 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
989 ATH_LED_OFF_DURATION_IDLE;
990 sc->led_on_cnt = sc->led_off_cnt = 0;
991 if (sc->sc_flags & SC_OP_LED_ON)
992 sc->sc_flags &= ~SC_OP_LED_ON;
993 else
994 sc->sc_flags |= SC_OP_LED_ON;
995}
996
997static void ath_led_brightness(struct led_classdev *led_cdev,
998 enum led_brightness brightness)
999{
1000 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1001 struct ath_softc *sc = led->sc;
1002
1003 switch (brightness) {
1004 case LED_OFF:
1005 if (led->led_type == ATH_LED_ASSOC ||
1006 led->led_type == ATH_LED_RADIO) {
1007 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1008 (led->led_type == ATH_LED_RADIO));
1009 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1010 if (led->led_type == ATH_LED_RADIO)
1011 sc->sc_flags &= ~SC_OP_LED_ON;
1012 } else {
1013 sc->led_off_cnt++;
1014 }
1015 break;
1016 case LED_FULL:
1017 if (led->led_type == ATH_LED_ASSOC) {
1018 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1019 ieee80211_queue_delayed_work(sc->hw,
1020 &sc->ath_led_blink_work, 0);
1021 } else if (led->led_type == ATH_LED_RADIO) {
1022 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1023 sc->sc_flags |= SC_OP_LED_ON;
1024 } else {
1025 sc->led_on_cnt++;
1026 }
1027 break;
1028 default:
1029 break;
1030 }
1031}
1032
1033static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1034 char *trigger)
1035{
1036 int ret;
1037
1038 led->sc = sc;
1039 led->led_cdev.name = led->name;
1040 led->led_cdev.default_trigger = trigger;
1041 led->led_cdev.brightness_set = ath_led_brightness;
1042
1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1044 if (ret)
1045 DPRINTF(sc, ATH_DBG_FATAL,
1046 "Failed to register led:%s", led->name);
1047 else
1048 led->registered = 1;
1049 return ret;
1050}
1051
1052static void ath_unregister_led(struct ath_led *led)
1053{
1054 if (led->registered) {
1055 led_classdev_unregister(&led->led_cdev);
1056 led->registered = 0;
1057 }
1058}
1059
1060static void ath_deinit_leds(struct ath_softc *sc)
1061{
1062 ath_unregister_led(&sc->assoc_led);
1063 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1064 ath_unregister_led(&sc->tx_led);
1065 ath_unregister_led(&sc->rx_led);
1066 ath_unregister_led(&sc->radio_led);
1067 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1068}
1069
1070static void ath_init_leds(struct ath_softc *sc)
1071{
1072 char *trigger;
1073 int ret;
1074
1075 if (AR_SREV_9287(sc->sc_ah))
1076 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1077 else
1078 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1079
1080 /* Configure gpio 1 for output */
1081 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1082 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1083 /* LED off, active low */
1084 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1085
1086 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1087
1088 trigger = ieee80211_get_radio_led_name(sc->hw);
1089 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1090 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1091 ret = ath_register_led(sc, &sc->radio_led, trigger);
1092 sc->radio_led.led_type = ATH_LED_RADIO;
1093 if (ret)
1094 goto fail;
1095
1096 trigger = ieee80211_get_assoc_led_name(sc->hw);
1097 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1098 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1099 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1100 sc->assoc_led.led_type = ATH_LED_ASSOC;
1101 if (ret)
1102 goto fail;
1103
1104 trigger = ieee80211_get_tx_led_name(sc->hw);
1105 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1106 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1107 ret = ath_register_led(sc, &sc->tx_led, trigger);
1108 sc->tx_led.led_type = ATH_LED_TX;
1109 if (ret)
1110 goto fail;
1111
1112 trigger = ieee80211_get_rx_led_name(sc->hw);
1113 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1114 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1115 ret = ath_register_led(sc, &sc->rx_led, trigger);
1116 sc->rx_led.led_type = ATH_LED_RX;
1117 if (ret)
1118 goto fail;
1119
1120 return;
1121
1122fail:
1123 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1124 ath_deinit_leds(sc);
1125}
1126
1127void ath_radio_enable(struct ath_softc *sc)
1128{ 857{
1129 struct ath_hw *ah = sc->sc_ah; 858 struct ath_hw *ah = sc->sc_ah;
1130 struct ieee80211_channel *channel = sc->hw->conf.channel; 859 struct ath_common *common = ath9k_hw_common(ah);
860 struct ieee80211_channel *channel = hw->conf.channel;
1131 int r; 861 int r;
1132 862
1133 ath9k_ps_wakeup(sc); 863 ath9k_ps_wakeup(sc);
@@ -1139,17 +869,17 @@ void ath_radio_enable(struct ath_softc *sc)
1139 spin_lock_bh(&sc->sc_resetlock); 869 spin_lock_bh(&sc->sc_resetlock);
1140 r = ath9k_hw_reset(ah, ah->curchan, false); 870 r = ath9k_hw_reset(ah, ah->curchan, false);
1141 if (r) { 871 if (r) {
1142 DPRINTF(sc, ATH_DBG_FATAL, 872 ath_print(common, ATH_DBG_FATAL,
1143 "Unable to reset channel %u (%uMhz) ", 873 "Unable to reset channel (%u MHz), "
1144 "reset status %d\n", 874 "reset status %d\n",
1145 channel->center_freq, r); 875 channel->center_freq, r);
1146 } 876 }
1147 spin_unlock_bh(&sc->sc_resetlock); 877 spin_unlock_bh(&sc->sc_resetlock);
1148 878
1149 ath_update_txpow(sc); 879 ath_update_txpow(sc);
1150 if (ath_startrecv(sc) != 0) { 880 if (ath_startrecv(sc) != 0) {
1151 DPRINTF(sc, ATH_DBG_FATAL, 881 ath_print(common, ATH_DBG_FATAL,
1152 "Unable to restart recv logic\n"); 882 "Unable to restart recv logic\n");
1153 return; 883 return;
1154 } 884 }
1155 885
@@ -1164,18 +894,18 @@ void ath_radio_enable(struct ath_softc *sc)
1164 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 894 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1165 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 895 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1166 896
1167 ieee80211_wake_queues(sc->hw); 897 ieee80211_wake_queues(hw);
1168 ath9k_ps_restore(sc); 898 ath9k_ps_restore(sc);
1169} 899}
1170 900
1171void ath_radio_disable(struct ath_softc *sc) 901void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
1172{ 902{
1173 struct ath_hw *ah = sc->sc_ah; 903 struct ath_hw *ah = sc->sc_ah;
1174 struct ieee80211_channel *channel = sc->hw->conf.channel; 904 struct ieee80211_channel *channel = hw->conf.channel;
1175 int r; 905 int r;
1176 906
1177 ath9k_ps_wakeup(sc); 907 ath9k_ps_wakeup(sc);
1178 ieee80211_stop_queues(sc->hw); 908 ieee80211_stop_queues(hw);
1179 909
1180 /* Disable LED */ 910 /* Disable LED */
1181 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 911 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
@@ -1189,471 +919,36 @@ void ath_radio_disable(struct ath_softc *sc)
1189 ath_flushrecv(sc); /* flush recv queue */ 919 ath_flushrecv(sc); /* flush recv queue */
1190 920
1191 if (!ah->curchan) 921 if (!ah->curchan)
1192 ah->curchan = ath_get_curchannel(sc, sc->hw); 922 ah->curchan = ath_get_curchannel(sc, hw);
1193 923
1194 spin_lock_bh(&sc->sc_resetlock); 924 spin_lock_bh(&sc->sc_resetlock);
1195 r = ath9k_hw_reset(ah, ah->curchan, false); 925 r = ath9k_hw_reset(ah, ah->curchan, false);
1196 if (r) { 926 if (r) {
1197 DPRINTF(sc, ATH_DBG_FATAL, 927 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1198 "Unable to reset channel %u (%uMhz) " 928 "Unable to reset channel (%u MHz), "
1199 "reset status %d\n", 929 "reset status %d\n",
1200 channel->center_freq, r); 930 channel->center_freq, r);
1201 } 931 }
1202 spin_unlock_bh(&sc->sc_resetlock); 932 spin_unlock_bh(&sc->sc_resetlock);
1203 933
1204 ath9k_hw_phy_disable(ah); 934 ath9k_hw_phy_disable(ah);
1205 ath9k_hw_configpcipowersave(ah, 1, 1); 935 ath9k_hw_configpcipowersave(ah, 1, 1);
1206 ath9k_ps_restore(sc); 936 ath9k_ps_restore(sc);
1207 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 937 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1208}
1209
1210/*******************/
1211/* Rfkill */
1212/*******************/
1213
1214static bool ath_is_rfkill_set(struct ath_softc *sc)
1215{
1216 struct ath_hw *ah = sc->sc_ah;
1217
1218 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1219 ah->rfkill_polarity;
1220}
1221
1222static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1223{
1224 struct ath_wiphy *aphy = hw->priv;
1225 struct ath_softc *sc = aphy->sc;
1226 bool blocked = !!ath_is_rfkill_set(sc);
1227
1228 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1229}
1230
1231static void ath_start_rfkill_poll(struct ath_softc *sc)
1232{
1233 struct ath_hw *ah = sc->sc_ah;
1234
1235 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy);
1237}
1238
1239void ath_cleanup(struct ath_softc *sc)
1240{
1241 ath_detach(sc);
1242 free_irq(sc->irq, sc);
1243 ath_bus_cleanup(sc);
1244 kfree(sc->sec_wiphy);
1245 ieee80211_free_hw(sc->hw);
1246}
1247
1248void ath_detach(struct ath_softc *sc)
1249{
1250 struct ieee80211_hw *hw = sc->hw;
1251 int i = 0;
1252
1253 ath9k_ps_wakeup(sc);
1254
1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1256
1257 ath_deinit_leds(sc);
1258 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1259
1260 for (i = 0; i < sc->num_sec_wiphy; i++) {
1261 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1262 if (aphy == NULL)
1263 continue;
1264 sc->sec_wiphy[i] = NULL;
1265 ieee80211_unregister_hw(aphy->hw);
1266 ieee80211_free_hw(aphy->hw);
1267 }
1268 ieee80211_unregister_hw(hw);
1269 ath_rx_cleanup(sc);
1270 ath_tx_cleanup(sc);
1271
1272 tasklet_kill(&sc->intr_tq);
1273 tasklet_kill(&sc->bcon_tasklet);
1274
1275 if (!(sc->sc_flags & SC_OP_INVALID))
1276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1277
1278 /* cleanup tx queues */
1279 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1280 if (ATH_TXQ_SETUP(sc, i))
1281 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1282
1283 if ((sc->btcoex_info.no_stomp_timer) &&
1284 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
1285 ath_gen_timer_free(sc->sc_ah, sc->btcoex_info.no_stomp_timer);
1286
1287 ath9k_hw_detach(sc->sc_ah);
1288 sc->sc_ah = NULL;
1289 ath9k_exit_debug(sc);
1290}
1291
1292static int ath9k_reg_notifier(struct wiphy *wiphy,
1293 struct regulatory_request *request)
1294{
1295 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1296 struct ath_wiphy *aphy = hw->priv;
1297 struct ath_softc *sc = aphy->sc;
1298 struct ath_regulatory *reg = &sc->common.regulatory;
1299
1300 return ath_reg_notifier_apply(wiphy, request, reg);
1301}
1302
1303/*
1304 * Initialize and fill ath_softc, ath_sofct is the
1305 * "Software Carrier" struct. Historically it has existed
1306 * to allow the separation between hardware specific
1307 * variables (now in ath_hw) and driver specific variables.
1308 */
1309static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1310{
1311 struct ath_hw *ah = NULL;
1312 int r = 0, i;
1313 int csz = 0;
1314
1315 /* XXX: hardware will not be ready until ath_open() being called */
1316 sc->sc_flags |= SC_OP_INVALID;
1317
1318 if (ath9k_init_debug(sc) < 0)
1319 printk(KERN_ERR "Unable to create debugfs files\n");
1320
1321 spin_lock_init(&sc->wiphy_lock);
1322 spin_lock_init(&sc->sc_resetlock);
1323 spin_lock_init(&sc->sc_serial_rw);
1324 spin_lock_init(&sc->ani_lock);
1325 spin_lock_init(&sc->sc_pm_lock);
1326 mutex_init(&sc->mutex);
1327 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1328 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1329 (unsigned long)sc);
1330
1331 /*
1332 * Cache line size is used to size and align various
1333 * structures used to communicate with the hardware.
1334 */
1335 ath_read_cachesize(sc, &csz);
1336 /* XXX assert csz is non-zero */
1337 sc->common.cachelsz = csz << 2; /* convert to bytes */
1338
1339 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1340 if (!ah) {
1341 r = -ENOMEM;
1342 goto bad_no_ah;
1343 }
1344
1345 ah->ah_sc = sc;
1346 ah->hw_version.devid = devid;
1347 ah->hw_version.subsysid = subsysid;
1348 sc->sc_ah = ah;
1349
1350 r = ath9k_hw_init(ah);
1351 if (r) {
1352 DPRINTF(sc, ATH_DBG_FATAL,
1353 "Unable to initialize hardware; "
1354 "initialization status: %d\n", r);
1355 goto bad;
1356 }
1357
1358 /* Get the hardware key cache size. */
1359 sc->keymax = ah->caps.keycache_size;
1360 if (sc->keymax > ATH_KEYMAX) {
1361 DPRINTF(sc, ATH_DBG_ANY,
1362 "Warning, using only %u entries in %u key cache\n",
1363 ATH_KEYMAX, sc->keymax);
1364 sc->keymax = ATH_KEYMAX;
1365 }
1366
1367 /*
1368 * Reset the key cache since some parts do not
1369 * reset the contents on initial power up.
1370 */
1371 for (i = 0; i < sc->keymax; i++)
1372 ath9k_hw_keyreset(ah, (u16) i);
1373
1374 /* default to MONITOR mode */
1375 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1376
1377 /* Setup rate tables */
1378
1379 ath_rate_attach(sc);
1380 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1381 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1382
1383 /*
1384 * Allocate hardware transmit queues: one queue for
1385 * beacon frames and one data queue for each QoS
1386 * priority. Note that the hal handles reseting
1387 * these queues at the needed time.
1388 */
1389 sc->beacon.beaconq = ath_beaconq_setup(ah);
1390 if (sc->beacon.beaconq == -1) {
1391 DPRINTF(sc, ATH_DBG_FATAL,
1392 "Unable to setup a beacon xmit queue\n");
1393 r = -EIO;
1394 goto bad2;
1395 }
1396 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->beacon.cabq == NULL) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
1399 "Unable to setup CAB xmit queue\n");
1400 r = -EIO;
1401 goto bad2;
1402 }
1403
1404 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1405 ath_cabq_update(sc);
1406
1407 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1408 sc->tx.hwq_map[i] = -1;
1409
1410 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
1414 "Unable to setup xmit queue for BK traffic\n");
1415 r = -EIO;
1416 goto bad2;
1417 }
1418
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
1421 "Unable to setup xmit queue for BE traffic\n");
1422 r = -EIO;
1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
1427 "Unable to setup xmit queue for VI traffic\n");
1428 r = -EIO;
1429 goto bad2;
1430 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
1433 "Unable to setup xmit queue for VO traffic\n");
1434 r = -EIO;
1435 goto bad2;
1436 }
1437
1438 /* Initializes the noise floor to a reasonable default value.
1439 * Later on this will be updated during ANI processing. */
1440
1441 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1442 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1443
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)) {
1446 /*
1447 * Whether we should enable h/w TKIP MIC.
1448 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1449 * report WMM capable, so it's always safe to turn on
1450 * TKIP MIC in this case.
1451 */
1452 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1453 0, 1, NULL);
1454 }
1455
1456 /*
1457 * Check whether the separate key cache entries
1458 * are required to handle both tx+rx MIC keys.
1459 * With split mic keys the number of stations is limited
1460 * to 27 otherwise 59.
1461 */
1462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463 ATH9K_CIPHER_TKIP, NULL)
1464 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_MIC, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1467 0, NULL))
1468 sc->splitmic = 1;
1469
1470 /* turn on mcast key search if possible */
1471 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1472 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1473 1, NULL);
1474
1475 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1476
1477 /* 11n Capabilities */
1478 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1479 sc->sc_flags |= SC_OP_TXAGGR;
1480 sc->sc_flags |= SC_OP_RXAGGR;
1481 }
1482
1483 sc->tx_chainmask = ah->caps.tx_chainmask;
1484 sc->rx_chainmask = ah->caps.rx_chainmask;
1485
1486 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1487 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1488
1489 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1490 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1491
1492 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1493
1494 /* initialize beacon slots */
1495 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1496 sc->beacon.bslot[i] = NULL;
1497 sc->beacon.bslot_aphy[i] = NULL;
1498 }
1499
1500 /* setup channels and rates */
1501
1502 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1503 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1504 sc->rates[IEEE80211_BAND_2GHZ];
1505 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1506 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1507 ARRAY_SIZE(ath9k_2ghz_chantable);
1508
1509 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1510 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1511 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1512 sc->rates[IEEE80211_BAND_5GHZ];
1513 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1514 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1515 ARRAY_SIZE(ath9k_5ghz_chantable);
1516 }
1517
1518 if (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) {
1519 r = ath9k_hw_btcoex_init(ah);
1520 if (r)
1521 goto bad2;
1522 }
1523
1524 return 0;
1525bad2:
1526 /* cleanup tx queues */
1527 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1528 if (ATH_TXQ_SETUP(sc, i))
1529 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1530bad:
1531 ath9k_hw_detach(ah);
1532 sc->sc_ah = NULL;
1533bad_no_ah:
1534 ath9k_exit_debug(sc);
1535
1536 return r;
1537}
1538
1539void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1540{
1541 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1542 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1543 IEEE80211_HW_SIGNAL_DBM |
1544 IEEE80211_HW_AMPDU_AGGREGATION |
1545 IEEE80211_HW_SUPPORTS_PS |
1546 IEEE80211_HW_PS_NULLFUNC_STACK |
1547 IEEE80211_HW_SPECTRUM_MGMT;
1548
1549 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1550 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1551
1552 hw->wiphy->interface_modes =
1553 BIT(NL80211_IFTYPE_AP) |
1554 BIT(NL80211_IFTYPE_STATION) |
1555 BIT(NL80211_IFTYPE_ADHOC) |
1556 BIT(NL80211_IFTYPE_MESH_POINT);
1557
1558 hw->wiphy->ps_default = false;
1559
1560 hw->queues = 4;
1561 hw->max_rates = 4;
1562 hw->channel_change_time = 5000;
1563 hw->max_listen_interval = 10;
1564 /* Hardware supports 10 but we use 4 */
1565 hw->max_rate_tries = 4;
1566 hw->sta_data_size = sizeof(struct ath_node);
1567 hw->vif_data_size = sizeof(struct ath_vif);
1568
1569 hw->rate_control_algorithm = "ath9k_rate_control";
1570
1571 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1572 &sc->sbands[IEEE80211_BAND_2GHZ];
1573 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1574 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1575 &sc->sbands[IEEE80211_BAND_5GHZ];
1576}
1577
1578/* Device driver core initialization */
1579int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1580{
1581 struct ieee80211_hw *hw = sc->hw;
1582 int error = 0, i;
1583 struct ath_regulatory *reg;
1584
1585 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1586
1587 error = ath_init_softc(devid, sc, subsysid);
1588 if (error != 0)
1589 return error;
1590
1591 /* get mac address from hardware and set in mac80211 */
1592
1593 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1594
1595 ath_set_hw_capab(sc, hw);
1596
1597 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
1598 ath9k_reg_notifier);
1599 if (error)
1600 return error;
1601
1602 reg = &sc->common.regulatory;
1603
1604 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1605 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1606 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1608 }
1609
1610 /* initialize tx/rx engine */
1611 error = ath_tx_init(sc, ATH_TXBUF);
1612 if (error != 0)
1613 goto error_attach;
1614
1615 error = ath_rx_init(sc, ATH_RXBUF);
1616 if (error != 0)
1617 goto error_attach;
1618
1619 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1620 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1621 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1622
1623 error = ieee80211_register_hw(hw);
1624
1625 if (!ath_is_world_regd(reg)) {
1626 error = regulatory_hint(hw->wiphy, reg->alpha2);
1627 if (error)
1628 goto error_attach;
1629 }
1630
1631 /* Initialize LED control */
1632 ath_init_leds(sc);
1633
1634 ath_start_rfkill_poll(sc);
1635
1636 return 0;
1637
1638error_attach:
1639 /* cleanup tx queues */
1640 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1641 if (ATH_TXQ_SETUP(sc, i))
1642 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1643
1644 ath9k_hw_detach(sc->sc_ah);
1645 sc->sc_ah = NULL;
1646 ath9k_exit_debug(sc);
1647
1648 return error;
1649} 938}
1650 939
1651int ath_reset(struct ath_softc *sc, bool retry_tx) 940int ath_reset(struct ath_softc *sc, bool retry_tx)
1652{ 941{
1653 struct ath_hw *ah = sc->sc_ah; 942 struct ath_hw *ah = sc->sc_ah;
943 struct ath_common *common = ath9k_hw_common(ah);
1654 struct ieee80211_hw *hw = sc->hw; 944 struct ieee80211_hw *hw = sc->hw;
1655 int r; 945 int r;
1656 946
947 /* Stop ANI */
948 del_timer_sync(&common->ani.timer);
949
950 ieee80211_stop_queues(hw);
951
1657 ath9k_hw_set_interrupts(ah, 0); 952 ath9k_hw_set_interrupts(ah, 0);
1658 ath_drain_all_txq(sc, retry_tx); 953 ath_drain_all_txq(sc, retry_tx);
1659 ath_stoprecv(sc); 954 ath_stoprecv(sc);
@@ -1662,12 +957,13 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1662 spin_lock_bh(&sc->sc_resetlock); 957 spin_lock_bh(&sc->sc_resetlock);
1663 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); 958 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1664 if (r) 959 if (r)
1665 DPRINTF(sc, ATH_DBG_FATAL, 960 ath_print(common, ATH_DBG_FATAL,
1666 "Unable to reset hardware; reset status %d\n", r); 961 "Unable to reset hardware; reset status %d\n", r);
1667 spin_unlock_bh(&sc->sc_resetlock); 962 spin_unlock_bh(&sc->sc_resetlock);
1668 963
1669 if (ath_startrecv(sc) != 0) 964 if (ath_startrecv(sc) != 0)
1670 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); 965 ath_print(common, ATH_DBG_FATAL,
966 "Unable to start recv logic\n");
1671 967
1672 /* 968 /*
1673 * We may be doing a reset in response to a request 969 * We may be doing a reset in response to a request
@@ -1694,125 +990,12 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1694 } 990 }
1695 } 991 }
1696 992
1697 return r; 993 ieee80211_wake_queues(hw);
1698}
1699
1700/*
1701 * This function will allocate both the DMA descriptor structure, and the
1702 * buffers it contains. These are used to contain the descriptors used
1703 * by the system.
1704*/
1705int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1706 struct list_head *head, const char *name,
1707 int nbuf, int ndesc)
1708{
1709#define DS2PHYS(_dd, _ds) \
1710 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1711#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1712#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1713
1714 struct ath_desc *ds;
1715 struct ath_buf *bf;
1716 int i, bsize, error;
1717
1718 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1719 name, nbuf, ndesc);
1720
1721 INIT_LIST_HEAD(head);
1722 /* ath_desc must be a multiple of DWORDs */
1723 if ((sizeof(struct ath_desc) % 4) != 0) {
1724 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1725 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1726 error = -ENOMEM;
1727 goto fail;
1728 }
1729
1730 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1731
1732 /*
1733 * Need additional DMA memory because we can't use
1734 * descriptors that cross the 4K page boundary. Assume
1735 * one skipped descriptor per 4K page.
1736 */
1737 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1738 u32 ndesc_skipped =
1739 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1740 u32 dma_len;
1741
1742 while (ndesc_skipped) {
1743 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1744 dd->dd_desc_len += dma_len;
1745
1746 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1747 };
1748 }
1749
1750 /* allocate descriptors */
1751 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1752 &dd->dd_desc_paddr, GFP_KERNEL);
1753 if (dd->dd_desc == NULL) {
1754 error = -ENOMEM;
1755 goto fail;
1756 }
1757 ds = dd->dd_desc;
1758 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1759 name, ds, (u32) dd->dd_desc_len,
1760 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1761
1762 /* allocate buffers */
1763 bsize = sizeof(struct ath_buf) * nbuf;
1764 bf = kzalloc(bsize, GFP_KERNEL);
1765 if (bf == NULL) {
1766 error = -ENOMEM;
1767 goto fail2;
1768 }
1769 dd->dd_bufptr = bf;
1770
1771 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1772 bf->bf_desc = ds;
1773 bf->bf_daddr = DS2PHYS(dd, ds);
1774
1775 if (!(sc->sc_ah->caps.hw_caps &
1776 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1777 /*
1778 * Skip descriptor addresses which can cause 4KB
1779 * boundary crossing (addr + length) with a 32 dword
1780 * descriptor fetch.
1781 */
1782 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1783 ASSERT((caddr_t) bf->bf_desc <
1784 ((caddr_t) dd->dd_desc +
1785 dd->dd_desc_len));
1786
1787 ds += ndesc;
1788 bf->bf_desc = ds;
1789 bf->bf_daddr = DS2PHYS(dd, ds);
1790 }
1791 }
1792 list_add_tail(&bf->list, head);
1793 }
1794 return 0;
1795fail2:
1796 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1797 dd->dd_desc_paddr);
1798fail:
1799 memset(dd, 0, sizeof(*dd));
1800 return error;
1801#undef ATH_DESC_4KB_BOUND_CHECK
1802#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1803#undef DS2PHYS
1804}
1805 994
1806void ath_descdma_cleanup(struct ath_softc *sc, 995 /* Start ANI */
1807 struct ath_descdma *dd, 996 ath_start_ani(common);
1808 struct list_head *head)
1809{
1810 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1811 dd->dd_desc_paddr);
1812 997
1813 INIT_LIST_HEAD(head); 998 return r;
1814 kfree(dd->dd_bufptr);
1815 memset(dd, 0, sizeof(*dd));
1816} 999}
1817 1000
1818int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) 1001int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
@@ -1884,15 +1067,9 @@ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1884 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; 1067 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1885 } 1068 }
1886 1069
1887 sc->tx_chan_width = ATH9K_HT_MACMODE_20; 1070 if (conf_is_ht(conf))
1888
1889 if (conf_is_ht(conf)) {
1890 if (conf_is_ht40(conf))
1891 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1892
1893 ichan->chanmode = ath_get_extchanmode(sc, chan, 1071 ichan->chanmode = ath_get_extchanmode(sc, chan,
1894 conf->channel_type); 1072 conf->channel_type);
1895 }
1896} 1073}
1897 1074
1898/**********************/ 1075/**********************/
@@ -1903,12 +1080,15 @@ static int ath9k_start(struct ieee80211_hw *hw)
1903{ 1080{
1904 struct ath_wiphy *aphy = hw->priv; 1081 struct ath_wiphy *aphy = hw->priv;
1905 struct ath_softc *sc = aphy->sc; 1082 struct ath_softc *sc = aphy->sc;
1083 struct ath_hw *ah = sc->sc_ah;
1084 struct ath_common *common = ath9k_hw_common(ah);
1906 struct ieee80211_channel *curchan = hw->conf.channel; 1085 struct ieee80211_channel *curchan = hw->conf.channel;
1907 struct ath9k_channel *init_channel; 1086 struct ath9k_channel *init_channel;
1908 int r; 1087 int r;
1909 1088
1910 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " 1089 ath_print(common, ATH_DBG_CONFIG,
1911 "initial channel: %d MHz\n", curchan->center_freq); 1090 "Starting driver with initial channel: %d MHz\n",
1091 curchan->center_freq);
1912 1092
1913 mutex_lock(&sc->mutex); 1093 mutex_lock(&sc->mutex);
1914 1094
@@ -1940,7 +1120,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1940 init_channel = ath_get_curchannel(sc, hw); 1120 init_channel = ath_get_curchannel(sc, hw);
1941 1121
1942 /* Reset SERDES registers */ 1122 /* Reset SERDES registers */
1943 ath9k_hw_configpcipowersave(sc->sc_ah, 0, 0); 1123 ath9k_hw_configpcipowersave(ah, 0, 0);
1944 1124
1945 /* 1125 /*
1946 * The basic interface to setting the hardware in a good 1126 * The basic interface to setting the hardware in a good
@@ -1950,12 +1130,12 @@ static int ath9k_start(struct ieee80211_hw *hw)
1950 * and then setup of the interrupt mask. 1130 * and then setup of the interrupt mask.
1951 */ 1131 */
1952 spin_lock_bh(&sc->sc_resetlock); 1132 spin_lock_bh(&sc->sc_resetlock);
1953 r = ath9k_hw_reset(sc->sc_ah, init_channel, false); 1133 r = ath9k_hw_reset(ah, init_channel, false);
1954 if (r) { 1134 if (r) {
1955 DPRINTF(sc, ATH_DBG_FATAL, 1135 ath_print(common, ATH_DBG_FATAL,
1956 "Unable to reset hardware; reset status %d " 1136 "Unable to reset hardware; reset status %d "
1957 "(freq %u MHz)\n", r, 1137 "(freq %u MHz)\n", r,
1958 curchan->center_freq); 1138 curchan->center_freq);
1959 spin_unlock_bh(&sc->sc_resetlock); 1139 spin_unlock_bh(&sc->sc_resetlock);
1960 goto mutex_unlock; 1140 goto mutex_unlock;
1961 } 1141 }
@@ -1975,7 +1155,8 @@ static int ath9k_start(struct ieee80211_hw *hw)
1975 * here except setup the interrupt mask. 1155 * here except setup the interrupt mask.
1976 */ 1156 */
1977 if (ath_startrecv(sc) != 0) { 1157 if (ath_startrecv(sc) != 0) {
1978 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); 1158 ath_print(common, ATH_DBG_FATAL,
1159 "Unable to start recv logic\n");
1979 r = -EIO; 1160 r = -EIO;
1980 goto mutex_unlock; 1161 goto mutex_unlock;
1981 } 1162 }
@@ -1985,10 +1166,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
1985 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN 1166 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1986 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 1167 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1987 1168
1988 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT) 1169 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1989 sc->imask |= ATH9K_INT_GTT; 1170 sc->imask |= ATH9K_INT_GTT;
1990 1171
1991 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 1172 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1992 sc->imask |= ATH9K_INT_CST; 1173 sc->imask |= ATH9K_INT_CST;
1993 1174
1994 ath_cache_conf_rate(sc, &hw->conf); 1175 ath_cache_conf_rate(sc, &hw->conf);
@@ -1997,21 +1178,22 @@ static int ath9k_start(struct ieee80211_hw *hw)
1997 1178
1998 /* Disable BMISS interrupt when we're not associated */ 1179 /* Disable BMISS interrupt when we're not associated */
1999 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 1180 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2000 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 1181 ath9k_hw_set_interrupts(ah, sc->imask);
2001 1182
2002 ieee80211_wake_queues(hw); 1183 ieee80211_wake_queues(hw);
2003 1184
2004 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 1185 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2005 1186
2006 if ((sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) && 1187 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2007 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED)) { 1188 !ah->btcoex_hw.enabled) {
2008 ath_btcoex_set_weight(&sc->btcoex_info, AR_BT_COEX_WGHT, 1189 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2009 AR_STOMP_LOW_WLAN_WGHT); 1190 AR_STOMP_LOW_WLAN_WGHT);
2010 ath9k_hw_btcoex_enable(sc->sc_ah); 1191 ath9k_hw_btcoex_enable(ah);
2011 1192
2012 ath_pcie_aspm_disable(sc); 1193 if (common->bus_ops->bt_coex_prep)
2013 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 1194 common->bus_ops->bt_coex_prep(common);
2014 ath_btcoex_timer_resume(sc, &sc->btcoex_info); 1195 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1196 ath9k_btcoex_timer_resume(sc);
2015 } 1197 }
2016 1198
2017mutex_unlock: 1199mutex_unlock:
@@ -2026,17 +1208,19 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2026 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1208 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2027 struct ath_wiphy *aphy = hw->priv; 1209 struct ath_wiphy *aphy = hw->priv;
2028 struct ath_softc *sc = aphy->sc; 1210 struct ath_softc *sc = aphy->sc;
1211 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2029 struct ath_tx_control txctl; 1212 struct ath_tx_control txctl;
2030 int hdrlen, padsize; 1213 int padpos, padsize;
1214 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2031 1215
2032 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 1216 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2033 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state " 1217 ath_print(common, ATH_DBG_XMIT,
2034 "%d\n", wiphy_name(hw->wiphy), aphy->state); 1218 "ath9k: %s: TX in unexpected wiphy state "
1219 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2035 goto exit; 1220 goto exit;
2036 } 1221 }
2037 1222
2038 if (sc->ps_enabled) { 1223 if (sc->ps_enabled) {
2039 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2040 /* 1224 /*
2041 * mac80211 does not set PM field for normal data frames, so we 1225 * mac80211 does not set PM field for normal data frames, so we
2042 * need to update that based on the current PS mode. 1226 * need to update that based on the current PS mode.
@@ -2044,8 +1228,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2044 if (ieee80211_is_data(hdr->frame_control) && 1228 if (ieee80211_is_data(hdr->frame_control) &&
2045 !ieee80211_is_nullfunc(hdr->frame_control) && 1229 !ieee80211_is_nullfunc(hdr->frame_control) &&
2046 !ieee80211_has_pm(hdr->frame_control)) { 1230 !ieee80211_has_pm(hdr->frame_control)) {
2047 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame " 1231 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2048 "while in PS mode\n"); 1232 "while in PS mode\n");
2049 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1233 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2050 } 1234 }
2051 } 1235 }
@@ -2056,16 +1240,16 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2056 * power save mode. Need to wake up hardware for the TX to be 1240 * power save mode. Need to wake up hardware for the TX to be
2057 * completed and if needed, also for RX of buffered frames. 1241 * completed and if needed, also for RX of buffered frames.
2058 */ 1242 */
2059 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2060 ath9k_ps_wakeup(sc); 1243 ath9k_ps_wakeup(sc);
2061 ath9k_hw_setrxabort(sc->sc_ah, 0); 1244 ath9k_hw_setrxabort(sc->sc_ah, 0);
2062 if (ieee80211_is_pspoll(hdr->frame_control)) { 1245 if (ieee80211_is_pspoll(hdr->frame_control)) {
2063 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a " 1246 ath_print(common, ATH_DBG_PS,
2064 "buffered frame\n"); 1247 "Sending PS-Poll to pick a buffered frame\n");
2065 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; 1248 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
2066 } else { 1249 } else {
2067 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n"); 1250 ath_print(common, ATH_DBG_PS,
2068 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; 1251 "Wake up to complete TX\n");
1252 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
2069 } 1253 }
2070 /* 1254 /*
2071 * The actual restore operation will happen only after 1255 * The actual restore operation will happen only after
@@ -2083,7 +1267,6 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2083 * BSSes. 1267 * BSSes.
2084 */ 1268 */
2085 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1269 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2086 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2087 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1270 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2088 sc->tx.seq_no += 0x10; 1271 sc->tx.seq_no += 0x10;
2089 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1272 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
@@ -2091,13 +1274,13 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2091 } 1274 }
2092 1275
2093 /* Add the padding after the header if this is not already done */ 1276 /* Add the padding after the header if this is not already done */
2094 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1277 padpos = ath9k_cmn_padpos(hdr->frame_control);
2095 if (hdrlen & 3) { 1278 padsize = padpos & 3;
2096 padsize = hdrlen % 4; 1279 if (padsize && skb->len>padpos) {
2097 if (skb_headroom(skb) < padsize) 1280 if (skb_headroom(skb) < padsize)
2098 return -1; 1281 return -1;
2099 skb_push(skb, padsize); 1282 skb_push(skb, padsize);
2100 memmove(skb->data, skb->data + padsize, hdrlen); 1283 memmove(skb->data, skb->data + padsize, padpos);
2101 } 1284 }
2102 1285
2103 /* Check if a tx queue is available */ 1286 /* Check if a tx queue is available */
@@ -2106,10 +1289,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2106 if (!txctl.txq) 1289 if (!txctl.txq)
2107 goto exit; 1290 goto exit;
2108 1291
2109 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 1292 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2110 1293
2111 if (ath_tx_start(hw, skb, &txctl) != 0) { 1294 if (ath_tx_start(hw, skb, &txctl) != 0) {
2112 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n"); 1295 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2113 goto exit; 1296 goto exit;
2114 } 1297 }
2115 1298
@@ -2123,6 +1306,8 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2123{ 1306{
2124 struct ath_wiphy *aphy = hw->priv; 1307 struct ath_wiphy *aphy = hw->priv;
2125 struct ath_softc *sc = aphy->sc; 1308 struct ath_softc *sc = aphy->sc;
1309 struct ath_hw *ah = sc->sc_ah;
1310 struct ath_common *common = ath9k_hw_common(ah);
2126 1311
2127 mutex_lock(&sc->mutex); 1312 mutex_lock(&sc->mutex);
2128 1313
@@ -2137,7 +1322,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2137 } 1322 }
2138 1323
2139 if (sc->sc_flags & SC_OP_INVALID) { 1324 if (sc->sc_flags & SC_OP_INVALID) {
2140 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n"); 1325 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2141 mutex_unlock(&sc->mutex); 1326 mutex_unlock(&sc->mutex);
2142 return; 1327 return;
2143 } 1328 }
@@ -2147,41 +1332,48 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2147 return; /* another wiphy still in use */ 1332 return; /* another wiphy still in use */
2148 } 1333 }
2149 1334
2150 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED) { 1335 /* Ensure HW is awake when we try to shut it down. */
2151 ath9k_hw_btcoex_disable(sc->sc_ah); 1336 ath9k_ps_wakeup(sc);
2152 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 1337
2153 ath_btcoex_timer_pause(sc, &sc->btcoex_info); 1338 if (ah->btcoex_hw.enabled) {
1339 ath9k_hw_btcoex_disable(ah);
1340 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1341 ath9k_btcoex_timer_pause(sc);
2154 } 1342 }
2155 1343
2156 /* make sure h/w will not generate any interrupt 1344 /* make sure h/w will not generate any interrupt
2157 * before setting the invalid flag. */ 1345 * before setting the invalid flag. */
2158 ath9k_hw_set_interrupts(sc->sc_ah, 0); 1346 ath9k_hw_set_interrupts(ah, 0);
2159 1347
2160 if (!(sc->sc_flags & SC_OP_INVALID)) { 1348 if (!(sc->sc_flags & SC_OP_INVALID)) {
2161 ath_drain_all_txq(sc, false); 1349 ath_drain_all_txq(sc, false);
2162 ath_stoprecv(sc); 1350 ath_stoprecv(sc);
2163 ath9k_hw_phy_disable(sc->sc_ah); 1351 ath9k_hw_phy_disable(ah);
2164 } else 1352 } else
2165 sc->rx.rxlink = NULL; 1353 sc->rx.rxlink = NULL;
2166 1354
2167 /* disable HAL and put h/w to sleep */ 1355 /* disable HAL and put h/w to sleep */
2168 ath9k_hw_disable(sc->sc_ah); 1356 ath9k_hw_disable(ah);
2169 ath9k_hw_configpcipowersave(sc->sc_ah, 1, 1); 1357 ath9k_hw_configpcipowersave(ah, 1, 1);
2170 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 1358 ath9k_ps_restore(sc);
1359
1360 /* Finally, put the chip in FULL SLEEP mode */
1361 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2171 1362
2172 sc->sc_flags |= SC_OP_INVALID; 1363 sc->sc_flags |= SC_OP_INVALID;
2173 1364
2174 mutex_unlock(&sc->mutex); 1365 mutex_unlock(&sc->mutex);
2175 1366
2176 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n"); 1367 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2177} 1368}
2178 1369
2179static int ath9k_add_interface(struct ieee80211_hw *hw, 1370static int ath9k_add_interface(struct ieee80211_hw *hw,
2180 struct ieee80211_if_init_conf *conf) 1371 struct ieee80211_vif *vif)
2181{ 1372{
2182 struct ath_wiphy *aphy = hw->priv; 1373 struct ath_wiphy *aphy = hw->priv;
2183 struct ath_softc *sc = aphy->sc; 1374 struct ath_softc *sc = aphy->sc;
2184 struct ath_vif *avp = (void *)conf->vif->drv_priv; 1375 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1376 struct ath_vif *avp = (void *)vif->drv_priv;
2185 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; 1377 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2186 int ret = 0; 1378 int ret = 0;
2187 1379
@@ -2193,7 +1385,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2193 goto out; 1385 goto out;
2194 } 1386 }
2195 1387
2196 switch (conf->type) { 1388 switch (vif->type) {
2197 case NL80211_IFTYPE_STATION: 1389 case NL80211_IFTYPE_STATION:
2198 ic_opmode = NL80211_IFTYPE_STATION; 1390 ic_opmode = NL80211_IFTYPE_STATION;
2199 break; 1391 break;
@@ -2204,16 +1396,17 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2204 ret = -ENOBUFS; 1396 ret = -ENOBUFS;
2205 goto out; 1397 goto out;
2206 } 1398 }
2207 ic_opmode = conf->type; 1399 ic_opmode = vif->type;
2208 break; 1400 break;
2209 default: 1401 default:
2210 DPRINTF(sc, ATH_DBG_FATAL, 1402 ath_print(common, ATH_DBG_FATAL,
2211 "Interface type %d not yet supported\n", conf->type); 1403 "Interface type %d not yet supported\n", vif->type);
2212 ret = -EOPNOTSUPP; 1404 ret = -EOPNOTSUPP;
2213 goto out; 1405 goto out;
2214 } 1406 }
2215 1407
2216 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); 1408 ath_print(common, ATH_DBG_CONFIG,
1409 "Attach a VIF of type: %d\n", ic_opmode);
2217 1410
2218 /* Set the VIF opmode */ 1411 /* Set the VIF opmode */
2219 avp->av_opmode = ic_opmode; 1412 avp->av_opmode = ic_opmode;
@@ -2239,19 +1432,19 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2239 * Enable MIB interrupts when there are hardware phy counters. 1432 * Enable MIB interrupts when there are hardware phy counters.
2240 * Note we only do this (at the moment) for station mode. 1433 * Note we only do this (at the moment) for station mode.
2241 */ 1434 */
2242 if ((conf->type == NL80211_IFTYPE_STATION) || 1435 if ((vif->type == NL80211_IFTYPE_STATION) ||
2243 (conf->type == NL80211_IFTYPE_ADHOC) || 1436 (vif->type == NL80211_IFTYPE_ADHOC) ||
2244 (conf->type == NL80211_IFTYPE_MESH_POINT)) { 1437 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2245 sc->imask |= ATH9K_INT_MIB; 1438 sc->imask |= ATH9K_INT_MIB;
2246 sc->imask |= ATH9K_INT_TSFOOR; 1439 sc->imask |= ATH9K_INT_TSFOOR;
2247 } 1440 }
2248 1441
2249 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 1442 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2250 1443
2251 if (conf->type == NL80211_IFTYPE_AP || 1444 if (vif->type == NL80211_IFTYPE_AP ||
2252 conf->type == NL80211_IFTYPE_ADHOC || 1445 vif->type == NL80211_IFTYPE_ADHOC ||
2253 conf->type == NL80211_IFTYPE_MONITOR) 1446 vif->type == NL80211_IFTYPE_MONITOR)
2254 ath_start_ani(sc); 1447 ath_start_ani(common);
2255 1448
2256out: 1449out:
2257 mutex_unlock(&sc->mutex); 1450 mutex_unlock(&sc->mutex);
@@ -2259,32 +1452,35 @@ out:
2259} 1452}
2260 1453
2261static void ath9k_remove_interface(struct ieee80211_hw *hw, 1454static void ath9k_remove_interface(struct ieee80211_hw *hw,
2262 struct ieee80211_if_init_conf *conf) 1455 struct ieee80211_vif *vif)
2263{ 1456{
2264 struct ath_wiphy *aphy = hw->priv; 1457 struct ath_wiphy *aphy = hw->priv;
2265 struct ath_softc *sc = aphy->sc; 1458 struct ath_softc *sc = aphy->sc;
2266 struct ath_vif *avp = (void *)conf->vif->drv_priv; 1459 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1460 struct ath_vif *avp = (void *)vif->drv_priv;
2267 int i; 1461 int i;
2268 1462
2269 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); 1463 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2270 1464
2271 mutex_lock(&sc->mutex); 1465 mutex_lock(&sc->mutex);
2272 1466
2273 /* Stop ANI */ 1467 /* Stop ANI */
2274 del_timer_sync(&sc->ani.timer); 1468 del_timer_sync(&common->ani.timer);
2275 1469
2276 /* Reclaim beacon resources */ 1470 /* Reclaim beacon resources */
2277 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 1471 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2278 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || 1472 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2279 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { 1473 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
1474 ath9k_ps_wakeup(sc);
2280 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1475 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2281 ath_beacon_return(sc, avp); 1476 ath9k_ps_restore(sc);
2282 } 1477 }
2283 1478
1479 ath_beacon_return(sc, avp);
2284 sc->sc_flags &= ~SC_OP_BEACONS; 1480 sc->sc_flags &= ~SC_OP_BEACONS;
2285 1481
2286 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { 1482 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2287 if (sc->beacon.bslot[i] == conf->vif) { 1483 if (sc->beacon.bslot[i] == vif) {
2288 printk(KERN_DEBUG "%s: vif had allocated beacon " 1484 printk(KERN_DEBUG "%s: vif had allocated beacon "
2289 "slot\n", __func__); 1485 "slot\n", __func__);
2290 sc->beacon.bslot[i] = NULL; 1486 sc->beacon.bslot[i] = NULL;
@@ -2297,56 +1493,92 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2297 mutex_unlock(&sc->mutex); 1493 mutex_unlock(&sc->mutex);
2298} 1494}
2299 1495
1496void ath9k_enable_ps(struct ath_softc *sc)
1497{
1498 sc->ps_enabled = true;
1499 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1500 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
1501 sc->imask |= ATH9K_INT_TIM_TIMER;
1502 ath9k_hw_set_interrupts(sc->sc_ah,
1503 sc->imask);
1504 }
1505 }
1506 ath9k_hw_setrxabort(sc->sc_ah, 1);
1507}
1508
2300static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1509static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2301{ 1510{
2302 struct ath_wiphy *aphy = hw->priv; 1511 struct ath_wiphy *aphy = hw->priv;
2303 struct ath_softc *sc = aphy->sc; 1512 struct ath_softc *sc = aphy->sc;
1513 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2304 struct ieee80211_conf *conf = &hw->conf; 1514 struct ieee80211_conf *conf = &hw->conf;
2305 struct ath_hw *ah = sc->sc_ah; 1515 struct ath_hw *ah = sc->sc_ah;
2306 bool all_wiphys_idle = false, disable_radio = false; 1516 bool disable_radio;
2307 1517
2308 mutex_lock(&sc->mutex); 1518 mutex_lock(&sc->mutex);
2309 1519
2310 /* Leave this as the first check */ 1520 /*
1521 * Leave this as the first check because we need to turn on the
1522 * radio if it was disabled before prior to processing the rest
1523 * of the changes. Likewise we must only disable the radio towards
1524 * the end.
1525 */
2311 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1526 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1527 bool enable_radio;
1528 bool all_wiphys_idle;
1529 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
2312 1530
2313 spin_lock_bh(&sc->wiphy_lock); 1531 spin_lock_bh(&sc->wiphy_lock);
2314 all_wiphys_idle = ath9k_all_wiphys_idle(sc); 1532 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
1533 ath9k_set_wiphy_idle(aphy, idle);
1534
1535 enable_radio = (!idle && all_wiphys_idle);
1536
1537 /*
1538 * After we unlock here its possible another wiphy
1539 * can be re-renabled so to account for that we will
1540 * only disable the radio toward the end of this routine
1541 * if by then all wiphys are still idle.
1542 */
2315 spin_unlock_bh(&sc->wiphy_lock); 1543 spin_unlock_bh(&sc->wiphy_lock);
2316 1544
2317 if (conf->flags & IEEE80211_CONF_IDLE){ 1545 if (enable_radio) {
2318 if (all_wiphys_idle) 1546 sc->ps_idle = false;
2319 disable_radio = true; 1547 ath_radio_enable(sc, hw);
2320 } 1548 ath_print(common, ATH_DBG_CONFIG,
2321 else if (all_wiphys_idle) { 1549 "not-idle: enabling radio\n");
2322 ath_radio_enable(sc);
2323 DPRINTF(sc, ATH_DBG_CONFIG,
2324 "not-idle: enabling radio\n");
2325 } 1550 }
2326 } 1551 }
2327 1552
1553 /*
1554 * We just prepare to enable PS. We have to wait until our AP has
1555 * ACK'd our null data frame to disable RX otherwise we'll ignore
1556 * those ACKs and end up retransmitting the same null data frames.
1557 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1558 */
2328 if (changed & IEEE80211_CONF_CHANGE_PS) { 1559 if (changed & IEEE80211_CONF_CHANGE_PS) {
2329 if (conf->flags & IEEE80211_CONF_PS) { 1560 if (conf->flags & IEEE80211_CONF_PS) {
2330 if (!(ah->caps.hw_caps & 1561 sc->ps_flags |= PS_ENABLED;
2331 ATH9K_HW_CAP_AUTOSLEEP)) { 1562 /*
2332 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) { 1563 * At this point we know hardware has received an ACK
2333 sc->imask |= ATH9K_INT_TIM_TIMER; 1564 * of a previously sent null data frame.
2334 ath9k_hw_set_interrupts(sc->sc_ah, 1565 */
2335 sc->imask); 1566 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
2336 } 1567 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
2337 ath9k_hw_setrxabort(sc->sc_ah, 1); 1568 ath9k_enable_ps(sc);
2338 } 1569 }
2339 sc->ps_enabled = true;
2340 } else { 1570 } else {
2341 sc->ps_enabled = false; 1571 sc->ps_enabled = false;
2342 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 1572 sc->ps_flags &= ~(PS_ENABLED |
1573 PS_NULLFUNC_COMPLETED);
1574 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2343 if (!(ah->caps.hw_caps & 1575 if (!(ah->caps.hw_caps &
2344 ATH9K_HW_CAP_AUTOSLEEP)) { 1576 ATH9K_HW_CAP_AUTOSLEEP)) {
2345 ath9k_hw_setrxabort(sc->sc_ah, 0); 1577 ath9k_hw_setrxabort(sc->sc_ah, 0);
2346 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON | 1578 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
2347 SC_OP_WAIT_FOR_CAB | 1579 PS_WAIT_FOR_CAB |
2348 SC_OP_WAIT_FOR_PSPOLL_DATA | 1580 PS_WAIT_FOR_PSPOLL_DATA |
2349 SC_OP_WAIT_FOR_TX_ACK); 1581 PS_WAIT_FOR_TX_ACK);
2350 if (sc->imask & ATH9K_INT_TIM_TIMER) { 1582 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2351 sc->imask &= ~ATH9K_INT_TIM_TIMER; 1583 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2352 ath9k_hw_set_interrupts(sc->sc_ah, 1584 ath9k_hw_set_interrupts(sc->sc_ah,
@@ -2356,6 +1588,14 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2356 } 1588 }
2357 } 1589 }
2358 1590
1591 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1592 if (conf->flags & IEEE80211_CONF_MONITOR) {
1593 ath_print(common, ATH_DBG_CONFIG,
1594 "HW opmode set to Monitor mode\n");
1595 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1596 }
1597 }
1598
2359 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1599 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2360 struct ieee80211_channel *curchan = hw->conf.channel; 1600 struct ieee80211_channel *curchan = hw->conf.channel;
2361 int pos = curchan->hw_value; 1601 int pos = curchan->hw_value;
@@ -2374,8 +1614,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2374 goto skip_chan_change; 1614 goto skip_chan_change;
2375 } 1615 }
2376 1616
2377 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 1617 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2378 curchan->center_freq); 1618 curchan->center_freq);
2379 1619
2380 /* XXX: remove me eventualy */ 1620 /* XXX: remove me eventualy */
2381 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 1621 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
@@ -2383,19 +1623,27 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2383 ath_update_chainmask(sc, conf_is_ht(conf)); 1623 ath_update_chainmask(sc, conf_is_ht(conf));
2384 1624
2385 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1625 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2386 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); 1626 ath_print(common, ATH_DBG_FATAL,
1627 "Unable to set channel\n");
2387 mutex_unlock(&sc->mutex); 1628 mutex_unlock(&sc->mutex);
2388 return -EINVAL; 1629 return -EINVAL;
2389 } 1630 }
2390 } 1631 }
2391 1632
2392skip_chan_change: 1633skip_chan_change:
2393 if (changed & IEEE80211_CONF_CHANGE_POWER) 1634 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2394 sc->config.txpowlimit = 2 * conf->power_level; 1635 sc->config.txpowlimit = 2 * conf->power_level;
1636 ath_update_txpow(sc);
1637 }
1638
1639 spin_lock_bh(&sc->wiphy_lock);
1640 disable_radio = ath9k_all_wiphys_idle(sc);
1641 spin_unlock_bh(&sc->wiphy_lock);
2395 1642
2396 if (disable_radio) { 1643 if (disable_radio) {
2397 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n"); 1644 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2398 ath_radio_disable(sc); 1645 sc->ps_idle = true;
1646 ath_radio_disable(sc, hw);
2399 } 1647 }
2400 1648
2401 mutex_unlock(&sc->mutex); 1649 mutex_unlock(&sc->mutex);
@@ -2431,27 +1679,32 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2431 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1679 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2432 ath9k_ps_restore(sc); 1680 ath9k_ps_restore(sc);
2433 1681
2434 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt); 1682 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1683 "Set HW RX filter: 0x%x\n", rfilt);
2435} 1684}
2436 1685
2437static void ath9k_sta_notify(struct ieee80211_hw *hw, 1686static int ath9k_sta_add(struct ieee80211_hw *hw,
2438 struct ieee80211_vif *vif, 1687 struct ieee80211_vif *vif,
2439 enum sta_notify_cmd cmd, 1688 struct ieee80211_sta *sta)
2440 struct ieee80211_sta *sta)
2441{ 1689{
2442 struct ath_wiphy *aphy = hw->priv; 1690 struct ath_wiphy *aphy = hw->priv;
2443 struct ath_softc *sc = aphy->sc; 1691 struct ath_softc *sc = aphy->sc;
2444 1692
2445 switch (cmd) { 1693 ath_node_attach(sc, sta);
2446 case STA_NOTIFY_ADD: 1694
2447 ath_node_attach(sc, sta); 1695 return 0;
2448 break; 1696}
2449 case STA_NOTIFY_REMOVE: 1697
2450 ath_node_detach(sc, sta); 1698static int ath9k_sta_remove(struct ieee80211_hw *hw,
2451 break; 1699 struct ieee80211_vif *vif,
2452 default: 1700 struct ieee80211_sta *sta)
2453 break; 1701{
2454 } 1702 struct ath_wiphy *aphy = hw->priv;
1703 struct ath_softc *sc = aphy->sc;
1704
1705 ath_node_detach(sc, sta);
1706
1707 return 0;
2455} 1708}
2456 1709
2457static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, 1710static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
@@ -2459,6 +1712,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2459{ 1712{
2460 struct ath_wiphy *aphy = hw->priv; 1713 struct ath_wiphy *aphy = hw->priv;
2461 struct ath_softc *sc = aphy->sc; 1714 struct ath_softc *sc = aphy->sc;
1715 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2462 struct ath9k_tx_queue_info qi; 1716 struct ath9k_tx_queue_info qi;
2463 int ret = 0, qnum; 1717 int ret = 0, qnum;
2464 1718
@@ -2475,15 +1729,19 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2475 qi.tqi_burstTime = params->txop; 1729 qi.tqi_burstTime = params->txop;
2476 qnum = ath_get_hal_qnum(queue, sc); 1730 qnum = ath_get_hal_qnum(queue, sc);
2477 1731
2478 DPRINTF(sc, ATH_DBG_CONFIG, 1732 ath_print(common, ATH_DBG_CONFIG,
2479 "Configure tx [queue/halq] [%d/%d], " 1733 "Configure tx [queue/halq] [%d/%d], "
2480 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1734 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2481 queue, qnum, params->aifs, params->cw_min, 1735 queue, qnum, params->aifs, params->cw_min,
2482 params->cw_max, params->txop); 1736 params->cw_max, params->txop);
2483 1737
2484 ret = ath_txq_update(sc, qnum, &qi); 1738 ret = ath_txq_update(sc, qnum, &qi);
2485 if (ret) 1739 if (ret)
2486 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n"); 1740 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
1741
1742 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1743 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
1744 ath_beaconq_config(sc);
2487 1745
2488 mutex_unlock(&sc->mutex); 1746 mutex_unlock(&sc->mutex);
2489 1747
@@ -2498,6 +1756,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2498{ 1756{
2499 struct ath_wiphy *aphy = hw->priv; 1757 struct ath_wiphy *aphy = hw->priv;
2500 struct ath_softc *sc = aphy->sc; 1758 struct ath_softc *sc = aphy->sc;
1759 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2501 int ret = 0; 1760 int ret = 0;
2502 1761
2503 if (modparam_nohwcrypt) 1762 if (modparam_nohwcrypt)
@@ -2505,11 +1764,11 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2505 1764
2506 mutex_lock(&sc->mutex); 1765 mutex_lock(&sc->mutex);
2507 ath9k_ps_wakeup(sc); 1766 ath9k_ps_wakeup(sc);
2508 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n"); 1767 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2509 1768
2510 switch (cmd) { 1769 switch (cmd) {
2511 case SET_KEY: 1770 case SET_KEY:
2512 ret = ath_key_config(sc, vif, sta, key); 1771 ret = ath_key_config(common, vif, sta, key);
2513 if (ret >= 0) { 1772 if (ret >= 0) {
2514 key->hw_key_idx = ret; 1773 key->hw_key_idx = ret;
2515 /* push IV and Michael MIC generation to stack */ 1774 /* push IV and Michael MIC generation to stack */
@@ -2522,7 +1781,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2522 } 1781 }
2523 break; 1782 break;
2524 case DISABLE_KEY: 1783 case DISABLE_KEY:
2525 ath_key_delete(sc, key); 1784 ath_key_delete(common, key);
2526 break; 1785 break;
2527 default: 1786 default:
2528 ret = -EINVAL; 1787 ret = -EINVAL;
@@ -2542,94 +1801,87 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2542 struct ath_wiphy *aphy = hw->priv; 1801 struct ath_wiphy *aphy = hw->priv;
2543 struct ath_softc *sc = aphy->sc; 1802 struct ath_softc *sc = aphy->sc;
2544 struct ath_hw *ah = sc->sc_ah; 1803 struct ath_hw *ah = sc->sc_ah;
1804 struct ath_common *common = ath9k_hw_common(ah);
2545 struct ath_vif *avp = (void *)vif->drv_priv; 1805 struct ath_vif *avp = (void *)vif->drv_priv;
2546 u32 rfilt = 0; 1806 int slottime;
2547 int error, i; 1807 int error;
2548 1808
2549 mutex_lock(&sc->mutex); 1809 mutex_lock(&sc->mutex);
2550 1810
2551 /* 1811 if (changed & BSS_CHANGED_BSSID) {
2552 * TODO: Need to decide which hw opmode to use for 1812 /* Set BSSID */
2553 * multi-interface cases 1813 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2554 * XXX: This belongs into add_interface! 1814 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2555 */ 1815 common->curaid = 0;
2556 if (vif->type == NL80211_IFTYPE_AP && 1816 ath9k_hw_write_associd(ah);
2557 ah->opmode != NL80211_IFTYPE_AP) {
2558 ah->opmode = NL80211_IFTYPE_STATION;
2559 ath9k_hw_setopmode(ah);
2560 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2561 sc->curaid = 0;
2562 ath9k_hw_write_associd(sc);
2563 /* Request full reset to get hw opmode changed properly */
2564 sc->sc_flags |= SC_OP_FULL_RESET;
2565 }
2566
2567 if ((changed & BSS_CHANGED_BSSID) &&
2568 !is_zero_ether_addr(bss_conf->bssid)) {
2569 switch (vif->type) {
2570 case NL80211_IFTYPE_STATION:
2571 case NL80211_IFTYPE_ADHOC:
2572 case NL80211_IFTYPE_MESH_POINT:
2573 /* Set BSSID */
2574 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2575 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2576 sc->curaid = 0;
2577 ath9k_hw_write_associd(sc);
2578
2579 /* Set aggregation protection mode parameters */
2580 sc->config.ath_aggr_prot = 0;
2581
2582 DPRINTF(sc, ATH_DBG_CONFIG,
2583 "RX filter 0x%x bssid %pM aid 0x%x\n",
2584 rfilt, sc->curbssid, sc->curaid);
2585
2586 /* need to reconfigure the beacon */
2587 sc->sc_flags &= ~SC_OP_BEACONS ;
2588 1817
2589 break; 1818 /* Set aggregation protection mode parameters */
2590 default: 1819 sc->config.ath_aggr_prot = 0;
2591 break; 1820
2592 } 1821 /* Only legacy IBSS for now */
1822 if (vif->type == NL80211_IFTYPE_ADHOC)
1823 ath_update_chainmask(sc, 0);
1824
1825 ath_print(common, ATH_DBG_CONFIG,
1826 "BSSID: %pM aid: 0x%x\n",
1827 common->curbssid, common->curaid);
1828
1829 /* need to reconfigure the beacon */
1830 sc->sc_flags &= ~SC_OP_BEACONS ;
2593 } 1831 }
2594 1832
2595 if ((vif->type == NL80211_IFTYPE_ADHOC) || 1833 /* Enable transmission of beacons (AP, IBSS, MESH) */
2596 (vif->type == NL80211_IFTYPE_AP) || 1834 if ((changed & BSS_CHANGED_BEACON) ||
2597 (vif->type == NL80211_IFTYPE_MESH_POINT)) { 1835 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2598 if ((changed & BSS_CHANGED_BEACON) || 1836 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2599 (changed & BSS_CHANGED_BEACON_ENABLED && 1837 error = ath_beacon_alloc(aphy, vif);
2600 bss_conf->enable_beacon)) { 1838 if (!error)
1839 ath_beacon_config(sc, vif);
1840 }
1841
1842 if (changed & BSS_CHANGED_ERP_SLOT) {
1843 if (bss_conf->use_short_slot)
1844 slottime = 9;
1845 else
1846 slottime = 20;
1847 if (vif->type == NL80211_IFTYPE_AP) {
2601 /* 1848 /*
2602 * Allocate and setup the beacon frame. 1849 * Defer update, so that connected stations can adjust
2603 * 1850 * their settings at the same time.
2604 * Stop any previous beacon DMA. This may be 1851 * See beacon.c for more details
2605 * necessary, for example, when an ibss merge
2606 * causes reconfiguration; we may be called
2607 * with beacon transmission active.
2608 */ 1852 */
2609 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1853 sc->beacon.slottime = slottime;
1854 sc->beacon.updateslot = UPDATE;
1855 } else {
1856 ah->slottime = slottime;
1857 ath9k_hw_init_global_settings(ah);
1858 }
1859 }
1860
1861 /* Disable transmission of beacons */
1862 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1863 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2610 1864
1865 if (changed & BSS_CHANGED_BEACON_INT) {
1866 sc->beacon_interval = bss_conf->beacon_int;
1867 /*
1868 * In case of AP mode, the HW TSF has to be reset
1869 * when the beacon interval changes.
1870 */
1871 if (vif->type == NL80211_IFTYPE_AP) {
1872 sc->sc_flags |= SC_OP_TSF_RESET;
1873 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2611 error = ath_beacon_alloc(aphy, vif); 1874 error = ath_beacon_alloc(aphy, vif);
2612 if (!error) 1875 if (!error)
2613 ath_beacon_config(sc, vif); 1876 ath_beacon_config(sc, vif);
1877 } else {
1878 ath_beacon_config(sc, vif);
2614 } 1879 }
2615 } 1880 }
2616 1881
2617 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2618 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2619 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2620 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2621 ath9k_hw_keysetmac(sc->sc_ah,
2622 (u16)i,
2623 sc->curbssid);
2624 }
2625
2626 /* Only legacy IBSS for now */
2627 if (vif->type == NL80211_IFTYPE_ADHOC)
2628 ath_update_chainmask(sc, 0);
2629
2630 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1882 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2631 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 1883 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2632 bss_conf->use_short_preamble); 1884 bss_conf->use_short_preamble);
2633 if (bss_conf->use_short_preamble) 1885 if (bss_conf->use_short_preamble)
2634 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 1886 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2635 else 1887 else
@@ -2637,8 +1889,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2637 } 1889 }
2638 1890
2639 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1891 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2640 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 1892 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2641 bss_conf->use_cts_prot); 1893 bss_conf->use_cts_prot);
2642 if (bss_conf->use_cts_prot && 1894 if (bss_conf->use_cts_prot &&
2643 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 1895 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2644 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 1896 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -2647,23 +1899,11 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2647 } 1899 }
2648 1900
2649 if (changed & BSS_CHANGED_ASSOC) { 1901 if (changed & BSS_CHANGED_ASSOC) {
2650 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 1902 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2651 bss_conf->assoc); 1903 bss_conf->assoc);
2652 ath9k_bss_assoc_info(sc, vif, bss_conf); 1904 ath9k_bss_assoc_info(sc, vif, bss_conf);
2653 } 1905 }
2654 1906
2655 /*
2656 * The HW TSF has to be reset when the beacon interval changes.
2657 * We set the flag here, and ath_beacon_config_ap() would take this
2658 * into account when it gets called through the subsequent
2659 * config_interface() call - with IFCC_BEACON in the changed field.
2660 */
2661
2662 if (changed & BSS_CHANGED_BEACON_INT) {
2663 sc->sc_flags |= SC_OP_TSF_RESET;
2664 sc->beacon_interval = bss_conf->beacon_int;
2665 }
2666
2667 mutex_unlock(&sc->mutex); 1907 mutex_unlock(&sc->mutex);
2668} 1908}
2669 1909
@@ -2696,11 +1936,16 @@ static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2696 struct ath_softc *sc = aphy->sc; 1936 struct ath_softc *sc = aphy->sc;
2697 1937
2698 mutex_lock(&sc->mutex); 1938 mutex_lock(&sc->mutex);
1939
1940 ath9k_ps_wakeup(sc);
2699 ath9k_hw_reset_tsf(sc->sc_ah); 1941 ath9k_hw_reset_tsf(sc->sc_ah);
1942 ath9k_ps_restore(sc);
1943
2700 mutex_unlock(&sc->mutex); 1944 mutex_unlock(&sc->mutex);
2701} 1945}
2702 1946
2703static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1947static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1948 struct ieee80211_vif *vif,
2704 enum ieee80211_ampdu_mlme_action action, 1949 enum ieee80211_ampdu_mlme_action action,
2705 struct ieee80211_sta *sta, 1950 struct ieee80211_sta *sta,
2706 u16 tid, u16 *ssn) 1951 u16 tid, u16 *ssn)
@@ -2717,18 +1962,25 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2717 case IEEE80211_AMPDU_RX_STOP: 1962 case IEEE80211_AMPDU_RX_STOP:
2718 break; 1963 break;
2719 case IEEE80211_AMPDU_TX_START: 1964 case IEEE80211_AMPDU_TX_START:
1965 ath9k_ps_wakeup(sc);
2720 ath_tx_aggr_start(sc, sta, tid, ssn); 1966 ath_tx_aggr_start(sc, sta, tid, ssn);
2721 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); 1967 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1968 ath9k_ps_restore(sc);
2722 break; 1969 break;
2723 case IEEE80211_AMPDU_TX_STOP: 1970 case IEEE80211_AMPDU_TX_STOP:
1971 ath9k_ps_wakeup(sc);
2724 ath_tx_aggr_stop(sc, sta, tid); 1972 ath_tx_aggr_stop(sc, sta, tid);
2725 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); 1973 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1974 ath9k_ps_restore(sc);
2726 break; 1975 break;
2727 case IEEE80211_AMPDU_TX_OPERATIONAL: 1976 case IEEE80211_AMPDU_TX_OPERATIONAL:
1977 ath9k_ps_wakeup(sc);
2728 ath_tx_aggr_resume(sc, sta, tid); 1978 ath_tx_aggr_resume(sc, sta, tid);
1979 ath9k_ps_restore(sc);
2729 break; 1980 break;
2730 default: 1981 default:
2731 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n"); 1982 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1983 "Unknown AMPDU action\n");
2732 } 1984 }
2733 1985
2734 return ret; 1986 return ret;
@@ -2738,6 +1990,7 @@ static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2738{ 1990{
2739 struct ath_wiphy *aphy = hw->priv; 1991 struct ath_wiphy *aphy = hw->priv;
2740 struct ath_softc *sc = aphy->sc; 1992 struct ath_softc *sc = aphy->sc;
1993 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2741 1994
2742 mutex_lock(&sc->mutex); 1995 mutex_lock(&sc->mutex);
2743 if (ath9k_wiphy_scanning(sc)) { 1996 if (ath9k_wiphy_scanning(sc)) {
@@ -2753,10 +2006,9 @@ static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2753 2006
2754 aphy->state = ATH_WIPHY_SCAN; 2007 aphy->state = ATH_WIPHY_SCAN;
2755 ath9k_wiphy_pause_all_forced(sc, aphy); 2008 ath9k_wiphy_pause_all_forced(sc, aphy);
2756
2757 spin_lock_bh(&sc->ani_lock);
2758 sc->sc_flags |= SC_OP_SCANNING; 2009 sc->sc_flags |= SC_OP_SCANNING;
2759 spin_unlock_bh(&sc->ani_lock); 2010 del_timer_sync(&common->ani.timer);
2011 cancel_delayed_work_sync(&sc->tx_complete_work);
2760 mutex_unlock(&sc->mutex); 2012 mutex_unlock(&sc->mutex);
2761} 2013}
2762 2014
@@ -2764,17 +2016,30 @@ static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2764{ 2016{
2765 struct ath_wiphy *aphy = hw->priv; 2017 struct ath_wiphy *aphy = hw->priv;
2766 struct ath_softc *sc = aphy->sc; 2018 struct ath_softc *sc = aphy->sc;
2019 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2767 2020
2768 mutex_lock(&sc->mutex); 2021 mutex_lock(&sc->mutex);
2769 spin_lock_bh(&sc->ani_lock);
2770 aphy->state = ATH_WIPHY_ACTIVE; 2022 aphy->state = ATH_WIPHY_ACTIVE;
2771 sc->sc_flags &= ~SC_OP_SCANNING; 2023 sc->sc_flags &= ~SC_OP_SCANNING;
2772 sc->sc_flags |= SC_OP_FULL_RESET; 2024 sc->sc_flags |= SC_OP_FULL_RESET;
2773 spin_unlock_bh(&sc->ani_lock); 2025 ath_start_ani(common);
2026 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2774 ath_beacon_config(sc, NULL); 2027 ath_beacon_config(sc, NULL);
2775 mutex_unlock(&sc->mutex); 2028 mutex_unlock(&sc->mutex);
2776} 2029}
2777 2030
2031static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2032{
2033 struct ath_wiphy *aphy = hw->priv;
2034 struct ath_softc *sc = aphy->sc;
2035 struct ath_hw *ah = sc->sc_ah;
2036
2037 mutex_lock(&sc->mutex);
2038 ah->coverage_class = coverage_class;
2039 ath9k_hw_init_global_settings(ah);
2040 mutex_unlock(&sc->mutex);
2041}
2042
2778struct ieee80211_ops ath9k_ops = { 2043struct ieee80211_ops ath9k_ops = {
2779 .tx = ath9k_tx, 2044 .tx = ath9k_tx,
2780 .start = ath9k_start, 2045 .start = ath9k_start,
@@ -2783,7 +2048,8 @@ struct ieee80211_ops ath9k_ops = {
2783 .remove_interface = ath9k_remove_interface, 2048 .remove_interface = ath9k_remove_interface,
2784 .config = ath9k_config, 2049 .config = ath9k_config,
2785 .configure_filter = ath9k_configure_filter, 2050 .configure_filter = ath9k_configure_filter,
2786 .sta_notify = ath9k_sta_notify, 2051 .sta_add = ath9k_sta_add,
2052 .sta_remove = ath9k_sta_remove,
2787 .conf_tx = ath9k_conf_tx, 2053 .conf_tx = ath9k_conf_tx,
2788 .bss_info_changed = ath9k_bss_info_changed, 2054 .bss_info_changed = ath9k_bss_info_changed,
2789 .set_key = ath9k_set_key, 2055 .set_key = ath9k_set_key,
@@ -2794,122 +2060,5 @@ struct ieee80211_ops ath9k_ops = {
2794 .sw_scan_start = ath9k_sw_scan_start, 2060 .sw_scan_start = ath9k_sw_scan_start,
2795 .sw_scan_complete = ath9k_sw_scan_complete, 2061 .sw_scan_complete = ath9k_sw_scan_complete,
2796 .rfkill_poll = ath9k_rfkill_poll_state, 2062 .rfkill_poll = ath9k_rfkill_poll_state,
2063 .set_coverage_class = ath9k_set_coverage_class,
2797}; 2064};
2798
2799static struct {
2800 u32 version;
2801 const char * name;
2802} ath_mac_bb_names[] = {
2803 { AR_SREV_VERSION_5416_PCI, "5416" },
2804 { AR_SREV_VERSION_5416_PCIE, "5418" },
2805 { AR_SREV_VERSION_9100, "9100" },
2806 { AR_SREV_VERSION_9160, "9160" },
2807 { AR_SREV_VERSION_9280, "9280" },
2808 { AR_SREV_VERSION_9285, "9285" },
2809 { AR_SREV_VERSION_9287, "9287" }
2810};
2811
2812static struct {
2813 u16 version;
2814 const char * name;
2815} ath_rf_names[] = {
2816 { 0, "5133" },
2817 { AR_RAD5133_SREV_MAJOR, "5133" },
2818 { AR_RAD5122_SREV_MAJOR, "5122" },
2819 { AR_RAD2133_SREV_MAJOR, "2133" },
2820 { AR_RAD2122_SREV_MAJOR, "2122" }
2821};
2822
2823/*
2824 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2825 */
2826const char *
2827ath_mac_bb_name(u32 mac_bb_version)
2828{
2829 int i;
2830
2831 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2832 if (ath_mac_bb_names[i].version == mac_bb_version) {
2833 return ath_mac_bb_names[i].name;
2834 }
2835 }
2836
2837 return "????";
2838}
2839
2840/*
2841 * Return the RF name. "????" is returned if the RF is unknown.
2842 */
2843const char *
2844ath_rf_name(u16 rf_version)
2845{
2846 int i;
2847
2848 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2849 if (ath_rf_names[i].version == rf_version) {
2850 return ath_rf_names[i].name;
2851 }
2852 }
2853
2854 return "????";
2855}
2856
2857static int __init ath9k_init(void)
2858{
2859 int error;
2860
2861 /* Register rate control algorithm */
2862 error = ath_rate_control_register();
2863 if (error != 0) {
2864 printk(KERN_ERR
2865 "ath9k: Unable to register rate control "
2866 "algorithm: %d\n",
2867 error);
2868 goto err_out;
2869 }
2870
2871 error = ath9k_debug_create_root();
2872 if (error) {
2873 printk(KERN_ERR
2874 "ath9k: Unable to create debugfs root: %d\n",
2875 error);
2876 goto err_rate_unregister;
2877 }
2878
2879 error = ath_pci_init();
2880 if (error < 0) {
2881 printk(KERN_ERR
2882 "ath9k: No PCI devices found, driver not installed.\n");
2883 error = -ENODEV;
2884 goto err_remove_root;
2885 }
2886
2887 error = ath_ahb_init();
2888 if (error < 0) {
2889 error = -ENODEV;
2890 goto err_pci_exit;
2891 }
2892
2893 return 0;
2894
2895 err_pci_exit:
2896 ath_pci_exit();
2897
2898 err_remove_root:
2899 ath9k_debug_remove_root();
2900 err_rate_unregister:
2901 ath_rate_control_unregister();
2902 err_out:
2903 return error;
2904}
2905module_init(ath9k_init);
2906
2907static void __exit ath9k_exit(void)
2908{
2909 ath_ahb_exit();
2910 ath_pci_exit();
2911 ath9k_debug_remove_root();
2912 ath_rate_control_unregister();
2913 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2914}
2915module_exit(ath9k_exit);
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 903dd8ad9d43..9441c6718a30 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -18,21 +18,23 @@
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include "ath9k.h" 19#include "ath9k.h"
20 20
21static struct pci_device_id ath_pci_id_table[] __devinitdata = { 21static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
28 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
28 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 29 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
29 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 30 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
30 { 0 } 31 { 0 }
31}; 32};
32 33
33/* return bus cachesize in 4B word units */ 34/* return bus cachesize in 4B word units */
34static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz) 35static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
35{ 36{
37 struct ath_softc *sc = (struct ath_softc *) common->priv;
36 u8 u8tmp; 38 u8 u8tmp;
37 39
38 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 40 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
@@ -48,18 +50,11 @@ static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
48 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 50 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
49} 51}
50 52
51static void ath_pci_cleanup(struct ath_softc *sc) 53static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
52{ 54{
53 struct pci_dev *pdev = to_pci_dev(sc->dev); 55 struct ath_hw *ah = (struct ath_hw *) common->ah;
54
55 pci_iounmap(pdev, sc->mem);
56 pci_disable_device(pdev);
57 pci_release_region(pdev, 0);
58}
59 56
60static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) 57 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
61{
62 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
63 58
64 if (!ath9k_hw_wait(ah, 59 if (!ath9k_hw_wait(ah,
65 AR_EEPROM_STATUS_DATA, 60 AR_EEPROM_STATUS_DATA,
@@ -69,16 +64,33 @@ static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
69 return false; 64 return false;
70 } 65 }
71 66
72 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 67 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
73 AR_EEPROM_STATUS_DATA_VAL); 68 AR_EEPROM_STATUS_DATA_VAL);
74 69
75 return true; 70 return true;
76} 71}
77 72
78static struct ath_bus_ops ath_pci_bus_ops = { 73/*
74 * Bluetooth coexistance requires disabling ASPM.
75 */
76static void ath_pci_bt_coex_prep(struct ath_common *common)
77{
78 struct ath_softc *sc = (struct ath_softc *) common->priv;
79 struct pci_dev *pdev = to_pci_dev(sc->dev);
80 u8 aspm;
81
82 if (!pdev->is_pcie)
83 return;
84
85 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
86 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
87 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
88}
89
90static const struct ath_bus_ops ath_pci_bus_ops = {
79 .read_cachesize = ath_pci_read_cachesize, 91 .read_cachesize = ath_pci_read_cachesize,
80 .cleanup = ath_pci_cleanup,
81 .eeprom_read = ath_pci_eeprom_read, 92 .eeprom_read = ath_pci_eeprom_read,
93 .bt_coex_prep = ath_pci_bt_coex_prep,
82}; 94};
83 95
84static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 96static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
@@ -91,24 +103,22 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
91 u16 subsysid; 103 u16 subsysid;
92 u32 val; 104 u32 val;
93 int ret = 0; 105 int ret = 0;
94 struct ath_hw *ah; 106 char hw_name[64];
95 107
96 if (pci_enable_device(pdev)) 108 if (pci_enable_device(pdev))
97 return -EIO; 109 return -EIO;
98 110
99 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 111 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
100
101 if (ret) { 112 if (ret) {
102 printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); 113 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
103 goto bad; 114 goto err_dma;
104 } 115 }
105 116
106 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 117 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
107
108 if (ret) { 118 if (ret) {
109 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 119 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
110 "DMA enable failed\n"); 120 "DMA enable failed\n");
111 goto bad; 121 goto err_dma;
112 } 122 }
113 123
114 /* 124 /*
@@ -148,22 +158,22 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
148 if (ret) { 158 if (ret) {
149 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 159 dev_err(&pdev->dev, "PCI memory region reserve error\n");
150 ret = -ENODEV; 160 ret = -ENODEV;
151 goto bad; 161 goto err_region;
152 } 162 }
153 163
154 mem = pci_iomap(pdev, 0, 0); 164 mem = pci_iomap(pdev, 0, 0);
155 if (!mem) { 165 if (!mem) {
156 printk(KERN_ERR "PCI memory map error\n") ; 166 printk(KERN_ERR "PCI memory map error\n") ;
157 ret = -EIO; 167 ret = -EIO;
158 goto bad1; 168 goto err_iomap;
159 } 169 }
160 170
161 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) + 171 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
162 sizeof(struct ath_softc), &ath9k_ops); 172 sizeof(struct ath_softc), &ath9k_ops);
163 if (!hw) { 173 if (!hw) {
164 dev_err(&pdev->dev, "no memory for ieee80211_hw\n"); 174 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
165 ret = -ENOMEM; 175 ret = -ENOMEM;
166 goto bad2; 176 goto err_alloc_hw;
167 } 177 }
168 178
169 SET_IEEE80211_DEV(hw, &pdev->dev); 179 SET_IEEE80211_DEV(hw, &pdev->dev);
@@ -177,46 +187,45 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
177 sc->hw = hw; 187 sc->hw = hw;
178 sc->dev = &pdev->dev; 188 sc->dev = &pdev->dev;
179 sc->mem = mem; 189 sc->mem = mem;
180 sc->bus_ops = &ath_pci_bus_ops;
181 190
182 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid); 191 /* Will be cleared in ath9k_start() */
183 ret = ath_init_device(id->device, sc, subsysid); 192 sc->sc_flags |= SC_OP_INVALID;
184 if (ret) {
185 dev_err(&pdev->dev, "failed to initialize device\n");
186 goto bad3;
187 }
188
189 /* setup interrupt service routine */
190 193
191 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 194 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
192 if (ret) { 195 if (ret) {
193 dev_err(&pdev->dev, "request_irq failed\n"); 196 dev_err(&pdev->dev, "request_irq failed\n");
194 goto bad4; 197 goto err_irq;
195 } 198 }
196 199
197 sc->irq = pdev->irq; 200 sc->irq = pdev->irq;
198 201
199 ah = sc->sc_ah; 202 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
203 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
204 if (ret) {
205 dev_err(&pdev->dev, "Failed to initialize device\n");
206 goto err_init;
207 }
208
209 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
200 printk(KERN_INFO 210 printk(KERN_INFO
201 "%s: Atheros AR%s MAC/BB Rev:%x " 211 "%s: %s mem=0x%lx, irq=%d\n",
202 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
203 wiphy_name(hw->wiphy), 212 wiphy_name(hw->wiphy),
204 ath_mac_bb_name(ah->hw_version.macVersion), 213 hw_name,
205 ah->hw_version.macRev,
206 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
207 ah->hw_version.phyRev,
208 (unsigned long)mem, pdev->irq); 214 (unsigned long)mem, pdev->irq);
209 215
210 return 0; 216 return 0;
211bad4: 217
212 ath_detach(sc); 218err_init:
213bad3: 219 free_irq(sc->irq, sc);
220err_irq:
214 ieee80211_free_hw(hw); 221 ieee80211_free_hw(hw);
215bad2: 222err_alloc_hw:
216 pci_iounmap(pdev, mem); 223 pci_iounmap(pdev, mem);
217bad1: 224err_iomap:
218 pci_release_region(pdev, 0); 225 pci_release_region(pdev, 0);
219bad: 226err_region:
227 /* Nothing */
228err_dma:
220 pci_disable_device(pdev); 229 pci_disable_device(pdev);
221 return ret; 230 return ret;
222} 231}
@@ -226,8 +235,15 @@ static void ath_pci_remove(struct pci_dev *pdev)
226 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 235 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
227 struct ath_wiphy *aphy = hw->priv; 236 struct ath_wiphy *aphy = hw->priv;
228 struct ath_softc *sc = aphy->sc; 237 struct ath_softc *sc = aphy->sc;
238 void __iomem *mem = sc->mem;
239
240 ath9k_deinit_device(sc);
241 free_irq(sc->irq, sc);
242 ieee80211_free_hw(sc->hw);
229 243
230 ath_cleanup(sc); 244 pci_iounmap(pdev, mem);
245 pci_disable_device(pdev);
246 pci_release_region(pdev, 0);
231} 247}
232 248
233#ifdef CONFIG_PM 249#ifdef CONFIG_PM
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index 63bf9a307c6a..2547b3c4a26c 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -14,90 +14,72 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17/**
18 18 * DOC: Programming Atheros 802.11n analog front end radios
19void 19 *
20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, 20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 int regWrites) 21 * devices have either an external AR2133 analog front end radio for single
22{ 22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 23 * band 2.4 GHz / 5 GHz communication.
24} 24 *
25 25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26bool 26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 27 * into a single-chip and require less programming.
28{ 28 *
29 u32 channelSel = 0; 29 * The following single-chips exist with a respective embedded radio:
30 u32 bModeSynth = 0; 30 *
31 u32 aModeRefSel = 0; 31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 u32 reg32 = 0; 32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 u16 freq; 33 * AR9285 - 11n single-band 1x1 for PCIe
34 struct chan_centers centers; 34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 35 *
36 ath9k_hw_get_channel_centers(ah, chan, &centers); 36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 freq = centers.synth_center; 37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 38 *
39 if (freq < 4800) { 39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 u32 txctl; 40 */
41
42 if (((freq - 2192) % 5) == 0) {
43 channelSel = ((freq - 672) * 2 - 3040) / 10;
44 bModeSynth = 0;
45 } else if (((freq - 2224) % 5) == 0) {
46 channelSel = ((freq - 704) * 2 - 3040) / 10;
47 bModeSynth = 1;
48 } else {
49 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
50 "Invalid channel %u MHz\n", freq);
51 return false;
52 }
53
54 channelSel = (channelSel << 2) & 0xff;
55 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
56
57 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
58 if (freq == 2484) {
59
60 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
61 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
62 } else {
63 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
64 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
65 }
66
67 } else if ((freq % 20) == 0 && freq >= 5120) {
68 channelSel =
69 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
70 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
71 } else if ((freq % 10) == 0) {
72 channelSel =
73 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
74 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
75 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
76 else
77 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
78 } else if ((freq % 5) == 0) {
79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
80 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
81 } else {
82 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
83 "Invalid channel %u MHz\n", freq);
84 return false;
85 }
86
87 reg32 =
88 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
89 (1 << 5) | 0x1;
90 41
91 REG_WRITE(ah, AR_PHY(0x37), reg32); 42#include <linux/slab.h>
92 43
93 ah->curchan = chan; 44#include "hw.h"
94 ah->curchan_rad_index = -1;
95 45
96 return true; 46/**
47 * ath9k_hw_write_regs - ??
48 *
49 * @ah: atheros hardware structure
50 * @freqIndex:
51 * @regWrites:
52 *
53 * Used for both the chipsets with an external AR2133/AR5133 radios and
54 * single-chip devices.
55 */
56void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
57{
58 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
97} 59}
98 60
99void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 61/**
100 struct ath9k_channel *chan) 62 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
63 * @ah: atheros hardware structure
64 * @chan:
65 *
66 * This is the function to change channel on single-chip devices, that is
67 * all devices after ar9280.
68 *
69 * This function takes the channel value in MHz and sets
70 * hardware channel value. Assumes writes have been enabled to analog bus.
71 *
72 * Actual Expression,
73 *
74 * For 2GHz channel,
75 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
76 * (freq_ref = 40MHz)
77 *
78 * For 5GHz channel,
79 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
80 * (freq_ref = 40MHz/(24>>amodeRefSel))
81 */
82int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
101{ 83{
102 u16 bMode, fracMode, aModeRefSel = 0; 84 u16 bMode, fracMode, aModeRefSel = 0;
103 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; 85 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
@@ -110,22 +92,34 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
110 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); 92 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
111 reg32 &= 0xc0000000; 93 reg32 &= 0xc0000000;
112 94
113 if (freq < 4800) { 95 if (freq < 4800) { /* 2 GHz, fractional mode */
114 u32 txctl; 96 u32 txctl;
97 int regWrites = 0;
115 98
116 bMode = 1; 99 bMode = 1;
117 fracMode = 1; 100 fracMode = 1;
118 aModeRefSel = 0; 101 aModeRefSel = 0;
119 channelSel = (freq * 0x10000) / 15; 102 channelSel = (freq * 0x10000) / 15;
120 103
121 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 104 if (AR_SREV_9287_11_OR_LATER(ah)) {
122 if (freq == 2484) { 105 if (freq == 2484) {
123 106 /* Enable channel spreading for channel 14 */
124 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 107 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
125 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 108 1, regWrites);
109 } else {
110 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
111 1, regWrites);
112 }
126 } else { 113 } else {
127 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 114 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
128 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 115 if (freq == 2484) {
116 /* Enable channel spreading for channel 14 */
117 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
118 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
119 } else {
120 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
121 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
122 }
129 } 123 }
130 } else { 124 } else {
131 bMode = 0; 125 bMode = 0;
@@ -143,10 +137,15 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
143 case 1: 137 case 1:
144 default: 138 default:
145 aModeRefSel = 0; 139 aModeRefSel = 0;
140 /*
141 * Enable 2G (fractional) mode for channels
142 * which are 5MHz spaced.
143 */
146 fracMode = 1; 144 fracMode = 1;
147 refDivA = 1; 145 refDivA = 1;
148 channelSel = (freq * 0x8000) / 15; 146 channelSel = (freq * 0x8000) / 15;
149 147
148 /* RefDivA setting */
150 REG_RMW_FIELD(ah, AR_AN_SYNTH9, 149 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
151 AR_AN_SYNTH9_REFDIVA, refDivA); 150 AR_AN_SYNTH9_REFDIVA, refDivA);
152 151
@@ -168,12 +167,284 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
168 167
169 ah->curchan = chan; 168 ah->curchan = chan;
170 ah->curchan_rad_index = -1; 169 ah->curchan_rad_index = -1;
170
171 return 0;
172}
173
174/**
175 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
176 * @ah: atheros hardware structure
177 * @chan:
178 *
179 * For single-chip solutions. Converts to baseband spur frequency given the
180 * input channel frequency and compute register settings below.
181 */
182void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
183{
184 int bb_spur = AR_NO_SPUR;
185 int freq;
186 int bin, cur_bin;
187 int bb_spur_off, spur_subchannel_sd;
188 int spur_freq_sd;
189 int spur_delta_phase;
190 int denominator;
191 int upper, lower, cur_vit_mask;
192 int tmp, newVal;
193 int i;
194 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
195 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
196 };
197 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
198 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
199 };
200 int inc[4] = { 0, 100, 0, 0 };
201 struct chan_centers centers;
202
203 int8_t mask_m[123];
204 int8_t mask_p[123];
205 int8_t mask_amt;
206 int tmp_mask;
207 int cur_bb_spur;
208 bool is2GHz = IS_CHAN_2GHZ(chan);
209
210 memset(&mask_m, 0, sizeof(int8_t) * 123);
211 memset(&mask_p, 0, sizeof(int8_t) * 123);
212
213 ath9k_hw_get_channel_centers(ah, chan, &centers);
214 freq = centers.synth_center;
215
216 ah->config.spurmode = SPUR_ENABLE_EEPROM;
217 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
218 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
219
220 if (is2GHz)
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
222 else
223 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
224
225 if (AR_NO_SPUR == cur_bb_spur)
226 break;
227 cur_bb_spur = cur_bb_spur - freq;
228
229 if (IS_CHAN_HT40(chan)) {
230 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
231 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
232 bb_spur = cur_bb_spur;
233 break;
234 }
235 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
236 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
237 bb_spur = cur_bb_spur;
238 break;
239 }
240 }
241
242 if (AR_NO_SPUR == bb_spur) {
243 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
244 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
245 return;
246 } else {
247 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
248 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
249 }
250
251 bin = bb_spur * 320;
252
253 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
254
255 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
256 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
257 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
258 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
259 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
260
261 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
262 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
263 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
264 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
265 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
266 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
267
268 if (IS_CHAN_HT40(chan)) {
269 if (bb_spur < 0) {
270 spur_subchannel_sd = 1;
271 bb_spur_off = bb_spur + 10;
272 } else {
273 spur_subchannel_sd = 0;
274 bb_spur_off = bb_spur - 10;
275 }
276 } else {
277 spur_subchannel_sd = 0;
278 bb_spur_off = bb_spur;
279 }
280
281 if (IS_CHAN_HT40(chan))
282 spur_delta_phase =
283 ((bb_spur * 262144) /
284 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
285 else
286 spur_delta_phase =
287 ((bb_spur * 524288) /
288 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
289
290 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
291 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
292
293 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
294 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
295 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
296 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
297
298 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
299 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
300
301 cur_bin = -6000;
302 upper = bin + 100;
303 lower = bin - 100;
304
305 for (i = 0; i < 4; i++) {
306 int pilot_mask = 0;
307 int chan_mask = 0;
308 int bp = 0;
309 for (bp = 0; bp < 30; bp++) {
310 if ((cur_bin > lower) && (cur_bin < upper)) {
311 pilot_mask = pilot_mask | 0x1 << bp;
312 chan_mask = chan_mask | 0x1 << bp;
313 }
314 cur_bin += 100;
315 }
316 cur_bin += inc[i];
317 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
318 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
319 }
320
321 cur_vit_mask = 6100;
322 upper = bin + 120;
323 lower = bin - 120;
324
325 for (i = 0; i < 123; i++) {
326 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
327
328 /* workaround for gcc bug #37014 */
329 volatile int tmp_v = abs(cur_vit_mask - bin);
330
331 if (tmp_v < 75)
332 mask_amt = 1;
333 else
334 mask_amt = 0;
335 if (cur_vit_mask < 0)
336 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
337 else
338 mask_p[cur_vit_mask / 100] = mask_amt;
339 }
340 cur_vit_mask -= 100;
341 }
342
343 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
344 | (mask_m[48] << 26) | (mask_m[49] << 24)
345 | (mask_m[50] << 22) | (mask_m[51] << 20)
346 | (mask_m[52] << 18) | (mask_m[53] << 16)
347 | (mask_m[54] << 14) | (mask_m[55] << 12)
348 | (mask_m[56] << 10) | (mask_m[57] << 8)
349 | (mask_m[58] << 6) | (mask_m[59] << 4)
350 | (mask_m[60] << 2) | (mask_m[61] << 0);
351 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
352 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
353
354 tmp_mask = (mask_m[31] << 28)
355 | (mask_m[32] << 26) | (mask_m[33] << 24)
356 | (mask_m[34] << 22) | (mask_m[35] << 20)
357 | (mask_m[36] << 18) | (mask_m[37] << 16)
358 | (mask_m[48] << 14) | (mask_m[39] << 12)
359 | (mask_m[40] << 10) | (mask_m[41] << 8)
360 | (mask_m[42] << 6) | (mask_m[43] << 4)
361 | (mask_m[44] << 2) | (mask_m[45] << 0);
362 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
363 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
364
365 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
366 | (mask_m[18] << 26) | (mask_m[18] << 24)
367 | (mask_m[20] << 22) | (mask_m[20] << 20)
368 | (mask_m[22] << 18) | (mask_m[22] << 16)
369 | (mask_m[24] << 14) | (mask_m[24] << 12)
370 | (mask_m[25] << 10) | (mask_m[26] << 8)
371 | (mask_m[27] << 6) | (mask_m[28] << 4)
372 | (mask_m[29] << 2) | (mask_m[30] << 0);
373 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
374 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
375
376 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
377 | (mask_m[2] << 26) | (mask_m[3] << 24)
378 | (mask_m[4] << 22) | (mask_m[5] << 20)
379 | (mask_m[6] << 18) | (mask_m[7] << 16)
380 | (mask_m[8] << 14) | (mask_m[9] << 12)
381 | (mask_m[10] << 10) | (mask_m[11] << 8)
382 | (mask_m[12] << 6) | (mask_m[13] << 4)
383 | (mask_m[14] << 2) | (mask_m[15] << 0);
384 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
385 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
386
387 tmp_mask = (mask_p[15] << 28)
388 | (mask_p[14] << 26) | (mask_p[13] << 24)
389 | (mask_p[12] << 22) | (mask_p[11] << 20)
390 | (mask_p[10] << 18) | (mask_p[9] << 16)
391 | (mask_p[8] << 14) | (mask_p[7] << 12)
392 | (mask_p[6] << 10) | (mask_p[5] << 8)
393 | (mask_p[4] << 6) | (mask_p[3] << 4)
394 | (mask_p[2] << 2) | (mask_p[1] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
397
398 tmp_mask = (mask_p[30] << 28)
399 | (mask_p[29] << 26) | (mask_p[28] << 24)
400 | (mask_p[27] << 22) | (mask_p[26] << 20)
401 | (mask_p[25] << 18) | (mask_p[24] << 16)
402 | (mask_p[23] << 14) | (mask_p[22] << 12)
403 | (mask_p[21] << 10) | (mask_p[20] << 8)
404 | (mask_p[19] << 6) | (mask_p[18] << 4)
405 | (mask_p[17] << 2) | (mask_p[16] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
408
409 tmp_mask = (mask_p[45] << 28)
410 | (mask_p[44] << 26) | (mask_p[43] << 24)
411 | (mask_p[42] << 22) | (mask_p[41] << 20)
412 | (mask_p[40] << 18) | (mask_p[39] << 16)
413 | (mask_p[38] << 14) | (mask_p[37] << 12)
414 | (mask_p[36] << 10) | (mask_p[35] << 8)
415 | (mask_p[34] << 6) | (mask_p[33] << 4)
416 | (mask_p[32] << 2) | (mask_p[31] << 0);
417 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
419
420 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
421 | (mask_p[59] << 26) | (mask_p[58] << 24)
422 | (mask_p[57] << 22) | (mask_p[56] << 20)
423 | (mask_p[55] << 18) | (mask_p[54] << 16)
424 | (mask_p[53] << 14) | (mask_p[52] << 12)
425 | (mask_p[51] << 10) | (mask_p[50] << 8)
426 | (mask_p[49] << 6) | (mask_p[48] << 4)
427 | (mask_p[47] << 2) | (mask_p[46] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
171} 430}
172 431
173static void 432/* All code below is for non single-chip solutions */
174ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 433
175 u32 numBits, u32 firstBit, 434/**
176 u32 column) 435 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
436 * @rfbuf:
437 * @reg32:
438 * @numBits:
439 * @firstBit:
440 * @column:
441 *
442 * Performs analog "swizzling" of parameters into their location.
443 * Used on external AR2133/AR5133 radios.
444 */
445static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
446 u32 numBits, u32 firstBit,
447 u32 column)
177{ 448{
178 u32 tmp32, mask, arrayEntry, lastBit; 449 u32 tmp32, mask, arrayEntry, lastBit;
179 int32_t bitPosition, bitsLeft; 450 int32_t bitPosition, bitsLeft;
@@ -197,26 +468,466 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
197 } 468 }
198} 469}
199 470
200bool 471/*
201ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, 472 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
202 u16 modesIndex) 473 * rf_pwd_icsyndiv.
474 *
475 * Theoretical Rules:
476 * if 2 GHz band
477 * if forceBiasAuto
478 * if synth_freq < 2412
479 * bias = 0
480 * else if 2412 <= synth_freq <= 2422
481 * bias = 1
482 * else // synth_freq > 2422
483 * bias = 2
484 * else if forceBias > 0
485 * bias = forceBias & 7
486 * else
487 * no change, use value from ini file
488 * else
489 * no change, invalid band
490 *
491 * 1st Mod:
492 * 2422 also uses value of 2
493 * <approved>
494 *
495 * 2nd Mod:
496 * Less than 2412 uses value of 0, 2412 and above uses value of 2
497 */
498static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
499{
500 struct ath_common *common = ath9k_hw_common(ah);
501 u32 tmp_reg;
502 int reg_writes = 0;
503 u32 new_bias = 0;
504
505 if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
506 return;
507 }
508
509 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
510
511 if (synth_freq < 2412)
512 new_bias = 0;
513 else if (synth_freq < 2422)
514 new_bias = 1;
515 else
516 new_bias = 2;
517
518 /* pre-reverse this field */
519 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
520
521 ath_print(common, ATH_DBG_CONFIG,
522 "Force rf_pwd_icsyndiv to %1d on %4d\n",
523 new_bias, synth_freq);
524
525 /* swizzle rf_pwd_icsyndiv */
526 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
527
528 /* write Bank 6 with new params */
529 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
530}
531
532/**
533 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
534 * @ah: atheros hardware stucture
535 * @chan:
536 *
537 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
538 * the channel value. Assumes writes enabled to analog bus and bank6 register
539 * cache in ah->analogBank6Data.
540 */
541int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
542{
543 struct ath_common *common = ath9k_hw_common(ah);
544 u32 channelSel = 0;
545 u32 bModeSynth = 0;
546 u32 aModeRefSel = 0;
547 u32 reg32 = 0;
548 u16 freq;
549 struct chan_centers centers;
550
551 ath9k_hw_get_channel_centers(ah, chan, &centers);
552 freq = centers.synth_center;
553
554 if (freq < 4800) {
555 u32 txctl;
556
557 if (((freq - 2192) % 5) == 0) {
558 channelSel = ((freq - 672) * 2 - 3040) / 10;
559 bModeSynth = 0;
560 } else if (((freq - 2224) % 5) == 0) {
561 channelSel = ((freq - 704) * 2 - 3040) / 10;
562 bModeSynth = 1;
563 } else {
564 ath_print(common, ATH_DBG_FATAL,
565 "Invalid channel %u MHz\n", freq);
566 return -EINVAL;
567 }
568
569 channelSel = (channelSel << 2) & 0xff;
570 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
571
572 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
573 if (freq == 2484) {
574
575 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
576 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
577 } else {
578 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
579 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
580 }
581
582 } else if ((freq % 20) == 0 && freq >= 5120) {
583 channelSel =
584 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
585 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
586 } else if ((freq % 10) == 0) {
587 channelSel =
588 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
589 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
590 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
591 else
592 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
593 } else if ((freq % 5) == 0) {
594 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
595 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
596 } else {
597 ath_print(common, ATH_DBG_FATAL,
598 "Invalid channel %u MHz\n", freq);
599 return -EINVAL;
600 }
601
602 ath9k_hw_force_bias(ah, freq);
603
604 reg32 =
605 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
606 (1 << 5) | 0x1;
607
608 REG_WRITE(ah, AR_PHY(0x37), reg32);
609
610 ah->curchan = chan;
611 ah->curchan_rad_index = -1;
612
613 return 0;
614}
615
616/**
617 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
618 * @ah: atheros hardware structure
619 * @chan:
620 *
621 * For non single-chip solutions. Converts to baseband spur frequency given the
622 * input channel frequency and compute register settings below.
623 */
624void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
625{
626 int bb_spur = AR_NO_SPUR;
627 int bin, cur_bin;
628 int spur_freq_sd;
629 int spur_delta_phase;
630 int denominator;
631 int upper, lower, cur_vit_mask;
632 int tmp, new;
633 int i;
634 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
635 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
636 };
637 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
638 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
639 };
640 int inc[4] = { 0, 100, 0, 0 };
641
642 int8_t mask_m[123];
643 int8_t mask_p[123];
644 int8_t mask_amt;
645 int tmp_mask;
646 int cur_bb_spur;
647 bool is2GHz = IS_CHAN_2GHZ(chan);
648
649 memset(&mask_m, 0, sizeof(int8_t) * 123);
650 memset(&mask_p, 0, sizeof(int8_t) * 123);
651
652 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
653 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
654 if (AR_NO_SPUR == cur_bb_spur)
655 break;
656 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
657 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
658 bb_spur = cur_bb_spur;
659 break;
660 }
661 }
662
663 if (AR_NO_SPUR == bb_spur)
664 return;
665
666 bin = bb_spur * 32;
667
668 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
669 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
670 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
671 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
672 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
673
674 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
675
676 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
677 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
678 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
679 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
680 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
681 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
682
683 spur_delta_phase = ((bb_spur * 524288) / 100) &
684 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
685
686 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
687 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
688
689 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
690 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
691 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
692 REG_WRITE(ah, AR_PHY_TIMING11, new);
693
694 cur_bin = -6000;
695 upper = bin + 100;
696 lower = bin - 100;
697
698 for (i = 0; i < 4; i++) {
699 int pilot_mask = 0;
700 int chan_mask = 0;
701 int bp = 0;
702 for (bp = 0; bp < 30; bp++) {
703 if ((cur_bin > lower) && (cur_bin < upper)) {
704 pilot_mask = pilot_mask | 0x1 << bp;
705 chan_mask = chan_mask | 0x1 << bp;
706 }
707 cur_bin += 100;
708 }
709 cur_bin += inc[i];
710 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
711 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
712 }
713
714 cur_vit_mask = 6100;
715 upper = bin + 120;
716 lower = bin - 120;
717
718 for (i = 0; i < 123; i++) {
719 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
720
721 /* workaround for gcc bug #37014 */
722 volatile int tmp_v = abs(cur_vit_mask - bin);
723
724 if (tmp_v < 75)
725 mask_amt = 1;
726 else
727 mask_amt = 0;
728 if (cur_vit_mask < 0)
729 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
730 else
731 mask_p[cur_vit_mask / 100] = mask_amt;
732 }
733 cur_vit_mask -= 100;
734 }
735
736 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
737 | (mask_m[48] << 26) | (mask_m[49] << 24)
738 | (mask_m[50] << 22) | (mask_m[51] << 20)
739 | (mask_m[52] << 18) | (mask_m[53] << 16)
740 | (mask_m[54] << 14) | (mask_m[55] << 12)
741 | (mask_m[56] << 10) | (mask_m[57] << 8)
742 | (mask_m[58] << 6) | (mask_m[59] << 4)
743 | (mask_m[60] << 2) | (mask_m[61] << 0);
744 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
745 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
746
747 tmp_mask = (mask_m[31] << 28)
748 | (mask_m[32] << 26) | (mask_m[33] << 24)
749 | (mask_m[34] << 22) | (mask_m[35] << 20)
750 | (mask_m[36] << 18) | (mask_m[37] << 16)
751 | (mask_m[48] << 14) | (mask_m[39] << 12)
752 | (mask_m[40] << 10) | (mask_m[41] << 8)
753 | (mask_m[42] << 6) | (mask_m[43] << 4)
754 | (mask_m[44] << 2) | (mask_m[45] << 0);
755 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
756 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
757
758 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
759 | (mask_m[18] << 26) | (mask_m[18] << 24)
760 | (mask_m[20] << 22) | (mask_m[20] << 20)
761 | (mask_m[22] << 18) | (mask_m[22] << 16)
762 | (mask_m[24] << 14) | (mask_m[24] << 12)
763 | (mask_m[25] << 10) | (mask_m[26] << 8)
764 | (mask_m[27] << 6) | (mask_m[28] << 4)
765 | (mask_m[29] << 2) | (mask_m[30] << 0);
766 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
767 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
768
769 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
770 | (mask_m[2] << 26) | (mask_m[3] << 24)
771 | (mask_m[4] << 22) | (mask_m[5] << 20)
772 | (mask_m[6] << 18) | (mask_m[7] << 16)
773 | (mask_m[8] << 14) | (mask_m[9] << 12)
774 | (mask_m[10] << 10) | (mask_m[11] << 8)
775 | (mask_m[12] << 6) | (mask_m[13] << 4)
776 | (mask_m[14] << 2) | (mask_m[15] << 0);
777 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
778 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
779
780 tmp_mask = (mask_p[15] << 28)
781 | (mask_p[14] << 26) | (mask_p[13] << 24)
782 | (mask_p[12] << 22) | (mask_p[11] << 20)
783 | (mask_p[10] << 18) | (mask_p[9] << 16)
784 | (mask_p[8] << 14) | (mask_p[7] << 12)
785 | (mask_p[6] << 10) | (mask_p[5] << 8)
786 | (mask_p[4] << 6) | (mask_p[3] << 4)
787 | (mask_p[2] << 2) | (mask_p[1] << 0);
788 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
789 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
790
791 tmp_mask = (mask_p[30] << 28)
792 | (mask_p[29] << 26) | (mask_p[28] << 24)
793 | (mask_p[27] << 22) | (mask_p[26] << 20)
794 | (mask_p[25] << 18) | (mask_p[24] << 16)
795 | (mask_p[23] << 14) | (mask_p[22] << 12)
796 | (mask_p[21] << 10) | (mask_p[20] << 8)
797 | (mask_p[19] << 6) | (mask_p[18] << 4)
798 | (mask_p[17] << 2) | (mask_p[16] << 0);
799 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
800 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
801
802 tmp_mask = (mask_p[45] << 28)
803 | (mask_p[44] << 26) | (mask_p[43] << 24)
804 | (mask_p[42] << 22) | (mask_p[41] << 20)
805 | (mask_p[40] << 18) | (mask_p[39] << 16)
806 | (mask_p[38] << 14) | (mask_p[37] << 12)
807 | (mask_p[36] << 10) | (mask_p[35] << 8)
808 | (mask_p[34] << 6) | (mask_p[33] << 4)
809 | (mask_p[32] << 2) | (mask_p[31] << 0);
810 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
811 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
812
813 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
814 | (mask_p[59] << 26) | (mask_p[58] << 24)
815 | (mask_p[57] << 22) | (mask_p[56] << 20)
816 | (mask_p[55] << 18) | (mask_p[54] << 16)
817 | (mask_p[53] << 14) | (mask_p[52] << 12)
818 | (mask_p[51] << 10) | (mask_p[50] << 8)
819 | (mask_p[49] << 6) | (mask_p[48] << 4)
820 | (mask_p[47] << 2) | (mask_p[46] << 0);
821 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
822 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
823}
824
825/**
826 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
827 * @ah: atheros hardware structure
828 *
829 * Only required for older devices with external AR2133/AR5133 radios.
830 */
831int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
832{
833#define ATH_ALLOC_BANK(bank, size) do { \
834 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
835 if (!bank) { \
836 ath_print(common, ATH_DBG_FATAL, \
837 "Cannot allocate RF banks\n"); \
838 return -ENOMEM; \
839 } \
840 } while (0);
841
842 struct ath_common *common = ath9k_hw_common(ah);
843
844 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
845
846 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
847 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
848 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
849 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
850 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
851 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
852 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
853 ATH_ALLOC_BANK(ah->addac5416_21,
854 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
855 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
856
857 return 0;
858#undef ATH_ALLOC_BANK
859}
860
861
862/**
863 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
864 * @ah: atheros hardware struture
865 * For the external AR2133/AR5133 radios banks.
866 */
867void
868ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
869{
870#define ATH_FREE_BANK(bank) do { \
871 kfree(bank); \
872 bank = NULL; \
873 } while (0);
874
875 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
876
877 ATH_FREE_BANK(ah->analogBank0Data);
878 ATH_FREE_BANK(ah->analogBank1Data);
879 ATH_FREE_BANK(ah->analogBank2Data);
880 ATH_FREE_BANK(ah->analogBank3Data);
881 ATH_FREE_BANK(ah->analogBank6Data);
882 ATH_FREE_BANK(ah->analogBank6TPCData);
883 ATH_FREE_BANK(ah->analogBank7Data);
884 ATH_FREE_BANK(ah->addac5416_21);
885 ATH_FREE_BANK(ah->bank6Temp);
886
887#undef ATH_FREE_BANK
888}
889
890/* *
891 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
892 * @ah: atheros hardware structure
893 * @chan:
894 * @modesIndex:
895 *
896 * Used for the external AR2133/AR5133 radios.
897 *
898 * Reads the EEPROM header info from the device structure and programs
899 * all rf registers. This routine requires access to the analog
900 * rf device. This is not required for single-chip devices.
901 */
902bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
903 u16 modesIndex)
203{ 904{
204 u32 eepMinorRev; 905 u32 eepMinorRev;
205 u32 ob5GHz = 0, db5GHz = 0; 906 u32 ob5GHz = 0, db5GHz = 0;
206 u32 ob2GHz = 0, db2GHz = 0; 907 u32 ob2GHz = 0, db2GHz = 0;
207 int regWrites = 0; 908 int regWrites = 0;
208 909
910 /*
911 * Software does not need to program bank data
912 * for single chip devices, that is AR9280 or anything
913 * after that.
914 */
209 if (AR_SREV_9280_10_OR_LATER(ah)) 915 if (AR_SREV_9280_10_OR_LATER(ah))
210 return true; 916 return true;
211 917
918 /* Setup rf parameters */
212 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 919 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
213 920
921 /* Setup Bank 0 Write */
214 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); 922 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
215 923
924 /* Setup Bank 1 Write */
216 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); 925 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
217 926
927 /* Setup Bank 2 Write */
218 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); 928 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
219 929
930 /* Setup Bank 6 Write */
220 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, 931 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
221 modesIndex); 932 modesIndex);
222 { 933 {
@@ -227,6 +938,7 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
227 } 938 }
228 } 939 }
229 940
941 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
230 if (eepMinorRev >= 2) { 942 if (eepMinorRev >= 2) {
231 if (IS_CHAN_2GHZ(chan)) { 943 if (IS_CHAN_2GHZ(chan)) {
232 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 944 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
@@ -245,8 +957,10 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
245 } 957 }
246 } 958 }
247 959
960 /* Setup Bank 7 Setup */
248 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); 961 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
249 962
963 /* Write Analog registers */
250 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 964 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
251 regWrites); 965 regWrites);
252 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 966 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
@@ -262,137 +976,3 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
262 976
263 return true; 977 return true;
264} 978}
265
266void
267ath9k_hw_rf_free(struct ath_hw *ah)
268{
269#define ATH_FREE_BANK(bank) do { \
270 kfree(bank); \
271 bank = NULL; \
272 } while (0);
273
274 ATH_FREE_BANK(ah->analogBank0Data);
275 ATH_FREE_BANK(ah->analogBank1Data);
276 ATH_FREE_BANK(ah->analogBank2Data);
277 ATH_FREE_BANK(ah->analogBank3Data);
278 ATH_FREE_BANK(ah->analogBank6Data);
279 ATH_FREE_BANK(ah->analogBank6TPCData);
280 ATH_FREE_BANK(ah->analogBank7Data);
281 ATH_FREE_BANK(ah->addac5416_21);
282 ATH_FREE_BANK(ah->bank6Temp);
283#undef ATH_FREE_BANK
284}
285
286bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
287{
288 if (!AR_SREV_9280_10_OR_LATER(ah)) {
289 ah->analogBank0Data =
290 kzalloc((sizeof(u32) *
291 ah->iniBank0.ia_rows), GFP_KERNEL);
292 ah->analogBank1Data =
293 kzalloc((sizeof(u32) *
294 ah->iniBank1.ia_rows), GFP_KERNEL);
295 ah->analogBank2Data =
296 kzalloc((sizeof(u32) *
297 ah->iniBank2.ia_rows), GFP_KERNEL);
298 ah->analogBank3Data =
299 kzalloc((sizeof(u32) *
300 ah->iniBank3.ia_rows), GFP_KERNEL);
301 ah->analogBank6Data =
302 kzalloc((sizeof(u32) *
303 ah->iniBank6.ia_rows), GFP_KERNEL);
304 ah->analogBank6TPCData =
305 kzalloc((sizeof(u32) *
306 ah->iniBank6TPC.ia_rows), GFP_KERNEL);
307 ah->analogBank7Data =
308 kzalloc((sizeof(u32) *
309 ah->iniBank7.ia_rows), GFP_KERNEL);
310
311 if (ah->analogBank0Data == NULL
312 || ah->analogBank1Data == NULL
313 || ah->analogBank2Data == NULL
314 || ah->analogBank3Data == NULL
315 || ah->analogBank6Data == NULL
316 || ah->analogBank6TPCData == NULL
317 || ah->analogBank7Data == NULL) {
318 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
319 "Cannot allocate RF banks\n");
320 *status = -ENOMEM;
321 return false;
322 }
323
324 ah->addac5416_21 =
325 kzalloc((sizeof(u32) *
326 ah->iniAddac.ia_rows *
327 ah->iniAddac.ia_columns), GFP_KERNEL);
328 if (ah->addac5416_21 == NULL) {
329 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
330 "Cannot allocate addac5416_21\n");
331 *status = -ENOMEM;
332 return false;
333 }
334
335 ah->bank6Temp =
336 kzalloc((sizeof(u32) *
337 ah->iniBank6.ia_rows), GFP_KERNEL);
338 if (ah->bank6Temp == NULL) {
339 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
340 "Cannot allocate bank6Temp\n");
341 *status = -ENOMEM;
342 return false;
343 }
344 }
345
346 return true;
347}
348
349void
350ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
351{
352 int i, regWrites = 0;
353 u32 bank6SelMask;
354 u32 *bank6Temp = ah->bank6Temp;
355
356 switch (ah->config.diversity_control) {
357 case ATH9K_ANT_FIXED_A:
358 bank6SelMask =
359 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
360 REDUCE_CHAIN_0 : REDUCE_CHAIN_1;
361 break;
362 case ATH9K_ANT_FIXED_B:
363 bank6SelMask =
364 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
365 REDUCE_CHAIN_1 : REDUCE_CHAIN_0;
366 break;
367 case ATH9K_ANT_VARIABLE:
368 return;
369 break;
370 default:
371 return;
372 break;
373 }
374
375 for (i = 0; i < ah->iniBank6.ia_rows; i++)
376 bank6Temp[i] = ah->analogBank6Data[i];
377
378 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
379
380 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
381 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
382 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
383 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
384 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
385 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
386 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
387 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
388 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
389
390 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
391
392 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
393#ifdef ALTER_SWITCH
394 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
395 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
396 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
397#endif
398}
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index dfda6f444648..0999a495fd46 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,20 +17,23 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 20/* Common between single chip and non single-chip solutions */
21 struct ath9k_channel 21void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
22 *chan); 22
23bool ath9k_hw_set_channel(struct ath_hw *ah, 23/* Single chip radio settings */
24 struct ath9k_channel *chan); 24int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
25void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, 25void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
26 u32 freqIndex, int regWrites); 26
27/* Routines below are for non single-chip solutions */
28int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
29void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
30
31int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33
27bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 34bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
28 struct ath9k_channel *chan, 35 struct ath9k_channel *chan,
29 u16 modesIndex); 36 u16 modesIndex);
30void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
31 struct ath9k_channel *chan);
32bool ath9k_hw_init_rf(struct ath_hw *ah,
33 int *status);
34 37
35#define AR_PHY_BASE 0x9800 38#define AR_PHY_BASE 0x9800
36#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 39#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
@@ -45,6 +48,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
45#define AR_PHY_FC_DYN2040_EN 0x00000004 48#define AR_PHY_FC_DYN2040_EN 0x00000004
46#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 49#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
47#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 50#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
51/* For 25 MHz channel spacing -- not used but supported by hw */
48#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 52#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
49#define AR_PHY_FC_HT_EN 0x00000040 53#define AR_PHY_FC_HT_EN 0x00000040
50#define AR_PHY_FC_SHORT_GI_40 0x00000080 54#define AR_PHY_FC_SHORT_GI_40 0x00000080
@@ -185,8 +189,20 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
185#define AR_PHY_PLL_CTL_44_2133 0xeb 189#define AR_PHY_PLL_CTL_44_2133 0xeb
186#define AR_PHY_PLL_CTL_40_2133 0xea 190#define AR_PHY_PLL_CTL_40_2133 0xea
187 191
188#define AR_PHY_SPECTRAL_SCAN 0x9912 192#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
189#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 193#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
194#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
195#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
196#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
197#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
198#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
199#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
200#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
201#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
202#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
203#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
204#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
205#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
190 206
191#define AR_PHY_RX_DELAY 0x9914 207#define AR_PHY_RX_DELAY 0x9914
192#define AR_PHY_SEARCH_START_DELAY 0x9918 208#define AR_PHY_SEARCH_START_DELAY 0x9918
@@ -368,6 +384,9 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
368 384
369#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 385#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
370 386
387#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
388#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
389
371#define AR_PHY_M_SLEEP 0x99f0 390#define AR_PHY_M_SLEEP 0x99f0
372#define AR_PHY_REFCLKDLY 0x99f4 391#define AR_PHY_REFCLKDLY 0x99f4
373#define AR_PHY_REFCLKPD 0x99f8 392#define AR_PHY_REFCLKPD 0x99f8
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 1895d63aad0a..244e1c629177 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -15,137 +15,98 @@
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */ 16 */
17 17
18#include <linux/slab.h>
19
18#include "ath9k.h" 20#include "ath9k.h"
19 21
20static const struct ath_rate_table ar5416_11na_ratetable = { 22static const struct ath_rate_table ar5416_11na_ratetable = {
21 42, 23 42,
24 8, /* MCS start */
22 { 25 {
23 { VALID, VALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */ 26 { VALID, VALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */
24 5400, 0x0b, 0x00, 12, 27 5400, 0, 12, 0, 0, 0, 0, 0 },
25 0, 0, 0, 0, 0, 0 },
26 { VALID, VALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */ 28 { VALID, VALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */
27 7800, 0x0f, 0x00, 18, 29 7800, 1, 18, 0, 1, 1, 1, 1 },
28 0, 1, 1, 1, 1, 0 },
29 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */ 30 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */
30 10000, 0x0a, 0x00, 24, 31 10000, 2, 24, 2, 2, 2, 2, 2 },
31 2, 2, 2, 2, 2, 0 },
32 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */ 32 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */
33 13900, 0x0e, 0x00, 36, 33 13900, 3, 36, 2, 3, 3, 3, 3 },
34 2, 3, 3, 3, 3, 0 },
35 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */ 34 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */
36 17300, 0x09, 0x00, 48, 35 17300, 4, 48, 4, 4, 4, 4, 4 },
37 4, 4, 4, 4, 4, 0 },
38 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */ 36 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */
39 23000, 0x0d, 0x00, 72, 37 23000, 5, 72, 4, 5, 5, 5, 5 },
40 4, 5, 5, 5, 5, 0 },
41 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */ 38 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */
42 27400, 0x08, 0x00, 96, 39 27400, 6, 96, 4, 6, 6, 6, 6 },
43 4, 6, 6, 6, 6, 0 },
44 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */ 40 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */
45 29300, 0x0c, 0x00, 108, 41 29300, 7, 108, 4, 7, 7, 7, 7 },
46 4, 7, 7, 7, 7, 0 },
47 { VALID_2040, VALID_2040, WLAN_RC_PHY_HT_20_SS, 6500, /* 6.5 Mb */ 42 { VALID_2040, VALID_2040, WLAN_RC_PHY_HT_20_SS, 6500, /* 6.5 Mb */
48 6400, 0x80, 0x00, 0, 43 6400, 0, 0, 0, 8, 24, 8, 24 },
49 0, 8, 24, 8, 24, 3216 },
50 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 13000, /* 13 Mb */ 44 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 13000, /* 13 Mb */
51 12700, 0x81, 0x00, 1, 45 12700, 1, 1, 2, 9, 25, 9, 25 },
52 2, 9, 25, 9, 25, 6434 },
53 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 19500, /* 19.5 Mb */ 46 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 19500, /* 19.5 Mb */
54 18800, 0x82, 0x00, 2, 47 18800, 2, 2, 2, 10, 26, 10, 26 },
55 2, 10, 26, 10, 26, 9650 },
56 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 26000, /* 26 Mb */ 48 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 26000, /* 26 Mb */
57 25000, 0x83, 0x00, 3, 49 25000, 3, 3, 4, 11, 27, 11, 27 },
58 4, 11, 27, 11, 27, 12868 },
59 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 39000, /* 39 Mb */ 50 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 39000, /* 39 Mb */
60 36700, 0x84, 0x00, 4, 51 36700, 4, 4, 4, 12, 28, 12, 28 },
61 4, 12, 28, 12, 28, 19304 },
62 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 52000, /* 52 Mb */ 52 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 52000, /* 52 Mb */
63 48100, 0x85, 0x00, 5, 53 48100, 5, 5, 4, 13, 29, 13, 29 },
64 4, 13, 29, 13, 29, 25740 },
65 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 58500, /* 58.5 Mb */ 54 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 58500, /* 58.5 Mb */
66 53500, 0x86, 0x00, 6, 55 53500, 6, 6, 4, 14, 30, 14, 30 },
67 4, 14, 30, 14, 30, 28956 },
68 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 65000, /* 65 Mb */ 56 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 65000, /* 65 Mb */
69 59000, 0x87, 0x00, 7, 57 59000, 7, 7, 4, 15, 31, 15, 32 },
70 4, 15, 31, 15, 32, 32180 },
71 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 13000, /* 13 Mb */ 58 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 13000, /* 13 Mb */
72 12700, 0x88, 0x00, 59 12700, 8, 8, 3, 16, 33, 16, 33 },
73 8, 3, 16, 33, 16, 33, 6430 },
74 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 26000, /* 26 Mb */ 60 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 26000, /* 26 Mb */
75 24800, 0x89, 0x00, 9, 61 24800, 9, 9, 2, 17, 34, 17, 34 },
76 2, 17, 34, 17, 34, 12860 },
77 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 39000, /* 39 Mb */ 62 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 39000, /* 39 Mb */
78 36600, 0x8a, 0x00, 10, 63 36600, 10, 10, 2, 18, 35, 18, 35 },
79 2, 18, 35, 18, 35, 19300 },
80 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 52000, /* 52 Mb */ 64 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 52000, /* 52 Mb */
81 48100, 0x8b, 0x00, 11, 65 48100, 11, 11, 4, 19, 36, 19, 36 },
82 4, 19, 36, 19, 36, 25736 },
83 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 78000, /* 78 Mb */ 66 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 78000, /* 78 Mb */
84 69500, 0x8c, 0x00, 12, 67 69500, 12, 12, 4, 20, 37, 20, 37 },
85 4, 20, 37, 20, 37, 38600 },
86 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 104000, /* 104 Mb */ 68 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 104000, /* 104 Mb */
87 89500, 0x8d, 0x00, 13, 69 89500, 13, 13, 4, 21, 38, 21, 38 },
88 4, 21, 38, 21, 38, 51472 },
89 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 117000, /* 117 Mb */ 70 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 117000, /* 117 Mb */
90 98900, 0x8e, 0x00, 14, 71 98900, 14, 14, 4, 22, 39, 22, 39 },
91 4, 22, 39, 22, 39, 57890 },
92 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 130000, /* 130 Mb */ 72 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 130000, /* 130 Mb */
93 108300, 0x8f, 0x00, 15, 73 108300, 15, 15, 4, 23, 40, 23, 41 },
94 4, 23, 40, 23, 41, 64320 },
95 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 13500, /* 13.5 Mb */ 74 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 13500, /* 13.5 Mb */
96 13200, 0x80, 0x00, 0, 75 13200, 0, 0, 0, 8, 24, 24, 24 },
97 0, 8, 24, 24, 24, 6684 },
98 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 27500, /* 27.0 Mb */ 76 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 27500, /* 27.0 Mb */
99 25900, 0x81, 0x00, 1, 77 25900, 1, 1, 2, 9, 25, 25, 25 },
100 2, 9, 25, 25, 25, 13368 },
101 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 40500, /* 40.5 Mb */ 78 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 40500, /* 40.5 Mb */
102 38600, 0x82, 0x00, 2, 79 38600, 2, 2, 2, 10, 26, 26, 26 },
103 2, 10, 26, 26, 26, 20052 },
104 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 54000, /* 54 Mb */ 80 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 54000, /* 54 Mb */
105 49800, 0x83, 0x00, 3, 81 49800, 3, 3, 4, 11, 27, 27, 27 },
106 4, 11, 27, 27, 27, 26738 },
107 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 81500, /* 81 Mb */ 82 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 81500, /* 81 Mb */
108 72200, 0x84, 0x00, 4, 83 72200, 4, 4, 4, 12, 28, 28, 28 },
109 4, 12, 28, 28, 28, 40104 },
110 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 108000, /* 108 Mb */ 84 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 108000, /* 108 Mb */
111 92900, 0x85, 0x00, 5, 85 92900, 5, 5, 4, 13, 29, 29, 29 },
112 4, 13, 29, 29, 29, 53476 },
113 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 121500, /* 121.5 Mb */ 86 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 121500, /* 121.5 Mb */
114 102700, 0x86, 0x00, 6, 87 102700, 6, 6, 4, 14, 30, 30, 30 },
115 4, 14, 30, 30, 30, 60156 },
116 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 135000, /* 135 Mb */ 88 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 135000, /* 135 Mb */
117 112000, 0x87, 0x00, 7, 89 112000, 7, 7, 4, 15, 31, 32, 32 },
118 4, 15, 31, 32, 32, 66840 },
119 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000, /* 150 Mb */ 90 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000, /* 150 Mb */
120 122000, 0x87, 0x00, 7, 91 122000, 7, 7, 4, 15, 31, 32, 32 },
121 4, 15, 31, 32, 32, 74200 },
122 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 27000, /* 27 Mb */ 92 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 27000, /* 27 Mb */
123 25800, 0x88, 0x00, 8, 93 25800, 8, 8, 0, 16, 33, 33, 33 },
124 0, 16, 33, 33, 33, 13360 },
125 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 54000, /* 54 Mb */ 94 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 54000, /* 54 Mb */
126 49800, 0x89, 0x00, 9, 95 49800, 9, 9, 2, 17, 34, 34, 34 },
127 2, 17, 34, 34, 34, 26720 },
128 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 81000, /* 81 Mb */ 96 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 81000, /* 81 Mb */
129 71900, 0x8a, 0x00, 10, 97 71900, 10, 10, 2, 18, 35, 35, 35 },
130 2, 18, 35, 35, 35, 40080 },
131 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 108000, /* 108 Mb */ 98 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 108000, /* 108 Mb */
132 92500, 0x8b, 0x00, 11, 99 92500, 11, 11, 4, 19, 36, 36, 36 },
133 4, 19, 36, 36, 36, 53440 },
134 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 162000, /* 162 Mb */ 100 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 162000, /* 162 Mb */
135 130300, 0x8c, 0x00, 12, 101 130300, 12, 12, 4, 20, 37, 37, 37 },
136 4, 20, 37, 37, 37, 80160 },
137 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 216000, /* 216 Mb */ 102 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 216000, /* 216 Mb */
138 162800, 0x8d, 0x00, 13, 103 162800, 13, 13, 4, 21, 38, 38, 38 },
139 4, 21, 38, 38, 38, 106880 },
140 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 243000, /* 243 Mb */ 104 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 243000, /* 243 Mb */
141 178200, 0x8e, 0x00, 14, 105 178200, 14, 14, 4, 22, 39, 39, 39 },
142 4, 22, 39, 39, 39, 120240 },
143 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 270000, /* 270 Mb */ 106 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 270000, /* 270 Mb */
144 192100, 0x8f, 0x00, 15, 107 192100, 15, 15, 4, 23, 40, 41, 41 },
145 4, 23, 40, 41, 41, 133600 },
146 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS_HGI, 300000, /* 300 Mb */ 108 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS_HGI, 300000, /* 300 Mb */
147 207000, 0x8f, 0x00, 15, 109 207000, 15, 15, 4, 23, 40, 41, 41 },
148 4, 23, 40, 41, 41, 148400 },
149 }, 110 },
150 50, /* probe interval */ 111 50, /* probe interval */
151 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ 112 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
@@ -156,177 +117,125 @@ static const struct ath_rate_table ar5416_11na_ratetable = {
156 117
157static const struct ath_rate_table ar5416_11ng_ratetable = { 118static const struct ath_rate_table ar5416_11ng_ratetable = {
158 46, 119 46,
120 12, /* MCS start */
159 { 121 {
160 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 1000, /* 1 Mb */ 122 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 1000, /* 1 Mb */
161 900, 0x1b, 0x00, 2, 123 900, 0, 2, 0, 0, 0, 0, 0 },
162 0, 0, 0, 0, 0, 0 },
163 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 2000, /* 2 Mb */ 124 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 2000, /* 2 Mb */
164 1900, 0x1a, 0x04, 4, 125 1900, 1, 4, 1, 1, 1, 1, 1 },
165 1, 1, 1, 1, 1, 0 },
166 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 5500, /* 5.5 Mb */ 126 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 5500, /* 5.5 Mb */
167 4900, 0x19, 0x04, 11, 127 4900, 2, 11, 2, 2, 2, 2, 2 },
168 2, 2, 2, 2, 2, 0 },
169 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 11000, /* 11 Mb */ 128 { VALID_ALL, VALID_ALL, WLAN_RC_PHY_CCK, 11000, /* 11 Mb */
170 8100, 0x18, 0x04, 22, 129 8100, 3, 22, 3, 3, 3, 3, 3 },
171 3, 3, 3, 3, 3, 0 },
172 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */ 130 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */
173 5400, 0x0b, 0x00, 12, 131 5400, 4, 12, 4, 4, 4, 4, 4 },
174 4, 4, 4, 4, 4, 0 },
175 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */ 132 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */
176 7800, 0x0f, 0x00, 18, 133 7800, 5, 18, 4, 5, 5, 5, 5 },
177 4, 5, 5, 5, 5, 0 },
178 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */ 134 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */
179 10100, 0x0a, 0x00, 24, 135 10100, 6, 24, 6, 6, 6, 6, 6 },
180 6, 6, 6, 6, 6, 0 },
181 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */ 136 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */
182 14100, 0x0e, 0x00, 36, 137 14100, 7, 36, 6, 7, 7, 7, 7 },
183 6, 7, 7, 7, 7, 0 },
184 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */ 138 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */
185 17700, 0x09, 0x00, 48, 139 17700, 8, 48, 8, 8, 8, 8, 8 },
186 8, 8, 8, 8, 8, 0 },
187 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */ 140 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */
188 23700, 0x0d, 0x00, 72, 141 23700, 9, 72, 8, 9, 9, 9, 9 },
189 8, 9, 9, 9, 9, 0 },
190 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */ 142 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */
191 27400, 0x08, 0x00, 96, 143 27400, 10, 96, 8, 10, 10, 10, 10 },
192 8, 10, 10, 10, 10, 0 },
193 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */ 144 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */
194 30900, 0x0c, 0x00, 108, 145 30900, 11, 108, 8, 11, 11, 11, 11 },
195 8, 11, 11, 11, 11, 0 },
196 { INVALID, INVALID, WLAN_RC_PHY_HT_20_SS, 6500, /* 6.5 Mb */ 146 { INVALID, INVALID, WLAN_RC_PHY_HT_20_SS, 6500, /* 6.5 Mb */
197 6400, 0x80, 0x00, 0, 147 6400, 0, 0, 4, 12, 28, 12, 28 },
198 4, 12, 28, 12, 28, 3216 },
199 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 13000, /* 13 Mb */ 148 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 13000, /* 13 Mb */
200 12700, 0x81, 0x00, 1, 149 12700, 1, 1, 6, 13, 29, 13, 29 },
201 6, 13, 29, 13, 29, 6434 },
202 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 19500, /* 19.5 Mb */ 150 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 19500, /* 19.5 Mb */
203 18800, 0x82, 0x00, 2, 151 18800, 2, 2, 6, 14, 30, 14, 30 },
204 6, 14, 30, 14, 30, 9650 },
205 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 26000, /* 26 Mb */ 152 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 26000, /* 26 Mb */
206 25000, 0x83, 0x00, 3, 153 25000, 3, 3, 8, 15, 31, 15, 31 },
207 8, 15, 31, 15, 31, 12868 },
208 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 39000, /* 39 Mb */ 154 { VALID_20, VALID_20, WLAN_RC_PHY_HT_20_SS, 39000, /* 39 Mb */
209 36700, 0x84, 0x00, 4, 155 36700, 4, 4, 8, 16, 32, 16, 32 },
210 8, 16, 32, 16, 32, 19304 },
211 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 52000, /* 52 Mb */ 156 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 52000, /* 52 Mb */
212 48100, 0x85, 0x00, 5, 157 48100, 5, 5, 8, 17, 33, 17, 33 },
213 8, 17, 33, 17, 33, 25740 },
214 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 58500, /* 58.5 Mb */ 158 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 58500, /* 58.5 Mb */
215 53500, 0x86, 0x00, 6, 159 53500, 6, 6, 8, 18, 34, 18, 34 },
216 8, 18, 34, 18, 34, 28956 },
217 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 65000, /* 65 Mb */ 160 { INVALID, VALID_20, WLAN_RC_PHY_HT_20_SS, 65000, /* 65 Mb */
218 59000, 0x87, 0x00, 7, 161 59000, 7, 7, 8, 19, 35, 19, 36 },
219 8, 19, 35, 19, 36, 32180 },
220 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 13000, /* 13 Mb */ 162 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 13000, /* 13 Mb */
221 12700, 0x88, 0x00, 8, 163 12700, 8, 8, 4, 20, 37, 20, 37 },
222 4, 20, 37, 20, 37, 6430 },
223 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 26000, /* 26 Mb */ 164 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 26000, /* 26 Mb */
224 24800, 0x89, 0x00, 9, 165 24800, 9, 9, 6, 21, 38, 21, 38 },
225 6, 21, 38, 21, 38, 12860 },
226 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 39000, /* 39 Mb */ 166 { INVALID, INVALID, WLAN_RC_PHY_HT_20_DS, 39000, /* 39 Mb */
227 36600, 0x8a, 0x00, 10, 167 36600, 10, 10, 6, 22, 39, 22, 39 },
228 6, 22, 39, 22, 39, 19300 },
229 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 52000, /* 52 Mb */ 168 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 52000, /* 52 Mb */
230 48100, 0x8b, 0x00, 11, 169 48100, 11, 11, 8, 23, 40, 23, 40 },
231 8, 23, 40, 23, 40, 25736 },
232 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 78000, /* 78 Mb */ 170 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 78000, /* 78 Mb */
233 69500, 0x8c, 0x00, 12, 171 69500, 12, 12, 8, 24, 41, 24, 41 },
234 8, 24, 41, 24, 41, 38600 },
235 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 104000, /* 104 Mb */ 172 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 104000, /* 104 Mb */
236 89500, 0x8d, 0x00, 13, 173 89500, 13, 13, 8, 25, 42, 25, 42 },
237 8, 25, 42, 25, 42, 51472 },
238 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 117000, /* 117 Mb */ 174 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 117000, /* 117 Mb */
239 98900, 0x8e, 0x00, 14, 175 98900, 14, 14, 8, 26, 43, 26, 44 },
240 8, 26, 43, 26, 44, 57890 },
241 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 130000, /* 130 Mb */ 176 { VALID_20, INVALID, WLAN_RC_PHY_HT_20_DS, 130000, /* 130 Mb */
242 108300, 0x8f, 0x00, 15, 177 108300, 15, 15, 8, 27, 44, 27, 45 },
243 8, 27, 44, 27, 45, 64320 },
244 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 13500, /* 13.5 Mb */ 178 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 13500, /* 13.5 Mb */
245 13200, 0x80, 0x00, 0, 179 13200, 0, 0, 8, 12, 28, 28, 28 },
246 8, 12, 28, 28, 28, 6684 },
247 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 27500, /* 27.0 Mb */ 180 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 27500, /* 27.0 Mb */
248 25900, 0x81, 0x00, 1, 181 25900, 1, 1, 8, 13, 29, 29, 29 },
249 8, 13, 29, 29, 29, 13368 },
250 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 40500, /* 40.5 Mb */ 182 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 40500, /* 40.5 Mb */
251 38600, 0x82, 0x00, 2, 183 38600, 2, 2, 8, 14, 30, 30, 30 },
252 8, 14, 30, 30, 30, 20052 },
253 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 54000, /* 54 Mb */ 184 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 54000, /* 54 Mb */
254 49800, 0x83, 0x00, 3, 185 49800, 3, 3, 8, 15, 31, 31, 31 },
255 8, 15, 31, 31, 31, 26738 },
256 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 81500, /* 81 Mb */ 186 { VALID_40, VALID_40, WLAN_RC_PHY_HT_40_SS, 81500, /* 81 Mb */
257 72200, 0x84, 0x00, 4, 187 72200, 4, 4, 8, 16, 32, 32, 32 },
258 8, 16, 32, 32, 32, 40104 },
259 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 108000, /* 108 Mb */ 188 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 108000, /* 108 Mb */
260 92900, 0x85, 0x00, 5, 189 92900, 5, 5, 8, 17, 33, 33, 33 },
261 8, 17, 33, 33, 33, 53476 },
262 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 121500, /* 121.5 Mb */ 190 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 121500, /* 121.5 Mb */
263 102700, 0x86, 0x00, 6, 191 102700, 6, 6, 8, 18, 34, 34, 34 },
264 8, 18, 34, 34, 34, 60156 },
265 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 135000, /* 135 Mb */ 192 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS, 135000, /* 135 Mb */
266 112000, 0x87, 0x00, 7, 193 112000, 7, 7, 8, 19, 35, 36, 36 },
267 8, 19, 35, 36, 36, 66840 },
268 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000, /* 150 Mb */ 194 { INVALID, VALID_40, WLAN_RC_PHY_HT_40_SS_HGI, 150000, /* 150 Mb */
269 122000, 0x87, 0x00, 7, 195 122000, 7, 7, 8, 19, 35, 36, 36 },
270 8, 19, 35, 36, 36, 74200 },
271 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 27000, /* 27 Mb */ 196 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 27000, /* 27 Mb */
272 25800, 0x88, 0x00, 8, 197 25800, 8, 8, 8, 20, 37, 37, 37 },
273 8, 20, 37, 37, 37, 13360 },
274 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 54000, /* 54 Mb */ 198 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 54000, /* 54 Mb */
275 49800, 0x89, 0x00, 9, 199 49800, 9, 9, 8, 21, 38, 38, 38 },
276 8, 21, 38, 38, 38, 26720 },
277 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 81000, /* 81 Mb */ 200 { INVALID, INVALID, WLAN_RC_PHY_HT_40_DS, 81000, /* 81 Mb */
278 71900, 0x8a, 0x00, 10, 201 71900, 10, 10, 8, 22, 39, 39, 39 },
279 8, 22, 39, 39, 39, 40080 },
280 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 108000, /* 108 Mb */ 202 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 108000, /* 108 Mb */
281 92500, 0x8b, 0x00, 11, 203 92500, 11, 11, 8, 23, 40, 40, 40 },
282 8, 23, 40, 40, 40, 53440 },
283 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 162000, /* 162 Mb */ 204 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 162000, /* 162 Mb */
284 130300, 0x8c, 0x00, 12, 205 130300, 12, 12, 8, 24, 41, 41, 41 },
285 8, 24, 41, 41, 41, 80160 },
286 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 216000, /* 216 Mb */ 206 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 216000, /* 216 Mb */
287 162800, 0x8d, 0x00, 13, 207 162800, 13, 13, 8, 25, 42, 42, 42 },
288 8, 25, 42, 42, 42, 106880 },
289 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 243000, /* 243 Mb */ 208 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 243000, /* 243 Mb */
290 178200, 0x8e, 0x00, 14, 209 178200, 14, 14, 8, 26, 43, 43, 43 },
291 8, 26, 43, 43, 43, 120240 },
292 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 270000, /* 270 Mb */ 210 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS, 270000, /* 270 Mb */
293 192100, 0x8f, 0x00, 15, 211 192100, 15, 15, 8, 27, 44, 45, 45 },
294 8, 27, 44, 45, 45, 133600 },
295 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS_HGI, 300000, /* 300 Mb */ 212 { VALID_40, INVALID, WLAN_RC_PHY_HT_40_DS_HGI, 300000, /* 300 Mb */
296 207000, 0x8f, 0x00, 15, 213 207000, 15, 15, 8, 27, 44, 45, 45 },
297 8, 27, 44, 45, 45, 148400 }, 214 },
298 },
299 50, /* probe interval */ 215 50, /* probe interval */
300 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ 216 WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
301}; 217};
302 218
303static const struct ath_rate_table ar5416_11a_ratetable = { 219static const struct ath_rate_table ar5416_11a_ratetable = {
304 8, 220 8,
221 0,
305 { 222 {
306 { VALID, VALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */ 223 { VALID, VALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */
307 5400, 0x0b, 0x00, (0x80|12), 224 5400, 0, 12, 0, 0, 0 },
308 0, 0, 0 },
309 { VALID, VALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */ 225 { VALID, VALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */
310 7800, 0x0f, 0x00, 18, 226 7800, 1, 18, 0, 1, 0 },
311 0, 1, 0 },
312 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */ 227 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */
313 10000, 0x0a, 0x00, (0x80|24), 228 10000, 2, 24, 2, 2, 0 },
314 2, 2, 0 },
315 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */ 229 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */
316 13900, 0x0e, 0x00, 36, 230 13900, 3, 36, 2, 3, 0 },
317 2, 3, 0 },
318 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */ 231 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */
319 17300, 0x09, 0x00, (0x80|48), 232 17300, 4, 48, 4, 4, 0 },
320 4, 4, 0 },
321 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */ 233 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */
322 23000, 0x0d, 0x00, 72, 234 23000, 5, 72, 4, 5, 0 },
323 4, 5, 0 },
324 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */ 235 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */
325 27400, 0x08, 0x00, 96, 236 27400, 6, 96, 4, 6, 0 },
326 4, 6, 0 },
327 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */ 237 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */
328 29300, 0x0c, 0x00, 108, 238 29300, 7, 108, 4, 7, 0 },
329 4, 7, 0 },
330 }, 239 },
331 50, /* probe interval */ 240 50, /* probe interval */
332 0, /* Phy rates allowed initially */ 241 0, /* Phy rates allowed initially */
@@ -334,48 +243,51 @@ static const struct ath_rate_table ar5416_11a_ratetable = {
334 243
335static const struct ath_rate_table ar5416_11g_ratetable = { 244static const struct ath_rate_table ar5416_11g_ratetable = {
336 12, 245 12,
246 0,
337 { 247 {
338 { VALID, VALID, WLAN_RC_PHY_CCK, 1000, /* 1 Mb */ 248 { VALID, VALID, WLAN_RC_PHY_CCK, 1000, /* 1 Mb */
339 900, 0x1b, 0x00, 2, 249 900, 0, 2, 0, 0, 0 },
340 0, 0, 0 },
341 { VALID, VALID, WLAN_RC_PHY_CCK, 2000, /* 2 Mb */ 250 { VALID, VALID, WLAN_RC_PHY_CCK, 2000, /* 2 Mb */
342 1900, 0x1a, 0x04, 4, 251 1900, 1, 4, 1, 1, 0 },
343 1, 1, 0 },
344 { VALID, VALID, WLAN_RC_PHY_CCK, 5500, /* 5.5 Mb */ 252 { VALID, VALID, WLAN_RC_PHY_CCK, 5500, /* 5.5 Mb */
345 4900, 0x19, 0x04, 11, 253 4900, 2, 11, 2, 2, 0 },
346 2, 2, 0 },
347 { VALID, VALID, WLAN_RC_PHY_CCK, 11000, /* 11 Mb */ 254 { VALID, VALID, WLAN_RC_PHY_CCK, 11000, /* 11 Mb */
348 8100, 0x18, 0x04, 22, 255 8100, 3, 22, 3, 3, 0 },
349 3, 3, 0 },
350 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */ 256 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 6000, /* 6 Mb */
351 5400, 0x0b, 0x00, 12, 257 5400, 4, 12, 4, 4, 0 },
352 4, 4, 0 },
353 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */ 258 { INVALID, INVALID, WLAN_RC_PHY_OFDM, 9000, /* 9 Mb */
354 7800, 0x0f, 0x00, 18, 259 7800, 5, 18, 4, 5, 0 },
355 4, 5, 0 },
356 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */ 260 { VALID, VALID, WLAN_RC_PHY_OFDM, 12000, /* 12 Mb */
357 10000, 0x0a, 0x00, 24, 261 10000, 6, 24, 6, 6, 0 },
358 6, 6, 0 },
359 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */ 262 { VALID, VALID, WLAN_RC_PHY_OFDM, 18000, /* 18 Mb */
360 13900, 0x0e, 0x00, 36, 263 13900, 7, 36, 6, 7, 0 },
361 6, 7, 0 },
362 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */ 264 { VALID, VALID, WLAN_RC_PHY_OFDM, 24000, /* 24 Mb */
363 17300, 0x09, 0x00, 48, 265 17300, 8, 48, 8, 8, 0 },
364 8, 8, 0 },
365 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */ 266 { VALID, VALID, WLAN_RC_PHY_OFDM, 36000, /* 36 Mb */
366 23000, 0x0d, 0x00, 72, 267 23000, 9, 72, 8, 9, 0 },
367 8, 9, 0 },
368 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */ 268 { VALID, VALID, WLAN_RC_PHY_OFDM, 48000, /* 48 Mb */
369 27400, 0x08, 0x00, 96, 269 27400, 10, 96, 8, 10, 0 },
370 8, 10, 0 },
371 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */ 270 { VALID, VALID, WLAN_RC_PHY_OFDM, 54000, /* 54 Mb */
372 29300, 0x0c, 0x00, 108, 271 29300, 11, 108, 8, 11, 0 },
373 8, 11, 0 },
374 }, 272 },
375 50, /* probe interval */ 273 50, /* probe interval */
376 0, /* Phy rates allowed initially */ 274 0, /* Phy rates allowed initially */
377}; 275};
378 276
277static const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX] = {
278 [ATH9K_MODE_11A] = &ar5416_11a_ratetable,
279 [ATH9K_MODE_11G] = &ar5416_11g_ratetable,
280 [ATH9K_MODE_11NA_HT20] = &ar5416_11na_ratetable,
281 [ATH9K_MODE_11NG_HT20] = &ar5416_11ng_ratetable,
282 [ATH9K_MODE_11NA_HT40PLUS] = &ar5416_11na_ratetable,
283 [ATH9K_MODE_11NA_HT40MINUS] = &ar5416_11na_ratetable,
284 [ATH9K_MODE_11NG_HT40PLUS] = &ar5416_11ng_ratetable,
285 [ATH9K_MODE_11NG_HT40MINUS] = &ar5416_11ng_ratetable,
286};
287
288static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
289 struct ieee80211_tx_rate *rate);
290
379static inline int8_t median(int8_t a, int8_t b, int8_t c) 291static inline int8_t median(int8_t a, int8_t b, int8_t c)
380{ 292{
381 if (a >= b) { 293 if (a >= b) {
@@ -425,7 +337,7 @@ static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
425static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv, 337static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv,
426 u8 index, int valid_tx_rate) 338 u8 index, int valid_tx_rate)
427{ 339{
428 ASSERT(index <= ath_rc_priv->rate_table_size); 340 BUG_ON(index > ath_rc_priv->rate_table_size);
429 ath_rc_priv->valid_rate_index[index] = valid_tx_rate ? 1 : 0; 341 ath_rc_priv->valid_rate_index[index] = valid_tx_rate ? 1 : 0;
430} 342}
431 343
@@ -534,7 +446,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
534 * capflag matches one of the validity 446 * capflag matches one of the validity
535 * (VALID/VALID_20/VALID_40) flags */ 447 * (VALID/VALID_20/VALID_40) flags */
536 448
537 if (((rate & 0x7F) == (dot11rate & 0x7F)) && 449 if ((rate == dot11rate) &&
538 ((valid & WLAN_RC_CAP_MODE(capflag)) == 450 ((valid & WLAN_RC_CAP_MODE(capflag)) ==
539 WLAN_RC_CAP_MODE(capflag)) && 451 WLAN_RC_CAP_MODE(capflag)) &&
540 !WLAN_RC_PHY_HT(phy)) { 452 !WLAN_RC_PHY_HT(phy)) {
@@ -576,8 +488,7 @@ static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv,
576 u8 rate = rateset->rs_rates[i]; 488 u8 rate = rateset->rs_rates[i];
577 u8 dot11rate = rate_table->info[j].dot11rate; 489 u8 dot11rate = rate_table->info[j].dot11rate;
578 490
579 if (((rate & 0x7F) != (dot11rate & 0x7F)) || 491 if ((rate != dot11rate) || !WLAN_RC_PHY_HT(phy) ||
580 !WLAN_RC_PHY_HT(phy) ||
581 !WLAN_RC_PHY_HT_VALID(valid, capflag)) 492 !WLAN_RC_PHY_HT_VALID(valid, capflag))
582 continue; 493 continue;
583 494
@@ -696,18 +607,20 @@ static void ath_rc_rate_set_series(const struct ath_rate_table *rate_table,
696 u8 tries, u8 rix, int rtsctsenable) 607 u8 tries, u8 rix, int rtsctsenable)
697{ 608{
698 rate->count = tries; 609 rate->count = tries;
699 rate->idx = rix; 610 rate->idx = rate_table->info[rix].ratecode;
700 611
701 if (txrc->short_preamble) 612 if (txrc->short_preamble)
702 rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE; 613 rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
703 if (txrc->rts || rtsctsenable) 614 if (txrc->rts || rtsctsenable)
704 rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS; 615 rate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
705 if (WLAN_RC_PHY_40(rate_table->info[rix].phy)) 616
706 rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 617 if (WLAN_RC_PHY_HT(rate_table->info[rix].phy)) {
707 if (WLAN_RC_PHY_SGI(rate_table->info[rix].phy))
708 rate->flags |= IEEE80211_TX_RC_SHORT_GI;
709 if (WLAN_RC_PHY_HT(rate_table->info[rix].phy))
710 rate->flags |= IEEE80211_TX_RC_MCS; 618 rate->flags |= IEEE80211_TX_RC_MCS;
619 if (WLAN_RC_PHY_40(rate_table->info[rix].phy))
620 rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
621 if (WLAN_RC_PHY_SGI(rate_table->info[rix].phy))
622 rate->flags |= IEEE80211_TX_RC_SHORT_GI;
623 }
711} 624}
712 625
713static void ath_rc_rate_set_rtscts(struct ath_softc *sc, 626static void ath_rc_rate_set_rtscts(struct ath_softc *sc,
@@ -720,7 +633,7 @@ static void ath_rc_rate_set_rtscts(struct ath_softc *sc,
720 /* get the cix for the lowest valid rix */ 633 /* get the cix for the lowest valid rix */
721 for (i = 3; i >= 0; i--) { 634 for (i = 3; i >= 0; i--) {
722 if (rates[i].count && (rates[i].idx >= 0)) { 635 if (rates[i].count && (rates[i].idx >= 0)) {
723 rix = rates[i].idx; 636 rix = ath_rc_get_rateindex(rate_table, &rates[i]);
724 break; 637 break;
725 } 638 }
726 } 639 }
@@ -757,7 +670,7 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
757 struct ieee80211_tx_rate *rates = tx_info->control.rates; 670 struct ieee80211_tx_rate *rates = tx_info->control.rates;
758 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 671 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
759 __le16 fc = hdr->frame_control; 672 __le16 fc = hdr->frame_control;
760 u8 try_per_rate, i = 0, rix, nrix; 673 u8 try_per_rate, i = 0, rix;
761 int is_probe = 0; 674 int is_probe = 0;
762 675
763 if (rate_control_send_low(sta, priv_sta, txrc)) 676 if (rate_control_send_low(sta, priv_sta, txrc))
@@ -767,48 +680,47 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
767 * For Multi Rate Retry we use a different number of 680 * For Multi Rate Retry we use a different number of
768 * retry attempt counts. This ends up looking like this: 681 * retry attempt counts. This ends up looking like this:
769 * 682 *
770 * MRR[0] = 2 683 * MRR[0] = 4
771 * MRR[1] = 2 684 * MRR[1] = 4
772 * MRR[2] = 2 685 * MRR[2] = 4
773 * MRR[3] = 4 686 * MRR[3] = 8
774 * 687 *
775 */ 688 */
776 try_per_rate = sc->hw->max_rate_tries; 689 try_per_rate = 4;
777 690
778 rate_table = sc->cur_rate_table; 691 rate_table = sc->cur_rate_table;
779 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe); 692 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
780 nrix = rix;
781 693
782 if (is_probe) { 694 if (is_probe) {
783 /* set one try for probe rates. For the 695 /* set one try for probe rates. For the
784 * probes don't enable rts */ 696 * probes don't enable rts */
785 ath_rc_rate_set_series(rate_table, &rates[i++], txrc, 697 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
786 1, nrix, 0); 698 1, rix, 0);
787 699
788 /* Get the next tried/allowed rate. No RTS for the next series 700 /* Get the next tried/allowed rate. No RTS for the next series
789 * after the probe rate 701 * after the probe rate
790 */ 702 */
791 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &nrix); 703 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix);
792 ath_rc_rate_set_series(rate_table, &rates[i++], txrc, 704 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
793 try_per_rate, nrix, 0); 705 try_per_rate, rix, 0);
794 706
795 tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE; 707 tx_info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE;
796 } else { 708 } else {
797 /* Set the choosen rate. No RTS for first series entry. */ 709 /* Set the choosen rate. No RTS for first series entry. */
798 ath_rc_rate_set_series(rate_table, &rates[i++], txrc, 710 ath_rc_rate_set_series(rate_table, &rates[i++], txrc,
799 try_per_rate, nrix, 0); 711 try_per_rate, rix, 0);
800 } 712 }
801 713
802 /* Fill in the other rates for multirate retry */ 714 /* Fill in the other rates for multirate retry */
803 for ( ; i < 4; i++) { 715 for ( ; i < 4; i++) {
804 /* Use twice the number of tries for the last MRR segment. */ 716 /* Use twice the number of tries for the last MRR segment. */
805 if (i + 1 == 4) 717 if (i + 1 == 4)
806 try_per_rate = 4; 718 try_per_rate = 8;
807 719
808 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &nrix); 720 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix);
809 /* All other rates in the series have RTS enabled */ 721 /* All other rates in the series have RTS enabled */
810 ath_rc_rate_set_series(rate_table, &rates[i], txrc, 722 ath_rc_rate_set_series(rate_table, &rates[i], txrc,
811 try_per_rate, nrix, 1); 723 try_per_rate, rix, 1);
812 } 724 }
813 725
814 /* 726 /*
@@ -859,12 +771,12 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
859static bool ath_rc_update_per(struct ath_softc *sc, 771static bool ath_rc_update_per(struct ath_softc *sc,
860 const struct ath_rate_table *rate_table, 772 const struct ath_rate_table *rate_table,
861 struct ath_rate_priv *ath_rc_priv, 773 struct ath_rate_priv *ath_rc_priv,
862 struct ath_tx_info_priv *tx_info_priv, 774 struct ieee80211_tx_info *tx_info,
863 int tx_rate, int xretries, int retries, 775 int tx_rate, int xretries, int retries,
864 u32 now_msec) 776 u32 now_msec)
865{ 777{
866 bool state_change = false; 778 bool state_change = false;
867 int count; 779 int count, n_bad_frames;
868 u8 last_per; 780 u8 last_per;
869 static u32 nretry_to_per_lookup[10] = { 781 static u32 nretry_to_per_lookup[10] = {
870 100 * 0 / 1, 782 100 * 0 / 1,
@@ -880,6 +792,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
880 }; 792 };
881 793
882 last_per = ath_rc_priv->per[tx_rate]; 794 last_per = ath_rc_priv->per[tx_rate];
795 n_bad_frames = tx_info->status.ampdu_len - tx_info->status.ampdu_ack_len;
883 796
884 if (xretries) { 797 if (xretries) {
885 if (xretries == 1) { 798 if (xretries == 1) {
@@ -907,7 +820,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
907 if (retries >= count) 820 if (retries >= count)
908 retries = count - 1; 821 retries = count - 1;
909 822
910 if (tx_info_priv->n_bad_frames) { 823 if (n_bad_frames) {
911 /* new_PER = 7/8*old_PER + 1/8*(currentPER) 824 /* new_PER = 7/8*old_PER + 1/8*(currentPER)
912 * Assuming that n_frames is not 0. The current PER 825 * Assuming that n_frames is not 0. The current PER
913 * from the retries is 100 * retries / (retries+1), 826 * from the retries is 100 * retries / (retries+1),
@@ -920,14 +833,14 @@ static bool ath_rc_update_per(struct ath_softc *sc,
920 * the above PER. The expression below is a 833 * the above PER. The expression below is a
921 * simplified version of the sum of these two terms. 834 * simplified version of the sum of these two terms.
922 */ 835 */
923 if (tx_info_priv->n_frames > 0) { 836 if (tx_info->status.ampdu_len > 0) {
924 int n_frames, n_bad_frames; 837 int n_frames, n_bad_tries;
925 u8 cur_per, new_per; 838 u8 cur_per, new_per;
926 839
927 n_bad_frames = retries * tx_info_priv->n_frames + 840 n_bad_tries = retries * tx_info->status.ampdu_len +
928 tx_info_priv->n_bad_frames; 841 n_bad_frames;
929 n_frames = tx_info_priv->n_frames * (retries + 1); 842 n_frames = tx_info->status.ampdu_len * (retries + 1);
930 cur_per = (100 * n_bad_frames / n_frames) >> 3; 843 cur_per = (100 * n_bad_tries / n_frames) >> 3;
931 new_per = (u8)(last_per - (last_per >> 3) + cur_per); 844 new_per = (u8)(last_per - (last_per >> 3) + cur_per);
932 ath_rc_priv->per[tx_rate] = new_per; 845 ath_rc_priv->per[tx_rate] = new_per;
933 } 846 }
@@ -943,8 +856,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
943 * this was a probe. Otherwise, ignore the probe. 856 * this was a probe. Otherwise, ignore the probe.
944 */ 857 */
945 if (ath_rc_priv->probe_rate && ath_rc_priv->probe_rate == tx_rate) { 858 if (ath_rc_priv->probe_rate && ath_rc_priv->probe_rate == tx_rate) {
946 if (retries > 0 || 2 * tx_info_priv->n_bad_frames > 859 if (retries > 0 || 2 * n_bad_frames > tx_info->status.ampdu_len) {
947 tx_info_priv->n_frames) {
948 /* 860 /*
949 * Since we probed with just a single attempt, 861 * Since we probed with just a single attempt,
950 * any retries means the probe failed. Also, 862 * any retries means the probe failed. Also,
@@ -969,7 +881,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
969 * Since this probe succeeded, we allow the next 881 * Since this probe succeeded, we allow the next
970 * probe twice as soon. This allows the maxRate 882 * probe twice as soon. This allows the maxRate
971 * to move up faster if the probes are 883 * to move up faster if the probes are
972 * succesful. 884 * successful.
973 */ 885 */
974 ath_rc_priv->probe_time = 886 ath_rc_priv->probe_time =
975 now_msec - rate_table->probe_interval / 2; 887 now_msec - rate_table->probe_interval / 2;
@@ -1003,7 +915,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
1003 915
1004static void ath_rc_update_ht(struct ath_softc *sc, 916static void ath_rc_update_ht(struct ath_softc *sc,
1005 struct ath_rate_priv *ath_rc_priv, 917 struct ath_rate_priv *ath_rc_priv,
1006 struct ath_tx_info_priv *tx_info_priv, 918 struct ieee80211_tx_info *tx_info,
1007 int tx_rate, int xretries, int retries) 919 int tx_rate, int xretries, int retries)
1008{ 920{
1009 u32 now_msec = jiffies_to_msecs(jiffies); 921 u32 now_msec = jiffies_to_msecs(jiffies);
@@ -1020,7 +932,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
1020 932
1021 /* Update PER first */ 933 /* Update PER first */
1022 state_change = ath_rc_update_per(sc, rate_table, ath_rc_priv, 934 state_change = ath_rc_update_per(sc, rate_table, ath_rc_priv,
1023 tx_info_priv, tx_rate, xretries, 935 tx_info, tx_rate, xretries,
1024 retries, now_msec); 936 retries, now_msec);
1025 937
1026 /* 938 /*
@@ -1080,15 +992,19 @@ static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
1080{ 992{
1081 int rix; 993 int rix;
1082 994
995 if (!(rate->flags & IEEE80211_TX_RC_MCS))
996 return rate->idx;
997
998 rix = rate->idx + rate_table->mcs_start;
1083 if ((rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) && 999 if ((rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) &&
1084 (rate->flags & IEEE80211_TX_RC_SHORT_GI)) 1000 (rate->flags & IEEE80211_TX_RC_SHORT_GI))
1085 rix = rate_table->info[rate->idx].ht_index; 1001 rix = rate_table->info[rix].ht_index;
1086 else if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 1002 else if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
1087 rix = rate_table->info[rate->idx].sgi_index; 1003 rix = rate_table->info[rix].sgi_index;
1088 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1004 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1089 rix = rate_table->info[rate->idx].cw40index; 1005 rix = rate_table->info[rix].cw40index;
1090 else 1006 else
1091 rix = rate_table->info[rate->idx].base_index; 1007 rix = rate_table->info[rix].base_index;
1092 1008
1093 return rix; 1009 return rix;
1094} 1010}
@@ -1098,7 +1014,6 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1098 struct ieee80211_tx_info *tx_info, 1014 struct ieee80211_tx_info *tx_info,
1099 int final_ts_idx, int xretries, int long_retry) 1015 int final_ts_idx, int xretries, int long_retry)
1100{ 1016{
1101 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1102 const struct ath_rate_table *rate_table; 1017 const struct ath_rate_table *rate_table;
1103 struct ieee80211_tx_rate *rates = tx_info->status.rates; 1018 struct ieee80211_tx_rate *rates = tx_info->status.rates;
1104 u8 flags; 1019 u8 flags;
@@ -1124,9 +1039,8 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1124 return; 1039 return;
1125 1040
1126 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 1041 rix = ath_rc_get_rateindex(rate_table, &rates[i]);
1127 ath_rc_update_ht(sc, ath_rc_priv, 1042 ath_rc_update_ht(sc, ath_rc_priv, tx_info,
1128 tx_info_priv, rix, 1043 rix, xretries ? 1 : 2,
1129 xretries ? 1 : 2,
1130 rates[i].count); 1044 rates[i].count);
1131 } 1045 }
1132 } 1046 }
@@ -1149,8 +1063,7 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1149 return; 1063 return;
1150 1064
1151 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 1065 rix = ath_rc_get_rateindex(rate_table, &rates[i]);
1152 ath_rc_update_ht(sc, ath_rc_priv, tx_info_priv, rix, 1066 ath_rc_update_ht(sc, ath_rc_priv, tx_info, rix, xretries, long_retry);
1153 xretries, long_retry);
1154} 1067}
1155 1068
1156static const 1069static const
@@ -1160,6 +1073,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1160 bool is_cw_40) 1073 bool is_cw_40)
1161{ 1074{
1162 int mode = 0; 1075 int mode = 0;
1076 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1163 1077
1164 switch(band) { 1078 switch(band) {
1165 case IEEE80211_BAND_2GHZ: 1079 case IEEE80211_BAND_2GHZ:
@@ -1177,14 +1091,17 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1177 mode = ATH9K_MODE_11NA_HT40PLUS; 1091 mode = ATH9K_MODE_11NA_HT40PLUS;
1178 break; 1092 break;
1179 default: 1093 default:
1180 DPRINTF(sc, ATH_DBG_CONFIG, "Invalid band\n"); 1094 ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
1181 return NULL; 1095 return NULL;
1182 } 1096 }
1183 1097
1184 BUG_ON(mode >= ATH9K_MODE_MAX); 1098 BUG_ON(mode >= ATH9K_MODE_MAX);
1185 1099
1186 DPRINTF(sc, ATH_DBG_CONFIG, "Choosing rate table for mode: %d\n", mode); 1100 ath_print(common, ATH_DBG_CONFIG,
1187 return sc->hw_rate_table[mode]; 1101 "Choosing rate table for mode: %d\n", mode);
1102
1103 sc->cur_rate_mode = mode;
1104 return hw_rate_table[mode];
1188} 1105}
1189 1106
1190static void ath_rc_init(struct ath_softc *sc, 1107static void ath_rc_init(struct ath_softc *sc,
@@ -1194,14 +1111,10 @@ static void ath_rc_init(struct ath_softc *sc,
1194 const struct ath_rate_table *rate_table) 1111 const struct ath_rate_table *rate_table)
1195{ 1112{
1196 struct ath_rateset *rateset = &ath_rc_priv->neg_rates; 1113 struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
1114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1197 u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates; 1115 u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates;
1198 u8 i, j, k, hi = 0, hthi = 0; 1116 u8 i, j, k, hi = 0, hthi = 0;
1199 1117
1200 if (!rate_table) {
1201 DPRINTF(sc, ATH_DBG_FATAL, "Rate table not initialized\n");
1202 return;
1203 }
1204
1205 /* Initial rate table size. Will change depending 1118 /* Initial rate table size. Will change depending
1206 * on the working rate set */ 1119 * on the working rate set */
1207 ath_rc_priv->rate_table_size = RATE_TABLE_SIZE; 1120 ath_rc_priv->rate_table_size = RATE_TABLE_SIZE;
@@ -1239,7 +1152,7 @@ static void ath_rc_init(struct ath_softc *sc,
1239 1152
1240 ath_rc_priv->rate_table_size = hi + 1; 1153 ath_rc_priv->rate_table_size = hi + 1;
1241 ath_rc_priv->rate_max_phy = 0; 1154 ath_rc_priv->rate_max_phy = 0;
1242 ASSERT(ath_rc_priv->rate_table_size <= RATE_TABLE_SIZE); 1155 BUG_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE);
1243 1156
1244 for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) { 1157 for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) {
1245 for (j = 0; j < ath_rc_priv->valid_phy_ratecnt[i]; j++) { 1158 for (j = 0; j < ath_rc_priv->valid_phy_ratecnt[i]; j++) {
@@ -1253,16 +1166,17 @@ static void ath_rc_init(struct ath_softc *sc,
1253 1166
1254 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_phy_rateidx[i][j-1]; 1167 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_phy_rateidx[i][j-1];
1255 } 1168 }
1256 ASSERT(ath_rc_priv->rate_table_size <= RATE_TABLE_SIZE); 1169 BUG_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE);
1257 ASSERT(k <= RATE_TABLE_SIZE); 1170 BUG_ON(k > RATE_TABLE_SIZE);
1258 1171
1259 ath_rc_priv->max_valid_rate = k; 1172 ath_rc_priv->max_valid_rate = k;
1260 ath_rc_sort_validrates(rate_table, ath_rc_priv); 1173 ath_rc_sort_validrates(rate_table, ath_rc_priv);
1261 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; 1174 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
1262 sc->cur_rate_table = rate_table; 1175 sc->cur_rate_table = rate_table;
1263 1176
1264 DPRINTF(sc, ATH_DBG_CONFIG, "RC Initialized with capabilities: 0x%x\n", 1177 ath_print(common, ATH_DBG_CONFIG,
1265 ath_rc_priv->ht_cap); 1178 "RC Initialized with capabilities: 0x%x\n",
1179 ath_rc_priv->ht_cap);
1266} 1180}
1267 1181
1268static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, 1182static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1296,44 +1210,52 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1296{ 1210{
1297 struct ath_softc *sc = priv; 1211 struct ath_softc *sc = priv;
1298 struct ath_rate_priv *ath_rc_priv = priv_sta; 1212 struct ath_rate_priv *ath_rc_priv = priv_sta;
1299 struct ath_tx_info_priv *tx_info_priv = NULL;
1300 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1213 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1301 struct ieee80211_hdr *hdr; 1214 struct ieee80211_hdr *hdr;
1302 int final_ts_idx, tx_status = 0, is_underrun = 0; 1215 int final_ts_idx = 0, tx_status = 0, is_underrun = 0;
1216 int long_retry = 0;
1303 __le16 fc; 1217 __le16 fc;
1218 int i;
1304 1219
1305 hdr = (struct ieee80211_hdr *)skb->data; 1220 hdr = (struct ieee80211_hdr *)skb->data;
1306 fc = hdr->frame_control; 1221 fc = hdr->frame_control;
1307 tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1222 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
1308 final_ts_idx = tx_info_priv->tx.ts_rateindex; 1223 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i];
1224 if (!rate->count)
1225 break;
1226
1227 final_ts_idx = i;
1228 long_retry = rate->count - 1;
1229 }
1309 1230
1310 if (!priv_sta || !ieee80211_is_data(fc) || 1231 if (!priv_sta || !ieee80211_is_data(fc) ||
1311 !tx_info_priv->update_rc) 1232 !(tx_info->pad[0] & ATH_TX_INFO_UPDATE_RC))
1312 goto exit; 1233 return;
1313 1234
1314 if (tx_info_priv->tx.ts_status & ATH9K_TXERR_FILT) 1235 if (tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED)
1315 goto exit; 1236 return;
1316 1237
1317 /* 1238 /*
1318 * If underrun error is seen assume it as an excessive retry only 1239 * If an underrun error is seen assume it as an excessive retry only
1319 * if prefetch trigger level have reached the max (0x3f for 5416) 1240 * if max frame trigger level has been reached (2 KB for singel stream,
1320 * Adjust the long retry as if the frame was tried hw->max_rate_tries 1241 * and 4 KB for dual stream). Adjust the long retry as if the frame was
1321 * times. This affects how ratectrl updates PER for the failed rate. 1242 * tried hw->max_rate_tries times to affect how ratectrl updates PER for
1243 * the failed rate. In case of congestion on the bus penalizing these
1244 * type of underruns should help hardware actually transmit new frames
1245 * successfully by eventually preferring slower rates. This itself
1246 * should also alleviate congestion on the bus.
1322 */ 1247 */
1323 if (tx_info_priv->tx.ts_flags & 1248 if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
1324 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && 1249 (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
1325 ((sc->sc_ah->tx_trig_level) >= ath_rc_priv->tx_triglevel_max)) {
1326 tx_status = 1; 1250 tx_status = 1;
1327 is_underrun = 1; 1251 is_underrun = 1;
1328 } 1252 }
1329 1253
1330 if ((tx_info_priv->tx.ts_status & ATH9K_TXERR_XRETRY) || 1254 if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
1331 (tx_info_priv->tx.ts_status & ATH9K_TXERR_FIFO))
1332 tx_status = 1; 1255 tx_status = 1;
1333 1256
1334 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status, 1257 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
1335 (is_underrun) ? sc->hw->max_rate_tries : 1258 (is_underrun) ? sc->hw->max_rate_tries : long_retry);
1336 tx_info_priv->tx.ts_longretry);
1337 1259
1338 /* Check if aggregation has to be enabled for this tid */ 1260 /* Check if aggregation has to be enabled for this tid */
1339 if (conf_is_ht(&sc->hw->conf) && 1261 if (conf_is_ht(&sc->hw->conf) &&
@@ -1347,13 +1269,12 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1347 an = (struct ath_node *)sta->drv_priv; 1269 an = (struct ath_node *)sta->drv_priv;
1348 1270
1349 if(ath_tx_aggr_check(sc, an, tid)) 1271 if(ath_tx_aggr_check(sc, an, tid))
1350 ieee80211_start_tx_ba_session(sc->hw, hdr->addr1, tid); 1272 ieee80211_start_tx_ba_session(sta, tid);
1351 } 1273 }
1352 } 1274 }
1353 1275
1354 ath_debug_stat_rc(sc, skb); 1276 ath_debug_stat_rc(sc, ath_rc_get_rateindex(sc->cur_rate_table,
1355exit: 1277 &tx_info->status.rates[final_ts_idx]));
1356 kfree(tx_info_priv);
1357} 1278}
1358 1279
1359static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband, 1280static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
@@ -1361,7 +1282,7 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
1361{ 1282{
1362 struct ath_softc *sc = priv; 1283 struct ath_softc *sc = priv;
1363 struct ath_rate_priv *ath_rc_priv = priv_sta; 1284 struct ath_rate_priv *ath_rc_priv = priv_sta;
1364 const struct ath_rate_table *rate_table = NULL; 1285 const struct ath_rate_table *rate_table;
1365 bool is_cw40, is_sgi40; 1286 bool is_cw40, is_sgi40;
1366 int i, j = 0; 1287 int i, j = 0;
1367 1288
@@ -1393,11 +1314,9 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
1393 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) || 1314 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT) ||
1394 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) { 1315 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) {
1395 rate_table = ath_choose_rate_table(sc, sband->band, 1316 rate_table = ath_choose_rate_table(sc, sband->band,
1396 sta->ht_cap.ht_supported, 1317 sta->ht_cap.ht_supported, is_cw40);
1397 is_cw40); 1318 } else {
1398 } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { 1319 rate_table = hw_rate_table[sc->cur_rate_mode];
1399 /* cur_rate_table would be set on init through config() */
1400 rate_table = sc->cur_rate_table;
1401 } 1320 }
1402 1321
1403 ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta, is_cw40, is_sgi40); 1322 ath_rc_priv->ht_cap = ath_rc_build_ht_caps(sc, sta, is_cw40, is_sgi40);
@@ -1406,7 +1325,7 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
1406 1325
1407static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, 1326static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1408 struct ieee80211_sta *sta, void *priv_sta, 1327 struct ieee80211_sta *sta, void *priv_sta,
1409 u32 changed) 1328 u32 changed, enum nl80211_channel_type oper_chan_type)
1410{ 1329{
1411 struct ath_softc *sc = priv; 1330 struct ath_softc *sc = priv;
1412 struct ath_rate_priv *ath_rc_priv = priv_sta; 1331 struct ath_rate_priv *ath_rc_priv = priv_sta;
@@ -1423,8 +1342,8 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1423 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1342 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1424 return; 1343 return;
1425 1344
1426 if (sc->hw->conf.channel_type == NL80211_CHAN_HT40MINUS || 1345 if (oper_chan_type == NL80211_CHAN_HT40MINUS ||
1427 sc->hw->conf.channel_type == NL80211_CHAN_HT40PLUS) 1346 oper_chan_type == NL80211_CHAN_HT40PLUS)
1428 oper_cw40 = true; 1347 oper_cw40 = true;
1429 1348
1430 oper_sgi40 = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1349 oper_sgi40 = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
@@ -1438,9 +1357,10 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1438 oper_cw40, oper_sgi40); 1357 oper_cw40, oper_sgi40);
1439 ath_rc_init(sc, priv_sta, sband, sta, rate_table); 1358 ath_rc_init(sc, priv_sta, sband, sta, rate_table);
1440 1359
1441 DPRINTF(sc, ATH_DBG_CONFIG, 1360 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1442 "Operating HT Bandwidth changed to: %d\n", 1361 "Operating HT Bandwidth changed to: %d\n",
1443 sc->hw->conf.channel_type); 1362 sc->hw->conf.channel_type);
1363 sc->cur_rate_table = hw_rate_table[sc->cur_rate_mode];
1444 } 1364 }
1445 } 1365 }
1446} 1366}
@@ -1463,8 +1383,8 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1463 1383
1464 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); 1384 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
1465 if (!rate_priv) { 1385 if (!rate_priv) {
1466 DPRINTF(sc, ATH_DBG_FATAL, 1386 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1467 "Unable to allocate private rc structure\n"); 1387 "Unable to allocate private rc structure\n");
1468 return NULL; 1388 return NULL;
1469 } 1389 }
1470 1390
@@ -1493,26 +1413,6 @@ static struct rate_control_ops ath_rate_ops = {
1493 .free_sta = ath_rate_free_sta, 1413 .free_sta = ath_rate_free_sta,
1494}; 1414};
1495 1415
1496void ath_rate_attach(struct ath_softc *sc)
1497{
1498 sc->hw_rate_table[ATH9K_MODE_11A] =
1499 &ar5416_11a_ratetable;
1500 sc->hw_rate_table[ATH9K_MODE_11G] =
1501 &ar5416_11g_ratetable;
1502 sc->hw_rate_table[ATH9K_MODE_11NA_HT20] =
1503 &ar5416_11na_ratetable;
1504 sc->hw_rate_table[ATH9K_MODE_11NG_HT20] =
1505 &ar5416_11ng_ratetable;
1506 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS] =
1507 &ar5416_11na_ratetable;
1508 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS] =
1509 &ar5416_11na_ratetable;
1510 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS] =
1511 &ar5416_11ng_ratetable;
1512 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS] =
1513 &ar5416_11ng_ratetable;
1514}
1515
1516int ath_rate_control_register(void) 1416int ath_rate_control_register(void)
1517{ 1417{
1518 return ieee80211_rate_control_register(&ath_rate_ops); 1418 return ieee80211_rate_control_register(&ath_rate_ops);
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index fa21a628ddd0..4f6d6fd442f4 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -19,6 +19,8 @@
19#ifndef RC_H 19#ifndef RC_H
20#define RC_H 20#define RC_H
21 21
22#include "hw.h"
23
22struct ath_softc; 24struct ath_softc;
23 25
24#define ATH_RATE_MAX 30 26#define ATH_RATE_MAX 30
@@ -55,6 +57,10 @@ enum {
55 || (_phy == WLAN_RC_PHY_HT_40_DS) \ 57 || (_phy == WLAN_RC_PHY_HT_40_DS) \
56 || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ 58 || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \
57 || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) 59 || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
60#define WLAN_RC_PHY_20(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS) \
61 || (_phy == WLAN_RC_PHY_HT_20_DS) \
62 || (_phy == WLAN_RC_PHY_HT_20_SS_HGI) \
63 || (_phy == WLAN_RC_PHY_HT_20_DS_HGI))
58#define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \ 64#define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \
59 || (_phy == WLAN_RC_PHY_HT_40_DS) \ 65 || (_phy == WLAN_RC_PHY_HT_40_DS) \
60 || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ 66 || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \
@@ -102,6 +108,7 @@ enum {
102 */ 108 */
103struct ath_rate_table { 109struct ath_rate_table {
104 int rate_cnt; 110 int rate_cnt;
111 int mcs_start;
105 struct { 112 struct {
106 int valid; 113 int valid;
107 int valid_single_stream; 114 int valid_single_stream;
@@ -109,14 +116,12 @@ struct ath_rate_table {
109 u32 ratekbps; 116 u32 ratekbps;
110 u32 user_ratekbps; 117 u32 user_ratekbps;
111 u8 ratecode; 118 u8 ratecode;
112 u8 short_preamble;
113 u8 dot11rate; 119 u8 dot11rate;
114 u8 ctrl_rate; 120 u8 ctrl_rate;
115 u8 base_index; 121 u8 base_index;
116 u8 cw40index; 122 u8 cw40index;
117 u8 sgi_index; 123 u8 sgi_index;
118 u8 ht_index; 124 u8 ht_index;
119 u32 max_4ms_framelen;
120 } info[RATE_TABLE_SIZE]; 125 } info[RATE_TABLE_SIZE];
121 u32 probe_interval; 126 u32 probe_interval;
122 u8 initial_ratemax; 127 u8 initial_ratemax;
@@ -165,26 +170,18 @@ struct ath_rate_priv {
165 struct ath_rate_softc *asc; 170 struct ath_rate_softc *asc;
166}; 171};
167 172
173#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
174#define ATH_TX_INFO_FRAME_TYPE_PAUSE (1 << 1)
175#define ATH_TX_INFO_UPDATE_RC (1 << 2)
176#define ATH_TX_INFO_XRETRY (1 << 3)
177#define ATH_TX_INFO_UNDERRUN (1 << 4)
178
168enum ath9k_internal_frame_type { 179enum ath9k_internal_frame_type {
169 ATH9K_NOT_INTERNAL, 180 ATH9K_NOT_INTERNAL,
170 ATH9K_INT_PAUSE, 181 ATH9K_INT_PAUSE,
171 ATH9K_INT_UNPAUSE 182 ATH9K_INT_UNPAUSE
172}; 183};
173 184
174struct ath_tx_info_priv {
175 struct ath_wiphy *aphy;
176 struct ath_tx_status tx;
177 int n_frames;
178 int n_bad_frames;
179 bool update_rc;
180 enum ath9k_internal_frame_type frame_type;
181};
182
183#define ATH_TX_INFO_PRIV(tx_info) \
184 ((struct ath_tx_info_priv *)((tx_info)->rate_driver_data[0]))
185
186void ath_rate_attach(struct ath_softc *sc);
187u8 ath_rate_findrateix(struct ath_softc *sc, u8 dot11_rate);
188int ath_rate_control_register(void); 185int ath_rate_control_register(void);
189void ath_rate_control_unregister(void); 186void ath_rate_control_unregister(void);
190 187
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index ec0abf823995..1ca42e5148c8 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -48,6 +48,7 @@ static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
48static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) 48static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
49{ 49{
50 struct ath_hw *ah = sc->sc_ah; 50 struct ath_hw *ah = sc->sc_ah;
51 struct ath_common *common = ath9k_hw_common(ah);
51 struct ath_desc *ds; 52 struct ath_desc *ds;
52 struct sk_buff *skb; 53 struct sk_buff *skb;
53 54
@@ -59,14 +60,16 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
59 60
60 /* virtual addr of the beginning of the buffer. */ 61 /* virtual addr of the beginning of the buffer. */
61 skb = bf->bf_mpdu; 62 skb = bf->bf_mpdu;
62 ASSERT(skb != NULL); 63 BUG_ON(skb == NULL);
63 ds->ds_vdata = skb->data; 64 ds->ds_vdata = skb->data;
64 65
65 /* setup rx descriptors. The rx.bufsize here tells the harware 66 /*
67 * setup rx descriptors. The rx_bufsize here tells the hardware
66 * how much data it can DMA to us and that we are prepared 68 * how much data it can DMA to us and that we are prepared
67 * to process */ 69 * to process
70 */
68 ath9k_hw_setuprxdesc(ah, ds, 71 ath9k_hw_setuprxdesc(ah, ds,
69 sc->rx.bufsize, 72 common->rx_bufsize,
70 0); 73 0);
71 74
72 if (sc->rx.rxlink == NULL) 75 if (sc->rx.rxlink == NULL)
@@ -86,192 +89,11 @@ static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
86 sc->rx.rxotherant = 0; 89 sc->rx.rxotherant = 0;
87} 90}
88 91
89/*
90 * Extend 15-bit time stamp from rx descriptor to
91 * a full 64-bit TSF using the current h/w TSF.
92*/
93static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
94{
95 u64 tsf;
96
97 tsf = ath9k_hw_gettsf64(sc->sc_ah);
98 if ((tsf & 0x7fff) < rstamp)
99 tsf -= 0x8000;
100 return (tsf & ~0x7fff) | rstamp;
101}
102
103/*
104 * For Decrypt or Demic errors, we only mark packet status here and always push
105 * up the frame up to let mac80211 handle the actual error case, be it no
106 * decryption key or real decryption error. This let us keep statistics there.
107 */
108static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
109 struct ieee80211_rx_status *rx_status, bool *decrypt_error,
110 struct ath_softc *sc)
111{
112 struct ieee80211_hdr *hdr;
113 u8 ratecode;
114 __le16 fc;
115 struct ieee80211_hw *hw;
116 struct ieee80211_sta *sta;
117 struct ath_node *an;
118 int last_rssi = ATH_RSSI_DUMMY_MARKER;
119
120
121 hdr = (struct ieee80211_hdr *)skb->data;
122 fc = hdr->frame_control;
123 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
124 hw = ath_get_virt_hw(sc, hdr);
125
126 if (ds->ds_rxstat.rs_more) {
127 /*
128 * Frame spans multiple descriptors; this cannot happen yet
129 * as we don't support jumbograms. If not in monitor mode,
130 * discard the frame. Enable this if you want to see
131 * error frames in Monitor mode.
132 */
133 if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR)
134 goto rx_next;
135 } else if (ds->ds_rxstat.rs_status != 0) {
136 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
137 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
138 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY)
139 goto rx_next;
140
141 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
142 *decrypt_error = true;
143 } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
144 if (ieee80211_is_ctl(fc))
145 /*
146 * Sometimes, we get invalid
147 * MIC failures on valid control frames.
148 * Remove these mic errors.
149 */
150 ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC;
151 else
152 rx_status->flag |= RX_FLAG_MMIC_ERROR;
153 }
154 /*
155 * Reject error frames with the exception of
156 * decryption and MIC failures. For monitor mode,
157 * we also ignore the CRC error.
158 */
159 if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) {
160 if (ds->ds_rxstat.rs_status &
161 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
162 ATH9K_RXERR_CRC))
163 goto rx_next;
164 } else {
165 if (ds->ds_rxstat.rs_status &
166 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
167 goto rx_next;
168 }
169 }
170 }
171
172 ratecode = ds->ds_rxstat.rs_rate;
173
174 if (ratecode & 0x80) {
175 /* HT rate */
176 rx_status->flag |= RX_FLAG_HT;
177 if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040)
178 rx_status->flag |= RX_FLAG_40MHZ;
179 if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
180 rx_status->flag |= RX_FLAG_SHORT_GI;
181 rx_status->rate_idx = ratecode & 0x7f;
182 } else {
183 int i = 0, cur_band, n_rates;
184
185 cur_band = hw->conf.channel->band;
186 n_rates = sc->sbands[cur_band].n_bitrates;
187
188 for (i = 0; i < n_rates; i++) {
189 if (sc->sbands[cur_band].bitrates[i].hw_value ==
190 ratecode) {
191 rx_status->rate_idx = i;
192 break;
193 }
194
195 if (sc->sbands[cur_band].bitrates[i].hw_value_short ==
196 ratecode) {
197 rx_status->rate_idx = i;
198 rx_status->flag |= RX_FLAG_SHORTPRE;
199 break;
200 }
201 }
202 }
203
204 rcu_read_lock();
205 sta = ieee80211_find_sta(sc->hw, hdr->addr2);
206 if (sta) {
207 an = (struct ath_node *) sta->drv_priv;
208 if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD &&
209 !ds->ds_rxstat.rs_moreaggr)
210 ATH_RSSI_LPF(an->last_rssi, ds->ds_rxstat.rs_rssi);
211 last_rssi = an->last_rssi;
212 }
213 rcu_read_unlock();
214
215 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
216 ds->ds_rxstat.rs_rssi = ATH_EP_RND(last_rssi,
217 ATH_RSSI_EP_MULTIPLIER);
218 if (ds->ds_rxstat.rs_rssi < 0)
219 ds->ds_rxstat.rs_rssi = 0;
220 else if (ds->ds_rxstat.rs_rssi > 127)
221 ds->ds_rxstat.rs_rssi = 127;
222
223 /* Update Beacon RSSI, this is used by ANI. */
224 if (ieee80211_is_beacon(fc))
225 sc->sc_ah->stats.avgbrssi = ds->ds_rxstat.rs_rssi;
226
227 rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
228 rx_status->band = hw->conf.channel->band;
229 rx_status->freq = hw->conf.channel->center_freq;
230 rx_status->noise = sc->ani.noise_floor;
231 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + ds->ds_rxstat.rs_rssi;
232 rx_status->antenna = ds->ds_rxstat.rs_antenna;
233
234 /*
235 * Theory for reporting quality:
236 *
237 * At a hardware RSSI of 45 you will be able to use MCS 7 reliably.
238 * At a hardware RSSI of 45 you will be able to use MCS 15 reliably.
239 * At a hardware RSSI of 35 you should be able use 54 Mbps reliably.
240 *
241 * MCS 7 is the highets MCS index usable by a 1-stream device.
242 * MCS 15 is the highest MCS index usable by a 2-stream device.
243 *
244 * All ath9k devices are either 1-stream or 2-stream.
245 *
246 * How many bars you see is derived from the qual reporting.
247 *
248 * A more elaborate scheme can be used here but it requires tables
249 * of SNR/throughput for each possible mode used. For the MCS table
250 * you can refer to the wireless wiki:
251 *
252 * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n
253 *
254 */
255 if (conf_is_ht(&hw->conf))
256 rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45;
257 else
258 rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 35;
259
260 /* rssi can be more than 45 though, anything above that
261 * should be considered at 100% */
262 if (rx_status->qual > 100)
263 rx_status->qual = 100;
264
265 rx_status->flag |= RX_FLAG_TSFT;
266
267 return 1;
268rx_next:
269 return 0;
270}
271
272static void ath_opmode_init(struct ath_softc *sc) 92static void ath_opmode_init(struct ath_softc *sc)
273{ 93{
274 struct ath_hw *ah = sc->sc_ah; 94 struct ath_hw *ah = sc->sc_ah;
95 struct ath_common *common = ath9k_hw_common(ah);
96
275 u32 rfilt, mfilt[2]; 97 u32 rfilt, mfilt[2];
276 98
277 /* configure rx filter */ 99 /* configure rx filter */
@@ -280,13 +102,13 @@ static void ath_opmode_init(struct ath_softc *sc)
280 102
281 /* configure bssid mask */ 103 /* configure bssid mask */
282 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 104 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
283 ath9k_hw_setbssidmask(sc); 105 ath_hw_setbssidmask(common);
284 106
285 /* configure operational mode */ 107 /* configure operational mode */
286 ath9k_hw_setopmode(ah); 108 ath9k_hw_setopmode(ah);
287 109
288 /* Handle any link-level address change. */ 110 /* Handle any link-level address change. */
289 ath9k_hw_setmac(ah, sc->sc_ah->macaddr); 111 ath9k_hw_setmac(ah, common->macaddr);
290 112
291 /* calculate and install multicast filter */ 113 /* calculate and install multicast filter */
292 mfilt[0] = mfilt[1] = ~0; 114 mfilt[0] = mfilt[1] = ~0;
@@ -295,6 +117,7 @@ static void ath_opmode_init(struct ath_softc *sc)
295 117
296int ath_rx_init(struct ath_softc *sc, int nbufs) 118int ath_rx_init(struct ath_softc *sc, int nbufs)
297{ 119{
120 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
298 struct sk_buff *skb; 121 struct sk_buff *skb;
299 struct ath_buf *bf; 122 struct ath_buf *bf;
300 int error = 0; 123 int error = 0;
@@ -303,24 +126,24 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
303 sc->sc_flags &= ~SC_OP_RXFLUSH; 126 sc->sc_flags &= ~SC_OP_RXFLUSH;
304 spin_lock_init(&sc->rx.rxbuflock); 127 spin_lock_init(&sc->rx.rxbuflock);
305 128
306 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 129 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
307 min(sc->common.cachelsz, (u16)64)); 130 min(common->cachelsz, (u16)64));
308 131
309 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 132 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
310 sc->common.cachelsz, sc->rx.bufsize); 133 common->cachelsz, common->rx_bufsize);
311 134
312 /* Initialize rx descriptors */ 135 /* Initialize rx descriptors */
313 136
314 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 137 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
315 "rx", nbufs, 1); 138 "rx", nbufs, 1);
316 if (error != 0) { 139 if (error != 0) {
317 DPRINTF(sc, ATH_DBG_FATAL, 140 ath_print(common, ATH_DBG_FATAL,
318 "failed to allocate rx descriptors: %d\n", error); 141 "failed to allocate rx descriptors: %d\n", error);
319 goto err; 142 goto err;
320 } 143 }
321 144
322 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 145 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
323 skb = ath_rxbuf_alloc(&sc->common, sc->rx.bufsize, GFP_KERNEL); 146 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
324 if (skb == NULL) { 147 if (skb == NULL) {
325 error = -ENOMEM; 148 error = -ENOMEM;
326 goto err; 149 goto err;
@@ -328,14 +151,14 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
328 151
329 bf->bf_mpdu = skb; 152 bf->bf_mpdu = skb;
330 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 153 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
331 sc->rx.bufsize, 154 common->rx_bufsize,
332 DMA_FROM_DEVICE); 155 DMA_FROM_DEVICE);
333 if (unlikely(dma_mapping_error(sc->dev, 156 if (unlikely(dma_mapping_error(sc->dev,
334 bf->bf_buf_addr))) { 157 bf->bf_buf_addr))) {
335 dev_kfree_skb_any(skb); 158 dev_kfree_skb_any(skb);
336 bf->bf_mpdu = NULL; 159 bf->bf_mpdu = NULL;
337 DPRINTF(sc, ATH_DBG_FATAL, 160 ath_print(common, ATH_DBG_FATAL,
338 "dma_mapping_error() on RX init\n"); 161 "dma_mapping_error() on RX init\n");
339 error = -ENOMEM; 162 error = -ENOMEM;
340 goto err; 163 goto err;
341 } 164 }
@@ -352,6 +175,8 @@ err:
352 175
353void ath_rx_cleanup(struct ath_softc *sc) 176void ath_rx_cleanup(struct ath_softc *sc)
354{ 177{
178 struct ath_hw *ah = sc->sc_ah;
179 struct ath_common *common = ath9k_hw_common(ah);
355 struct sk_buff *skb; 180 struct sk_buff *skb;
356 struct ath_buf *bf; 181 struct ath_buf *bf;
357 182
@@ -359,7 +184,7 @@ void ath_rx_cleanup(struct ath_softc *sc)
359 skb = bf->bf_mpdu; 184 skb = bf->bf_mpdu;
360 if (skb) { 185 if (skb) {
361 dma_unmap_single(sc->dev, bf->bf_buf_addr, 186 dma_unmap_single(sc->dev, bf->bf_buf_addr,
362 sc->rx.bufsize, DMA_FROM_DEVICE); 187 common->rx_bufsize, DMA_FROM_DEVICE);
363 dev_kfree_skb(skb); 188 dev_kfree_skb(skb);
364 } 189 }
365 } 190 }
@@ -420,7 +245,10 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
420 else 245 else
421 rfilt |= ATH9K_RX_FILTER_BEACON; 246 rfilt |= ATH9K_RX_FILTER_BEACON;
422 247
423 if (sc->rx.rxfilter & FIF_PSPOLL) 248 if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
249 AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
250 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
251 (sc->rx.rxfilter & FIF_PSPOLL))
424 rfilt |= ATH9K_RX_FILTER_PSPOLL; 252 rfilt |= ATH9K_RX_FILTER_PSPOLL;
425 253
426 if (conf_is_ht(&sc->hw->conf)) 254 if (conf_is_ht(&sc->hw->conf))
@@ -527,20 +355,22 @@ static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
527static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) 355static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
528{ 356{
529 struct ieee80211_mgmt *mgmt; 357 struct ieee80211_mgmt *mgmt;
358 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
530 359
531 if (skb->len < 24 + 8 + 2 + 2) 360 if (skb->len < 24 + 8 + 2 + 2)
532 return; 361 return;
533 362
534 mgmt = (struct ieee80211_mgmt *)skb->data; 363 mgmt = (struct ieee80211_mgmt *)skb->data;
535 if (memcmp(sc->curbssid, mgmt->bssid, ETH_ALEN) != 0) 364 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
536 return; /* not from our current AP */ 365 return; /* not from our current AP */
537 366
538 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; 367 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
539 368
540 if (sc->sc_flags & SC_OP_BEACON_SYNC) { 369 if (sc->ps_flags & PS_BEACON_SYNC) {
541 sc->sc_flags &= ~SC_OP_BEACON_SYNC; 370 sc->ps_flags &= ~PS_BEACON_SYNC;
542 DPRINTF(sc, ATH_DBG_PS, "Reconfigure Beacon timers based on " 371 ath_print(common, ATH_DBG_PS,
543 "timestamp from the AP\n"); 372 "Reconfigure Beacon timers based on "
373 "timestamp from the AP\n");
544 ath_beacon_config(sc, NULL); 374 ath_beacon_config(sc, NULL);
545 } 375 }
546 376
@@ -552,34 +382,36 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
552 * a backup trigger for returning into NETWORK SLEEP state, 382 * a backup trigger for returning into NETWORK SLEEP state,
553 * so we are waiting for it as well. 383 * so we are waiting for it as well.
554 */ 384 */
555 DPRINTF(sc, ATH_DBG_PS, "Received DTIM beacon indicating " 385 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
556 "buffered broadcast/multicast frame(s)\n"); 386 "buffered broadcast/multicast frame(s)\n");
557 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; 387 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
558 return; 388 return;
559 } 389 }
560 390
561 if (sc->sc_flags & SC_OP_WAIT_FOR_CAB) { 391 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
562 /* 392 /*
563 * This can happen if a broadcast frame is dropped or the AP 393 * This can happen if a broadcast frame is dropped or the AP
564 * fails to send a frame indicating that all CAB frames have 394 * fails to send a frame indicating that all CAB frames have
565 * been delivered. 395 * been delivered.
566 */ 396 */
567 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 397 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
568 DPRINTF(sc, ATH_DBG_PS, "PS wait for CAB frames timed out\n"); 398 ath_print(common, ATH_DBG_PS,
399 "PS wait for CAB frames timed out\n");
569 } 400 }
570} 401}
571 402
572static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) 403static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
573{ 404{
574 struct ieee80211_hdr *hdr; 405 struct ieee80211_hdr *hdr;
406 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
575 407
576 hdr = (struct ieee80211_hdr *)skb->data; 408 hdr = (struct ieee80211_hdr *)skb->data;
577 409
578 /* Process Beacon and CAB receive in PS state */ 410 /* Process Beacon and CAB receive in PS state */
579 if ((sc->sc_flags & SC_OP_WAIT_FOR_BEACON) && 411 if ((sc->ps_flags & PS_WAIT_FOR_BEACON) &&
580 ieee80211_is_beacon(hdr->frame_control)) 412 ieee80211_is_beacon(hdr->frame_control))
581 ath_rx_ps_beacon(sc, skb); 413 ath_rx_ps_beacon(sc, skb);
582 else if ((sc->sc_flags & SC_OP_WAIT_FOR_CAB) && 414 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
583 (ieee80211_is_data(hdr->frame_control) || 415 (ieee80211_is_data(hdr->frame_control) ||
584 ieee80211_is_action(hdr->frame_control)) && 416 ieee80211_is_action(hdr->frame_control)) &&
585 is_multicast_ether_addr(hdr->addr1) && 417 is_multicast_ether_addr(hdr->addr1) &&
@@ -588,24 +420,26 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
588 * No more broadcast/multicast frames to be received at this 420 * No more broadcast/multicast frames to be received at this
589 * point. 421 * point.
590 */ 422 */
591 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 423 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
592 DPRINTF(sc, ATH_DBG_PS, "All PS CAB frames received, back to " 424 ath_print(common, ATH_DBG_PS,
593 "sleep\n"); 425 "All PS CAB frames received, back to sleep\n");
594 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && 426 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
595 !is_multicast_ether_addr(hdr->addr1) && 427 !is_multicast_ether_addr(hdr->addr1) &&
596 !ieee80211_has_morefrags(hdr->frame_control)) { 428 !ieee80211_has_morefrags(hdr->frame_control)) {
597 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; 429 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
598 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 430 ath_print(common, ATH_DBG_PS,
599 "received PS-Poll data (0x%x)\n", 431 "Going back to sleep after having received "
600 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 432 "PS-Poll data (0x%lx)\n",
601 SC_OP_WAIT_FOR_CAB | 433 sc->ps_flags & (PS_WAIT_FOR_BEACON |
602 SC_OP_WAIT_FOR_PSPOLL_DATA | 434 PS_WAIT_FOR_CAB |
603 SC_OP_WAIT_FOR_TX_ACK)); 435 PS_WAIT_FOR_PSPOLL_DATA |
436 PS_WAIT_FOR_TX_ACK));
604 } 437 }
605} 438}
606 439
607static void ath_rx_send_to_mac80211(struct ath_softc *sc, struct sk_buff *skb, 440static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
608 struct ieee80211_rx_status *rx_status) 441 struct ath_softc *sc, struct sk_buff *skb,
442 struct ieee80211_rx_status *rxs)
609{ 443{
610 struct ieee80211_hdr *hdr; 444 struct ieee80211_hdr *hdr;
611 445
@@ -625,19 +459,14 @@ static void ath_rx_send_to_mac80211(struct ath_softc *sc, struct sk_buff *skb,
625 if (aphy == NULL) 459 if (aphy == NULL)
626 continue; 460 continue;
627 nskb = skb_copy(skb, GFP_ATOMIC); 461 nskb = skb_copy(skb, GFP_ATOMIC);
628 if (nskb) { 462 if (!nskb)
629 memcpy(IEEE80211_SKB_RXCB(nskb), rx_status, 463 continue;
630 sizeof(*rx_status)); 464 ieee80211_rx(aphy->hw, nskb);
631 ieee80211_rx(aphy->hw, nskb);
632 }
633 } 465 }
634 memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status));
635 ieee80211_rx(sc->hw, skb); 466 ieee80211_rx(sc->hw, skb);
636 } else { 467 } else
637 /* Deliver unicast frames based on receiver address */ 468 /* Deliver unicast frames based on receiver address */
638 memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); 469 ieee80211_rx(hw, skb);
639 ieee80211_rx(ath_get_virt_hw(sc, hdr), skb);
640 }
641} 470}
642 471
643int ath_rx_tasklet(struct ath_softc *sc, int flush) 472int ath_rx_tasklet(struct ath_softc *sc, int flush)
@@ -648,14 +477,20 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
648 477
649 struct ath_buf *bf; 478 struct ath_buf *bf;
650 struct ath_desc *ds; 479 struct ath_desc *ds;
480 struct ath_rx_status *rx_stats;
651 struct sk_buff *skb = NULL, *requeue_skb; 481 struct sk_buff *skb = NULL, *requeue_skb;
652 struct ieee80211_rx_status rx_status; 482 struct ieee80211_rx_status *rxs;
653 struct ath_hw *ah = sc->sc_ah; 483 struct ath_hw *ah = sc->sc_ah;
484 struct ath_common *common = ath9k_hw_common(ah);
485 /*
486 * The hw can techncically differ from common->hw when using ath9k
487 * virtual wiphy so to account for that we iterate over the active
488 * wiphys and find the appropriate wiphy and therefore hw.
489 */
490 struct ieee80211_hw *hw = NULL;
654 struct ieee80211_hdr *hdr; 491 struct ieee80211_hdr *hdr;
655 int hdrlen, padsize, retval; 492 int retval;
656 bool decrypt_error = false; 493 bool decrypt_error = false;
657 u8 keyix;
658 __le16 fc;
659 494
660 spin_lock_bh(&sc->rx.rxbuflock); 495 spin_lock_bh(&sc->rx.rxbuflock);
661 496
@@ -727,9 +562,17 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
727 * 2. requeueing the same buffer to h/w 562 * 2. requeueing the same buffer to h/w
728 */ 563 */
729 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 564 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
730 sc->rx.bufsize, 565 common->rx_bufsize,
731 DMA_FROM_DEVICE); 566 DMA_FROM_DEVICE);
732 567
568 hdr = (struct ieee80211_hdr *) skb->data;
569 rxs = IEEE80211_SKB_RXCB(skb);
570
571 hw = ath_get_virt_hw(sc, hdr);
572 rx_stats = &ds->ds_rxstat;
573
574 ath_debug_stat_rx(sc, bf);
575
733 /* 576 /*
734 * If we're asked to flush receive queue, directly 577 * If we're asked to flush receive queue, directly
735 * chain it back at the queue without processing it. 578 * chain it back at the queue without processing it.
@@ -737,19 +580,14 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
737 if (flush) 580 if (flush)
738 goto requeue; 581 goto requeue;
739 582
740 if (!ds->ds_rxstat.rs_datalen) 583 retval = ath9k_cmn_rx_skb_preprocess(common, hw, skb, rx_stats,
741 goto requeue; 584 rxs, &decrypt_error);
742 585 if (retval)
743 /* The status portion of the descriptor could get corrupted. */
744 if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen)
745 goto requeue;
746
747 if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc))
748 goto requeue; 586 goto requeue;
749 587
750 /* Ensure we always have an skb to requeue once we are done 588 /* Ensure we always have an skb to requeue once we are done
751 * processing the current buffer's skb */ 589 * processing the current buffer's skb */
752 requeue_skb = ath_rxbuf_alloc(&sc->common, sc->rx.bufsize, GFP_ATOMIC); 590 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
753 591
754 /* If there is no memory we ignore the current RX'd frame, 592 /* If there is no memory we ignore the current RX'd frame,
755 * tell hardware it can give us a new frame using the old 593 * tell hardware it can give us a new frame using the old
@@ -760,60 +598,26 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
760 598
761 /* Unmap the frame */ 599 /* Unmap the frame */
762 dma_unmap_single(sc->dev, bf->bf_buf_addr, 600 dma_unmap_single(sc->dev, bf->bf_buf_addr,
763 sc->rx.bufsize, 601 common->rx_bufsize,
764 DMA_FROM_DEVICE); 602 DMA_FROM_DEVICE);
765 603
766 skb_put(skb, ds->ds_rxstat.rs_datalen); 604 skb_put(skb, rx_stats->rs_datalen);
767
768 /* see if any padding is done by the hw and remove it */
769 hdr = (struct ieee80211_hdr *)skb->data;
770 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
771 fc = hdr->frame_control;
772
773 /* The MAC header is padded to have 32-bit boundary if the
774 * packet payload is non-zero. The general calculation for
775 * padsize would take into account odd header lengths:
776 * padsize = (4 - hdrlen % 4) % 4; However, since only
777 * even-length headers are used, padding can only be 0 or 2
778 * bytes and we can optimize this a bit. In addition, we must
779 * not try to remove padding from short control frames that do
780 * not have payload. */
781 padsize = hdrlen & 3;
782 if (padsize && hdrlen >= 24) {
783 memmove(skb->data + padsize, skb->data, hdrlen);
784 skb_pull(skb, padsize);
785 }
786
787 keyix = ds->ds_rxstat.rs_keyix;
788 605
789 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { 606 ath9k_cmn_rx_skb_postprocess(common, skb, rx_stats,
790 rx_status.flag |= RX_FLAG_DECRYPTED; 607 rxs, decrypt_error);
791 } else if (ieee80211_has_protected(fc)
792 && !decrypt_error && skb->len >= hdrlen + 4) {
793 keyix = skb->data[hdrlen + 3] >> 6;
794
795 if (test_bit(keyix, sc->keymap))
796 rx_status.flag |= RX_FLAG_DECRYPTED;
797 }
798 if (ah->sw_mgmt_crypto &&
799 (rx_status.flag & RX_FLAG_DECRYPTED) &&
800 ieee80211_is_mgmt(fc)) {
801 /* Use software decrypt for management frames. */
802 rx_status.flag &= ~RX_FLAG_DECRYPTED;
803 }
804 608
805 /* We will now give hardware our shiny new allocated skb */ 609 /* We will now give hardware our shiny new allocated skb */
806 bf->bf_mpdu = requeue_skb; 610 bf->bf_mpdu = requeue_skb;
807 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, 611 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
808 sc->rx.bufsize, 612 common->rx_bufsize,
809 DMA_FROM_DEVICE); 613 DMA_FROM_DEVICE);
810 if (unlikely(dma_mapping_error(sc->dev, 614 if (unlikely(dma_mapping_error(sc->dev,
811 bf->bf_buf_addr))) { 615 bf->bf_buf_addr))) {
812 dev_kfree_skb_any(requeue_skb); 616 dev_kfree_skb_any(requeue_skb);
813 bf->bf_mpdu = NULL; 617 bf->bf_mpdu = NULL;
814 DPRINTF(sc, ATH_DBG_FATAL, 618 ath_print(common, ATH_DBG_FATAL,
815 "dma_mapping_error() on RX\n"); 619 "dma_mapping_error() on RX\n");
816 ath_rx_send_to_mac80211(sc, skb, &rx_status); 620 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
817 break; 621 break;
818 } 622 }
819 bf->bf_dmacontext = bf->bf_buf_addr; 623 bf->bf_dmacontext = bf->bf_buf_addr;
@@ -824,17 +628,17 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
824 */ 628 */
825 if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { 629 if (sc->rx.defant != ds->ds_rxstat.rs_antenna) {
826 if (++sc->rx.rxotherant >= 3) 630 if (++sc->rx.rxotherant >= 3)
827 ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); 631 ath_setdefantenna(sc, rx_stats->rs_antenna);
828 } else { 632 } else {
829 sc->rx.rxotherant = 0; 633 sc->rx.rxotherant = 0;
830 } 634 }
831 635
832 if (unlikely(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 636 if (unlikely(sc->ps_flags & (PS_WAIT_FOR_BEACON |
833 SC_OP_WAIT_FOR_CAB | 637 PS_WAIT_FOR_CAB |
834 SC_OP_WAIT_FOR_PSPOLL_DATA))) 638 PS_WAIT_FOR_PSPOLL_DATA)))
835 ath_rx_ps(sc, skb); 639 ath_rx_ps(sc, skb);
836 640
837 ath_rx_send_to_mac80211(sc, skb, &rx_status); 641 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
838 642
839requeue: 643requeue:
840 list_move_tail(&bf->list, &sc->rx.rxbuf); 644 list_move_tail(&bf->list, &sc->rx.rxbuf);
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index d83b77f821e9..72cfa8ebd9ae 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -17,6 +17,8 @@
17#ifndef REG_H 17#ifndef REG_H
18#define REG_H 18#define REG_H
19 19
20#include "../reg.h"
21
20#define AR_CR 0x0008 22#define AR_CR 0x0008
21#define AR_CR_RXE 0x00000004 23#define AR_CR_RXE 0x00000004
22#define AR_CR_RXD 0x00000020 24#define AR_CR_RXD 0x00000020
@@ -969,10 +971,10 @@ enum {
969#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 971#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4
970#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 972#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080
971#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 973#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7
974#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400
975#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10
972#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 976#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000
973#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 977#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12
974#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00001000
975#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 1
976#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 978#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000
977#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 979#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15
978#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 980#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
@@ -1330,13 +1332,22 @@ enum {
1330#define AR_MCAST_FIL0 0x8040 1332#define AR_MCAST_FIL0 0x8040
1331#define AR_MCAST_FIL1 0x8044 1333#define AR_MCAST_FIL1 0x8044
1332 1334
1335/*
1336 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes.
1337 *
1338 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with
1339 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down
1340 * receive. The force RX abort bit will kill any frame which is currently being
1341 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS)
1342 * will prevent any new frames from getting started.
1343 */
1333#define AR_DIAG_SW 0x8048 1344#define AR_DIAG_SW 0x8048
1334#define AR_DIAG_CACHE_ACK 0x00000001 1345#define AR_DIAG_CACHE_ACK 0x00000001
1335#define AR_DIAG_ACK_DIS 0x00000002 1346#define AR_DIAG_ACK_DIS 0x00000002
1336#define AR_DIAG_CTS_DIS 0x00000004 1347#define AR_DIAG_CTS_DIS 0x00000004
1337#define AR_DIAG_ENCRYPT_DIS 0x00000008 1348#define AR_DIAG_ENCRYPT_DIS 0x00000008
1338#define AR_DIAG_DECRYPT_DIS 0x00000010 1349#define AR_DIAG_DECRYPT_DIS 0x00000010
1339#define AR_DIAG_RX_DIS 0x00000020 1350#define AR_DIAG_RX_DIS 0x00000020 /* RX block */
1340#define AR_DIAG_LOOP_BACK 0x00000040 1351#define AR_DIAG_LOOP_BACK 0x00000040
1341#define AR_DIAG_CORR_FCS 0x00000080 1352#define AR_DIAG_CORR_FCS 0x00000080
1342#define AR_DIAG_CHAN_INFO 0x00000100 1353#define AR_DIAG_CHAN_INFO 0x00000100
@@ -1345,12 +1356,12 @@ enum {
1345#define AR_DIAG_FRAME_NV0 0x00020000 1356#define AR_DIAG_FRAME_NV0 0x00020000
1346#define AR_DIAG_OBS_PT_SEL1 0x000C0000 1357#define AR_DIAG_OBS_PT_SEL1 0x000C0000
1347#define AR_DIAG_OBS_PT_SEL1_S 18 1358#define AR_DIAG_OBS_PT_SEL1_S 18
1348#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1359#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */
1349#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1360#define AR_DIAG_IGNORE_VIRT_CS 0x00200000
1350#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1361#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000
1351#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1362#define AR_DIAG_EIFS_CTRL_ENA 0x00800000
1352#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1363#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000
1353#define AR_DIAG_RX_ABORT 0x02000000 1364#define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */
1354#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1365#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000
1355#define AR_DIAG_OBS_PT_SEL2 0x08000000 1366#define AR_DIAG_OBS_PT_SEL2 0x08000000
1356#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1367#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000
@@ -1421,9 +1432,6 @@ enum {
1421#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1432#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000
1422#define AR_SLEEP2_BEACON_TIMEOUT_S 21 1433#define AR_SLEEP2_BEACON_TIMEOUT_S 21
1423 1434
1424#define AR_BSSMSKL 0x80e0
1425#define AR_BSSMSKU 0x80e4
1426
1427#define AR_TPC 0x80e8 1435#define AR_TPC 0x80e8
1428#define AR_TPC_ACK 0x0000003f 1436#define AR_TPC_ACK 0x0000003f
1429#define AR_TPC_ACK_S 0x00 1437#define AR_TPC_ACK_S 0x00
@@ -1539,9 +1547,9 @@ enum {
1539 1547
1540#define AR_BT_COEX_WEIGHT 0x8174 1548#define AR_BT_COEX_WEIGHT 0x8174
1541#define AR_BT_COEX_WGHT 0xff55 1549#define AR_BT_COEX_WGHT 0xff55
1542#define AR_STOMP_ALL_WLAN_WGHT 0xffcc 1550#define AR_STOMP_ALL_WLAN_WGHT 0xfcfc
1543#define AR_STOMP_LOW_WLAN_WGHT 0xaaa8 1551#define AR_STOMP_LOW_WLAN_WGHT 0xa8a8
1544#define AR_STOMP_NONE_WLAN_WGHT 0xaa00 1552#define AR_STOMP_NONE_WLAN_WGHT 0x0000
1545#define AR_BTCOEX_BT_WGHT 0x0000ffff 1553#define AR_BTCOEX_BT_WGHT 0x0000ffff
1546#define AR_BTCOEX_BT_WGHT_S 0 1554#define AR_BTCOEX_BT_WGHT_S 0
1547#define AR_BTCOEX_WL_WGHT 0xffff0000 1555#define AR_BTCOEX_WL_WGHT 0xffff0000
@@ -1705,4 +1713,7 @@ enum {
1705#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1713#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
1706#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1714#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
1707 1715
1716#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1717#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
1718
1708#endif 1719#endif
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
index 19b88f8177fd..00c0e21a4af7 100644
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ b/drivers/net/wireless/ath/ath9k/virtual.c
@@ -14,6 +14,8 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <linux/slab.h>
18
17#include "ath9k.h" 19#include "ath9k.h"
18 20
19struct ath9k_vif_iter_data { 21struct ath9k_vif_iter_data {
@@ -40,6 +42,7 @@ void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
40{ 42{
41 struct ath_wiphy *aphy = hw->priv; 43 struct ath_wiphy *aphy = hw->priv;
42 struct ath_softc *sc = aphy->sc; 44 struct ath_softc *sc = aphy->sc;
45 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
43 struct ath9k_vif_iter_data iter_data; 46 struct ath9k_vif_iter_data iter_data;
44 int i, j; 47 int i, j;
45 u8 mask[ETH_ALEN]; 48 u8 mask[ETH_ALEN];
@@ -51,7 +54,7 @@ void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
51 */ 54 */
52 iter_data.addr = kmalloc(ETH_ALEN, GFP_ATOMIC); 55 iter_data.addr = kmalloc(ETH_ALEN, GFP_ATOMIC);
53 if (iter_data.addr) { 56 if (iter_data.addr) {
54 memcpy(iter_data.addr, sc->sc_ah->macaddr, ETH_ALEN); 57 memcpy(iter_data.addr, common->macaddr, ETH_ALEN);
55 iter_data.count = 1; 58 iter_data.count = 1;
56 } else 59 } else
57 iter_data.count = 0; 60 iter_data.count = 0;
@@ -86,20 +89,21 @@ void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
86 kfree(iter_data.addr); 89 kfree(iter_data.addr);
87 90
88 /* Invert the mask and configure hardware */ 91 /* Invert the mask and configure hardware */
89 sc->bssidmask[0] = ~mask[0]; 92 common->bssidmask[0] = ~mask[0];
90 sc->bssidmask[1] = ~mask[1]; 93 common->bssidmask[1] = ~mask[1];
91 sc->bssidmask[2] = ~mask[2]; 94 common->bssidmask[2] = ~mask[2];
92 sc->bssidmask[3] = ~mask[3]; 95 common->bssidmask[3] = ~mask[3];
93 sc->bssidmask[4] = ~mask[4]; 96 common->bssidmask[4] = ~mask[4];
94 sc->bssidmask[5] = ~mask[5]; 97 common->bssidmask[5] = ~mask[5];
95 98
96 ath9k_hw_setbssidmask(sc); 99 ath_hw_setbssidmask(common);
97} 100}
98 101
99int ath9k_wiphy_add(struct ath_softc *sc) 102int ath9k_wiphy_add(struct ath_softc *sc)
100{ 103{
101 int i, error; 104 int i, error;
102 struct ath_wiphy *aphy; 105 struct ath_wiphy *aphy;
106 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 struct ieee80211_hw *hw; 107 struct ieee80211_hw *hw;
104 u8 addr[ETH_ALEN]; 108 u8 addr[ETH_ALEN];
105 109
@@ -138,7 +142,7 @@ int ath9k_wiphy_add(struct ath_softc *sc)
138 sc->sec_wiphy[i] = aphy; 142 sc->sec_wiphy[i] = aphy;
139 spin_unlock_bh(&sc->wiphy_lock); 143 spin_unlock_bh(&sc->wiphy_lock);
140 144
141 memcpy(addr, sc->sc_ah->macaddr, ETH_ALEN); 145 memcpy(addr, common->macaddr, ETH_ALEN);
142 addr[0] |= 0x02; /* Locally managed address */ 146 addr[0] |= 0x02; /* Locally managed address */
143 /* 147 /*
144 * XOR virtual wiphy index into the least significant bits to generate 148 * XOR virtual wiphy index into the least significant bits to generate
@@ -150,7 +154,7 @@ int ath9k_wiphy_add(struct ath_softc *sc)
150 154
151 SET_IEEE80211_PERM_ADDR(hw, addr); 155 SET_IEEE80211_PERM_ADDR(hw, addr);
152 156
153 ath_set_hw_capab(sc, hw); 157 ath9k_set_hw_capab(sc, hw);
154 158
155 error = ieee80211_register_hw(hw); 159 error = ieee80211_register_hw(hw);
156 160
@@ -296,6 +300,7 @@ static void ath9k_wiphy_unpause_channel(struct ath_softc *sc)
296void ath9k_wiphy_chan_work(struct work_struct *work) 300void ath9k_wiphy_chan_work(struct work_struct *work)
297{ 301{
298 struct ath_softc *sc = container_of(work, struct ath_softc, chan_work); 302 struct ath_softc *sc = container_of(work, struct ath_softc, chan_work);
303 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
299 struct ath_wiphy *aphy = sc->next_wiphy; 304 struct ath_wiphy *aphy = sc->next_wiphy;
300 305
301 if (aphy == NULL) 306 if (aphy == NULL)
@@ -311,6 +316,10 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
311 /* XXX: remove me eventually */ 316 /* XXX: remove me eventually */
312 ath9k_update_ichannel(sc, aphy->hw, 317 ath9k_update_ichannel(sc, aphy->hw,
313 &sc->sc_ah->channels[sc->chan_idx]); 318 &sc->sc_ah->channels[sc->chan_idx]);
319
320 /* sync hw configuration for hw code */
321 common->hw = aphy->hw;
322
314 ath_update_chainmask(sc, sc->chan_is_ht); 323 ath_update_chainmask(sc, sc->chan_is_ht);
315 if (ath_set_channel(sc, aphy->hw, 324 if (ath_set_channel(sc, aphy->hw,
316 &sc->sc_ah->channels[sc->chan_idx]) < 0) { 325 &sc->sc_ah->channels[sc->chan_idx]) < 0) {
@@ -331,13 +340,11 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
331void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 340void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
332{ 341{
333 struct ath_wiphy *aphy = hw->priv; 342 struct ath_wiphy *aphy = hw->priv;
334 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
335 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
336 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
337 344
338 if (tx_info_priv && tx_info_priv->frame_type == ATH9K_INT_PAUSE && 345 if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
339 aphy->state == ATH_WIPHY_PAUSING) { 346 aphy->state == ATH_WIPHY_PAUSING) {
340 if (!(info->flags & IEEE80211_TX_STAT_ACK)) { 347 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
341 printk(KERN_DEBUG "ath9k: %s: no ACK for pause " 348 printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
342 "frame\n", wiphy_name(hw->wiphy)); 349 "frame\n", wiphy_name(hw->wiphy));
343 /* 350 /*
@@ -356,9 +363,6 @@ void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
356 } 363 }
357 } 364 }
358 365
359 kfree(tx_info_priv);
360 tx_info->rate_driver_data[0] = NULL;
361
362 dev_kfree_skb(skb); 366 dev_kfree_skb(skb);
363} 367}
364 368
@@ -519,8 +523,9 @@ int ath9k_wiphy_select(struct ath_wiphy *aphy)
519 * frame being completed) 523 * frame being completed)
520 */ 524 */
521 spin_unlock_bh(&sc->wiphy_lock); 525 spin_unlock_bh(&sc->wiphy_lock);
522 ath_radio_disable(sc); 526 ath_radio_disable(sc, aphy->hw);
523 ath_radio_enable(sc); 527 ath_radio_enable(sc, aphy->hw);
528 /* Only the primary wiphy hw is used for queuing work */
524 ieee80211_queue_work(aphy->sc->hw, 529 ieee80211_queue_work(aphy->sc->hw,
525 &aphy->sc->chan_work); 530 &aphy->sc->chan_work);
526 return -EBUSY; /* previous select still in progress */ 531 return -EBUSY; /* previous select still in progress */
@@ -666,15 +671,78 @@ void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int)
666bool ath9k_all_wiphys_idle(struct ath_softc *sc) 671bool ath9k_all_wiphys_idle(struct ath_softc *sc)
667{ 672{
668 unsigned int i; 673 unsigned int i;
669 if (sc->pri_wiphy->state != ATH_WIPHY_INACTIVE) { 674 if (!sc->pri_wiphy->idle)
670 return false; 675 return false;
671 }
672 for (i = 0; i < sc->num_sec_wiphy; i++) { 676 for (i = 0; i < sc->num_sec_wiphy; i++) {
673 struct ath_wiphy *aphy = sc->sec_wiphy[i]; 677 struct ath_wiphy *aphy = sc->sec_wiphy[i];
674 if (!aphy) 678 if (!aphy)
675 continue; 679 continue;
676 if (aphy->state != ATH_WIPHY_INACTIVE) 680 if (!aphy->idle)
677 return false; 681 return false;
678 } 682 }
679 return true; 683 return true;
680} 684}
685
686/* caller must hold wiphy_lock */
687void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle)
688{
689 struct ath_softc *sc = aphy->sc;
690
691 aphy->idle = idle;
692 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
693 "Marking %s as %s\n",
694 wiphy_name(aphy->hw->wiphy),
695 idle ? "idle" : "not-idle");
696}
697/* Only bother starting a queue on an active virtual wiphy */
698void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue)
699{
700 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
701 unsigned int i;
702
703 spin_lock_bh(&sc->wiphy_lock);
704
705 /* Start the primary wiphy */
706 if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE) {
707 ieee80211_wake_queue(hw, skb_queue);
708 goto unlock;
709 }
710
711 /* Now start the secondary wiphy queues */
712 for (i = 0; i < sc->num_sec_wiphy; i++) {
713 struct ath_wiphy *aphy = sc->sec_wiphy[i];
714 if (!aphy)
715 continue;
716 if (aphy->state != ATH_WIPHY_ACTIVE)
717 continue;
718
719 hw = aphy->hw;
720 ieee80211_wake_queue(hw, skb_queue);
721 break;
722 }
723
724unlock:
725 spin_unlock_bh(&sc->wiphy_lock);
726}
727
728/* Go ahead and propagate information to all virtual wiphys, it won't hurt */
729void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue)
730{
731 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
732 unsigned int i;
733
734 spin_lock_bh(&sc->wiphy_lock);
735
736 /* Stop the primary wiphy */
737 ieee80211_stop_queue(hw, skb_queue);
738
739 /* Now stop the secondary wiphy queues */
740 for (i = 0; i < sc->num_sec_wiphy; i++) {
741 struct ath_wiphy *aphy = sc->sec_wiphy[i];
742 if (!aphy)
743 continue;
744 hw = aphy->hw;
745 ieee80211_stop_queue(hw, skb_queue);
746 }
747 spin_unlock_bh(&sc->wiphy_lock);
748}
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 42551a48c8ac..294b486bc3ed 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -70,6 +70,29 @@ static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
70static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, 70static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
71 int nbad, int txok, bool update_rc); 71 int nbad, int txok, bool update_rc);
72 72
73enum {
74 MCS_DEFAULT,
75 MCS_HT40,
76 MCS_HT40_SGI,
77};
78
79static int ath_max_4ms_framelen[3][16] = {
80 [MCS_DEFAULT] = {
81 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180,
82 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320,
83 },
84 [MCS_HT40] = {
85 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840,
86 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600,
87 },
88 [MCS_HT40_SGI] = {
89 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */
90 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200,
91 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400,
92 }
93};
94
95
73/*********************/ 96/*********************/
74/* Aggregation logic */ 97/* Aggregation logic */
75/*********************/ 98/*********************/
@@ -107,7 +130,7 @@ static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
107{ 130{
108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 131 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
109 132
110 ASSERT(tid->paused > 0); 133 BUG_ON(tid->paused <= 0);
111 spin_lock_bh(&txq->axq_lock); 134 spin_lock_bh(&txq->axq_lock);
112 135
113 tid->paused--; 136 tid->paused--;
@@ -131,7 +154,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
131 struct list_head bf_head; 154 struct list_head bf_head;
132 INIT_LIST_HEAD(&bf_head); 155 INIT_LIST_HEAD(&bf_head);
133 156
134 ASSERT(tid->paused > 0); 157 BUG_ON(tid->paused <= 0);
135 spin_lock_bh(&txq->axq_lock); 158 spin_lock_bh(&txq->axq_lock);
136 159
137 tid->paused--; 160 tid->paused--;
@@ -143,7 +166,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
143 166
144 while (!list_empty(&tid->buf_q)) { 167 while (!list_empty(&tid->buf_q)) {
145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 168 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
146 ASSERT(!bf_isretried(bf)); 169 BUG_ON(bf_isretried(bf));
147 list_move_tail(&bf->list, &bf_head); 170 list_move_tail(&bf->list, &bf_head);
148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head); 171 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
149 } 172 }
@@ -178,7 +201,7 @@ static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); 201 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
180 203
181 ASSERT(tid->tx_buf[cindex] == NULL); 204 BUG_ON(tid->tx_buf[cindex] != NULL);
182 tid->tx_buf[cindex] = bf; 205 tid->tx_buf[cindex] = bf;
183 206
184 if (index >= ((tid->baw_tail - tid->baw_head) & 207 if (index >= ((tid->baw_tail - tid->baw_head) &
@@ -251,6 +274,7 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
251 274
252 ATH_TXBUF_RESET(tbf); 275 ATH_TXBUF_RESET(tbf);
253 276
277 tbf->aphy = bf->aphy;
254 tbf->bf_mpdu = bf->bf_mpdu; 278 tbf->bf_mpdu = bf->bf_mpdu;
255 tbf->bf_buf_addr = bf->bf_buf_addr; 279 tbf->bf_buf_addr = bf->bf_buf_addr;
256 *(tbf->bf_desc) = *(bf->bf_desc); 280 *(tbf->bf_desc) = *(bf->bf_desc);
@@ -267,7 +291,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
267 struct ath_node *an = NULL; 291 struct ath_node *an = NULL;
268 struct sk_buff *skb; 292 struct sk_buff *skb;
269 struct ieee80211_sta *sta; 293 struct ieee80211_sta *sta;
294 struct ieee80211_hw *hw;
270 struct ieee80211_hdr *hdr; 295 struct ieee80211_hdr *hdr;
296 struct ieee80211_tx_info *tx_info;
271 struct ath_atx_tid *tid = NULL; 297 struct ath_atx_tid *tid = NULL;
272 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 298 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
273 struct ath_desc *ds = bf_last->bf_desc; 299 struct ath_desc *ds = bf_last->bf_desc;
@@ -280,9 +306,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
280 skb = bf->bf_mpdu; 306 skb = bf->bf_mpdu;
281 hdr = (struct ieee80211_hdr *)skb->data; 307 hdr = (struct ieee80211_hdr *)skb->data;
282 308
309 tx_info = IEEE80211_SKB_CB(skb);
310 hw = bf->aphy->hw;
311
283 rcu_read_lock(); 312 rcu_read_lock();
284 313
285 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 314 /* XXX: use ieee80211_find_sta! */
315 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
286 if (!sta) { 316 if (!sta) {
287 rcu_read_unlock(); 317 rcu_read_unlock();
288 return; 318 return;
@@ -358,7 +388,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
358 else 388 else
359 INIT_LIST_HEAD(&bf_head); 389 INIT_LIST_HEAD(&bf_head);
360 } else { 390 } else {
361 ASSERT(!list_empty(bf_q)); 391 BUG_ON(list_empty(bf_q));
362 list_move_tail(&bf->list, &bf_head); 392 list_move_tail(&bf->list, &bf_head);
363 } 393 }
364 394
@@ -452,11 +482,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
452static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 482static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
453 struct ath_atx_tid *tid) 483 struct ath_atx_tid *tid)
454{ 484{
455 const struct ath_rate_table *rate_table = sc->cur_rate_table;
456 struct sk_buff *skb; 485 struct sk_buff *skb;
457 struct ieee80211_tx_info *tx_info; 486 struct ieee80211_tx_info *tx_info;
458 struct ieee80211_tx_rate *rates; 487 struct ieee80211_tx_rate *rates;
459 struct ath_tx_info_priv *tx_info_priv;
460 u32 max_4ms_framelen, frmlen; 488 u32 max_4ms_framelen, frmlen;
461 u16 aggr_limit, legacy = 0; 489 u16 aggr_limit, legacy = 0;
462 int i; 490 int i;
@@ -464,7 +492,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
464 skb = bf->bf_mpdu; 492 skb = bf->bf_mpdu;
465 tx_info = IEEE80211_SKB_CB(skb); 493 tx_info = IEEE80211_SKB_CB(skb);
466 rates = tx_info->control.rates; 494 rates = tx_info->control.rates;
467 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
468 495
469 /* 496 /*
470 * Find the lowest frame length among the rate series that will have a 497 * Find the lowest frame length among the rate series that will have a
@@ -475,12 +502,20 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
475 502
476 for (i = 0; i < 4; i++) { 503 for (i = 0; i < 4; i++) {
477 if (rates[i].count) { 504 if (rates[i].count) {
478 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { 505 int modeidx;
506 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
479 legacy = 1; 507 legacy = 1;
480 break; 508 break;
481 } 509 }
482 510
483 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; 511 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
512 modeidx = MCS_HT40_SGI;
513 else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
514 modeidx = MCS_HT40;
515 else
516 modeidx = MCS_DEFAULT;
517
518 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
484 max_4ms_framelen = min(max_4ms_framelen, frmlen); 519 max_4ms_framelen = min(max_4ms_framelen, frmlen);
485 } 520 }
486 } 521 }
@@ -518,12 +553,11 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
518static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 553static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
519 struct ath_buf *bf, u16 frmlen) 554 struct ath_buf *bf, u16 frmlen)
520{ 555{
521 const struct ath_rate_table *rt = sc->cur_rate_table;
522 struct sk_buff *skb = bf->bf_mpdu; 556 struct sk_buff *skb = bf->bf_mpdu;
523 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 557 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
524 u32 nsymbits, nsymbols; 558 u32 nsymbits, nsymbols;
525 u16 minlen; 559 u16 minlen;
526 u8 rc, flags, rix; 560 u8 flags, rix;
527 int width, half_gi, ndelim, mindelim; 561 int width, half_gi, ndelim, mindelim;
528 562
529 /* Select standard number of delimiters based on frame length alone */ 563 /* Select standard number of delimiters based on frame length alone */
@@ -553,7 +587,6 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
553 587
554 rix = tx_info->control.rates[0].idx; 588 rix = tx_info->control.rates[0].idx;
555 flags = tx_info->control.rates[0].flags; 589 flags = tx_info->control.rates[0].flags;
556 rc = rt->info[rix].ratecode;
557 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 590 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
558 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 591 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
559 592
@@ -565,7 +598,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
565 if (nsymbols == 0) 598 if (nsymbols == 0)
566 nsymbols = 1; 599 nsymbols = 1;
567 600
568 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 601 nsymbits = bits_per_symbol[rix][width];
569 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 602 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
570 603
571 if (frmlen < minlen) { 604 if (frmlen < minlen) {
@@ -694,7 +727,6 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
694 /* anchor last desc of aggregate */ 727 /* anchor last desc of aggregate */
695 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 728 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
696 729
697 txq->axq_aggr_depth++;
698 ath_tx_txqaddbuf(sc, txq, &bf_q); 730 ath_tx_txqaddbuf(sc, txq, &bf_q);
699 TX_STAT_INC(txq->axq_qnum, a_aggr); 731 TX_STAT_INC(txq->axq_qnum, a_aggr);
700 732
@@ -815,6 +847,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
815struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 847struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
816{ 848{
817 struct ath_hw *ah = sc->sc_ah; 849 struct ath_hw *ah = sc->sc_ah;
850 struct ath_common *common = ath9k_hw_common(ah);
818 struct ath9k_tx_queue_info qi; 851 struct ath9k_tx_queue_info qi;
819 int qnum; 852 int qnum;
820 853
@@ -854,9 +887,9 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
854 return NULL; 887 return NULL;
855 } 888 }
856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 889 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
857 DPRINTF(sc, ATH_DBG_FATAL, 890 ath_print(common, ATH_DBG_FATAL,
858 "qnum %u out of range, max %u!\n", 891 "qnum %u out of range, max %u!\n",
859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 892 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
860 ath9k_hw_releasetxqueue(ah, qnum); 893 ath9k_hw_releasetxqueue(ah, qnum);
861 return NULL; 894 return NULL;
862 } 895 }
@@ -869,8 +902,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
869 INIT_LIST_HEAD(&txq->axq_acq); 902 INIT_LIST_HEAD(&txq->axq_acq);
870 spin_lock_init(&txq->axq_lock); 903 spin_lock_init(&txq->axq_lock);
871 txq->axq_depth = 0; 904 txq->axq_depth = 0;
872 txq->axq_aggr_depth = 0;
873 txq->axq_linkbuf = NULL;
874 txq->axq_tx_inprogress = false; 905 txq->axq_tx_inprogress = false;
875 sc->tx.txqsetup |= 1<<qnum; 906 sc->tx.txqsetup |= 1<<qnum;
876 } 907 }
@@ -884,9 +915,9 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
884 switch (qtype) { 915 switch (qtype) {
885 case ATH9K_TX_QUEUE_DATA: 916 case ATH9K_TX_QUEUE_DATA:
886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 917 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
887 DPRINTF(sc, ATH_DBG_FATAL, 918 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
888 "HAL AC %u out of range, max %zu!\n", 919 "HAL AC %u out of range, max %zu!\n",
889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 920 haltype, ARRAY_SIZE(sc->tx.hwq_map));
890 return -1; 921 return -1;
891 } 922 }
892 qnum = sc->tx.hwq_map[haltype]; 923 qnum = sc->tx.hwq_map[haltype];
@@ -906,18 +937,19 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
906struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) 937struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
907{ 938{
908 struct ath_txq *txq = NULL; 939 struct ath_txq *txq = NULL;
940 u16 skb_queue = skb_get_queue_mapping(skb);
909 int qnum; 941 int qnum;
910 942
911 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 943 qnum = ath_get_hal_qnum(skb_queue, sc);
912 txq = &sc->tx.txq[qnum]; 944 txq = &sc->tx.txq[qnum];
913 945
914 spin_lock_bh(&txq->axq_lock); 946 spin_lock_bh(&txq->axq_lock);
915 947
916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 948 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
917 DPRINTF(sc, ATH_DBG_XMIT, 949 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
918 "TX queue: %d is full, depth: %d\n", 950 "TX queue: %d is full, depth: %d\n",
919 qnum, txq->axq_depth); 951 qnum, txq->axq_depth);
920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 952 ath_mac80211_stop_queue(sc, skb_queue);
921 txq->stopped = 1; 953 txq->stopped = 1;
922 spin_unlock_bh(&txq->axq_lock); 954 spin_unlock_bh(&txq->axq_lock);
923 return NULL; 955 return NULL;
@@ -945,7 +977,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
945 return 0; 977 return 0;
946 } 978 }
947 979
948 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); 980 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
949 981
950 ath9k_hw_get_txq_props(ah, qnum, &qi); 982 ath9k_hw_get_txq_props(ah, qnum, &qi);
951 qi.tqi_aifs = qinfo->tqi_aifs; 983 qi.tqi_aifs = qinfo->tqi_aifs;
@@ -955,8 +987,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
955 qi.tqi_readyTime = qinfo->tqi_readyTime; 987 qi.tqi_readyTime = qinfo->tqi_readyTime;
956 988
957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 989 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
958 DPRINTF(sc, ATH_DBG_FATAL, 990 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
959 "Unable to update hardware queue %u!\n", qnum); 991 "Unable to update hardware queue %u!\n", qnum);
960 error = -EIO; 992 error = -EIO;
961 } else { 993 } else {
962 ath9k_hw_resettxqueue(ah, qnum); 994 ath9k_hw_resettxqueue(ah, qnum);
@@ -1004,7 +1036,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1004 1036
1005 if (list_empty(&txq->axq_q)) { 1037 if (list_empty(&txq->axq_q)) {
1006 txq->axq_link = NULL; 1038 txq->axq_link = NULL;
1007 txq->axq_linkbuf = NULL;
1008 spin_unlock_bh(&txq->axq_lock); 1039 spin_unlock_bh(&txq->axq_lock);
1009 break; 1040 break;
1010 } 1041 }
@@ -1055,6 +1086,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1055void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1086void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1056{ 1087{
1057 struct ath_hw *ah = sc->sc_ah; 1088 struct ath_hw *ah = sc->sc_ah;
1089 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1058 struct ath_txq *txq; 1090 struct ath_txq *txq;
1059 int i, npend = 0; 1091 int i, npend = 0;
1060 1092
@@ -1076,14 +1108,15 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1076 if (npend) { 1108 if (npend) {
1077 int r; 1109 int r;
1078 1110
1079 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1111 ath_print(common, ATH_DBG_FATAL,
1112 "Unable to stop TxDMA. Reset HAL!\n");
1080 1113
1081 spin_lock_bh(&sc->sc_resetlock); 1114 spin_lock_bh(&sc->sc_resetlock);
1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1115 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1083 if (r) 1116 if (r)
1084 DPRINTF(sc, ATH_DBG_FATAL, 1117 ath_print(common, ATH_DBG_FATAL,
1085 "Unable to reset hardware; reset status %d\n", 1118 "Unable to reset hardware; reset status %d\n",
1086 r); 1119 r);
1087 spin_unlock_bh(&sc->sc_resetlock); 1120 spin_unlock_bh(&sc->sc_resetlock);
1088 } 1121 }
1089 1122
@@ -1147,8 +1180,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1147 struct ath_txq *txq; 1180 struct ath_txq *txq;
1148 1181
1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1182 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1150 DPRINTF(sc, ATH_DBG_FATAL, 1183 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1151 "HAL AC %u out of range, max %zu!\n", 1184 "HAL AC %u out of range, max %zu!\n",
1152 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1185 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1153 return 0; 1186 return 0;
1154 } 1187 }
@@ -1172,6 +1205,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1172 struct list_head *head) 1205 struct list_head *head)
1173{ 1206{
1174 struct ath_hw *ah = sc->sc_ah; 1207 struct ath_hw *ah = sc->sc_ah;
1208 struct ath_common *common = ath9k_hw_common(ah);
1175 struct ath_buf *bf; 1209 struct ath_buf *bf;
1176 1210
1177 /* 1211 /*
@@ -1186,21 +1220,20 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1186 1220
1187 list_splice_tail_init(head, &txq->axq_q); 1221 list_splice_tail_init(head, &txq->axq_q);
1188 txq->axq_depth++; 1222 txq->axq_depth++;
1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1190 1223
1191 DPRINTF(sc, ATH_DBG_QUEUE, 1224 ath_print(common, ATH_DBG_QUEUE,
1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1225 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1193 1226
1194 if (txq->axq_link == NULL) { 1227 if (txq->axq_link == NULL) {
1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1228 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1196 DPRINTF(sc, ATH_DBG_XMIT, 1229 ath_print(common, ATH_DBG_XMIT,
1197 "TXDP[%u] = %llx (%p)\n", 1230 "TXDP[%u] = %llx (%p)\n",
1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1231 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1199 } else { 1232 } else {
1200 *txq->axq_link = bf->bf_daddr; 1233 *txq->axq_link = bf->bf_daddr;
1201 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1234 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1202 txq->axq_qnum, txq->axq_link, 1235 txq->axq_qnum, txq->axq_link,
1203 ito64(bf->bf_daddr), bf->bf_desc); 1236 ito64(bf->bf_daddr), bf->bf_desc);
1204 } 1237 }
1205 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); 1238 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1206 ath9k_hw_txstart(ah, txq->axq_qnum); 1239 ath9k_hw_txstart(ah, txq->axq_qnum);
@@ -1320,25 +1353,6 @@ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1320 return htype; 1353 return htype;
1321} 1354}
1322 1355
1323static bool is_pae(struct sk_buff *skb)
1324{
1325 struct ieee80211_hdr *hdr;
1326 __le16 fc;
1327
1328 hdr = (struct ieee80211_hdr *)skb->data;
1329 fc = hdr->frame_control;
1330
1331 if (ieee80211_is_data(fc)) {
1332 if (ieee80211_is_nullfunc(fc) ||
1333 /* Port Access Entity (IEEE 802.1X) */
1334 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1335 return true;
1336 }
1337 }
1338
1339 return false;
1340}
1341
1342static int get_hw_crypto_keytype(struct sk_buff *skb) 1356static int get_hw_crypto_keytype(struct sk_buff *skb)
1343{ 1357{
1344 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1358 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -1381,17 +1395,9 @@ static void assign_aggr_tid_seqno(struct sk_buff *skb,
1381 * For HT capable stations, we save tidno for later use. 1395 * For HT capable stations, we save tidno for later use.
1382 * We also override seqno set by upper layer with the one 1396 * We also override seqno set by upper layer with the one
1383 * in tx aggregation state. 1397 * in tx aggregation state.
1384 *
1385 * If fragmentation is on, the sequence number is
1386 * not overridden, since it has been
1387 * incremented by the fragmentation routine.
1388 *
1389 * FIXME: check if the fragmentation threshold exceeds
1390 * IEEE80211 max.
1391 */ 1398 */
1392 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1399 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1393 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << 1400 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1394 IEEE80211_SEQ_SEQ_SHIFT);
1395 bf->bf_seqno = tid->seq_next; 1401 bf->bf_seqno = tid->seq_next;
1396 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1402 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1397} 1403}
@@ -1420,22 +1426,14 @@ static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1420static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, 1426static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1421 int width, int half_gi, bool shortPreamble) 1427 int width, int half_gi, bool shortPreamble)
1422{ 1428{
1423 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1424 u32 nbits, nsymbits, duration, nsymbols; 1429 u32 nbits, nsymbits, duration, nsymbols;
1425 u8 rc;
1426 int streams, pktlen; 1430 int streams, pktlen;
1427 1431
1428 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; 1432 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1429 rc = rate_table->info[rix].ratecode;
1430
1431 /* for legacy rates, use old function to compute packet duration */
1432 if (!IS_HT_RATE(rc))
1433 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1434 rix, shortPreamble);
1435 1433
1436 /* find number of symbols: PLCP + data */ 1434 /* find number of symbols: PLCP + data */
1437 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1435 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1438 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 1436 nsymbits = bits_per_symbol[rix][width];
1439 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1437 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1440 1438
1441 if (!half_gi) 1439 if (!half_gi)
@@ -1444,7 +1442,7 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1444 duration = SYMBOL_TIME_HALFGI(nsymbols); 1442 duration = SYMBOL_TIME_HALFGI(nsymbols);
1445 1443
1446 /* addup duration for legacy/ht training and signal fields */ 1444 /* addup duration for legacy/ht training and signal fields */
1447 streams = HT_RC_2_STREAMS(rc); 1445 streams = HT_RC_2_STREAMS(rix);
1448 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1446 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1449 1447
1450 return duration; 1448 return duration;
@@ -1452,11 +1450,12 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1452 1450
1453static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) 1451static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1454{ 1452{
1455 const struct ath_rate_table *rt = sc->cur_rate_table; 1453 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1456 struct ath9k_11n_rate_series series[4]; 1454 struct ath9k_11n_rate_series series[4];
1457 struct sk_buff *skb; 1455 struct sk_buff *skb;
1458 struct ieee80211_tx_info *tx_info; 1456 struct ieee80211_tx_info *tx_info;
1459 struct ieee80211_tx_rate *rates; 1457 struct ieee80211_tx_rate *rates;
1458 const struct ieee80211_rate *rate;
1460 struct ieee80211_hdr *hdr; 1459 struct ieee80211_hdr *hdr;
1461 int i, flags = 0; 1460 int i, flags = 0;
1462 u8 rix = 0, ctsrate = 0; 1461 u8 rix = 0, ctsrate = 0;
@@ -1475,59 +1474,76 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1475 * checking the BSS's global flag. 1474 * checking the BSS's global flag.
1476 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 1475 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1477 */ 1476 */
1477 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1478 ctsrate = rate->hw_value;
1478 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 1479 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1479 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | 1480 ctsrate |= rate->hw_value_short;
1480 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1481 else
1482 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1483
1484 /*
1485 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1486 * Check the first rate in the series to decide whether RTS/CTS
1487 * or CTS-to-self has to be used.
1488 */
1489 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1490 flags = ATH9K_TXDESC_CTSENA;
1491 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1492 flags = ATH9K_TXDESC_RTSENA;
1493
1494 /* FIXME: Handle aggregation protection */
1495 if (sc->config.ath_aggr_prot &&
1496 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1497 flags = ATH9K_TXDESC_RTSENA;
1498 }
1499
1500 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1501 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1502 flags &= ~(ATH9K_TXDESC_RTSENA);
1503 1481
1504 for (i = 0; i < 4; i++) { 1482 for (i = 0; i < 4; i++) {
1483 bool is_40, is_sgi, is_sp;
1484 int phy;
1485
1505 if (!rates[i].count || (rates[i].idx < 0)) 1486 if (!rates[i].count || (rates[i].idx < 0))
1506 continue; 1487 continue;
1507 1488
1508 rix = rates[i].idx; 1489 rix = rates[i].idx;
1509 series[i].Tries = rates[i].count; 1490 series[i].Tries = rates[i].count;
1510 series[i].ChSel = sc->tx_chainmask; 1491 series[i].ChSel = common->tx_chainmask;
1511 1492
1512 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1493 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1513 series[i].Rate = rt->info[rix].ratecode | 1494 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1514 rt->info[rix].short_preamble; 1495 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1515 else 1496 flags |= ATH9K_TXDESC_RTSENA;
1516 series[i].Rate = rt->info[rix].ratecode; 1497 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1517
1518 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1519 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1498 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1499 flags |= ATH9K_TXDESC_CTSENA;
1500 }
1501
1520 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1502 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1521 series[i].RateFlags |= ATH9K_RATESERIES_2040; 1503 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1522 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1504 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1523 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1505 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1524 1506
1525 series[i].PktDuration = ath_pkt_duration(sc, rix, bf, 1507 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1526 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, 1508 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1527 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), 1509 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1528 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); 1510
1511 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1512 /* MCS rates */
1513 series[i].Rate = rix | 0x80;
1514 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1515 is_40, is_sgi, is_sp);
1516 continue;
1517 }
1518
1519 /* legcay rates */
1520 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1521 !(rate->flags & IEEE80211_RATE_ERP_G))
1522 phy = WLAN_RC_PHY_CCK;
1523 else
1524 phy = WLAN_RC_PHY_OFDM;
1525
1526 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1527 series[i].Rate = rate->hw_value;
1528 if (rate->hw_value_short) {
1529 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1530 series[i].Rate |= rate->hw_value_short;
1531 } else {
1532 is_sp = false;
1533 }
1534
1535 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1536 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1529 } 1537 }
1530 1538
1539 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1540 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1541 flags &= ~ATH9K_TXDESC_RTSENA;
1542
1543 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1544 if (flags & ATH9K_TXDESC_RTSENA)
1545 flags &= ~ATH9K_TXDESC_CTSENA;
1546
1531 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1547 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1532 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 1548 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1533 bf->bf_lastbf->bf_desc, 1549 bf->bf_lastbf->bf_desc,
@@ -1546,24 +1562,36 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1546 struct ath_softc *sc = aphy->sc; 1562 struct ath_softc *sc = aphy->sc;
1547 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1563 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1564 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1549 struct ath_tx_info_priv *tx_info_priv;
1550 int hdrlen; 1565 int hdrlen;
1551 __le16 fc; 1566 __le16 fc;
1567 int padpos, padsize;
1552 1568
1553 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); 1569 tx_info->pad[0] = 0;
1554 if (unlikely(!tx_info_priv)) 1570 switch (txctl->frame_type) {
1555 return -ENOMEM; 1571 case ATH9K_NOT_INTERNAL:
1556 tx_info->rate_driver_data[0] = tx_info_priv; 1572 break;
1557 tx_info_priv->aphy = aphy; 1573 case ATH9K_INT_PAUSE:
1558 tx_info_priv->frame_type = txctl->frame_type; 1574 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1575 /* fall through */
1576 case ATH9K_INT_UNPAUSE:
1577 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1578 break;
1579 }
1559 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1580 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1560 fc = hdr->frame_control; 1581 fc = hdr->frame_control;
1561 1582
1562 ATH_TXBUF_RESET(bf); 1583 ATH_TXBUF_RESET(bf);
1563 1584
1564 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); 1585 bf->aphy = aphy;
1586 bf->bf_frmlen = skb->len + FCS_LEN;
1587 /* Remove the padding size from bf_frmlen, if any */
1588 padpos = ath9k_cmn_padpos(hdr->frame_control);
1589 padsize = padpos & 3;
1590 if (padsize && skb->len>padpos+padsize) {
1591 bf->bf_frmlen -= padsize;
1592 }
1565 1593
1566 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) 1594 if (conf_is_ht(&hw->conf))
1567 bf->bf_state.bf_type |= BUF_HT; 1595 bf->bf_state.bf_type |= BUF_HT;
1568 1596
1569 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); 1597 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
@@ -1576,7 +1604,8 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1576 bf->bf_keyix = ATH9K_TXKEYIX_INVALID; 1604 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1577 } 1605 }
1578 1606
1579 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) 1607 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1608 (sc->sc_flags & SC_OP_TXAGGR))
1580 assign_aggr_tid_seqno(skb, bf); 1609 assign_aggr_tid_seqno(skb, bf);
1581 1610
1582 bf->bf_mpdu = skb; 1611 bf->bf_mpdu = skb;
@@ -1585,13 +1614,20 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1585 skb->len, DMA_TO_DEVICE); 1614 skb->len, DMA_TO_DEVICE);
1586 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { 1615 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1587 bf->bf_mpdu = NULL; 1616 bf->bf_mpdu = NULL;
1588 kfree(tx_info_priv); 1617 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1589 tx_info->rate_driver_data[0] = NULL; 1618 "dma_mapping_error() on TX\n");
1590 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1591 return -ENOMEM; 1619 return -ENOMEM;
1592 } 1620 }
1593 1621
1594 bf->bf_buf_addr = bf->bf_dmacontext; 1622 bf->bf_buf_addr = bf->bf_dmacontext;
1623
1624 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1625 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1626 bf->bf_isnullfunc = true;
1627 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1628 } else
1629 bf->bf_isnullfunc = false;
1630
1595 return 0; 1631 return 0;
1596} 1632}
1597 1633
@@ -1669,12 +1705,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1669{ 1705{
1670 struct ath_wiphy *aphy = hw->priv; 1706 struct ath_wiphy *aphy = hw->priv;
1671 struct ath_softc *sc = aphy->sc; 1707 struct ath_softc *sc = aphy->sc;
1708 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1672 struct ath_buf *bf; 1709 struct ath_buf *bf;
1673 int r; 1710 int r;
1674 1711
1675 bf = ath_tx_get_buffer(sc); 1712 bf = ath_tx_get_buffer(sc);
1676 if (!bf) { 1713 if (!bf) {
1677 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); 1714 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1678 return -1; 1715 return -1;
1679 } 1716 }
1680 1717
@@ -1682,7 +1719,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1682 if (unlikely(r)) { 1719 if (unlikely(r)) {
1683 struct ath_txq *txq = txctl->txq; 1720 struct ath_txq *txq = txctl->txq;
1684 1721
1685 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1722 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1686 1723
1687 /* upon ath_tx_processq() this TX queue will be resumed, we 1724 /* upon ath_tx_processq() this TX queue will be resumed, we
1688 * guarantee this will happen by knowing beforehand that 1725 * guarantee this will happen by knowing beforehand that
@@ -1690,8 +1727,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1690 * on the queue */ 1727 * on the queue */
1691 spin_lock_bh(&txq->axq_lock); 1728 spin_lock_bh(&txq->axq_lock);
1692 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { 1729 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1693 ieee80211_stop_queue(sc->hw, 1730 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1694 skb_get_queue_mapping(skb));
1695 txq->stopped = 1; 1731 txq->stopped = 1;
1696 } 1732 }
1697 spin_unlock_bh(&txq->axq_lock); 1733 spin_unlock_bh(&txq->axq_lock);
@@ -1712,7 +1748,9 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1712{ 1748{
1713 struct ath_wiphy *aphy = hw->priv; 1749 struct ath_wiphy *aphy = hw->priv;
1714 struct ath_softc *sc = aphy->sc; 1750 struct ath_softc *sc = aphy->sc;
1715 int hdrlen, padsize; 1751 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1752 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1753 int padpos, padsize;
1716 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1754 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1717 struct ath_tx_control txctl; 1755 struct ath_tx_control txctl;
1718 1756
@@ -1724,7 +1762,6 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1724 * BSSes. 1762 * BSSes.
1725 */ 1763 */
1726 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1764 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1727 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1728 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1765 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1729 sc->tx.seq_no += 0x10; 1766 sc->tx.seq_no += 0x10;
1730 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1767 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
@@ -1732,24 +1769,26 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1732 } 1769 }
1733 1770
1734 /* Add the padding after the header if this is not already done */ 1771 /* Add the padding after the header if this is not already done */
1735 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1772 padpos = ath9k_cmn_padpos(hdr->frame_control);
1736 if (hdrlen & 3) { 1773 padsize = padpos & 3;
1737 padsize = hdrlen % 4; 1774 if (padsize && skb->len>padpos) {
1738 if (skb_headroom(skb) < padsize) { 1775 if (skb_headroom(skb) < padsize) {
1739 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); 1776 ath_print(common, ATH_DBG_XMIT,
1777 "TX CABQ padding failed\n");
1740 dev_kfree_skb_any(skb); 1778 dev_kfree_skb_any(skb);
1741 return; 1779 return;
1742 } 1780 }
1743 skb_push(skb, padsize); 1781 skb_push(skb, padsize);
1744 memmove(skb->data, skb->data + padsize, hdrlen); 1782 memmove(skb->data, skb->data + padsize, padpos);
1745 } 1783 }
1746 1784
1747 txctl.txq = sc->beacon.cabq; 1785 txctl.txq = sc->beacon.cabq;
1748 1786
1749 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1787 ath_print(common, ATH_DBG_XMIT,
1788 "transmitting CABQ packet, skb: %p\n", skb);
1750 1789
1751 if (ath_tx_start(hw, skb, &txctl) != 0) { 1790 if (ath_tx_start(hw, skb, &txctl) != 0) {
1752 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); 1791 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1753 goto exit; 1792 goto exit;
1754 } 1793 }
1755 1794
@@ -1763,26 +1802,18 @@ exit:
1763/*****************/ 1802/*****************/
1764 1803
1765static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1804static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1766 int tx_flags) 1805 struct ath_wiphy *aphy, int tx_flags)
1767{ 1806{
1768 struct ieee80211_hw *hw = sc->hw; 1807 struct ieee80211_hw *hw = sc->hw;
1769 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1808 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1770 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1809 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1771 int hdrlen, padsize; 1810 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1772 int frame_type = ATH9K_NOT_INTERNAL; 1811 int padpos, padsize;
1773 1812
1774 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1813 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1775
1776 if (tx_info_priv) {
1777 hw = tx_info_priv->aphy->hw;
1778 frame_type = tx_info_priv->frame_type;
1779 }
1780 1814
1781 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || 1815 if (aphy)
1782 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { 1816 hw = aphy->hw;
1783 kfree(tx_info_priv);
1784 tx_info->rate_driver_data[0] = NULL;
1785 }
1786 1817
1787 if (tx_flags & ATH_TX_BAR) 1818 if (tx_flags & ATH_TX_BAR)
1788 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1819 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
@@ -1792,31 +1823,32 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1792 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1823 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1793 } 1824 }
1794 1825
1795 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1826 padpos = ath9k_cmn_padpos(hdr->frame_control);
1796 padsize = hdrlen & 3; 1827 padsize = padpos & 3;
1797 if (padsize && hdrlen >= 24) { 1828 if (padsize && skb->len>padpos+padsize) {
1798 /* 1829 /*
1799 * Remove MAC header padding before giving the frame back to 1830 * Remove MAC header padding before giving the frame back to
1800 * mac80211. 1831 * mac80211.
1801 */ 1832 */
1802 memmove(skb->data + padsize, skb->data, hdrlen); 1833 memmove(skb->data + padsize, skb->data, padpos);
1803 skb_pull(skb, padsize); 1834 skb_pull(skb, padsize);
1804 } 1835 }
1805 1836
1806 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1837 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1807 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1838 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1808 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 1839 ath_print(common, ATH_DBG_PS,
1809 "received TX status (0x%x)\n", 1840 "Going back to sleep after having "
1810 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1841 "received TX status (0x%lx)\n",
1811 SC_OP_WAIT_FOR_CAB | 1842 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1812 SC_OP_WAIT_FOR_PSPOLL_DATA | 1843 PS_WAIT_FOR_CAB |
1813 SC_OP_WAIT_FOR_TX_ACK)); 1844 PS_WAIT_FOR_PSPOLL_DATA |
1845 PS_WAIT_FOR_TX_ACK));
1814 } 1846 }
1815 1847
1816 if (frame_type == ATH9K_NOT_INTERNAL) 1848 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1817 ieee80211_tx_status(hw, skb);
1818 else
1819 ath9k_tx_status(hw, skb); 1849 ath9k_tx_status(hw, skb);
1850 else
1851 ieee80211_tx_status(hw, skb);
1820} 1852}
1821 1853
1822static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 1854static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
@@ -1839,7 +1871,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1839 } 1871 }
1840 1872
1841 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); 1873 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1842 ath_tx_complete(sc, skb, tx_flags); 1874 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1843 ath_debug_stat_tx(sc, txq, bf); 1875 ath_debug_stat_tx(sc, txq, bf);
1844 1876
1845 /* 1877 /*
@@ -1887,8 +1919,7 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1887 struct sk_buff *skb = bf->bf_mpdu; 1919 struct sk_buff *skb = bf->bf_mpdu;
1888 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1920 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1889 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1921 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1890 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1922 struct ieee80211_hw *hw = bf->aphy->hw;
1891 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1892 u8 i, tx_rateindex; 1923 u8 i, tx_rateindex;
1893 1924
1894 if (txok) 1925 if (txok)
@@ -1897,22 +1928,29 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1897 tx_rateindex = ds->ds_txstat.ts_rateindex; 1928 tx_rateindex = ds->ds_txstat.ts_rateindex;
1898 WARN_ON(tx_rateindex >= hw->max_rates); 1929 WARN_ON(tx_rateindex >= hw->max_rates);
1899 1930
1900 tx_info_priv->update_rc = update_rc; 1931 if (update_rc)
1932 tx_info->pad[0] |= ATH_TX_INFO_UPDATE_RC;
1901 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) 1933 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1902 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1934 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1903 1935
1904 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && 1936 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1905 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1937 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1906 if (ieee80211_is_data(hdr->frame_control)) { 1938 if (ieee80211_is_data(hdr->frame_control)) {
1907 memcpy(&tx_info_priv->tx, &ds->ds_txstat, 1939 if (ds->ds_txstat.ts_flags &
1908 sizeof(tx_info_priv->tx)); 1940 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
1909 tx_info_priv->n_frames = bf->bf_nframes; 1941 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
1910 tx_info_priv->n_bad_frames = nbad; 1942 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) ||
1943 (ds->ds_txstat.ts_status & ATH9K_TXERR_FIFO))
1944 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
1945 tx_info->status.ampdu_len = bf->bf_nframes;
1946 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
1911 } 1947 }
1912 } 1948 }
1913 1949
1914 for (i = tx_rateindex + 1; i < hw->max_rates; i++) 1950 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1915 tx_info->status.rates[i].count = 0; 1951 tx_info->status.rates[i].count = 0;
1952 tx_info->status.rates[i].idx = -1;
1953 }
1916 1954
1917 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; 1955 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1918} 1956}
@@ -1926,7 +1964,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1926 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { 1964 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1927 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); 1965 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1928 if (qnum != -1) { 1966 if (qnum != -1) {
1929 ieee80211_wake_queue(sc->hw, qnum); 1967 ath_mac80211_start_queue(sc, qnum);
1930 txq->stopped = 0; 1968 txq->stopped = 0;
1931 } 1969 }
1932 } 1970 }
@@ -1936,21 +1974,21 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1936static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1974static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1937{ 1975{
1938 struct ath_hw *ah = sc->sc_ah; 1976 struct ath_hw *ah = sc->sc_ah;
1977 struct ath_common *common = ath9k_hw_common(ah);
1939 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1978 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1940 struct list_head bf_head; 1979 struct list_head bf_head;
1941 struct ath_desc *ds; 1980 struct ath_desc *ds;
1942 int txok; 1981 int txok;
1943 int status; 1982 int status;
1944 1983
1945 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1984 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1946 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1985 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1947 txq->axq_link); 1986 txq->axq_link);
1948 1987
1949 for (;;) { 1988 for (;;) {
1950 spin_lock_bh(&txq->axq_lock); 1989 spin_lock_bh(&txq->axq_lock);
1951 if (list_empty(&txq->axq_q)) { 1990 if (list_empty(&txq->axq_q)) {
1952 txq->axq_link = NULL; 1991 txq->axq_link = NULL;
1953 txq->axq_linkbuf = NULL;
1954 spin_unlock_bh(&txq->axq_lock); 1992 spin_unlock_bh(&txq->axq_lock);
1955 break; 1993 break;
1956 } 1994 }
@@ -1984,10 +2022,18 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1984 spin_unlock_bh(&txq->axq_lock); 2022 spin_unlock_bh(&txq->axq_lock);
1985 break; 2023 break;
1986 } 2024 }
1987 if (bf->bf_desc == txq->axq_lastdsWithCTS) 2025
1988 txq->axq_lastdsWithCTS = NULL; 2026 /*
1989 if (ds == txq->axq_gatingds) 2027 * We now know the nullfunc frame has been ACKed so we
1990 txq->axq_gatingds = NULL; 2028 * can disable RX.
2029 */
2030 if (bf->bf_isnullfunc &&
2031 (ds->ds_txstat.ts_status & ATH9K_TX_ACKED)) {
2032 if ((sc->ps_flags & PS_ENABLED))
2033 ath9k_enable_ps(sc);
2034 else
2035 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2036 }
1991 2037
1992 /* 2038 /*
1993 * Remove ath_buf's of the same transmit unit from txq, 2039 * Remove ath_buf's of the same transmit unit from txq,
@@ -2001,10 +2047,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2001 &txq->axq_q, lastbf->list.prev); 2047 &txq->axq_q, lastbf->list.prev);
2002 2048
2003 txq->axq_depth--; 2049 txq->axq_depth--;
2004 if (bf_isaggr(bf)) 2050 txok = !(ds->ds_txstat.ts_status & ATH9K_TXERR_MASK);
2005 txq->axq_aggr_depth--;
2006
2007 txok = (ds->ds_txstat.ts_status == 0);
2008 txq->axq_tx_inprogress = false; 2051 txq->axq_tx_inprogress = false;
2009 spin_unlock_bh(&txq->axq_lock); 2052 spin_unlock_bh(&txq->axq_lock);
2010 2053
@@ -2064,8 +2107,11 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2064 } 2107 }
2065 2108
2066 if (needreset) { 2109 if (needreset) {
2067 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n"); 2110 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2111 "tx hung, resetting the chip\n");
2112 ath9k_ps_wakeup(sc);
2068 ath_reset(sc, false); 2113 ath_reset(sc, false);
2114 ath9k_ps_restore(sc);
2069 } 2115 }
2070 2116
2071 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2117 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2093,6 +2139,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
2093 2139
2094int ath_tx_init(struct ath_softc *sc, int nbufs) 2140int ath_tx_init(struct ath_softc *sc, int nbufs)
2095{ 2141{
2142 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2096 int error = 0; 2143 int error = 0;
2097 2144
2098 spin_lock_init(&sc->tx.txbuflock); 2145 spin_lock_init(&sc->tx.txbuflock);
@@ -2100,16 +2147,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2100 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2147 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2101 "tx", nbufs, 1); 2148 "tx", nbufs, 1);
2102 if (error != 0) { 2149 if (error != 0) {
2103 DPRINTF(sc, ATH_DBG_FATAL, 2150 ath_print(common, ATH_DBG_FATAL,
2104 "Failed to allocate tx descriptors: %d\n", error); 2151 "Failed to allocate tx descriptors: %d\n", error);
2105 goto err; 2152 goto err;
2106 } 2153 }
2107 2154
2108 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2155 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2109 "beacon", ATH_BCBUF, 1); 2156 "beacon", ATH_BCBUF, 1);
2110 if (error != 0) { 2157 if (error != 0) {
2111 DPRINTF(sc, ATH_DBG_FATAL, 2158 ath_print(common, ATH_DBG_FATAL,
2112 "Failed to allocate beacon descriptors: %d\n", error); 2159 "Failed to allocate beacon descriptors: %d\n", error);
2113 goto err; 2160 goto err;
2114 } 2161 }
2115 2162
@@ -2192,7 +2239,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2192 if (ATH_TXQ_SETUP(sc, i)) { 2239 if (ATH_TXQ_SETUP(sc, i)) {
2193 txq = &sc->tx.txq[i]; 2240 txq = &sc->tx.txq[i];
2194 2241
2195 spin_lock(&txq->axq_lock); 2242 spin_lock_bh(&txq->axq_lock);
2196 2243
2197 list_for_each_entry_safe(ac, 2244 list_for_each_entry_safe(ac,
2198 ac_tmp, &txq->axq_acq, list) { 2245 ac_tmp, &txq->axq_acq, list) {
@@ -2213,7 +2260,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2213 } 2260 }
2214 } 2261 }
2215 2262
2216 spin_unlock(&txq->axq_lock); 2263 spin_unlock_bh(&txq->axq_lock);
2217 } 2264 }
2218 } 2265 }
2219} 2266}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-29 16:48:34 -0400