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path: root/drivers/net/wireless/ath/ath9k/xmit.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/xmit.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c465
1 files changed, 256 insertions, 209 deletions
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 42551a48c8ac..294b486bc3ed 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -70,6 +70,29 @@ static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
70static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, 70static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
71 int nbad, int txok, bool update_rc); 71 int nbad, int txok, bool update_rc);
72 72
73enum {
74 MCS_DEFAULT,
75 MCS_HT40,
76 MCS_HT40_SGI,
77};
78
79static int ath_max_4ms_framelen[3][16] = {
80 [MCS_DEFAULT] = {
81 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180,
82 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320,
83 },
84 [MCS_HT40] = {
85 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840,
86 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600,
87 },
88 [MCS_HT40_SGI] = {
89 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */
90 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200,
91 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400,
92 }
93};
94
95
73/*********************/ 96/*********************/
74/* Aggregation logic */ 97/* Aggregation logic */
75/*********************/ 98/*********************/
@@ -107,7 +130,7 @@ static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
107{ 130{
108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 131 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
109 132
110 ASSERT(tid->paused > 0); 133 BUG_ON(tid->paused <= 0);
111 spin_lock_bh(&txq->axq_lock); 134 spin_lock_bh(&txq->axq_lock);
112 135
113 tid->paused--; 136 tid->paused--;
@@ -131,7 +154,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
131 struct list_head bf_head; 154 struct list_head bf_head;
132 INIT_LIST_HEAD(&bf_head); 155 INIT_LIST_HEAD(&bf_head);
133 156
134 ASSERT(tid->paused > 0); 157 BUG_ON(tid->paused <= 0);
135 spin_lock_bh(&txq->axq_lock); 158 spin_lock_bh(&txq->axq_lock);
136 159
137 tid->paused--; 160 tid->paused--;
@@ -143,7 +166,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
143 166
144 while (!list_empty(&tid->buf_q)) { 167 while (!list_empty(&tid->buf_q)) {
145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 168 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
146 ASSERT(!bf_isretried(bf)); 169 BUG_ON(bf_isretried(bf));
147 list_move_tail(&bf->list, &bf_head); 170 list_move_tail(&bf->list, &bf_head);
148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head); 171 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
149 } 172 }
@@ -178,7 +201,7 @@ static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); 201 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
180 203
181 ASSERT(tid->tx_buf[cindex] == NULL); 204 BUG_ON(tid->tx_buf[cindex] != NULL);
182 tid->tx_buf[cindex] = bf; 205 tid->tx_buf[cindex] = bf;
183 206
184 if (index >= ((tid->baw_tail - tid->baw_head) & 207 if (index >= ((tid->baw_tail - tid->baw_head) &
@@ -251,6 +274,7 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
251 274
252 ATH_TXBUF_RESET(tbf); 275 ATH_TXBUF_RESET(tbf);
253 276
277 tbf->aphy = bf->aphy;
254 tbf->bf_mpdu = bf->bf_mpdu; 278 tbf->bf_mpdu = bf->bf_mpdu;
255 tbf->bf_buf_addr = bf->bf_buf_addr; 279 tbf->bf_buf_addr = bf->bf_buf_addr;
256 *(tbf->bf_desc) = *(bf->bf_desc); 280 *(tbf->bf_desc) = *(bf->bf_desc);
@@ -267,7 +291,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
267 struct ath_node *an = NULL; 291 struct ath_node *an = NULL;
268 struct sk_buff *skb; 292 struct sk_buff *skb;
269 struct ieee80211_sta *sta; 293 struct ieee80211_sta *sta;
294 struct ieee80211_hw *hw;
270 struct ieee80211_hdr *hdr; 295 struct ieee80211_hdr *hdr;
296 struct ieee80211_tx_info *tx_info;
271 struct ath_atx_tid *tid = NULL; 297 struct ath_atx_tid *tid = NULL;
272 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 298 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
273 struct ath_desc *ds = bf_last->bf_desc; 299 struct ath_desc *ds = bf_last->bf_desc;
@@ -280,9 +306,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
280 skb = bf->bf_mpdu; 306 skb = bf->bf_mpdu;
281 hdr = (struct ieee80211_hdr *)skb->data; 307 hdr = (struct ieee80211_hdr *)skb->data;
282 308
309 tx_info = IEEE80211_SKB_CB(skb);
310 hw = bf->aphy->hw;
311
283 rcu_read_lock(); 312 rcu_read_lock();
284 313
285 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 314 /* XXX: use ieee80211_find_sta! */
315 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
286 if (!sta) { 316 if (!sta) {
287 rcu_read_unlock(); 317 rcu_read_unlock();
288 return; 318 return;
@@ -358,7 +388,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
358 else 388 else
359 INIT_LIST_HEAD(&bf_head); 389 INIT_LIST_HEAD(&bf_head);
360 } else { 390 } else {
361 ASSERT(!list_empty(bf_q)); 391 BUG_ON(list_empty(bf_q));
362 list_move_tail(&bf->list, &bf_head); 392 list_move_tail(&bf->list, &bf_head);
363 } 393 }
364 394
@@ -452,11 +482,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
452static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 482static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
453 struct ath_atx_tid *tid) 483 struct ath_atx_tid *tid)
454{ 484{
455 const struct ath_rate_table *rate_table = sc->cur_rate_table;
456 struct sk_buff *skb; 485 struct sk_buff *skb;
457 struct ieee80211_tx_info *tx_info; 486 struct ieee80211_tx_info *tx_info;
458 struct ieee80211_tx_rate *rates; 487 struct ieee80211_tx_rate *rates;
459 struct ath_tx_info_priv *tx_info_priv;
460 u32 max_4ms_framelen, frmlen; 488 u32 max_4ms_framelen, frmlen;
461 u16 aggr_limit, legacy = 0; 489 u16 aggr_limit, legacy = 0;
462 int i; 490 int i;
@@ -464,7 +492,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
464 skb = bf->bf_mpdu; 492 skb = bf->bf_mpdu;
465 tx_info = IEEE80211_SKB_CB(skb); 493 tx_info = IEEE80211_SKB_CB(skb);
466 rates = tx_info->control.rates; 494 rates = tx_info->control.rates;
467 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
468 495
469 /* 496 /*
470 * Find the lowest frame length among the rate series that will have a 497 * Find the lowest frame length among the rate series that will have a
@@ -475,12 +502,20 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
475 502
476 for (i = 0; i < 4; i++) { 503 for (i = 0; i < 4; i++) {
477 if (rates[i].count) { 504 if (rates[i].count) {
478 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { 505 int modeidx;
506 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
479 legacy = 1; 507 legacy = 1;
480 break; 508 break;
481 } 509 }
482 510
483 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; 511 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
512 modeidx = MCS_HT40_SGI;
513 else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
514 modeidx = MCS_HT40;
515 else
516 modeidx = MCS_DEFAULT;
517
518 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
484 max_4ms_framelen = min(max_4ms_framelen, frmlen); 519 max_4ms_framelen = min(max_4ms_framelen, frmlen);
485 } 520 }
486 } 521 }
@@ -518,12 +553,11 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
518static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 553static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
519 struct ath_buf *bf, u16 frmlen) 554 struct ath_buf *bf, u16 frmlen)
520{ 555{
521 const struct ath_rate_table *rt = sc->cur_rate_table;
522 struct sk_buff *skb = bf->bf_mpdu; 556 struct sk_buff *skb = bf->bf_mpdu;
523 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 557 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
524 u32 nsymbits, nsymbols; 558 u32 nsymbits, nsymbols;
525 u16 minlen; 559 u16 minlen;
526 u8 rc, flags, rix; 560 u8 flags, rix;
527 int width, half_gi, ndelim, mindelim; 561 int width, half_gi, ndelim, mindelim;
528 562
529 /* Select standard number of delimiters based on frame length alone */ 563 /* Select standard number of delimiters based on frame length alone */
@@ -553,7 +587,6 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
553 587
554 rix = tx_info->control.rates[0].idx; 588 rix = tx_info->control.rates[0].idx;
555 flags = tx_info->control.rates[0].flags; 589 flags = tx_info->control.rates[0].flags;
556 rc = rt->info[rix].ratecode;
557 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 590 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
558 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 591 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
559 592
@@ -565,7 +598,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
565 if (nsymbols == 0) 598 if (nsymbols == 0)
566 nsymbols = 1; 599 nsymbols = 1;
567 600
568 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 601 nsymbits = bits_per_symbol[rix][width];
569 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 602 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
570 603
571 if (frmlen < minlen) { 604 if (frmlen < minlen) {
@@ -694,7 +727,6 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
694 /* anchor last desc of aggregate */ 727 /* anchor last desc of aggregate */
695 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 728 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
696 729
697 txq->axq_aggr_depth++;
698 ath_tx_txqaddbuf(sc, txq, &bf_q); 730 ath_tx_txqaddbuf(sc, txq, &bf_q);
699 TX_STAT_INC(txq->axq_qnum, a_aggr); 731 TX_STAT_INC(txq->axq_qnum, a_aggr);
700 732
@@ -815,6 +847,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
815struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 847struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
816{ 848{
817 struct ath_hw *ah = sc->sc_ah; 849 struct ath_hw *ah = sc->sc_ah;
850 struct ath_common *common = ath9k_hw_common(ah);
818 struct ath9k_tx_queue_info qi; 851 struct ath9k_tx_queue_info qi;
819 int qnum; 852 int qnum;
820 853
@@ -854,9 +887,9 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
854 return NULL; 887 return NULL;
855 } 888 }
856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 889 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
857 DPRINTF(sc, ATH_DBG_FATAL, 890 ath_print(common, ATH_DBG_FATAL,
858 "qnum %u out of range, max %u!\n", 891 "qnum %u out of range, max %u!\n",
859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 892 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
860 ath9k_hw_releasetxqueue(ah, qnum); 893 ath9k_hw_releasetxqueue(ah, qnum);
861 return NULL; 894 return NULL;
862 } 895 }
@@ -869,8 +902,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
869 INIT_LIST_HEAD(&txq->axq_acq); 902 INIT_LIST_HEAD(&txq->axq_acq);
870 spin_lock_init(&txq->axq_lock); 903 spin_lock_init(&txq->axq_lock);
871 txq->axq_depth = 0; 904 txq->axq_depth = 0;
872 txq->axq_aggr_depth = 0;
873 txq->axq_linkbuf = NULL;
874 txq->axq_tx_inprogress = false; 905 txq->axq_tx_inprogress = false;
875 sc->tx.txqsetup |= 1<<qnum; 906 sc->tx.txqsetup |= 1<<qnum;
876 } 907 }
@@ -884,9 +915,9 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
884 switch (qtype) { 915 switch (qtype) {
885 case ATH9K_TX_QUEUE_DATA: 916 case ATH9K_TX_QUEUE_DATA:
886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 917 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
887 DPRINTF(sc, ATH_DBG_FATAL, 918 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
888 "HAL AC %u out of range, max %zu!\n", 919 "HAL AC %u out of range, max %zu!\n",
889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 920 haltype, ARRAY_SIZE(sc->tx.hwq_map));
890 return -1; 921 return -1;
891 } 922 }
892 qnum = sc->tx.hwq_map[haltype]; 923 qnum = sc->tx.hwq_map[haltype];
@@ -906,18 +937,19 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
906struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) 937struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
907{ 938{
908 struct ath_txq *txq = NULL; 939 struct ath_txq *txq = NULL;
940 u16 skb_queue = skb_get_queue_mapping(skb);
909 int qnum; 941 int qnum;
910 942
911 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 943 qnum = ath_get_hal_qnum(skb_queue, sc);
912 txq = &sc->tx.txq[qnum]; 944 txq = &sc->tx.txq[qnum];
913 945
914 spin_lock_bh(&txq->axq_lock); 946 spin_lock_bh(&txq->axq_lock);
915 947
916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 948 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
917 DPRINTF(sc, ATH_DBG_XMIT, 949 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
918 "TX queue: %d is full, depth: %d\n", 950 "TX queue: %d is full, depth: %d\n",
919 qnum, txq->axq_depth); 951 qnum, txq->axq_depth);
920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 952 ath_mac80211_stop_queue(sc, skb_queue);
921 txq->stopped = 1; 953 txq->stopped = 1;
922 spin_unlock_bh(&txq->axq_lock); 954 spin_unlock_bh(&txq->axq_lock);
923 return NULL; 955 return NULL;
@@ -945,7 +977,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
945 return 0; 977 return 0;
946 } 978 }
947 979
948 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); 980 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
949 981
950 ath9k_hw_get_txq_props(ah, qnum, &qi); 982 ath9k_hw_get_txq_props(ah, qnum, &qi);
951 qi.tqi_aifs = qinfo->tqi_aifs; 983 qi.tqi_aifs = qinfo->tqi_aifs;
@@ -955,8 +987,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
955 qi.tqi_readyTime = qinfo->tqi_readyTime; 987 qi.tqi_readyTime = qinfo->tqi_readyTime;
956 988
957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 989 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
958 DPRINTF(sc, ATH_DBG_FATAL, 990 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
959 "Unable to update hardware queue %u!\n", qnum); 991 "Unable to update hardware queue %u!\n", qnum);
960 error = -EIO; 992 error = -EIO;
961 } else { 993 } else {
962 ath9k_hw_resettxqueue(ah, qnum); 994 ath9k_hw_resettxqueue(ah, qnum);
@@ -1004,7 +1036,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1004 1036
1005 if (list_empty(&txq->axq_q)) { 1037 if (list_empty(&txq->axq_q)) {
1006 txq->axq_link = NULL; 1038 txq->axq_link = NULL;
1007 txq->axq_linkbuf = NULL;
1008 spin_unlock_bh(&txq->axq_lock); 1039 spin_unlock_bh(&txq->axq_lock);
1009 break; 1040 break;
1010 } 1041 }
@@ -1055,6 +1086,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1055void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1086void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1056{ 1087{
1057 struct ath_hw *ah = sc->sc_ah; 1088 struct ath_hw *ah = sc->sc_ah;
1089 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1058 struct ath_txq *txq; 1090 struct ath_txq *txq;
1059 int i, npend = 0; 1091 int i, npend = 0;
1060 1092
@@ -1076,14 +1108,15 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1076 if (npend) { 1108 if (npend) {
1077 int r; 1109 int r;
1078 1110
1079 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1111 ath_print(common, ATH_DBG_FATAL,
1112 "Unable to stop TxDMA. Reset HAL!\n");
1080 1113
1081 spin_lock_bh(&sc->sc_resetlock); 1114 spin_lock_bh(&sc->sc_resetlock);
1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1115 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1083 if (r) 1116 if (r)
1084 DPRINTF(sc, ATH_DBG_FATAL, 1117 ath_print(common, ATH_DBG_FATAL,
1085 "Unable to reset hardware; reset status %d\n", 1118 "Unable to reset hardware; reset status %d\n",
1086 r); 1119 r);
1087 spin_unlock_bh(&sc->sc_resetlock); 1120 spin_unlock_bh(&sc->sc_resetlock);
1088 } 1121 }
1089 1122
@@ -1147,8 +1180,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1147 struct ath_txq *txq; 1180 struct ath_txq *txq;
1148 1181
1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1182 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1150 DPRINTF(sc, ATH_DBG_FATAL, 1183 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1151 "HAL AC %u out of range, max %zu!\n", 1184 "HAL AC %u out of range, max %zu!\n",
1152 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1185 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1153 return 0; 1186 return 0;
1154 } 1187 }
@@ -1172,6 +1205,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1172 struct list_head *head) 1205 struct list_head *head)
1173{ 1206{
1174 struct ath_hw *ah = sc->sc_ah; 1207 struct ath_hw *ah = sc->sc_ah;
1208 struct ath_common *common = ath9k_hw_common(ah);
1175 struct ath_buf *bf; 1209 struct ath_buf *bf;
1176 1210
1177 /* 1211 /*
@@ -1186,21 +1220,20 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1186 1220
1187 list_splice_tail_init(head, &txq->axq_q); 1221 list_splice_tail_init(head, &txq->axq_q);
1188 txq->axq_depth++; 1222 txq->axq_depth++;
1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1190 1223
1191 DPRINTF(sc, ATH_DBG_QUEUE, 1224 ath_print(common, ATH_DBG_QUEUE,
1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1225 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1193 1226
1194 if (txq->axq_link == NULL) { 1227 if (txq->axq_link == NULL) {
1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1228 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1196 DPRINTF(sc, ATH_DBG_XMIT, 1229 ath_print(common, ATH_DBG_XMIT,
1197 "TXDP[%u] = %llx (%p)\n", 1230 "TXDP[%u] = %llx (%p)\n",
1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1231 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1199 } else { 1232 } else {
1200 *txq->axq_link = bf->bf_daddr; 1233 *txq->axq_link = bf->bf_daddr;
1201 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1234 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1202 txq->axq_qnum, txq->axq_link, 1235 txq->axq_qnum, txq->axq_link,
1203 ito64(bf->bf_daddr), bf->bf_desc); 1236 ito64(bf->bf_daddr), bf->bf_desc);
1204 } 1237 }
1205 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); 1238 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1206 ath9k_hw_txstart(ah, txq->axq_qnum); 1239 ath9k_hw_txstart(ah, txq->axq_qnum);
@@ -1320,25 +1353,6 @@ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1320 return htype; 1353 return htype;
1321} 1354}
1322 1355
1323static bool is_pae(struct sk_buff *skb)
1324{
1325 struct ieee80211_hdr *hdr;
1326 __le16 fc;
1327
1328 hdr = (struct ieee80211_hdr *)skb->data;
1329 fc = hdr->frame_control;
1330
1331 if (ieee80211_is_data(fc)) {
1332 if (ieee80211_is_nullfunc(fc) ||
1333 /* Port Access Entity (IEEE 802.1X) */
1334 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1335 return true;
1336 }
1337 }
1338
1339 return false;
1340}
1341
1342static int get_hw_crypto_keytype(struct sk_buff *skb) 1356static int get_hw_crypto_keytype(struct sk_buff *skb)
1343{ 1357{
1344 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1358 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -1381,17 +1395,9 @@ static void assign_aggr_tid_seqno(struct sk_buff *skb,
1381 * For HT capable stations, we save tidno for later use. 1395 * For HT capable stations, we save tidno for later use.
1382 * We also override seqno set by upper layer with the one 1396 * We also override seqno set by upper layer with the one
1383 * in tx aggregation state. 1397 * in tx aggregation state.
1384 *
1385 * If fragmentation is on, the sequence number is
1386 * not overridden, since it has been
1387 * incremented by the fragmentation routine.
1388 *
1389 * FIXME: check if the fragmentation threshold exceeds
1390 * IEEE80211 max.
1391 */ 1398 */
1392 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1399 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1393 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << 1400 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1394 IEEE80211_SEQ_SEQ_SHIFT);
1395 bf->bf_seqno = tid->seq_next; 1401 bf->bf_seqno = tid->seq_next;
1396 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1402 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1397} 1403}
@@ -1420,22 +1426,14 @@ static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1420static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, 1426static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1421 int width, int half_gi, bool shortPreamble) 1427 int width, int half_gi, bool shortPreamble)
1422{ 1428{
1423 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1424 u32 nbits, nsymbits, duration, nsymbols; 1429 u32 nbits, nsymbits, duration, nsymbols;
1425 u8 rc;
1426 int streams, pktlen; 1430 int streams, pktlen;
1427 1431
1428 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; 1432 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1429 rc = rate_table->info[rix].ratecode;
1430
1431 /* for legacy rates, use old function to compute packet duration */
1432 if (!IS_HT_RATE(rc))
1433 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1434 rix, shortPreamble);
1435 1433
1436 /* find number of symbols: PLCP + data */ 1434 /* find number of symbols: PLCP + data */
1437 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1435 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1438 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 1436 nsymbits = bits_per_symbol[rix][width];
1439 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1437 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1440 1438
1441 if (!half_gi) 1439 if (!half_gi)
@@ -1444,7 +1442,7 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1444 duration = SYMBOL_TIME_HALFGI(nsymbols); 1442 duration = SYMBOL_TIME_HALFGI(nsymbols);
1445 1443
1446 /* addup duration for legacy/ht training and signal fields */ 1444 /* addup duration for legacy/ht training and signal fields */
1447 streams = HT_RC_2_STREAMS(rc); 1445 streams = HT_RC_2_STREAMS(rix);
1448 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1446 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1449 1447
1450 return duration; 1448 return duration;
@@ -1452,11 +1450,12 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1452 1450
1453static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) 1451static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1454{ 1452{
1455 const struct ath_rate_table *rt = sc->cur_rate_table; 1453 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1456 struct ath9k_11n_rate_series series[4]; 1454 struct ath9k_11n_rate_series series[4];
1457 struct sk_buff *skb; 1455 struct sk_buff *skb;
1458 struct ieee80211_tx_info *tx_info; 1456 struct ieee80211_tx_info *tx_info;
1459 struct ieee80211_tx_rate *rates; 1457 struct ieee80211_tx_rate *rates;
1458 const struct ieee80211_rate *rate;
1460 struct ieee80211_hdr *hdr; 1459 struct ieee80211_hdr *hdr;
1461 int i, flags = 0; 1460 int i, flags = 0;
1462 u8 rix = 0, ctsrate = 0; 1461 u8 rix = 0, ctsrate = 0;
@@ -1475,59 +1474,76 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1475 * checking the BSS's global flag. 1474 * checking the BSS's global flag.
1476 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 1475 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1477 */ 1476 */
1477 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1478 ctsrate = rate->hw_value;
1478 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 1479 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1479 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | 1480 ctsrate |= rate->hw_value_short;
1480 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1481 else
1482 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1483
1484 /*
1485 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1486 * Check the first rate in the series to decide whether RTS/CTS
1487 * or CTS-to-self has to be used.
1488 */
1489 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1490 flags = ATH9K_TXDESC_CTSENA;
1491 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1492 flags = ATH9K_TXDESC_RTSENA;
1493
1494 /* FIXME: Handle aggregation protection */
1495 if (sc->config.ath_aggr_prot &&
1496 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1497 flags = ATH9K_TXDESC_RTSENA;
1498 }
1499
1500 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1501 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1502 flags &= ~(ATH9K_TXDESC_RTSENA);
1503 1481
1504 for (i = 0; i < 4; i++) { 1482 for (i = 0; i < 4; i++) {
1483 bool is_40, is_sgi, is_sp;
1484 int phy;
1485
1505 if (!rates[i].count || (rates[i].idx < 0)) 1486 if (!rates[i].count || (rates[i].idx < 0))
1506 continue; 1487 continue;
1507 1488
1508 rix = rates[i].idx; 1489 rix = rates[i].idx;
1509 series[i].Tries = rates[i].count; 1490 series[i].Tries = rates[i].count;
1510 series[i].ChSel = sc->tx_chainmask; 1491 series[i].ChSel = common->tx_chainmask;
1511 1492
1512 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1493 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1513 series[i].Rate = rt->info[rix].ratecode | 1494 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1514 rt->info[rix].short_preamble; 1495 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1515 else 1496 flags |= ATH9K_TXDESC_RTSENA;
1516 series[i].Rate = rt->info[rix].ratecode; 1497 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1517
1518 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1519 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1498 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1499 flags |= ATH9K_TXDESC_CTSENA;
1500 }
1501
1520 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1502 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1521 series[i].RateFlags |= ATH9K_RATESERIES_2040; 1503 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1522 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1504 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1523 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1505 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1524 1506
1525 series[i].PktDuration = ath_pkt_duration(sc, rix, bf, 1507 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1526 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, 1508 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1527 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), 1509 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1528 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); 1510
1511 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1512 /* MCS rates */
1513 series[i].Rate = rix | 0x80;
1514 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1515 is_40, is_sgi, is_sp);
1516 continue;
1517 }
1518
1519 /* legcay rates */
1520 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1521 !(rate->flags & IEEE80211_RATE_ERP_G))
1522 phy = WLAN_RC_PHY_CCK;
1523 else
1524 phy = WLAN_RC_PHY_OFDM;
1525
1526 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1527 series[i].Rate = rate->hw_value;
1528 if (rate->hw_value_short) {
1529 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1530 series[i].Rate |= rate->hw_value_short;
1531 } else {
1532 is_sp = false;
1533 }
1534
1535 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1536 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1529 } 1537 }
1530 1538
1539 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1540 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1541 flags &= ~ATH9K_TXDESC_RTSENA;
1542
1543 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1544 if (flags & ATH9K_TXDESC_RTSENA)
1545 flags &= ~ATH9K_TXDESC_CTSENA;
1546
1531 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1547 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1532 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 1548 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1533 bf->bf_lastbf->bf_desc, 1549 bf->bf_lastbf->bf_desc,
@@ -1546,24 +1562,36 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1546 struct ath_softc *sc = aphy->sc; 1562 struct ath_softc *sc = aphy->sc;
1547 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1563 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1564 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1549 struct ath_tx_info_priv *tx_info_priv;
1550 int hdrlen; 1565 int hdrlen;
1551 __le16 fc; 1566 __le16 fc;
1567 int padpos, padsize;
1552 1568
1553 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); 1569 tx_info->pad[0] = 0;
1554 if (unlikely(!tx_info_priv)) 1570 switch (txctl->frame_type) {
1555 return -ENOMEM; 1571 case ATH9K_NOT_INTERNAL:
1556 tx_info->rate_driver_data[0] = tx_info_priv; 1572 break;
1557 tx_info_priv->aphy = aphy; 1573 case ATH9K_INT_PAUSE:
1558 tx_info_priv->frame_type = txctl->frame_type; 1574 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1575 /* fall through */
1576 case ATH9K_INT_UNPAUSE:
1577 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1578 break;
1579 }
1559 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1580 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1560 fc = hdr->frame_control; 1581 fc = hdr->frame_control;
1561 1582
1562 ATH_TXBUF_RESET(bf); 1583 ATH_TXBUF_RESET(bf);
1563 1584
1564 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); 1585 bf->aphy = aphy;
1586 bf->bf_frmlen = skb->len + FCS_LEN;
1587 /* Remove the padding size from bf_frmlen, if any */
1588 padpos = ath9k_cmn_padpos(hdr->frame_control);
1589 padsize = padpos & 3;
1590 if (padsize && skb->len>padpos+padsize) {
1591 bf->bf_frmlen -= padsize;
1592 }
1565 1593
1566 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) 1594 if (conf_is_ht(&hw->conf))
1567 bf->bf_state.bf_type |= BUF_HT; 1595 bf->bf_state.bf_type |= BUF_HT;
1568 1596
1569 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); 1597 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
@@ -1576,7 +1604,8 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1576 bf->bf_keyix = ATH9K_TXKEYIX_INVALID; 1604 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1577 } 1605 }
1578 1606
1579 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) 1607 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1608 (sc->sc_flags & SC_OP_TXAGGR))
1580 assign_aggr_tid_seqno(skb, bf); 1609 assign_aggr_tid_seqno(skb, bf);
1581 1610
1582 bf->bf_mpdu = skb; 1611 bf->bf_mpdu = skb;
@@ -1585,13 +1614,20 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1585 skb->len, DMA_TO_DEVICE); 1614 skb->len, DMA_TO_DEVICE);
1586 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { 1615 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1587 bf->bf_mpdu = NULL; 1616 bf->bf_mpdu = NULL;
1588 kfree(tx_info_priv); 1617 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1589 tx_info->rate_driver_data[0] = NULL; 1618 "dma_mapping_error() on TX\n");
1590 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1591 return -ENOMEM; 1619 return -ENOMEM;
1592 } 1620 }
1593 1621
1594 bf->bf_buf_addr = bf->bf_dmacontext; 1622 bf->bf_buf_addr = bf->bf_dmacontext;
1623
1624 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1625 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1626 bf->bf_isnullfunc = true;
1627 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1628 } else
1629 bf->bf_isnullfunc = false;
1630
1595 return 0; 1631 return 0;
1596} 1632}
1597 1633
@@ -1669,12 +1705,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1669{ 1705{
1670 struct ath_wiphy *aphy = hw->priv; 1706 struct ath_wiphy *aphy = hw->priv;
1671 struct ath_softc *sc = aphy->sc; 1707 struct ath_softc *sc = aphy->sc;
1708 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1672 struct ath_buf *bf; 1709 struct ath_buf *bf;
1673 int r; 1710 int r;
1674 1711
1675 bf = ath_tx_get_buffer(sc); 1712 bf = ath_tx_get_buffer(sc);
1676 if (!bf) { 1713 if (!bf) {
1677 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); 1714 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1678 return -1; 1715 return -1;
1679 } 1716 }
1680 1717
@@ -1682,7 +1719,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1682 if (unlikely(r)) { 1719 if (unlikely(r)) {
1683 struct ath_txq *txq = txctl->txq; 1720 struct ath_txq *txq = txctl->txq;
1684 1721
1685 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1722 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1686 1723
1687 /* upon ath_tx_processq() this TX queue will be resumed, we 1724 /* upon ath_tx_processq() this TX queue will be resumed, we
1688 * guarantee this will happen by knowing beforehand that 1725 * guarantee this will happen by knowing beforehand that
@@ -1690,8 +1727,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1690 * on the queue */ 1727 * on the queue */
1691 spin_lock_bh(&txq->axq_lock); 1728 spin_lock_bh(&txq->axq_lock);
1692 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { 1729 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1693 ieee80211_stop_queue(sc->hw, 1730 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1694 skb_get_queue_mapping(skb));
1695 txq->stopped = 1; 1731 txq->stopped = 1;
1696 } 1732 }
1697 spin_unlock_bh(&txq->axq_lock); 1733 spin_unlock_bh(&txq->axq_lock);
@@ -1712,7 +1748,9 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1712{ 1748{
1713 struct ath_wiphy *aphy = hw->priv; 1749 struct ath_wiphy *aphy = hw->priv;
1714 struct ath_softc *sc = aphy->sc; 1750 struct ath_softc *sc = aphy->sc;
1715 int hdrlen, padsize; 1751 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1752 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1753 int padpos, padsize;
1716 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1754 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1717 struct ath_tx_control txctl; 1755 struct ath_tx_control txctl;
1718 1756
@@ -1724,7 +1762,6 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1724 * BSSes. 1762 * BSSes.
1725 */ 1763 */
1726 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1764 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1727 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1728 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1765 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1729 sc->tx.seq_no += 0x10; 1766 sc->tx.seq_no += 0x10;
1730 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1767 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
@@ -1732,24 +1769,26 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1732 } 1769 }
1733 1770
1734 /* Add the padding after the header if this is not already done */ 1771 /* Add the padding after the header if this is not already done */
1735 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1772 padpos = ath9k_cmn_padpos(hdr->frame_control);
1736 if (hdrlen & 3) { 1773 padsize = padpos & 3;
1737 padsize = hdrlen % 4; 1774 if (padsize && skb->len>padpos) {
1738 if (skb_headroom(skb) < padsize) { 1775 if (skb_headroom(skb) < padsize) {
1739 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); 1776 ath_print(common, ATH_DBG_XMIT,
1777 "TX CABQ padding failed\n");
1740 dev_kfree_skb_any(skb); 1778 dev_kfree_skb_any(skb);
1741 return; 1779 return;
1742 } 1780 }
1743 skb_push(skb, padsize); 1781 skb_push(skb, padsize);
1744 memmove(skb->data, skb->data + padsize, hdrlen); 1782 memmove(skb->data, skb->data + padsize, padpos);
1745 } 1783 }
1746 1784
1747 txctl.txq = sc->beacon.cabq; 1785 txctl.txq = sc->beacon.cabq;
1748 1786
1749 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1787 ath_print(common, ATH_DBG_XMIT,
1788 "transmitting CABQ packet, skb: %p\n", skb);
1750 1789
1751 if (ath_tx_start(hw, skb, &txctl) != 0) { 1790 if (ath_tx_start(hw, skb, &txctl) != 0) {
1752 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); 1791 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1753 goto exit; 1792 goto exit;
1754 } 1793 }
1755 1794
@@ -1763,26 +1802,18 @@ exit:
1763/*****************/ 1802/*****************/
1764 1803
1765static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1804static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1766 int tx_flags) 1805 struct ath_wiphy *aphy, int tx_flags)
1767{ 1806{
1768 struct ieee80211_hw *hw = sc->hw; 1807 struct ieee80211_hw *hw = sc->hw;
1769 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1808 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1770 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1809 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1771 int hdrlen, padsize; 1810 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1772 int frame_type = ATH9K_NOT_INTERNAL; 1811 int padpos, padsize;
1773 1812
1774 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1813 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1775
1776 if (tx_info_priv) {
1777 hw = tx_info_priv->aphy->hw;
1778 frame_type = tx_info_priv->frame_type;
1779 }
1780 1814
1781 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || 1815 if (aphy)
1782 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { 1816 hw = aphy->hw;
1783 kfree(tx_info_priv);
1784 tx_info->rate_driver_data[0] = NULL;
1785 }
1786 1817
1787 if (tx_flags & ATH_TX_BAR) 1818 if (tx_flags & ATH_TX_BAR)
1788 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1819 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
@@ -1792,31 +1823,32 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1792 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1823 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1793 } 1824 }
1794 1825
1795 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1826 padpos = ath9k_cmn_padpos(hdr->frame_control);
1796 padsize = hdrlen & 3; 1827 padsize = padpos & 3;
1797 if (padsize && hdrlen >= 24) { 1828 if (padsize && skb->len>padpos+padsize) {
1798 /* 1829 /*
1799 * Remove MAC header padding before giving the frame back to 1830 * Remove MAC header padding before giving the frame back to
1800 * mac80211. 1831 * mac80211.
1801 */ 1832 */
1802 memmove(skb->data + padsize, skb->data, hdrlen); 1833 memmove(skb->data + padsize, skb->data, padpos);
1803 skb_pull(skb, padsize); 1834 skb_pull(skb, padsize);
1804 } 1835 }
1805 1836
1806 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1837 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1807 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1838 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1808 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 1839 ath_print(common, ATH_DBG_PS,
1809 "received TX status (0x%x)\n", 1840 "Going back to sleep after having "
1810 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1841 "received TX status (0x%lx)\n",
1811 SC_OP_WAIT_FOR_CAB | 1842 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1812 SC_OP_WAIT_FOR_PSPOLL_DATA | 1843 PS_WAIT_FOR_CAB |
1813 SC_OP_WAIT_FOR_TX_ACK)); 1844 PS_WAIT_FOR_PSPOLL_DATA |
1845 PS_WAIT_FOR_TX_ACK));
1814 } 1846 }
1815 1847
1816 if (frame_type == ATH9K_NOT_INTERNAL) 1848 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1817 ieee80211_tx_status(hw, skb);
1818 else
1819 ath9k_tx_status(hw, skb); 1849 ath9k_tx_status(hw, skb);
1850 else
1851 ieee80211_tx_status(hw, skb);
1820} 1852}
1821 1853
1822static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 1854static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
@@ -1839,7 +1871,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1839 } 1871 }
1840 1872
1841 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); 1873 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1842 ath_tx_complete(sc, skb, tx_flags); 1874 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1843 ath_debug_stat_tx(sc, txq, bf); 1875 ath_debug_stat_tx(sc, txq, bf);
1844 1876
1845 /* 1877 /*
@@ -1887,8 +1919,7 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1887 struct sk_buff *skb = bf->bf_mpdu; 1919 struct sk_buff *skb = bf->bf_mpdu;
1888 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1920 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1889 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1921 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1890 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1922 struct ieee80211_hw *hw = bf->aphy->hw;
1891 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1892 u8 i, tx_rateindex; 1923 u8 i, tx_rateindex;
1893 1924
1894 if (txok) 1925 if (txok)
@@ -1897,22 +1928,29 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1897 tx_rateindex = ds->ds_txstat.ts_rateindex; 1928 tx_rateindex = ds->ds_txstat.ts_rateindex;
1898 WARN_ON(tx_rateindex >= hw->max_rates); 1929 WARN_ON(tx_rateindex >= hw->max_rates);
1899 1930
1900 tx_info_priv->update_rc = update_rc; 1931 if (update_rc)
1932 tx_info->pad[0] |= ATH_TX_INFO_UPDATE_RC;
1901 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) 1933 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1902 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1934 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1903 1935
1904 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && 1936 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1905 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1937 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1906 if (ieee80211_is_data(hdr->frame_control)) { 1938 if (ieee80211_is_data(hdr->frame_control)) {
1907 memcpy(&tx_info_priv->tx, &ds->ds_txstat, 1939 if (ds->ds_txstat.ts_flags &
1908 sizeof(tx_info_priv->tx)); 1940 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
1909 tx_info_priv->n_frames = bf->bf_nframes; 1941 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
1910 tx_info_priv->n_bad_frames = nbad; 1942 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) ||
1943 (ds->ds_txstat.ts_status & ATH9K_TXERR_FIFO))
1944 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
1945 tx_info->status.ampdu_len = bf->bf_nframes;
1946 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
1911 } 1947 }
1912 } 1948 }
1913 1949
1914 for (i = tx_rateindex + 1; i < hw->max_rates; i++) 1950 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1915 tx_info->status.rates[i].count = 0; 1951 tx_info->status.rates[i].count = 0;
1952 tx_info->status.rates[i].idx = -1;
1953 }
1916 1954
1917 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; 1955 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1918} 1956}
@@ -1926,7 +1964,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1926 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { 1964 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1927 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); 1965 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1928 if (qnum != -1) { 1966 if (qnum != -1) {
1929 ieee80211_wake_queue(sc->hw, qnum); 1967 ath_mac80211_start_queue(sc, qnum);
1930 txq->stopped = 0; 1968 txq->stopped = 0;
1931 } 1969 }
1932 } 1970 }
@@ -1936,21 +1974,21 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1936static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1974static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1937{ 1975{
1938 struct ath_hw *ah = sc->sc_ah; 1976 struct ath_hw *ah = sc->sc_ah;
1977 struct ath_common *common = ath9k_hw_common(ah);
1939 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1978 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1940 struct list_head bf_head; 1979 struct list_head bf_head;
1941 struct ath_desc *ds; 1980 struct ath_desc *ds;
1942 int txok; 1981 int txok;
1943 int status; 1982 int status;
1944 1983
1945 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1984 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1946 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1985 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1947 txq->axq_link); 1986 txq->axq_link);
1948 1987
1949 for (;;) { 1988 for (;;) {
1950 spin_lock_bh(&txq->axq_lock); 1989 spin_lock_bh(&txq->axq_lock);
1951 if (list_empty(&txq->axq_q)) { 1990 if (list_empty(&txq->axq_q)) {
1952 txq->axq_link = NULL; 1991 txq->axq_link = NULL;
1953 txq->axq_linkbuf = NULL;
1954 spin_unlock_bh(&txq->axq_lock); 1992 spin_unlock_bh(&txq->axq_lock);
1955 break; 1993 break;
1956 } 1994 }
@@ -1984,10 +2022,18 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1984 spin_unlock_bh(&txq->axq_lock); 2022 spin_unlock_bh(&txq->axq_lock);
1985 break; 2023 break;
1986 } 2024 }
1987 if (bf->bf_desc == txq->axq_lastdsWithCTS) 2025
1988 txq->axq_lastdsWithCTS = NULL; 2026 /*
1989 if (ds == txq->axq_gatingds) 2027 * We now know the nullfunc frame has been ACKed so we
1990 txq->axq_gatingds = NULL; 2028 * can disable RX.
2029 */
2030 if (bf->bf_isnullfunc &&
2031 (ds->ds_txstat.ts_status & ATH9K_TX_ACKED)) {
2032 if ((sc->ps_flags & PS_ENABLED))
2033 ath9k_enable_ps(sc);
2034 else
2035 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2036 }
1991 2037
1992 /* 2038 /*
1993 * Remove ath_buf's of the same transmit unit from txq, 2039 * Remove ath_buf's of the same transmit unit from txq,
@@ -2001,10 +2047,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2001 &txq->axq_q, lastbf->list.prev); 2047 &txq->axq_q, lastbf->list.prev);
2002 2048
2003 txq->axq_depth--; 2049 txq->axq_depth--;
2004 if (bf_isaggr(bf)) 2050 txok = !(ds->ds_txstat.ts_status & ATH9K_TXERR_MASK);
2005 txq->axq_aggr_depth--;
2006
2007 txok = (ds->ds_txstat.ts_status == 0);
2008 txq->axq_tx_inprogress = false; 2051 txq->axq_tx_inprogress = false;
2009 spin_unlock_bh(&txq->axq_lock); 2052 spin_unlock_bh(&txq->axq_lock);
2010 2053
@@ -2064,8 +2107,11 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2064 } 2107 }
2065 2108
2066 if (needreset) { 2109 if (needreset) {
2067 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n"); 2110 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2111 "tx hung, resetting the chip\n");
2112 ath9k_ps_wakeup(sc);
2068 ath_reset(sc, false); 2113 ath_reset(sc, false);
2114 ath9k_ps_restore(sc);
2069 } 2115 }
2070 2116
2071 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2117 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2093,6 +2139,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
2093 2139
2094int ath_tx_init(struct ath_softc *sc, int nbufs) 2140int ath_tx_init(struct ath_softc *sc, int nbufs)
2095{ 2141{
2142 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2096 int error = 0; 2143 int error = 0;
2097 2144
2098 spin_lock_init(&sc->tx.txbuflock); 2145 spin_lock_init(&sc->tx.txbuflock);
@@ -2100,16 +2147,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2100 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2147 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2101 "tx", nbufs, 1); 2148 "tx", nbufs, 1);
2102 if (error != 0) { 2149 if (error != 0) {
2103 DPRINTF(sc, ATH_DBG_FATAL, 2150 ath_print(common, ATH_DBG_FATAL,
2104 "Failed to allocate tx descriptors: %d\n", error); 2151 "Failed to allocate tx descriptors: %d\n", error);
2105 goto err; 2152 goto err;
2106 } 2153 }
2107 2154
2108 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2155 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2109 "beacon", ATH_BCBUF, 1); 2156 "beacon", ATH_BCBUF, 1);
2110 if (error != 0) { 2157 if (error != 0) {
2111 DPRINTF(sc, ATH_DBG_FATAL, 2158 ath_print(common, ATH_DBG_FATAL,
2112 "Failed to allocate beacon descriptors: %d\n", error); 2159 "Failed to allocate beacon descriptors: %d\n", error);
2113 goto err; 2160 goto err;
2114 } 2161 }
2115 2162
@@ -2192,7 +2239,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2192 if (ATH_TXQ_SETUP(sc, i)) { 2239 if (ATH_TXQ_SETUP(sc, i)) {
2193 txq = &sc->tx.txq[i]; 2240 txq = &sc->tx.txq[i];
2194 2241
2195 spin_lock(&txq->axq_lock); 2242 spin_lock_bh(&txq->axq_lock);
2196 2243
2197 list_for_each_entry_safe(ac, 2244 list_for_each_entry_safe(ac,
2198 ac_tmp, &txq->axq_acq, list) { 2245 ac_tmp, &txq->axq_acq, list) {
@@ -2213,7 +2260,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2213 } 2260 }
2214 } 2261 }
2215 2262
2216 spin_unlock(&txq->axq_lock); 2263 spin_unlock_bh(&txq->axq_lock);
2217 } 2264 }
2218 } 2265 }
2219} 2266}