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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c52
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c54
-rw-r--r--drivers/gpu/drm/radeon/atombios_i2c.c2
-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.c20
-rw-r--r--drivers/gpu/drm/radeon/ci_dpm.c70
-rw-r--r--drivers/gpu/drm/radeon/ci_smc.c1
-rw-r--r--drivers/gpu/drm/radeon/cik.c369
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c120
-rw-r--r--drivers/gpu/drm/radeon/cikd.h11
-rw-r--r--drivers/gpu/drm/radeon/cypress_dpm.c15
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c99
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c5
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/kv_dpm.c48
-rw-r--r--drivers/gpu/drm/radeon/ni.c141
-rw-r--r--drivers/gpu/drm/radeon/ni_dma.c77
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c21
-rw-r--r--drivers/gpu/drm/radeon/nid.h1
-rw-r--r--drivers/gpu/drm/radeon/pptable.h4
-rw-r--r--drivers/gpu/drm/radeon/r100.c38
-rw-r--r--drivers/gpu/drm/radeon/r300.c7
-rw-r--r--drivers/gpu/drm/radeon/r300_cmdbuf.c8
-rw-r--r--drivers/gpu/drm/radeon/r420.c7
-rw-r--r--drivers/gpu/drm/radeon/r520.c5
-rw-r--r--drivers/gpu/drm/radeon/r600.c166
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c4
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c7
-rw-r--r--drivers/gpu/drm/radeon/r600_dma.c19
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c20
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.h2
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c2
-rw-r--r--drivers/gpu/drm/radeon/r600d.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon.h19
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c85
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h64
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c46
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c46
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c24
-rw-r--r--drivers/gpu/drm/radeon/radeon_mem.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h36
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c158
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c94
-rw-r--r--drivers/gpu/drm/radeon/radeon_sa.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_trace.h21
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c197
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c3
-rw-r--r--drivers/gpu/drm/radeon/rs400.c7
-rw-r--r--drivers/gpu/drm/radeon/rs600.c7
-rw-r--r--drivers/gpu/drm/radeon/rs690.c7
-rw-r--r--drivers/gpu/drm/radeon/rs780_dpm.c8
-rw-r--r--drivers/gpu/drm/radeon/rv515.c7
-rw-r--r--drivers/gpu/drm/radeon/rv6xx_dpm.c10
-rw-r--r--drivers/gpu/drm/radeon/rv770.c58
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c35
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.h4
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h7
-rw-r--r--drivers/gpu/drm/radeon/si.c163
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c69
-rw-r--r--drivers/gpu/drm/radeon/si_smc.c1
-rw-r--r--drivers/gpu/drm/radeon/sid.h9
-rw-r--r--drivers/gpu/drm/radeon/sislands_smc.h2
-rw-r--r--drivers/gpu/drm/radeon/sumo_dpm.c21
-rw-r--r--drivers/gpu/drm/radeon/sumo_smc.c1
-rw-r--r--drivers/gpu/drm/radeon/trinity_dpm.c21
-rw-r--r--drivers/gpu/drm/radeon/trinity_smc.c3
-rw-r--r--drivers/gpu/drm/radeon/uvd_v2_2.c1
82 files changed, 1944 insertions, 843 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 0b9621c9aeea..a9338c85630f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -209,6 +209,16 @@ static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210} 210}
211 211
212static const u32 vga_control_regs[6] =
213{
214 AVIVO_D1VGA_CONTROL,
215 AVIVO_D2VGA_CONTROL,
216 EVERGREEN_D3VGA_CONTROL,
217 EVERGREEN_D4VGA_CONTROL,
218 EVERGREEN_D5VGA_CONTROL,
219 EVERGREEN_D6VGA_CONTROL,
220};
221
212static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 222static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
213{ 223{
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -216,13 +226,23 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
216 struct radeon_device *rdev = dev->dev_private; 226 struct radeon_device *rdev = dev->dev_private;
217 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 227 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
218 BLANK_CRTC_PS_ALLOCATION args; 228 BLANK_CRTC_PS_ALLOCATION args;
229 u32 vga_control = 0;
219 230
220 memset(&args, 0, sizeof(args)); 231 memset(&args, 0, sizeof(args));
221 232
233 if (ASIC_IS_DCE8(rdev)) {
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
236 }
237
222 args.ucCRTC = radeon_crtc->crtc_id; 238 args.ucCRTC = radeon_crtc->crtc_id;
223 args.ucBlanking = state; 239 args.ucBlanking = state;
224 240
225 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
242
243 if (ASIC_IS_DCE8(rdev)) {
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
245 }
226} 246}
227 247
228static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 248static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
@@ -423,7 +443,17 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
423 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 443 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
424 union atom_enable_ss args; 444 union atom_enable_ss args;
425 445
426 if (!enable) { 446 if (enable) {
447 /* Don't mess with SS if percentage is 0 or external ss.
448 * SS is already disabled previously, and disabling it
449 * again can cause display problems if the pll is already
450 * programmed.
451 */
452 if (ss->percentage == 0)
453 return;
454 if (ss->type & ATOM_EXTERNAL_SS_MASK)
455 return;
456 } else {
427 for (i = 0; i < rdev->num_crtc; i++) { 457 for (i = 0; i < rdev->num_crtc; i++) {
428 if (rdev->mode_info.crtcs[i] && 458 if (rdev->mode_info.crtcs[i] &&
429 rdev->mode_info.crtcs[i]->enabled && 459 rdev->mode_info.crtcs[i]->enabled &&
@@ -459,8 +489,6 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
459 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 489 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
460 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 490 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
461 args.v3.ucEnable = enable; 491 args.v3.ucEnable = enable;
462 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
463 args.v3.ucEnable = ATOM_DISABLE;
464 } else if (ASIC_IS_DCE4(rdev)) { 492 } else if (ASIC_IS_DCE4(rdev)) {
465 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 493 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
466 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 494 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
@@ -480,8 +508,6 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
480 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 508 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
481 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 509 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
482 args.v2.ucEnable = enable; 510 args.v2.ucEnable = enable;
483 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
484 args.v2.ucEnable = ATOM_DISABLE;
485 } else if (ASIC_IS_DCE3(rdev)) { 511 } else if (ASIC_IS_DCE3(rdev)) {
486 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 512 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
487 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 513 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
@@ -503,8 +529,7 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
503 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 529 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
504 args.lvds_ss_2.ucEnable = enable; 530 args.lvds_ss_2.ucEnable = enable;
505 } else { 531 } else {
506 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 532 if (enable == ATOM_DISABLE) {
507 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
508 atombios_disable_ss(rdev, pll_id); 533 atombios_disable_ss(rdev, pll_id);
509 return; 534 return;
510 } 535 }
@@ -938,11 +963,14 @@ static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_
938 radeon_atombios_get_ppll_ss_info(rdev, 963 radeon_atombios_get_ppll_ss_info(rdev,
939 &radeon_crtc->ss, 964 &radeon_crtc->ss,
940 ATOM_DP_SS_ID1); 965 ATOM_DP_SS_ID1);
941 } else 966 } else {
942 radeon_crtc->ss_enabled = 967 radeon_crtc->ss_enabled =
943 radeon_atombios_get_ppll_ss_info(rdev, 968 radeon_atombios_get_ppll_ss_info(rdev,
944 &radeon_crtc->ss, 969 &radeon_crtc->ss,
945 ATOM_DP_SS_ID1); 970 ATOM_DP_SS_ID1);
971 }
972 /* disable spread spectrum on DCE3 DP */
973 radeon_crtc->ss_enabled = false;
946 } 974 }
947 break; 975 break;
948 case ATOM_ENCODER_MODE_LVDS: 976 case ATOM_ENCODER_MODE_LVDS:
@@ -1039,15 +1067,17 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1039 /* calculate ss amount and step size */ 1067 /* calculate ss amount and step size */
1040 if (ASIC_IS_DCE4(rdev)) { 1068 if (ASIC_IS_DCE4(rdev)) {
1041 u32 step_size; 1069 u32 step_size;
1042 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 1070 u32 amount = (((fb_div * 10) + frac_fb_div) *
1071 (u32)radeon_crtc->ss.percentage) /
1072 (100 * (u32)radeon_crtc->ss.percentage_divider);
1043 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1073 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1044 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1074 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1045 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1075 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1046 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1076 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1047 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1077 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1048 (125 * 25 * pll->reference_freq / 100); 1078 (125 * 25 * pll->reference_freq / 100);
1049 else 1079 else
1050 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1080 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1051 (125 * 25 * pll->reference_freq / 100); 1081 (125 * 25 * pll->reference_freq / 100);
1052 radeon_crtc->ss.step = step_size; 1082 radeon_crtc->ss.step = step_size;
1053 } 1083 }
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index fb3ae07a1469..4ad7643fce5f 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -157,21 +157,22 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
157 157
158 msg[0] = address; 158 msg[0] = address;
159 msg[1] = address >> 8; 159 msg[1] = address >> 8;
160 msg[2] = AUX_NATIVE_WRITE << 4; 160 msg[2] = DP_AUX_NATIVE_WRITE << 4;
161 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 161 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
162 memcpy(&msg[4], send, send_bytes); 162 memcpy(&msg[4], send, send_bytes);
163 163
164 for (retry = 0; retry < 4; retry++) { 164 for (retry = 0; retry < 7; retry++) {
165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
166 msg, msg_bytes, NULL, 0, delay, &ack); 166 msg, msg_bytes, NULL, 0, delay, &ack);
167 if (ret == -EBUSY) 167 if (ret == -EBUSY)
168 continue; 168 continue;
169 else if (ret < 0) 169 else if (ret < 0)
170 return ret; 170 return ret;
171 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 171 ack >>= 4;
172 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
172 return send_bytes; 173 return send_bytes;
173 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 174 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
174 udelay(400); 175 usleep_range(400, 500);
175 else 176 else
176 return -EIO; 177 return -EIO;
177 } 178 }
@@ -191,20 +192,21 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
191 192
192 msg[0] = address; 193 msg[0] = address;
193 msg[1] = address >> 8; 194 msg[1] = address >> 8;
194 msg[2] = AUX_NATIVE_READ << 4; 195 msg[2] = DP_AUX_NATIVE_READ << 4;
195 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 196 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
196 197
197 for (retry = 0; retry < 4; retry++) { 198 for (retry = 0; retry < 7; retry++) {
198 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 199 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
199 msg, msg_bytes, recv, recv_bytes, delay, &ack); 200 msg, msg_bytes, recv, recv_bytes, delay, &ack);
200 if (ret == -EBUSY) 201 if (ret == -EBUSY)
201 continue; 202 continue;
202 else if (ret < 0) 203 else if (ret < 0)
203 return ret; 204 return ret;
204 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 205 ack >>= 4;
206 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
205 return ret; 207 return ret;
206 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 208 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
207 udelay(400); 209 usleep_range(400, 500);
208 else if (ret == 0) 210 else if (ret == 0)
209 return -EPROTO; 211 return -EPROTO;
210 else 212 else
@@ -246,12 +248,12 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
246 248
247 /* Set up the command byte */ 249 /* Set up the command byte */
248 if (mode & MODE_I2C_READ) 250 if (mode & MODE_I2C_READ)
249 msg[2] = AUX_I2C_READ << 4; 251 msg[2] = DP_AUX_I2C_READ << 4;
250 else 252 else
251 msg[2] = AUX_I2C_WRITE << 4; 253 msg[2] = DP_AUX_I2C_WRITE << 4;
252 254
253 if (!(mode & MODE_I2C_STOP)) 255 if (!(mode & MODE_I2C_STOP))
254 msg[2] |= AUX_I2C_MOT << 4; 256 msg[2] |= DP_AUX_I2C_MOT << 4;
255 257
256 msg[0] = address; 258 msg[0] = address;
257 msg[1] = address >> 8; 259 msg[1] = address >> 8;
@@ -272,7 +274,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
272 break; 274 break;
273 } 275 }
274 276
275 for (retry = 0; retry < 4; retry++) { 277 for (retry = 0; retry < 7; retry++) {
276 ret = radeon_process_aux_ch(auxch, 278 ret = radeon_process_aux_ch(auxch,
277 msg, msg_bytes, reply, reply_bytes, 0, &ack); 279 msg, msg_bytes, reply, reply_bytes, 0, &ack);
278 if (ret == -EBUSY) 280 if (ret == -EBUSY)
@@ -282,35 +284,35 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
282 return ret; 284 return ret;
283 } 285 }
284 286
285 switch (ack & AUX_NATIVE_REPLY_MASK) { 287 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
286 case AUX_NATIVE_REPLY_ACK: 288 case DP_AUX_NATIVE_REPLY_ACK:
287 /* I2C-over-AUX Reply field is only valid 289 /* I2C-over-AUX Reply field is only valid
288 * when paired with AUX ACK. 290 * when paired with AUX ACK.
289 */ 291 */
290 break; 292 break;
291 case AUX_NATIVE_REPLY_NACK: 293 case DP_AUX_NATIVE_REPLY_NACK:
292 DRM_DEBUG_KMS("aux_ch native nack\n"); 294 DRM_DEBUG_KMS("aux_ch native nack\n");
293 return -EREMOTEIO; 295 return -EREMOTEIO;
294 case AUX_NATIVE_REPLY_DEFER: 296 case DP_AUX_NATIVE_REPLY_DEFER:
295 DRM_DEBUG_KMS("aux_ch native defer\n"); 297 DRM_DEBUG_KMS("aux_ch native defer\n");
296 udelay(400); 298 usleep_range(500, 600);
297 continue; 299 continue;
298 default: 300 default:
299 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); 301 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
300 return -EREMOTEIO; 302 return -EREMOTEIO;
301 } 303 }
302 304
303 switch (ack & AUX_I2C_REPLY_MASK) { 305 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
304 case AUX_I2C_REPLY_ACK: 306 case DP_AUX_I2C_REPLY_ACK:
305 if (mode == MODE_I2C_READ) 307 if (mode == MODE_I2C_READ)
306 *read_byte = reply[0]; 308 *read_byte = reply[0];
307 return ret; 309 return ret;
308 case AUX_I2C_REPLY_NACK: 310 case DP_AUX_I2C_REPLY_NACK:
309 DRM_DEBUG_KMS("aux_i2c nack\n"); 311 DRM_DEBUG_KMS("aux_i2c nack\n");
310 return -EREMOTEIO; 312 return -EREMOTEIO;
311 case AUX_I2C_REPLY_DEFER: 313 case DP_AUX_I2C_REPLY_DEFER:
312 DRM_DEBUG_KMS("aux_i2c defer\n"); 314 DRM_DEBUG_KMS("aux_i2c defer\n");
313 udelay(400); 315 usleep_range(400, 500);
314 break; 316 break;
315 default: 317 default:
316 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); 318 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
@@ -671,9 +673,11 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
671 u8 tmp; 673 u8 tmp;
672 674
673 /* power up the sink */ 675 /* power up the sink */
674 if (dp_info->dpcd[0] >= 0x11) 676 if (dp_info->dpcd[0] >= 0x11) {
675 radeon_write_dpcd_reg(dp_info->radeon_connector, 677 radeon_write_dpcd_reg(dp_info->radeon_connector,
676 DP_SET_POWER, DP_SET_POWER_D0); 678 DP_SET_POWER, DP_SET_POWER_D0);
679 usleep_range(1000, 2000);
680 }
677 681
678 /* possibly enable downspread on the sink */ 682 /* possibly enable downspread on the sink */
679 if (dp_info->dpcd[3] & 0x1) 683 if (dp_info->dpcd[3] & 0x1)
diff --git a/drivers/gpu/drm/radeon/atombios_i2c.c b/drivers/gpu/drm/radeon/atombios_i2c.c
index f685035dbe39..b5162c3b6111 100644
--- a/drivers/gpu/drm/radeon/atombios_i2c.c
+++ b/drivers/gpu/drm/radeon/atombios_i2c.c
@@ -27,8 +27,6 @@
27#include "radeon.h" 27#include "radeon.h"
28#include "atom.h" 28#include "atom.h"
29 29
30extern void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
31
32#define TARGET_HW_I2C_CLOCK 50 30#define TARGET_HW_I2C_CLOCK 50
33 31
34/* these are a limitation of ProcessI2cChannelTransaction not the hw */ 32/* these are a limitation of ProcessI2cChannelTransaction not the hw */
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 9b6950d9b3c0..0fbd36f3d4e9 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -49,6 +49,7 @@ struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
49struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 49struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
50struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 50struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
51 51
52extern int ni_mc_load_microcode(struct radeon_device *rdev);
52 53
53//********* BARTS **************// 54//********* BARTS **************//
54static const u32 barts_cgcg_cgls_default[] = 55static const u32 barts_cgcg_cgls_default[] =
@@ -2510,21 +2511,6 @@ int btc_dpm_enable(struct radeon_device *rdev)
2510 if (eg_pi->ls_clock_gating) 2511 if (eg_pi->ls_clock_gating)
2511 btc_ls_clock_gating_enable(rdev, true); 2512 btc_ls_clock_gating_enable(rdev, true);
2512 2513
2513 if (rdev->irq.installed &&
2514 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2515 PPSMC_Result result;
2516
2517 ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
2518 if (ret)
2519 return ret;
2520 rdev->irq.dpm_thermal = true;
2521 radeon_irq_set(rdev);
2522 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
2523
2524 if (result != PPSMC_Result_OK)
2525 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
2526 }
2527
2528 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 2514 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
2529 2515
2530 btc_init_stutter_mode(rdev); 2516 btc_init_stutter_mode(rdev);
@@ -2576,7 +2562,11 @@ void btc_dpm_disable(struct radeon_device *rdev)
2576void btc_dpm_setup_asic(struct radeon_device *rdev) 2562void btc_dpm_setup_asic(struct radeon_device *rdev)
2577{ 2563{
2578 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2564 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2565 int r;
2579 2566
2567 r = ni_mc_load_microcode(rdev);
2568 if (r)
2569 DRM_ERROR("Failed to load MC firmware!\n");
2580 rv770_get_memory_type(rdev); 2570 rv770_get_memory_type(rdev);
2581 rv740_read_clock_registers(rdev); 2571 rv740_read_clock_registers(rdev);
2582 btc_read_arb_registers(rdev); 2572 btc_read_arb_registers(rdev);
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 1ed479976358..8d49104ca6c2 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -171,8 +171,7 @@ extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 struct atom_voltage_table *voltage_table); 171 struct atom_voltage_table *voltage_table);
172extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev); 172extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
173extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev); 173extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
174extern void cik_update_cg(struct radeon_device *rdev, 174extern int ci_mc_load_microcode(struct radeon_device *rdev);
175 u32 block, bool enable);
176 175
177static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, 176static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
178 struct atom_voltage_table_entry *voltage_table, 177 struct atom_voltage_table_entry *voltage_table,
@@ -4503,8 +4502,8 @@ static void ci_get_memory_type(struct radeon_device *rdev)
4503 4502
4504} 4503}
4505 4504
4506void ci_update_current_ps(struct radeon_device *rdev, 4505static void ci_update_current_ps(struct radeon_device *rdev,
4507 struct radeon_ps *rps) 4506 struct radeon_ps *rps)
4508{ 4507{
4509 struct ci_ps *new_ps = ci_get_ps(rps); 4508 struct ci_ps *new_ps = ci_get_ps(rps);
4510 struct ci_power_info *pi = ci_get_pi(rdev); 4509 struct ci_power_info *pi = ci_get_pi(rdev);
@@ -4514,8 +4513,8 @@ void ci_update_current_ps(struct radeon_device *rdev,
4514 pi->current_rps.ps_priv = &pi->current_ps; 4513 pi->current_rps.ps_priv = &pi->current_ps;
4515} 4514}
4516 4515
4517void ci_update_requested_ps(struct radeon_device *rdev, 4516static void ci_update_requested_ps(struct radeon_device *rdev,
4518 struct radeon_ps *rps) 4517 struct radeon_ps *rps)
4519{ 4518{
4520 struct ci_ps *new_ps = ci_get_ps(rps); 4519 struct ci_ps *new_ps = ci_get_ps(rps);
4521 struct ci_power_info *pi = ci_get_pi(rdev); 4520 struct ci_power_info *pi = ci_get_pi(rdev);
@@ -4549,6 +4548,11 @@ void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4549 4548
4550void ci_dpm_setup_asic(struct radeon_device *rdev) 4549void ci_dpm_setup_asic(struct radeon_device *rdev)
4551{ 4550{
4551 int r;
4552
4553 r = ci_mc_load_microcode(rdev);
4554 if (r)
4555 DRM_ERROR("Failed to load MC firmware!\n");
4552 ci_read_clock_registers(rdev); 4556 ci_read_clock_registers(rdev);
4553 ci_get_memory_type(rdev); 4557 ci_get_memory_type(rdev);
4554 ci_enable_acpi_power_management(rdev); 4558 ci_enable_acpi_power_management(rdev);
@@ -4561,13 +4565,6 @@ int ci_dpm_enable(struct radeon_device *rdev)
4561 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4565 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4562 int ret; 4566 int ret;
4563 4567
4564 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4565 RADEON_CG_BLOCK_MC |
4566 RADEON_CG_BLOCK_SDMA |
4567 RADEON_CG_BLOCK_BIF |
4568 RADEON_CG_BLOCK_UVD |
4569 RADEON_CG_BLOCK_HDP), false);
4570
4571 if (ci_is_smc_running(rdev)) 4568 if (ci_is_smc_running(rdev))
4572 return -EINVAL; 4569 return -EINVAL;
4573 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { 4570 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
@@ -4665,6 +4662,18 @@ int ci_dpm_enable(struct radeon_device *rdev)
4665 DRM_ERROR("ci_enable_power_containment failed\n"); 4662 DRM_ERROR("ci_enable_power_containment failed\n");
4666 return ret; 4663 return ret;
4667 } 4664 }
4665
4666 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4667
4668 ci_update_current_ps(rdev, boot_ps);
4669
4670 return 0;
4671}
4672
4673int ci_dpm_late_enable(struct radeon_device *rdev)
4674{
4675 int ret;
4676
4668 if (rdev->irq.installed && 4677 if (rdev->irq.installed &&
4669 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 4678 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4670#if 0 4679#if 0
@@ -4685,19 +4694,8 @@ int ci_dpm_enable(struct radeon_device *rdev)
4685#endif 4694#endif
4686 } 4695 }
4687 4696
4688 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4689
4690 ci_dpm_powergate_uvd(rdev, true); 4697 ci_dpm_powergate_uvd(rdev, true);
4691 4698
4692 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4693 RADEON_CG_BLOCK_MC |
4694 RADEON_CG_BLOCK_SDMA |
4695 RADEON_CG_BLOCK_BIF |
4696 RADEON_CG_BLOCK_UVD |
4697 RADEON_CG_BLOCK_HDP), true);
4698
4699 ci_update_current_ps(rdev, boot_ps);
4700
4701 return 0; 4699 return 0;
4702} 4700}
4703 4701
@@ -4706,12 +4704,6 @@ void ci_dpm_disable(struct radeon_device *rdev)
4706 struct ci_power_info *pi = ci_get_pi(rdev); 4704 struct ci_power_info *pi = ci_get_pi(rdev);
4707 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 4705 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4708 4706
4709 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4710 RADEON_CG_BLOCK_MC |
4711 RADEON_CG_BLOCK_SDMA |
4712 RADEON_CG_BLOCK_UVD |
4713 RADEON_CG_BLOCK_HDP), false);
4714
4715 ci_dpm_powergate_uvd(rdev, false); 4707 ci_dpm_powergate_uvd(rdev, false);
4716 4708
4717 if (!ci_is_smc_running(rdev)) 4709 if (!ci_is_smc_running(rdev))
@@ -4742,13 +4734,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
4742 struct radeon_ps *old_ps = &pi->current_rps; 4734 struct radeon_ps *old_ps = &pi->current_rps;
4743 int ret; 4735 int ret;
4744 4736
4745 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4746 RADEON_CG_BLOCK_MC |
4747 RADEON_CG_BLOCK_SDMA |
4748 RADEON_CG_BLOCK_BIF |
4749 RADEON_CG_BLOCK_UVD |
4750 RADEON_CG_BLOCK_HDP), false);
4751
4752 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); 4737 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4753 if (pi->pcie_performance_request) 4738 if (pi->pcie_performance_request)
4754 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 4739 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
@@ -4804,13 +4789,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
4804 if (pi->pcie_performance_request) 4789 if (pi->pcie_performance_request)
4805 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 4790 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4806 4791
4807 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
4808 RADEON_CG_BLOCK_MC |
4809 RADEON_CG_BLOCK_SDMA |
4810 RADEON_CG_BLOCK_BIF |
4811 RADEON_CG_BLOCK_UVD |
4812 RADEON_CG_BLOCK_HDP), true);
4813
4814 return 0; 4792 return 0;
4815} 4793}
4816 4794
@@ -5023,8 +5001,8 @@ static int ci_parse_power_table(struct radeon_device *rdev)
5023 return 0; 5001 return 0;
5024} 5002}
5025 5003
5026int ci_get_vbios_boot_values(struct radeon_device *rdev, 5004static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5027 struct ci_vbios_boot_state *boot_state) 5005 struct ci_vbios_boot_state *boot_state)
5028{ 5006{
5029 struct radeon_mode_info *mode_info = &rdev->mode_info; 5007 struct radeon_mode_info *mode_info = &rdev->mode_info;
5030 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 5008 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c
index 9c745dd22438..8debc9d47362 100644
--- a/drivers/gpu/drm/radeon/ci_smc.c
+++ b/drivers/gpu/drm/radeon/ci_smc.c
@@ -28,6 +28,7 @@
28#include "cikd.h" 28#include "cikd.h"
29#include "ppsmc.h" 29#include "ppsmc.h"
30#include "radeon_ucode.h" 30#include "radeon_ucode.h"
31#include "ci_dpm.h"
31 32
32static int ci_set_smc_sram_address(struct radeon_device *rdev, 33static int ci_set_smc_sram_address(struct radeon_device *rdev,
33 u32 smc_address, u32 limit) 34 u32 smc_address, u32 limit)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e950fabd7f5e..e6419ca7cd37 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1697,7 +1697,7 @@ static void cik_srbm_select(struct radeon_device *rdev,
1697 * Load the GDDR MC ucode into the hw (CIK). 1697 * Load the GDDR MC ucode into the hw (CIK).
1698 * Returns 0 on success, error on failure. 1698 * Returns 0 on success, error on failure.
1699 */ 1699 */
1700static int ci_mc_load_microcode(struct radeon_device *rdev) 1700int ci_mc_load_microcode(struct radeon_device *rdev)
1701{ 1701{
1702 const __be32 *fw_data; 1702 const __be32 *fw_data;
1703 u32 running, blackout = 0; 1703 u32 running, blackout = 0;
@@ -3487,6 +3487,51 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3487} 3487}
3488 3488
3489/** 3489/**
3490 * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3491 *
3492 * @rdev: radeon_device pointer
3493 * @ridx: radeon ring index
3494 *
3495 * Emits an hdp flush on the cp.
3496 */
3497static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3498 int ridx)
3499{
3500 struct radeon_ring *ring = &rdev->ring[ridx];
3501 u32 ref_and_mask;
3502
3503 switch (ring->idx) {
3504 case CAYMAN_RING_TYPE_CP1_INDEX:
3505 case CAYMAN_RING_TYPE_CP2_INDEX:
3506 default:
3507 switch (ring->me) {
3508 case 0:
3509 ref_and_mask = CP2 << ring->pipe;
3510 break;
3511 case 1:
3512 ref_and_mask = CP6 << ring->pipe;
3513 break;
3514 default:
3515 return;
3516 }
3517 break;
3518 case RADEON_RING_TYPE_GFX_INDEX:
3519 ref_and_mask = CP0;
3520 break;
3521 }
3522
3523 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3524 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3525 WAIT_REG_MEM_FUNCTION(3) | /* == */
3526 WAIT_REG_MEM_ENGINE(1))); /* pfp */
3527 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3528 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3529 radeon_ring_write(ring, ref_and_mask);
3530 radeon_ring_write(ring, ref_and_mask);
3531 radeon_ring_write(ring, 0x20); /* poll interval */
3532}
3533
3534/**
3490 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring 3535 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3491 * 3536 *
3492 * @rdev: radeon_device pointer 3537 * @rdev: radeon_device pointer
@@ -3512,15 +3557,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3512 radeon_ring_write(ring, fence->seq); 3557 radeon_ring_write(ring, fence->seq);
3513 radeon_ring_write(ring, 0); 3558 radeon_ring_write(ring, 0);
3514 /* HDP flush */ 3559 /* HDP flush */
3515 /* We should be using the new WAIT_REG_MEM special op packet here 3560 cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
3516 * but it causes the CP to hang
3517 */
3518 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3519 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3520 WRITE_DATA_DST_SEL(0)));
3521 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3522 radeon_ring_write(ring, 0);
3523 radeon_ring_write(ring, 0);
3524} 3561}
3525 3562
3526/** 3563/**
@@ -3550,15 +3587,7 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3550 radeon_ring_write(ring, fence->seq); 3587 radeon_ring_write(ring, fence->seq);
3551 radeon_ring_write(ring, 0); 3588 radeon_ring_write(ring, 0);
3552 /* HDP flush */ 3589 /* HDP flush */
3553 /* We should be using the new WAIT_REG_MEM special op packet here 3590 cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
3554 * but it causes the CP to hang
3555 */
3556 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3557 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3558 WRITE_DATA_DST_SEL(0)));
3559 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3560 radeon_ring_write(ring, 0);
3561 radeon_ring_write(ring, 0);
3562} 3591}
3563 3592
3564bool cik_semaphore_ring_emit(struct radeon_device *rdev, 3593bool cik_semaphore_ring_emit(struct radeon_device *rdev,
@@ -3566,8 +3595,6 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3566 struct radeon_semaphore *semaphore, 3595 struct radeon_semaphore *semaphore,
3567 bool emit_wait) 3596 bool emit_wait)
3568{ 3597{
3569/* TODO: figure out why semaphore cause lockups */
3570#if 0
3571 uint64_t addr = semaphore->gpu_addr; 3598 uint64_t addr = semaphore->gpu_addr;
3572 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3599 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3573 3600
@@ -3576,9 +3603,6 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3576 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); 3603 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3577 3604
3578 return true; 3605 return true;
3579#else
3580 return false;
3581#endif
3582} 3606}
3583 3607
3584/** 3608/**
@@ -3816,6 +3840,8 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3816 if (enable) 3840 if (enable)
3817 WREG32(CP_ME_CNTL, 0); 3841 WREG32(CP_ME_CNTL, 0);
3818 else { 3842 else {
3843 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3844 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3819 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 3845 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3820 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3846 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3821 } 3847 }
@@ -4014,18 +4040,50 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
4014 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 4040 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4015 return r; 4041 return r;
4016 } 4042 }
4043
4044 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
4045 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
4046
4017 return 0; 4047 return 0;
4018} 4048}
4019 4049
4020u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 4050u32 cik_gfx_get_rptr(struct radeon_device *rdev,
4021 struct radeon_ring *ring) 4051 struct radeon_ring *ring)
4022{ 4052{
4023 u32 rptr; 4053 u32 rptr;
4024 4054
4055 if (rdev->wb.enabled)
4056 rptr = rdev->wb.wb[ring->rptr_offs/4];
4057 else
4058 rptr = RREG32(CP_RB0_RPTR);
4059
4060 return rptr;
4061}
4062
4063u32 cik_gfx_get_wptr(struct radeon_device *rdev,
4064 struct radeon_ring *ring)
4065{
4066 u32 wptr;
4067
4068 wptr = RREG32(CP_RB0_WPTR);
4069
4070 return wptr;
4071}
4025 4072
4073void cik_gfx_set_wptr(struct radeon_device *rdev,
4074 struct radeon_ring *ring)
4075{
4076 WREG32(CP_RB0_WPTR, ring->wptr);
4077 (void)RREG32(CP_RB0_WPTR);
4078}
4079
4080u32 cik_compute_get_rptr(struct radeon_device *rdev,
4081 struct radeon_ring *ring)
4082{
4083 u32 rptr;
4026 4084
4027 if (rdev->wb.enabled) { 4085 if (rdev->wb.enabled) {
4028 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 4086 rptr = rdev->wb.wb[ring->rptr_offs/4];
4029 } else { 4087 } else {
4030 mutex_lock(&rdev->srbm_mutex); 4088 mutex_lock(&rdev->srbm_mutex);
4031 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); 4089 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
@@ -4037,13 +4095,14 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
4037 return rptr; 4095 return rptr;
4038} 4096}
4039 4097
4040u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 4098u32 cik_compute_get_wptr(struct radeon_device *rdev,
4041 struct radeon_ring *ring) 4099 struct radeon_ring *ring)
4042{ 4100{
4043 u32 wptr; 4101 u32 wptr;
4044 4102
4045 if (rdev->wb.enabled) { 4103 if (rdev->wb.enabled) {
4046 wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]); 4104 /* XXX check if swapping is necessary on BE */
4105 wptr = rdev->wb.wb[ring->wptr_offs/4];
4047 } else { 4106 } else {
4048 mutex_lock(&rdev->srbm_mutex); 4107 mutex_lock(&rdev->srbm_mutex);
4049 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); 4108 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
@@ -4055,10 +4114,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
4055 return wptr; 4114 return wptr;
4056} 4115}
4057 4116
4058void cik_compute_ring_set_wptr(struct radeon_device *rdev, 4117void cik_compute_set_wptr(struct radeon_device *rdev,
4059 struct radeon_ring *ring) 4118 struct radeon_ring *ring)
4060{ 4119{
4061 rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr); 4120 /* XXX check if swapping is necessary on BE */
4121 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4062 WDOORBELL32(ring->doorbell_index, ring->wptr); 4122 WDOORBELL32(ring->doorbell_index, ring->wptr);
4063} 4123}
4064 4124
@@ -4852,6 +4912,160 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
4852 cik_print_gpu_status_regs(rdev); 4912 cik_print_gpu_status_regs(rdev);
4853} 4913}
4854 4914
4915struct kv_reset_save_regs {
4916 u32 gmcon_reng_execute;
4917 u32 gmcon_misc;
4918 u32 gmcon_misc3;
4919};
4920
4921static void kv_save_regs_for_reset(struct radeon_device *rdev,
4922 struct kv_reset_save_regs *save)
4923{
4924 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
4925 save->gmcon_misc = RREG32(GMCON_MISC);
4926 save->gmcon_misc3 = RREG32(GMCON_MISC3);
4927
4928 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
4929 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
4930 STCTRL_STUTTER_EN));
4931}
4932
4933static void kv_restore_regs_for_reset(struct radeon_device *rdev,
4934 struct kv_reset_save_regs *save)
4935{
4936 int i;
4937
4938 WREG32(GMCON_PGFSM_WRITE, 0);
4939 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
4940
4941 for (i = 0; i < 5; i++)
4942 WREG32(GMCON_PGFSM_WRITE, 0);
4943
4944 WREG32(GMCON_PGFSM_WRITE, 0);
4945 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
4946
4947 for (i = 0; i < 5; i++)
4948 WREG32(GMCON_PGFSM_WRITE, 0);
4949
4950 WREG32(GMCON_PGFSM_WRITE, 0x210000);
4951 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
4952
4953 for (i = 0; i < 5; i++)
4954 WREG32(GMCON_PGFSM_WRITE, 0);
4955
4956 WREG32(GMCON_PGFSM_WRITE, 0x21003);
4957 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
4958
4959 for (i = 0; i < 5; i++)
4960 WREG32(GMCON_PGFSM_WRITE, 0);
4961
4962 WREG32(GMCON_PGFSM_WRITE, 0x2b00);
4963 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
4964
4965 for (i = 0; i < 5; i++)
4966 WREG32(GMCON_PGFSM_WRITE, 0);
4967
4968 WREG32(GMCON_PGFSM_WRITE, 0);
4969 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
4970
4971 for (i = 0; i < 5; i++)
4972 WREG32(GMCON_PGFSM_WRITE, 0);
4973
4974 WREG32(GMCON_PGFSM_WRITE, 0x420000);
4975 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
4976
4977 for (i = 0; i < 5; i++)
4978 WREG32(GMCON_PGFSM_WRITE, 0);
4979
4980 WREG32(GMCON_PGFSM_WRITE, 0x120202);
4981 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
4982
4983 for (i = 0; i < 5; i++)
4984 WREG32(GMCON_PGFSM_WRITE, 0);
4985
4986 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
4987 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
4988
4989 for (i = 0; i < 5; i++)
4990 WREG32(GMCON_PGFSM_WRITE, 0);
4991
4992 WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
4993 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
4994
4995 for (i = 0; i < 5; i++)
4996 WREG32(GMCON_PGFSM_WRITE, 0);
4997
4998 WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
4999 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
5000
5001 WREG32(GMCON_MISC3, save->gmcon_misc3);
5002 WREG32(GMCON_MISC, save->gmcon_misc);
5003 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
5004}
5005
5006static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
5007{
5008 struct evergreen_mc_save save;
5009 struct kv_reset_save_regs kv_save = { 0 };
5010 u32 tmp, i;
5011
5012 dev_info(rdev->dev, "GPU pci config reset\n");
5013
5014 /* disable dpm? */
5015
5016 /* disable cg/pg */
5017 cik_fini_pg(rdev);
5018 cik_fini_cg(rdev);
5019
5020 /* Disable GFX parsing/prefetching */
5021 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5022
5023 /* Disable MEC parsing/prefetching */
5024 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5025
5026 /* sdma0 */
5027 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5028 tmp |= SDMA_HALT;
5029 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5030 /* sdma1 */
5031 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5032 tmp |= SDMA_HALT;
5033 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5034 /* XXX other engines? */
5035
5036 /* halt the rlc, disable cp internal ints */
5037 cik_rlc_stop(rdev);
5038
5039 udelay(50);
5040
5041 /* disable mem access */
5042 evergreen_mc_stop(rdev, &save);
5043 if (evergreen_mc_wait_for_idle(rdev)) {
5044 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
5045 }
5046
5047 if (rdev->flags & RADEON_IS_IGP)
5048 kv_save_regs_for_reset(rdev, &kv_save);
5049
5050 /* disable BM */
5051 pci_clear_master(rdev->pdev);
5052 /* reset */
5053 radeon_pci_config_reset(rdev);
5054
5055 udelay(100);
5056
5057 /* wait for asic to come out of reset */
5058 for (i = 0; i < rdev->usec_timeout; i++) {
5059 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
5060 break;
5061 udelay(1);
5062 }
5063
5064 /* does asic init need to be run first??? */
5065 if (rdev->flags & RADEON_IS_IGP)
5066 kv_restore_regs_for_reset(rdev, &kv_save);
5067}
5068
4855/** 5069/**
4856 * cik_asic_reset - soft reset GPU 5070 * cik_asic_reset - soft reset GPU
4857 * 5071 *
@@ -4870,10 +5084,17 @@ int cik_asic_reset(struct radeon_device *rdev)
4870 if (reset_mask) 5084 if (reset_mask)
4871 r600_set_bios_scratch_engine_hung(rdev, true); 5085 r600_set_bios_scratch_engine_hung(rdev, true);
4872 5086
5087 /* try soft reset */
4873 cik_gpu_soft_reset(rdev, reset_mask); 5088 cik_gpu_soft_reset(rdev, reset_mask);
4874 5089
4875 reset_mask = cik_gpu_check_soft_reset(rdev); 5090 reset_mask = cik_gpu_check_soft_reset(rdev);
4876 5091
5092 /* try pci config reset */
5093 if (reset_mask && radeon_hard_reset)
5094 cik_gpu_pci_config_reset(rdev);
5095
5096 reset_mask = cik_gpu_check_soft_reset(rdev);
5097
4877 if (!reset_mask) 5098 if (!reset_mask)
4878 r600_set_bios_scratch_engine_hung(rdev, false); 5099 r600_set_bios_scratch_engine_hung(rdev, false);
4879 5100
@@ -5138,20 +5359,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
5138 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 5359 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5139 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 5360 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
5140 5361
5141 /* TC cache setup ??? */
5142 WREG32(TC_CFG_L1_LOAD_POLICY0, 0);
5143 WREG32(TC_CFG_L1_LOAD_POLICY1, 0);
5144 WREG32(TC_CFG_L1_STORE_POLICY, 0);
5145
5146 WREG32(TC_CFG_L2_LOAD_POLICY0, 0);
5147 WREG32(TC_CFG_L2_LOAD_POLICY1, 0);
5148 WREG32(TC_CFG_L2_STORE_POLICY0, 0);
5149 WREG32(TC_CFG_L2_STORE_POLICY1, 0);
5150 WREG32(TC_CFG_L2_ATOMIC_POLICY, 0);
5151
5152 WREG32(TC_CFG_L1_VOLATILE, 0);
5153 WREG32(TC_CFG_L2_VOLATILE, 0);
5154
5155 if (rdev->family == CHIP_KAVERI) { 5362 if (rdev->family == CHIP_KAVERI) {
5156 u32 tmp = RREG32(CHUB_CONTROL); 5363 u32 tmp = RREG32(CHUB_CONTROL);
5157 tmp &= ~BYPASS_VM; 5364 tmp &= ~BYPASS_VM;
@@ -5367,16 +5574,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
5367 radeon_ring_write(ring, VMID(0)); 5574 radeon_ring_write(ring, VMID(0));
5368 5575
5369 /* HDP flush */ 5576 /* HDP flush */
5370 /* We should be using the WAIT_REG_MEM packet here like in 5577 cik_hdp_flush_cp_ring_emit(rdev, ridx);
5371 * cik_fence_ring_emit(), but it causes the CP to hang in this
5372 * context...
5373 */
5374 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5375 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5376 WRITE_DATA_DST_SEL(0)));
5377 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5378 radeon_ring_write(ring, 0);
5379 radeon_ring_write(ring, 0);
5380 5578
5381 /* bits 0-15 are the VM contexts0-15 */ 5579 /* bits 0-15 are the VM contexts0-15 */
5382 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5580 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -7503,26 +7701,7 @@ static int cik_startup(struct radeon_device *rdev)
7503 7701
7504 cik_mc_program(rdev); 7702 cik_mc_program(rdev);
7505 7703
7506 if (rdev->flags & RADEON_IS_IGP) { 7704 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
7507 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
7508 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
7509 r = cik_init_microcode(rdev);
7510 if (r) {
7511 DRM_ERROR("Failed to load firmware!\n");
7512 return r;
7513 }
7514 }
7515 } else {
7516 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
7517 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
7518 !rdev->mc_fw) {
7519 r = cik_init_microcode(rdev);
7520 if (r) {
7521 DRM_ERROR("Failed to load firmware!\n");
7522 return r;
7523 }
7524 }
7525
7526 r = ci_mc_load_microcode(rdev); 7705 r = ci_mc_load_microcode(rdev);
7527 if (r) { 7706 if (r) {
7528 DRM_ERROR("Failed to load MC firmware!\n"); 7707 DRM_ERROR("Failed to load MC firmware!\n");
@@ -7627,7 +7806,6 @@ static int cik_startup(struct radeon_device *rdev)
7627 7806
7628 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 7807 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7629 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 7808 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
7630 CP_RB0_RPTR, CP_RB0_WPTR,
7631 PACKET3(PACKET3_NOP, 0x3FFF)); 7809 PACKET3(PACKET3_NOP, 0x3FFF));
7632 if (r) 7810 if (r)
7633 return r; 7811 return r;
@@ -7636,7 +7814,6 @@ static int cik_startup(struct radeon_device *rdev)
7636 /* type-2 packets are deprecated on MEC, use type-3 instead */ 7814 /* type-2 packets are deprecated on MEC, use type-3 instead */
7637 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 7815 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7638 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, 7816 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
7639 CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
7640 PACKET3(PACKET3_NOP, 0x3FFF)); 7817 PACKET3(PACKET3_NOP, 0x3FFF));
7641 if (r) 7818 if (r)
7642 return r; 7819 return r;
@@ -7648,7 +7825,6 @@ static int cik_startup(struct radeon_device *rdev)
7648 /* type-2 packets are deprecated on MEC, use type-3 instead */ 7825 /* type-2 packets are deprecated on MEC, use type-3 instead */
7649 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 7826 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7650 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, 7827 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
7651 CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
7652 PACKET3(PACKET3_NOP, 0x3FFF)); 7828 PACKET3(PACKET3_NOP, 0x3FFF));
7653 if (r) 7829 if (r)
7654 return r; 7830 return r;
@@ -7660,16 +7836,12 @@ static int cik_startup(struct radeon_device *rdev)
7660 7836
7661 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 7837 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7662 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 7838 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
7663 SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,
7664 SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,
7665 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 7839 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
7666 if (r) 7840 if (r)
7667 return r; 7841 return r;
7668 7842
7669 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 7843 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7670 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 7844 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
7671 SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,
7672 SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET,
7673 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 7845 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
7674 if (r) 7846 if (r)
7675 return r; 7847 return r;
@@ -7685,7 +7857,6 @@ static int cik_startup(struct radeon_device *rdev)
7685 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 7857 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
7686 if (ring->ring_size) { 7858 if (ring->ring_size) {
7687 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 7859 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
7688 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
7689 RADEON_CP_PACKET2); 7860 RADEON_CP_PACKET2);
7690 if (!r) 7861 if (!r)
7691 r = uvd_v1_0_init(rdev); 7862 r = uvd_v1_0_init(rdev);
@@ -7731,6 +7902,8 @@ int cik_resume(struct radeon_device *rdev)
7731 /* init golden registers */ 7902 /* init golden registers */
7732 cik_init_golden_registers(rdev); 7903 cik_init_golden_registers(rdev);
7733 7904
7905 radeon_pm_resume(rdev);
7906
7734 rdev->accel_working = true; 7907 rdev->accel_working = true;
7735 r = cik_startup(rdev); 7908 r = cik_startup(rdev);
7736 if (r) { 7909 if (r) {
@@ -7754,6 +7927,7 @@ int cik_resume(struct radeon_device *rdev)
7754 */ 7927 */
7755int cik_suspend(struct radeon_device *rdev) 7928int cik_suspend(struct radeon_device *rdev)
7756{ 7929{
7930 radeon_pm_suspend(rdev);
7757 dce6_audio_fini(rdev); 7931 dce6_audio_fini(rdev);
7758 radeon_vm_manager_fini(rdev); 7932 radeon_vm_manager_fini(rdev);
7759 cik_cp_enable(rdev, false); 7933 cik_cp_enable(rdev, false);
@@ -7835,6 +8009,30 @@ int cik_init(struct radeon_device *rdev)
7835 if (r) 8009 if (r)
7836 return r; 8010 return r;
7837 8011
8012 if (rdev->flags & RADEON_IS_IGP) {
8013 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8014 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
8015 r = cik_init_microcode(rdev);
8016 if (r) {
8017 DRM_ERROR("Failed to load firmware!\n");
8018 return r;
8019 }
8020 }
8021 } else {
8022 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8023 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
8024 !rdev->mc_fw) {
8025 r = cik_init_microcode(rdev);
8026 if (r) {
8027 DRM_ERROR("Failed to load firmware!\n");
8028 return r;
8029 }
8030 }
8031 }
8032
8033 /* Initialize power management */
8034 radeon_pm_init(rdev);
8035
7838 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 8036 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7839 ring->ring_obj = NULL; 8037 ring->ring_obj = NULL;
7840 r600_ring_init(rdev, ring, 1024 * 1024); 8038 r600_ring_init(rdev, ring, 1024 * 1024);
@@ -7915,6 +8113,7 @@ int cik_init(struct radeon_device *rdev)
7915 */ 8113 */
7916void cik_fini(struct radeon_device *rdev) 8114void cik_fini(struct radeon_device *rdev)
7917{ 8115{
8116 radeon_pm_fini(rdev);
7918 cik_cp_fini(rdev); 8117 cik_cp_fini(rdev);
7919 cik_sdma_fini(rdev); 8118 cik_sdma_fini(rdev);
7920 cik_fini_pg(rdev); 8119 cik_fini_pg(rdev);
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index d08b83c6267b..1ecb3f1070e3 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -52,6 +52,75 @@ u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
52 */ 52 */
53 53
54/** 54/**
55 * cik_sdma_get_rptr - get the current read pointer
56 *
57 * @rdev: radeon_device pointer
58 * @ring: radeon ring pointer
59 *
60 * Get the current rptr from the hardware (CIK+).
61 */
62uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
63 struct radeon_ring *ring)
64{
65 u32 rptr, reg;
66
67 if (rdev->wb.enabled) {
68 rptr = rdev->wb.wb[ring->rptr_offs/4];
69 } else {
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
71 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
72 else
73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
74
75 rptr = RREG32(reg);
76 }
77
78 return (rptr & 0x3fffc) >> 2;
79}
80
81/**
82 * cik_sdma_get_wptr - get the current write pointer
83 *
84 * @rdev: radeon_device pointer
85 * @ring: radeon ring pointer
86 *
87 * Get the current wptr from the hardware (CIK+).
88 */
89uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
90 struct radeon_ring *ring)
91{
92 u32 reg;
93
94 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
95 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
96 else
97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
98
99 return (RREG32(reg) & 0x3fffc) >> 2;
100}
101
102/**
103 * cik_sdma_set_wptr - commit the write pointer
104 *
105 * @rdev: radeon_device pointer
106 * @ring: radeon ring pointer
107 *
108 * Write the wptr back to the hardware (CIK+).
109 */
110void cik_sdma_set_wptr(struct radeon_device *rdev,
111 struct radeon_ring *ring)
112{
113 u32 reg;
114
115 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
116 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
117 else
118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
119
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
121}
122
123/**
55 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine 124 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
56 * 125 *
57 * @rdev: radeon_device pointer 126 * @rdev: radeon_device pointer
@@ -88,6 +157,35 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
88} 157}
89 158
90/** 159/**
160 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
161 *
162 * @rdev: radeon_device pointer
163 * @ridx: radeon ring index
164 *
165 * Emit an hdp flush packet on the requested DMA ring.
166 */
167static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
168 int ridx)
169{
170 struct radeon_ring *ring = &rdev->ring[ridx];
171 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
172 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
173 u32 ref_and_mask;
174
175 if (ridx == R600_RING_TYPE_DMA_INDEX)
176 ref_and_mask = SDMA0;
177 else
178 ref_and_mask = SDMA1;
179
180 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
181 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
182 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
183 radeon_ring_write(ring, ref_and_mask); /* reference */
184 radeon_ring_write(ring, ref_and_mask); /* mask */
185 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
186}
187
188/**
91 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring 189 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
92 * 190 *
93 * @rdev: radeon_device pointer 191 * @rdev: radeon_device pointer
@@ -111,12 +209,7 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
111 /* generate an interrupt */ 209 /* generate an interrupt */
112 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 210 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
113 /* flush HDP */ 211 /* flush HDP */
114 /* We should be using the new POLL_REG_MEM special op packet here 212 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
115 * but it causes sDMA to hang sometimes
116 */
117 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
118 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
119 radeon_ring_write(ring, 0);
120} 213}
121 214
122/** 215/**
@@ -157,7 +250,9 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
157 u32 rb_cntl, reg_offset; 250 u32 rb_cntl, reg_offset;
158 int i; 251 int i;
159 252
160 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 253 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
254 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
255 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
161 256
162 for (i = 0; i < 2; i++) { 257 for (i = 0; i < 2; i++) {
163 if (i == 0) 258 if (i == 0)
@@ -288,7 +383,9 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
288 } 383 }
289 } 384 }
290 385
291 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 386 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
387 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
388 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
292 389
293 return 0; 390 return 0;
294} 391}
@@ -747,12 +844,7 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm
747 radeon_ring_write(ring, VMID(0)); 844 radeon_ring_write(ring, VMID(0));
748 845
749 /* flush HDP */ 846 /* flush HDP */
750 /* We should be using the new POLL_REG_MEM special op packet here 847 cik_sdma_hdp_flush_ring_emit(rdev, ridx);
751 * but it causes sDMA to hang sometimes
752 */
753 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
754 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
755 radeon_ring_write(ring, 0);
756 848
757 /* flush TLB */ 849 /* flush TLB */
758 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 850 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 5964af5e5b2d..98bae9d7b74d 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -724,6 +724,17 @@
724 724
725#define ATC_MISC_CG 0x3350 725#define ATC_MISC_CG 0x3350
726 726
727#define GMCON_RENG_EXECUTE 0x3508
728#define RENG_EXECUTE_ON_PWR_UP (1 << 0)
729#define GMCON_MISC 0x350c
730#define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
731#define STCTRL_STUTTER_EN (1 << 16)
732
733#define GMCON_PGFSM_CONFIG 0x3538
734#define GMCON_PGFSM_WRITE 0x353c
735#define GMCON_PGFSM_READ 0x3540
736#define GMCON_MISC3 0x3544
737
727#define MC_SEQ_CNTL_3 0x3600 738#define MC_SEQ_CNTL_3 0x3600
728# define CAC_EN (1 << 31) 739# define CAC_EN (1 << 31)
729#define MC_SEQ_G5PDX_CTRL 0x3604 740#define MC_SEQ_G5PDX_CTRL 0x3604
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c
index 920e1e4a52c5..cf783fc0ef21 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -1905,21 +1905,6 @@ int cypress_dpm_enable(struct radeon_device *rdev)
1905 if (pi->mg_clock_gating) 1905 if (pi->mg_clock_gating)
1906 cypress_mg_clock_gating_enable(rdev, true); 1906 cypress_mg_clock_gating_enable(rdev, true);
1907 1907
1908 if (rdev->irq.installed &&
1909 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1910 PPSMC_Result result;
1911
1912 ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1913 if (ret)
1914 return ret;
1915 rdev->irq.dpm_thermal = true;
1916 radeon_irq_set(rdev);
1917 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
1918
1919 if (result != PPSMC_Result_OK)
1920 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1921 }
1922
1923 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 1908 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1924 1909
1925 return 0; 1910 return 0;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 9702e55e924e..f2b9e21ce4da 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -146,6 +146,7 @@ extern u32 si_get_csb_size(struct radeon_device *rdev);
146extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 146extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
147extern u32 cik_get_csb_size(struct radeon_device *rdev); 147extern u32 cik_get_csb_size(struct radeon_device *rdev);
148extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 148extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
149extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
149 150
150static const u32 evergreen_golden_registers[] = 151static const u32 evergreen_golden_registers[] =
151{ 152{
@@ -3867,6 +3868,48 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3867 evergreen_print_gpu_status_regs(rdev); 3868 evergreen_print_gpu_status_regs(rdev);
3868} 3869}
3869 3870
3871void evergreen_gpu_pci_config_reset(struct radeon_device *rdev)
3872{
3873 struct evergreen_mc_save save;
3874 u32 tmp, i;
3875
3876 dev_info(rdev->dev, "GPU pci config reset\n");
3877
3878 /* disable dpm? */
3879
3880 /* Disable CP parsing/prefetching */
3881 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
3882 udelay(50);
3883 /* Disable DMA */
3884 tmp = RREG32(DMA_RB_CNTL);
3885 tmp &= ~DMA_RB_ENABLE;
3886 WREG32(DMA_RB_CNTL, tmp);
3887 /* XXX other engines? */
3888
3889 /* halt the rlc */
3890 r600_rlc_stop(rdev);
3891
3892 udelay(50);
3893
3894 /* set mclk/sclk to bypass */
3895 rv770_set_clk_bypass_mode(rdev);
3896 /* disable BM */
3897 pci_clear_master(rdev->pdev);
3898 /* disable mem access */
3899 evergreen_mc_stop(rdev, &save);
3900 if (evergreen_mc_wait_for_idle(rdev)) {
3901 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
3902 }
3903 /* reset */
3904 radeon_pci_config_reset(rdev);
3905 /* wait for asic to come out of reset */
3906 for (i = 0; i < rdev->usec_timeout; i++) {
3907 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
3908 break;
3909 udelay(1);
3910 }
3911}
3912
3870int evergreen_asic_reset(struct radeon_device *rdev) 3913int evergreen_asic_reset(struct radeon_device *rdev)
3871{ 3914{
3872 u32 reset_mask; 3915 u32 reset_mask;
@@ -3876,10 +3919,17 @@ int evergreen_asic_reset(struct radeon_device *rdev)
3876 if (reset_mask) 3919 if (reset_mask)
3877 r600_set_bios_scratch_engine_hung(rdev, true); 3920 r600_set_bios_scratch_engine_hung(rdev, true);
3878 3921
3922 /* try soft reset */
3879 evergreen_gpu_soft_reset(rdev, reset_mask); 3923 evergreen_gpu_soft_reset(rdev, reset_mask);
3880 3924
3881 reset_mask = evergreen_gpu_check_soft_reset(rdev); 3925 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3882 3926
3927 /* try pci config reset */
3928 if (reset_mask && radeon_hard_reset)
3929 evergreen_gpu_pci_config_reset(rdev);
3930
3931 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3932
3883 if (!reset_mask) 3933 if (!reset_mask)
3884 r600_set_bios_scratch_engine_hung(rdev, false); 3934 r600_set_bios_scratch_engine_hung(rdev, false);
3885 3935
@@ -4298,8 +4348,8 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
4298 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 4348 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4299 } 4349 }
4300 4350
4301 /* only one DAC on DCE6 */ 4351 /* only one DAC on DCE5 */
4302 if (!ASIC_IS_DCE6(rdev)) 4352 if (!ASIC_IS_DCE5(rdev))
4303 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 4353 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
4304 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 4354 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
4305 4355
@@ -5109,27 +5159,12 @@ static int evergreen_startup(struct radeon_device *rdev)
5109 5159
5110 evergreen_mc_program(rdev); 5160 evergreen_mc_program(rdev);
5111 5161
5112 if (ASIC_IS_DCE5(rdev)) { 5162 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {
5113 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
5114 r = ni_init_microcode(rdev);
5115 if (r) {
5116 DRM_ERROR("Failed to load firmware!\n");
5117 return r;
5118 }
5119 }
5120 r = ni_mc_load_microcode(rdev); 5163 r = ni_mc_load_microcode(rdev);
5121 if (r) { 5164 if (r) {
5122 DRM_ERROR("Failed to load MC firmware!\n"); 5165 DRM_ERROR("Failed to load MC firmware!\n");
5123 return r; 5166 return r;
5124 } 5167 }
5125 } else {
5126 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
5127 r = r600_init_microcode(rdev);
5128 if (r) {
5129 DRM_ERROR("Failed to load firmware!\n");
5130 return r;
5131 }
5132 }
5133 } 5168 }
5134 5169
5135 if (rdev->flags & RADEON_IS_AGP) { 5170 if (rdev->flags & RADEON_IS_AGP) {
@@ -5199,14 +5234,12 @@ static int evergreen_startup(struct radeon_device *rdev)
5199 5234
5200 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 5235 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
5201 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 5236 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
5202 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
5203 RADEON_CP_PACKET2); 5237 RADEON_CP_PACKET2);
5204 if (r) 5238 if (r)
5205 return r; 5239 return r;
5206 5240
5207 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 5241 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
5208 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 5242 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
5209 DMA_RB_RPTR, DMA_RB_WPTR,
5210 DMA_PACKET(DMA_PACKET_NOP, 0, 0)); 5243 DMA_PACKET(DMA_PACKET_NOP, 0, 0));
5211 if (r) 5244 if (r)
5212 return r; 5245 return r;
@@ -5224,7 +5257,6 @@ static int evergreen_startup(struct radeon_device *rdev)
5224 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 5257 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
5225 if (ring->ring_size) { 5258 if (ring->ring_size) {
5226 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 5259 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
5227 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
5228 RADEON_CP_PACKET2); 5260 RADEON_CP_PACKET2);
5229 if (!r) 5261 if (!r)
5230 r = uvd_v1_0_init(rdev); 5262 r = uvd_v1_0_init(rdev);
@@ -5267,6 +5299,8 @@ int evergreen_resume(struct radeon_device *rdev)
5267 /* init golden registers */ 5299 /* init golden registers */
5268 evergreen_init_golden_registers(rdev); 5300 evergreen_init_golden_registers(rdev);
5269 5301
5302 radeon_pm_resume(rdev);
5303
5270 rdev->accel_working = true; 5304 rdev->accel_working = true;
5271 r = evergreen_startup(rdev); 5305 r = evergreen_startup(rdev);
5272 if (r) { 5306 if (r) {
@@ -5281,6 +5315,7 @@ int evergreen_resume(struct radeon_device *rdev)
5281 5315
5282int evergreen_suspend(struct radeon_device *rdev) 5316int evergreen_suspend(struct radeon_device *rdev)
5283{ 5317{
5318 radeon_pm_suspend(rdev);
5284 r600_audio_fini(rdev); 5319 r600_audio_fini(rdev);
5285 uvd_v1_0_fini(rdev); 5320 uvd_v1_0_fini(rdev);
5286 radeon_uvd_suspend(rdev); 5321 radeon_uvd_suspend(rdev);
@@ -5357,6 +5392,27 @@ int evergreen_init(struct radeon_device *rdev)
5357 if (r) 5392 if (r)
5358 return r; 5393 return r;
5359 5394
5395 if (ASIC_IS_DCE5(rdev)) {
5396 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
5397 r = ni_init_microcode(rdev);
5398 if (r) {
5399 DRM_ERROR("Failed to load firmware!\n");
5400 return r;
5401 }
5402 }
5403 } else {
5404 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
5405 r = r600_init_microcode(rdev);
5406 if (r) {
5407 DRM_ERROR("Failed to load firmware!\n");
5408 return r;
5409 }
5410 }
5411 }
5412
5413 /* Initialize power management */
5414 radeon_pm_init(rdev);
5415
5360 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 5416 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
5361 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 5417 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
5362 5418
@@ -5409,6 +5465,7 @@ int evergreen_init(struct radeon_device *rdev)
5409 5465
5410void evergreen_fini(struct radeon_device *rdev) 5466void evergreen_fini(struct radeon_device *rdev)
5411{ 5467{
5468 radeon_pm_fini(rdev);
5412 r600_audio_fini(rdev); 5469 r600_audio_fini(rdev);
5413 r700_cp_fini(rdev); 5470 r700_cp_fini(rdev);
5414 r600_dma_fini(rdev); 5471 r600_dma_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index eb8ac315f92f..c7cac07f139b 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -967,7 +967,10 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
967 if (track->cb_dirty) { 967 if (track->cb_dirty) {
968 tmp = track->cb_target_mask; 968 tmp = track->cb_target_mask;
969 for (i = 0; i < 8; i++) { 969 for (i = 0; i < 8; i++) {
970 if ((tmp >> (i * 4)) & 0xF) { 970 u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
971
972 if (format != V_028C70_COLOR_INVALID &&
973 (tmp >> (i * 4)) & 0xF) {
971 /* at least one component is enabled */ 974 /* at least one component is enabled */
972 if (track->cb_color_bo[i] == NULL) { 975 if (track->cb_color_bo[i] == NULL) {
973 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 976 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index 8a4e641f0e3c..a0f63ff5a5e9 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -33,6 +33,7 @@
33#define EVERGREEN_PIF_PHY0_DATA 0xc 33#define EVERGREEN_PIF_PHY0_DATA 0xc
34#define EVERGREEN_PIF_PHY1_INDEX 0x10 34#define EVERGREEN_PIF_PHY1_INDEX 0x10
35#define EVERGREEN_PIF_PHY1_DATA 0x14 35#define EVERGREEN_PIF_PHY1_DATA 0x14
36#define EVERGREEN_MM_INDEX_HI 0x18
36 37
37#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 38#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
38#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 39#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 17f990798992..f9c7963b3ee6 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -82,12 +82,16 @@
82#define CG_SPLL_FUNC_CNTL_2 0x604 82#define CG_SPLL_FUNC_CNTL_2 0x604
83#define SCLK_MUX_SEL(x) ((x) << 0) 83#define SCLK_MUX_SEL(x) ((x) << 0)
84#define SCLK_MUX_SEL_MASK (0x1ff << 0) 84#define SCLK_MUX_SEL_MASK (0x1ff << 0)
85#define SCLK_MUX_UPDATE (1 << 26)
85#define CG_SPLL_FUNC_CNTL_3 0x608 86#define CG_SPLL_FUNC_CNTL_3 0x608
86#define SPLL_FB_DIV(x) ((x) << 0) 87#define SPLL_FB_DIV(x) ((x) << 0)
87#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 88#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
88#define SPLL_DITHEN (1 << 28) 89#define SPLL_DITHEN (1 << 28)
90#define CG_SPLL_STATUS 0x60c
91#define SPLL_CHG_STATUS (1 << 1)
89 92
90#define MPLL_CNTL_MODE 0x61c 93#define MPLL_CNTL_MODE 0x61c
94# define MPLL_MCLK_SEL (1 << 11)
91# define SS_SSEN (1 << 24) 95# define SS_SSEN (1 << 24)
92# define SS_DSMODE_EN (1 << 25) 96# define SS_DSMODE_EN (1 << 25)
93 97
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index b41905573cd2..b6e01d5d2cce 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -1126,11 +1126,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
1126 struct kv_power_info *pi = kv_get_pi(rdev); 1126 struct kv_power_info *pi = kv_get_pi(rdev);
1127 int ret; 1127 int ret;
1128 1128
1129 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1130 RADEON_CG_BLOCK_SDMA |
1131 RADEON_CG_BLOCK_BIF |
1132 RADEON_CG_BLOCK_HDP), false);
1133
1134 ret = kv_process_firmware_header(rdev); 1129 ret = kv_process_firmware_header(rdev);
1135 if (ret) { 1130 if (ret) {
1136 DRM_ERROR("kv_process_firmware_header failed\n"); 1131 DRM_ERROR("kv_process_firmware_header failed\n");
@@ -1215,6 +1210,21 @@ int kv_dpm_enable(struct radeon_device *rdev)
1215 1210
1216 kv_reset_acp_boot_level(rdev); 1211 kv_reset_acp_boot_level(rdev);
1217 1212
1213 ret = kv_smc_bapm_enable(rdev, false);
1214 if (ret) {
1215 DRM_ERROR("kv_smc_bapm_enable failed\n");
1216 return ret;
1217 }
1218
1219 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1220
1221 return ret;
1222}
1223
1224int kv_dpm_late_enable(struct radeon_device *rdev)
1225{
1226 int ret;
1227
1218 if (rdev->irq.installed && 1228 if (rdev->irq.installed &&
1219 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1229 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1220 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1230 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1226,35 +1236,17 @@ int kv_dpm_enable(struct radeon_device *rdev)
1226 radeon_irq_set(rdev); 1236 radeon_irq_set(rdev);
1227 } 1237 }
1228 1238
1229 ret = kv_smc_bapm_enable(rdev, false);
1230 if (ret) {
1231 DRM_ERROR("kv_smc_bapm_enable failed\n");
1232 return ret;
1233 }
1234
1235 /* powerdown unused blocks for now */ 1239 /* powerdown unused blocks for now */
1236 kv_dpm_powergate_acp(rdev, true); 1240 kv_dpm_powergate_acp(rdev, true);
1237 kv_dpm_powergate_samu(rdev, true); 1241 kv_dpm_powergate_samu(rdev, true);
1238 kv_dpm_powergate_vce(rdev, true); 1242 kv_dpm_powergate_vce(rdev, true);
1239 kv_dpm_powergate_uvd(rdev, true); 1243 kv_dpm_powergate_uvd(rdev, true);
1240 1244
1241 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1242 RADEON_CG_BLOCK_SDMA |
1243 RADEON_CG_BLOCK_BIF |
1244 RADEON_CG_BLOCK_HDP), true);
1245
1246 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1247
1248 return ret; 1245 return ret;
1249} 1246}
1250 1247
1251void kv_dpm_disable(struct radeon_device *rdev) 1248void kv_dpm_disable(struct radeon_device *rdev)
1252{ 1249{
1253 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1254 RADEON_CG_BLOCK_SDMA |
1255 RADEON_CG_BLOCK_BIF |
1256 RADEON_CG_BLOCK_HDP), false);
1257
1258 kv_smc_bapm_enable(rdev, false); 1250 kv_smc_bapm_enable(rdev, false);
1259 1251
1260 /* powerup blocks */ 1252 /* powerup blocks */
@@ -1779,11 +1771,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
1779 /*struct radeon_ps *old_ps = &pi->current_rps;*/ 1771 /*struct radeon_ps *old_ps = &pi->current_rps;*/
1780 int ret; 1772 int ret;
1781 1773
1782 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1783 RADEON_CG_BLOCK_SDMA |
1784 RADEON_CG_BLOCK_BIF |
1785 RADEON_CG_BLOCK_HDP), false);
1786
1787 if (pi->bapm_enable) { 1774 if (pi->bapm_enable) {
1788 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power); 1775 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1789 if (ret) { 1776 if (ret) {
@@ -1849,11 +1836,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
1849 } 1836 }
1850 } 1837 }
1851 1838
1852 cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
1853 RADEON_CG_BLOCK_SDMA |
1854 RADEON_CG_BLOCK_BIF |
1855 RADEON_CG_BLOCK_HDP), true);
1856
1857 return 0; 1839 return 0;
1858} 1840}
1859 1841
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index f59a9e9fccf8..ea932ac66fc6 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -174,6 +174,7 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174extern void evergreen_program_aspm(struct radeon_device *rdev); 174extern void evergreen_program_aspm(struct radeon_device *rdev);
175extern void sumo_rlc_fini(struct radeon_device *rdev); 175extern void sumo_rlc_fini(struct radeon_device *rdev);
176extern int sumo_rlc_init(struct radeon_device *rdev); 176extern int sumo_rlc_init(struct radeon_device *rdev);
177extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
177 178
178/* Firmware Names */ 179/* Firmware Names */
179MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 180MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -1330,13 +1331,12 @@ void cayman_fence_ring_emit(struct radeon_device *rdev,
1330{ 1331{
1331 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1332 struct radeon_ring *ring = &rdev->ring[fence->ring];
1332 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1333 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1334 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1335 PACKET3_SH_ACTION_ENA;
1333 1336
1334 /* flush read cache over gart for this vmid */ 1337 /* flush read cache over gart for this vmid */
1335 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1336 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1337 radeon_ring_write(ring, 0);
1338 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1338 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1339 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); 1339 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1340 radeon_ring_write(ring, 0xFFFFFFFF); 1340 radeon_ring_write(ring, 0xFFFFFFFF);
1341 radeon_ring_write(ring, 0); 1341 radeon_ring_write(ring, 0);
1342 radeon_ring_write(ring, 10); /* poll interval */ 1342 radeon_ring_write(ring, 10); /* poll interval */
@@ -1352,6 +1352,8 @@ void cayman_fence_ring_emit(struct radeon_device *rdev,
1352void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1352void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1353{ 1353{
1354 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1354 struct radeon_ring *ring = &rdev->ring[ib->ring];
1355 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1356 PACKET3_SH_ACTION_ENA;
1355 1357
1356 /* set to DX10/11 mode */ 1358 /* set to DX10/11 mode */
1357 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1359 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
@@ -1376,14 +1378,11 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1376 (ib->vm ? (ib->vm->id << 24) : 0)); 1378 (ib->vm ? (ib->vm->id << 24) : 0));
1377 1379
1378 /* flush read cache over gart for this vmid */ 1380 /* flush read cache over gart for this vmid */
1379 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1380 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1381 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1382 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1381 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1383 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); 1382 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1384 radeon_ring_write(ring, 0xFFFFFFFF); 1383 radeon_ring_write(ring, 0xFFFFFFFF);
1385 radeon_ring_write(ring, 0); 1384 radeon_ring_write(ring, 0);
1386 radeon_ring_write(ring, 10); /* poll interval */ 1385 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
1387} 1386}
1388 1387
1389static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1388static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
@@ -1391,13 +1390,63 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1391 if (enable) 1390 if (enable)
1392 WREG32(CP_ME_CNTL, 0); 1391 WREG32(CP_ME_CNTL, 0);
1393 else { 1392 else {
1394 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1393 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1394 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1395 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1395 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1396 WREG32(SCRATCH_UMSK, 0); 1396 WREG32(SCRATCH_UMSK, 0);
1397 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1397 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1398 } 1398 }
1399} 1399}
1400 1400
1401u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1402 struct radeon_ring *ring)
1403{
1404 u32 rptr;
1405
1406 if (rdev->wb.enabled)
1407 rptr = rdev->wb.wb[ring->rptr_offs/4];
1408 else {
1409 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1410 rptr = RREG32(CP_RB0_RPTR);
1411 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1412 rptr = RREG32(CP_RB1_RPTR);
1413 else
1414 rptr = RREG32(CP_RB2_RPTR);
1415 }
1416
1417 return rptr;
1418}
1419
1420u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1421 struct radeon_ring *ring)
1422{
1423 u32 wptr;
1424
1425 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1426 wptr = RREG32(CP_RB0_WPTR);
1427 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1428 wptr = RREG32(CP_RB1_WPTR);
1429 else
1430 wptr = RREG32(CP_RB2_WPTR);
1431
1432 return wptr;
1433}
1434
1435void cayman_gfx_set_wptr(struct radeon_device *rdev,
1436 struct radeon_ring *ring)
1437{
1438 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1439 WREG32(CP_RB0_WPTR, ring->wptr);
1440 (void)RREG32(CP_RB0_WPTR);
1441 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1442 WREG32(CP_RB1_WPTR, ring->wptr);
1443 (void)RREG32(CP_RB1_WPTR);
1444 } else {
1445 WREG32(CP_RB2_WPTR, ring->wptr);
1446 (void)RREG32(CP_RB2_WPTR);
1447 }
1448}
1449
1401static int cayman_cp_load_microcode(struct radeon_device *rdev) 1450static int cayman_cp_load_microcode(struct radeon_device *rdev)
1402{ 1451{
1403 const __be32 *fw_data; 1452 const __be32 *fw_data;
@@ -1526,6 +1575,16 @@ static int cayman_cp_resume(struct radeon_device *rdev)
1526 CP_RB1_BASE, 1575 CP_RB1_BASE,
1527 CP_RB2_BASE 1576 CP_RB2_BASE
1528 }; 1577 };
1578 static const unsigned cp_rb_rptr[] = {
1579 CP_RB0_RPTR,
1580 CP_RB1_RPTR,
1581 CP_RB2_RPTR
1582 };
1583 static const unsigned cp_rb_wptr[] = {
1584 CP_RB0_WPTR,
1585 CP_RB1_WPTR,
1586 CP_RB2_WPTR
1587 };
1529 struct radeon_ring *ring; 1588 struct radeon_ring *ring;
1530 int i, r; 1589 int i, r;
1531 1590
@@ -1584,8 +1643,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
1584 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1643 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1585 1644
1586 ring->rptr = ring->wptr = 0; 1645 ring->rptr = ring->wptr = 0;
1587 WREG32(ring->rptr_reg, ring->rptr); 1646 WREG32(cp_rb_rptr[i], ring->rptr);
1588 WREG32(ring->wptr_reg, ring->wptr); 1647 WREG32(cp_rb_wptr[i], ring->wptr);
1589 1648
1590 mdelay(1); 1649 mdelay(1);
1591 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1650 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
@@ -1605,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev)
1605 return r; 1664 return r;
1606 } 1665 }
1607 1666
1667 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1668 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1669
1608 return 0; 1670 return 0;
1609} 1671}
1610 1672
@@ -1831,8 +1893,10 @@ int cayman_asic_reset(struct radeon_device *rdev)
1831 1893
1832 reset_mask = cayman_gpu_check_soft_reset(rdev); 1894 reset_mask = cayman_gpu_check_soft_reset(rdev);
1833 1895
1834 if (!reset_mask) 1896 if (reset_mask)
1835 r600_set_bios_scratch_engine_hung(rdev, false); 1897 evergreen_gpu_pci_config_reset(rdev);
1898
1899 r600_set_bios_scratch_engine_hung(rdev, false);
1836 1900
1837 return 0; 1901 return 0;
1838} 1902}
@@ -1878,23 +1942,7 @@ static int cayman_startup(struct radeon_device *rdev)
1878 1942
1879 evergreen_mc_program(rdev); 1943 evergreen_mc_program(rdev);
1880 1944
1881 if (rdev->flags & RADEON_IS_IGP) { 1945 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
1882 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1883 r = ni_init_microcode(rdev);
1884 if (r) {
1885 DRM_ERROR("Failed to load firmware!\n");
1886 return r;
1887 }
1888 }
1889 } else {
1890 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1891 r = ni_init_microcode(rdev);
1892 if (r) {
1893 DRM_ERROR("Failed to load firmware!\n");
1894 return r;
1895 }
1896 }
1897
1898 r = ni_mc_load_microcode(rdev); 1946 r = ni_mc_load_microcode(rdev);
1899 if (r) { 1947 if (r) {
1900 DRM_ERROR("Failed to load MC firmware!\n"); 1948 DRM_ERROR("Failed to load MC firmware!\n");
@@ -1981,23 +2029,18 @@ static int cayman_startup(struct radeon_device *rdev)
1981 evergreen_irq_set(rdev); 2029 evergreen_irq_set(rdev);
1982 2030
1983 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2031 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1984 CP_RB0_RPTR, CP_RB0_WPTR,
1985 RADEON_CP_PACKET2); 2032 RADEON_CP_PACKET2);
1986 if (r) 2033 if (r)
1987 return r; 2034 return r;
1988 2035
1989 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2036 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1990 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2037 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1991 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1992 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1993 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2038 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1994 if (r) 2039 if (r)
1995 return r; 2040 return r;
1996 2041
1997 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 2042 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1998 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 2043 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1999 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
2000 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
2001 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2044 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2002 if (r) 2045 if (r)
2003 return r; 2046 return r;
@@ -2016,7 +2059,6 @@ static int cayman_startup(struct radeon_device *rdev)
2016 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 2059 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2017 if (ring->ring_size) { 2060 if (ring->ring_size) {
2018 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 2061 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2019 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
2020 RADEON_CP_PACKET2); 2062 RADEON_CP_PACKET2);
2021 if (!r) 2063 if (!r)
2022 r = uvd_v1_0_init(rdev); 2064 r = uvd_v1_0_init(rdev);
@@ -2063,6 +2105,8 @@ int cayman_resume(struct radeon_device *rdev)
2063 /* init golden registers */ 2105 /* init golden registers */
2064 ni_init_golden_registers(rdev); 2106 ni_init_golden_registers(rdev);
2065 2107
2108 radeon_pm_resume(rdev);
2109
2066 rdev->accel_working = true; 2110 rdev->accel_working = true;
2067 r = cayman_startup(rdev); 2111 r = cayman_startup(rdev);
2068 if (r) { 2112 if (r) {
@@ -2075,6 +2119,7 @@ int cayman_resume(struct radeon_device *rdev)
2075 2119
2076int cayman_suspend(struct radeon_device *rdev) 2120int cayman_suspend(struct radeon_device *rdev)
2077{ 2121{
2122 radeon_pm_suspend(rdev);
2078 if (ASIC_IS_DCE6(rdev)) 2123 if (ASIC_IS_DCE6(rdev))
2079 dce6_audio_fini(rdev); 2124 dce6_audio_fini(rdev);
2080 else 2125 else
@@ -2145,6 +2190,27 @@ int cayman_init(struct radeon_device *rdev)
2145 if (r) 2190 if (r)
2146 return r; 2191 return r;
2147 2192
2193 if (rdev->flags & RADEON_IS_IGP) {
2194 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2195 r = ni_init_microcode(rdev);
2196 if (r) {
2197 DRM_ERROR("Failed to load firmware!\n");
2198 return r;
2199 }
2200 }
2201 } else {
2202 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2203 r = ni_init_microcode(rdev);
2204 if (r) {
2205 DRM_ERROR("Failed to load firmware!\n");
2206 return r;
2207 }
2208 }
2209 }
2210
2211 /* Initialize power management */
2212 radeon_pm_init(rdev);
2213
2148 ring->ring_obj = NULL; 2214 ring->ring_obj = NULL;
2149 r600_ring_init(rdev, ring, 1024 * 1024); 2215 r600_ring_init(rdev, ring, 1024 * 1024);
2150 2216
@@ -2204,6 +2270,7 @@ int cayman_init(struct radeon_device *rdev)
2204 2270
2205void cayman_fini(struct radeon_device *rdev) 2271void cayman_fini(struct radeon_device *rdev)
2206{ 2272{
2273 radeon_pm_fini(rdev);
2207 cayman_cp_fini(rdev); 2274 cayman_cp_fini(rdev);
2208 cayman_dma_fini(rdev); 2275 cayman_dma_fini(rdev);
2209 r600_irq_fini(rdev); 2276 r600_irq_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
index bdeb65ed3658..7cf96b15377f 100644
--- a/drivers/gpu/drm/radeon/ni_dma.c
+++ b/drivers/gpu/drm/radeon/ni_dma.c
@@ -43,6 +43,75 @@ u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);
43 */ 43 */
44 44
45/** 45/**
46 * cayman_dma_get_rptr - get the current read pointer
47 *
48 * @rdev: radeon_device pointer
49 * @ring: radeon ring pointer
50 *
51 * Get the current rptr from the hardware (cayman+).
52 */
53uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
54 struct radeon_ring *ring)
55{
56 u32 rptr, reg;
57
58 if (rdev->wb.enabled) {
59 rptr = rdev->wb.wb[ring->rptr_offs/4];
60 } else {
61 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
62 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;
63 else
64 reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;
65
66 rptr = RREG32(reg);
67 }
68
69 return (rptr & 0x3fffc) >> 2;
70}
71
72/**
73 * cayman_dma_get_wptr - get the current write pointer
74 *
75 * @rdev: radeon_device pointer
76 * @ring: radeon ring pointer
77 *
78 * Get the current wptr from the hardware (cayman+).
79 */
80uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
81 struct radeon_ring *ring)
82{
83 u32 reg;
84
85 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
86 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
87 else
88 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
89
90 return (RREG32(reg) & 0x3fffc) >> 2;
91}
92
93/**
94 * cayman_dma_set_wptr - commit the write pointer
95 *
96 * @rdev: radeon_device pointer
97 * @ring: radeon ring pointer
98 *
99 * Write the wptr back to the hardware (cayman+).
100 */
101void cayman_dma_set_wptr(struct radeon_device *rdev,
102 struct radeon_ring *ring)
103{
104 u32 reg;
105
106 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
107 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
108 else
109 reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
110
111 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
112}
113
114/**
46 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine 115 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
47 * 116 *
48 * @rdev: radeon_device pointer 117 * @rdev: radeon_device pointer
@@ -88,7 +157,9 @@ void cayman_dma_stop(struct radeon_device *rdev)
88{ 157{
89 u32 rb_cntl; 158 u32 rb_cntl;
90 159
91 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 160 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
161 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
162 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
92 163
93 /* dma0 */ 164 /* dma0 */
94 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
@@ -190,7 +261,9 @@ int cayman_dma_resume(struct radeon_device *rdev)
190 } 261 }
191 } 262 }
192 263
193 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 264 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
265 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
266 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
194 267
195 return 0; 268 return 0;
196} 269}
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 49c4d48f54d6..c351226ecb31 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -720,6 +720,8 @@ static const u32 cayman_sysls_enable[] =
720struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 720struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
721struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 721struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
722 722
723extern int ni_mc_load_microcode(struct radeon_device *rdev);
724
723struct ni_power_info *ni_get_pi(struct radeon_device *rdev) 725struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
724{ 726{
725 struct ni_power_info *pi = rdev->pm.dpm.priv; 727 struct ni_power_info *pi = rdev->pm.dpm.priv;
@@ -3565,7 +3567,11 @@ void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
3565void ni_dpm_setup_asic(struct radeon_device *rdev) 3567void ni_dpm_setup_asic(struct radeon_device *rdev)
3566{ 3568{
3567 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3569 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3570 int r;
3568 3571
3572 r = ni_mc_load_microcode(rdev);
3573 if (r)
3574 DRM_ERROR("Failed to load MC firmware!\n");
3569 ni_read_clock_registers(rdev); 3575 ni_read_clock_registers(rdev);
3570 btc_read_arb_registers(rdev); 3576 btc_read_arb_registers(rdev);
3571 rv770_get_memory_type(rdev); 3577 rv770_get_memory_type(rdev);
@@ -3710,21 +3716,6 @@ int ni_dpm_enable(struct radeon_device *rdev)
3710 if (eg_pi->ls_clock_gating) 3716 if (eg_pi->ls_clock_gating)
3711 ni_ls_clockgating_enable(rdev, true); 3717 ni_ls_clockgating_enable(rdev, true);
3712 3718
3713 if (rdev->irq.installed &&
3714 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3715 PPSMC_Result result;
3716
3717 ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, 0xff * 1000);
3718 if (ret)
3719 return ret;
3720 rdev->irq.dpm_thermal = true;
3721 radeon_irq_set(rdev);
3722 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3723
3724 if (result != PPSMC_Result_OK)
3725 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
3726 }
3727
3728 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 3719 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
3729 3720
3730 ni_update_current_ps(rdev, boot_ps); 3721 ni_update_current_ps(rdev, boot_ps);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 22421bc80c0d..d996033c243e 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -1154,6 +1154,7 @@
1154# define PACKET3_DB_ACTION_ENA (1 << 26) 1154# define PACKET3_DB_ACTION_ENA (1 << 26)
1155# define PACKET3_SH_ACTION_ENA (1 << 27) 1155# define PACKET3_SH_ACTION_ENA (1 << 27)
1156# define PACKET3_SX_ACTION_ENA (1 << 28) 1156# define PACKET3_SX_ACTION_ENA (1 << 28)
1157# define PACKET3_ENGINE_ME (1 << 31)
1157#define PACKET3_ME_INITIALIZE 0x44 1158#define PACKET3_ME_INITIALIZE 0x44
1158#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1159#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1159#define PACKET3_COND_WRITE 0x45 1160#define PACKET3_COND_WRITE 0x45
diff --git a/drivers/gpu/drm/radeon/pptable.h b/drivers/gpu/drm/radeon/pptable.h
index da43ab328833..2d532996c697 100644
--- a/drivers/gpu/drm/radeon/pptable.h
+++ b/drivers/gpu/drm/radeon/pptable.h
@@ -23,7 +23,7 @@
23#ifndef _PPTABLE_H 23#ifndef _PPTABLE_H
24#define _PPTABLE_H 24#define _PPTABLE_H
25 25
26#pragma pack(push, 1) 26#pragma pack(1)
27 27
28typedef struct _ATOM_PPLIB_THERMALCONTROLLER 28typedef struct _ATOM_PPLIB_THERMALCONTROLLER
29 29
@@ -677,6 +677,6 @@ typedef struct _ATOM_PPLIB_PPM_Table
677 ULONG ulTjmax; 677 ULONG ulTjmax;
678} ATOM_PPLIB_PPM_Table; 678} ATOM_PPLIB_PPM_Table;
679 679
680#pragma pack(pop) 680#pragma pack()
681 681
682#endif 682#endif
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 10abc4d5a6cc..ef024ce3f7cc 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1050,6 +1050,36 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
1050 return err; 1050 return err;
1051} 1051}
1052 1052
1053u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1054 struct radeon_ring *ring)
1055{
1056 u32 rptr;
1057
1058 if (rdev->wb.enabled)
1059 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1060 else
1061 rptr = RREG32(RADEON_CP_RB_RPTR);
1062
1063 return rptr;
1064}
1065
1066u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1067 struct radeon_ring *ring)
1068{
1069 u32 wptr;
1070
1071 wptr = RREG32(RADEON_CP_RB_WPTR);
1072
1073 return wptr;
1074}
1075
1076void r100_gfx_set_wptr(struct radeon_device *rdev,
1077 struct radeon_ring *ring)
1078{
1079 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1080 (void)RREG32(RADEON_CP_RB_WPTR);
1081}
1082
1053static void r100_cp_load_microcode(struct radeon_device *rdev) 1083static void r100_cp_load_microcode(struct radeon_device *rdev)
1054{ 1084{
1055 const __be32 *fw_data; 1085 const __be32 *fw_data;
@@ -1102,7 +1132,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1102 ring_size = (1 << (rb_bufsz + 1)) * 4; 1132 ring_size = (1 << (rb_bufsz + 1)) * 4;
1103 r100_cp_load_microcode(rdev); 1133 r100_cp_load_microcode(rdev);
1104 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1134 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1105 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1106 RADEON_CP_PACKET2); 1135 RADEON_CP_PACKET2);
1107 if (r) { 1136 if (r) {
1108 return r; 1137 return r;
@@ -3913,6 +3942,8 @@ int r100_resume(struct radeon_device *rdev)
3913 /* Initialize surface registers */ 3942 /* Initialize surface registers */
3914 radeon_surface_init(rdev); 3943 radeon_surface_init(rdev);
3915 3944
3945 radeon_pm_resume(rdev);
3946
3916 rdev->accel_working = true; 3947 rdev->accel_working = true;
3917 r = r100_startup(rdev); 3948 r = r100_startup(rdev);
3918 if (r) { 3949 if (r) {
@@ -3923,6 +3954,7 @@ int r100_resume(struct radeon_device *rdev)
3923 3954
3924int r100_suspend(struct radeon_device *rdev) 3955int r100_suspend(struct radeon_device *rdev)
3925{ 3956{
3957 radeon_pm_suspend(rdev);
3926 r100_cp_disable(rdev); 3958 r100_cp_disable(rdev);
3927 radeon_wb_disable(rdev); 3959 radeon_wb_disable(rdev);
3928 r100_irq_disable(rdev); 3960 r100_irq_disable(rdev);
@@ -3933,6 +3965,7 @@ int r100_suspend(struct radeon_device *rdev)
3933 3965
3934void r100_fini(struct radeon_device *rdev) 3966void r100_fini(struct radeon_device *rdev)
3935{ 3967{
3968 radeon_pm_fini(rdev);
3936 r100_cp_fini(rdev); 3969 r100_cp_fini(rdev);
3937 radeon_wb_fini(rdev); 3970 radeon_wb_fini(rdev);
3938 radeon_ib_pool_fini(rdev); 3971 radeon_ib_pool_fini(rdev);
@@ -4039,6 +4072,9 @@ int r100_init(struct radeon_device *rdev)
4039 } 4072 }
4040 r100_set_safe_registers(rdev); 4073 r100_set_safe_registers(rdev);
4041 4074
4075 /* Initialize power management */
4076 radeon_pm_init(rdev);
4077
4042 rdev->accel_working = true; 4078 rdev->accel_working = true;
4043 r = r100_startup(rdev); 4079 r = r100_startup(rdev);
4044 if (r) { 4080 if (r) {
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index d8dd269b9159..7c63ef840e86 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1430,6 +1430,8 @@ int r300_resume(struct radeon_device *rdev)
1430 /* Initialize surface registers */ 1430 /* Initialize surface registers */
1431 radeon_surface_init(rdev); 1431 radeon_surface_init(rdev);
1432 1432
1433 radeon_pm_resume(rdev);
1434
1433 rdev->accel_working = true; 1435 rdev->accel_working = true;
1434 r = r300_startup(rdev); 1436 r = r300_startup(rdev);
1435 if (r) { 1437 if (r) {
@@ -1440,6 +1442,7 @@ int r300_resume(struct radeon_device *rdev)
1440 1442
1441int r300_suspend(struct radeon_device *rdev) 1443int r300_suspend(struct radeon_device *rdev)
1442{ 1444{
1445 radeon_pm_suspend(rdev);
1443 r100_cp_disable(rdev); 1446 r100_cp_disable(rdev);
1444 radeon_wb_disable(rdev); 1447 radeon_wb_disable(rdev);
1445 r100_irq_disable(rdev); 1448 r100_irq_disable(rdev);
@@ -1452,6 +1455,7 @@ int r300_suspend(struct radeon_device *rdev)
1452 1455
1453void r300_fini(struct radeon_device *rdev) 1456void r300_fini(struct radeon_device *rdev)
1454{ 1457{
1458 radeon_pm_fini(rdev);
1455 r100_cp_fini(rdev); 1459 r100_cp_fini(rdev);
1456 radeon_wb_fini(rdev); 1460 radeon_wb_fini(rdev);
1457 radeon_ib_pool_fini(rdev); 1461 radeon_ib_pool_fini(rdev);
@@ -1538,6 +1542,9 @@ int r300_init(struct radeon_device *rdev)
1538 } 1542 }
1539 r300_set_reg_safe(rdev); 1543 r300_set_reg_safe(rdev);
1540 1544
1545 /* Initialize power management */
1546 radeon_pm_init(rdev);
1547
1541 rdev->accel_working = true; 1548 rdev->accel_working = true;
1542 r = r300_startup(rdev); 1549 r = r300_startup(rdev);
1543 if (r) { 1550 if (r) {
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
index 60170ea5e3a2..84b1d5367a11 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -75,7 +75,7 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); 75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
76 76
77 for (i = 0; i < nr; ++i) { 77 for (i = 0; i < nr; ++i) {
78 if (DRM_COPY_FROM_USER 78 if (copy_from_user
79 (&box, &cmdbuf->boxes[n + i], sizeof(box))) { 79 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
80 DRM_ERROR("copy cliprect faulted\n"); 80 DRM_ERROR("copy cliprect faulted\n");
81 return -EFAULT; 81 return -EFAULT;
@@ -928,12 +928,12 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
928 buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); 928 buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
929 *buf_idx *= 2; /* 8 bytes per buf */ 929 *buf_idx *= 2; /* 8 bytes per buf */
930 930
931 if (DRM_COPY_TO_USER(ref_age_base + *buf_idx, 931 if (copy_to_user(ref_age_base + *buf_idx,
932 &dev_priv->scratch_ages[header.scratch.reg], 932 &dev_priv->scratch_ages[header.scratch.reg],
933 sizeof(u32))) 933 sizeof(u32)))
934 return -EINVAL; 934 return -EINVAL;
935 935
936 if (DRM_COPY_FROM_USER(&h_pending, 936 if (copy_from_user(&h_pending,
937 ref_age_base + *buf_idx + 1, 937 ref_age_base + *buf_idx + 1,
938 sizeof(u32))) 938 sizeof(u32)))
939 return -EINVAL; 939 return -EINVAL;
@@ -943,7 +943,7 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
943 943
944 h_pending--; 944 h_pending--;
945 945
946 if (DRM_COPY_TO_USER(ref_age_base + *buf_idx + 1, 946 if (copy_to_user(ref_age_base + *buf_idx + 1,
947 &h_pending, 947 &h_pending,
948 sizeof(u32))) 948 sizeof(u32)))
949 return -EINVAL; 949 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 6edf2b3a52b4..3768aab2710b 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -325,6 +325,8 @@ int r420_resume(struct radeon_device *rdev)
325 /* Initialize surface registers */ 325 /* Initialize surface registers */
326 radeon_surface_init(rdev); 326 radeon_surface_init(rdev);
327 327
328 radeon_pm_resume(rdev);
329
328 rdev->accel_working = true; 330 rdev->accel_working = true;
329 r = r420_startup(rdev); 331 r = r420_startup(rdev);
330 if (r) { 332 if (r) {
@@ -335,6 +337,7 @@ int r420_resume(struct radeon_device *rdev)
335 337
336int r420_suspend(struct radeon_device *rdev) 338int r420_suspend(struct radeon_device *rdev)
337{ 339{
340 radeon_pm_suspend(rdev);
338 r420_cp_errata_fini(rdev); 341 r420_cp_errata_fini(rdev);
339 r100_cp_disable(rdev); 342 r100_cp_disable(rdev);
340 radeon_wb_disable(rdev); 343 radeon_wb_disable(rdev);
@@ -348,6 +351,7 @@ int r420_suspend(struct radeon_device *rdev)
348 351
349void r420_fini(struct radeon_device *rdev) 352void r420_fini(struct radeon_device *rdev)
350{ 353{
354 radeon_pm_fini(rdev);
351 r100_cp_fini(rdev); 355 r100_cp_fini(rdev);
352 radeon_wb_fini(rdev); 356 radeon_wb_fini(rdev);
353 radeon_ib_pool_fini(rdev); 357 radeon_ib_pool_fini(rdev);
@@ -444,6 +448,9 @@ int r420_init(struct radeon_device *rdev)
444 } 448 }
445 r420_set_reg_safe(rdev); 449 r420_set_reg_safe(rdev);
446 450
451 /* Initialize power management */
452 radeon_pm_init(rdev);
453
447 rdev->accel_working = true; 454 rdev->accel_working = true;
448 r = r420_startup(rdev); 455 r = r420_startup(rdev);
449 if (r) { 456 if (r) {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index e1aece73b370..e209eb75024f 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -240,6 +240,8 @@ int r520_resume(struct radeon_device *rdev)
240 /* Initialize surface registers */ 240 /* Initialize surface registers */
241 radeon_surface_init(rdev); 241 radeon_surface_init(rdev);
242 242
243 radeon_pm_resume(rdev);
244
243 rdev->accel_working = true; 245 rdev->accel_working = true;
244 r = r520_startup(rdev); 246 r = r520_startup(rdev);
245 if (r) { 247 if (r) {
@@ -312,6 +314,9 @@ int r520_init(struct radeon_device *rdev)
312 return r; 314 return r;
313 rv515_set_safe_registers(rdev); 315 rv515_set_safe_registers(rdev);
314 316
317 /* Initialize power management */
318 radeon_pm_init(rdev);
319
315 rdev->accel_working = true; 320 rdev->accel_working = true;
316 r = r520_startup(rdev); 321 r = r520_startup(rdev);
317 if (r) { 322 if (r) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 9ad06732a78b..56140b4e5bb2 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -105,6 +105,7 @@ void r600_fini(struct radeon_device *rdev);
105void r600_irq_disable(struct radeon_device *rdev); 105void r600_irq_disable(struct radeon_device *rdev);
106static void r600_pcie_gen2_enable(struct radeon_device *rdev); 106static void r600_pcie_gen2_enable(struct radeon_device *rdev);
107extern int evergreen_rlc_resume(struct radeon_device *rdev); 107extern int evergreen_rlc_resume(struct radeon_device *rdev);
108extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
108 109
109/** 110/**
110 * r600_get_xclk - get the xclk 111 * r600_get_xclk - get the xclk
@@ -1644,6 +1645,67 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1644 r600_print_gpu_status_regs(rdev); 1645 r600_print_gpu_status_regs(rdev);
1645} 1646}
1646 1647
1648static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1649{
1650 struct rv515_mc_save save;
1651 u32 tmp, i;
1652
1653 dev_info(rdev->dev, "GPU pci config reset\n");
1654
1655 /* disable dpm? */
1656
1657 /* Disable CP parsing/prefetching */
1658 if (rdev->family >= CHIP_RV770)
1659 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1660 else
1661 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1662
1663 /* disable the RLC */
1664 WREG32(RLC_CNTL, 0);
1665
1666 /* Disable DMA */
1667 tmp = RREG32(DMA_RB_CNTL);
1668 tmp &= ~DMA_RB_ENABLE;
1669 WREG32(DMA_RB_CNTL, tmp);
1670
1671 mdelay(50);
1672
1673 /* set mclk/sclk to bypass */
1674 if (rdev->family >= CHIP_RV770)
1675 rv770_set_clk_bypass_mode(rdev);
1676 /* disable BM */
1677 pci_clear_master(rdev->pdev);
1678 /* disable mem access */
1679 rv515_mc_stop(rdev, &save);
1680 if (r600_mc_wait_for_idle(rdev)) {
1681 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1682 }
1683
1684 /* BIF reset workaround. Not sure if this is needed on 6xx */
1685 tmp = RREG32(BUS_CNTL);
1686 tmp |= VGA_COHE_SPEC_TIMER_DIS;
1687 WREG32(BUS_CNTL, tmp);
1688
1689 tmp = RREG32(BIF_SCRATCH0);
1690
1691 /* reset */
1692 radeon_pci_config_reset(rdev);
1693 mdelay(1);
1694
1695 /* BIF reset workaround. Not sure if this is needed on 6xx */
1696 tmp = SOFT_RESET_BIF;
1697 WREG32(SRBM_SOFT_RESET, tmp);
1698 mdelay(1);
1699 WREG32(SRBM_SOFT_RESET, 0);
1700
1701 /* wait for asic to come out of reset */
1702 for (i = 0; i < rdev->usec_timeout; i++) {
1703 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1704 break;
1705 udelay(1);
1706 }
1707}
1708
1647int r600_asic_reset(struct radeon_device *rdev) 1709int r600_asic_reset(struct radeon_device *rdev)
1648{ 1710{
1649 u32 reset_mask; 1711 u32 reset_mask;
@@ -1653,10 +1715,17 @@ int r600_asic_reset(struct radeon_device *rdev)
1653 if (reset_mask) 1715 if (reset_mask)
1654 r600_set_bios_scratch_engine_hung(rdev, true); 1716 r600_set_bios_scratch_engine_hung(rdev, true);
1655 1717
1718 /* try soft reset */
1656 r600_gpu_soft_reset(rdev, reset_mask); 1719 r600_gpu_soft_reset(rdev, reset_mask);
1657 1720
1658 reset_mask = r600_gpu_check_soft_reset(rdev); 1721 reset_mask = r600_gpu_check_soft_reset(rdev);
1659 1722
1723 /* try pci config reset */
1724 if (reset_mask && radeon_hard_reset)
1725 r600_gpu_pci_config_reset(rdev);
1726
1727 reset_mask = r600_gpu_check_soft_reset(rdev);
1728
1660 if (!reset_mask) 1729 if (!reset_mask)
1661 r600_set_bios_scratch_engine_hung(rdev, false); 1730 r600_set_bios_scratch_engine_hung(rdev, false);
1662 1731
@@ -2185,7 +2254,8 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2185 */ 2254 */
2186void r600_cp_stop(struct radeon_device *rdev) 2255void r600_cp_stop(struct radeon_device *rdev)
2187{ 2256{
2188 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2257 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2258 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2189 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 2259 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2190 WREG32(SCRATCH_UMSK, 0); 2260 WREG32(SCRATCH_UMSK, 0);
2191 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2261 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -2382,6 +2452,36 @@ out:
2382 return err; 2452 return err;
2383} 2453}
2384 2454
2455u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2456 struct radeon_ring *ring)
2457{
2458 u32 rptr;
2459
2460 if (rdev->wb.enabled)
2461 rptr = rdev->wb.wb[ring->rptr_offs/4];
2462 else
2463 rptr = RREG32(R600_CP_RB_RPTR);
2464
2465 return rptr;
2466}
2467
2468u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2469 struct radeon_ring *ring)
2470{
2471 u32 wptr;
2472
2473 wptr = RREG32(R600_CP_RB_WPTR);
2474
2475 return wptr;
2476}
2477
2478void r600_gfx_set_wptr(struct radeon_device *rdev,
2479 struct radeon_ring *ring)
2480{
2481 WREG32(R600_CP_RB_WPTR, ring->wptr);
2482 (void)RREG32(R600_CP_RB_WPTR);
2483}
2484
2385static int r600_cp_load_microcode(struct radeon_device *rdev) 2485static int r600_cp_load_microcode(struct radeon_device *rdev)
2386{ 2486{
2387 const __be32 *fw_data; 2487 const __be32 *fw_data;
@@ -2513,6 +2613,10 @@ int r600_cp_resume(struct radeon_device *rdev)
2513 ring->ready = false; 2613 ring->ready = false;
2514 return r; 2614 return r;
2515 } 2615 }
2616
2617 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2618 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2619
2516 return 0; 2620 return 0;
2517} 2621}
2518 2622
@@ -2607,14 +2711,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2607 struct radeon_fence *fence) 2711 struct radeon_fence *fence)
2608{ 2712{
2609 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2713 struct radeon_ring *ring = &rdev->ring[fence->ring];
2714 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2715 PACKET3_SH_ACTION_ENA;
2716
2717 if (rdev->family >= CHIP_RV770)
2718 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2610 2719
2611 if (rdev->wb.use_event) { 2720 if (rdev->wb.use_event) {
2612 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2721 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2613 /* flush read cache over gart */ 2722 /* flush read cache over gart */
2614 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2723 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2615 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2724 radeon_ring_write(ring, cp_coher_cntl);
2616 PACKET3_VC_ACTION_ENA |
2617 PACKET3_SH_ACTION_ENA);
2618 radeon_ring_write(ring, 0xFFFFFFFF); 2725 radeon_ring_write(ring, 0xFFFFFFFF);
2619 radeon_ring_write(ring, 0); 2726 radeon_ring_write(ring, 0);
2620 radeon_ring_write(ring, 10); /* poll interval */ 2727 radeon_ring_write(ring, 10); /* poll interval */
@@ -2628,9 +2735,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2628 } else { 2735 } else {
2629 /* flush read cache over gart */ 2736 /* flush read cache over gart */
2630 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2737 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2631 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2738 radeon_ring_write(ring, cp_coher_cntl);
2632 PACKET3_VC_ACTION_ENA |
2633 PACKET3_SH_ACTION_ENA);
2634 radeon_ring_write(ring, 0xFFFFFFFF); 2739 radeon_ring_write(ring, 0xFFFFFFFF);
2635 radeon_ring_write(ring, 0); 2740 radeon_ring_write(ring, 0);
2636 radeon_ring_write(ring, 10); /* poll interval */ 2741 radeon_ring_write(ring, 10); /* poll interval */
@@ -2775,14 +2880,6 @@ static int r600_startup(struct radeon_device *rdev)
2775 2880
2776 r600_mc_program(rdev); 2881 r600_mc_program(rdev);
2777 2882
2778 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2779 r = r600_init_microcode(rdev);
2780 if (r) {
2781 DRM_ERROR("Failed to load firmware!\n");
2782 return r;
2783 }
2784 }
2785
2786 if (rdev->flags & RADEON_IS_AGP) { 2883 if (rdev->flags & RADEON_IS_AGP) {
2787 r600_agp_enable(rdev); 2884 r600_agp_enable(rdev);
2788 } else { 2885 } else {
@@ -2803,12 +2900,6 @@ static int r600_startup(struct radeon_device *rdev)
2803 return r; 2900 return r;
2804 } 2901 }
2805 2902
2806 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2807 if (r) {
2808 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2809 return r;
2810 }
2811
2812 /* Enable IRQ */ 2903 /* Enable IRQ */
2813 if (!rdev->irq.installed) { 2904 if (!rdev->irq.installed) {
2814 r = radeon_irq_kms_init(rdev); 2905 r = radeon_irq_kms_init(rdev);
@@ -2826,18 +2917,10 @@ static int r600_startup(struct radeon_device *rdev)
2826 2917
2827 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2918 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2828 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2919 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2829 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2830 RADEON_CP_PACKET2); 2920 RADEON_CP_PACKET2);
2831 if (r) 2921 if (r)
2832 return r; 2922 return r;
2833 2923
2834 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2835 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2836 DMA_RB_RPTR, DMA_RB_WPTR,
2837 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2838 if (r)
2839 return r;
2840
2841 r = r600_cp_load_microcode(rdev); 2924 r = r600_cp_load_microcode(rdev);
2842 if (r) 2925 if (r)
2843 return r; 2926 return r;
@@ -2845,10 +2928,6 @@ static int r600_startup(struct radeon_device *rdev)
2845 if (r) 2928 if (r)
2846 return r; 2929 return r;
2847 2930
2848 r = r600_dma_resume(rdev);
2849 if (r)
2850 return r;
2851
2852 r = radeon_ib_pool_init(rdev); 2931 r = radeon_ib_pool_init(rdev);
2853 if (r) { 2932 if (r) {
2854 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2933 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -2889,6 +2968,8 @@ int r600_resume(struct radeon_device *rdev)
2889 /* post card */ 2968 /* post card */
2890 atom_asic_init(rdev->mode_info.atom_context); 2969 atom_asic_init(rdev->mode_info.atom_context);
2891 2970
2971 radeon_pm_resume(rdev);
2972
2892 rdev->accel_working = true; 2973 rdev->accel_working = true;
2893 r = r600_startup(rdev); 2974 r = r600_startup(rdev);
2894 if (r) { 2975 if (r) {
@@ -2902,9 +2983,9 @@ int r600_resume(struct radeon_device *rdev)
2902 2983
2903int r600_suspend(struct radeon_device *rdev) 2984int r600_suspend(struct radeon_device *rdev)
2904{ 2985{
2986 radeon_pm_suspend(rdev);
2905 r600_audio_fini(rdev); 2987 r600_audio_fini(rdev);
2906 r600_cp_stop(rdev); 2988 r600_cp_stop(rdev);
2907 r600_dma_stop(rdev);
2908 r600_irq_suspend(rdev); 2989 r600_irq_suspend(rdev);
2909 radeon_wb_disable(rdev); 2990 radeon_wb_disable(rdev);
2910 r600_pcie_gart_disable(rdev); 2991 r600_pcie_gart_disable(rdev);
@@ -2970,12 +3051,20 @@ int r600_init(struct radeon_device *rdev)
2970 if (r) 3051 if (r)
2971 return r; 3052 return r;
2972 3053
3054 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3055 r = r600_init_microcode(rdev);
3056 if (r) {
3057 DRM_ERROR("Failed to load firmware!\n");
3058 return r;
3059 }
3060 }
3061
3062 /* Initialize power management */
3063 radeon_pm_init(rdev);
3064
2973 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3065 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2974 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3066 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2975 3067
2976 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2977 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2978
2979 rdev->ih.ring_obj = NULL; 3068 rdev->ih.ring_obj = NULL;
2980 r600_ih_ring_init(rdev, 64 * 1024); 3069 r600_ih_ring_init(rdev, 64 * 1024);
2981 3070
@@ -2988,7 +3077,6 @@ int r600_init(struct radeon_device *rdev)
2988 if (r) { 3077 if (r) {
2989 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3078 dev_err(rdev->dev, "disabling GPU acceleration\n");
2990 r600_cp_fini(rdev); 3079 r600_cp_fini(rdev);
2991 r600_dma_fini(rdev);
2992 r600_irq_fini(rdev); 3080 r600_irq_fini(rdev);
2993 radeon_wb_fini(rdev); 3081 radeon_wb_fini(rdev);
2994 radeon_ib_pool_fini(rdev); 3082 radeon_ib_pool_fini(rdev);
@@ -3002,9 +3090,9 @@ int r600_init(struct radeon_device *rdev)
3002 3090
3003void r600_fini(struct radeon_device *rdev) 3091void r600_fini(struct radeon_device *rdev)
3004{ 3092{
3093 radeon_pm_fini(rdev);
3005 r600_audio_fini(rdev); 3094 r600_audio_fini(rdev);
3006 r600_cp_fini(rdev); 3095 r600_cp_fini(rdev);
3007 r600_dma_fini(rdev);
3008 r600_irq_fini(rdev); 3096 r600_irq_fini(rdev);
3009 radeon_wb_fini(rdev); 3097 radeon_wb_fini(rdev);
3010 radeon_ib_pool_fini(rdev); 3098 radeon_ib_pool_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index d8eb48bff0ed..8c9b7e26533c 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -2515,7 +2515,7 @@ int r600_cp_dispatch_texture(struct drm_device *dev,
2515 buf = radeon_freelist_get(dev); 2515 buf = radeon_freelist_get(dev);
2516 if (!buf) { 2516 if (!buf) {
2517 DRM_DEBUG("EAGAIN\n"); 2517 DRM_DEBUG("EAGAIN\n");
2518 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 2518 if (copy_to_user(tex->image, image, sizeof(*image)))
2519 return -EFAULT; 2519 return -EFAULT;
2520 return -EAGAIN; 2520 return -EAGAIN;
2521 } 2521 }
@@ -2528,7 +2528,7 @@ int r600_cp_dispatch_texture(struct drm_device *dev,
2528 buffer = 2528 buffer =
2529 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 2529 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2530 2530
2531 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 2531 if (copy_from_user(buffer, data, pass_size)) {
2532 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 2532 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2533 return -EFAULT; 2533 return -EFAULT;
2534 } 2534 }
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 5dceea6f71ae..7b399dc5fd54 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -749,7 +749,10 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
749 } 749 }
750 750
751 for (i = 0; i < 8; i++) { 751 for (i = 0; i < 8; i++) {
752 if ((tmp >> (i * 4)) & 0xF) { 752 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
753
754 if (format != V_0280A0_COLOR_INVALID &&
755 (tmp >> (i * 4)) & 0xF) {
753 /* at least one component is enabled */ 756 /* at least one component is enabled */
754 if (track->cb_color_bo[i] == NULL) { 757 if (track->cb_color_bo[i] == NULL) {
755 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 758 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
@@ -2386,7 +2389,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2386 ib_chunk = &parser.chunks[parser.chunk_ib_idx]; 2389 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2387 parser.ib.length_dw = ib_chunk->length_dw; 2390 parser.ib.length_dw = ib_chunk->length_dw;
2388 *l = parser.ib.length_dw; 2391 *l = parser.ib.length_dw;
2389 if (DRM_COPY_FROM_USER(ib, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) { 2392 if (copy_from_user(ib, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) {
2390 r = -EFAULT; 2393 r = -EFAULT;
2391 r600_cs_parser_fini(&parser, r); 2394 r600_cs_parser_fini(&parser, r);
2392 return r; 2395 return r;
diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c
index 7844d15c139f..b2d4c91e6272 100644
--- a/drivers/gpu/drm/radeon/r600_dma.c
+++ b/drivers/gpu/drm/radeon/r600_dma.c
@@ -51,7 +51,14 @@ u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);
51uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 51uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
52 struct radeon_ring *ring) 52 struct radeon_ring *ring)
53{ 53{
54 return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2; 54 u32 rptr;
55
56 if (rdev->wb.enabled)
57 rptr = rdev->wb.wb[ring->rptr_offs/4];
58 else
59 rptr = RREG32(DMA_RB_RPTR);
60
61 return (rptr & 0x3fffc) >> 2;
55} 62}
56 63
57/** 64/**
@@ -65,7 +72,7 @@ uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
65uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 72uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
66 struct radeon_ring *ring) 73 struct radeon_ring *ring)
67{ 74{
68 return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2; 75 return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
69} 76}
70 77
71/** 78/**
@@ -79,7 +86,7 @@ uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
79void r600_dma_set_wptr(struct radeon_device *rdev, 86void r600_dma_set_wptr(struct radeon_device *rdev,
80 struct radeon_ring *ring) 87 struct radeon_ring *ring)
81{ 88{
82 WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc); 89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
83} 90}
84 91
85/** 92/**
@@ -93,7 +100,8 @@ void r600_dma_stop(struct radeon_device *rdev)
93{ 100{
94 u32 rb_cntl = RREG32(DMA_RB_CNTL); 101 u32 rb_cntl = RREG32(DMA_RB_CNTL);
95 102
96 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 103 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
104 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
97 105
98 rb_cntl &= ~DMA_RB_ENABLE; 106 rb_cntl &= ~DMA_RB_ENABLE;
99 WREG32(DMA_RB_CNTL, rb_cntl); 107 WREG32(DMA_RB_CNTL, rb_cntl);
@@ -180,7 +188,8 @@ int r600_dma_resume(struct radeon_device *rdev)
180 return r; 188 return r;
181 } 189 }
182 190
183 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 191 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
192 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
184 193
185 return 0; 194 return 0;
186} 195}
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 5513d8f06252..e4cc9b314ce9 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -729,8 +729,8 @@ bool r600_is_uvd_state(u32 class, u32 class2)
729 return false; 729 return false;
730} 730}
731 731
732int r600_set_thermal_temperature_range(struct radeon_device *rdev, 732static int r600_set_thermal_temperature_range(struct radeon_device *rdev,
733 int min_temp, int max_temp) 733 int min_temp, int max_temp)
734{ 734{
735 int low_temp = 0 * 1000; 735 int low_temp = 0 * 1000;
736 int high_temp = 255 * 1000; 736 int high_temp = 255 * 1000;
@@ -777,6 +777,22 @@ bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
777 } 777 }
778} 778}
779 779
780int r600_dpm_late_enable(struct radeon_device *rdev)
781{
782 int ret;
783
784 if (rdev->irq.installed &&
785 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
786 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
787 if (ret)
788 return ret;
789 rdev->irq.dpm_thermal = true;
790 radeon_irq_set(rdev);
791 }
792
793 return 0;
794}
795
780union power_info { 796union power_info {
781 struct _ATOM_POWERPLAY_INFO info; 797 struct _ATOM_POWERPLAY_INFO info;
782 struct _ATOM_POWERPLAY_INFO_V2 info_2; 798 struct _ATOM_POWERPLAY_INFO_V2 info_2;
diff --git a/drivers/gpu/drm/radeon/r600_dpm.h b/drivers/gpu/drm/radeon/r600_dpm.h
index 1000bf9719f2..07eab2b04e81 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.h
+++ b/drivers/gpu/drm/radeon/r600_dpm.h
@@ -213,8 +213,6 @@ void r600_wait_for_power_level(struct radeon_device *rdev,
213void r600_start_dpm(struct radeon_device *rdev); 213void r600_start_dpm(struct radeon_device *rdev);
214void r600_stop_dpm(struct radeon_device *rdev); 214void r600_stop_dpm(struct radeon_device *rdev);
215 215
216int r600_set_thermal_temperature_range(struct radeon_device *rdev,
217 int min_temp, int max_temp);
218bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor); 216bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor);
219 217
220int r600_parse_extended_power_table(struct radeon_device *rdev); 218int r600_parse_extended_power_table(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index b7d3ecba43e3..3016fc14f502 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -250,7 +250,7 @@ static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
250 value, ~HDMI0_AUDIO_TEST_EN); 250 value, ~HDMI0_AUDIO_TEST_EN);
251} 251}
252 252
253void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) 253static void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
254{ 254{
255 struct drm_device *dev = encoder->dev; 255 struct drm_device *dev = encoder->dev;
256 struct radeon_device *rdev = dev->dev_private; 256 struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index ebe38724a976..37455f65107f 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -701,11 +701,18 @@
701#define RLC_UCODE_DATA 0x3f30 701#define RLC_UCODE_DATA 0x3f30
702 702
703#define SRBM_SOFT_RESET 0xe60 703#define SRBM_SOFT_RESET 0xe60
704# define SOFT_RESET_BIF (1 << 1)
704# define SOFT_RESET_DMA (1 << 12) 705# define SOFT_RESET_DMA (1 << 12)
705# define SOFT_RESET_RLC (1 << 13) 706# define SOFT_RESET_RLC (1 << 13)
706# define SOFT_RESET_UVD (1 << 18) 707# define SOFT_RESET_UVD (1 << 18)
707# define RV770_SOFT_RESET_DMA (1 << 20) 708# define RV770_SOFT_RESET_DMA (1 << 20)
708 709
710#define BIF_SCRATCH0 0x5438
711
712#define BUS_CNTL 0x5420
713# define BIOS_ROM_DIS (1 << 1)
714# define VGA_COHE_SPEC_TIMER_DIS (1 << 9)
715
709#define CP_INT_CNTL 0xc124 716#define CP_INT_CNTL 0xc124
710# define CNTX_BUSY_INT_ENABLE (1 << 19) 717# define CNTX_BUSY_INT_ENABLE (1 << 19)
711# define CNTX_EMPTY_INT_ENABLE (1 << 20) 718# define CNTX_EMPTY_INT_ENABLE (1 << 20)
@@ -1575,6 +1582,7 @@
1575# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1582# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1576#define PACKET3_SURFACE_SYNC 0x43 1583#define PACKET3_SURFACE_SYNC 0x43
1577# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1584# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1585# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
1578# define PACKET3_TC_ACTION_ENA (1 << 23) 1586# define PACKET3_TC_ACTION_ENA (1 << 23)
1579# define PACKET3_VC_ACTION_ENA (1 << 24) 1587# define PACKET3_VC_ACTION_ENA (1 << 24)
1580# define PACKET3_CB_ACTION_ENA (1 << 25) 1588# define PACKET3_CB_ACTION_ENA (1 << 25)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 45e1f447bc79..4a8ac1cd6b4c 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -99,6 +99,7 @@ extern int radeon_fastfb;
99extern int radeon_dpm; 99extern int radeon_dpm;
100extern int radeon_aspm; 100extern int radeon_aspm;
101extern int radeon_runtime_pm; 101extern int radeon_runtime_pm;
102extern int radeon_hard_reset;
102 103
103/* 104/*
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting 105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -139,6 +140,9 @@ extern int radeon_runtime_pm;
139#define RADEON_VA_RESERVED_SIZE (8 << 20) 140#define RADEON_VA_RESERVED_SIZE (8 << 20)
140#define RADEON_IB_VM_MAX_SIZE (64 << 10) 141#define RADEON_IB_VM_MAX_SIZE (64 << 10)
141 142
143/* hard reset data */
144#define RADEON_ASIC_RESET_DATA 0x39d5e86b
145
142/* reset flags */ 146/* reset flags */
143#define RADEON_RESET_GFX (1 << 0) 147#define RADEON_RESET_GFX (1 << 0)
144#define RADEON_RESET_COMPUTE (1 << 1) 148#define RADEON_RESET_COMPUTE (1 << 1)
@@ -252,6 +256,7 @@ struct radeon_clock {
252 * Power management 256 * Power management
253 */ 257 */
254int radeon_pm_init(struct radeon_device *rdev); 258int radeon_pm_init(struct radeon_device *rdev);
259int radeon_pm_late_init(struct radeon_device *rdev);
255void radeon_pm_fini(struct radeon_device *rdev); 260void radeon_pm_fini(struct radeon_device *rdev);
256void radeon_pm_compute_clocks(struct radeon_device *rdev); 261void radeon_pm_compute_clocks(struct radeon_device *rdev);
257void radeon_pm_suspend(struct radeon_device *rdev); 262void radeon_pm_suspend(struct radeon_device *rdev);
@@ -413,6 +418,11 @@ struct radeon_mman {
413 struct ttm_bo_device bdev; 418 struct ttm_bo_device bdev;
414 bool mem_global_referenced; 419 bool mem_global_referenced;
415 bool initialized; 420 bool initialized;
421
422#if defined(CONFIG_DEBUG_FS)
423 struct dentry *vram;
424 struct dentry *gtt;
425#endif
416}; 426};
417 427
418/* bo virtual address in a specific vm */ 428/* bo virtual address in a specific vm */
@@ -779,13 +789,11 @@ struct radeon_ring {
779 volatile uint32_t *ring; 789 volatile uint32_t *ring;
780 unsigned rptr; 790 unsigned rptr;
781 unsigned rptr_offs; 791 unsigned rptr_offs;
782 unsigned rptr_reg;
783 unsigned rptr_save_reg; 792 unsigned rptr_save_reg;
784 u64 next_rptr_gpu_addr; 793 u64 next_rptr_gpu_addr;
785 volatile u32 *next_rptr_cpu_addr; 794 volatile u32 *next_rptr_cpu_addr;
786 unsigned wptr; 795 unsigned wptr;
787 unsigned wptr_old; 796 unsigned wptr_old;
788 unsigned wptr_reg;
789 unsigned ring_size; 797 unsigned ring_size;
790 unsigned ring_free_dw; 798 unsigned ring_free_dw;
791 int count_dw; 799 int count_dw;
@@ -859,6 +867,8 @@ struct radeon_vm {
859 struct radeon_fence *fence; 867 struct radeon_fence *fence;
860 /* last flush or NULL if we still need to flush */ 868 /* last flush or NULL if we still need to flush */
861 struct radeon_fence *last_flush; 869 struct radeon_fence *last_flush;
870 /* last use of vmid */
871 struct radeon_fence *last_id_use;
862}; 872};
863 873
864struct radeon_vm_manager { 874struct radeon_vm_manager {
@@ -949,7 +959,7 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring
949int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 959int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
950 unsigned size, uint32_t *data); 960 unsigned size, uint32_t *data);
951int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 961int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
952 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop); 962 unsigned rptr_offs, u32 nop);
953void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 963void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
954 964
955 965
@@ -1775,6 +1785,7 @@ struct radeon_asic {
1775 int (*init)(struct radeon_device *rdev); 1785 int (*init)(struct radeon_device *rdev);
1776 void (*setup_asic)(struct radeon_device *rdev); 1786 void (*setup_asic)(struct radeon_device *rdev);
1777 int (*enable)(struct radeon_device *rdev); 1787 int (*enable)(struct radeon_device *rdev);
1788 int (*late_enable)(struct radeon_device *rdev);
1778 void (*disable)(struct radeon_device *rdev); 1789 void (*disable)(struct radeon_device *rdev);
1779 int (*pre_set_power_state)(struct radeon_device *rdev); 1790 int (*pre_set_power_state)(struct radeon_device *rdev);
1780 int (*set_power_state)(struct radeon_device *rdev); 1791 int (*set_power_state)(struct radeon_device *rdev);
@@ -2650,6 +2661,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2650#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2661#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2651#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2662#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2652#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2663#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2664#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2653#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2665#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2654#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2666#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2655#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2667#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
@@ -2668,6 +2680,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2668/* Common functions */ 2680/* Common functions */
2669/* AGP */ 2681/* AGP */
2670extern int radeon_gpu_reset(struct radeon_device *rdev); 2682extern int radeon_gpu_reset(struct radeon_device *rdev);
2683extern void radeon_pci_config_reset(struct radeon_device *rdev);
2671extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2684extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2672extern void radeon_agp_disable(struct radeon_device *rdev); 2685extern void radeon_agp_disable(struct radeon_device *rdev);
2673extern int radeon_modeset_init(struct radeon_device *rdev); 2686extern int radeon_modeset_init(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index c0425bb6223a..f74db43346fd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -182,9 +182,9 @@ static struct radeon_asic_ring r100_gfx_ring = {
182 .ring_test = &r100_ring_test, 182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test, 183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup, 184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &radeon_ring_generic_get_rptr, 185 .get_rptr = &r100_gfx_get_rptr,
186 .get_wptr = &radeon_ring_generic_get_wptr, 186 .get_wptr = &r100_gfx_get_wptr,
187 .set_wptr = &radeon_ring_generic_set_wptr, 187 .set_wptr = &r100_gfx_set_wptr,
188}; 188};
189 189
190static struct radeon_asic r100_asic = { 190static struct radeon_asic r100_asic = {
@@ -330,9 +330,9 @@ static struct radeon_asic_ring r300_gfx_ring = {
330 .ring_test = &r100_ring_test, 330 .ring_test = &r100_ring_test,
331 .ib_test = &r100_ib_test, 331 .ib_test = &r100_ib_test,
332 .is_lockup = &r100_gpu_is_lockup, 332 .is_lockup = &r100_gpu_is_lockup,
333 .get_rptr = &radeon_ring_generic_get_rptr, 333 .get_rptr = &r100_gfx_get_rptr,
334 .get_wptr = &radeon_ring_generic_get_wptr, 334 .get_wptr = &r100_gfx_get_wptr,
335 .set_wptr = &radeon_ring_generic_set_wptr, 335 .set_wptr = &r100_gfx_set_wptr,
336}; 336};
337 337
338static struct radeon_asic r300_asic = { 338static struct radeon_asic r300_asic = {
@@ -883,9 +883,9 @@ static struct radeon_asic_ring r600_gfx_ring = {
883 .ring_test = &r600_ring_test, 883 .ring_test = &r600_ring_test,
884 .ib_test = &r600_ib_test, 884 .ib_test = &r600_ib_test,
885 .is_lockup = &r600_gfx_is_lockup, 885 .is_lockup = &r600_gfx_is_lockup,
886 .get_rptr = &radeon_ring_generic_get_rptr, 886 .get_rptr = &r600_gfx_get_rptr,
887 .get_wptr = &radeon_ring_generic_get_wptr, 887 .get_wptr = &r600_gfx_get_wptr,
888 .set_wptr = &radeon_ring_generic_set_wptr, 888 .set_wptr = &r600_gfx_set_wptr,
889}; 889};
890 890
891static struct radeon_asic_ring r600_dma_ring = { 891static struct radeon_asic_ring r600_dma_ring = {
@@ -1045,6 +1045,7 @@ static struct radeon_asic rv6xx_asic = {
1045 .init = &rv6xx_dpm_init, 1045 .init = &rv6xx_dpm_init,
1046 .setup_asic = &rv6xx_setup_asic, 1046 .setup_asic = &rv6xx_setup_asic,
1047 .enable = &rv6xx_dpm_enable, 1047 .enable = &rv6xx_dpm_enable,
1048 .late_enable = &r600_dpm_late_enable,
1048 .disable = &rv6xx_dpm_disable, 1049 .disable = &rv6xx_dpm_disable,
1049 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1050 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1050 .set_power_state = &rv6xx_dpm_set_power_state, 1051 .set_power_state = &rv6xx_dpm_set_power_state,
@@ -1135,6 +1136,7 @@ static struct radeon_asic rs780_asic = {
1135 .init = &rs780_dpm_init, 1136 .init = &rs780_dpm_init,
1136 .setup_asic = &rs780_dpm_setup_asic, 1137 .setup_asic = &rs780_dpm_setup_asic,
1137 .enable = &rs780_dpm_enable, 1138 .enable = &rs780_dpm_enable,
1139 .late_enable = &r600_dpm_late_enable,
1138 .disable = &rs780_dpm_disable, 1140 .disable = &rs780_dpm_disable,
1139 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1141 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1140 .set_power_state = &rs780_dpm_set_power_state, 1142 .set_power_state = &rs780_dpm_set_power_state,
@@ -1239,6 +1241,7 @@ static struct radeon_asic rv770_asic = {
1239 .init = &rv770_dpm_init, 1241 .init = &rv770_dpm_init,
1240 .setup_asic = &rv770_dpm_setup_asic, 1242 .setup_asic = &rv770_dpm_setup_asic,
1241 .enable = &rv770_dpm_enable, 1243 .enable = &rv770_dpm_enable,
1244 .late_enable = &rv770_dpm_late_enable,
1242 .disable = &rv770_dpm_disable, 1245 .disable = &rv770_dpm_disable,
1243 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1246 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1244 .set_power_state = &rv770_dpm_set_power_state, 1247 .set_power_state = &rv770_dpm_set_power_state,
@@ -1267,9 +1270,9 @@ static struct radeon_asic_ring evergreen_gfx_ring = {
1267 .ring_test = &r600_ring_test, 1270 .ring_test = &r600_ring_test,
1268 .ib_test = &r600_ib_test, 1271 .ib_test = &r600_ib_test,
1269 .is_lockup = &evergreen_gfx_is_lockup, 1272 .is_lockup = &evergreen_gfx_is_lockup,
1270 .get_rptr = &radeon_ring_generic_get_rptr, 1273 .get_rptr = &r600_gfx_get_rptr,
1271 .get_wptr = &radeon_ring_generic_get_wptr, 1274 .get_wptr = &r600_gfx_get_wptr,
1272 .set_wptr = &radeon_ring_generic_set_wptr, 1275 .set_wptr = &r600_gfx_set_wptr,
1273}; 1276};
1274 1277
1275static struct radeon_asic_ring evergreen_dma_ring = { 1278static struct radeon_asic_ring evergreen_dma_ring = {
@@ -1357,6 +1360,7 @@ static struct radeon_asic evergreen_asic = {
1357 .init = &cypress_dpm_init, 1360 .init = &cypress_dpm_init,
1358 .setup_asic = &cypress_dpm_setup_asic, 1361 .setup_asic = &cypress_dpm_setup_asic,
1359 .enable = &cypress_dpm_enable, 1362 .enable = &cypress_dpm_enable,
1363 .late_enable = &rv770_dpm_late_enable,
1360 .disable = &cypress_dpm_disable, 1364 .disable = &cypress_dpm_disable,
1361 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1365 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1362 .set_power_state = &cypress_dpm_set_power_state, 1366 .set_power_state = &cypress_dpm_set_power_state,
@@ -1449,6 +1453,7 @@ static struct radeon_asic sumo_asic = {
1449 .init = &sumo_dpm_init, 1453 .init = &sumo_dpm_init,
1450 .setup_asic = &sumo_dpm_setup_asic, 1454 .setup_asic = &sumo_dpm_setup_asic,
1451 .enable = &sumo_dpm_enable, 1455 .enable = &sumo_dpm_enable,
1456 .late_enable = &sumo_dpm_late_enable,
1452 .disable = &sumo_dpm_disable, 1457 .disable = &sumo_dpm_disable,
1453 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1458 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1454 .set_power_state = &sumo_dpm_set_power_state, 1459 .set_power_state = &sumo_dpm_set_power_state,
@@ -1540,6 +1545,7 @@ static struct radeon_asic btc_asic = {
1540 .init = &btc_dpm_init, 1545 .init = &btc_dpm_init,
1541 .setup_asic = &btc_dpm_setup_asic, 1546 .setup_asic = &btc_dpm_setup_asic,
1542 .enable = &btc_dpm_enable, 1547 .enable = &btc_dpm_enable,
1548 .late_enable = &rv770_dpm_late_enable,
1543 .disable = &btc_dpm_disable, 1549 .disable = &btc_dpm_disable,
1544 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1550 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1545 .set_power_state = &btc_dpm_set_power_state, 1551 .set_power_state = &btc_dpm_set_power_state,
@@ -1570,9 +1576,9 @@ static struct radeon_asic_ring cayman_gfx_ring = {
1570 .ib_test = &r600_ib_test, 1576 .ib_test = &r600_ib_test,
1571 .is_lockup = &cayman_gfx_is_lockup, 1577 .is_lockup = &cayman_gfx_is_lockup,
1572 .vm_flush = &cayman_vm_flush, 1578 .vm_flush = &cayman_vm_flush,
1573 .get_rptr = &radeon_ring_generic_get_rptr, 1579 .get_rptr = &cayman_gfx_get_rptr,
1574 .get_wptr = &radeon_ring_generic_get_wptr, 1580 .get_wptr = &cayman_gfx_get_wptr,
1575 .set_wptr = &radeon_ring_generic_set_wptr, 1581 .set_wptr = &cayman_gfx_set_wptr,
1576}; 1582};
1577 1583
1578static struct radeon_asic_ring cayman_dma_ring = { 1584static struct radeon_asic_ring cayman_dma_ring = {
@@ -1585,9 +1591,9 @@ static struct radeon_asic_ring cayman_dma_ring = {
1585 .ib_test = &r600_dma_ib_test, 1591 .ib_test = &r600_dma_ib_test,
1586 .is_lockup = &cayman_dma_is_lockup, 1592 .is_lockup = &cayman_dma_is_lockup,
1587 .vm_flush = &cayman_dma_vm_flush, 1593 .vm_flush = &cayman_dma_vm_flush,
1588 .get_rptr = &r600_dma_get_rptr, 1594 .get_rptr = &cayman_dma_get_rptr,
1589 .get_wptr = &r600_dma_get_wptr, 1595 .get_wptr = &cayman_dma_get_wptr,
1590 .set_wptr = &r600_dma_set_wptr 1596 .set_wptr = &cayman_dma_set_wptr
1591}; 1597};
1592 1598
1593static struct radeon_asic_ring cayman_uvd_ring = { 1599static struct radeon_asic_ring cayman_uvd_ring = {
@@ -1683,6 +1689,7 @@ static struct radeon_asic cayman_asic = {
1683 .init = &ni_dpm_init, 1689 .init = &ni_dpm_init,
1684 .setup_asic = &ni_dpm_setup_asic, 1690 .setup_asic = &ni_dpm_setup_asic,
1685 .enable = &ni_dpm_enable, 1691 .enable = &ni_dpm_enable,
1692 .late_enable = &rv770_dpm_late_enable,
1686 .disable = &ni_dpm_disable, 1693 .disable = &ni_dpm_disable,
1687 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1694 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1688 .set_power_state = &ni_dpm_set_power_state, 1695 .set_power_state = &ni_dpm_set_power_state,
@@ -1783,6 +1790,7 @@ static struct radeon_asic trinity_asic = {
1783 .init = &trinity_dpm_init, 1790 .init = &trinity_dpm_init,
1784 .setup_asic = &trinity_dpm_setup_asic, 1791 .setup_asic = &trinity_dpm_setup_asic,
1785 .enable = &trinity_dpm_enable, 1792 .enable = &trinity_dpm_enable,
1793 .late_enable = &trinity_dpm_late_enable,
1786 .disable = &trinity_dpm_disable, 1794 .disable = &trinity_dpm_disable,
1787 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1795 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1788 .set_power_state = &trinity_dpm_set_power_state, 1796 .set_power_state = &trinity_dpm_set_power_state,
@@ -1813,9 +1821,9 @@ static struct radeon_asic_ring si_gfx_ring = {
1813 .ib_test = &r600_ib_test, 1821 .ib_test = &r600_ib_test,
1814 .is_lockup = &si_gfx_is_lockup, 1822 .is_lockup = &si_gfx_is_lockup,
1815 .vm_flush = &si_vm_flush, 1823 .vm_flush = &si_vm_flush,
1816 .get_rptr = &radeon_ring_generic_get_rptr, 1824 .get_rptr = &cayman_gfx_get_rptr,
1817 .get_wptr = &radeon_ring_generic_get_wptr, 1825 .get_wptr = &cayman_gfx_get_wptr,
1818 .set_wptr = &radeon_ring_generic_set_wptr, 1826 .set_wptr = &cayman_gfx_set_wptr,
1819}; 1827};
1820 1828
1821static struct radeon_asic_ring si_dma_ring = { 1829static struct radeon_asic_ring si_dma_ring = {
@@ -1828,9 +1836,9 @@ static struct radeon_asic_ring si_dma_ring = {
1828 .ib_test = &r600_dma_ib_test, 1836 .ib_test = &r600_dma_ib_test,
1829 .is_lockup = &si_dma_is_lockup, 1837 .is_lockup = &si_dma_is_lockup,
1830 .vm_flush = &si_dma_vm_flush, 1838 .vm_flush = &si_dma_vm_flush,
1831 .get_rptr = &r600_dma_get_rptr, 1839 .get_rptr = &cayman_dma_get_rptr,
1832 .get_wptr = &r600_dma_get_wptr, 1840 .get_wptr = &cayman_dma_get_wptr,
1833 .set_wptr = &r600_dma_set_wptr, 1841 .set_wptr = &cayman_dma_set_wptr,
1834}; 1842};
1835 1843
1836static struct radeon_asic si_asic = { 1844static struct radeon_asic si_asic = {
@@ -1913,6 +1921,7 @@ static struct radeon_asic si_asic = {
1913 .init = &si_dpm_init, 1921 .init = &si_dpm_init,
1914 .setup_asic = &si_dpm_setup_asic, 1922 .setup_asic = &si_dpm_setup_asic,
1915 .enable = &si_dpm_enable, 1923 .enable = &si_dpm_enable,
1924 .late_enable = &si_dpm_late_enable,
1916 .disable = &si_dpm_disable, 1925 .disable = &si_dpm_disable,
1917 .pre_set_power_state = &si_dpm_pre_set_power_state, 1926 .pre_set_power_state = &si_dpm_pre_set_power_state,
1918 .set_power_state = &si_dpm_set_power_state, 1927 .set_power_state = &si_dpm_set_power_state,
@@ -1943,9 +1952,9 @@ static struct radeon_asic_ring ci_gfx_ring = {
1943 .ib_test = &cik_ib_test, 1952 .ib_test = &cik_ib_test,
1944 .is_lockup = &cik_gfx_is_lockup, 1953 .is_lockup = &cik_gfx_is_lockup,
1945 .vm_flush = &cik_vm_flush, 1954 .vm_flush = &cik_vm_flush,
1946 .get_rptr = &radeon_ring_generic_get_rptr, 1955 .get_rptr = &cik_gfx_get_rptr,
1947 .get_wptr = &radeon_ring_generic_get_wptr, 1956 .get_wptr = &cik_gfx_get_wptr,
1948 .set_wptr = &radeon_ring_generic_set_wptr, 1957 .set_wptr = &cik_gfx_set_wptr,
1949}; 1958};
1950 1959
1951static struct radeon_asic_ring ci_cp_ring = { 1960static struct radeon_asic_ring ci_cp_ring = {
@@ -1958,9 +1967,9 @@ static struct radeon_asic_ring ci_cp_ring = {
1958 .ib_test = &cik_ib_test, 1967 .ib_test = &cik_ib_test,
1959 .is_lockup = &cik_gfx_is_lockup, 1968 .is_lockup = &cik_gfx_is_lockup,
1960 .vm_flush = &cik_vm_flush, 1969 .vm_flush = &cik_vm_flush,
1961 .get_rptr = &cik_compute_ring_get_rptr, 1970 .get_rptr = &cik_compute_get_rptr,
1962 .get_wptr = &cik_compute_ring_get_wptr, 1971 .get_wptr = &cik_compute_get_wptr,
1963 .set_wptr = &cik_compute_ring_set_wptr, 1972 .set_wptr = &cik_compute_set_wptr,
1964}; 1973};
1965 1974
1966static struct radeon_asic_ring ci_dma_ring = { 1975static struct radeon_asic_ring ci_dma_ring = {
@@ -1973,9 +1982,9 @@ static struct radeon_asic_ring ci_dma_ring = {
1973 .ib_test = &cik_sdma_ib_test, 1982 .ib_test = &cik_sdma_ib_test,
1974 .is_lockup = &cik_sdma_is_lockup, 1983 .is_lockup = &cik_sdma_is_lockup,
1975 .vm_flush = &cik_dma_vm_flush, 1984 .vm_flush = &cik_dma_vm_flush,
1976 .get_rptr = &r600_dma_get_rptr, 1985 .get_rptr = &cik_sdma_get_rptr,
1977 .get_wptr = &r600_dma_get_wptr, 1986 .get_wptr = &cik_sdma_get_wptr,
1978 .set_wptr = &r600_dma_set_wptr, 1987 .set_wptr = &cik_sdma_set_wptr,
1979}; 1988};
1980 1989
1981static struct radeon_asic ci_asic = { 1990static struct radeon_asic ci_asic = {
@@ -2058,6 +2067,7 @@ static struct radeon_asic ci_asic = {
2058 .init = &ci_dpm_init, 2067 .init = &ci_dpm_init,
2059 .setup_asic = &ci_dpm_setup_asic, 2068 .setup_asic = &ci_dpm_setup_asic,
2060 .enable = &ci_dpm_enable, 2069 .enable = &ci_dpm_enable,
2070 .late_enable = &ci_dpm_late_enable,
2061 .disable = &ci_dpm_disable, 2071 .disable = &ci_dpm_disable,
2062 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2072 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2063 .set_power_state = &ci_dpm_set_power_state, 2073 .set_power_state = &ci_dpm_set_power_state,
@@ -2159,6 +2169,7 @@ static struct radeon_asic kv_asic = {
2159 .init = &kv_dpm_init, 2169 .init = &kv_dpm_init,
2160 .setup_asic = &kv_dpm_setup_asic, 2170 .setup_asic = &kv_dpm_setup_asic,
2161 .enable = &kv_dpm_enable, 2171 .enable = &kv_dpm_enable,
2172 .late_enable = &kv_dpm_late_enable,
2162 .disable = &kv_dpm_disable, 2173 .disable = &kv_dpm_disable,
2163 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2174 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2164 .set_power_state = &kv_dpm_set_power_state, 2175 .set_power_state = &kv_dpm_set_power_state,
@@ -2449,7 +2460,7 @@ int radeon_asic_init(struct radeon_device *rdev)
2449 rdev->cg_flags = 2460 rdev->cg_flags =
2450 RADEON_CG_SUPPORT_GFX_MGCG | 2461 RADEON_CG_SUPPORT_GFX_MGCG |
2451 RADEON_CG_SUPPORT_GFX_MGLS | 2462 RADEON_CG_SUPPORT_GFX_MGLS |
2452 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2463 RADEON_CG_SUPPORT_GFX_CGCG |
2453 RADEON_CG_SUPPORT_GFX_CGLS | 2464 RADEON_CG_SUPPORT_GFX_CGLS |
2454 RADEON_CG_SUPPORT_GFX_CGTS | 2465 RADEON_CG_SUPPORT_GFX_CGTS |
2455 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2466 RADEON_CG_SUPPORT_GFX_CGTS_LS |
@@ -2468,7 +2479,7 @@ int radeon_asic_init(struct radeon_device *rdev)
2468 rdev->cg_flags = 2479 rdev->cg_flags =
2469 RADEON_CG_SUPPORT_GFX_MGCG | 2480 RADEON_CG_SUPPORT_GFX_MGCG |
2470 RADEON_CG_SUPPORT_GFX_MGLS | 2481 RADEON_CG_SUPPORT_GFX_MGLS |
2471 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2482 RADEON_CG_SUPPORT_GFX_CGCG |
2472 RADEON_CG_SUPPORT_GFX_CGLS | 2483 RADEON_CG_SUPPORT_GFX_CGLS |
2473 RADEON_CG_SUPPORT_GFX_CGTS | 2484 RADEON_CG_SUPPORT_GFX_CGTS |
2474 RADEON_CG_SUPPORT_GFX_CP_LS | 2485 RADEON_CG_SUPPORT_GFX_CP_LS |
@@ -2493,7 +2504,7 @@ int radeon_asic_init(struct radeon_device *rdev)
2493 rdev->cg_flags = 2504 rdev->cg_flags =
2494 RADEON_CG_SUPPORT_GFX_MGCG | 2505 RADEON_CG_SUPPORT_GFX_MGCG |
2495 RADEON_CG_SUPPORT_GFX_MGLS | 2506 RADEON_CG_SUPPORT_GFX_MGLS |
2496 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2507 RADEON_CG_SUPPORT_GFX_CGCG |
2497 RADEON_CG_SUPPORT_GFX_CGLS | 2508 RADEON_CG_SUPPORT_GFX_CGLS |
2498 RADEON_CG_SUPPORT_GFX_CGTS | 2509 RADEON_CG_SUPPORT_GFX_CGTS |
2499 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2510 RADEON_CG_SUPPORT_GFX_CGTS_LS |
@@ -2521,7 +2532,7 @@ int radeon_asic_init(struct radeon_device *rdev)
2521 rdev->cg_flags = 2532 rdev->cg_flags =
2522 RADEON_CG_SUPPORT_GFX_MGCG | 2533 RADEON_CG_SUPPORT_GFX_MGCG |
2523 RADEON_CG_SUPPORT_GFX_MGLS | 2534 RADEON_CG_SUPPORT_GFX_MGLS |
2524 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2535 RADEON_CG_SUPPORT_GFX_CGCG |
2525 RADEON_CG_SUPPORT_GFX_CGLS | 2536 RADEON_CG_SUPPORT_GFX_CGLS |
2526 RADEON_CG_SUPPORT_GFX_CGTS | 2537 RADEON_CG_SUPPORT_GFX_CGTS |
2527 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2538 RADEON_CG_SUPPORT_GFX_CGTS_LS |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c9fd97b58076..b3bc433eed4c 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -47,13 +47,6 @@ u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
49 49
50u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
51 struct radeon_ring *ring);
52u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
53 struct radeon_ring *ring);
54void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
55 struct radeon_ring *ring);
56
57/* 50/*
58 * r100,rv100,rs100,rv200,rs200 51 * r100,rv100,rs100,rv200,rs200
59 */ 52 */
@@ -148,6 +141,13 @@ extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
148extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 141extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
149extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 142extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
150 143
144u32 r100_gfx_get_rptr(struct radeon_device *rdev,
145 struct radeon_ring *ring);
146u32 r100_gfx_get_wptr(struct radeon_device *rdev,
147 struct radeon_ring *ring);
148void r100_gfx_set_wptr(struct radeon_device *rdev,
149 struct radeon_ring *ring);
150
151/* 151/*
152 * r200,rv250,rs300,rv280 152 * r200,rv250,rs300,rv280
153 */ 153 */
@@ -368,6 +368,12 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
368int r600_pcie_gart_init(struct radeon_device *rdev); 368int r600_pcie_gart_init(struct radeon_device *rdev);
369void r600_scratch_init(struct radeon_device *rdev); 369void r600_scratch_init(struct radeon_device *rdev);
370int r600_init_microcode(struct radeon_device *rdev); 370int r600_init_microcode(struct radeon_device *rdev);
371u32 r600_gfx_get_rptr(struct radeon_device *rdev,
372 struct radeon_ring *ring);
373u32 r600_gfx_get_wptr(struct radeon_device *rdev,
374 struct radeon_ring *ring);
375void r600_gfx_set_wptr(struct radeon_device *rdev,
376 struct radeon_ring *ring);
371/* r600 irq */ 377/* r600 irq */
372int r600_irq_process(struct radeon_device *rdev); 378int r600_irq_process(struct radeon_device *rdev);
373int r600_irq_init(struct radeon_device *rdev); 379int r600_irq_init(struct radeon_device *rdev);
@@ -392,6 +398,7 @@ int rv6xx_get_temp(struct radeon_device *rdev);
392int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 398int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
393int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 399int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
394void r600_dpm_post_set_power_state(struct radeon_device *rdev); 400void r600_dpm_post_set_power_state(struct radeon_device *rdev);
401int r600_dpm_late_enable(struct radeon_device *rdev);
395/* r600 dma */ 402/* r600 dma */
396uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 403uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
397 struct radeon_ring *ring); 404 struct radeon_ring *ring);
@@ -454,6 +461,7 @@ int rv770_get_temp(struct radeon_device *rdev);
454/* rv7xx pm */ 461/* rv7xx pm */
455int rv770_dpm_init(struct radeon_device *rdev); 462int rv770_dpm_init(struct radeon_device *rdev);
456int rv770_dpm_enable(struct radeon_device *rdev); 463int rv770_dpm_enable(struct radeon_device *rdev);
464int rv770_dpm_late_enable(struct radeon_device *rdev);
457void rv770_dpm_disable(struct radeon_device *rdev); 465void rv770_dpm_disable(struct radeon_device *rdev);
458int rv770_dpm_set_power_state(struct radeon_device *rdev); 466int rv770_dpm_set_power_state(struct radeon_device *rdev);
459void rv770_dpm_setup_asic(struct radeon_device *rdev); 467void rv770_dpm_setup_asic(struct radeon_device *rdev);
@@ -545,6 +553,7 @@ u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
545bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 553bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
546int sumo_dpm_init(struct radeon_device *rdev); 554int sumo_dpm_init(struct radeon_device *rdev);
547int sumo_dpm_enable(struct radeon_device *rdev); 555int sumo_dpm_enable(struct radeon_device *rdev);
556int sumo_dpm_late_enable(struct radeon_device *rdev);
548void sumo_dpm_disable(struct radeon_device *rdev); 557void sumo_dpm_disable(struct radeon_device *rdev);
549int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 558int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
550int sumo_dpm_set_power_state(struct radeon_device *rdev); 559int sumo_dpm_set_power_state(struct radeon_device *rdev);
@@ -591,6 +600,19 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev,
591 600
592void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 601void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
593 602
603u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
604 struct radeon_ring *ring);
605u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
606 struct radeon_ring *ring);
607void cayman_gfx_set_wptr(struct radeon_device *rdev,
608 struct radeon_ring *ring);
609uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
610 struct radeon_ring *ring);
611uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
612 struct radeon_ring *ring);
613void cayman_dma_set_wptr(struct radeon_device *rdev,
614 struct radeon_ring *ring);
615
594int ni_dpm_init(struct radeon_device *rdev); 616int ni_dpm_init(struct radeon_device *rdev);
595void ni_dpm_setup_asic(struct radeon_device *rdev); 617void ni_dpm_setup_asic(struct radeon_device *rdev);
596int ni_dpm_enable(struct radeon_device *rdev); 618int ni_dpm_enable(struct radeon_device *rdev);
@@ -610,6 +632,7 @@ int ni_dpm_force_performance_level(struct radeon_device *rdev,
610bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 632bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
611int trinity_dpm_init(struct radeon_device *rdev); 633int trinity_dpm_init(struct radeon_device *rdev);
612int trinity_dpm_enable(struct radeon_device *rdev); 634int trinity_dpm_enable(struct radeon_device *rdev);
635int trinity_dpm_late_enable(struct radeon_device *rdev);
613void trinity_dpm_disable(struct radeon_device *rdev); 636void trinity_dpm_disable(struct radeon_device *rdev);
614int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 637int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
615int trinity_dpm_set_power_state(struct radeon_device *rdev); 638int trinity_dpm_set_power_state(struct radeon_device *rdev);
@@ -669,6 +692,7 @@ int si_get_temp(struct radeon_device *rdev);
669int si_dpm_init(struct radeon_device *rdev); 692int si_dpm_init(struct radeon_device *rdev);
670void si_dpm_setup_asic(struct radeon_device *rdev); 693void si_dpm_setup_asic(struct radeon_device *rdev);
671int si_dpm_enable(struct radeon_device *rdev); 694int si_dpm_enable(struct radeon_device *rdev);
695int si_dpm_late_enable(struct radeon_device *rdev);
672void si_dpm_disable(struct radeon_device *rdev); 696void si_dpm_disable(struct radeon_device *rdev);
673int si_dpm_pre_set_power_state(struct radeon_device *rdev); 697int si_dpm_pre_set_power_state(struct radeon_device *rdev);
674int si_dpm_set_power_state(struct radeon_device *rdev); 698int si_dpm_set_power_state(struct radeon_device *rdev);
@@ -739,17 +763,30 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
739 uint32_t incr, uint32_t flags); 763 uint32_t incr, uint32_t flags);
740void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 764void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
741int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 765int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
742u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 766u32 cik_gfx_get_rptr(struct radeon_device *rdev,
743 struct radeon_ring *ring); 767 struct radeon_ring *ring);
744u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 768u32 cik_gfx_get_wptr(struct radeon_device *rdev,
745 struct radeon_ring *ring); 769 struct radeon_ring *ring);
746void cik_compute_ring_set_wptr(struct radeon_device *rdev, 770void cik_gfx_set_wptr(struct radeon_device *rdev,
747 struct radeon_ring *ring); 771 struct radeon_ring *ring);
772u32 cik_compute_get_rptr(struct radeon_device *rdev,
773 struct radeon_ring *ring);
774u32 cik_compute_get_wptr(struct radeon_device *rdev,
775 struct radeon_ring *ring);
776void cik_compute_set_wptr(struct radeon_device *rdev,
777 struct radeon_ring *ring);
778u32 cik_sdma_get_rptr(struct radeon_device *rdev,
779 struct radeon_ring *ring);
780u32 cik_sdma_get_wptr(struct radeon_device *rdev,
781 struct radeon_ring *ring);
782void cik_sdma_set_wptr(struct radeon_device *rdev,
783 struct radeon_ring *ring);
748int ci_get_temp(struct radeon_device *rdev); 784int ci_get_temp(struct radeon_device *rdev);
749int kv_get_temp(struct radeon_device *rdev); 785int kv_get_temp(struct radeon_device *rdev);
750 786
751int ci_dpm_init(struct radeon_device *rdev); 787int ci_dpm_init(struct radeon_device *rdev);
752int ci_dpm_enable(struct radeon_device *rdev); 788int ci_dpm_enable(struct radeon_device *rdev);
789int ci_dpm_late_enable(struct radeon_device *rdev);
753void ci_dpm_disable(struct radeon_device *rdev); 790void ci_dpm_disable(struct radeon_device *rdev);
754int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 791int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
755int ci_dpm_set_power_state(struct radeon_device *rdev); 792int ci_dpm_set_power_state(struct radeon_device *rdev);
@@ -770,6 +807,7 @@ void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
770 807
771int kv_dpm_init(struct radeon_device *rdev); 808int kv_dpm_init(struct radeon_device *rdev);
772int kv_dpm_enable(struct radeon_device *rdev); 809int kv_dpm_enable(struct radeon_device *rdev);
810int kv_dpm_late_enable(struct radeon_device *rdev);
773void kv_dpm_disable(struct radeon_device *rdev); 811void kv_dpm_disable(struct radeon_device *rdev);
774int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 812int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
775int kv_dpm_set_power_state(struct radeon_device *rdev); 813int kv_dpm_set_power_state(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5c39bf7c3d88..30844814c25a 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -30,27 +30,10 @@
30#include "atom.h" 30#include "atom.h"
31#include "atom-bits.h" 31#include "atom-bits.h"
32 32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void 33extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 34radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps); 35 uint32_t supported_device, u16 caps);
41 36
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54/* from radeon_legacy_encoder.c */ 37/* from radeon_legacy_encoder.c */
55extern void 38extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 39radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
@@ -1528,6 +1511,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1528 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1511 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1529 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1512 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1530 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1513 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1514 ss->percentage_divider = 100;
1531 return true; 1515 return true;
1532 } 1516 }
1533 ss_assign = (union asic_ss_assignment *) 1517 ss_assign = (union asic_ss_assignment *)
@@ -1545,6 +1529,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1545 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1529 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1546 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1530 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1547 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1531 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1532 ss->percentage_divider = 100;
1548 if ((crev == 2) && 1533 if ((crev == 2) &&
1549 ((id == ASIC_INTERNAL_ENGINE_SS) || 1534 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1550 (id == ASIC_INTERNAL_MEMORY_SS))) 1535 (id == ASIC_INTERNAL_MEMORY_SS)))
@@ -1566,6 +1551,11 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1566 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1551 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1567 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1552 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1568 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1553 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1554 if (ss_assign->v3.ucSpreadSpectrumMode &
1555 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1556 ss->percentage_divider = 1000;
1557 else
1558 ss->percentage_divider = 100;
1569 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1559 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1570 (id == ASIC_INTERNAL_MEMORY_SS)) 1560 (id == ASIC_INTERNAL_MEMORY_SS))
1571 ss->rate /= 100; 1561 ss->rate /= 100;
@@ -1809,7 +1799,8 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1809 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1799 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1810 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1800 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1811 1801
1812 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1802 mode->crtc_clock = mode->clock =
1803 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1813 1804
1814 if (index == 1) { 1805 if (index == 1) {
1815 /* PAL timings appear to have wrong values for totals */ 1806 /* PAL timings appear to have wrong values for totals */
@@ -1852,7 +1843,8 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1852 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1843 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1853 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1844 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1854 1845
1855 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 1846 mode->crtc_clock = mode->clock =
1847 le16_to_cpu(dtd_timings->usPixClk) * 10;
1856 break; 1848 break;
1857 } 1849 }
1858 return true; 1850 return true;
@@ -3884,16 +3876,18 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3884 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 3876 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
3885 } 3877 }
3886 reg_table->last = i; 3878 reg_table->last = i;
3887 while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) && 3879 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
3888 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 3880 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3889 t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); 3881 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
3882 >> MEM_ID_SHIFT);
3890 if (module_index == t_mem_id) { 3883 if (module_index == t_mem_id) {
3891 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 3884 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3892 (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT); 3885 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
3886 >> CLOCK_RANGE_SHIFT);
3893 for (i = 0, j = 1; i < reg_table->last; i++) { 3887 for (i = 0, j = 1; i < reg_table->last; i++) {
3894 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 3888 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3895 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 3889 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3896 (u32)*((u32 *)reg_data + j); 3890 (u32)le32_to_cpu(*((u32 *)reg_data + j));
3897 j++; 3891 j++;
3898 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 3892 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3899 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 3893 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
@@ -3905,7 +3899,7 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3905 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3899 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3906 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 3900 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
3907 } 3901 }
3908 if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) 3902 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
3909 return -EINVAL; 3903 return -EINVAL;
3910 reg_table->num_entries = num_ranges; 3904 reg_table->num_entries = num_ranges;
3911 } else 3905 } else
@@ -3944,6 +3938,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
3944 /* tell the bios not to handle mode switching */ 3938 /* tell the bios not to handle mode switching */
3945 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 3939 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
3946 3940
3941 /* clear the vbios dpms state */
3942 if (ASIC_IS_DCE4(rdev))
3943 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
3944
3947 if (rdev->family >= CHIP_R600) { 3945 if (rdev->family >= CHIP_R600) {
3948 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 3946 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3949 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 3947 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 68ce36056019..6651177110f0 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -37,22 +37,6 @@
37#include <asm/pci-bridge.h> 37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */ 38#endif /* CONFIG_PPC_PMAC */
39 39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56/* from radeon_legacy_encoder.c */ 40/* from radeon_legacy_encoder.c */
57extern void 41extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 42radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 20a768ac89a8..82d4f865546e 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -33,15 +33,6 @@
33 33
34#include <linux/pm_runtime.h> 34#include <linux/pm_runtime.h>
35 35
36extern void
37radeon_combios_connected_scratch_regs(struct drm_connector *connector,
38 struct drm_encoder *encoder,
39 bool connected);
40extern void
41radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
42 struct drm_encoder *encoder,
43 bool connected);
44
45void radeon_connector_hotplug(struct drm_connector *connector) 36void radeon_connector_hotplug(struct drm_connector *connector)
46{ 37{
47 struct drm_device *dev = connector->dev; 38 struct drm_device *dev = connector->dev;
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 3cae2bbc1854..bb0d5c3a8311 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -2020,10 +2020,10 @@ static int radeon_cp_get_buffers(struct drm_device *dev,
2020 2020
2021 buf->file_priv = file_priv; 2021 buf->file_priv = file_priv;
2022 2022
2023 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 2023 if (copy_to_user(&d->request_indices[i], &buf->idx,
2024 sizeof(buf->idx))) 2024 sizeof(buf->idx)))
2025 return -EFAULT; 2025 return -EFAULT;
2026 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 2026 if (copy_to_user(&d->request_sizes[i], &buf->total,
2027 sizeof(buf->total))) 2027 sizeof(buf->total)))
2028 return -EFAULT; 2028 return -EFAULT;
2029 2029
@@ -2228,7 +2228,7 @@ void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2228 2228
2229 dev_priv->ring.tail &= dev_priv->ring.tail_mask; 2229 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2230 2230
2231 DRM_MEMORYBARRIER(); 2231 mb();
2232 GET_RING_HEAD( dev_priv ); 2232 GET_RING_HEAD( dev_priv );
2233 2233
2234 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 2234 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 0b366169d64d..dfb5a1db87d4 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -138,7 +138,7 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
138 p->ring = R600_RING_TYPE_DMA_INDEX; 138 p->ring = R600_RING_TYPE_DMA_INDEX;
139 else 139 else
140 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; 140 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
141 } else if (p->rdev->family >= CHIP_R600) { 141 } else if (p->rdev->family >= CHIP_RV770) {
142 p->ring = R600_RING_TYPE_DMA_INDEX; 142 p->ring = R600_RING_TYPE_DMA_INDEX;
143 } else { 143 } else {
144 return -EINVAL; 144 return -EINVAL;
@@ -192,7 +192,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
192 return -ENOMEM; 192 return -ENOMEM;
193 } 193 }
194 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 194 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
195 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, 195 if (copy_from_user(p->chunks_array, chunk_array_ptr,
196 sizeof(uint64_t)*cs->num_chunks)) { 196 sizeof(uint64_t)*cs->num_chunks)) {
197 return -EFAULT; 197 return -EFAULT;
198 } 198 }
@@ -208,7 +208,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
208 uint32_t __user *cdata; 208 uint32_t __user *cdata;
209 209
210 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 210 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
211 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, 211 if (copy_from_user(&user_chunk, chunk_ptr,
212 sizeof(struct drm_radeon_cs_chunk))) { 212 sizeof(struct drm_radeon_cs_chunk))) {
213 return -EFAULT; 213 return -EFAULT;
214 } 214 }
@@ -252,7 +252,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
252 if (p->chunks[i].kdata == NULL) { 252 if (p->chunks[i].kdata == NULL) {
253 return -ENOMEM; 253 return -ENOMEM;
254 } 254 }
255 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, cdata, size)) { 255 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
256 return -EFAULT; 256 return -EFAULT;
257 } 257 }
258 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 258 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
@@ -472,7 +472,7 @@ static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser
472 } 472 }
473 parser->const_ib.is_const_ib = true; 473 parser->const_ib.is_const_ib = true;
474 parser->const_ib.length_dw = ib_chunk->length_dw; 474 parser->const_ib.length_dw = ib_chunk->length_dw;
475 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, 475 if (copy_from_user(parser->const_ib.ptr,
476 ib_chunk->user_ptr, 476 ib_chunk->user_ptr,
477 ib_chunk->length_dw * 4)) 477 ib_chunk->length_dw * 4))
478 return -EFAULT; 478 return -EFAULT;
@@ -495,7 +495,7 @@ static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser
495 parser->ib.length_dw = ib_chunk->length_dw; 495 parser->ib.length_dw = ib_chunk->length_dw;
496 if (ib_chunk->kdata) 496 if (ib_chunk->kdata)
497 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); 497 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
498 else if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) 498 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
499 return -EFAULT; 499 return -EFAULT;
500 return 0; 500 return 0;
501} 501}
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 39b033b441d2..b012cbbc3ed5 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -144,6 +144,11 @@ void radeon_program_register_sequence(struct radeon_device *rdev,
144 } 144 }
145} 145}
146 146
147void radeon_pci_config_reset(struct radeon_device *rdev)
148{
149 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
150}
151
147/** 152/**
148 * radeon_surface_init - Clear GPU surface registers. 153 * radeon_surface_init - Clear GPU surface registers.
149 * 154 *
@@ -249,7 +254,7 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
249 * Init doorbell driver information (CIK) 254 * Init doorbell driver information (CIK)
250 * Returns 0 on success, error on failure. 255 * Returns 0 on success, error on failure.
251 */ 256 */
252int radeon_doorbell_init(struct radeon_device *rdev) 257static int radeon_doorbell_init(struct radeon_device *rdev)
253{ 258{
254 /* doorbell bar mapping */ 259 /* doorbell bar mapping */
255 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 260 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
@@ -278,7 +283,7 @@ int radeon_doorbell_init(struct radeon_device *rdev)
278 * 283 *
279 * Tear down doorbell driver information (CIK) 284 * Tear down doorbell driver information (CIK)
280 */ 285 */
281void radeon_doorbell_fini(struct radeon_device *rdev) 286static void radeon_doorbell_fini(struct radeon_device *rdev)
282{ 287{
283 iounmap(rdev->doorbell.ptr); 288 iounmap(rdev->doorbell.ptr);
284 rdev->doorbell.ptr = NULL; 289 rdev->doorbell.ptr = NULL;
@@ -1330,6 +1335,7 @@ int radeon_device_init(struct radeon_device *rdev,
1330 if (r) 1335 if (r)
1331 return r; 1336 return r;
1332 } 1337 }
1338
1333 if ((radeon_testing & 1)) { 1339 if ((radeon_testing & 1)) {
1334 if (rdev->accel_working) 1340 if (rdev->accel_working)
1335 radeon_test_moves(rdev); 1341 radeon_test_moves(rdev);
@@ -1455,7 +1461,6 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1455 1461
1456 radeon_save_bios_scratch_regs(rdev); 1462 radeon_save_bios_scratch_regs(rdev);
1457 1463
1458 radeon_pm_suspend(rdev);
1459 radeon_suspend(rdev); 1464 radeon_suspend(rdev);
1460 radeon_hpd_fini(rdev); 1465 radeon_hpd_fini(rdev);
1461 /* evict remaining vram memory */ 1466 /* evict remaining vram memory */
@@ -1516,14 +1521,22 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1516 if (r) 1521 if (r)
1517 DRM_ERROR("ib ring test failed (%d).\n", r); 1522 DRM_ERROR("ib ring test failed (%d).\n", r);
1518 1523
1519 radeon_pm_resume(rdev); 1524 if (rdev->pm.dpm_enabled) {
1525 /* do dpm late init */
1526 r = radeon_pm_late_init(rdev);
1527 if (r) {
1528 rdev->pm.dpm_enabled = false;
1529 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1530 }
1531 }
1532
1520 radeon_restore_bios_scratch_regs(rdev); 1533 radeon_restore_bios_scratch_regs(rdev);
1521 1534
1522 if (fbcon) { 1535 if (fbcon) {
1523 radeon_fbdev_set_suspend(rdev, 0); 1536 radeon_fbdev_set_suspend(rdev, 0);
1524 console_unlock(); 1537 console_unlock();
1525 } 1538 }
1526 1539
1527 /* init dig PHYs, disp eng pll */ 1540 /* init dig PHYs, disp eng pll */
1528 if (rdev->is_atom_bios) { 1541 if (rdev->is_atom_bios) {
1529 radeon_atom_encoder_init(rdev); 1542 radeon_atom_encoder_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 7b253815a323..d680608f6f5b 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -306,7 +306,7 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
306 * to complete in this vblank? 306 * to complete in this vblank?
307 */ 307 */
308 if (update_pending && 308 if (update_pending &&
309 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 309 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
310 &vpos, &hpos, NULL, NULL)) && 310 &vpos, &hpos, NULL, NULL)) &&
311 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 311 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
312 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 312 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
@@ -1464,12 +1464,22 @@ int radeon_modeset_init(struct radeon_device *rdev)
1464 /* setup afmt */ 1464 /* setup afmt */
1465 radeon_afmt_init(rdev); 1465 radeon_afmt_init(rdev);
1466 1466
1467 /* Initialize power management */
1468 radeon_pm_init(rdev);
1469
1470 radeon_fbdev_init(rdev); 1467 radeon_fbdev_init(rdev);
1471 drm_kms_helper_poll_init(rdev->ddev); 1468 drm_kms_helper_poll_init(rdev->ddev);
1472 1469
1470 if (rdev->pm.dpm_enabled) {
1471 /* do dpm late init */
1472 ret = radeon_pm_late_init(rdev);
1473 if (ret) {
1474 rdev->pm.dpm_enabled = false;
1475 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1476 }
1477 /* set the dpm state for PX since there won't be
1478 * a modeset to call this.
1479 */
1480 radeon_pm_compute_clocks(rdev);
1481 }
1482
1473 return 0; 1483 return 0;
1474} 1484}
1475 1485
@@ -1477,7 +1487,6 @@ void radeon_modeset_fini(struct radeon_device *rdev)
1477{ 1487{
1478 radeon_fbdev_fini(rdev); 1488 radeon_fbdev_fini(rdev);
1479 kfree(rdev->mode_info.bios_hardcoded_edid); 1489 kfree(rdev->mode_info.bios_hardcoded_edid);
1480 radeon_pm_fini(rdev);
1481 1490
1482 if (rdev->mode_info.mode_config_initialized) { 1491 if (rdev->mode_info.mode_config_initialized) {
1483 radeon_afmt_fini(rdev); 1492 radeon_afmt_fini(rdev);
@@ -1601,6 +1610,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1601 * 1610 *
1602 * \param dev Device to query. 1611 * \param dev Device to query.
1603 * \param crtc Crtc to query. 1612 * \param crtc Crtc to query.
1613 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1604 * \param *vpos Location where vertical scanout position should be stored. 1614 * \param *vpos Location where vertical scanout position should be stored.
1605 * \param *hpos Location where horizontal scanout position should go. 1615 * \param *hpos Location where horizontal scanout position should go.
1606 * \param *stime Target location for timestamp taken immediately before 1616 * \param *stime Target location for timestamp taken immediately before
@@ -1622,8 +1632,8 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1622 * unknown small number of scanlines wrt. real scanout position. 1632 * unknown small number of scanlines wrt. real scanout position.
1623 * 1633 *
1624 */ 1634 */
1625int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos, 1635int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1626 ktime_t *stime, ktime_t *etime) 1636 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1627{ 1637{
1628 u32 stat_crtc = 0, vbl = 0, position = 0; 1638 u32 stat_crtc = 0, vbl = 0, position = 0;
1629 int vbl_start, vbl_end, vtotal, ret = 0; 1639 int vbl_start, vbl_end, vtotal, ret = 0;
@@ -1765,5 +1775,27 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int
1765 if (in_vbl) 1775 if (in_vbl)
1766 ret |= DRM_SCANOUTPOS_INVBL; 1776 ret |= DRM_SCANOUTPOS_INVBL;
1767 1777
1778 /* Is vpos outside nominal vblank area, but less than
1779 * 1/100 of a frame height away from start of vblank?
1780 * If so, assume this isn't a massively delayed vblank
1781 * interrupt, but a vblank interrupt that fired a few
1782 * microseconds before true start of vblank. Compensate
1783 * by adding a full frame duration to the final timestamp.
1784 * Happens, e.g., on ATI R500, R600.
1785 *
1786 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1787 */
1788 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1789 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1790 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1791
1792 if (vbl_start - *vpos < vtotal / 100) {
1793 *vpos -= vtotal;
1794
1795 /* Signal this correction as "applied". */
1796 ret |= 0x8;
1797 }
1798 }
1799
1768 return ret; 1800 return ret;
1769} 1801}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index db39ea36bf22..ec8c388eec17 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -102,13 +102,14 @@ int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
102void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 102void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
103int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 103int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
104void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 104void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
105irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); 105irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
106void radeon_gem_object_free(struct drm_gem_object *obj); 106void radeon_gem_object_free(struct drm_gem_object *obj);
107int radeon_gem_object_open(struct drm_gem_object *obj, 107int radeon_gem_object_open(struct drm_gem_object *obj,
108 struct drm_file *file_priv); 108 struct drm_file *file_priv);
109void radeon_gem_object_close(struct drm_gem_object *obj, 109void radeon_gem_object_close(struct drm_gem_object *obj,
110 struct drm_file *file_priv); 110 struct drm_file *file_priv);
111extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 111extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
112 unsigned int flags,
112 int *vpos, int *hpos, ktime_t *stime, 113 int *vpos, int *hpos, ktime_t *stime,
113 ktime_t *etime); 114 ktime_t *etime);
114extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 115extern const struct drm_ioctl_desc radeon_ioctls_kms[];
@@ -168,6 +169,7 @@ int radeon_fastfb = 0;
168int radeon_dpm = -1; 169int radeon_dpm = -1;
169int radeon_aspm = -1; 170int radeon_aspm = -1;
170int radeon_runtime_pm = -1; 171int radeon_runtime_pm = -1;
172int radeon_hard_reset = 0;
171 173
172MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 174MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
173module_param_named(no_wb, radeon_no_wb, int, 0444); 175module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -232,6 +234,9 @@ module_param_named(aspm, radeon_aspm, int, 0444);
232MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 234MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
233module_param_named(runpm, radeon_runtime_pm, int, 0444); 235module_param_named(runpm, radeon_runtime_pm, int, 0444);
234 236
237MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
238module_param_named(hard_reset, radeon_hard_reset, int, 0444);
239
235static struct pci_device_id pciidlist[] = { 240static struct pci_device_id pciidlist[] = {
236 radeon_PCI_IDS 241 radeon_PCI_IDS
237}; 242};
@@ -400,6 +405,9 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
400 if (radeon_runtime_pm == 0) 405 if (radeon_runtime_pm == 0)
401 return -EINVAL; 406 return -EINVAL;
402 407
408 if (radeon_runtime_pm == -1 && !radeon_is_px())
409 return -EINVAL;
410
403 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 411 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
404 drm_kms_helper_poll_disable(drm_dev); 412 drm_kms_helper_poll_disable(drm_dev);
405 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 413 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
@@ -422,6 +430,9 @@ static int radeon_pmops_runtime_resume(struct device *dev)
422 if (radeon_runtime_pm == 0) 430 if (radeon_runtime_pm == 0)
423 return -EINVAL; 431 return -EINVAL;
424 432
433 if (radeon_runtime_pm == -1 && !radeon_is_px())
434 return -EINVAL;
435
425 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 436 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
426 437
427 pci_set_power_state(pdev, PCI_D0); 438 pci_set_power_state(pdev, PCI_D0);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 00e0d449021c..dafd812e4571 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -405,7 +405,7 @@ extern void radeon_do_release(struct drm_device * dev);
405extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 405extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
406extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 406extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
407extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 407extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
408extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 408extern irqreturn_t radeon_driver_irq_handler(int irq, void *arg);
409extern void radeon_driver_irq_preinstall(struct drm_device * dev); 409extern void radeon_driver_irq_preinstall(struct drm_device * dev);
410extern int radeon_driver_irq_postinstall(struct drm_device *dev); 410extern int radeon_driver_irq_postinstall(struct drm_device *dev);
411extern void radeon_driver_irq_uninstall(struct drm_device * dev); 411extern void radeon_driver_irq_uninstall(struct drm_device * dev);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index d3a86e43c012..c37cb79a9489 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -121,7 +121,7 @@ int radeon_fence_emit(struct radeon_device *rdev,
121 (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring]; 121 (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
122 (*fence)->ring = ring; 122 (*fence)->ring = ring;
123 radeon_fence_ring_emit(rdev, ring, *fence); 123 radeon_fence_ring_emit(rdev, ring, *fence);
124 trace_radeon_fence_emit(rdev->ddev, (*fence)->seq); 124 trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
125 return 0; 125 return 0;
126} 126}
127 127
@@ -313,7 +313,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
313 continue; 313 continue;
314 314
315 last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq); 315 last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq);
316 trace_radeon_fence_wait_begin(rdev->ddev, target_seq[i]); 316 trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
317 radeon_irq_kms_sw_irq_get(rdev, i); 317 radeon_irq_kms_sw_irq_get(rdev, i);
318 } 318 }
319 319
@@ -332,7 +332,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
332 continue; 332 continue;
333 333
334 radeon_irq_kms_sw_irq_put(rdev, i); 334 radeon_irq_kms_sw_irq_put(rdev, i);
335 trace_radeon_fence_wait_end(rdev->ddev, target_seq[i]); 335 trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
336 } 336 }
337 337
338 if (unlikely(r < 0)) 338 if (unlikely(r < 0))
@@ -841,6 +841,8 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
841 if (!rdev->fence_drv[i].initialized) 841 if (!rdev->fence_drv[i].initialized)
842 continue; 842 continue;
843 843
844 radeon_fence_process(rdev, i);
845
844 seq_printf(m, "--- ring %d ---\n", i); 846 seq_printf(m, "--- ring %d ---\n", i);
845 seq_printf(m, "Last signaled fence 0x%016llx\n", 847 seq_printf(m, "Last signaled fence 0x%016llx\n",
846 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq)); 848 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 96e440061bdb..a8f9b463bf2a 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -713,7 +713,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
713 unsigned i; 713 unsigned i;
714 714
715 /* check if the id is still valid */ 715 /* check if the id is still valid */
716 if (vm->fence && vm->fence == rdev->vm_manager.active[vm->id]) 716 if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
717 return NULL; 717 return NULL;
718 718
719 /* we definately need to flush */ 719 /* we definately need to flush */
@@ -726,6 +726,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
726 if (fence == NULL) { 726 if (fence == NULL) {
727 /* found a free one */ 727 /* found a free one */
728 vm->id = i; 728 vm->id = i;
729 trace_radeon_vm_grab_id(vm->id, ring);
729 return NULL; 730 return NULL;
730 } 731 }
731 732
@@ -769,6 +770,9 @@ void radeon_vm_fence(struct radeon_device *rdev,
769 770
770 radeon_fence_unref(&vm->fence); 771 radeon_fence_unref(&vm->fence);
771 vm->fence = radeon_fence_ref(fence); 772 vm->fence = radeon_fence_ref(fence);
773
774 radeon_fence_unref(&vm->last_id_use);
775 vm->last_id_use = radeon_fence_ref(fence);
772} 776}
773 777
774/** 778/**
@@ -1303,6 +1307,8 @@ void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1303{ 1307{
1304 vm->id = 0; 1308 vm->id = 0;
1305 vm->fence = NULL; 1309 vm->fence = NULL;
1310 vm->last_flush = NULL;
1311 vm->last_id_use = NULL;
1306 mutex_init(&vm->mutex); 1312 mutex_init(&vm->mutex);
1307 INIT_LIST_HEAD(&vm->list); 1313 INIT_LIST_HEAD(&vm->list);
1308 INIT_LIST_HEAD(&vm->va); 1314 INIT_LIST_HEAD(&vm->va);
@@ -1341,5 +1347,6 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1341 } 1347 }
1342 radeon_fence_unref(&vm->fence); 1348 radeon_fence_unref(&vm->fence);
1343 radeon_fence_unref(&vm->last_flush); 1349 radeon_fence_unref(&vm->last_flush);
1350 radeon_fence_unref(&vm->last_id_use);
1344 mutex_unlock(&vm->mutex); 1351 mutex_unlock(&vm->mutex);
1345} 1352}
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 805c5e566b9a..b96c819024b3 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -86,7 +86,7 @@ retry:
86 return 0; 86 return 0;
87} 87}
88 88
89int radeon_gem_set_domain(struct drm_gem_object *gobj, 89static int radeon_gem_set_domain(struct drm_gem_object *gobj,
90 uint32_t rdomain, uint32_t wdomain) 90 uint32_t rdomain, uint32_t wdomain)
91{ 91{
92 struct radeon_bo *robj; 92 struct radeon_bo *robj;
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index fc60b74ee304..e24ca6ab96de 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -1020,6 +1020,9 @@ void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1020/* Add the default buses */ 1020/* Add the default buses */
1021void radeon_i2c_init(struct radeon_device *rdev) 1021void radeon_i2c_init(struct radeon_device *rdev)
1022{ 1022{
1023 if (radeon_hw_i2c)
1024 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
1025
1023 if (rdev->is_atom_bios) 1026 if (rdev->is_atom_bios)
1024 radeon_atombios_i2c_init(rdev); 1027 radeon_atombios_i2c_init(rdev);
1025 else 1028 else
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 8d68e972789a..244b19bab2e7 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -181,7 +181,7 @@ static u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_dis
181 * tied to dma at all, this is just a hangover from dri prehistory. 181 * tied to dma at all, this is just a hangover from dri prehistory.
182 */ 182 */
183 183
184irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) 184irqreturn_t radeon_driver_irq_handler(int irq, void *arg)
185{ 185{
186 struct drm_device *dev = (struct drm_device *) arg; 186 struct drm_device *dev = (struct drm_device *) arg;
187 drm_radeon_private_t *dev_priv = 187 drm_radeon_private_t *dev_priv =
@@ -203,7 +203,7 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
203 203
204 /* SW interrupt */ 204 /* SW interrupt */
205 if (stat & RADEON_SW_INT_TEST) 205 if (stat & RADEON_SW_INT_TEST)
206 DRM_WAKEUP(&dev_priv->swi_queue); 206 wake_up(&dev_priv->swi_queue);
207 207
208 /* VBLANK interrupt */ 208 /* VBLANK interrupt */
209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { 209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
@@ -249,7 +249,7 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
249 249
250 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 250 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
251 251
252 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ, 252 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * HZ,
253 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); 253 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
254 254
255 return ret; 255 return ret;
@@ -302,7 +302,7 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr
302 302
303 result = radeon_emit_irq(dev); 303 result = radeon_emit_irq(dev);
304 304
305 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 305 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
306 DRM_ERROR("copy_to_user\n"); 306 DRM_ERROR("copy_to_user\n");
307 return -EFAULT; 307 return -EFAULT;
308 } 308 }
@@ -354,7 +354,7 @@ int radeon_driver_irq_postinstall(struct drm_device *dev)
354 (drm_radeon_private_t *) dev->dev_private; 354 (drm_radeon_private_t *) dev->dev_private;
355 355
356 atomic_set(&dev_priv->swi_emitted, 0); 356 atomic_set(&dev_priv->swi_emitted, 0);
357 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); 357 init_waitqueue_head(&dev_priv->swi_queue);
358 358
359 dev->max_vblank_count = 0x001fffff; 359 dev->max_vblank_count = 0x001fffff;
360 360
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index ec6240b00469..089c9ffb0aa9 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -39,13 +39,13 @@
39/** 39/**
40 * radeon_driver_irq_handler_kms - irq handler for KMS 40 * radeon_driver_irq_handler_kms - irq handler for KMS
41 * 41 *
42 * @DRM_IRQ_ARGS: args 42 * @int irq, void *arg: args
43 * 43 *
44 * This is the irq handler for the radeon KMS driver (all asics). 44 * This is the irq handler for the radeon KMS driver (all asics).
45 * radeon_irq_process is a macro that points to the per-asic 45 * radeon_irq_process is a macro that points to the per-asic
46 * irq handler callback. 46 * irq handler callback.
47 */ 47 */
48irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) 48irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg)
49{ 49{
50 struct drm_device *dev = (struct drm_device *) arg; 50 struct drm_device *dev = (struct drm_device *) arg;
51 struct radeon_device *rdev = dev->dev_private; 51 struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 21d593c0ecaf..114d1672d616 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -191,7 +191,7 @@ static void radeon_set_filp_rights(struct drm_device *dev,
191 * etc. (all asics). 191 * etc. (all asics).
192 * Returns 0 on success, -EINVAL on failure. 192 * Returns 0 on success, -EINVAL on failure.
193 */ 193 */
194int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 194static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
195{ 195{
196 struct radeon_device *rdev = dev->dev_private; 196 struct radeon_device *rdev = dev->dev_private;
197 struct drm_radeon_info *info = data; 197 struct drm_radeon_info *info = data;
@@ -223,7 +223,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
223 *value = rdev->accel_working; 223 *value = rdev->accel_working;
224 break; 224 break;
225 case RADEON_INFO_CRTC_FROM_ID: 225 case RADEON_INFO_CRTC_FROM_ID:
226 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 226 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
227 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 227 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
228 return -EFAULT; 228 return -EFAULT;
229 } 229 }
@@ -269,7 +269,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
269 * 269 *
270 * When returning, the value is 1 if filp owns hyper-z access, 270 * When returning, the value is 1 if filp owns hyper-z access,
271 * 0 otherwise. */ 271 * 0 otherwise. */
272 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 272 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
273 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 273 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
274 return -EFAULT; 274 return -EFAULT;
275 } 275 }
@@ -281,7 +281,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
281 break; 281 break;
282 case RADEON_INFO_WANT_CMASK: 282 case RADEON_INFO_WANT_CMASK:
283 /* The same logic as Hyper-Z. */ 283 /* The same logic as Hyper-Z. */
284 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 284 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
285 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 285 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
286 return -EFAULT; 286 return -EFAULT;
287 } 287 }
@@ -417,7 +417,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
417 *value = rdev->fastfb_working; 417 *value = rdev->fastfb_working;
418 break; 418 break;
419 case RADEON_INFO_RING_WORKING: 419 case RADEON_INFO_RING_WORKING:
420 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 420 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
421 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 421 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
422 return -EFAULT; 422 return -EFAULT;
423 } 423 }
@@ -470,11 +470,18 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
470 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 470 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
471 } 471 }
472 break; 472 break;
473 case RADEON_INFO_MAX_SCLK:
474 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
475 rdev->pm.dpm_enabled)
476 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
477 else
478 *value = rdev->pm.default_sclk * 10;
479 break;
473 default: 480 default:
474 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 481 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
475 return -EINVAL; 482 return -EINVAL;
476 } 483 }
477 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) { 484 if (copy_to_user(value_ptr, (char*)value, value_size)) {
478 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 485 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
479 return -EFAULT; 486 return -EFAULT;
480 } 487 }
@@ -712,11 +719,12 @@ int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
712 /* Helper routine in DRM core does all the work: */ 719 /* Helper routine in DRM core does all the work: */
713 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 720 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
714 vblank_time, flags, 721 vblank_time, flags,
715 drmcrtc); 722 drmcrtc, &drmcrtc->hwmode);
716} 723}
717 724
718#define KMS_INVALID_IOCTL(name) \ 725#define KMS_INVALID_IOCTL(name) \
719int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ 726static int name(struct drm_device *dev, void *data, struct drm_file \
727 *file_priv) \
720{ \ 728{ \
721 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 729 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
722 return -EINVAL; \ 730 return -EINVAL; \
diff --git a/drivers/gpu/drm/radeon/radeon_mem.c b/drivers/gpu/drm/radeon/radeon_mem.c
index d54d2d7c9031..146d253f1131 100644
--- a/drivers/gpu/drm/radeon/radeon_mem.c
+++ b/drivers/gpu/drm/radeon/radeon_mem.c
@@ -243,7 +243,7 @@ int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_p
243 if (!block) 243 if (!block)
244 return -ENOMEM; 244 return -ENOMEM;
245 245
246 if (DRM_COPY_TO_USER(alloc->region_offset, &block->start, 246 if (copy_to_user(alloc->region_offset, &block->start,
247 sizeof(int))) { 247 sizeof(int))) {
248 DRM_ERROR("copy_to_user\n"); 248 DRM_ERROR("copy_to_user\n");
249 return -EFAULT; 249 return -EFAULT;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3f0dd664af90..402dbe32c234 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -291,6 +291,7 @@ struct radeon_tv_regs {
291 291
292struct radeon_atom_ss { 292struct radeon_atom_ss {
293 uint16_t percentage; 293 uint16_t percentage;
294 uint16_t percentage_divider;
294 uint8_t type; 295 uint8_t type;
295 uint16_t step; 296 uint16_t step;
296 uint8_t delay; 297 uint8_t delay;
@@ -624,6 +625,30 @@ struct atom_voltage_table
624 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 625 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
625}; 626};
626 627
628
629extern void
630radeon_add_atom_connector(struct drm_device *dev,
631 uint32_t connector_id,
632 uint32_t supported_device,
633 int connector_type,
634 struct radeon_i2c_bus_rec *i2c_bus,
635 uint32_t igp_lane_info,
636 uint16_t connector_object_id,
637 struct radeon_hpd *hpd,
638 struct radeon_router *router);
639extern void
640radeon_add_legacy_connector(struct drm_device *dev,
641 uint32_t connector_id,
642 uint32_t supported_device,
643 int connector_type,
644 struct radeon_i2c_bus_rec *i2c_bus,
645 uint16_t connector_object_id,
646 struct radeon_hpd *hpd);
647extern uint32_t
648radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
649 uint8_t dac);
650extern void radeon_link_encoder_connector(struct drm_device *dev);
651
627extern enum radeon_tv_std 652extern enum radeon_tv_std
628radeon_combios_get_tv_info(struct radeon_device *rdev); 653radeon_combios_get_tv_info(struct radeon_device *rdev);
629extern enum radeon_tv_std 654extern enum radeon_tv_std
@@ -631,6 +656,15 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev);
631extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 656extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
632 u16 *vddc, u16 *vddci, u16 *mvdd); 657 u16 *vddc, u16 *vddci, u16 *mvdd);
633 658
659extern void
660radeon_combios_connected_scratch_regs(struct drm_connector *connector,
661 struct drm_encoder *encoder,
662 bool connected);
663extern void
664radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
665 struct drm_encoder *encoder,
666 bool connected);
667
634extern struct drm_connector * 668extern struct drm_connector *
635radeon_get_connector_for_encoder(struct drm_encoder *encoder); 669radeon_get_connector_for_encoder(struct drm_encoder *encoder);
636extern struct drm_connector * 670extern struct drm_connector *
@@ -666,6 +700,7 @@ extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
666extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 700extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
667extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 701extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
668 u8 write_byte, u8 *read_byte); 702 u8 write_byte, u8 *read_byte);
703void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
669 704
670extern void radeon_i2c_init(struct radeon_device *rdev); 705extern void radeon_i2c_init(struct radeon_device *rdev);
671extern void radeon_i2c_fini(struct radeon_device *rdev); 706extern void radeon_i2c_fini(struct radeon_device *rdev);
@@ -766,6 +801,7 @@ extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
766 int x, int y); 801 int x, int y);
767 802
768extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 803extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
804 unsigned int flags,
769 int *vpos, int *hpos, ktime_t *stime, 805 int *vpos, int *hpos, ktime_t *stime,
770 ktime_t *etime); 806 ktime_t *etime);
771 807
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index c0fa4aa9ceea..08595cf90b01 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -46,7 +46,7 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
46 * function are calling it. 46 * function are calling it.
47 */ 47 */
48 48
49void radeon_bo_clear_va(struct radeon_bo *bo) 49static void radeon_bo_clear_va(struct radeon_bo *bo)
50{ 50{
51 struct radeon_bo_va *bo_va, *tmp; 51 struct radeon_bo_va *bo_va, *tmp;
52 52
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 984097b907ef..8e8153e471c2 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -924,6 +924,10 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
924 924
925 if (rdev->asic->dpm.powergate_uvd) { 925 if (rdev->asic->dpm.powergate_uvd) {
926 mutex_lock(&rdev->pm.mutex); 926 mutex_lock(&rdev->pm.mutex);
927 /* don't powergate anything if we
928 have active but pause streams */
929 enable |= rdev->pm.dpm.sd > 0;
930 enable |= rdev->pm.dpm.hd > 0;
927 /* enable/disable UVD */ 931 /* enable/disable UVD */
928 radeon_dpm_powergate_uvd(rdev, !enable); 932 radeon_dpm_powergate_uvd(rdev, !enable);
929 mutex_unlock(&rdev->pm.mutex); 933 mutex_unlock(&rdev->pm.mutex);
@@ -1010,8 +1014,10 @@ static void radeon_pm_resume_old(struct radeon_device *rdev)
1010 rdev->pm.current_clock_mode_index = 0; 1014 rdev->pm.current_clock_mode_index = 0;
1011 rdev->pm.current_sclk = rdev->pm.default_sclk; 1015 rdev->pm.current_sclk = rdev->pm.default_sclk;
1012 rdev->pm.current_mclk = rdev->pm.default_mclk; 1016 rdev->pm.current_mclk = rdev->pm.default_mclk;
1013 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1017 if (rdev->pm.power_state) {
1014 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1018 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1019 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1020 }
1015 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1021 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1016 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1022 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1017 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1023 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
@@ -1032,25 +1038,27 @@ static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1032 radeon_dpm_setup_asic(rdev); 1038 radeon_dpm_setup_asic(rdev);
1033 ret = radeon_dpm_enable(rdev); 1039 ret = radeon_dpm_enable(rdev);
1034 mutex_unlock(&rdev->pm.mutex); 1040 mutex_unlock(&rdev->pm.mutex);
1035 if (ret) { 1041 if (ret)
1036 DRM_ERROR("radeon: dpm resume failed\n"); 1042 goto dpm_resume_fail;
1037 if ((rdev->family >= CHIP_BARTS) && 1043 rdev->pm.dpm_enabled = true;
1038 (rdev->family <= CHIP_CAYMAN) && 1044 radeon_pm_compute_clocks(rdev);
1039 rdev->mc_fw) { 1045 return;
1040 if (rdev->pm.default_vddc) 1046
1041 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1047dpm_resume_fail:
1042 SET_VOLTAGE_TYPE_ASIC_VDDC); 1048 DRM_ERROR("radeon: dpm resume failed\n");
1043 if (rdev->pm.default_vddci) 1049 if ((rdev->family >= CHIP_BARTS) &&
1044 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1050 (rdev->family <= CHIP_CAYMAN) &&
1045 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1051 rdev->mc_fw) {
1046 if (rdev->pm.default_sclk) 1052 if (rdev->pm.default_vddc)
1047 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1053 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1048 if (rdev->pm.default_mclk) 1054 SET_VOLTAGE_TYPE_ASIC_VDDC);
1049 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1055 if (rdev->pm.default_vddci)
1050 } 1056 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1051 } else { 1057 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1052 rdev->pm.dpm_enabled = true; 1058 if (rdev->pm.default_sclk)
1053 radeon_pm_compute_clocks(rdev); 1059 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1060 if (rdev->pm.default_mclk)
1061 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1054 } 1062 }
1055} 1063}
1056 1064
@@ -1170,51 +1178,50 @@ static int radeon_pm_init_dpm(struct radeon_device *rdev)
1170 radeon_dpm_setup_asic(rdev); 1178 radeon_dpm_setup_asic(rdev);
1171 ret = radeon_dpm_enable(rdev); 1179 ret = radeon_dpm_enable(rdev);
1172 mutex_unlock(&rdev->pm.mutex); 1180 mutex_unlock(&rdev->pm.mutex);
1173 if (ret) { 1181 if (ret)
1174 rdev->pm.dpm_enabled = false; 1182 goto dpm_failed;
1175 if ((rdev->family >= CHIP_BARTS) &&
1176 (rdev->family <= CHIP_CAYMAN) &&
1177 rdev->mc_fw) {
1178 if (rdev->pm.default_vddc)
1179 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1180 SET_VOLTAGE_TYPE_ASIC_VDDC);
1181 if (rdev->pm.default_vddci)
1182 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1183 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1184 if (rdev->pm.default_sclk)
1185 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1186 if (rdev->pm.default_mclk)
1187 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1188 }
1189 DRM_ERROR("radeon: dpm initialization failed\n");
1190 return ret;
1191 }
1192 rdev->pm.dpm_enabled = true; 1183 rdev->pm.dpm_enabled = true;
1193 radeon_pm_compute_clocks(rdev);
1194 1184
1195 if (rdev->pm.num_power_states > 1) { 1185 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1196 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1186 if (ret)
1197 if (ret) 1187 DRM_ERROR("failed to create device file for dpm state\n");
1198 DRM_ERROR("failed to create device file for dpm state\n"); 1188 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1199 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1189 if (ret)
1200 if (ret) 1190 DRM_ERROR("failed to create device file for dpm state\n");
1201 DRM_ERROR("failed to create device file for dpm state\n"); 1191 /* XXX: these are noops for dpm but are here for backwards compat */
1202 /* XXX: these are noops for dpm but are here for backwards compat */ 1192 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1203 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1193 if (ret)
1204 if (ret) 1194 DRM_ERROR("failed to create device file for power profile\n");
1205 DRM_ERROR("failed to create device file for power profile\n"); 1195 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1206 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1196 if (ret)
1207 if (ret) 1197 DRM_ERROR("failed to create device file for power method\n");
1208 DRM_ERROR("failed to create device file for power method\n");
1209
1210 if (radeon_debugfs_pm_init(rdev)) {
1211 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1212 }
1213 1198
1214 DRM_INFO("radeon: dpm initialized\n"); 1199 if (radeon_debugfs_pm_init(rdev)) {
1200 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1215 } 1201 }
1216 1202
1203 DRM_INFO("radeon: dpm initialized\n");
1204
1217 return 0; 1205 return 0;
1206
1207dpm_failed:
1208 rdev->pm.dpm_enabled = false;
1209 if ((rdev->family >= CHIP_BARTS) &&
1210 (rdev->family <= CHIP_CAYMAN) &&
1211 rdev->mc_fw) {
1212 if (rdev->pm.default_vddc)
1213 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1214 SET_VOLTAGE_TYPE_ASIC_VDDC);
1215 if (rdev->pm.default_vddci)
1216 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1217 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1218 if (rdev->pm.default_sclk)
1219 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1220 if (rdev->pm.default_mclk)
1221 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1222 }
1223 DRM_ERROR("radeon: dpm initialization failed\n");
1224 return ret;
1218} 1225}
1219 1226
1220int radeon_pm_init(struct radeon_device *rdev) 1227int radeon_pm_init(struct radeon_device *rdev)
@@ -1228,11 +1235,10 @@ int radeon_pm_init(struct radeon_device *rdev)
1228 case CHIP_RV670: 1235 case CHIP_RV670:
1229 case CHIP_RS780: 1236 case CHIP_RS780:
1230 case CHIP_RS880: 1237 case CHIP_RS880:
1238 case CHIP_BARTS:
1239 case CHIP_TURKS:
1240 case CHIP_CAICOS:
1231 case CHIP_CAYMAN: 1241 case CHIP_CAYMAN:
1232 case CHIP_BONAIRE:
1233 case CHIP_KABINI:
1234 case CHIP_KAVERI:
1235 case CHIP_HAWAII:
1236 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1242 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1237 if (!rdev->rlc_fw) 1243 if (!rdev->rlc_fw)
1238 rdev->pm.pm_method = PM_METHOD_PROFILE; 1244 rdev->pm.pm_method = PM_METHOD_PROFILE;
@@ -1257,15 +1263,16 @@ int radeon_pm_init(struct radeon_device *rdev)
1257 case CHIP_PALM: 1263 case CHIP_PALM:
1258 case CHIP_SUMO: 1264 case CHIP_SUMO:
1259 case CHIP_SUMO2: 1265 case CHIP_SUMO2:
1260 case CHIP_BARTS:
1261 case CHIP_TURKS:
1262 case CHIP_CAICOS:
1263 case CHIP_ARUBA: 1266 case CHIP_ARUBA:
1264 case CHIP_TAHITI: 1267 case CHIP_TAHITI:
1265 case CHIP_PITCAIRN: 1268 case CHIP_PITCAIRN:
1266 case CHIP_VERDE: 1269 case CHIP_VERDE:
1267 case CHIP_OLAND: 1270 case CHIP_OLAND:
1268 case CHIP_HAINAN: 1271 case CHIP_HAINAN:
1272 case CHIP_BONAIRE:
1273 case CHIP_KABINI:
1274 case CHIP_KAVERI:
1275 case CHIP_HAWAII:
1269 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1276 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1270 if (!rdev->rlc_fw) 1277 if (!rdev->rlc_fw)
1271 rdev->pm.pm_method = PM_METHOD_PROFILE; 1278 rdev->pm.pm_method = PM_METHOD_PROFILE;
@@ -1290,6 +1297,18 @@ int radeon_pm_init(struct radeon_device *rdev)
1290 return radeon_pm_init_old(rdev); 1297 return radeon_pm_init_old(rdev);
1291} 1298}
1292 1299
1300int radeon_pm_late_init(struct radeon_device *rdev)
1301{
1302 int ret = 0;
1303
1304 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1305 mutex_lock(&rdev->pm.mutex);
1306 ret = radeon_dpm_late_enable(rdev);
1307 mutex_unlock(&rdev->pm.mutex);
1308 }
1309 return ret;
1310}
1311
1293static void radeon_pm_fini_old(struct radeon_device *rdev) 1312static void radeon_pm_fini_old(struct radeon_device *rdev)
1294{ 1313{
1295 if (rdev->pm.num_power_states > 1) { 1314 if (rdev->pm.num_power_states > 1) {
@@ -1420,6 +1439,9 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1420 struct drm_crtc *crtc; 1439 struct drm_crtc *crtc;
1421 struct radeon_crtc *radeon_crtc; 1440 struct radeon_crtc *radeon_crtc;
1422 1441
1442 if (!rdev->pm.dpm_enabled)
1443 return;
1444
1423 mutex_lock(&rdev->pm.mutex); 1445 mutex_lock(&rdev->pm.mutex);
1424 1446
1425 /* update active crtc counts */ 1447 /* update active crtc counts */
@@ -1464,7 +1486,7 @@ static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1464 */ 1486 */
1465 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1487 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1466 if (rdev->pm.active_crtcs & (1 << crtc)) { 1488 if (rdev->pm.active_crtcs & (1 << crtc)) {
1467 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos, NULL, NULL); 1489 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1468 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1490 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1469 !(vbl_status & DRM_SCANOUTPOS_INVBL)) 1491 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1470 in_vbl = false; 1492 in_vbl = false;
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 9214403ae173..1b783f0e6d3a 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -332,36 +332,6 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
332 } 332 }
333} 333}
334 334
335u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
336 struct radeon_ring *ring)
337{
338 u32 rptr;
339
340 if (rdev->wb.enabled)
341 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
342 else
343 rptr = RREG32(ring->rptr_reg);
344
345 return rptr;
346}
347
348u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
349 struct radeon_ring *ring)
350{
351 u32 wptr;
352
353 wptr = RREG32(ring->wptr_reg);
354
355 return wptr;
356}
357
358void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
359 struct radeon_ring *ring)
360{
361 WREG32(ring->wptr_reg, ring->wptr);
362 (void)RREG32(ring->wptr_reg);
363}
364
365/** 335/**
366 * radeon_ring_free_size - update the free size 336 * radeon_ring_free_size - update the free size
367 * 337 *
@@ -463,7 +433,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
463 while (ring->wptr & ring->align_mask) { 433 while (ring->wptr & ring->align_mask) {
464 radeon_ring_write(ring, ring->nop); 434 radeon_ring_write(ring, ring->nop);
465 } 435 }
466 DRM_MEMORYBARRIER(); 436 mb();
467 radeon_ring_set_wptr(rdev, ring); 437 radeon_ring_set_wptr(rdev, ring);
468} 438}
469 439
@@ -689,22 +659,18 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
689 * @ring: radeon_ring structure holding ring information 659 * @ring: radeon_ring structure holding ring information
690 * @ring_size: size of the ring 660 * @ring_size: size of the ring
691 * @rptr_offs: offset of the rptr writeback location in the WB buffer 661 * @rptr_offs: offset of the rptr writeback location in the WB buffer
692 * @rptr_reg: MMIO offset of the rptr register
693 * @wptr_reg: MMIO offset of the wptr register
694 * @nop: nop packet for this ring 662 * @nop: nop packet for this ring
695 * 663 *
696 * Initialize the driver information for the selected ring (all asics). 664 * Initialize the driver information for the selected ring (all asics).
697 * Returns 0 on success, error on failure. 665 * Returns 0 on success, error on failure.
698 */ 666 */
699int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, 667int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
700 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop) 668 unsigned rptr_offs, u32 nop)
701{ 669{
702 int r; 670 int r;
703 671
704 ring->ring_size = ring_size; 672 ring->ring_size = ring_size;
705 ring->rptr_offs = rptr_offs; 673 ring->rptr_offs = rptr_offs;
706 ring->rptr_reg = rptr_reg;
707 ring->wptr_reg = wptr_reg;
708 ring->nop = nop; 674 ring->nop = nop;
709 /* Allocate ring buffer */ 675 /* Allocate ring buffer */
710 if (ring->ring_obj == NULL) { 676 if (ring->ring_obj == NULL) {
@@ -790,34 +756,54 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
790 struct radeon_device *rdev = dev->dev_private; 756 struct radeon_device *rdev = dev->dev_private;
791 int ridx = *(int*)node->info_ent->data; 757 int ridx = *(int*)node->info_ent->data;
792 struct radeon_ring *ring = &rdev->ring[ridx]; 758 struct radeon_ring *ring = &rdev->ring[ridx];
759
760 uint32_t rptr, wptr, rptr_next;
793 unsigned count, i, j; 761 unsigned count, i, j;
794 u32 tmp;
795 762
796 radeon_ring_free_size(rdev, ring); 763 radeon_ring_free_size(rdev, ring);
797 count = (ring->ring_size / 4) - ring->ring_free_dw; 764 count = (ring->ring_size / 4) - ring->ring_free_dw;
798 tmp = radeon_ring_get_wptr(rdev, ring); 765
799 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); 766 wptr = radeon_ring_get_wptr(rdev, ring);
800 tmp = radeon_ring_get_rptr(rdev, ring); 767 seq_printf(m, "wptr: 0x%08x [%5d]\n",
801 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); 768 wptr, wptr);
769
770 rptr = radeon_ring_get_rptr(rdev, ring);
771 seq_printf(m, "rptr: 0x%08x [%5d]\n",
772 rptr, rptr);
773
802 if (ring->rptr_save_reg) { 774 if (ring->rptr_save_reg) {
803 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, 775 rptr_next = RREG32(ring->rptr_save_reg);
804 RREG32(ring->rptr_save_reg)); 776 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
805 } 777 ring->rptr_save_reg, rptr_next, rptr_next);
806 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); 778 } else
807 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); 779 rptr_next = ~0;
808 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); 780
809 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); 781 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
782 ring->wptr, ring->wptr);
783 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n",
784 ring->rptr, ring->rptr);
785 seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
786 ring->last_semaphore_signal_addr);
787 seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
788 ring->last_semaphore_wait_addr);
810 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 789 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
811 seq_printf(m, "%u dwords in ring\n", count); 790 seq_printf(m, "%u dwords in ring\n", count);
791
792 if (!ring->ready)
793 return 0;
794
812 /* print 8 dw before current rptr as often it's the last executed 795 /* print 8 dw before current rptr as often it's the last executed
813 * packet that is the root issue 796 * packet that is the root issue
814 */ 797 */
815 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; 798 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
816 if (ring->ready) { 799 for (j = 0; j <= (count + 32); j++) {
817 for (j = 0; j <= (count + 32); j++) { 800 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
818 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); 801 if (rptr == i)
819 i = (i + 1) & ring->ptr_mask; 802 seq_puts(m, " *");
820 } 803 if (rptr_next == i)
804 seq_puts(m, " #");
805 seq_puts(m, "\n");
806 i = (i + 1) & ring->ptr_mask;
821 } 807 }
822 return 0; 808 return 0;
823} 809}
diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index f0bac68254b7..c0625805cdd7 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -402,13 +402,15 @@ void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
402 402
403 spin_lock(&sa_manager->wq.lock); 403 spin_lock(&sa_manager->wq.lock);
404 list_for_each_entry(i, &sa_manager->olist, olist) { 404 list_for_each_entry(i, &sa_manager->olist, olist) {
405 uint64_t soffset = i->soffset + sa_manager->gpu_addr;
406 uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
405 if (&i->olist == sa_manager->hole) { 407 if (&i->olist == sa_manager->hole) {
406 seq_printf(m, ">"); 408 seq_printf(m, ">");
407 } else { 409 } else {
408 seq_printf(m, " "); 410 seq_printf(m, " ");
409 } 411 }
410 seq_printf(m, "[0x%08x 0x%08x] size %8d", 412 seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
411 i->soffset, i->eoffset, i->eoffset - i->soffset); 413 soffset, eoffset, eoffset - soffset);
412 if (i->fence) { 414 if (i->fence) {
413 seq_printf(m, " protected by 0x%016llx on ring %d", 415 seq_printf(m, " protected by 0x%016llx on ring %d",
414 i->fence->seq, i->fence->ring); 416 i->fence->seq, i->fence->ring);
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 4d20910899d4..956ab7f14e16 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1810,7 +1810,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1810 } 1810 }
1811 if (!buf) { 1811 if (!buf) {
1812 DRM_DEBUG("EAGAIN\n"); 1812 DRM_DEBUG("EAGAIN\n");
1813 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 1813 if (copy_to_user(tex->image, image, sizeof(*image)))
1814 return -EFAULT; 1814 return -EFAULT;
1815 return -EAGAIN; 1815 return -EAGAIN;
1816 } 1816 }
@@ -1823,7 +1823,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1823 1823
1824#define RADEON_COPY_MT(_buf, _data, _width) \ 1824#define RADEON_COPY_MT(_buf, _data, _width) \
1825 do { \ 1825 do { \
1826 if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\ 1826 if (copy_from_user(_buf, _data, (_width))) {\
1827 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \ 1827 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
1828 return -EFAULT; \ 1828 return -EFAULT; \
1829 } \ 1829 } \
@@ -2168,7 +2168,7 @@ static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *
2168 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) 2168 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2169 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2169 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2170 2170
2171 if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes, 2171 if (copy_from_user(&depth_boxes, clear->depth_boxes,
2172 sarea_priv->nbox * sizeof(depth_boxes[0]))) 2172 sarea_priv->nbox * sizeof(depth_boxes[0])))
2173 return -EFAULT; 2173 return -EFAULT;
2174 2174
@@ -2436,7 +2436,7 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file
2436 return -EINVAL; 2436 return -EINVAL;
2437 } 2437 }
2438 2438
2439 if (DRM_COPY_FROM_USER(&image, 2439 if (copy_from_user(&image,
2440 (drm_radeon_tex_image_t __user *) tex->image, 2440 (drm_radeon_tex_image_t __user *) tex->image,
2441 sizeof(image))) 2441 sizeof(image)))
2442 return -EFAULT; 2442 return -EFAULT;
@@ -2460,7 +2460,7 @@ static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file
2460 2460
2461 LOCK_TEST_WITH_RETURN(dev, file_priv); 2461 LOCK_TEST_WITH_RETURN(dev, file_priv);
2462 2462
2463 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) 2463 if (copy_from_user(&mask, stipple->mask, 32 * sizeof(u32)))
2464 return -EFAULT; 2464 return -EFAULT;
2465 2465
2466 RING_SPACE_TEST_WITH_RETURN(dev_priv); 2466 RING_SPACE_TEST_WITH_RETURN(dev_priv);
@@ -2585,13 +2585,13 @@ static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file
2585 drm_radeon_prim_t prim; 2585 drm_radeon_prim_t prim;
2586 drm_radeon_tcl_prim_t tclprim; 2586 drm_radeon_tcl_prim_t tclprim;
2587 2587
2588 if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim))) 2588 if (copy_from_user(&prim, &vertex->prim[i], sizeof(prim)))
2589 return -EFAULT; 2589 return -EFAULT;
2590 2590
2591 if (prim.stateidx != laststate) { 2591 if (prim.stateidx != laststate) {
2592 drm_radeon_state_t state; 2592 drm_radeon_state_t state;
2593 2593
2594 if (DRM_COPY_FROM_USER(&state, 2594 if (copy_from_user(&state,
2595 &vertex->state[prim.stateidx], 2595 &vertex->state[prim.stateidx],
2596 sizeof(state))) 2596 sizeof(state)))
2597 return -EFAULT; 2597 return -EFAULT;
@@ -2799,7 +2799,7 @@ static int radeon_emit_packet3_cliprect(struct drm_device *dev,
2799 2799
2800 do { 2800 do {
2801 if (i < cmdbuf->nbox) { 2801 if (i < cmdbuf->nbox) {
2802 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) 2802 if (copy_from_user(&box, &boxes[i], sizeof(box)))
2803 return -EFAULT; 2803 return -EFAULT;
2804 /* FIXME The second and subsequent times round 2804 /* FIXME The second and subsequent times round
2805 * this loop, send a WAIT_UNTIL_3D_IDLE before 2805 * this loop, send a WAIT_UNTIL_3D_IDLE before
@@ -3116,7 +3116,7 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3116 return -EINVAL; 3116 return -EINVAL;
3117 } 3117 }
3118 3118
3119 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 3119 if (copy_to_user(param->value, &value, sizeof(int))) {
3120 DRM_ERROR("copy_to_user\n"); 3120 DRM_ERROR("copy_to_user\n");
3121 return -EFAULT; 3121 return -EFAULT;
3122 } 3122 }
diff --git a/drivers/gpu/drm/radeon/radeon_trace.h b/drivers/gpu/drm/radeon/radeon_trace.h
index 0473257d4078..f749f2c3bbdb 100644
--- a/drivers/gpu/drm/radeon/radeon_trace.h
+++ b/drivers/gpu/drm/radeon/radeon_trace.h
@@ -106,42 +106,45 @@ TRACE_EVENT(radeon_vm_set_page,
106 106
107DECLARE_EVENT_CLASS(radeon_fence_request, 107DECLARE_EVENT_CLASS(radeon_fence_request,
108 108
109 TP_PROTO(struct drm_device *dev, u32 seqno), 109 TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
110 110
111 TP_ARGS(dev, seqno), 111 TP_ARGS(dev, ring, seqno),
112 112
113 TP_STRUCT__entry( 113 TP_STRUCT__entry(
114 __field(u32, dev) 114 __field(u32, dev)
115 __field(int, ring)
115 __field(u32, seqno) 116 __field(u32, seqno)
116 ), 117 ),
117 118
118 TP_fast_assign( 119 TP_fast_assign(
119 __entry->dev = dev->primary->index; 120 __entry->dev = dev->primary->index;
121 __entry->ring = ring;
120 __entry->seqno = seqno; 122 __entry->seqno = seqno;
121 ), 123 ),
122 124
123 TP_printk("dev=%u, seqno=%u", __entry->dev, __entry->seqno) 125 TP_printk("dev=%u, ring=%d, seqno=%u",
126 __entry->dev, __entry->ring, __entry->seqno)
124); 127);
125 128
126DEFINE_EVENT(radeon_fence_request, radeon_fence_emit, 129DEFINE_EVENT(radeon_fence_request, radeon_fence_emit,
127 130
128 TP_PROTO(struct drm_device *dev, u32 seqno), 131 TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
129 132
130 TP_ARGS(dev, seqno) 133 TP_ARGS(dev, ring, seqno)
131); 134);
132 135
133DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin, 136DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin,
134 137
135 TP_PROTO(struct drm_device *dev, u32 seqno), 138 TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
136 139
137 TP_ARGS(dev, seqno) 140 TP_ARGS(dev, ring, seqno)
138); 141);
139 142
140DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_end, 143DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_end,
141 144
142 TP_PROTO(struct drm_device *dev, u32 seqno), 145 TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
143 146
144 TP_ARGS(dev, seqno) 147 TP_ARGS(dev, ring, seqno)
145); 148);
146 149
147DECLARE_EVENT_CLASS(radeon_semaphore_request, 150DECLARE_EVENT_CLASS(radeon_semaphore_request,
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 71245d6f34a2..77f5b0c3edb8 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -39,12 +39,14 @@
39#include <linux/seq_file.h> 39#include <linux/seq_file.h>
40#include <linux/slab.h> 40#include <linux/slab.h>
41#include <linux/swiotlb.h> 41#include <linux/swiotlb.h>
42#include <linux/debugfs.h>
42#include "radeon_reg.h" 43#include "radeon_reg.h"
43#include "radeon.h" 44#include "radeon.h"
44 45
45#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 46#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
46 47
47static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 48static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
49static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
48 50
49static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 51static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
50{ 52{
@@ -142,7 +144,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
142 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 144 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
143#if __OS_HAS_AGP 145#if __OS_HAS_AGP
144 if (rdev->flags & RADEON_IS_AGP) { 146 if (rdev->flags & RADEON_IS_AGP) {
145 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { 147 if (!rdev->ddev->agp) {
146 DRM_ERROR("AGP is not enabled for memory type %u\n", 148 DRM_ERROR("AGP is not enabled for memory type %u\n",
147 (unsigned)type); 149 (unsigned)type);
148 return -EINVAL; 150 return -EINVAL;
@@ -753,6 +755,7 @@ void radeon_ttm_fini(struct radeon_device *rdev)
753 755
754 if (!rdev->mman.initialized) 756 if (!rdev->mman.initialized)
755 return; 757 return;
758 radeon_ttm_debugfs_fini(rdev);
756 if (rdev->stollen_vga_memory) { 759 if (rdev->stollen_vga_memory) {
757 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 760 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
758 if (r == 0) { 761 if (r == 0) {
@@ -832,16 +835,15 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
832 return 0; 835 return 0;
833} 836}
834 837
835
836#define RADEON_DEBUGFS_MEM_TYPES 2
837
838#if defined(CONFIG_DEBUG_FS) 838#if defined(CONFIG_DEBUG_FS)
839
839static int radeon_mm_dump_table(struct seq_file *m, void *data) 840static int radeon_mm_dump_table(struct seq_file *m, void *data)
840{ 841{
841 struct drm_info_node *node = (struct drm_info_node *)m->private; 842 struct drm_info_node *node = (struct drm_info_node *)m->private;
842 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; 843 unsigned ttm_pl = *(int *)node->info_ent->data;
843 struct drm_device *dev = node->minor->dev; 844 struct drm_device *dev = node->minor->dev;
844 struct radeon_device *rdev = dev->dev_private; 845 struct radeon_device *rdev = dev->dev_private;
846 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
845 int ret; 847 int ret;
846 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 848 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
847 849
@@ -850,46 +852,169 @@ static int radeon_mm_dump_table(struct seq_file *m, void *data)
850 spin_unlock(&glob->lru_lock); 852 spin_unlock(&glob->lru_lock);
851 return ret; 853 return ret;
852} 854}
855
856static int ttm_pl_vram = TTM_PL_VRAM;
857static int ttm_pl_tt = TTM_PL_TT;
858
859static struct drm_info_list radeon_ttm_debugfs_list[] = {
860 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
861 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
862 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
863#ifdef CONFIG_SWIOTLB
864 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
853#endif 865#endif
866};
854 867
855static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 868static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
856{ 869{
857#if defined(CONFIG_DEBUG_FS) 870 struct radeon_device *rdev = inode->i_private;
858 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; 871 i_size_write(inode, rdev->mc.mc_vram_size);
859 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; 872 filep->private_data = inode->i_private;
860 unsigned i; 873 return 0;
874}
861 875
862 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { 876static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
863 if (i == 0) 877 size_t size, loff_t *pos)
864 sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); 878{
865 else 879 struct radeon_device *rdev = f->private_data;
866 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); 880 ssize_t result = 0;
867 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 881 int r;
868 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
869 radeon_mem_types_list[i].driver_features = 0;
870 if (i == 0)
871 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
872 else
873 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
874 882
883 if (size & 0x3 || *pos & 0x3)
884 return -EINVAL;
885
886 while (size) {
887 unsigned long flags;
888 uint32_t value;
889
890 if (*pos >= rdev->mc.mc_vram_size)
891 return result;
892
893 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
894 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
895 if (rdev->family >= CHIP_CEDAR)
896 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
897 value = RREG32(RADEON_MM_DATA);
898 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
899
900 r = put_user(value, (uint32_t *)buf);
901 if (r)
902 return r;
903
904 result += 4;
905 buf += 4;
906 *pos += 4;
907 size -= 4;
875 } 908 }
876 /* Add ttm page pool to debugfs */ 909
877 sprintf(radeon_mem_types_names[i], "ttm_page_pool"); 910 return result;
878 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 911}
879 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; 912
880 radeon_mem_types_list[i].driver_features = 0; 913static const struct file_operations radeon_ttm_vram_fops = {
881 radeon_mem_types_list[i++].data = NULL; 914 .owner = THIS_MODULE,
882#ifdef CONFIG_SWIOTLB 915 .open = radeon_ttm_vram_open,
883 if (swiotlb_nr_tbl()) { 916 .read = radeon_ttm_vram_read,
884 sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); 917 .llseek = default_llseek
885 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 918};
886 radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; 919
887 radeon_mem_types_list[i].driver_features = 0; 920static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
888 radeon_mem_types_list[i++].data = NULL; 921{
922 struct radeon_device *rdev = inode->i_private;
923 i_size_write(inode, rdev->mc.gtt_size);
924 filep->private_data = inode->i_private;
925 return 0;
926}
927
928static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
929 size_t size, loff_t *pos)
930{
931 struct radeon_device *rdev = f->private_data;
932 ssize_t result = 0;
933 int r;
934
935 while (size) {
936 loff_t p = *pos / PAGE_SIZE;
937 unsigned off = *pos & ~PAGE_MASK;
938 ssize_t cur_size = min(size, PAGE_SIZE - off);
939 struct page *page;
940 void *ptr;
941
942 if (p >= rdev->gart.num_cpu_pages)
943 return result;
944
945 page = rdev->gart.pages[p];
946 if (page) {
947 ptr = kmap(page);
948 ptr += off;
949
950 r = copy_to_user(buf, ptr, cur_size);
951 kunmap(rdev->gart.pages[p]);
952 } else
953 r = clear_user(buf, cur_size);
954
955 if (r)
956 return -EFAULT;
957
958 result += cur_size;
959 buf += cur_size;
960 *pos += cur_size;
961 size -= cur_size;
889 } 962 }
963
964 return result;
965}
966
967static const struct file_operations radeon_ttm_gtt_fops = {
968 .owner = THIS_MODULE,
969 .open = radeon_ttm_gtt_open,
970 .read = radeon_ttm_gtt_read,
971 .llseek = default_llseek
972};
973
890#endif 974#endif
891 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i);
892 975
976static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
977{
978#if defined(CONFIG_DEBUG_FS)
979 unsigned count;
980
981 struct drm_minor *minor = rdev->ddev->primary;
982 struct dentry *ent, *root = minor->debugfs_root;
983
984 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
985 rdev, &radeon_ttm_vram_fops);
986 if (IS_ERR(ent))
987 return PTR_ERR(ent);
988 rdev->mman.vram = ent;
989
990 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
991 rdev, &radeon_ttm_gtt_fops);
992 if (IS_ERR(ent))
993 return PTR_ERR(ent);
994 rdev->mman.gtt = ent;
995
996 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
997
998#ifdef CONFIG_SWIOTLB
999 if (!swiotlb_nr_tbl())
1000 --count;
893#endif 1001#endif
1002
1003 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1004#else
1005
894 return 0; 1006 return 0;
1007#endif
1008}
1009
1010static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1011{
1012#if defined(CONFIG_DEBUG_FS)
1013
1014 debugfs_remove(rdev->mman.vram);
1015 rdev->mman.vram = NULL;
1016
1017 debugfs_remove(rdev->mman.gtt);
1018 rdev->mman.gtt = NULL;
1019#endif
895} 1020}
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index b9c0529b4a2e..6781fee1eaad 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -91,6 +91,7 @@ int radeon_uvd_init(struct radeon_device *rdev)
91 case CHIP_VERDE: 91 case CHIP_VERDE:
92 case CHIP_PITCAIRN: 92 case CHIP_PITCAIRN:
93 case CHIP_ARUBA: 93 case CHIP_ARUBA:
94 case CHIP_OLAND:
94 fw_name = FIRMWARE_TAHITI; 95 fw_name = FIRMWARE_TAHITI;
95 break; 96 break;
96 97
@@ -778,6 +779,8 @@ static void radeon_uvd_idle_work_handler(struct work_struct *work)
778 779
779 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { 780 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
780 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 781 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
782 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
783 &rdev->pm.dpm.hd);
781 radeon_dpm_enable_uvd(rdev, false); 784 radeon_dpm_enable_uvd(rdev, false);
782 } else { 785 } else {
783 radeon_set_uvd_clocks(rdev, 0, 0); 786 radeon_set_uvd_clocks(rdev, 0, 0);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 9566b5940a5a..b5c2369cda2f 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -474,6 +474,8 @@ int rs400_resume(struct radeon_device *rdev)
474 /* Initialize surface registers */ 474 /* Initialize surface registers */
475 radeon_surface_init(rdev); 475 radeon_surface_init(rdev);
476 476
477 radeon_pm_resume(rdev);
478
477 rdev->accel_working = true; 479 rdev->accel_working = true;
478 r = rs400_startup(rdev); 480 r = rs400_startup(rdev);
479 if (r) { 481 if (r) {
@@ -484,6 +486,7 @@ int rs400_resume(struct radeon_device *rdev)
484 486
485int rs400_suspend(struct radeon_device *rdev) 487int rs400_suspend(struct radeon_device *rdev)
486{ 488{
489 radeon_pm_suspend(rdev);
487 r100_cp_disable(rdev); 490 r100_cp_disable(rdev);
488 radeon_wb_disable(rdev); 491 radeon_wb_disable(rdev);
489 r100_irq_disable(rdev); 492 r100_irq_disable(rdev);
@@ -493,6 +496,7 @@ int rs400_suspend(struct radeon_device *rdev)
493 496
494void rs400_fini(struct radeon_device *rdev) 497void rs400_fini(struct radeon_device *rdev)
495{ 498{
499 radeon_pm_fini(rdev);
496 r100_cp_fini(rdev); 500 r100_cp_fini(rdev);
497 radeon_wb_fini(rdev); 501 radeon_wb_fini(rdev);
498 radeon_ib_pool_fini(rdev); 502 radeon_ib_pool_fini(rdev);
@@ -560,6 +564,9 @@ int rs400_init(struct radeon_device *rdev)
560 return r; 564 return r;
561 r300_set_reg_safe(rdev); 565 r300_set_reg_safe(rdev);
562 566
567 /* Initialize power management */
568 radeon_pm_init(rdev);
569
563 rdev->accel_working = true; 570 rdev->accel_working = true;
564 r = rs400_startup(rdev); 571 r = rs400_startup(rdev);
565 if (r) { 572 if (r) {
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 76cc8d3aafec..fdcde7693032 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -1048,6 +1048,8 @@ int rs600_resume(struct radeon_device *rdev)
1048 /* Initialize surface registers */ 1048 /* Initialize surface registers */
1049 radeon_surface_init(rdev); 1049 radeon_surface_init(rdev);
1050 1050
1051 radeon_pm_resume(rdev);
1052
1051 rdev->accel_working = true; 1053 rdev->accel_working = true;
1052 r = rs600_startup(rdev); 1054 r = rs600_startup(rdev);
1053 if (r) { 1055 if (r) {
@@ -1058,6 +1060,7 @@ int rs600_resume(struct radeon_device *rdev)
1058 1060
1059int rs600_suspend(struct radeon_device *rdev) 1061int rs600_suspend(struct radeon_device *rdev)
1060{ 1062{
1063 radeon_pm_suspend(rdev);
1061 r600_audio_fini(rdev); 1064 r600_audio_fini(rdev);
1062 r100_cp_disable(rdev); 1065 r100_cp_disable(rdev);
1063 radeon_wb_disable(rdev); 1066 radeon_wb_disable(rdev);
@@ -1068,6 +1071,7 @@ int rs600_suspend(struct radeon_device *rdev)
1068 1071
1069void rs600_fini(struct radeon_device *rdev) 1072void rs600_fini(struct radeon_device *rdev)
1070{ 1073{
1074 radeon_pm_fini(rdev);
1071 r600_audio_fini(rdev); 1075 r600_audio_fini(rdev);
1072 r100_cp_fini(rdev); 1076 r100_cp_fini(rdev);
1073 radeon_wb_fini(rdev); 1077 radeon_wb_fini(rdev);
@@ -1136,6 +1140,9 @@ int rs600_init(struct radeon_device *rdev)
1136 return r; 1140 return r;
1137 rs600_set_safe_registers(rdev); 1141 rs600_set_safe_registers(rdev);
1138 1142
1143 /* Initialize power management */
1144 radeon_pm_init(rdev);
1145
1139 rdev->accel_working = true; 1146 rdev->accel_working = true;
1140 r = rs600_startup(rdev); 1147 r = rs600_startup(rdev);
1141 if (r) { 1148 if (r) {
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index e7dab069cccf..35950738bd5e 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -756,6 +756,8 @@ int rs690_resume(struct radeon_device *rdev)
756 /* Initialize surface registers */ 756 /* Initialize surface registers */
757 radeon_surface_init(rdev); 757 radeon_surface_init(rdev);
758 758
759 radeon_pm_resume(rdev);
760
759 rdev->accel_working = true; 761 rdev->accel_working = true;
760 r = rs690_startup(rdev); 762 r = rs690_startup(rdev);
761 if (r) { 763 if (r) {
@@ -766,6 +768,7 @@ int rs690_resume(struct radeon_device *rdev)
766 768
767int rs690_suspend(struct radeon_device *rdev) 769int rs690_suspend(struct radeon_device *rdev)
768{ 770{
771 radeon_pm_suspend(rdev);
769 r600_audio_fini(rdev); 772 r600_audio_fini(rdev);
770 r100_cp_disable(rdev); 773 r100_cp_disable(rdev);
771 radeon_wb_disable(rdev); 774 radeon_wb_disable(rdev);
@@ -776,6 +779,7 @@ int rs690_suspend(struct radeon_device *rdev)
776 779
777void rs690_fini(struct radeon_device *rdev) 780void rs690_fini(struct radeon_device *rdev)
778{ 781{
782 radeon_pm_fini(rdev);
779 r600_audio_fini(rdev); 783 r600_audio_fini(rdev);
780 r100_cp_fini(rdev); 784 r100_cp_fini(rdev);
781 radeon_wb_fini(rdev); 785 radeon_wb_fini(rdev);
@@ -845,6 +849,9 @@ int rs690_init(struct radeon_device *rdev)
845 return r; 849 return r;
846 rs600_set_safe_registers(rdev); 850 rs600_set_safe_registers(rdev);
847 851
852 /* Initialize power management */
853 radeon_pm_init(rdev);
854
848 rdev->accel_working = true; 855 rdev->accel_working = true;
849 r = rs690_startup(rdev); 856 r = rs690_startup(rdev);
850 if (r) { 857 if (r) {
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c
index 6af8505cf4d2..8512085b0aef 100644
--- a/drivers/gpu/drm/radeon/rs780_dpm.c
+++ b/drivers/gpu/drm/radeon/rs780_dpm.c
@@ -623,14 +623,6 @@ int rs780_dpm_enable(struct radeon_device *rdev)
623 if (pi->gfx_clock_gating) 623 if (pi->gfx_clock_gating)
624 r600_gfx_clockgating_enable(rdev, true); 624 r600_gfx_clockgating_enable(rdev, true);
625 625
626 if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
627 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
628 if (ret)
629 return ret;
630 rdev->irq.dpm_thermal = true;
631 radeon_irq_set(rdev);
632 }
633
634 return 0; 626 return 0;
635} 627}
636 628
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 5d1c316115ef..98e8138ff779 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -586,6 +586,8 @@ int rv515_resume(struct radeon_device *rdev)
586 /* Initialize surface registers */ 586 /* Initialize surface registers */
587 radeon_surface_init(rdev); 587 radeon_surface_init(rdev);
588 588
589 radeon_pm_resume(rdev);
590
589 rdev->accel_working = true; 591 rdev->accel_working = true;
590 r = rv515_startup(rdev); 592 r = rv515_startup(rdev);
591 if (r) { 593 if (r) {
@@ -596,6 +598,7 @@ int rv515_resume(struct radeon_device *rdev)
596 598
597int rv515_suspend(struct radeon_device *rdev) 599int rv515_suspend(struct radeon_device *rdev)
598{ 600{
601 radeon_pm_suspend(rdev);
599 r100_cp_disable(rdev); 602 r100_cp_disable(rdev);
600 radeon_wb_disable(rdev); 603 radeon_wb_disable(rdev);
601 rs600_irq_disable(rdev); 604 rs600_irq_disable(rdev);
@@ -612,6 +615,7 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
612 615
613void rv515_fini(struct radeon_device *rdev) 616void rv515_fini(struct radeon_device *rdev)
614{ 617{
618 radeon_pm_fini(rdev);
615 r100_cp_fini(rdev); 619 r100_cp_fini(rdev);
616 radeon_wb_fini(rdev); 620 radeon_wb_fini(rdev);
617 radeon_ib_pool_fini(rdev); 621 radeon_ib_pool_fini(rdev);
@@ -685,6 +689,9 @@ int rv515_init(struct radeon_device *rdev)
685 return r; 689 return r;
686 rv515_set_safe_registers(rdev); 690 rv515_set_safe_registers(rdev);
687 691
692 /* Initialize power management */
693 radeon_pm_init(rdev);
694
688 rdev->accel_working = true; 695 rdev->accel_working = true;
689 r = rv515_startup(rdev); 696 r = rv515_startup(rdev);
690 if (r) { 697 if (r) {
diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index 26633a025252..bebf31c4d841 100644
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -1546,7 +1546,6 @@ int rv6xx_dpm_enable(struct radeon_device *rdev)
1546{ 1546{
1547 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); 1547 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1549 int ret;
1550 1549
1551 if (r600_dynamicpm_enabled(rdev)) 1550 if (r600_dynamicpm_enabled(rdev))
1552 return -EINVAL; 1551 return -EINVAL;
@@ -1594,15 +1593,6 @@ int rv6xx_dpm_enable(struct radeon_device *rdev)
1594 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); 1593 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1595 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); 1594 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1596 1595
1597 if (rdev->irq.installed &&
1598 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1599 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1600 if (ret)
1601 return ret;
1602 rdev->irq.dpm_thermal = true;
1603 radeon_irq_set(rdev);
1604 }
1605
1606 rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 1596 rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1607 1597
1608 r600_start_dpm(rdev); 1598 r600_start_dpm(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 9f5846743c9e..6c772e58c784 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1071,7 +1071,8 @@ static void rv770_mc_program(struct radeon_device *rdev)
1071 */ 1071 */
1072void r700_cp_stop(struct radeon_device *rdev) 1072void r700_cp_stop(struct radeon_device *rdev)
1073{ 1073{
1074 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1074 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1075 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1075 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 1076 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1076 WREG32(SCRATCH_UMSK, 0); 1077 WREG32(SCRATCH_UMSK, 0);
1077 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1078 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -1123,6 +1124,35 @@ void r700_cp_fini(struct radeon_device *rdev)
1123 radeon_scratch_free(rdev, ring->rptr_save_reg); 1124 radeon_scratch_free(rdev, ring->rptr_save_reg);
1124} 1125}
1125 1126
1127void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
1128{
1129 u32 tmp, i;
1130
1131 if (rdev->flags & RADEON_IS_IGP)
1132 return;
1133
1134 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1135 tmp &= SCLK_MUX_SEL_MASK;
1136 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1137 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1138
1139 for (i = 0; i < rdev->usec_timeout; i++) {
1140 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
1141 break;
1142 udelay(1);
1143 }
1144
1145 tmp &= ~SCLK_MUX_UPDATE;
1146 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1147
1148 tmp = RREG32(MPLL_CNTL_MODE);
1149 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1150 tmp &= ~RV730_MPLL_MCLK_SEL;
1151 else
1152 tmp &= ~MPLL_MCLK_SEL;
1153 WREG32(MPLL_CNTL_MODE, tmp);
1154}
1155
1126/* 1156/*
1127 * Core functions 1157 * Core functions
1128 */ 1158 */
@@ -1665,14 +1695,6 @@ static int rv770_startup(struct radeon_device *rdev)
1665 1695
1666 rv770_mc_program(rdev); 1696 rv770_mc_program(rdev);
1667 1697
1668 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1669 r = r600_init_microcode(rdev);
1670 if (r) {
1671 DRM_ERROR("Failed to load firmware!\n");
1672 return r;
1673 }
1674 }
1675
1676 if (rdev->flags & RADEON_IS_AGP) { 1698 if (rdev->flags & RADEON_IS_AGP) {
1677 rv770_agp_enable(rdev); 1699 rv770_agp_enable(rdev);
1678 } else { 1700 } else {
@@ -1728,14 +1750,12 @@ static int rv770_startup(struct radeon_device *rdev)
1728 1750
1729 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1751 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1730 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 1752 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1731 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
1732 RADEON_CP_PACKET2); 1753 RADEON_CP_PACKET2);
1733 if (r) 1754 if (r)
1734 return r; 1755 return r;
1735 1756
1736 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 1757 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1737 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 1758 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1738 DMA_RB_RPTR, DMA_RB_WPTR,
1739 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 1759 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1740 if (r) 1760 if (r)
1741 return r; 1761 return r;
@@ -1754,7 +1774,6 @@ static int rv770_startup(struct radeon_device *rdev)
1754 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 1774 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1755 if (ring->ring_size) { 1775 if (ring->ring_size) {
1756 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 1776 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
1757 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1758 RADEON_CP_PACKET2); 1777 RADEON_CP_PACKET2);
1759 if (!r) 1778 if (!r)
1760 r = uvd_v1_0_init(rdev); 1779 r = uvd_v1_0_init(rdev);
@@ -1792,6 +1811,8 @@ int rv770_resume(struct radeon_device *rdev)
1792 /* init golden registers */ 1811 /* init golden registers */
1793 rv770_init_golden_registers(rdev); 1812 rv770_init_golden_registers(rdev);
1794 1813
1814 radeon_pm_resume(rdev);
1815
1795 rdev->accel_working = true; 1816 rdev->accel_working = true;
1796 r = rv770_startup(rdev); 1817 r = rv770_startup(rdev);
1797 if (r) { 1818 if (r) {
@@ -1806,6 +1827,7 @@ int rv770_resume(struct radeon_device *rdev)
1806 1827
1807int rv770_suspend(struct radeon_device *rdev) 1828int rv770_suspend(struct radeon_device *rdev)
1808{ 1829{
1830 radeon_pm_suspend(rdev);
1809 r600_audio_fini(rdev); 1831 r600_audio_fini(rdev);
1810 uvd_v1_0_fini(rdev); 1832 uvd_v1_0_fini(rdev);
1811 radeon_uvd_suspend(rdev); 1833 radeon_uvd_suspend(rdev);
@@ -1876,6 +1898,17 @@ int rv770_init(struct radeon_device *rdev)
1876 if (r) 1898 if (r)
1877 return r; 1899 return r;
1878 1900
1901 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1902 r = r600_init_microcode(rdev);
1903 if (r) {
1904 DRM_ERROR("Failed to load firmware!\n");
1905 return r;
1906 }
1907 }
1908
1909 /* Initialize power management */
1910 radeon_pm_init(rdev);
1911
1879 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 1912 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1880 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 1913 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1881 1914
@@ -1915,6 +1948,7 @@ int rv770_init(struct radeon_device *rdev)
1915 1948
1916void rv770_fini(struct radeon_device *rdev) 1949void rv770_fini(struct radeon_device *rdev)
1917{ 1950{
1951 radeon_pm_fini(rdev);
1918 r700_cp_fini(rdev); 1952 r700_cp_fini(rdev);
1919 r600_dma_fini(rdev); 1953 r600_dma_fini(rdev);
1920 r600_irq_fini(rdev); 1954 r600_irq_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 374499db20c7..80c595aba359 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -1863,8 +1863,8 @@ void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
1863 } 1863 }
1864} 1864}
1865 1865
1866int rv770_set_thermal_temperature_range(struct radeon_device *rdev, 1866static int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
1867 int min_temp, int max_temp) 1867 int min_temp, int max_temp)
1868{ 1868{
1869 int low_temp = 0 * 1000; 1869 int low_temp = 0 * 1000;
1870 int high_temp = 255 * 1000; 1870 int high_temp = 255 * 1000;
@@ -1966,6 +1966,15 @@ int rv770_dpm_enable(struct radeon_device *rdev)
1966 if (pi->mg_clock_gating) 1966 if (pi->mg_clock_gating)
1967 rv770_mg_clock_gating_enable(rdev, true); 1967 rv770_mg_clock_gating_enable(rdev, true);
1968 1968
1969 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1970
1971 return 0;
1972}
1973
1974int rv770_dpm_late_enable(struct radeon_device *rdev)
1975{
1976 int ret;
1977
1969 if (rdev->irq.installed && 1978 if (rdev->irq.installed &&
1970 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1979 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1971 PPSMC_Result result; 1980 PPSMC_Result result;
@@ -1981,8 +1990,6 @@ int rv770_dpm_enable(struct radeon_device *rdev)
1981 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 1990 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1982 } 1991 }
1983 1992
1984 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1985
1986 return 0; 1993 return 0;
1987} 1994}
1988 1995
@@ -2244,14 +2251,12 @@ static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev,
2244 pl->vddci = vddci; 2251 pl->vddci = vddci;
2245 } 2252 }
2246 2253
2247 if (rdev->family >= CHIP_BARTS) { 2254 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2248 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2255 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2249 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 2256 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
2250 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 2257 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
2251 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 2258 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
2252 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 2259 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
2253 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
2254 }
2255 } 2260 }
2256} 2261}
2257 2262
@@ -2531,6 +2536,12 @@ bool rv770_dpm_vblank_too_short(struct radeon_device *rdev)
2531 (rdev->pdev->subsystem_device == 0x1c42)) 2536 (rdev->pdev->subsystem_device == 0x1c42))
2532 switch_limit = 200; 2537 switch_limit = 200;
2533 2538
2539 /* RV770 */
2540 /* mclk switching doesn't seem to work reliably on desktop RV770s */
2541 if ((rdev->family == CHIP_RV770) &&
2542 !(rdev->flags & RADEON_IS_MOBILITY))
2543 switch_limit = 0xffffffff; /* disable mclk switching */
2544
2534 if (vblank_time < switch_limit) 2545 if (vblank_time < switch_limit)
2535 return true; 2546 return true;
2536 else 2547 else
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h
index 9244effc6b59..f776634840c9 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.h
+++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -283,8 +283,4 @@ int rv770_read_smc_soft_register(struct radeon_device *rdev,
283int rv770_write_smc_soft_register(struct radeon_device *rdev, 283int rv770_write_smc_soft_register(struct radeon_device *rdev,
284 u16 reg_offset, u32 value); 284 u16 reg_offset, u32 value);
285 285
286/* thermal */
287int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
288 int min_temp, int max_temp);
289
290#endif 286#endif
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 1ae277152cc7..3cf1e2921545 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -100,14 +100,21 @@
100#define CG_SPLL_FUNC_CNTL_2 0x604 100#define CG_SPLL_FUNC_CNTL_2 0x604
101#define SCLK_MUX_SEL(x) ((x) << 0) 101#define SCLK_MUX_SEL(x) ((x) << 0)
102#define SCLK_MUX_SEL_MASK (0x1ff << 0) 102#define SCLK_MUX_SEL_MASK (0x1ff << 0)
103#define SCLK_MUX_UPDATE (1 << 26)
103#define CG_SPLL_FUNC_CNTL_3 0x608 104#define CG_SPLL_FUNC_CNTL_3 0x608
104#define SPLL_FB_DIV(x) ((x) << 0) 105#define SPLL_FB_DIV(x) ((x) << 0)
105#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 106#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
106#define SPLL_DITHEN (1 << 28) 107#define SPLL_DITHEN (1 << 28)
108#define CG_SPLL_STATUS 0x60c
109#define SPLL_CHG_STATUS (1 << 1)
107 110
108#define SPLL_CNTL_MODE 0x610 111#define SPLL_CNTL_MODE 0x610
109#define SPLL_DIV_SYNC (1 << 5) 112#define SPLL_DIV_SYNC (1 << 5)
110 113
114#define MPLL_CNTL_MODE 0x61c
115# define MPLL_MCLK_SEL (1 << 11)
116# define RV730_MPLL_MCLK_SEL (1 << 25)
117
111#define MPLL_AD_FUNC_CNTL 0x624 118#define MPLL_AD_FUNC_CNTL 0x624
112#define CLKF(x) ((x) << 0) 119#define CLKF(x) ((x) << 0)
113#define CLKF_MASK (0x7f << 0) 120#define CLKF_MASK (0x7f << 0)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 85e1edfaa3be..09ec4f6c53bb 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -80,6 +80,8 @@ extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
80extern bool evergreen_is_display_hung(struct radeon_device *rdev); 80extern bool evergreen_is_display_hung(struct radeon_device *rdev);
81static void si_enable_gui_idle_interrupt(struct radeon_device *rdev, 81static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
82 bool enable); 82 bool enable);
83static void si_init_pg(struct radeon_device *rdev);
84static void si_init_cg(struct radeon_device *rdev);
83static void si_fini_pg(struct radeon_device *rdev); 85static void si_fini_pg(struct radeon_device *rdev);
84static void si_fini_cg(struct radeon_device *rdev); 86static void si_fini_cg(struct radeon_device *rdev);
85static void si_rlc_stop(struct radeon_device *rdev); 87static void si_rlc_stop(struct radeon_device *rdev);
@@ -1460,7 +1462,7 @@ static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1460}; 1462};
1461 1463
1462/* ucode loading */ 1464/* ucode loading */
1463static int si_mc_load_microcode(struct radeon_device *rdev) 1465int si_mc_load_microcode(struct radeon_device *rdev)
1464{ 1466{
1465 const __be32 *fw_data; 1467 const __be32 *fw_data;
1466 u32 running, blackout = 0; 1468 u32 running, blackout = 0;
@@ -3247,7 +3249,8 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
3247 if (enable) 3249 if (enable)
3248 WREG32(CP_ME_CNTL, 0); 3250 WREG32(CP_ME_CNTL, 0);
3249 else { 3251 else {
3250 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 3252 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3253 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3251 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 3254 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3252 WREG32(SCRATCH_UMSK, 0); 3255 WREG32(SCRATCH_UMSK, 0);
3253 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3256 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
@@ -3508,6 +3511,9 @@ static int si_cp_resume(struct radeon_device *rdev)
3508 3511
3509 si_enable_gui_idle_interrupt(rdev, true); 3512 si_enable_gui_idle_interrupt(rdev, true);
3510 3513
3514 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3515 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3516
3511 return 0; 3517 return 0;
3512} 3518}
3513 3519
@@ -3724,6 +3730,106 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3724 evergreen_print_gpu_status_regs(rdev); 3730 evergreen_print_gpu_status_regs(rdev);
3725} 3731}
3726 3732
3733static void si_set_clk_bypass_mode(struct radeon_device *rdev)
3734{
3735 u32 tmp, i;
3736
3737 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3738 tmp |= SPLL_BYPASS_EN;
3739 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3740
3741 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3742 tmp |= SPLL_CTLREQ_CHG;
3743 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3744
3745 for (i = 0; i < rdev->usec_timeout; i++) {
3746 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
3747 break;
3748 udelay(1);
3749 }
3750
3751 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3752 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
3753 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3754
3755 tmp = RREG32(MPLL_CNTL_MODE);
3756 tmp &= ~MPLL_MCLK_SEL;
3757 WREG32(MPLL_CNTL_MODE, tmp);
3758}
3759
3760static void si_spll_powerdown(struct radeon_device *rdev)
3761{
3762 u32 tmp;
3763
3764 tmp = RREG32(SPLL_CNTL_MODE);
3765 tmp |= SPLL_SW_DIR_CONTROL;
3766 WREG32(SPLL_CNTL_MODE, tmp);
3767
3768 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3769 tmp |= SPLL_RESET;
3770 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3771
3772 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3773 tmp |= SPLL_SLEEP;
3774 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3775
3776 tmp = RREG32(SPLL_CNTL_MODE);
3777 tmp &= ~SPLL_SW_DIR_CONTROL;
3778 WREG32(SPLL_CNTL_MODE, tmp);
3779}
3780
3781static void si_gpu_pci_config_reset(struct radeon_device *rdev)
3782{
3783 struct evergreen_mc_save save;
3784 u32 tmp, i;
3785
3786 dev_info(rdev->dev, "GPU pci config reset\n");
3787
3788 /* disable dpm? */
3789
3790 /* disable cg/pg */
3791 si_fini_pg(rdev);
3792 si_fini_cg(rdev);
3793
3794 /* Disable CP parsing/prefetching */
3795 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3796 /* dma0 */
3797 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3798 tmp &= ~DMA_RB_ENABLE;
3799 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3800 /* dma1 */
3801 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3802 tmp &= ~DMA_RB_ENABLE;
3803 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3804 /* XXX other engines? */
3805
3806 /* halt the rlc, disable cp internal ints */
3807 si_rlc_stop(rdev);
3808
3809 udelay(50);
3810
3811 /* disable mem access */
3812 evergreen_mc_stop(rdev, &save);
3813 if (evergreen_mc_wait_for_idle(rdev)) {
3814 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
3815 }
3816
3817 /* set mclk/sclk to bypass */
3818 si_set_clk_bypass_mode(rdev);
3819 /* powerdown spll */
3820 si_spll_powerdown(rdev);
3821 /* disable BM */
3822 pci_clear_master(rdev->pdev);
3823 /* reset */
3824 radeon_pci_config_reset(rdev);
3825 /* wait for asic to come out of reset */
3826 for (i = 0; i < rdev->usec_timeout; i++) {
3827 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
3828 break;
3829 udelay(1);
3830 }
3831}
3832
3727int si_asic_reset(struct radeon_device *rdev) 3833int si_asic_reset(struct radeon_device *rdev)
3728{ 3834{
3729 u32 reset_mask; 3835 u32 reset_mask;
@@ -3733,10 +3839,17 @@ int si_asic_reset(struct radeon_device *rdev)
3733 if (reset_mask) 3839 if (reset_mask)
3734 r600_set_bios_scratch_engine_hung(rdev, true); 3840 r600_set_bios_scratch_engine_hung(rdev, true);
3735 3841
3842 /* try soft reset */
3736 si_gpu_soft_reset(rdev, reset_mask); 3843 si_gpu_soft_reset(rdev, reset_mask);
3737 3844
3738 reset_mask = si_gpu_check_soft_reset(rdev); 3845 reset_mask = si_gpu_check_soft_reset(rdev);
3739 3846
3847 /* try pci config reset */
3848 if (reset_mask && radeon_hard_reset)
3849 si_gpu_pci_config_reset(rdev);
3850
3851 reset_mask = si_gpu_check_soft_reset(rdev);
3852
3740 if (!reset_mask) 3853 if (!reset_mask)
3741 r600_set_bios_scratch_engine_hung(rdev, false); 3854 r600_set_bios_scratch_engine_hung(rdev, false);
3742 3855
@@ -5212,8 +5325,8 @@ static void si_enable_hdp_ls(struct radeon_device *rdev,
5212 WREG32(HDP_MEM_POWER_LS, data); 5325 WREG32(HDP_MEM_POWER_LS, data);
5213} 5326}
5214 5327
5215void si_update_cg(struct radeon_device *rdev, 5328static void si_update_cg(struct radeon_device *rdev,
5216 u32 block, bool enable) 5329 u32 block, bool enable)
5217{ 5330{
5218 if (block & RADEON_CG_BLOCK_GFX) { 5331 if (block & RADEON_CG_BLOCK_GFX) {
5219 si_enable_gui_idle_interrupt(rdev, false); 5332 si_enable_gui_idle_interrupt(rdev, false);
@@ -5379,6 +5492,9 @@ static void si_init_pg(struct radeon_device *rdev)
5379 si_init_ao_cu_mask(rdev); 5492 si_init_ao_cu_mask(rdev);
5380 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) { 5493 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5381 si_init_gfx_cgpg(rdev); 5494 si_init_gfx_cgpg(rdev);
5495 } else {
5496 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5497 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5382 } 5498 }
5383 si_enable_dma_pg(rdev, true); 5499 si_enable_dma_pg(rdev, true);
5384 si_enable_gfx_cgpg(rdev, true); 5500 si_enable_gfx_cgpg(rdev, true);
@@ -5566,7 +5682,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
5566 } 5682 }
5567 5683
5568 if (!ASIC_IS_NODCE(rdev)) { 5684 if (!ASIC_IS_NODCE(rdev)) {
5569 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 5685 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5570 5686
5571 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 5687 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5572 WREG32(DC_HPD1_INT_CONTROL, tmp); 5688 WREG32(DC_HPD1_INT_CONTROL, tmp);
@@ -6324,21 +6440,14 @@ static int si_startup(struct radeon_device *rdev)
6324 6440
6325 si_mc_program(rdev); 6441 si_mc_program(rdev);
6326 6442
6327 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 6443 if (!rdev->pm.dpm_enabled) {
6328 !rdev->rlc_fw || !rdev->mc_fw) { 6444 r = si_mc_load_microcode(rdev);
6329 r = si_init_microcode(rdev);
6330 if (r) { 6445 if (r) {
6331 DRM_ERROR("Failed to load firmware!\n"); 6446 DRM_ERROR("Failed to load MC firmware!\n");
6332 return r; 6447 return r;
6333 } 6448 }
6334 } 6449 }
6335 6450
6336 r = si_mc_load_microcode(rdev);
6337 if (r) {
6338 DRM_ERROR("Failed to load MC firmware!\n");
6339 return r;
6340 }
6341
6342 r = si_pcie_gart_enable(rdev); 6451 r = si_pcie_gart_enable(rdev);
6343 if (r) 6452 if (r)
6344 return r; 6453 return r;
@@ -6421,37 +6530,30 @@ static int si_startup(struct radeon_device *rdev)
6421 6530
6422 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 6531 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6423 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 6532 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
6424 CP_RB0_RPTR, CP_RB0_WPTR,
6425 RADEON_CP_PACKET2); 6533 RADEON_CP_PACKET2);
6426 if (r) 6534 if (r)
6427 return r; 6535 return r;
6428 6536
6429 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 6537 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6430 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, 6538 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
6431 CP_RB1_RPTR, CP_RB1_WPTR,
6432 RADEON_CP_PACKET2); 6539 RADEON_CP_PACKET2);
6433 if (r) 6540 if (r)
6434 return r; 6541 return r;
6435 6542
6436 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 6543 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6437 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, 6544 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
6438 CP_RB2_RPTR, CP_RB2_WPTR,
6439 RADEON_CP_PACKET2); 6545 RADEON_CP_PACKET2);
6440 if (r) 6546 if (r)
6441 return r; 6547 return r;
6442 6548
6443 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 6549 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6444 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 6550 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
6445 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
6446 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
6447 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 6551 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6448 if (r) 6552 if (r)
6449 return r; 6553 return r;
6450 6554
6451 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 6555 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6452 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 6556 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
6453 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
6454 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
6455 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 6557 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6456 if (r) 6558 if (r)
6457 return r; 6559 return r;
@@ -6471,7 +6573,6 @@ static int si_startup(struct radeon_device *rdev)
6471 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 6573 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6472 if (ring->ring_size) { 6574 if (ring->ring_size) {
6473 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 6575 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
6474 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
6475 RADEON_CP_PACKET2); 6576 RADEON_CP_PACKET2);
6476 if (!r) 6577 if (!r)
6477 r = uvd_v1_0_init(rdev); 6578 r = uvd_v1_0_init(rdev);
@@ -6513,6 +6614,8 @@ int si_resume(struct radeon_device *rdev)
6513 /* init golden registers */ 6614 /* init golden registers */
6514 si_init_golden_registers(rdev); 6615 si_init_golden_registers(rdev);
6515 6616
6617 radeon_pm_resume(rdev);
6618
6516 rdev->accel_working = true; 6619 rdev->accel_working = true;
6517 r = si_startup(rdev); 6620 r = si_startup(rdev);
6518 if (r) { 6621 if (r) {
@@ -6527,6 +6630,7 @@ int si_resume(struct radeon_device *rdev)
6527 6630
6528int si_suspend(struct radeon_device *rdev) 6631int si_suspend(struct radeon_device *rdev)
6529{ 6632{
6633 radeon_pm_suspend(rdev);
6530 dce6_audio_fini(rdev); 6634 dce6_audio_fini(rdev);
6531 radeon_vm_manager_fini(rdev); 6635 radeon_vm_manager_fini(rdev);
6532 si_cp_enable(rdev, false); 6636 si_cp_enable(rdev, false);
@@ -6600,6 +6704,18 @@ int si_init(struct radeon_device *rdev)
6600 if (r) 6704 if (r)
6601 return r; 6705 return r;
6602 6706
6707 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
6708 !rdev->rlc_fw || !rdev->mc_fw) {
6709 r = si_init_microcode(rdev);
6710 if (r) {
6711 DRM_ERROR("Failed to load firmware!\n");
6712 return r;
6713 }
6714 }
6715
6716 /* Initialize power management */
6717 radeon_pm_init(rdev);
6718
6603 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 6719 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6604 ring->ring_obj = NULL; 6720 ring->ring_obj = NULL;
6605 r600_ring_init(rdev, ring, 1024 * 1024); 6721 r600_ring_init(rdev, ring, 1024 * 1024);
@@ -6666,6 +6782,7 @@ int si_init(struct radeon_device *rdev)
6666 6782
6667void si_fini(struct radeon_device *rdev) 6783void si_fini(struct radeon_device *rdev)
6668{ 6784{
6785 radeon_pm_fini(rdev);
6669 si_cp_fini(rdev); 6786 si_cp_fini(rdev);
6670 cayman_dma_fini(rdev); 6787 cayman_dma_fini(rdev);
6671 si_fini_pg(rdev); 6788 si_fini_pg(rdev);
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 0b00c790fb77..0471501338fb 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -1738,6 +1738,8 @@ struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1738struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1739struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740 1740
1741extern int si_mc_load_microcode(struct radeon_device *rdev);
1742
1741static int si_populate_voltage_value(struct radeon_device *rdev, 1743static int si_populate_voltage_value(struct radeon_device *rdev,
1742 const struct atom_voltage_table *table, 1744 const struct atom_voltage_table *table,
1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
@@ -1753,9 +1755,6 @@ static int si_calculate_sclk_params(struct radeon_device *rdev,
1753 u32 engine_clock, 1755 u32 engine_clock,
1754 SISLANDS_SMC_SCLK_VALUE *sclk); 1756 SISLANDS_SMC_SCLK_VALUE *sclk);
1755 1757
1756extern void si_update_cg(struct radeon_device *rdev,
1757 u32 block, bool enable);
1758
1759static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1758static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1760{ 1759{
1761 struct si_power_info *pi = rdev->pm.dpm.priv; 1760 struct si_power_info *pi = rdev->pm.dpm.priv;
@@ -2396,7 +2395,7 @@ static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2396 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2395 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2397 enable_sq_ramping = false; 2396 enable_sq_ramping = false;
2398 2397
2399 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2398 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2400 enable_sq_ramping = false; 2399 enable_sq_ramping = false;
2401 2400
2402 for (i = 0; i < state->performance_level_count; i++) { 2401 for (i = 0; i < state->performance_level_count; i++) {
@@ -3591,10 +3590,9 @@ static void si_program_display_gap(struct radeon_device *rdev)
3591 3590
3592 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3591 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3593 * This can be a problem on PowerXpress systems or if you want to use the card 3592 * This can be a problem on PowerXpress systems or if you want to use the card
3594 * for offscreen rendering or compute if there are no crtcs enabled. Set it to 3593 * for offscreen rendering or compute if there are no crtcs enabled.
3595 * true for now so that performance scales even if the displays are off.
3596 */ 3594 */
3597 si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/); 3595 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3598} 3596}
3599 3597
3600static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3598static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
@@ -5414,7 +5412,7 @@ static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5414 5412
5415 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5413 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5416 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5414 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5417 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5415 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5418 break; 5416 break;
5419 mc_reg_table->address[i].s0 = 5417 mc_reg_table->address[i].s0 =
5420 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5418 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
@@ -5754,6 +5752,11 @@ static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5754 5752
5755void si_dpm_setup_asic(struct radeon_device *rdev) 5753void si_dpm_setup_asic(struct radeon_device *rdev)
5756{ 5754{
5755 int r;
5756
5757 r = si_mc_load_microcode(rdev);
5758 if (r)
5759 DRM_ERROR("Failed to load MC firmware!\n");
5757 rv770_get_memory_type(rdev); 5760 rv770_get_memory_type(rdev);
5758 si_read_clock_registers(rdev); 5761 si_read_clock_registers(rdev);
5759 si_enable_acpi_power_management(rdev); 5762 si_enable_acpi_power_management(rdev);
@@ -5791,13 +5794,6 @@ int si_dpm_enable(struct radeon_device *rdev)
5791 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5794 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5792 int ret; 5795 int ret;
5793 5796
5794 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5795 RADEON_CG_BLOCK_MC |
5796 RADEON_CG_BLOCK_SDMA |
5797 RADEON_CG_BLOCK_BIF |
5798 RADEON_CG_BLOCK_UVD |
5799 RADEON_CG_BLOCK_HDP), false);
5800
5801 if (si_is_smc_running(rdev)) 5797 if (si_is_smc_running(rdev))
5802 return -EINVAL; 5798 return -EINVAL;
5803 if (pi->voltage_control) 5799 if (pi->voltage_control)
@@ -5900,6 +5896,17 @@ int si_dpm_enable(struct radeon_device *rdev)
5900 si_enable_sclk_control(rdev, true); 5896 si_enable_sclk_control(rdev, true);
5901 si_start_dpm(rdev); 5897 si_start_dpm(rdev);
5902 5898
5899 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5900
5901 ni_update_current_ps(rdev, boot_ps);
5902
5903 return 0;
5904}
5905
5906int si_dpm_late_enable(struct radeon_device *rdev)
5907{
5908 int ret;
5909
5903 if (rdev->irq.installed && 5910 if (rdev->irq.installed &&
5904 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5911 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5905 PPSMC_Result result; 5912 PPSMC_Result result;
@@ -5915,17 +5922,6 @@ int si_dpm_enable(struct radeon_device *rdev)
5915 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5922 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5916 } 5923 }
5917 5924
5918 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5919
5920 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5921 RADEON_CG_BLOCK_MC |
5922 RADEON_CG_BLOCK_SDMA |
5923 RADEON_CG_BLOCK_BIF |
5924 RADEON_CG_BLOCK_UVD |
5925 RADEON_CG_BLOCK_HDP), true);
5926
5927 ni_update_current_ps(rdev, boot_ps);
5928
5929 return 0; 5925 return 0;
5930} 5926}
5931 5927
@@ -5934,13 +5930,6 @@ void si_dpm_disable(struct radeon_device *rdev)
5934 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5930 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5935 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5931 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5936 5932
5937 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5938 RADEON_CG_BLOCK_MC |
5939 RADEON_CG_BLOCK_SDMA |
5940 RADEON_CG_BLOCK_BIF |
5941 RADEON_CG_BLOCK_UVD |
5942 RADEON_CG_BLOCK_HDP), false);
5943
5944 if (!si_is_smc_running(rdev)) 5933 if (!si_is_smc_running(rdev))
5945 return; 5934 return;
5946 si_disable_ulv(rdev); 5935 si_disable_ulv(rdev);
@@ -6005,13 +5994,6 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
6005 struct radeon_ps *old_ps = &eg_pi->current_rps; 5994 struct radeon_ps *old_ps = &eg_pi->current_rps;
6006 int ret; 5995 int ret;
6007 5996
6008 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
6009 RADEON_CG_BLOCK_MC |
6010 RADEON_CG_BLOCK_SDMA |
6011 RADEON_CG_BLOCK_BIF |
6012 RADEON_CG_BLOCK_UVD |
6013 RADEON_CG_BLOCK_HDP), false);
6014
6015 ret = si_disable_ulv(rdev); 5997 ret = si_disable_ulv(rdev);
6016 if (ret) { 5998 if (ret) {
6017 DRM_ERROR("si_disable_ulv failed\n"); 5999 DRM_ERROR("si_disable_ulv failed\n");
@@ -6104,13 +6086,6 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
6104 return ret; 6086 return ret;
6105 } 6087 }
6106 6088
6107 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
6108 RADEON_CG_BLOCK_MC |
6109 RADEON_CG_BLOCK_SDMA |
6110 RADEON_CG_BLOCK_BIF |
6111 RADEON_CG_BLOCK_UVD |
6112 RADEON_CG_BLOCK_HDP), true);
6113
6114 return 0; 6089 return 0;
6115} 6090}
6116 6091
diff --git a/drivers/gpu/drm/radeon/si_smc.c b/drivers/gpu/drm/radeon/si_smc.c
index d422a1cbf727..e80efcf0c230 100644
--- a/drivers/gpu/drm/radeon/si_smc.c
+++ b/drivers/gpu/drm/radeon/si_smc.c
@@ -28,6 +28,7 @@
28#include "sid.h" 28#include "sid.h"
29#include "ppsmc.h" 29#include "ppsmc.h"
30#include "radeon_ucode.h" 30#include "radeon_ucode.h"
31#include "sislands_smc.h"
31 32
32static int si_set_smc_sram_address(struct radeon_device *rdev, 33static int si_set_smc_sram_address(struct radeon_device *rdev,
33 u32 smc_address, u32 limit) 34 u32 smc_address, u32 limit)
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index b322acc48097..9239a6d29128 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -94,6 +94,8 @@
94#define CG_SPLL_FUNC_CNTL_2 0x604 94#define CG_SPLL_FUNC_CNTL_2 0x604
95#define SCLK_MUX_SEL(x) ((x) << 0) 95#define SCLK_MUX_SEL(x) ((x) << 0)
96#define SCLK_MUX_SEL_MASK (0x1ff << 0) 96#define SCLK_MUX_SEL_MASK (0x1ff << 0)
97#define SPLL_CTLREQ_CHG (1 << 23)
98#define SCLK_MUX_UPDATE (1 << 26)
97#define CG_SPLL_FUNC_CNTL_3 0x608 99#define CG_SPLL_FUNC_CNTL_3 0x608
98#define SPLL_FB_DIV(x) ((x) << 0) 100#define SPLL_FB_DIV(x) ((x) << 0)
99#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 101#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
@@ -101,7 +103,10 @@
101#define SPLL_DITHEN (1 << 28) 103#define SPLL_DITHEN (1 << 28)
102#define CG_SPLL_FUNC_CNTL_4 0x60c 104#define CG_SPLL_FUNC_CNTL_4 0x60c
103 105
106#define SPLL_STATUS 0x614
107#define SPLL_CHG_STATUS (1 << 1)
104#define SPLL_CNTL_MODE 0x618 108#define SPLL_CNTL_MODE 0x618
109#define SPLL_SW_DIR_CONTROL (1 << 0)
105# define SPLL_REFCLK_SEL(x) ((x) << 8) 110# define SPLL_REFCLK_SEL(x) ((x) << 8)
106# define SPLL_REFCLK_SEL_MASK 0xFF00 111# define SPLL_REFCLK_SEL_MASK 0xFF00
107 112
@@ -559,6 +564,8 @@
559# define MRDCK0_BYPASS (1 << 24) 564# define MRDCK0_BYPASS (1 << 24)
560# define MRDCK1_BYPASS (1 << 25) 565# define MRDCK1_BYPASS (1 << 25)
561 566
567#define MPLL_CNTL_MODE 0x2bb0
568# define MPLL_MCLK_SEL (1 << 11)
562#define MPLL_FUNC_CNTL 0x2bb4 569#define MPLL_FUNC_CNTL 0x2bb4
563#define BWCTRL(x) ((x) << 20) 570#define BWCTRL(x) ((x) << 20)
564#define BWCTRL_MASK (0xff << 20) 571#define BWCTRL_MASK (0xff << 20)
@@ -815,7 +822,7 @@
815# define GRPH_PFLIP_INT_MASK (1 << 0) 822# define GRPH_PFLIP_INT_MASK (1 << 0)
816# define GRPH_PFLIP_INT_TYPE (1 << 8) 823# define GRPH_PFLIP_INT_TYPE (1 << 8)
817 824
818#define DACA_AUTODETECT_INT_CONTROL 0x66c8 825#define DAC_AUTODETECT_INT_CONTROL 0x67c8
819 826
820#define DC_HPD1_INT_STATUS 0x601c 827#define DC_HPD1_INT_STATUS 0x601c
821#define DC_HPD2_INT_STATUS 0x6028 828#define DC_HPD2_INT_STATUS 0x6028
diff --git a/drivers/gpu/drm/radeon/sislands_smc.h b/drivers/gpu/drm/radeon/sislands_smc.h
index 5578e9837026..10e945a49479 100644
--- a/drivers/gpu/drm/radeon/sislands_smc.h
+++ b/drivers/gpu/drm/radeon/sislands_smc.h
@@ -374,8 +374,6 @@ typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
374 374
375#pragma pack(pop) 375#pragma pack(pop)
376 376
377int si_set_smc_sram_address(struct radeon_device *rdev,
378 u32 smc_address, u32 limit);
379int si_copy_bytes_to_smc(struct radeon_device *rdev, 377int si_copy_bytes_to_smc(struct radeon_device *rdev,
380 u32 smc_start_address, 378 u32 smc_start_address,
381 const u8 *src, u32 byte_count, u32 limit); 379 const u8 *src, u32 byte_count, u32 limit);
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index 96ea6db8bf57..f121efe12dc5 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -71,7 +71,7 @@ static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
71 SUMO_DTC_DFLT_14, 71 SUMO_DTC_DFLT_14,
72}; 72};
73 73
74struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) 74static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
75{ 75{
76 struct sumo_ps *ps = rps->ps_priv; 76 struct sumo_ps *ps = rps->ps_priv;
77 77
@@ -1202,14 +1202,10 @@ static void sumo_update_requested_ps(struct radeon_device *rdev,
1202int sumo_dpm_enable(struct radeon_device *rdev) 1202int sumo_dpm_enable(struct radeon_device *rdev)
1203{ 1203{
1204 struct sumo_power_info *pi = sumo_get_pi(rdev); 1204 struct sumo_power_info *pi = sumo_get_pi(rdev);
1205 int ret;
1206 1205
1207 if (sumo_dpm_enabled(rdev)) 1206 if (sumo_dpm_enabled(rdev))
1208 return -EINVAL; 1207 return -EINVAL;
1209 1208
1210 ret = sumo_enable_clock_power_gating(rdev);
1211 if (ret)
1212 return ret;
1213 sumo_program_bootup_state(rdev); 1209 sumo_program_bootup_state(rdev);
1214 sumo_init_bsp(rdev); 1210 sumo_init_bsp(rdev);
1215 sumo_reset_am(rdev); 1211 sumo_reset_am(rdev);
@@ -1233,6 +1229,19 @@ int sumo_dpm_enable(struct radeon_device *rdev)
1233 if (pi->enable_boost) 1229 if (pi->enable_boost)
1234 sumo_enable_boost_timer(rdev); 1230 sumo_enable_boost_timer(rdev);
1235 1231
1232 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1233
1234 return 0;
1235}
1236
1237int sumo_dpm_late_enable(struct radeon_device *rdev)
1238{
1239 int ret;
1240
1241 ret = sumo_enable_clock_power_gating(rdev);
1242 if (ret)
1243 return ret;
1244
1236 if (rdev->irq.installed && 1245 if (rdev->irq.installed &&
1237 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1246 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1238 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1247 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1242,8 +1251,6 @@ int sumo_dpm_enable(struct radeon_device *rdev)
1242 radeon_irq_set(rdev); 1251 radeon_irq_set(rdev);
1243 } 1252 }
1244 1253
1245 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1246
1247 return 0; 1254 return 0;
1248} 1255}
1249 1256
diff --git a/drivers/gpu/drm/radeon/sumo_smc.c b/drivers/gpu/drm/radeon/sumo_smc.c
index 18abba5b5810..fb081d2ae374 100644
--- a/drivers/gpu/drm/radeon/sumo_smc.c
+++ b/drivers/gpu/drm/radeon/sumo_smc.c
@@ -31,7 +31,6 @@
31#define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27 31#define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27
32#define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20 20 32#define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20 20
33 33
34struct sumo_ps *sumo_get_ps(struct radeon_ps *rps);
35struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev); 34struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
36 35
37static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id) 36static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c
index d700698a1f22..2d447192d6f7 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -342,14 +342,14 @@ static void trinity_apply_state_adjust_rules(struct radeon_device *rdev,
342 struct radeon_ps *new_rps, 342 struct radeon_ps *new_rps,
343 struct radeon_ps *old_rps); 343 struct radeon_ps *old_rps);
344 344
345struct trinity_ps *trinity_get_ps(struct radeon_ps *rps) 345static struct trinity_ps *trinity_get_ps(struct radeon_ps *rps)
346{ 346{
347 struct trinity_ps *ps = rps->ps_priv; 347 struct trinity_ps *ps = rps->ps_priv;
348 348
349 return ps; 349 return ps;
350} 350}
351 351
352struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev) 352static struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev)
353{ 353{
354 struct trinity_power_info *pi = rdev->pm.dpm.priv; 354 struct trinity_power_info *pi = rdev->pm.dpm.priv;
355 355
@@ -1082,7 +1082,6 @@ void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1082int trinity_dpm_enable(struct radeon_device *rdev) 1082int trinity_dpm_enable(struct radeon_device *rdev)
1083{ 1083{
1084 struct trinity_power_info *pi = trinity_get_pi(rdev); 1084 struct trinity_power_info *pi = trinity_get_pi(rdev);
1085 int ret;
1086 1085
1087 trinity_acquire_mutex(rdev); 1086 trinity_acquire_mutex(rdev);
1088 1087
@@ -1091,7 +1090,6 @@ int trinity_dpm_enable(struct radeon_device *rdev)
1091 return -EINVAL; 1090 return -EINVAL;
1092 } 1091 }
1093 1092
1094 trinity_enable_clock_power_gating(rdev);
1095 trinity_program_bootup_state(rdev); 1093 trinity_program_bootup_state(rdev);
1096 sumo_program_vc(rdev, 0x00C00033); 1094 sumo_program_vc(rdev, 0x00C00033);
1097 trinity_start_am(rdev); 1095 trinity_start_am(rdev);
@@ -1105,6 +1103,18 @@ int trinity_dpm_enable(struct radeon_device *rdev)
1105 trinity_dpm_bapm_enable(rdev, false); 1103 trinity_dpm_bapm_enable(rdev, false);
1106 trinity_release_mutex(rdev); 1104 trinity_release_mutex(rdev);
1107 1105
1106 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1107
1108 return 0;
1109}
1110
1111int trinity_dpm_late_enable(struct radeon_device *rdev)
1112{
1113 int ret;
1114
1115 trinity_acquire_mutex(rdev);
1116 trinity_enable_clock_power_gating(rdev);
1117
1108 if (rdev->irq.installed && 1118 if (rdev->irq.installed &&
1109 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 1119 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1110 ret = trinity_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 1120 ret = trinity_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
@@ -1115,8 +1125,7 @@ int trinity_dpm_enable(struct radeon_device *rdev)
1115 rdev->irq.dpm_thermal = true; 1125 rdev->irq.dpm_thermal = true;
1116 radeon_irq_set(rdev); 1126 radeon_irq_set(rdev);
1117 } 1127 }
1118 1128 trinity_release_mutex(rdev);
1119 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1120 1129
1121 return 0; 1130 return 0;
1122} 1131}
diff --git a/drivers/gpu/drm/radeon/trinity_smc.c b/drivers/gpu/drm/radeon/trinity_smc.c
index 9672bcbc7312..99dd0455334d 100644
--- a/drivers/gpu/drm/radeon/trinity_smc.c
+++ b/drivers/gpu/drm/radeon/trinity_smc.c
@@ -27,9 +27,6 @@
27#include "trinity_dpm.h" 27#include "trinity_dpm.h"
28#include "ppsmc.h" 28#include "ppsmc.h"
29 29
30struct trinity_ps *trinity_get_ps(struct radeon_ps *rps);
31struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev);
32
33static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id) 30static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id)
34{ 31{
35 int i; 32 int i;
diff --git a/drivers/gpu/drm/radeon/uvd_v2_2.c b/drivers/gpu/drm/radeon/uvd_v2_2.c
index b19ef4951085..824550db3fed 100644
--- a/drivers/gpu/drm/radeon/uvd_v2_2.c
+++ b/drivers/gpu/drm/radeon/uvd_v2_2.c
@@ -153,6 +153,7 @@ int uvd_v2_2_resume(struct radeon_device *rdev)
153 chip_id = 0x01000015; 153 chip_id = 0x01000015;
154 break; 154 break;
155 case CHIP_PITCAIRN: 155 case CHIP_PITCAIRN:
156 case CHIP_OLAND:
156 chip_id = 0x01000016; 157 chip_id = 0x01000016;
157 break; 158 break;
158 case CHIP_ARUBA: 159 case CHIP_ARUBA:
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 12:38:58 -0500