diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index b322acc48097..9239a6d29128 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
| @@ -94,6 +94,8 @@ | |||
| 94 | #define CG_SPLL_FUNC_CNTL_2 0x604 | 94 | #define CG_SPLL_FUNC_CNTL_2 0x604 |
| 95 | #define SCLK_MUX_SEL(x) ((x) << 0) | 95 | #define SCLK_MUX_SEL(x) ((x) << 0) |
| 96 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | 96 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) |
| 97 | #define SPLL_CTLREQ_CHG (1 << 23) | ||
| 98 | #define SCLK_MUX_UPDATE (1 << 26) | ||
| 97 | #define CG_SPLL_FUNC_CNTL_3 0x608 | 99 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
| 98 | #define SPLL_FB_DIV(x) ((x) << 0) | 100 | #define SPLL_FB_DIV(x) ((x) << 0) |
| 99 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | 101 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
| @@ -101,7 +103,10 @@ | |||
| 101 | #define SPLL_DITHEN (1 << 28) | 103 | #define SPLL_DITHEN (1 << 28) |
| 102 | #define CG_SPLL_FUNC_CNTL_4 0x60c | 104 | #define CG_SPLL_FUNC_CNTL_4 0x60c |
| 103 | 105 | ||
| 106 | #define SPLL_STATUS 0x614 | ||
| 107 | #define SPLL_CHG_STATUS (1 << 1) | ||
| 104 | #define SPLL_CNTL_MODE 0x618 | 108 | #define SPLL_CNTL_MODE 0x618 |
| 109 | #define SPLL_SW_DIR_CONTROL (1 << 0) | ||
| 105 | # define SPLL_REFCLK_SEL(x) ((x) << 8) | 110 | # define SPLL_REFCLK_SEL(x) ((x) << 8) |
| 106 | # define SPLL_REFCLK_SEL_MASK 0xFF00 | 111 | # define SPLL_REFCLK_SEL_MASK 0xFF00 |
| 107 | 112 | ||
| @@ -559,6 +564,8 @@ | |||
| 559 | # define MRDCK0_BYPASS (1 << 24) | 564 | # define MRDCK0_BYPASS (1 << 24) |
| 560 | # define MRDCK1_BYPASS (1 << 25) | 565 | # define MRDCK1_BYPASS (1 << 25) |
| 561 | 566 | ||
| 567 | #define MPLL_CNTL_MODE 0x2bb0 | ||
| 568 | # define MPLL_MCLK_SEL (1 << 11) | ||
| 562 | #define MPLL_FUNC_CNTL 0x2bb4 | 569 | #define MPLL_FUNC_CNTL 0x2bb4 |
| 563 | #define BWCTRL(x) ((x) << 20) | 570 | #define BWCTRL(x) ((x) << 20) |
| 564 | #define BWCTRL_MASK (0xff << 20) | 571 | #define BWCTRL_MASK (0xff << 20) |
| @@ -815,7 +822,7 @@ | |||
| 815 | # define GRPH_PFLIP_INT_MASK (1 << 0) | 822 | # define GRPH_PFLIP_INT_MASK (1 << 0) |
| 816 | # define GRPH_PFLIP_INT_TYPE (1 << 8) | 823 | # define GRPH_PFLIP_INT_TYPE (1 << 8) |
| 817 | 824 | ||
| 818 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 | 825 | #define DAC_AUTODETECT_INT_CONTROL 0x67c8 |
| 819 | 826 | ||
| 820 | #define DC_HPD1_INT_STATUS 0x601c | 827 | #define DC_HPD1_INT_STATUS 0x601c |
| 821 | #define DC_HPD2_INT_STATUS 0x6028 | 828 | #define DC_HPD2_INT_STATUS 0x6028 |