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-rw-r--r--drivers/char/agp/Kconfig6
-rw-r--r--drivers/char/agp/Makefile1
-rw-r--r--drivers/char/agp/agp.h8
-rw-r--r--drivers/char/agp/amd-k7-agp.c27
-rw-r--r--drivers/char/agp/amd64-agp.c53
-rw-r--r--drivers/char/agp/backend.c22
-rw-r--r--drivers/char/agp/compat_ioctl.c1
-rw-r--r--drivers/char/agp/compat_ioctl.h1
-rw-r--r--drivers/char/agp/frontend.c9
-rw-r--r--drivers/char/agp/generic.c58
-rw-r--r--drivers/char/agp/i460-agp.c2
-rw-r--r--drivers/char/agp/intel-agp.c236
-rw-r--r--drivers/char/agp/intel-agp.h71
-rw-r--r--drivers/char/agp/intel-gtt.c2085
-rw-r--r--drivers/char/agp/parisc-agp.c5
-rw-r--r--drivers/char/agp/sworks-agp.c2
-rw-r--r--drivers/char/agp/uninorth-agp.c2
-rw-r--r--drivers/char/agp/via-agp.c2
18 files changed, 1120 insertions, 1471 deletions
diff --git a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig
index 4b66c69eaf57..d8b1b576556c 100644
--- a/drivers/char/agp/Kconfig
+++ b/drivers/char/agp/Kconfig
@@ -34,7 +34,7 @@ config AGP_ALI
34 X on the following ALi chipsets. The supported chipsets 34 X on the following ALi chipsets. The supported chipsets
35 include M1541, M1621, M1631, M1632, M1641,M1647,and M1651. 35 include M1541, M1621, M1631, M1632, M1641,M1647,and M1651.
36 For the ALi-chipset question, ALi suggests you refer to 36 For the ALi-chipset question, ALi suggests you refer to
37 <http://www.ali.com.tw/eng/support/index.shtml>. 37 <http://www.ali.com.tw/>.
38 38
39 The M1541 chipset can do AGP 1x and 2x, but note that there is an 39 The M1541 chipset can do AGP 1x and 2x, but note that there is an
40 acknowledged incompatibility with Matrox G200 cards. Due to 40 acknowledged incompatibility with Matrox G200 cards. Due to
@@ -50,14 +50,14 @@ config AGP_ATI
50 50
51config AGP_AMD 51config AGP_AMD
52 tristate "AMD Irongate, 761, and 762 chipset support" 52 tristate "AMD Irongate, 761, and 762 chipset support"
53 depends on AGP && (X86_32 || ALPHA) 53 depends on AGP && X86_32
54 help 54 help
55 This option gives you AGP support for the GLX component of 55 This option gives you AGP support for the GLX component of
56 X on AMD Irongate, 761, and 762 chipsets. 56 X on AMD Irongate, 761, and 762 chipsets.
57 57
58config AGP_AMD64 58config AGP_AMD64
59 tristate "AMD Opteron/Athlon64 on-CPU GART support" 59 tristate "AMD Opteron/Athlon64 on-CPU GART support"
60 depends on AGP && X86 && K8_NB 60 depends on AGP && X86 && AMD_NB
61 help 61 help
62 This option gives you AGP support for the GLX component of 62 This option gives you AGP support for the GLX component of
63 X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs. 63 X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
diff --git a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile
index 627f542827c7..8eb56e273e75 100644
--- a/drivers/char/agp/Makefile
+++ b/drivers/char/agp/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
13obj-$(CONFIG_AGP_PARISC) += parisc-agp.o 13obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
14obj-$(CONFIG_AGP_I460) += i460-agp.o 14obj-$(CONFIG_AGP_I460) += i460-agp.o
15obj-$(CONFIG_AGP_INTEL) += intel-agp.o 15obj-$(CONFIG_AGP_INTEL) += intel-agp.o
16obj-$(CONFIG_AGP_INTEL) += intel-gtt.o
16obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o 17obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
17obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o 18obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o
18obj-$(CONFIG_AGP_SIS) += sis-agp.o 19obj-$(CONFIG_AGP_SIS) += sis-agp.o
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 120490949997..923f99df4f1c 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -120,12 +120,6 @@ struct agp_bridge_driver {
120 void (*agp_destroy_page)(struct page *, int flags); 120 void (*agp_destroy_page)(struct page *, int flags);
121 void (*agp_destroy_pages)(struct agp_memory *); 121 void (*agp_destroy_pages)(struct agp_memory *);
122 int (*agp_type_to_mask_type) (struct agp_bridge_data *, int); 122 int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
123 void (*chipset_flush)(struct agp_bridge_data *);
124
125 int (*agp_map_page)(struct page *page, dma_addr_t *ret);
126 void (*agp_unmap_page)(struct page *page, dma_addr_t dma);
127 int (*agp_map_memory)(struct agp_memory *mem);
128 void (*agp_unmap_memory)(struct agp_memory *mem);
129}; 123};
130 124
131struct agp_bridge_data { 125struct agp_bridge_data {
@@ -243,7 +237,7 @@ extern int agp_try_unsupported_boot;
243 237
244long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 238long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
245 239
246/* Chipset independant registers (from AGP Spec) */ 240/* Chipset independent registers (from AGP Spec) */
247#define AGP_APBASE 0x10 241#define AGP_APBASE 0x10
248 242
249#define AGPSTAT 0x4 243#define AGPSTAT 0x4
diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c
index b6b1568314c8..f7e88787af97 100644
--- a/drivers/char/agp/amd-k7-agp.c
+++ b/drivers/char/agp/amd-k7-agp.c
@@ -41,22 +41,8 @@ static int amd_create_page_map(struct amd_page_map *page_map)
41 if (page_map->real == NULL) 41 if (page_map->real == NULL)
42 return -ENOMEM; 42 return -ENOMEM;
43 43
44#ifndef CONFIG_X86
45 SetPageReserved(virt_to_page(page_map->real));
46 global_cache_flush();
47 page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
48 PAGE_SIZE);
49 if (page_map->remapped == NULL) {
50 ClearPageReserved(virt_to_page(page_map->real));
51 free_page((unsigned long) page_map->real);
52 page_map->real = NULL;
53 return -ENOMEM;
54 }
55 global_cache_flush();
56#else
57 set_memory_uc((unsigned long)page_map->real, 1); 44 set_memory_uc((unsigned long)page_map->real, 1);
58 page_map->remapped = page_map->real; 45 page_map->remapped = page_map->real;
59#endif
60 46
61 for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { 47 for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
62 writel(agp_bridge->scratch_page, page_map->remapped+i); 48 writel(agp_bridge->scratch_page, page_map->remapped+i);
@@ -68,12 +54,7 @@ static int amd_create_page_map(struct amd_page_map *page_map)
68 54
69static void amd_free_page_map(struct amd_page_map *page_map) 55static void amd_free_page_map(struct amd_page_map *page_map)
70{ 56{
71#ifndef CONFIG_X86
72 iounmap(page_map->remapped);
73 ClearPageReserved(virt_to_page(page_map->real));
74#else
75 set_memory_wb((unsigned long)page_map->real, 1); 57 set_memory_wb((unsigned long)page_map->real, 1);
76#endif
77 free_page((unsigned long) page_map->real); 58 free_page((unsigned long) page_map->real);
78} 59}
79 60
@@ -291,7 +272,7 @@ static void amd_irongate_cleanup(void)
291 * This routine could be implemented by taking the addresses 272 * This routine could be implemented by taking the addresses
292 * written to the GATT, and flushing them individually. However 273 * written to the GATT, and flushing them individually. However
293 * currently it just flushes the whole table. Which is probably 274 * currently it just flushes the whole table. Which is probably
294 * more efficent, since agp_memory blocks can be a large number of 275 * more efficient, since agp_memory blocks can be a large number of
295 * entries. 276 * entries.
296 */ 277 */
297 278
@@ -309,7 +290,8 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
309 290
310 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; 291 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
311 292
312 if (type != 0 || mem->type != 0) 293 if (type != mem->type ||
294 agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
313 return -EINVAL; 295 return -EINVAL;
314 296
315 if ((pg_start + mem->page_count) > num_entries) 297 if ((pg_start + mem->page_count) > num_entries)
@@ -348,7 +330,8 @@ static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
348 unsigned long __iomem *cur_gatt; 330 unsigned long __iomem *cur_gatt;
349 unsigned long addr; 331 unsigned long addr;
350 332
351 if (type != 0 || mem->type != 0) 333 if (type != mem->type ||
334 agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
352 return -EINVAL; 335 return -EINVAL;
353 336
354 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 337 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 70312da4c968..780498d76581 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -15,7 +15,7 @@
15#include <linux/mmzone.h> 15#include <linux/mmzone.h>
16#include <asm/page.h> /* PAGE_SIZE */ 16#include <asm/page.h> /* PAGE_SIZE */
17#include <asm/e820.h> 17#include <asm/e820.h>
18#include <asm/k8.h> 18#include <asm/amd_nb.h>
19#include <asm/gart.h> 19#include <asm/gart.h>
20#include "agp.h" 20#include "agp.h"
21 21
@@ -38,7 +38,7 @@ static int agp_bridges_found;
38 38
39static void amd64_tlbflush(struct agp_memory *temp) 39static void amd64_tlbflush(struct agp_memory *temp)
40{ 40{
41 k8_flush_garts(); 41 amd_flush_garts();
42} 42}
43 43
44static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 44static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
@@ -124,7 +124,7 @@ static int amd64_fetch_size(void)
124 u32 temp; 124 u32 temp;
125 struct aper_size_info_32 *values; 125 struct aper_size_info_32 *values;
126 126
127 dev = k8_northbridges[0]; 127 dev = node_to_amd_nb(0)->misc;
128 if (dev==NULL) 128 if (dev==NULL)
129 return 0; 129 return 0;
130 130
@@ -181,12 +181,15 @@ static int amd_8151_configure(void)
181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real); 181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
182 int i; 182 int i;
183 183
184 if (!amd_nb_has_feature(AMD_NB_GART))
185 return 0;
186
184 /* Configure AGP regs in each x86-64 host bridge. */ 187 /* Configure AGP regs in each x86-64 host bridge. */
185 for (i = 0; i < num_k8_northbridges; i++) { 188 for (i = 0; i < amd_nb_num(); i++) {
186 agp_bridge->gart_bus_addr = 189 agp_bridge->gart_bus_addr =
187 amd64_configure(k8_northbridges[i], gatt_bus); 190 amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
188 } 191 }
189 k8_flush_garts(); 192 amd_flush_garts();
190 return 0; 193 return 0;
191} 194}
192 195
@@ -195,11 +198,15 @@ static void amd64_cleanup(void)
195{ 198{
196 u32 tmp; 199 u32 tmp;
197 int i; 200 int i;
198 for (i = 0; i < num_k8_northbridges; i++) { 201
199 struct pci_dev *dev = k8_northbridges[i]; 202 if (!amd_nb_has_feature(AMD_NB_GART))
203 return;
204
205 for (i = 0; i < amd_nb_num(); i++) {
206 struct pci_dev *dev = node_to_amd_nb(i)->misc;
200 /* disable gart translation */ 207 /* disable gart translation */
201 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp); 208 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
202 tmp &= ~AMD64_GARTEN; 209 tmp &= ~GARTEN;
203 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp); 210 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
204 } 211 }
205} 212}
@@ -313,22 +320,25 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
313 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order)) 320 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
314 return -1; 321 return -1;
315 322
316 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1); 323 gart_set_size_and_enable(nb, order);
317 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25); 324 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
318 325
319 return 0; 326 return 0;
320} 327}
321 328
322static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) 329static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
323{ 330{
324 int i; 331 int i;
325 332
326 if (cache_k8_northbridges() < 0) 333 if (amd_cache_northbridges() < 0)
334 return -ENODEV;
335
336 if (!amd_nb_has_feature(AMD_NB_GART))
327 return -ENODEV; 337 return -ENODEV;
328 338
329 i = 0; 339 i = 0;
330 for (i = 0; i < num_k8_northbridges; i++) { 340 for (i = 0; i < amd_nb_num(); i++) {
331 struct pci_dev *dev = k8_northbridges[i]; 341 struct pci_dev *dev = node_to_amd_nb(i)->misc;
332 if (fix_northbridge(dev, pdev, cap_ptr) < 0) { 342 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
333 dev_err(&dev->dev, "no usable aperture found\n"); 343 dev_err(&dev->dev, "no usable aperture found\n");
334#ifdef __x86_64__ 344#ifdef __x86_64__
@@ -405,7 +415,8 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
405 } 415 }
406 416
407 /* shadow x86-64 registers into ULi registers */ 417 /* shadow x86-64 registers into ULi registers */
408 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); 418 pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
419 &httfea);
409 420
410 /* if x86-64 aperture base is beyond 4G, exit here */ 421 /* if x86-64 aperture base is beyond 4G, exit here */
411 if ((httfea & 0x7fff) >> (32 - 25)) { 422 if ((httfea & 0x7fff) >> (32 - 25)) {
@@ -472,7 +483,8 @@ static int nforce3_agp_init(struct pci_dev *pdev)
472 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); 483 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
473 484
474 /* shadow x86-64 registers into NVIDIA registers */ 485 /* shadow x86-64 registers into NVIDIA registers */
475 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); 486 pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
487 &apbase);
476 488
477 /* if x86-64 aperture base is beyond 4G, exit here */ 489 /* if x86-64 aperture base is beyond 4G, exit here */
478 if ( (apbase & 0x7fff) >> (32 - 25) ) { 490 if ( (apbase & 0x7fff) >> (32 - 25) ) {
@@ -761,18 +773,23 @@ int __init agp_amd64_init(void)
761#else 773#else
762 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); 774 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
763#endif 775#endif
776 pci_unregister_driver(&agp_amd64_pci_driver);
764 return -ENODEV; 777 return -ENODEV;
765 } 778 }
766 779
767 /* First check that we have at least one AMD64 NB */ 780 /* First check that we have at least one AMD64 NB */
768 if (!pci_dev_present(k8_nb_ids)) 781 if (!pci_dev_present(amd_nb_misc_ids)) {
782 pci_unregister_driver(&agp_amd64_pci_driver);
769 return -ENODEV; 783 return -ENODEV;
784 }
770 785
771 /* Look for any AGP bridge */ 786 /* Look for any AGP bridge */
772 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table; 787 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
773 err = driver_attach(&agp_amd64_pci_driver.driver); 788 err = driver_attach(&agp_amd64_pci_driver.driver);
774 if (err == 0 && agp_bridges_found == 0) 789 if (err == 0 && agp_bridges_found == 0) {
790 pci_unregister_driver(&agp_amd64_pci_driver);
775 err = -ENODEV; 791 err = -ENODEV;
792 }
776 } 793 }
777 return err; 794 return err;
778} 795}
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c
index ee4f855611b6..f27d0d0816d3 100644
--- a/drivers/char/agp/backend.c
+++ b/drivers/char/agp/backend.c
@@ -151,17 +151,7 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
151 } 151 }
152 152
153 bridge->scratch_page_page = page; 153 bridge->scratch_page_page = page;
154 if (bridge->driver->agp_map_page) { 154 bridge->scratch_page_dma = page_to_phys(page);
155 if (bridge->driver->agp_map_page(page,
156 &bridge->scratch_page_dma)) {
157 dev_err(&bridge->dev->dev,
158 "unable to dma-map scratch page\n");
159 rc = -ENOMEM;
160 goto err_out_nounmap;
161 }
162 } else {
163 bridge->scratch_page_dma = page_to_phys(page);
164 }
165 155
166 bridge->scratch_page = bridge->driver->mask_memory(bridge, 156 bridge->scratch_page = bridge->driver->mask_memory(bridge,
167 bridge->scratch_page_dma, 0); 157 bridge->scratch_page_dma, 0);
@@ -204,12 +194,6 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
204 return 0; 194 return 0;
205 195
206err_out: 196err_out:
207 if (bridge->driver->needs_scratch_page &&
208 bridge->driver->agp_unmap_page) {
209 bridge->driver->agp_unmap_page(bridge->scratch_page_page,
210 bridge->scratch_page_dma);
211 }
212err_out_nounmap:
213 if (bridge->driver->needs_scratch_page) { 197 if (bridge->driver->needs_scratch_page) {
214 void *va = page_address(bridge->scratch_page_page); 198 void *va = page_address(bridge->scratch_page_page);
215 199
@@ -240,10 +224,6 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge)
240 bridge->driver->needs_scratch_page) { 224 bridge->driver->needs_scratch_page) {
241 void *va = page_address(bridge->scratch_page_page); 225 void *va = page_address(bridge->scratch_page_page);
242 226
243 if (bridge->driver->agp_unmap_page)
244 bridge->driver->agp_unmap_page(bridge->scratch_page_page,
245 bridge->scratch_page_dma);
246
247 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP); 227 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
248 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE); 228 bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
249 } 229 }
diff --git a/drivers/char/agp/compat_ioctl.c b/drivers/char/agp/compat_ioctl.c
index 9d2c97a69cdd..a48e05b31593 100644
--- a/drivers/char/agp/compat_ioctl.c
+++ b/drivers/char/agp/compat_ioctl.c
@@ -276,7 +276,6 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
276 break; 276 break;
277 277
278 case AGPIOC_CHIPSET_FLUSH32: 278 case AGPIOC_CHIPSET_FLUSH32:
279 ret_val = agpioc_chipset_flush_wrap(curr_priv);
280 break; 279 break;
281 } 280 }
282 281
diff --git a/drivers/char/agp/compat_ioctl.h b/drivers/char/agp/compat_ioctl.h
index 0c9678ac0371..f30e0fd97963 100644
--- a/drivers/char/agp/compat_ioctl.h
+++ b/drivers/char/agp/compat_ioctl.h
@@ -102,6 +102,5 @@ void agp_free_memory_wrap(struct agp_memory *memory);
102struct agp_memory *agp_allocate_memory_wrap(size_t pg_count, u32 type); 102struct agp_memory *agp_allocate_memory_wrap(size_t pg_count, u32 type);
103struct agp_memory *agp_find_mem_by_key(int key); 103struct agp_memory *agp_find_mem_by_key(int key);
104struct agp_client *agp_find_client_by_pid(pid_t id); 104struct agp_client *agp_find_client_by_pid(pid_t id);
105int agpioc_chipset_flush_wrap(struct agp_file_private *priv);
106 105
107#endif /* _AGP_COMPAT_H */ 106#endif /* _AGP_COMPAT_H */
diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c
index 43412c03969e..2e044338753c 100644
--- a/drivers/char/agp/frontend.c
+++ b/drivers/char/agp/frontend.c
@@ -39,7 +39,6 @@
39#include <linux/mm.h> 39#include <linux/mm.h>
40#include <linux/fs.h> 40#include <linux/fs.h>
41#include <linux/sched.h> 41#include <linux/sched.h>
42#include <linux/smp_lock.h>
43#include <asm/uaccess.h> 42#include <asm/uaccess.h>
44#include <asm/pgtable.h> 43#include <asm/pgtable.h>
45#include "agp.h" 44#include "agp.h"
@@ -958,13 +957,6 @@ static int agpioc_unbind_wrap(struct agp_file_private *priv, void __user *arg)
958 return agp_unbind_memory(memory); 957 return agp_unbind_memory(memory);
959} 958}
960 959
961int agpioc_chipset_flush_wrap(struct agp_file_private *priv)
962{
963 DBG("");
964 agp_flush_chipset(agp_bridge);
965 return 0;
966}
967
968static long agp_ioctl(struct file *file, 960static long agp_ioctl(struct file *file,
969 unsigned int cmd, unsigned long arg) 961 unsigned int cmd, unsigned long arg)
970{ 962{
@@ -1040,7 +1032,6 @@ static long agp_ioctl(struct file *file,
1040 break; 1032 break;
1041 1033
1042 case AGPIOC_CHIPSET_FLUSH: 1034 case AGPIOC_CHIPSET_FLUSH:
1043 ret_val = agpioc_chipset_flush_wrap(curr_priv);
1044 break; 1035 break;
1045 } 1036 }
1046 1037
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index d2abf5143983..b072648dc3f6 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -81,13 +81,6 @@ static int agp_get_key(void)
81 return -1; 81 return -1;
82} 82}
83 83
84void agp_flush_chipset(struct agp_bridge_data *bridge)
85{
86 if (bridge->driver->chipset_flush)
87 bridge->driver->chipset_flush(bridge);
88}
89EXPORT_SYMBOL(agp_flush_chipset);
90
91/* 84/*
92 * Use kmalloc if possible for the page list. Otherwise fall back to 85 * Use kmalloc if possible for the page list. Otherwise fall back to
93 * vmalloc. This speeds things up and also saves memory for small AGP 86 * vmalloc. This speeds things up and also saves memory for small AGP
@@ -122,6 +115,9 @@ static struct agp_memory *agp_create_user_memory(unsigned long num_agp_pages)
122 struct agp_memory *new; 115 struct agp_memory *new;
123 unsigned long alloc_size = num_agp_pages*sizeof(struct page *); 116 unsigned long alloc_size = num_agp_pages*sizeof(struct page *);
124 117
118 if (INT_MAX/sizeof(struct page *) < num_agp_pages)
119 return NULL;
120
125 new = kzalloc(sizeof(struct agp_memory), GFP_KERNEL); 121 new = kzalloc(sizeof(struct agp_memory), GFP_KERNEL);
126 if (new == NULL) 122 if (new == NULL)
127 return NULL; 123 return NULL;
@@ -241,11 +237,14 @@ struct agp_memory *agp_allocate_memory(struct agp_bridge_data *bridge,
241 int scratch_pages; 237 int scratch_pages;
242 struct agp_memory *new; 238 struct agp_memory *new;
243 size_t i; 239 size_t i;
240 int cur_memory;
244 241
245 if (!bridge) 242 if (!bridge)
246 return NULL; 243 return NULL;
247 244
248 if ((atomic_read(&bridge->current_memory_agp) + page_count) > bridge->max_memory_agp) 245 cur_memory = atomic_read(&bridge->current_memory_agp);
246 if ((cur_memory + page_count > bridge->max_memory_agp) ||
247 (cur_memory + page_count < page_count))
249 return NULL; 248 return NULL;
250 249
251 if (type >= AGP_USER_TYPES) { 250 if (type >= AGP_USER_TYPES) {
@@ -437,11 +436,6 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start)
437 curr->is_flushed = true; 436 curr->is_flushed = true;
438 } 437 }
439 438
440 if (curr->bridge->driver->agp_map_memory) {
441 ret_val = curr->bridge->driver->agp_map_memory(curr);
442 if (ret_val)
443 return ret_val;
444 }
445 ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); 439 ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
446 440
447 if (ret_val != 0) 441 if (ret_val != 0)
@@ -483,9 +477,6 @@ int agp_unbind_memory(struct agp_memory *curr)
483 if (ret_val != 0) 477 if (ret_val != 0)
484 return ret_val; 478 return ret_val;
485 479
486 if (curr->bridge->driver->agp_unmap_memory)
487 curr->bridge->driver->agp_unmap_memory(curr);
488
489 curr->is_bound = false; 480 curr->is_bound = false;
490 curr->pg_start = 0; 481 curr->pg_start = 0;
491 spin_lock(&curr->bridge->mapped_lock); 482 spin_lock(&curr->bridge->mapped_lock);
@@ -495,26 +486,6 @@ int agp_unbind_memory(struct agp_memory *curr)
495} 486}
496EXPORT_SYMBOL(agp_unbind_memory); 487EXPORT_SYMBOL(agp_unbind_memory);
497 488
498/**
499 * agp_rebind_emmory - Rewrite the entire GATT, useful on resume
500 */
501int agp_rebind_memory(void)
502{
503 struct agp_memory *curr;
504 int ret_val = 0;
505
506 spin_lock(&agp_bridge->mapped_lock);
507 list_for_each_entry(curr, &agp_bridge->mapped_list, mapped_list) {
508 ret_val = curr->bridge->driver->insert_memory(curr,
509 curr->pg_start,
510 curr->type);
511 if (ret_val != 0)
512 break;
513 }
514 spin_unlock(&agp_bridge->mapped_lock);
515 return ret_val;
516}
517EXPORT_SYMBOL(agp_rebind_memory);
518 489
519/* End - Routines for handling swapping of agp_memory into the GATT */ 490/* End - Routines for handling swapping of agp_memory into the GATT */
520 491
@@ -984,7 +955,9 @@ int agp_generic_create_gatt_table(struct agp_bridge_data *bridge)
984 955
985 bridge->driver->cache_flush(); 956 bridge->driver->cache_flush();
986#ifdef CONFIG_X86 957#ifdef CONFIG_X86
987 set_memory_uc((unsigned long)table, 1 << page_order); 958 if (set_memory_uc((unsigned long)table, 1 << page_order))
959 printk(KERN_WARNING "Could not set GATT table memory to UC!");
960
988 bridge->gatt_table = (void *)table; 961 bridge->gatt_table = (void *)table;
989#else 962#else
990 bridge->gatt_table = ioremap_nocache(virt_to_phys(table), 963 bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
@@ -1122,8 +1095,8 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
1122 return -EINVAL; 1095 return -EINVAL;
1123 } 1096 }
1124 1097
1125 /* AK: could wrap */ 1098 if (((pg_start + mem->page_count) > num_entries) ||
1126 if ((pg_start + mem->page_count) > num_entries) 1099 ((pg_start + mem->page_count) < pg_start))
1127 return -EINVAL; 1100 return -EINVAL;
1128 1101
1129 j = pg_start; 1102 j = pg_start;
@@ -1157,7 +1130,7 @@ int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
1157{ 1130{
1158 size_t i; 1131 size_t i;
1159 struct agp_bridge_data *bridge; 1132 struct agp_bridge_data *bridge;
1160 int mask_type; 1133 int mask_type, num_entries;
1161 1134
1162 bridge = mem->bridge; 1135 bridge = mem->bridge;
1163 if (!bridge) 1136 if (!bridge)
@@ -1169,6 +1142,11 @@ int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
1169 if (type != mem->type) 1142 if (type != mem->type)
1170 return -EINVAL; 1143 return -EINVAL;
1171 1144
1145 num_entries = agp_num_entries();
1146 if (((pg_start + mem->page_count) > num_entries) ||
1147 ((pg_start + mem->page_count) < pg_start))
1148 return -EINVAL;
1149
1172 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); 1150 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
1173 if (mask_type != 0) { 1151 if (mask_type != 0) {
1174 /* The generic routines know nothing of memory types */ 1152 /* The generic routines know nothing of memory types */
diff --git a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c
index e763d3312ce7..75b763cb3ea1 100644
--- a/drivers/char/agp/i460-agp.c
+++ b/drivers/char/agp/i460-agp.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of 2 * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
3 * the "Intel 460GTX Chipset Software Developer's Manual": 3 * the "Intel 460GTX Chipset Software Developer's Manual":
4 * http://developer.intel.com/design/itanium/downloads/24870401s.htm 4 * http://www.intel.com/design/archives/itanium/downloads/248704.htm
5 */ 5 */
6/* 6/*
7 * 460GX support by Chris Ahna <christopher.j.ahna@intel.com> 7 * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index cd18493c9527..b427711be4be 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -12,9 +12,6 @@
12#include <asm/smp.h> 12#include <asm/smp.h>
13#include "agp.h" 13#include "agp.h"
14#include "intel-agp.h" 14#include "intel-agp.h"
15#include <linux/intel-gtt.h>
16
17#include "intel-gtt.c"
18 15
19int intel_agp_enabled; 16int intel_agp_enabled;
20EXPORT_SYMBOL(intel_agp_enabled); 17EXPORT_SYMBOL(intel_agp_enabled);
@@ -703,179 +700,37 @@ static const struct agp_bridge_driver intel_7505_driver = {
703 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 700 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
704}; 701};
705 702
706static int find_gmch(u16 device)
707{
708 struct pci_dev *gmch_device;
709
710 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
711 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
712 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
713 device, gmch_device);
714 }
715
716 if (!gmch_device)
717 return 0;
718
719 intel_private.pcidev = gmch_device;
720 return 1;
721}
722
723/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 703/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
724 * driver and gmch_driver must be non-null, and find_gmch will determine 704 * driver and gmch_driver must be non-null, and find_gmch will determine
725 * which one should be used if a gmch_chip_id is present. 705 * which one should be used if a gmch_chip_id is present.
726 */ 706 */
727static const struct intel_driver_description { 707static const struct intel_agp_driver_description {
728 unsigned int chip_id; 708 unsigned int chip_id;
729 unsigned int gmch_chip_id;
730 char *name; 709 char *name;
731 const struct agp_bridge_driver *driver; 710 const struct agp_bridge_driver *driver;
732 const struct agp_bridge_driver *gmch_driver;
733} intel_agp_chipsets[] = { 711} intel_agp_chipsets[] = {
734 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL }, 712 { PCI_DEVICE_ID_INTEL_82443LX_0, "440LX", &intel_generic_driver },
735 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL }, 713 { PCI_DEVICE_ID_INTEL_82443BX_0, "440BX", &intel_generic_driver },
736 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL }, 714 { PCI_DEVICE_ID_INTEL_82443GX_0, "440GX", &intel_generic_driver },
737 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 715 { PCI_DEVICE_ID_INTEL_82815_MC, "i815", &intel_815_driver },
738 NULL, &intel_810_driver }, 716 { PCI_DEVICE_ID_INTEL_82820_HB, "i820", &intel_820_driver },
739 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 717 { PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
740 NULL, &intel_810_driver }, 718 { PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
741 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 719 { PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
742 NULL, &intel_810_driver }, 720 { PCI_DEVICE_ID_INTEL_82845_HB, "i845", &intel_845_driver },
743 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 721 { PCI_DEVICE_ID_INTEL_82845G_HB, "845G", &intel_845_driver },
744 &intel_815_driver, &intel_810_driver }, 722 { PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
745 { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL }, 723 { PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
746 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL }, 724 { PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
747 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 725 { PCI_DEVICE_ID_INTEL_82855GM_HB, "855GM", &intel_845_driver },
748 &intel_830mp_driver, &intel_830_driver }, 726 { PCI_DEVICE_ID_INTEL_82860_HB, "i860", &intel_860_driver },
749 { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL }, 727 { PCI_DEVICE_ID_INTEL_82865_HB, "865", &intel_845_driver },
750 { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL }, 728 { PCI_DEVICE_ID_INTEL_82875_HB, "i875", &intel_845_driver },
751 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 729 { PCI_DEVICE_ID_INTEL_7505_0, "E7505", &intel_7505_driver },
752 &intel_845_driver, &intel_830_driver }, 730 { PCI_DEVICE_ID_INTEL_7205_0, "E7205", &intel_7505_driver },
753 { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL }, 731 { 0, NULL, NULL }
754 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, "854",
755 &intel_845_driver, &intel_830_driver },
756 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
757 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
758 &intel_845_driver, &intel_830_driver },
759 { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
760 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
761 &intel_845_driver, &intel_830_driver },
762 { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
763 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
764 NULL, &intel_915_driver },
765 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
766 NULL, &intel_915_driver },
767 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
768 NULL, &intel_915_driver },
769 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
770 NULL, &intel_915_driver },
771 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
772 NULL, &intel_915_driver },
773 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
774 NULL, &intel_915_driver },
775 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
776 NULL, &intel_i965_driver },
777 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
778 NULL, &intel_i965_driver },
779 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
780 NULL, &intel_i965_driver },
781 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
782 NULL, &intel_i965_driver },
783 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
784 NULL, &intel_i965_driver },
785 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
786 NULL, &intel_i965_driver },
787 { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
788 { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
789 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33",
790 NULL, &intel_g33_driver },
791 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
792 NULL, &intel_g33_driver },
793 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
794 NULL, &intel_g33_driver },
795 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
796 NULL, &intel_g33_driver },
797 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
798 NULL, &intel_g33_driver },
799 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG,
800 "GM45", NULL, &intel_i965_driver },
801 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG,
802 "Eaglelake", NULL, &intel_i965_driver },
803 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG,
804 "Q45/Q43", NULL, &intel_i965_driver },
805 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG,
806 "G45/G43", NULL, &intel_i965_driver },
807 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG,
808 "B43", NULL, &intel_i965_driver },
809 { PCI_DEVICE_ID_INTEL_B43_1_HB, PCI_DEVICE_ID_INTEL_B43_1_IG,
810 "B43", NULL, &intel_i965_driver },
811 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG,
812 "G41", NULL, &intel_i965_driver },
813 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
814 "HD Graphics", NULL, &intel_i965_driver },
815 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
816 "HD Graphics", NULL, &intel_i965_driver },
817 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
818 "HD Graphics", NULL, &intel_i965_driver },
819 { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
820 "HD Graphics", NULL, &intel_i965_driver },
821 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
822 "Sandybridge", NULL, &intel_gen6_driver },
823 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
824 "Sandybridge", NULL, &intel_gen6_driver },
825 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
826 "Sandybridge", NULL, &intel_gen6_driver },
827 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
828 "Sandybridge", NULL, &intel_gen6_driver },
829 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
830 "Sandybridge", NULL, &intel_gen6_driver },
831 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
832 "Sandybridge", NULL, &intel_gen6_driver },
833 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
834 "Sandybridge", NULL, &intel_gen6_driver },
835 { 0, 0, NULL, NULL, NULL }
836}; 732};
837 733
838static int __devinit intel_gmch_probe(struct pci_dev *pdev,
839 struct agp_bridge_data *bridge)
840{
841 int i, mask;
842
843 bridge->driver = NULL;
844
845 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
846 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
847 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
848 bridge->driver =
849 intel_agp_chipsets[i].gmch_driver;
850 break;
851 }
852 }
853
854 if (!bridge->driver)
855 return 0;
856
857 bridge->dev_private_data = &intel_private;
858 bridge->dev = pdev;
859
860 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
861
862 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
863 mask = 40;
864 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
865 mask = 36;
866 else
867 mask = 32;
868
869 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
870 dev_err(&intel_private.pcidev->dev,
871 "set gfx device dma mask %d-bit failed!\n", mask);
872 else
873 pci_set_consistent_dma_mask(intel_private.pcidev,
874 DMA_BIT_MASK(mask));
875
876 return 1;
877}
878
879static int __devinit agp_intel_probe(struct pci_dev *pdev, 734static int __devinit agp_intel_probe(struct pci_dev *pdev,
880 const struct pci_device_id *ent) 735 const struct pci_device_id *ent)
881{ 736{
@@ -905,7 +760,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
905 } 760 }
906 } 761 }
907 762
908 if (intel_agp_chipsets[i].name == NULL) { 763 if (!bridge->driver) {
909 if (cap_ptr) 764 if (cap_ptr)
910 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", 765 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
911 pdev->vendor, pdev->device); 766 pdev->vendor, pdev->device);
@@ -913,34 +768,20 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
913 return -ENODEV; 768 return -ENODEV;
914 } 769 }
915 770
916 if (!bridge->driver) {
917 if (cap_ptr)
918 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
919 intel_agp_chipsets[i].gmch_chip_id);
920 agp_put_bridge(bridge);
921 return -ENODEV;
922 }
923
924 bridge->dev = pdev; 771 bridge->dev = pdev;
925 bridge->dev_private_data = NULL; 772 bridge->dev_private_data = NULL;
926 773
927 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); 774 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
928 775
929 /* 776 /*
930 * If the device has not been properly setup, the following will catch
931 * the problem and should stop the system from crashing.
932 * 20030610 - hamish@zot.org
933 */
934 if (pci_enable_device(pdev)) {
935 dev_err(&pdev->dev, "can't enable PCI device\n");
936 agp_put_bridge(bridge);
937 return -ENODEV;
938 }
939
940 /*
941 * The following fixes the case where the BIOS has "forgotten" to 777 * The following fixes the case where the BIOS has "forgotten" to
942 * provide an address range for the GART. 778 * provide an address range for the GART.
943 * 20030610 - hamish@zot.org 779 * 20030610 - hamish@zot.org
780 * This happens before pci_enable_device() intentionally;
781 * calling pci_enable_device() before assigning the resource
782 * will result in the GART being disabled on machines with such
783 * BIOSs (the GART ends up with a BAR starting at 0, which
784 * conflicts a lot of other devices).
944 */ 785 */
945 r = &pdev->resource[0]; 786 r = &pdev->resource[0];
946 if (!r->start && r->end) { 787 if (!r->start && r->end) {
@@ -951,6 +792,17 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
951 } 792 }
952 } 793 }
953 794
795 /*
796 * If the device has not been properly setup, the following will catch
797 * the problem and should stop the system from crashing.
798 * 20030610 - hamish@zot.org
799 */
800 if (pci_enable_device(pdev)) {
801 dev_err(&pdev->dev, "can't enable PCI device\n");
802 agp_put_bridge(bridge);
803 return -ENODEV;
804 }
805
954 /* Fill in the mode register */ 806 /* Fill in the mode register */
955 if (cap_ptr) { 807 if (cap_ptr) {
956 pci_read_config_dword(pdev, 808 pci_read_config_dword(pdev,
@@ -972,8 +824,7 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
972 824
973 agp_remove_bridge(bridge); 825 agp_remove_bridge(bridge);
974 826
975 if (intel_private.pcidev) 827 intel_gmch_remove(pdev);
976 pci_dev_put(intel_private.pcidev);
977 828
978 agp_put_bridge(bridge); 829 agp_put_bridge(bridge);
979} 830}
@@ -982,14 +833,9 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
982static int agp_intel_resume(struct pci_dev *pdev) 833static int agp_intel_resume(struct pci_dev *pdev)
983{ 834{
984 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 835 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
985 int ret_val;
986 836
987 bridge->driver->configure(); 837 bridge->driver->configure();
988 838
989 ret_val = agp_rebind_memory();
990 if (ret_val != 0)
991 return ret_val;
992
993 return 0; 839 return 0;
994} 840}
995#endif 841#endif
@@ -1049,6 +895,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
1049 ID(PCI_DEVICE_ID_INTEL_G45_HB), 895 ID(PCI_DEVICE_ID_INTEL_G45_HB),
1050 ID(PCI_DEVICE_ID_INTEL_G41_HB), 896 ID(PCI_DEVICE_ID_INTEL_G41_HB),
1051 ID(PCI_DEVICE_ID_INTEL_B43_HB), 897 ID(PCI_DEVICE_ID_INTEL_B43_HB),
898 ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
1052 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB), 899 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
1053 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), 900 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
1054 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), 901 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
@@ -1056,6 +903,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
1056 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), 903 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
1057 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB), 904 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
1058 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB), 905 ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
906 ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
907 ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
908 ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
1059 { } 909 { }
1060}; 910};
1061 911
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index d09b1ab7e8ab..5da67f165afa 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -75,6 +75,8 @@
75#define I810_GMS_DISABLE 0x00000000 75#define I810_GMS_DISABLE 0x00000000
76#define I810_PGETBL_CTL 0x2020 76#define I810_PGETBL_CTL 0x2020
77#define I810_PGETBL_ENABLED 0x00000001 77#define I810_PGETBL_ENABLED 0x00000001
78/* Note: PGETBL_CTL2 has a different offset on G33. */
79#define I965_PGETBL_CTL2 0x20c4
78#define I965_PGETBL_SIZE_MASK 0x0000000e 80#define I965_PGETBL_SIZE_MASK 0x0000000e
79#define I965_PGETBL_SIZE_512KB (0 << 1) 81#define I965_PGETBL_SIZE_512KB (0 << 1)
80#define I965_PGETBL_SIZE_256KB (1 << 1) 82#define I965_PGETBL_SIZE_256KB (1 << 1)
@@ -82,9 +84,18 @@
82#define I965_PGETBL_SIZE_1MB (3 << 1) 84#define I965_PGETBL_SIZE_1MB (3 << 1)
83#define I965_PGETBL_SIZE_2MB (4 << 1) 85#define I965_PGETBL_SIZE_2MB (4 << 1)
84#define I965_PGETBL_SIZE_1_5MB (5 << 1) 86#define I965_PGETBL_SIZE_1_5MB (5 << 1)
85#define G33_PGETBL_SIZE_MASK (3 << 8) 87#define G33_GMCH_SIZE_MASK (3 << 8)
86#define G33_PGETBL_SIZE_1M (1 << 8) 88#define G33_GMCH_SIZE_1M (1 << 8)
87#define G33_PGETBL_SIZE_2M (2 << 8) 89#define G33_GMCH_SIZE_2M (2 << 8)
90#define G4x_GMCH_SIZE_MASK (0xf << 8)
91#define G4x_GMCH_SIZE_1M (0x1 << 8)
92#define G4x_GMCH_SIZE_2M (0x3 << 8)
93#define G4x_GMCH_SIZE_VT_EN (0x8 << 8)
94#define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
95#define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
96#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
97
98#define GFX_FLSH_CNTL 0x2170 /* 915+ */
88 99
89#define I810_DRAM_CTL 0x3000 100#define I810_DRAM_CTL 0x3000
90#define I810_DRAM_ROW_0 0x00000001 101#define I810_DRAM_ROW_0 0x00000001
@@ -120,6 +131,7 @@
120#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 131#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
121 132
122#define I915_IFPADDR 0x60 133#define I915_IFPADDR 0x60
134#define I830_HIC 0x70
123 135
124/* Intel 965G registers */ 136/* Intel 965G registers */
125#define I965_MSAC 0x62 137#define I965_MSAC 0x62
@@ -214,45 +226,16 @@
214#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126 226#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
215#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ 227#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
216#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A 228#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
217 229#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */
218/* cover 915 and 945 variants */ 230#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152
219#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 231#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162
220 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ 232#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */
221 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ 233#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156
222 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ 234#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
223 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ 235#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
224 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) 236#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
225 237
226#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 238int intel_gmch_probe(struct pci_dev *pdev,
227 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ 239 struct agp_bridge_data *bridge);
228 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 240void intel_gmch_remove(struct pci_dev *pdev);
229 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
230 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
231 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
232
233#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
234 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
235 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
236 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
237 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
238
239#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
240 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
241
242#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
243 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \
244 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)
245
246#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
247 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
248 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
249 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
250 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
251 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
252 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
253 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
254 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
255 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
256 IS_SNB)
257
258#endif 241#endif
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 75e0a3497888..85151019dde1 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -15,6 +15,18 @@
15 * /fairy-tale-mode off 15 * /fairy-tale-mode off
16 */ 16 */
17 17
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/pagemap.h>
23#include <linux/agp_backend.h>
24#include <linux/delay.h>
25#include <asm/smp.h>
26#include "agp.h"
27#include "intel-agp.h"
28#include <drm/intel-gtt.h>
29
18/* 30/*
19 * If we have Intel graphics, we're not going to have anything other than 31 * If we have Intel graphics, we're not going to have anything other than
20 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
@@ -23,121 +35,79 @@
23 */ 35 */
24#ifdef CONFIG_DMAR 36#ifdef CONFIG_DMAR
25#define USE_PCI_DMA_API 1 37#define USE_PCI_DMA_API 1
38#else
39#define USE_PCI_DMA_API 0
26#endif 40#endif
27 41
28/* Max amount of stolen space, anything above will be returned to Linux */ 42struct intel_gtt_driver {
29int intel_max_stolen = 32 * 1024 * 1024; 43 unsigned int gen : 8;
30EXPORT_SYMBOL(intel_max_stolen); 44 unsigned int is_g33 : 1;
31 45 unsigned int is_pineview : 1;
32static const struct aper_size_info_fixed intel_i810_sizes[] = 46 unsigned int is_ironlake : 1;
33{ 47 unsigned int has_pgtbl_enable : 1;
34 {64, 16384, 4}, 48 unsigned int dma_mask_size : 8;
35 /* The 32M mode still requires a 64k gatt */ 49 /* Chipset specific GTT setup */
36 {32, 8192, 4} 50 int (*setup)(void);
37}; 51 /* This should undo anything done in ->setup() save the unmapping
38 52 * of the mmio register file, that's done in the generic code. */
39#define AGP_DCACHE_MEMORY 1 53 void (*cleanup)(void);
40#define AGP_PHYS_MEMORY 2 54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
41#define INTEL_AGP_CACHED_MEMORY 3 55 /* Flags is a more or less chipset specific opaque value.
42 56 * For chipsets that need to support old ums (non-gem) code, this
43static struct gatt_mask intel_i810_masks[] = 57 * needs to be identical to the various supported agp memory types! */
44{ 58 bool (*check_flags)(unsigned int flags);
45 {.mask = I810_PTE_VALID, .type = 0}, 59 void (*chipset_flush)(void);
46 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
47 {.mask = I810_PTE_VALID, .type = 0},
48 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
49 .type = INTEL_AGP_CACHED_MEMORY}
50};
51
52#define INTEL_AGP_UNCACHED_MEMORY 0
53#define INTEL_AGP_CACHED_MEMORY_LLC 1
54#define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
55#define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
56#define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
57
58static struct gatt_mask intel_gen6_masks[] =
59{
60 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
61 .type = INTEL_AGP_UNCACHED_MEMORY },
62 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
63 .type = INTEL_AGP_CACHED_MEMORY_LLC },
64 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
65 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
66 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
67 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
68 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
69 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
70}; 60};
71 61
72static struct _intel_private { 62static struct _intel_private {
63 struct intel_gtt base;
64 const struct intel_gtt_driver *driver;
73 struct pci_dev *pcidev; /* device one */ 65 struct pci_dev *pcidev; /* device one */
66 struct pci_dev *bridge_dev;
74 u8 __iomem *registers; 67 u8 __iomem *registers;
68 phys_addr_t gtt_bus_addr;
69 phys_addr_t gma_bus_addr;
70 u32 PGETBL_save;
75 u32 __iomem *gtt; /* I915G */ 71 u32 __iomem *gtt; /* I915G */
72 bool clear_fake_agp; /* on first access via agp, fill with scratch */
76 int num_dcache_entries; 73 int num_dcache_entries;
77 /* gtt_entries is the number of gtt entries that are already mapped 74 void __iomem *i9xx_flush_page;
78 * to stolen memory. Stolen memory is larger than the memory mapped 75 char *i81x_gtt_table;
79 * through gtt_entries, as it includes some reserved space for the BIOS
80 * popup and for the GTT.
81 */
82 int gtt_entries; /* i830+ */
83 int gtt_total_size;
84 union {
85 void __iomem *i9xx_flush_page;
86 void *i8xx_flush_page;
87 };
88 struct page *i8xx_page;
89 struct resource ifp_resource; 76 struct resource ifp_resource;
90 int resource_valid; 77 int resource_valid;
78 struct page *scratch_page;
79 dma_addr_t scratch_page_dma;
91} intel_private; 80} intel_private;
92 81
93#ifdef USE_PCI_DMA_API 82#define INTEL_GTT_GEN intel_private.driver->gen
94static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 83#define IS_G33 intel_private.driver->is_g33
95{ 84#define IS_PINEVIEW intel_private.driver->is_pineview
96 *ret = pci_map_page(intel_private.pcidev, page, 0, 85#define IS_IRONLAKE intel_private.driver->is_ironlake
97 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 86#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
98 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
99 return -EINVAL;
100 return 0;
101}
102 87
103static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 88int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
104{ 89 struct scatterlist **sg_list, int *num_sg)
105 pci_unmap_page(intel_private.pcidev, dma,
106 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
107}
108
109static void intel_agp_free_sglist(struct agp_memory *mem)
110{
111 struct sg_table st;
112
113 st.sgl = mem->sg_list;
114 st.orig_nents = st.nents = mem->page_count;
115
116 sg_free_table(&st);
117
118 mem->sg_list = NULL;
119 mem->num_sg = 0;
120}
121
122static int intel_agp_map_memory(struct agp_memory *mem)
123{ 90{
124 struct sg_table st; 91 struct sg_table st;
125 struct scatterlist *sg; 92 struct scatterlist *sg;
126 int i; 93 int i;
127 94
128 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 95 if (*sg_list)
96 return 0; /* already mapped (for e.g. resume */
97
98 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
129 99
130 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 100 if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
131 goto err; 101 goto err;
132 102
133 mem->sg_list = sg = st.sgl; 103 *sg_list = sg = st.sgl;
134 104
135 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 105 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
136 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 106 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
137 107
138 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 108 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
139 mem->page_count, PCI_DMA_BIDIRECTIONAL); 109 num_entries, PCI_DMA_BIDIRECTIONAL);
140 if (unlikely(!mem->num_sg)) 110 if (unlikely(!*num_sg))
141 goto err; 111 goto err;
142 112
143 return 0; 113 return 0;
@@ -146,145 +116,24 @@ err:
146 sg_free_table(&st); 116 sg_free_table(&st);
147 return -ENOMEM; 117 return -ENOMEM;
148} 118}
119EXPORT_SYMBOL(intel_gtt_map_memory);
149 120
150static void intel_agp_unmap_memory(struct agp_memory *mem) 121void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
151{ 122{
123 struct sg_table st;
152 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 124 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
153 125
154 pci_unmap_sg(intel_private.pcidev, mem->sg_list, 126 pci_unmap_sg(intel_private.pcidev, sg_list,
155 mem->page_count, PCI_DMA_BIDIRECTIONAL); 127 num_sg, PCI_DMA_BIDIRECTIONAL);
156 intel_agp_free_sglist(mem);
157}
158
159static void intel_agp_insert_sg_entries(struct agp_memory *mem,
160 off_t pg_start, int mask_type)
161{
162 struct scatterlist *sg;
163 int i, j;
164
165 j = pg_start;
166
167 WARN_ON(!mem->num_sg);
168
169 if (mem->num_sg == mem->page_count) {
170 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
171 writel(agp_bridge->driver->mask_memory(agp_bridge,
172 sg_dma_address(sg), mask_type),
173 intel_private.gtt+j);
174 j++;
175 }
176 } else {
177 /* sg may merge pages, but we have to separate
178 * per-page addr for GTT */
179 unsigned int len, m;
180
181 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
182 len = sg_dma_len(sg) / PAGE_SIZE;
183 for (m = 0; m < len; m++) {
184 writel(agp_bridge->driver->mask_memory(agp_bridge,
185 sg_dma_address(sg) + m * PAGE_SIZE,
186 mask_type),
187 intel_private.gtt+j);
188 j++;
189 }
190 }
191 }
192 readl(intel_private.gtt+j-1);
193}
194
195#else
196
197static void intel_agp_insert_sg_entries(struct agp_memory *mem,
198 off_t pg_start, int mask_type)
199{
200 int i, j;
201
202 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
203 writel(agp_bridge->driver->mask_memory(agp_bridge,
204 page_to_phys(mem->pages[i]), mask_type),
205 intel_private.gtt+j);
206 }
207
208 readl(intel_private.gtt+j-1);
209}
210
211#endif
212
213static int intel_i810_fetch_size(void)
214{
215 u32 smram_miscc;
216 struct aper_size_info_fixed *values;
217 128
218 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 129 st.sgl = sg_list;
219 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 130 st.orig_nents = st.nents = num_sg;
220
221 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
222 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
223 return 0;
224 }
225 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
226 agp_bridge->current_size = (void *) (values + 1);
227 agp_bridge->aperture_size_idx = 1;
228 return values[1].size;
229 } else {
230 agp_bridge->current_size = (void *) (values);
231 agp_bridge->aperture_size_idx = 0;
232 return values[0].size;
233 }
234
235 return 0;
236}
237
238static int intel_i810_configure(void)
239{
240 struct aper_size_info_fixed *current_size;
241 u32 temp;
242 int i;
243
244 current_size = A_SIZE_FIX(agp_bridge->current_size);
245
246 if (!intel_private.registers) {
247 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
248 temp &= 0xfff80000;
249
250 intel_private.registers = ioremap(temp, 128 * 4096);
251 if (!intel_private.registers) {
252 dev_err(&intel_private.pcidev->dev,
253 "can't remap memory\n");
254 return -ENOMEM;
255 }
256 }
257
258 if ((readl(intel_private.registers+I810_DRAM_CTL)
259 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
260 /* This will need to be dynamically assigned */
261 dev_info(&intel_private.pcidev->dev,
262 "detected 4MB dedicated video ram\n");
263 intel_private.num_dcache_entries = 1024;
264 }
265 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
266 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
267 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
268 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
269
270 if (agp_bridge->driver->needs_scratch_page) {
271 for (i = 0; i < current_size->num_entries; i++) {
272 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
273 }
274 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
275 }
276 global_cache_flush();
277 return 0;
278}
279 131
280static void intel_i810_cleanup(void) 132 sg_free_table(&st);
281{
282 writel(0, intel_private.registers+I810_PGETBL_CTL);
283 readl(intel_private.registers); /* PCI Posting. */
284 iounmap(intel_private.registers);
285} 133}
134EXPORT_SYMBOL(intel_gtt_unmap_memory);
286 135
287static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 136static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
288{ 137{
289 return; 138 return;
290} 139}
@@ -319,108 +168,64 @@ static void i8xx_destroy_pages(struct page *page)
319 atomic_dec(&agp_bridge->current_memory_agp); 168 atomic_dec(&agp_bridge->current_memory_agp);
320} 169}
321 170
322static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 171#define I810_GTT_ORDER 4
323 int type) 172static int i810_setup(void)
324{
325 if (type < AGP_USER_TYPES)
326 return type;
327 else if (type == AGP_USER_CACHED_MEMORY)
328 return INTEL_AGP_CACHED_MEMORY;
329 else
330 return 0;
331}
332
333static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
334 int type)
335{ 173{
336 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT; 174 u32 reg_addr;
337 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT; 175 char *gtt_table;
338
339 if (type_mask == AGP_USER_UNCACHED_MEMORY)
340 return INTEL_AGP_UNCACHED_MEMORY;
341 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
342 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
343 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
344 else /* set 'normal'/'cached' to LLC by default */
345 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
346 INTEL_AGP_CACHED_MEMORY_LLC;
347}
348 176
177 /* i81x does not preallocate the gtt. It's always 64kb in size. */
178 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
179 if (gtt_table == NULL)
180 return -ENOMEM;
181 intel_private.i81x_gtt_table = gtt_table;
349 182
350static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 183 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
351 int type) 184 reg_addr &= 0xfff80000;
352{
353 int i, j, num_entries;
354 void *temp;
355 int ret = -EINVAL;
356 int mask_type;
357
358 if (mem->page_count == 0)
359 goto out;
360 185
361 temp = agp_bridge->current_size; 186 intel_private.registers = ioremap(reg_addr, KB(64));
362 num_entries = A_SIZE_FIX(temp)->num_entries; 187 if (!intel_private.registers)
188 return -ENOMEM;
363 189
364 if ((pg_start + mem->page_count) > num_entries) 190 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
365 goto out_err; 191 intel_private.registers+I810_PGETBL_CTL);
366 192
193 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
367 194
368 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 195 if ((readl(intel_private.registers+I810_DRAM_CTL)
369 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 196 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
370 ret = -EBUSY; 197 dev_info(&intel_private.pcidev->dev,
371 goto out_err; 198 "detected 4MB dedicated video ram\n");
372 } 199 intel_private.num_dcache_entries = 1024;
373 } 200 }
374 201
375 if (type != mem->type) 202 return 0;
376 goto out_err; 203}
377
378 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
379
380 switch (mask_type) {
381 case AGP_DCACHE_MEMORY:
382 if (!mem->is_flushed)
383 global_cache_flush();
384 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
385 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
386 intel_private.registers+I810_PTE_BASE+(i*4));
387 }
388 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
389 break;
390 case AGP_PHYS_MEMORY:
391 case AGP_NORMAL_MEMORY:
392 if (!mem->is_flushed)
393 global_cache_flush();
394 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
395 writel(agp_bridge->driver->mask_memory(agp_bridge,
396 page_to_phys(mem->pages[i]), mask_type),
397 intel_private.registers+I810_PTE_BASE+(j*4));
398 }
399 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
400 break;
401 default:
402 goto out_err;
403 }
404 204
405out: 205static void i810_cleanup(void)
406 ret = 0; 206{
407out_err: 207 writel(0, intel_private.registers+I810_PGETBL_CTL);
408 mem->is_flushed = true; 208 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
409 return ret;
410} 209}
411 210
412static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 211static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
413 int type) 212 int type)
414{ 213{
415 int i; 214 int i;
416 215
417 if (mem->page_count == 0) 216 if ((pg_start + mem->page_count)
418 return 0; 217 > intel_private.num_dcache_entries)
218 return -EINVAL;
219
220 if (!mem->is_flushed)
221 global_cache_flush();
419 222
420 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 223 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
421 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 224 dma_addr_t addr = i << PAGE_SHIFT;
225 intel_private.driver->write_entry(addr,
226 i, type);
422 } 227 }
423 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 228 readl(intel_private.gtt+i-1);
424 229
425 return 0; 230 return 0;
426} 231}
@@ -467,29 +272,6 @@ static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
467 return new; 272 return new;
468} 273}
469 274
470static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
471{
472 struct agp_memory *new;
473
474 if (type == AGP_DCACHE_MEMORY) {
475 if (pg_count != intel_private.num_dcache_entries)
476 return NULL;
477
478 new = agp_create_memory(1);
479 if (new == NULL)
480 return NULL;
481
482 new->type = AGP_DCACHE_MEMORY;
483 new->page_count = pg_count;
484 new->num_scratch_pages = 0;
485 agp_free_page_array(new);
486 return new;
487 }
488 if (type == AGP_PHYS_MEMORY)
489 return alloc_agpphysmem_i8xx(pg_count, type);
490 return NULL;
491}
492
493static void intel_i810_free_by_type(struct agp_memory *curr) 275static void intel_i810_free_by_type(struct agp_memory *curr)
494{ 276{
495 agp_free_key(curr->key); 277 agp_free_key(curr->key);
@@ -507,118 +289,94 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
507 kfree(curr); 289 kfree(curr);
508} 290}
509 291
510static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 292static int intel_gtt_setup_scratch_page(void)
511 dma_addr_t addr, int type)
512{ 293{
513 /* Type checking must be done elsewhere */ 294 struct page *page;
514 return addr | bridge->driver->masks[type].mask; 295 dma_addr_t dma_addr;
296
297 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
298 if (page == NULL)
299 return -ENOMEM;
300 get_page(page);
301 set_pages_uc(page, 1);
302
303 if (intel_private.base.needs_dmar) {
304 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
305 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
306 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
307 return -EINVAL;
308
309 intel_private.scratch_page_dma = dma_addr;
310 } else
311 intel_private.scratch_page_dma = page_to_phys(page);
312
313 intel_private.scratch_page = page;
314
315 return 0;
515} 316}
516 317
517static struct aper_size_info_fixed intel_i830_sizes[] = 318static void i810_write_entry(dma_addr_t addr, unsigned int entry,
319 unsigned int flags)
518{ 320{
321 u32 pte_flags = I810_PTE_VALID;
322
323 switch (flags) {
324 case AGP_DCACHE_MEMORY:
325 pte_flags |= I810_PTE_LOCAL;
326 break;
327 case AGP_USER_CACHED_MEMORY:
328 pte_flags |= I830_PTE_SYSTEM_CACHED;
329 break;
330 }
331
332 writel(addr | pte_flags, intel_private.gtt + entry);
333}
334
335static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
336 {32, 8192, 3},
337 {64, 16384, 4},
519 {128, 32768, 5}, 338 {128, 32768, 5},
520 /* The 64M mode still requires a 128k gatt */
521 {64, 16384, 5},
522 {256, 65536, 6}, 339 {256, 65536, 6},
523 {512, 131072, 7}, 340 {512, 131072, 7},
524}; 341};
525 342
526static void intel_i830_init_gtt_entries(void) 343static unsigned int intel_gtt_stolen_size(void)
527{ 344{
528 u16 gmch_ctrl; 345 u16 gmch_ctrl;
529 int gtt_entries = 0;
530 u8 rdct; 346 u8 rdct;
531 int local = 0; 347 int local = 0;
532 static const int ddt[4] = { 0, 16, 32, 64 }; 348 static const int ddt[4] = { 0, 16, 32, 64 };
533 int size; /* reserved space (in kb) at the top of stolen memory */ 349 unsigned int stolen_size = 0;
534 350
535 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 351 if (INTEL_GTT_GEN == 1)
352 return 0; /* no stolen mem on i81x */
536 353
537 if (IS_I965) { 354 pci_read_config_word(intel_private.bridge_dev,
538 u32 pgetbl_ctl; 355 I830_GMCH_CTRL, &gmch_ctrl);
539 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
540
541 /* The 965 has a field telling us the size of the GTT,
542 * which may be larger than what is necessary to map the
543 * aperture.
544 */
545 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
546 case I965_PGETBL_SIZE_128KB:
547 size = 128;
548 break;
549 case I965_PGETBL_SIZE_256KB:
550 size = 256;
551 break;
552 case I965_PGETBL_SIZE_512KB:
553 size = 512;
554 break;
555 case I965_PGETBL_SIZE_1MB:
556 size = 1024;
557 break;
558 case I965_PGETBL_SIZE_2MB:
559 size = 2048;
560 break;
561 case I965_PGETBL_SIZE_1_5MB:
562 size = 1024 + 512;
563 break;
564 default:
565 dev_info(&intel_private.pcidev->dev,
566 "unknown page table size, assuming 512KB\n");
567 size = 512;
568 }
569 size += 4; /* add in BIOS popup space */
570 } else if (IS_G33 && !IS_PINEVIEW) {
571 /* G33's GTT size defined in gmch_ctrl */
572 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
573 case G33_PGETBL_SIZE_1M:
574 size = 1024;
575 break;
576 case G33_PGETBL_SIZE_2M:
577 size = 2048;
578 break;
579 default:
580 dev_info(&agp_bridge->dev->dev,
581 "unknown page table size 0x%x, assuming 512KB\n",
582 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
583 size = 512;
584 }
585 size += 4;
586 } else if (IS_G4X || IS_PINEVIEW) {
587 /* On 4 series hardware, GTT stolen is separate from graphics
588 * stolen, ignore it in stolen gtt entries counting. However,
589 * 4KB of the stolen memory doesn't get mapped to the GTT.
590 */
591 size = 4;
592 } else {
593 /* On previous hardware, the GTT size was just what was
594 * required to map the aperture.
595 */
596 size = agp_bridge->driver->fetch_size() + 4;
597 }
598 356
599 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 357 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
600 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 358 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
601 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 359 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
602 case I830_GMCH_GMS_STOLEN_512: 360 case I830_GMCH_GMS_STOLEN_512:
603 gtt_entries = KB(512) - KB(size); 361 stolen_size = KB(512);
604 break; 362 break;
605 case I830_GMCH_GMS_STOLEN_1024: 363 case I830_GMCH_GMS_STOLEN_1024:
606 gtt_entries = MB(1) - KB(size); 364 stolen_size = MB(1);
607 break; 365 break;
608 case I830_GMCH_GMS_STOLEN_8192: 366 case I830_GMCH_GMS_STOLEN_8192:
609 gtt_entries = MB(8) - KB(size); 367 stolen_size = MB(8);
610 break; 368 break;
611 case I830_GMCH_GMS_LOCAL: 369 case I830_GMCH_GMS_LOCAL:
612 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 370 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
613 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 371 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
614 MB(ddt[I830_RDRAM_DDT(rdct)]); 372 MB(ddt[I830_RDRAM_DDT(rdct)]);
615 local = 1; 373 local = 1;
616 break; 374 break;
617 default: 375 default:
618 gtt_entries = 0; 376 stolen_size = 0;
619 break; 377 break;
620 } 378 }
621 } else if (IS_SNB) { 379 } else if (INTEL_GTT_GEN == 6) {
622 /* 380 /*
623 * SandyBridge has new memory control reg at 0x50.w 381 * SandyBridge has new memory control reg at 0x50.w
624 */ 382 */
@@ -626,167 +384,341 @@ static void intel_i830_init_gtt_entries(void)
626 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 384 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
627 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 385 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
628 case SNB_GMCH_GMS_STOLEN_32M: 386 case SNB_GMCH_GMS_STOLEN_32M:
629 gtt_entries = MB(32) - KB(size); 387 stolen_size = MB(32);
630 break; 388 break;
631 case SNB_GMCH_GMS_STOLEN_64M: 389 case SNB_GMCH_GMS_STOLEN_64M:
632 gtt_entries = MB(64) - KB(size); 390 stolen_size = MB(64);
633 break; 391 break;
634 case SNB_GMCH_GMS_STOLEN_96M: 392 case SNB_GMCH_GMS_STOLEN_96M:
635 gtt_entries = MB(96) - KB(size); 393 stolen_size = MB(96);
636 break; 394 break;
637 case SNB_GMCH_GMS_STOLEN_128M: 395 case SNB_GMCH_GMS_STOLEN_128M:
638 gtt_entries = MB(128) - KB(size); 396 stolen_size = MB(128);
639 break; 397 break;
640 case SNB_GMCH_GMS_STOLEN_160M: 398 case SNB_GMCH_GMS_STOLEN_160M:
641 gtt_entries = MB(160) - KB(size); 399 stolen_size = MB(160);
642 break; 400 break;
643 case SNB_GMCH_GMS_STOLEN_192M: 401 case SNB_GMCH_GMS_STOLEN_192M:
644 gtt_entries = MB(192) - KB(size); 402 stolen_size = MB(192);
645 break; 403 break;
646 case SNB_GMCH_GMS_STOLEN_224M: 404 case SNB_GMCH_GMS_STOLEN_224M:
647 gtt_entries = MB(224) - KB(size); 405 stolen_size = MB(224);
648 break; 406 break;
649 case SNB_GMCH_GMS_STOLEN_256M: 407 case SNB_GMCH_GMS_STOLEN_256M:
650 gtt_entries = MB(256) - KB(size); 408 stolen_size = MB(256);
651 break; 409 break;
652 case SNB_GMCH_GMS_STOLEN_288M: 410 case SNB_GMCH_GMS_STOLEN_288M:
653 gtt_entries = MB(288) - KB(size); 411 stolen_size = MB(288);
654 break; 412 break;
655 case SNB_GMCH_GMS_STOLEN_320M: 413 case SNB_GMCH_GMS_STOLEN_320M:
656 gtt_entries = MB(320) - KB(size); 414 stolen_size = MB(320);
657 break; 415 break;
658 case SNB_GMCH_GMS_STOLEN_352M: 416 case SNB_GMCH_GMS_STOLEN_352M:
659 gtt_entries = MB(352) - KB(size); 417 stolen_size = MB(352);
660 break; 418 break;
661 case SNB_GMCH_GMS_STOLEN_384M: 419 case SNB_GMCH_GMS_STOLEN_384M:
662 gtt_entries = MB(384) - KB(size); 420 stolen_size = MB(384);
663 break; 421 break;
664 case SNB_GMCH_GMS_STOLEN_416M: 422 case SNB_GMCH_GMS_STOLEN_416M:
665 gtt_entries = MB(416) - KB(size); 423 stolen_size = MB(416);
666 break; 424 break;
667 case SNB_GMCH_GMS_STOLEN_448M: 425 case SNB_GMCH_GMS_STOLEN_448M:
668 gtt_entries = MB(448) - KB(size); 426 stolen_size = MB(448);
669 break; 427 break;
670 case SNB_GMCH_GMS_STOLEN_480M: 428 case SNB_GMCH_GMS_STOLEN_480M:
671 gtt_entries = MB(480) - KB(size); 429 stolen_size = MB(480);
672 break; 430 break;
673 case SNB_GMCH_GMS_STOLEN_512M: 431 case SNB_GMCH_GMS_STOLEN_512M:
674 gtt_entries = MB(512) - KB(size); 432 stolen_size = MB(512);
675 break; 433 break;
676 } 434 }
677 } else { 435 } else {
678 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 436 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
679 case I855_GMCH_GMS_STOLEN_1M: 437 case I855_GMCH_GMS_STOLEN_1M:
680 gtt_entries = MB(1) - KB(size); 438 stolen_size = MB(1);
681 break; 439 break;
682 case I855_GMCH_GMS_STOLEN_4M: 440 case I855_GMCH_GMS_STOLEN_4M:
683 gtt_entries = MB(4) - KB(size); 441 stolen_size = MB(4);
684 break; 442 break;
685 case I855_GMCH_GMS_STOLEN_8M: 443 case I855_GMCH_GMS_STOLEN_8M:
686 gtt_entries = MB(8) - KB(size); 444 stolen_size = MB(8);
687 break; 445 break;
688 case I855_GMCH_GMS_STOLEN_16M: 446 case I855_GMCH_GMS_STOLEN_16M:
689 gtt_entries = MB(16) - KB(size); 447 stolen_size = MB(16);
690 break; 448 break;
691 case I855_GMCH_GMS_STOLEN_32M: 449 case I855_GMCH_GMS_STOLEN_32M:
692 gtt_entries = MB(32) - KB(size); 450 stolen_size = MB(32);
693 break; 451 break;
694 case I915_GMCH_GMS_STOLEN_48M: 452 case I915_GMCH_GMS_STOLEN_48M:
695 /* Check it's really I915G */ 453 stolen_size = MB(48);
696 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
697 gtt_entries = MB(48) - KB(size);
698 else
699 gtt_entries = 0;
700 break; 454 break;
701 case I915_GMCH_GMS_STOLEN_64M: 455 case I915_GMCH_GMS_STOLEN_64M:
702 /* Check it's really I915G */ 456 stolen_size = MB(64);
703 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
704 gtt_entries = MB(64) - KB(size);
705 else
706 gtt_entries = 0;
707 break; 457 break;
708 case G33_GMCH_GMS_STOLEN_128M: 458 case G33_GMCH_GMS_STOLEN_128M:
709 if (IS_G33 || IS_I965 || IS_G4X) 459 stolen_size = MB(128);
710 gtt_entries = MB(128) - KB(size);
711 else
712 gtt_entries = 0;
713 break; 460 break;
714 case G33_GMCH_GMS_STOLEN_256M: 461 case G33_GMCH_GMS_STOLEN_256M:
715 if (IS_G33 || IS_I965 || IS_G4X) 462 stolen_size = MB(256);
716 gtt_entries = MB(256) - KB(size);
717 else
718 gtt_entries = 0;
719 break; 463 break;
720 case INTEL_GMCH_GMS_STOLEN_96M: 464 case INTEL_GMCH_GMS_STOLEN_96M:
721 if (IS_I965 || IS_G4X) 465 stolen_size = MB(96);
722 gtt_entries = MB(96) - KB(size);
723 else
724 gtt_entries = 0;
725 break; 466 break;
726 case INTEL_GMCH_GMS_STOLEN_160M: 467 case INTEL_GMCH_GMS_STOLEN_160M:
727 if (IS_I965 || IS_G4X) 468 stolen_size = MB(160);
728 gtt_entries = MB(160) - KB(size);
729 else
730 gtt_entries = 0;
731 break; 469 break;
732 case INTEL_GMCH_GMS_STOLEN_224M: 470 case INTEL_GMCH_GMS_STOLEN_224M:
733 if (IS_I965 || IS_G4X) 471 stolen_size = MB(224);
734 gtt_entries = MB(224) - KB(size);
735 else
736 gtt_entries = 0;
737 break; 472 break;
738 case INTEL_GMCH_GMS_STOLEN_352M: 473 case INTEL_GMCH_GMS_STOLEN_352M:
739 if (IS_I965 || IS_G4X) 474 stolen_size = MB(352);
740 gtt_entries = MB(352) - KB(size);
741 else
742 gtt_entries = 0;
743 break; 475 break;
744 default: 476 default:
745 gtt_entries = 0; 477 stolen_size = 0;
746 break; 478 break;
747 } 479 }
748 } 480 }
749 if (!local && gtt_entries > intel_max_stolen) { 481
750 dev_info(&agp_bridge->dev->dev, 482 if (stolen_size > 0) {
751 "detected %dK stolen memory, trimming to %dK\n", 483 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
752 gtt_entries / KB(1), intel_max_stolen / KB(1)); 484 stolen_size / KB(1), local ? "local" : "stolen");
753 gtt_entries = intel_max_stolen / KB(4);
754 } else if (gtt_entries > 0) {
755 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
756 gtt_entries / KB(1), local ? "local" : "stolen");
757 gtt_entries /= KB(4);
758 } else { 485 } else {
759 dev_info(&agp_bridge->dev->dev, 486 dev_info(&intel_private.bridge_dev->dev,
760 "no pre-allocated video memory detected\n"); 487 "no pre-allocated video memory detected\n");
761 gtt_entries = 0; 488 stolen_size = 0;
762 } 489 }
763 490
764 intel_private.gtt_entries = gtt_entries; 491 return stolen_size;
492}
493
494static void i965_adjust_pgetbl_size(unsigned int size_flag)
495{
496 u32 pgetbl_ctl, pgetbl_ctl2;
497
498 /* ensure that ppgtt is disabled */
499 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
500 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
501 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
502
503 /* write the new ggtt size */
504 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
505 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
506 pgetbl_ctl |= size_flag;
507 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
765} 508}
766 509
767static void intel_i830_fini_flush(void) 510static unsigned int i965_gtt_total_entries(void)
768{ 511{
769 kunmap(intel_private.i8xx_page); 512 int size;
770 intel_private.i8xx_flush_page = NULL; 513 u32 pgetbl_ctl;
771 unmap_page_from_agp(intel_private.i8xx_page); 514 u16 gmch_ctl;
515
516 pci_read_config_word(intel_private.bridge_dev,
517 I830_GMCH_CTRL, &gmch_ctl);
772 518
773 __free_page(intel_private.i8xx_page); 519 if (INTEL_GTT_GEN == 5) {
774 intel_private.i8xx_page = NULL; 520 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
521 case G4x_GMCH_SIZE_1M:
522 case G4x_GMCH_SIZE_VT_1M:
523 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
524 break;
525 case G4x_GMCH_SIZE_VT_1_5M:
526 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
527 break;
528 case G4x_GMCH_SIZE_2M:
529 case G4x_GMCH_SIZE_VT_2M:
530 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
531 break;
532 }
533 }
534
535 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
536
537 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
538 case I965_PGETBL_SIZE_128KB:
539 size = KB(128);
540 break;
541 case I965_PGETBL_SIZE_256KB:
542 size = KB(256);
543 break;
544 case I965_PGETBL_SIZE_512KB:
545 size = KB(512);
546 break;
547 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
548 case I965_PGETBL_SIZE_1MB:
549 size = KB(1024);
550 break;
551 case I965_PGETBL_SIZE_2MB:
552 size = KB(2048);
553 break;
554 case I965_PGETBL_SIZE_1_5MB:
555 size = KB(1024 + 512);
556 break;
557 default:
558 dev_info(&intel_private.pcidev->dev,
559 "unknown page table size, assuming 512KB\n");
560 size = KB(512);
561 }
562
563 return size/4;
775} 564}
776 565
777static void intel_i830_setup_flush(void) 566static unsigned int intel_gtt_total_entries(void)
778{ 567{
779 /* return if we've already set the flush mechanism up */ 568 int size;
780 if (intel_private.i8xx_page)
781 return;
782 569
783 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 570 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
784 if (!intel_private.i8xx_page) 571 return i965_gtt_total_entries();
785 return; 572 else if (INTEL_GTT_GEN == 6) {
573 u16 snb_gmch_ctl;
574
575 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
576 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
577 default:
578 case SNB_GTT_SIZE_0M:
579 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
580 size = MB(0);
581 break;
582 case SNB_GTT_SIZE_1M:
583 size = MB(1);
584 break;
585 case SNB_GTT_SIZE_2M:
586 size = MB(2);
587 break;
588 }
589 return size/4;
590 } else {
591 /* On previous hardware, the GTT size was just what was
592 * required to map the aperture.
593 */
594 return intel_private.base.gtt_mappable_entries;
595 }
596}
597
598static unsigned int intel_gtt_mappable_entries(void)
599{
600 unsigned int aperture_size;
601
602 if (INTEL_GTT_GEN == 1) {
603 u32 smram_miscc;
604
605 pci_read_config_dword(intel_private.bridge_dev,
606 I810_SMRAM_MISCC, &smram_miscc);
607
608 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
609 == I810_GFX_MEM_WIN_32M)
610 aperture_size = MB(32);
611 else
612 aperture_size = MB(64);
613 } else if (INTEL_GTT_GEN == 2) {
614 u16 gmch_ctrl;
615
616 pci_read_config_word(intel_private.bridge_dev,
617 I830_GMCH_CTRL, &gmch_ctrl);
618
619 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
620 aperture_size = MB(64);
621 else
622 aperture_size = MB(128);
623 } else {
624 /* 9xx supports large sizes, just look at the length */
625 aperture_size = pci_resource_len(intel_private.pcidev, 2);
626 }
627
628 return aperture_size >> PAGE_SHIFT;
629}
630
631static void intel_gtt_teardown_scratch_page(void)
632{
633 set_pages_wb(intel_private.scratch_page, 1);
634 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
635 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
636 put_page(intel_private.scratch_page);
637 __free_page(intel_private.scratch_page);
638}
639
640static void intel_gtt_cleanup(void)
641{
642 intel_private.driver->cleanup();
643
644 iounmap(intel_private.gtt);
645 iounmap(intel_private.registers);
646
647 intel_gtt_teardown_scratch_page();
648}
649
650static int intel_gtt_init(void)
651{
652 u32 gtt_map_size;
653 int ret;
654
655 ret = intel_private.driver->setup();
656 if (ret != 0)
657 return ret;
658
659 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
660 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
661
662 /* save the PGETBL reg for resume */
663 intel_private.PGETBL_save =
664 readl(intel_private.registers+I810_PGETBL_CTL)
665 & ~I810_PGETBL_ENABLED;
666 /* we only ever restore the register when enabling the PGTBL... */
667 if (HAS_PGTBL_EN)
668 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
669
670 dev_info(&intel_private.bridge_dev->dev,
671 "detected gtt size: %dK total, %dK mappable\n",
672 intel_private.base.gtt_total_entries * 4,
673 intel_private.base.gtt_mappable_entries * 4);
674
675 gtt_map_size = intel_private.base.gtt_total_entries * 4;
676
677 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
678 gtt_map_size);
679 if (!intel_private.gtt) {
680 intel_private.driver->cleanup();
681 iounmap(intel_private.registers);
682 return -ENOMEM;
683 }
684
685 global_cache_flush(); /* FIXME: ? */
786 686
787 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 687 intel_private.base.stolen_size = intel_gtt_stolen_size();
788 if (!intel_private.i8xx_flush_page) 688
789 intel_i830_fini_flush(); 689 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
690
691 ret = intel_gtt_setup_scratch_page();
692 if (ret != 0) {
693 intel_gtt_cleanup();
694 return ret;
695 }
696
697 return 0;
698}
699
700static int intel_fake_agp_fetch_size(void)
701{
702 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
703 unsigned int aper_size;
704 int i;
705
706 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
707 / MB(1);
708
709 for (i = 0; i < num_sizes; i++) {
710 if (aper_size == intel_fake_agp_sizes[i].size) {
711 agp_bridge->current_size =
712 (void *) (intel_fake_agp_sizes + i);
713 return aper_size;
714 }
715 }
716
717 return 0;
718}
719
720static void i830_cleanup(void)
721{
790} 722}
791 723
792/* The chipset_flush interface needs to get data that has already been 724/* The chipset_flush interface needs to get data that has already been
@@ -799,181 +731,234 @@ static void intel_i830_setup_flush(void)
799 * that buffer out, we just fill 1KB and clflush it out, on the assumption 731 * that buffer out, we just fill 1KB and clflush it out, on the assumption
800 * that it'll push whatever was in there out. It appears to work. 732 * that it'll push whatever was in there out. It appears to work.
801 */ 733 */
802static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 734static void i830_chipset_flush(void)
803{ 735{
804 unsigned int *pg = intel_private.i8xx_flush_page; 736 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
805 737
806 memset(pg, 0, 1024); 738 /* Forcibly evict everything from the CPU write buffers.
739 * clflush appears to be insufficient.
740 */
741 wbinvd_on_all_cpus();
807 742
808 if (cpu_has_clflush) 743 /* Now we've only seen documents for this magic bit on 855GM,
809 clflush_cache_range(pg, 1024); 744 * we hope it exists for the other gen2 chipsets...
810 else if (wbinvd_on_all_cpus() != 0) 745 *
811 printk(KERN_ERR "Timed out waiting for cache flush.\n"); 746 * Also works as advertised on my 845G.
747 */
748 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
749 intel_private.registers+I830_HIC);
750
751 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
752 if (time_after(jiffies, timeout))
753 break;
754
755 udelay(50);
756 }
812} 757}
813 758
814/* The intel i830 automatically initializes the agp aperture during POST. 759static void i830_write_entry(dma_addr_t addr, unsigned int entry,
815 * Use the memory already set aside for in the GTT. 760 unsigned int flags)
816 */
817static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
818{ 761{
819 int page_order; 762 u32 pte_flags = I810_PTE_VALID;
820 struct aper_size_info_fixed *size;
821 int num_entries;
822 u32 temp;
823 763
824 size = agp_bridge->current_size; 764 if (flags == AGP_USER_CACHED_MEMORY)
825 page_order = size->page_order; 765 pte_flags |= I830_PTE_SYSTEM_CACHED;
826 num_entries = size->num_entries;
827 agp_bridge->gatt_table_real = NULL;
828 766
829 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 767 writel(addr | pte_flags, intel_private.gtt + entry);
830 temp &= 0xfff80000; 768}
831 769
832 intel_private.registers = ioremap(temp, 128 * 4096); 770static bool intel_enable_gtt(void)
833 if (!intel_private.registers) 771{
834 return -ENOMEM; 772 u32 gma_addr;
773 u8 __iomem *reg;
835 774
836 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 775 if (INTEL_GTT_GEN <= 2)
837 global_cache_flush(); /* FIXME: ?? */ 776 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
777 &gma_addr);
778 else
779 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
780 &gma_addr);
838 781
839 /* we have to call this as early as possible after the MMIO base address is known */ 782 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
840 intel_i830_init_gtt_entries(); 783
841 if (intel_private.gtt_entries == 0) { 784 if (INTEL_GTT_GEN >= 6)
842 iounmap(intel_private.registers); 785 return true;
843 return -ENOMEM; 786
787 if (INTEL_GTT_GEN == 2) {
788 u16 gmch_ctrl;
789
790 pci_read_config_word(intel_private.bridge_dev,
791 I830_GMCH_CTRL, &gmch_ctrl);
792 gmch_ctrl |= I830_GMCH_ENABLED;
793 pci_write_config_word(intel_private.bridge_dev,
794 I830_GMCH_CTRL, gmch_ctrl);
795
796 pci_read_config_word(intel_private.bridge_dev,
797 I830_GMCH_CTRL, &gmch_ctrl);
798 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
799 dev_err(&intel_private.pcidev->dev,
800 "failed to enable the GTT: GMCH_CTRL=%x\n",
801 gmch_ctrl);
802 return false;
803 }
844 } 804 }
845 805
846 agp_bridge->gatt_table = NULL; 806 /* On the resume path we may be adjusting the PGTBL value, so
807 * be paranoid and flush all chipset write buffers...
808 */
809 if (INTEL_GTT_GEN >= 3)
810 writel(0, intel_private.registers+GFX_FLSH_CNTL);
847 811
848 agp_bridge->gatt_bus_addr = temp; 812 reg = intel_private.registers+I810_PGETBL_CTL;
813 writel(intel_private.PGETBL_save, reg);
814 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
815 dev_err(&intel_private.pcidev->dev,
816 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
817 readl(reg), intel_private.PGETBL_save);
818 return false;
819 }
849 820
850 return 0; 821 if (INTEL_GTT_GEN >= 3)
822 writel(0, intel_private.registers+GFX_FLSH_CNTL);
823
824 return true;
851} 825}
852 826
853/* Return the gatt table to a sane state. Use the top of stolen 827static int i830_setup(void)
854 * memory for the GTT.
855 */
856static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
857{ 828{
829 u32 reg_addr;
830
831 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
832 reg_addr &= 0xfff80000;
833
834 intel_private.registers = ioremap(reg_addr, KB(64));
835 if (!intel_private.registers)
836 return -ENOMEM;
837
838 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
839
858 return 0; 840 return 0;
859} 841}
860 842
861static int intel_i830_fetch_size(void) 843static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
862{ 844{
863 u16 gmch_ctrl; 845 agp_bridge->gatt_table_real = NULL;
864 struct aper_size_info_fixed *values; 846 agp_bridge->gatt_table = NULL;
847 agp_bridge->gatt_bus_addr = 0;
865 848
866 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 849 return 0;
850}
867 851
868 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 852static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
869 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 853{
870 /* 855GM/852GM/865G has 128MB aperture size */ 854 return 0;
871 agp_bridge->current_size = (void *) values; 855}
872 agp_bridge->aperture_size_idx = 0;
873 return values[0].size;
874 }
875 856
876 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 857static int intel_fake_agp_configure(void)
858{
859 if (!intel_enable_gtt())
860 return -EIO;
877 861
878 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 862 intel_private.clear_fake_agp = true;
879 agp_bridge->current_size = (void *) values; 863 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
880 agp_bridge->aperture_size_idx = 0;
881 return values[0].size;
882 } else {
883 agp_bridge->current_size = (void *) (values + 1);
884 agp_bridge->aperture_size_idx = 1;
885 return values[1].size;
886 }
887 864
888 return 0; 865 return 0;
889} 866}
890 867
891static int intel_i830_configure(void) 868static bool i830_check_flags(unsigned int flags)
892{ 869{
893 struct aper_size_info_fixed *current_size; 870 switch (flags) {
894 u32 temp; 871 case 0:
895 u16 gmch_ctrl; 872 case AGP_PHYS_MEMORY:
896 int i; 873 case AGP_USER_CACHED_MEMORY:
897 874 case AGP_USER_MEMORY:
898 current_size = A_SIZE_FIX(agp_bridge->current_size); 875 return true;
876 }
899 877
900 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 878 return false;
901 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 879}
902 880
903 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); 881void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
904 gmch_ctrl |= I830_GMCH_ENABLED; 882 unsigned int sg_len,
905 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); 883 unsigned int pg_start,
884 unsigned int flags)
885{
886 struct scatterlist *sg;
887 unsigned int len, m;
888 int i, j;
906 889
907 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 890 j = pg_start;
908 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
909 891
910 if (agp_bridge->driver->needs_scratch_page) { 892 /* sg may merge pages, but we have to separate
911 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { 893 * per-page addr for GTT */
912 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 894 for_each_sg(sg_list, sg, sg_len, i) {
895 len = sg_dma_len(sg) >> PAGE_SHIFT;
896 for (m = 0; m < len; m++) {
897 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
898 intel_private.driver->write_entry(addr,
899 j, flags);
900 j++;
913 } 901 }
914 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
915 } 902 }
916 903 readl(intel_private.gtt+j-1);
917 global_cache_flush();
918
919 intel_i830_setup_flush();
920 return 0;
921} 904}
905EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
922 906
923static void intel_i830_cleanup(void) 907void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
908 struct page **pages, unsigned int flags)
924{ 909{
925 iounmap(intel_private.registers); 910 int i, j;
911
912 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
913 dma_addr_t addr = page_to_phys(pages[i]);
914 intel_private.driver->write_entry(addr,
915 j, flags);
916 }
917 readl(intel_private.gtt+j-1);
926} 918}
919EXPORT_SYMBOL(intel_gtt_insert_pages);
927 920
928static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 921static int intel_fake_agp_insert_entries(struct agp_memory *mem,
929 int type) 922 off_t pg_start, int type)
930{ 923{
931 int i, j, num_entries;
932 void *temp;
933 int ret = -EINVAL; 924 int ret = -EINVAL;
934 int mask_type;
935 925
936 if (mem->page_count == 0) 926 if (intel_private.clear_fake_agp) {
937 goto out; 927 int start = intel_private.base.stolen_size / PAGE_SIZE;
938 928 int end = intel_private.base.gtt_mappable_entries;
939 temp = agp_bridge->current_size; 929 intel_gtt_clear_range(start, end - start);
940 num_entries = A_SIZE_FIX(temp)->num_entries; 930 intel_private.clear_fake_agp = false;
931 }
941 932
942 if (pg_start < intel_private.gtt_entries) { 933 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
943 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 934 return i810_insert_dcache_entries(mem, pg_start, type);
944 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
945 pg_start, intel_private.gtt_entries);
946 935
947 dev_info(&intel_private.pcidev->dev, 936 if (mem->page_count == 0)
948 "trying to insert into local/stolen memory\n"); 937 goto out;
949 goto out_err;
950 }
951 938
952 if ((pg_start + mem->page_count) > num_entries) 939 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
953 goto out_err; 940 goto out_err;
954 941
955 /* The i830 can't check the GTT for entries since its read only,
956 * depend on the caller to make the correct offset decisions.
957 */
958
959 if (type != mem->type) 942 if (type != mem->type)
960 goto out_err; 943 goto out_err;
961 944
962 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 945 if (!intel_private.driver->check_flags(type))
963
964 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
965 mask_type != INTEL_AGP_CACHED_MEMORY)
966 goto out_err; 946 goto out_err;
967 947
968 if (!mem->is_flushed) 948 if (!mem->is_flushed)
969 global_cache_flush(); 949 global_cache_flush();
970 950
971 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 951 if (intel_private.base.needs_dmar) {
972 writel(agp_bridge->driver->mask_memory(agp_bridge, 952 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
973 page_to_phys(mem->pages[i]), mask_type), 953 &mem->sg_list, &mem->num_sg);
974 intel_private.registers+I810_PTE_BASE+(j*4)); 954 if (ret != 0)
975 } 955 return ret;
976 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 956
957 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
958 pg_start, type);
959 } else
960 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
961 type);
977 962
978out: 963out:
979 ret = 0; 964 ret = 0;
@@ -982,30 +967,54 @@ out_err:
982 return ret; 967 return ret;
983} 968}
984 969
985static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 970void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
986 int type)
987{ 971{
988 int i; 972 unsigned int i;
973
974 for (i = first_entry; i < (first_entry + num_entries); i++) {
975 intel_private.driver->write_entry(intel_private.scratch_page_dma,
976 i, 0);
977 }
978 readl(intel_private.gtt+i-1);
979}
980EXPORT_SYMBOL(intel_gtt_clear_range);
989 981
982static int intel_fake_agp_remove_entries(struct agp_memory *mem,
983 off_t pg_start, int type)
984{
990 if (mem->page_count == 0) 985 if (mem->page_count == 0)
991 return 0; 986 return 0;
992 987
993 if (pg_start < intel_private.gtt_entries) { 988 intel_gtt_clear_range(pg_start, mem->page_count);
994 dev_info(&intel_private.pcidev->dev,
995 "trying to disable local/stolen memory\n");
996 return -EINVAL;
997 }
998 989
999 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 990 if (intel_private.base.needs_dmar) {
1000 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 991 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
992 mem->sg_list = NULL;
993 mem->num_sg = 0;
1001 } 994 }
1002 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1003 995
1004 return 0; 996 return 0;
1005} 997}
1006 998
1007static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) 999static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1000 int type)
1008{ 1001{
1002 struct agp_memory *new;
1003
1004 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1005 if (pg_count != intel_private.num_dcache_entries)
1006 return NULL;
1007
1008 new = agp_create_memory(1);
1009 if (new == NULL)
1010 return NULL;
1011
1012 new->type = AGP_DCACHE_MEMORY;
1013 new->page_count = pg_count;
1014 new->num_scratch_pages = 0;
1015 agp_free_page_array(new);
1016 return new;
1017 }
1009 if (type == AGP_PHYS_MEMORY) 1018 if (type == AGP_PHYS_MEMORY)
1010 return alloc_agpphysmem_i8xx(pg_count, type); 1019 return alloc_agpphysmem_i8xx(pg_count, type);
1011 /* always return NULL for other allocation types for now */ 1020 /* always return NULL for other allocation types for now */
@@ -1015,9 +1024,9 @@ static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1015static int intel_alloc_chipset_flush_resource(void) 1024static int intel_alloc_chipset_flush_resource(void)
1016{ 1025{
1017 int ret; 1026 int ret;
1018 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1027 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1019 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1028 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1020 pcibios_align_resource, agp_bridge->dev); 1029 pcibios_align_resource, intel_private.bridge_dev);
1021 1030
1022 return ret; 1031 return ret;
1023} 1032}
@@ -1027,11 +1036,11 @@ static void intel_i915_setup_chipset_flush(void)
1027 int ret; 1036 int ret;
1028 u32 temp; 1037 u32 temp;
1029 1038
1030 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); 1039 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1031 if (!(temp & 0x1)) { 1040 if (!(temp & 0x1)) {
1032 intel_alloc_chipset_flush_resource(); 1041 intel_alloc_chipset_flush_resource();
1033 intel_private.resource_valid = 1; 1042 intel_private.resource_valid = 1;
1034 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1043 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1035 } else { 1044 } else {
1036 temp &= ~1; 1045 temp &= ~1;
1037 1046
@@ -1050,17 +1059,17 @@ static void intel_i965_g33_setup_chipset_flush(void)
1050 u32 temp_hi, temp_lo; 1059 u32 temp_hi, temp_lo;
1051 int ret; 1060 int ret;
1052 1061
1053 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); 1062 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1054 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); 1063 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1055 1064
1056 if (!(temp_lo & 0x1)) { 1065 if (!(temp_lo & 0x1)) {
1057 1066
1058 intel_alloc_chipset_flush_resource(); 1067 intel_alloc_chipset_flush_resource();
1059 1068
1060 intel_private.resource_valid = 1; 1069 intel_private.resource_valid = 1;
1061 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, 1070 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1062 upper_32_bits(intel_private.ifp_resource.start)); 1071 upper_32_bits(intel_private.ifp_resource.start));
1063 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1072 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1064 } else { 1073 } else {
1065 u64 l64; 1074 u64 l64;
1066 1075
@@ -1083,7 +1092,7 @@ static void intel_i9xx_setup_flush(void)
1083 if (intel_private.ifp_resource.start) 1092 if (intel_private.ifp_resource.start)
1084 return; 1093 return;
1085 1094
1086 if (IS_SNB) 1095 if (INTEL_GTT_GEN == 6)
1087 return; 1096 return;
1088 1097
1089 /* setup a resource for this object */ 1098 /* setup a resource for this object */
@@ -1091,7 +1100,7 @@ static void intel_i9xx_setup_flush(void)
1091 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1100 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1092 1101
1093 /* Setup chipset flush for 915 */ 1102 /* Setup chipset flush for 915 */
1094 if (IS_I965 || IS_G33 || IS_G4X) { 1103 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1095 intel_i965_g33_setup_chipset_flush(); 1104 intel_i965_g33_setup_chipset_flush();
1096 } else { 1105 } else {
1097 intel_i915_setup_chipset_flush(); 1106 intel_i915_setup_chipset_flush();
@@ -1104,41 +1113,7 @@ static void intel_i9xx_setup_flush(void)
1104 "can't ioremap flush page - no chipset flushing\n"); 1113 "can't ioremap flush page - no chipset flushing\n");
1105} 1114}
1106 1115
1107static int intel_i9xx_configure(void) 1116static void i9xx_cleanup(void)
1108{
1109 struct aper_size_info_fixed *current_size;
1110 u32 temp;
1111 u16 gmch_ctrl;
1112 int i;
1113
1114 current_size = A_SIZE_FIX(agp_bridge->current_size);
1115
1116 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1117
1118 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1119
1120 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1121 gmch_ctrl |= I830_GMCH_ENABLED;
1122 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1123
1124 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1125 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1126
1127 if (agp_bridge->driver->needs_scratch_page) {
1128 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1129 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1130 }
1131 readl(intel_private.gtt+i-1); /* PCI Posting. */
1132 }
1133
1134 global_cache_flush();
1135
1136 intel_i9xx_setup_flush();
1137
1138 return 0;
1139}
1140
1141static void intel_i915_cleanup(void)
1142{ 1117{
1143 if (intel_private.i9xx_flush_page) 1118 if (intel_private.i9xx_flush_page)
1144 iounmap(intel_private.i9xx_flush_page); 1119 iounmap(intel_private.i9xx_flush_page);
@@ -1146,505 +1121,399 @@ static void intel_i915_cleanup(void)
1146 release_resource(&intel_private.ifp_resource); 1121 release_resource(&intel_private.ifp_resource);
1147 intel_private.ifp_resource.start = 0; 1122 intel_private.ifp_resource.start = 0;
1148 intel_private.resource_valid = 0; 1123 intel_private.resource_valid = 0;
1149 iounmap(intel_private.gtt);
1150 iounmap(intel_private.registers);
1151} 1124}
1152 1125
1153static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1126static void i9xx_chipset_flush(void)
1154{ 1127{
1155 if (intel_private.i9xx_flush_page) 1128 if (intel_private.i9xx_flush_page)
1156 writel(1, intel_private.i9xx_flush_page); 1129 writel(1, intel_private.i9xx_flush_page);
1157} 1130}
1158 1131
1159static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1132static void i965_write_entry(dma_addr_t addr,
1160 int type) 1133 unsigned int entry,
1134 unsigned int flags)
1161{ 1135{
1162 int num_entries; 1136 u32 pte_flags;
1163 void *temp;
1164 int ret = -EINVAL;
1165 int mask_type;
1166
1167 if (mem->page_count == 0)
1168 goto out;
1169
1170 temp = agp_bridge->current_size;
1171 num_entries = A_SIZE_FIX(temp)->num_entries;
1172
1173 if (pg_start < intel_private.gtt_entries) {
1174 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1175 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1176 pg_start, intel_private.gtt_entries);
1177
1178 dev_info(&intel_private.pcidev->dev,
1179 "trying to insert into local/stolen memory\n");
1180 goto out_err;
1181 }
1182
1183 if ((pg_start + mem->page_count) > num_entries)
1184 goto out_err;
1185
1186 /* The i915 can't check the GTT for entries since it's read only;
1187 * depend on the caller to make the correct offset decisions.
1188 */
1189
1190 if (type != mem->type)
1191 goto out_err;
1192
1193 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1194
1195 if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1196 mask_type != INTEL_AGP_CACHED_MEMORY)
1197 goto out_err;
1198 1137
1199 if (!mem->is_flushed) 1138 pte_flags = I810_PTE_VALID;
1200 global_cache_flush(); 1139 if (flags == AGP_USER_CACHED_MEMORY)
1140 pte_flags |= I830_PTE_SYSTEM_CACHED;
1201 1141
1202 intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1142 /* Shift high bits down */
1203 1143 addr |= (addr >> 28) & 0xf0;
1204 out: 1144 writel(addr | pte_flags, intel_private.gtt + entry);
1205 ret = 0;
1206 out_err:
1207 mem->is_flushed = true;
1208 return ret;
1209} 1145}
1210 1146
1211static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1147static bool gen6_check_flags(unsigned int flags)
1212 int type)
1213{ 1148{
1214 int i; 1149 return true;
1215
1216 if (mem->page_count == 0)
1217 return 0;
1218
1219 if (pg_start < intel_private.gtt_entries) {
1220 dev_info(&intel_private.pcidev->dev,
1221 "trying to disable local/stolen memory\n");
1222 return -EINVAL;
1223 }
1224
1225 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1226 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1227
1228 readl(intel_private.gtt+i-1);
1229
1230 return 0;
1231} 1150}
1232 1151
1233/* Return the aperture size by just checking the resource length. The effect 1152static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1234 * described in the spec of the MSAC registers is just changing of the 1153 unsigned int flags)
1235 * resource size.
1236 */
1237static int intel_i9xx_fetch_size(void)
1238{ 1154{
1239 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 1155 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1240 int aper_size; /* size in megabytes */ 1156 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1241 int i; 1157 u32 pte_flags;
1242 1158
1243 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); 1159 if (type_mask == AGP_USER_MEMORY)
1244 1160 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1245 for (i = 0; i < num_sizes; i++) { 1161 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1246 if (aper_size == intel_i830_sizes[i].size) { 1162 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1247 agp_bridge->current_size = intel_i830_sizes + i; 1163 if (gfdt)
1248 return aper_size; 1164 pte_flags |= GEN6_PTE_GFDT;
1249 } 1165 } else { /* set 'normal'/'cached' to LLC by default */
1166 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1167 if (gfdt)
1168 pte_flags |= GEN6_PTE_GFDT;
1250 } 1169 }
1251 1170
1252 return 0; 1171 /* gen6 has bit11-4 for physical addr bit39-32 */
1172 addr |= (addr >> 28) & 0xff0;
1173 writel(addr | pte_flags, intel_private.gtt + entry);
1253} 1174}
1254 1175
1255static int intel_i915_get_gtt_size(void) 1176static void gen6_cleanup(void)
1256{ 1177{
1257 int size;
1258
1259 if (IS_G33) {
1260 u16 gmch_ctrl;
1261
1262 /* G33's GTT size defined in gmch_ctrl */
1263 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1264 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
1265 case I830_GMCH_GMS_STOLEN_512:
1266 size = 512;
1267 break;
1268 case I830_GMCH_GMS_STOLEN_1024:
1269 size = 1024;
1270 break;
1271 case I830_GMCH_GMS_STOLEN_8192:
1272 size = 8*1024;
1273 break;
1274 default:
1275 dev_info(&agp_bridge->dev->dev,
1276 "unknown page table size 0x%x, assuming 512KB\n",
1277 (gmch_ctrl & I830_GMCH_GMS_MASK));
1278 size = 512;
1279 }
1280 } else {
1281 /* On previous hardware, the GTT size was just what was
1282 * required to map the aperture.
1283 */
1284 size = agp_bridge->driver->fetch_size();
1285 }
1286
1287 return KB(size);
1288} 1178}
1289 1179
1290/* The intel i915 automatically initializes the agp aperture during POST. 1180static int i9xx_setup(void)
1291 * Use the memory already set aside for in the GTT.
1292 */
1293static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1294{ 1181{
1295 int page_order; 1182 u32 reg_addr;
1296 struct aper_size_info_fixed *size;
1297 int num_entries;
1298 u32 temp, temp2;
1299 int gtt_map_size;
1300
1301 size = agp_bridge->current_size;
1302 page_order = size->page_order;
1303 num_entries = size->num_entries;
1304 agp_bridge->gatt_table_real = NULL;
1305 1183
1306 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); 1184 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1307 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1308 1185
1309 gtt_map_size = intel_i915_get_gtt_size(); 1186 reg_addr &= 0xfff80000;
1310 1187
1311 intel_private.gtt = ioremap(temp2, gtt_map_size); 1188 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1312 if (!intel_private.gtt) 1189 if (!intel_private.registers)
1313 return -ENOMEM; 1190 return -ENOMEM;
1314 1191
1315 intel_private.gtt_total_size = gtt_map_size / 4; 1192 if (INTEL_GTT_GEN == 3) {
1193 u32 gtt_addr;
1316 1194
1317 temp &= 0xfff80000; 1195 pci_read_config_dword(intel_private.pcidev,
1318 1196 I915_PTEADDR, &gtt_addr);
1319 intel_private.registers = ioremap(temp, 128 * 4096); 1197 intel_private.gtt_bus_addr = gtt_addr;
1320 if (!intel_private.registers) { 1198 } else {
1321 iounmap(intel_private.gtt); 1199 u32 gtt_offset;
1322 return -ENOMEM;
1323 }
1324
1325 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1326 global_cache_flush(); /* FIXME: ? */
1327 1200
1328 /* we have to call this as early as possible after the MMIO base address is known */ 1201 switch (INTEL_GTT_GEN) {
1329 intel_i830_init_gtt_entries(); 1202 case 5:
1330 if (intel_private.gtt_entries == 0) { 1203 case 6:
1331 iounmap(intel_private.gtt); 1204 gtt_offset = MB(2);
1332 iounmap(intel_private.registers); 1205 break;
1333 return -ENOMEM; 1206 case 4:
1207 default:
1208 gtt_offset = KB(512);
1209 break;
1210 }
1211 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1334 } 1212 }
1335 1213
1336 agp_bridge->gatt_table = NULL; 1214 intel_i9xx_setup_flush();
1337
1338 agp_bridge->gatt_bus_addr = temp;
1339 1215
1340 return 0; 1216 return 0;
1341} 1217}
1342 1218
1343/* 1219static const struct agp_bridge_driver intel_fake_agp_driver = {
1344 * The i965 supports 36-bit physical addresses, but to keep 1220 .owner = THIS_MODULE,
1345 * the format of the GTT the same, the bits that don't fit 1221 .size_type = FIXED_APER_SIZE,
1346 * in a 32-bit word are shifted down to bits 4..7. 1222 .aperture_sizes = intel_fake_agp_sizes,
1347 * 1223 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1348 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1224 .configure = intel_fake_agp_configure,
1349 * is always zero on 32-bit architectures, so no need to make 1225 .fetch_size = intel_fake_agp_fetch_size,
1350 * this conditional. 1226 .cleanup = intel_gtt_cleanup,
1227 .agp_enable = intel_fake_agp_enable,
1228 .cache_flush = global_cache_flush,
1229 .create_gatt_table = intel_fake_agp_create_gatt_table,
1230 .free_gatt_table = intel_fake_agp_free_gatt_table,
1231 .insert_memory = intel_fake_agp_insert_entries,
1232 .remove_memory = intel_fake_agp_remove_entries,
1233 .alloc_by_type = intel_fake_agp_alloc_by_type,
1234 .free_by_type = intel_i810_free_by_type,
1235 .agp_alloc_page = agp_generic_alloc_page,
1236 .agp_alloc_pages = agp_generic_alloc_pages,
1237 .agp_destroy_page = agp_generic_destroy_page,
1238 .agp_destroy_pages = agp_generic_destroy_pages,
1239};
1240
1241static const struct intel_gtt_driver i81x_gtt_driver = {
1242 .gen = 1,
1243 .has_pgtbl_enable = 1,
1244 .dma_mask_size = 32,
1245 .setup = i810_setup,
1246 .cleanup = i810_cleanup,
1247 .check_flags = i830_check_flags,
1248 .write_entry = i810_write_entry,
1249};
1250static const struct intel_gtt_driver i8xx_gtt_driver = {
1251 .gen = 2,
1252 .has_pgtbl_enable = 1,
1253 .setup = i830_setup,
1254 .cleanup = i830_cleanup,
1255 .write_entry = i830_write_entry,
1256 .dma_mask_size = 32,
1257 .check_flags = i830_check_flags,
1258 .chipset_flush = i830_chipset_flush,
1259};
1260static const struct intel_gtt_driver i915_gtt_driver = {
1261 .gen = 3,
1262 .has_pgtbl_enable = 1,
1263 .setup = i9xx_setup,
1264 .cleanup = i9xx_cleanup,
1265 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1266 .write_entry = i830_write_entry,
1267 .dma_mask_size = 32,
1268 .check_flags = i830_check_flags,
1269 .chipset_flush = i9xx_chipset_flush,
1270};
1271static const struct intel_gtt_driver g33_gtt_driver = {
1272 .gen = 3,
1273 .is_g33 = 1,
1274 .setup = i9xx_setup,
1275 .cleanup = i9xx_cleanup,
1276 .write_entry = i965_write_entry,
1277 .dma_mask_size = 36,
1278 .check_flags = i830_check_flags,
1279 .chipset_flush = i9xx_chipset_flush,
1280};
1281static const struct intel_gtt_driver pineview_gtt_driver = {
1282 .gen = 3,
1283 .is_pineview = 1, .is_g33 = 1,
1284 .setup = i9xx_setup,
1285 .cleanup = i9xx_cleanup,
1286 .write_entry = i965_write_entry,
1287 .dma_mask_size = 36,
1288 .check_flags = i830_check_flags,
1289 .chipset_flush = i9xx_chipset_flush,
1290};
1291static const struct intel_gtt_driver i965_gtt_driver = {
1292 .gen = 4,
1293 .has_pgtbl_enable = 1,
1294 .setup = i9xx_setup,
1295 .cleanup = i9xx_cleanup,
1296 .write_entry = i965_write_entry,
1297 .dma_mask_size = 36,
1298 .check_flags = i830_check_flags,
1299 .chipset_flush = i9xx_chipset_flush,
1300};
1301static const struct intel_gtt_driver g4x_gtt_driver = {
1302 .gen = 5,
1303 .setup = i9xx_setup,
1304 .cleanup = i9xx_cleanup,
1305 .write_entry = i965_write_entry,
1306 .dma_mask_size = 36,
1307 .check_flags = i830_check_flags,
1308 .chipset_flush = i9xx_chipset_flush,
1309};
1310static const struct intel_gtt_driver ironlake_gtt_driver = {
1311 .gen = 5,
1312 .is_ironlake = 1,
1313 .setup = i9xx_setup,
1314 .cleanup = i9xx_cleanup,
1315 .write_entry = i965_write_entry,
1316 .dma_mask_size = 36,
1317 .check_flags = i830_check_flags,
1318 .chipset_flush = i9xx_chipset_flush,
1319};
1320static const struct intel_gtt_driver sandybridge_gtt_driver = {
1321 .gen = 6,
1322 .setup = i9xx_setup,
1323 .cleanup = gen6_cleanup,
1324 .write_entry = gen6_write_entry,
1325 .dma_mask_size = 40,
1326 .check_flags = gen6_check_flags,
1327 .chipset_flush = i9xx_chipset_flush,
1328};
1329
1330/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1331 * driver and gmch_driver must be non-null, and find_gmch will determine
1332 * which one should be used if a gmch_chip_id is present.
1351 */ 1333 */
1352static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1334static const struct intel_gtt_driver_description {
1353 dma_addr_t addr, int type) 1335 unsigned int gmch_chip_id;
1336 char *name;
1337 const struct intel_gtt_driver *gtt_driver;
1338} intel_gtt_chipsets[] = {
1339 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1340 &i81x_gtt_driver},
1341 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1342 &i81x_gtt_driver},
1343 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1344 &i81x_gtt_driver},
1345 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1346 &i81x_gtt_driver},
1347 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1348 &i8xx_gtt_driver},
1349 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1350 &i8xx_gtt_driver},
1351 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1352 &i8xx_gtt_driver},
1353 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1354 &i8xx_gtt_driver},
1355 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1356 &i8xx_gtt_driver},
1357 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1358 &i915_gtt_driver },
1359 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1360 &i915_gtt_driver },
1361 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1362 &i915_gtt_driver },
1363 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1364 &i915_gtt_driver },
1365 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1366 &i915_gtt_driver },
1367 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1368 &i915_gtt_driver },
1369 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1370 &i965_gtt_driver },
1371 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1372 &i965_gtt_driver },
1373 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1374 &i965_gtt_driver },
1375 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1376 &i965_gtt_driver },
1377 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1378 &i965_gtt_driver },
1379 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1380 &i965_gtt_driver },
1381 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1382 &g33_gtt_driver },
1383 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1384 &g33_gtt_driver },
1385 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1386 &g33_gtt_driver },
1387 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1388 &pineview_gtt_driver },
1389 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1390 &pineview_gtt_driver },
1391 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1392 &g4x_gtt_driver },
1393 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1394 &g4x_gtt_driver },
1395 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1396 &g4x_gtt_driver },
1397 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1398 &g4x_gtt_driver },
1399 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1400 &g4x_gtt_driver },
1401 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1402 &g4x_gtt_driver },
1403 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1404 &g4x_gtt_driver },
1405 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1406 "HD Graphics", &ironlake_gtt_driver },
1407 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1408 "HD Graphics", &ironlake_gtt_driver },
1409 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1410 "Sandybridge", &sandybridge_gtt_driver },
1411 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1412 "Sandybridge", &sandybridge_gtt_driver },
1413 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1414 "Sandybridge", &sandybridge_gtt_driver },
1415 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1416 "Sandybridge", &sandybridge_gtt_driver },
1417 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1418 "Sandybridge", &sandybridge_gtt_driver },
1419 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1420 "Sandybridge", &sandybridge_gtt_driver },
1421 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1422 "Sandybridge", &sandybridge_gtt_driver },
1423 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1424 "Ivybridge", &sandybridge_gtt_driver },
1425 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1426 "Ivybridge", &sandybridge_gtt_driver },
1427 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1428 "Ivybridge", &sandybridge_gtt_driver },
1429 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1430 "Ivybridge", &sandybridge_gtt_driver },
1431 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1432 "Ivybridge", &sandybridge_gtt_driver },
1433 { 0, NULL, NULL }
1434};
1435
1436static int find_gmch(u16 device)
1354{ 1437{
1355 /* Shift high bits down */ 1438 struct pci_dev *gmch_device;
1356 addr |= (addr >> 28) & 0xf0;
1357 1439
1358 /* Type checking must be done elsewhere */ 1440 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1359 return addr | bridge->driver->masks[type].mask; 1441 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1360} 1442 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1443 device, gmch_device);
1444 }
1361 1445
1362static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, 1446 if (!gmch_device)
1363 dma_addr_t addr, int type) 1447 return 0;
1364{
1365 /* gen6 has bit11-4 for physical addr bit39-32 */
1366 addr |= (addr >> 28) & 0xff0;
1367 1448
1368 /* Type checking must be done elsewhere */ 1449 intel_private.pcidev = gmch_device;
1369 return addr | bridge->driver->masks[type].mask; 1450 return 1;
1370} 1451}
1371 1452
1372static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 1453int intel_gmch_probe(struct pci_dev *pdev,
1454 struct agp_bridge_data *bridge)
1373{ 1455{
1374 u16 snb_gmch_ctl; 1456 int i, mask;
1375 1457 intel_private.driver = NULL;
1376 switch (agp_bridge->dev->device) {
1377 case PCI_DEVICE_ID_INTEL_GM45_HB:
1378 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1379 case PCI_DEVICE_ID_INTEL_Q45_HB:
1380 case PCI_DEVICE_ID_INTEL_G45_HB:
1381 case PCI_DEVICE_ID_INTEL_G41_HB:
1382 case PCI_DEVICE_ID_INTEL_B43_HB:
1383 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1384 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1385 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1386 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1387 *gtt_offset = *gtt_size = MB(2);
1388 break;
1389 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1390 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1391 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
1392 *gtt_offset = MB(2);
1393 1458
1394 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 1459 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1395 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 1460 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1396 default: 1461 intel_private.driver =
1397 case SNB_GTT_SIZE_0M: 1462 intel_gtt_chipsets[i].gtt_driver;
1398 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1399 *gtt_size = MB(0);
1400 break;
1401 case SNB_GTT_SIZE_1M:
1402 *gtt_size = MB(1);
1403 break;
1404 case SNB_GTT_SIZE_2M:
1405 *gtt_size = MB(2);
1406 break; 1463 break;
1407 } 1464 }
1408 break;
1409 default:
1410 *gtt_offset = *gtt_size = KB(512);
1411 } 1465 }
1412}
1413
1414/* The intel i965 automatically initializes the agp aperture during POST.
1415 * Use the memory already set aside for in the GTT.
1416 */
1417static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1418{
1419 int page_order;
1420 struct aper_size_info_fixed *size;
1421 int num_entries;
1422 u32 temp;
1423 int gtt_offset, gtt_size;
1424
1425 size = agp_bridge->current_size;
1426 page_order = size->page_order;
1427 num_entries = size->num_entries;
1428 agp_bridge->gatt_table_real = NULL;
1429
1430 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1431 1466
1432 temp &= 0xfff00000; 1467 if (!intel_private.driver)
1433 1468 return 0;
1434 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1435
1436 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1437 1469
1438 if (!intel_private.gtt) 1470 bridge->driver = &intel_fake_agp_driver;
1439 return -ENOMEM; 1471 bridge->dev_private_data = &intel_private;
1472 bridge->dev = pdev;
1440 1473
1441 intel_private.gtt_total_size = gtt_size / 4; 1474 intel_private.bridge_dev = pci_dev_get(pdev);
1442 1475
1443 intel_private.registers = ioremap(temp, 128 * 4096); 1476 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1444 if (!intel_private.registers) {
1445 iounmap(intel_private.gtt);
1446 return -ENOMEM;
1447 }
1448 1477
1449 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 1478 mask = intel_private.driver->dma_mask_size;
1450 global_cache_flush(); /* FIXME: ? */ 1479 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1451 1480 dev_err(&intel_private.pcidev->dev,
1452 /* we have to call this as early as possible after the MMIO base address is known */ 1481 "set gfx device dma mask %d-bit failed!\n", mask);
1453 intel_i830_init_gtt_entries(); 1482 else
1454 if (intel_private.gtt_entries == 0) { 1483 pci_set_consistent_dma_mask(intel_private.pcidev,
1455 iounmap(intel_private.gtt); 1484 DMA_BIT_MASK(mask));
1456 iounmap(intel_private.registers);
1457 return -ENOMEM;
1458 }
1459 1485
1460 agp_bridge->gatt_table = NULL; 1486 /*if (bridge->driver == &intel_810_driver)
1487 return 1;*/
1461 1488
1462 agp_bridge->gatt_bus_addr = temp; 1489 if (intel_gtt_init() != 0)
1490 return 0;
1463 1491
1464 return 0; 1492 return 1;
1465} 1493}
1494EXPORT_SYMBOL(intel_gmch_probe);
1466 1495
1467static const struct agp_bridge_driver intel_810_driver = { 1496const struct intel_gtt *intel_gtt_get(void)
1468 .owner = THIS_MODULE, 1497{
1469 .aperture_sizes = intel_i810_sizes, 1498 return &intel_private.base;
1470 .size_type = FIXED_APER_SIZE, 1499}
1471 .num_aperture_sizes = 2, 1500EXPORT_SYMBOL(intel_gtt_get);
1472 .needs_scratch_page = true,
1473 .configure = intel_i810_configure,
1474 .fetch_size = intel_i810_fetch_size,
1475 .cleanup = intel_i810_cleanup,
1476 .mask_memory = intel_i810_mask_memory,
1477 .masks = intel_i810_masks,
1478 .agp_enable = intel_i810_agp_enable,
1479 .cache_flush = global_cache_flush,
1480 .create_gatt_table = agp_generic_create_gatt_table,
1481 .free_gatt_table = agp_generic_free_gatt_table,
1482 .insert_memory = intel_i810_insert_entries,
1483 .remove_memory = intel_i810_remove_entries,
1484 .alloc_by_type = intel_i810_alloc_by_type,
1485 .free_by_type = intel_i810_free_by_type,
1486 .agp_alloc_page = agp_generic_alloc_page,
1487 .agp_alloc_pages = agp_generic_alloc_pages,
1488 .agp_destroy_page = agp_generic_destroy_page,
1489 .agp_destroy_pages = agp_generic_destroy_pages,
1490 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1491};
1492
1493static const struct agp_bridge_driver intel_830_driver = {
1494 .owner = THIS_MODULE,
1495 .aperture_sizes = intel_i830_sizes,
1496 .size_type = FIXED_APER_SIZE,
1497 .num_aperture_sizes = 4,
1498 .needs_scratch_page = true,
1499 .configure = intel_i830_configure,
1500 .fetch_size = intel_i830_fetch_size,
1501 .cleanup = intel_i830_cleanup,
1502 .mask_memory = intel_i810_mask_memory,
1503 .masks = intel_i810_masks,
1504 .agp_enable = intel_i810_agp_enable,
1505 .cache_flush = global_cache_flush,
1506 .create_gatt_table = intel_i830_create_gatt_table,
1507 .free_gatt_table = intel_i830_free_gatt_table,
1508 .insert_memory = intel_i830_insert_entries,
1509 .remove_memory = intel_i830_remove_entries,
1510 .alloc_by_type = intel_i830_alloc_by_type,
1511 .free_by_type = intel_i810_free_by_type,
1512 .agp_alloc_page = agp_generic_alloc_page,
1513 .agp_alloc_pages = agp_generic_alloc_pages,
1514 .agp_destroy_page = agp_generic_destroy_page,
1515 .agp_destroy_pages = agp_generic_destroy_pages,
1516 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1517 .chipset_flush = intel_i830_chipset_flush,
1518};
1519
1520static const struct agp_bridge_driver intel_915_driver = {
1521 .owner = THIS_MODULE,
1522 .aperture_sizes = intel_i830_sizes,
1523 .size_type = FIXED_APER_SIZE,
1524 .num_aperture_sizes = 4,
1525 .needs_scratch_page = true,
1526 .configure = intel_i9xx_configure,
1527 .fetch_size = intel_i9xx_fetch_size,
1528 .cleanup = intel_i915_cleanup,
1529 .mask_memory = intel_i810_mask_memory,
1530 .masks = intel_i810_masks,
1531 .agp_enable = intel_i810_agp_enable,
1532 .cache_flush = global_cache_flush,
1533 .create_gatt_table = intel_i915_create_gatt_table,
1534 .free_gatt_table = intel_i830_free_gatt_table,
1535 .insert_memory = intel_i915_insert_entries,
1536 .remove_memory = intel_i915_remove_entries,
1537 .alloc_by_type = intel_i830_alloc_by_type,
1538 .free_by_type = intel_i810_free_by_type,
1539 .agp_alloc_page = agp_generic_alloc_page,
1540 .agp_alloc_pages = agp_generic_alloc_pages,
1541 .agp_destroy_page = agp_generic_destroy_page,
1542 .agp_destroy_pages = agp_generic_destroy_pages,
1543 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1544 .chipset_flush = intel_i915_chipset_flush,
1545#ifdef USE_PCI_DMA_API
1546 .agp_map_page = intel_agp_map_page,
1547 .agp_unmap_page = intel_agp_unmap_page,
1548 .agp_map_memory = intel_agp_map_memory,
1549 .agp_unmap_memory = intel_agp_unmap_memory,
1550#endif
1551};
1552 1501
1553static const struct agp_bridge_driver intel_i965_driver = { 1502void intel_gtt_chipset_flush(void)
1554 .owner = THIS_MODULE, 1503{
1555 .aperture_sizes = intel_i830_sizes, 1504 if (intel_private.driver->chipset_flush)
1556 .size_type = FIXED_APER_SIZE, 1505 intel_private.driver->chipset_flush();
1557 .num_aperture_sizes = 4, 1506}
1558 .needs_scratch_page = true, 1507EXPORT_SYMBOL(intel_gtt_chipset_flush);
1559 .configure = intel_i9xx_configure,
1560 .fetch_size = intel_i9xx_fetch_size,
1561 .cleanup = intel_i915_cleanup,
1562 .mask_memory = intel_i965_mask_memory,
1563 .masks = intel_i810_masks,
1564 .agp_enable = intel_i810_agp_enable,
1565 .cache_flush = global_cache_flush,
1566 .create_gatt_table = intel_i965_create_gatt_table,
1567 .free_gatt_table = intel_i830_free_gatt_table,
1568 .insert_memory = intel_i915_insert_entries,
1569 .remove_memory = intel_i915_remove_entries,
1570 .alloc_by_type = intel_i830_alloc_by_type,
1571 .free_by_type = intel_i810_free_by_type,
1572 .agp_alloc_page = agp_generic_alloc_page,
1573 .agp_alloc_pages = agp_generic_alloc_pages,
1574 .agp_destroy_page = agp_generic_destroy_page,
1575 .agp_destroy_pages = agp_generic_destroy_pages,
1576 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1577 .chipset_flush = intel_i915_chipset_flush,
1578#ifdef USE_PCI_DMA_API
1579 .agp_map_page = intel_agp_map_page,
1580 .agp_unmap_page = intel_agp_unmap_page,
1581 .agp_map_memory = intel_agp_map_memory,
1582 .agp_unmap_memory = intel_agp_unmap_memory,
1583#endif
1584};
1585 1508
1586static const struct agp_bridge_driver intel_gen6_driver = { 1509void intel_gmch_remove(struct pci_dev *pdev)
1587 .owner = THIS_MODULE, 1510{
1588 .aperture_sizes = intel_i830_sizes, 1511 if (intel_private.pcidev)
1589 .size_type = FIXED_APER_SIZE, 1512 pci_dev_put(intel_private.pcidev);
1590 .num_aperture_sizes = 4, 1513 if (intel_private.bridge_dev)
1591 .needs_scratch_page = true, 1514 pci_dev_put(intel_private.bridge_dev);
1592 .configure = intel_i9xx_configure, 1515}
1593 .fetch_size = intel_i9xx_fetch_size, 1516EXPORT_SYMBOL(intel_gmch_remove);
1594 .cleanup = intel_i915_cleanup,
1595 .mask_memory = intel_gen6_mask_memory,
1596 .masks = intel_gen6_masks,
1597 .agp_enable = intel_i810_agp_enable,
1598 .cache_flush = global_cache_flush,
1599 .create_gatt_table = intel_i965_create_gatt_table,
1600 .free_gatt_table = intel_i830_free_gatt_table,
1601 .insert_memory = intel_i915_insert_entries,
1602 .remove_memory = intel_i915_remove_entries,
1603 .alloc_by_type = intel_i830_alloc_by_type,
1604 .free_by_type = intel_i810_free_by_type,
1605 .agp_alloc_page = agp_generic_alloc_page,
1606 .agp_alloc_pages = agp_generic_alloc_pages,
1607 .agp_destroy_page = agp_generic_destroy_page,
1608 .agp_destroy_pages = agp_generic_destroy_pages,
1609 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1610 .chipset_flush = intel_i915_chipset_flush,
1611#ifdef USE_PCI_DMA_API
1612 .agp_map_page = intel_agp_map_page,
1613 .agp_unmap_page = intel_agp_unmap_page,
1614 .agp_map_memory = intel_agp_map_memory,
1615 .agp_unmap_memory = intel_agp_unmap_memory,
1616#endif
1617};
1618 1517
1619static const struct agp_bridge_driver intel_g33_driver = { 1518MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1620 .owner = THIS_MODULE, 1519MODULE_LICENSE("GPL and additional rights");
1621 .aperture_sizes = intel_i830_sizes,
1622 .size_type = FIXED_APER_SIZE,
1623 .num_aperture_sizes = 4,
1624 .needs_scratch_page = true,
1625 .configure = intel_i9xx_configure,
1626 .fetch_size = intel_i9xx_fetch_size,
1627 .cleanup = intel_i915_cleanup,
1628 .mask_memory = intel_i965_mask_memory,
1629 .masks = intel_i810_masks,
1630 .agp_enable = intel_i810_agp_enable,
1631 .cache_flush = global_cache_flush,
1632 .create_gatt_table = intel_i915_create_gatt_table,
1633 .free_gatt_table = intel_i830_free_gatt_table,
1634 .insert_memory = intel_i915_insert_entries,
1635 .remove_memory = intel_i915_remove_entries,
1636 .alloc_by_type = intel_i830_alloc_by_type,
1637 .free_by_type = intel_i810_free_by_type,
1638 .agp_alloc_page = agp_generic_alloc_page,
1639 .agp_alloc_pages = agp_generic_alloc_pages,
1640 .agp_destroy_page = agp_generic_destroy_page,
1641 .agp_destroy_pages = agp_generic_destroy_pages,
1642 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1643 .chipset_flush = intel_i915_chipset_flush,
1644#ifdef USE_PCI_DMA_API
1645 .agp_map_page = intel_agp_map_page,
1646 .agp_unmap_page = intel_agp_unmap_page,
1647 .agp_map_memory = intel_agp_map_memory,
1648 .agp_unmap_memory = intel_agp_unmap_memory,
1649#endif
1650};
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 1c129211302d..94821ab01c6d 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -19,6 +19,7 @@
19#include <linux/klist.h> 19#include <linux/klist.h>
20#include <linux/agp_backend.h> 20#include <linux/agp_backend.h>
21#include <linux/log2.h> 21#include <linux/log2.h>
22#include <linux/slab.h>
22 23
23#include <asm/parisc-device.h> 24#include <asm/parisc-device.h>
24#include <asm/ropes.h> 25#include <asm/ropes.h>
@@ -358,8 +359,12 @@ parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa)
358 bridge->dev = fake_bridge_dev; 359 bridge->dev = fake_bridge_dev;
359 360
360 error = agp_add_bridge(bridge); 361 error = agp_add_bridge(bridge);
362 if (error)
363 goto fail;
364 return 0;
361 365
362fail: 366fail:
367 kfree(fake_bridge_dev);
363 return error; 368 return error;
364} 369}
365 370
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c
index 13acaaf64edb..f02f9b07fd4c 100644
--- a/drivers/char/agp/sworks-agp.c
+++ b/drivers/char/agp/sworks-agp.c
@@ -229,7 +229,7 @@ static int serverworks_fetch_size(void)
229 * This routine could be implemented by taking the addresses 229 * This routine could be implemented by taking the addresses
230 * written to the GATT, and flushing them individually. However 230 * written to the GATT, and flushing them individually. However
231 * currently it just flushes the whole table. Which is probably 231 * currently it just flushes the whole table. Which is probably
232 * more efficent, since agp_memory blocks can be a large number of 232 * more efficient, since agp_memory blocks can be a large number of
233 * entries. 233 * entries.
234 */ 234 */
235static void serverworks_tlbflush(struct agp_memory *temp) 235static void serverworks_tlbflush(struct agp_memory *temp)
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index f845a8f718b3..a32c492baf5c 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -80,7 +80,7 @@ static void uninorth_tlbflush(struct agp_memory *mem)
80 ctrl | UNI_N_CFG_GART_INVAL); 80 ctrl | UNI_N_CFG_GART_INVAL);
81 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 81 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
82 82
83 if (uninorth_rev <= 0x30) { 83 if (!mem && uninorth_rev <= 0x30) {
84 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 84 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
85 ctrl | UNI_N_CFG_GART_2xRESET); 85 ctrl | UNI_N_CFG_GART_2xRESET);
86 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 86 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index df67e80019d2..8bc384937401 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -400,7 +400,7 @@ static struct agp_device_ids via_agp_device_ids[] __devinitdata =
400 * the traditional AGP which resides only in chipset. AGP is used 400 * the traditional AGP which resides only in chipset. AGP is used
401 * by 3D driver which wasn't available for the VT3336 and VT3364 401 * by 3D driver which wasn't available for the VT3336 and VT3364
402 * generation until now. Unfortunately, by testing, VT3364 works 402 * generation until now. Unfortunately, by testing, VT3364 works
403 * but VT3336 doesn't. - explaination from via, just leave this as 403 * but VT3336 doesn't. - explanation from via, just leave this as
404 * as a placeholder to avoid future patches adding it back in. 404 * as a placeholder to avoid future patches adding it back in.
405 */ 405 */
406#if 0 406#if 0
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-05 07:06:58 -0400