1 files changed, 35 insertions, 18 deletions

diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 70312da4c968..780498d76581 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -15,7 +15,7 @@
 #include <linux/mmzone.h>
 #include <asm/page.h>           /* PAGE_SIZE */
 #include <asm/e820.h>
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 #include <asm/gart.h>
 #include "agp.h"
 
@@ -38,7 +38,7 @@ static int agp_bridges_found;
 
 static void amd64_tlbflush(struct agp_memory *temp)
 {
-        k8_flush_garts();
+        amd_flush_garts();
 }
 
 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
@@ -124,7 +124,7 @@ static int amd64_fetch_size(void)
         u32 temp;
         struct aper_size_info_32 *values;
 
-        dev = k8_northbridges[0];
+        dev = node_to_amd_nb(0)->misc;
         if (dev==NULL)
                 return 0;
 
@@ -181,12 +181,15 @@ static int amd_8151_configure(void)
         unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
         int i;
 
+        if (!amd_nb_has_feature(AMD_NB_GART))
+                return 0;
+
         /* Configure AGP regs in each x86-64 host bridge. */
-        for (i = 0; i < num_k8_northbridges; i++) {
+        for (i = 0; i < amd_nb_num(); i++) {
                 agp_bridge->gart_bus_addr =
-                                amd64_configure(k8_northbridges[i], gatt_bus);
+                        amd64_configure(node_to_amd_nb(i)->misc, gatt_bus);
         }
-        k8_flush_garts();
+        amd_flush_garts();
         return 0;
 }
 
@@ -195,11 +198,15 @@ static void amd64_cleanup(void)
 {
         u32 tmp;
         int i;
-        for (i = 0; i < num_k8_northbridges; i++) {
-                struct pci_dev *dev = k8_northbridges[i];
+
+        if (!amd_nb_has_feature(AMD_NB_GART))
+                return;
+
+        for (i = 0; i < amd_nb_num(); i++) {
+                struct pci_dev *dev = node_to_amd_nb(i)->misc;
                 /* disable gart translation */
                 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
-                tmp &= ~AMD64_GARTEN;
+                tmp &= ~GARTEN;
                 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
         }
 }
@@ -313,22 +320,25 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
         if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
                 return -1;
 
-        pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
+        gart_set_size_and_enable(nb, order);
         pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
 
         return 0;
 }
 
-static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
+static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr)
 {
         int i;
 
-        if (cache_k8_northbridges() < 0)
+        if (amd_cache_northbridges() < 0)
+                return -ENODEV;
+
+        if (!amd_nb_has_feature(AMD_NB_GART))
                 return -ENODEV;
 
         i = 0;
-        for (i = 0; i < num_k8_northbridges; i++) {
-                struct pci_dev *dev = k8_northbridges[i];
+        for (i = 0; i < amd_nb_num(); i++) {
+                struct pci_dev *dev = node_to_amd_nb(i)->misc;
                 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
                         dev_err(&dev->dev, "no usable aperture found\n");
 #ifdef __x86_64__
@@ -405,7 +415,8 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
         }
 
         /* shadow x86-64 registers into ULi registers */
-        pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
+        pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
+                               &httfea);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
         if ((httfea & 0x7fff) >> (32 - 25)) {
@@ -472,7 +483,8 @@ static int nforce3_agp_init(struct pci_dev *pdev)
         pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
 
         /* shadow x86-64 registers into NVIDIA registers */
-        pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
+        pci_read_config_dword (node_to_amd_nb(0)->misc, AMD64_GARTAPERTUREBASE,
+                               &apbase);
 
         /* if x86-64 aperture base is beyond 4G, exit here */
         if ( (apbase & 0x7fff) >> (32 - 25) ) {
@@ -761,18 +773,23 @@ int __init agp_amd64_init(void)
 #else
                         printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
 #endif
+                        pci_unregister_driver(&agp_amd64_pci_driver);
                         return -ENODEV;
                 }
 
                 /* First check that we have at least one AMD64 NB */
-                if (!pci_dev_present(k8_nb_ids))
+                if (!pci_dev_present(amd_nb_misc_ids)) {
+                        pci_unregister_driver(&agp_amd64_pci_driver);
                         return -ENODEV;
+                }
 
                 /* Look for any AGP bridge */
                 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
                 err = driver_attach(&agp_amd64_pci_driver.driver);
-                if (err == 0 && agp_bridges_found == 0)
+                if (err == 0 && agp_bridges_found == 0) {
+                        pci_unregister_driver(&agp_amd64_pci_driver);
                         err = -ENODEV;
+                }
         }
         return err;
 }