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-rw-r--r--arch/mips/Kconfig88
-rw-r--r--arch/mips/Makefile22
-rw-r--r--arch/mips/alchemy/common/setup.c4
-rw-r--r--arch/mips/alchemy/common/time.c15
-rw-r--r--arch/mips/ar7/platform.c32
-rw-r--r--arch/mips/bcm63xx/Kconfig25
-rw-r--r--arch/mips/bcm63xx/Makefile7
-rw-r--r--arch/mips/bcm63xx/boards/Kconfig11
-rw-r--r--arch/mips/bcm63xx/boards/Makefile3
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c837
-rw-r--r--arch/mips/bcm63xx/clk.c226
-rw-r--r--arch/mips/bcm63xx/cpu.c345
-rw-r--r--arch/mips/bcm63xx/cs.c144
-rw-r--r--arch/mips/bcm63xx/dev-dsp.c56
-rw-r--r--arch/mips/bcm63xx/dev-enet.c159
-rw-r--r--arch/mips/bcm63xx/early_printk.c30
-rw-r--r--arch/mips/bcm63xx/gpio.c134
-rw-r--r--arch/mips/bcm63xx/irq.c253
-rw-r--r--arch/mips/bcm63xx/prom.c55
-rw-r--r--arch/mips/bcm63xx/setup.c125
-rw-r--r--arch/mips/bcm63xx/timer.c205
-rw-r--r--arch/mips/boot/elf2ecoff.c4
-rw-r--r--arch/mips/cavium-octeon/Makefile4
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c164
-rw-r--r--arch/mips/cavium-octeon/setup.c103
-rw-r--r--arch/mips/configs/ar7_defconfig1
-rw-r--r--arch/mips/configs/bcm47xx_defconfig1
-rw-r--r--arch/mips/configs/bcm63xx_defconfig972
-rw-r--r--arch/mips/configs/bigsur_defconfig1
-rw-r--r--arch/mips/configs/cobalt_defconfig1
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/excite_defconfig1
-rw-r--r--arch/mips/configs/fuloong2e_defconfig (renamed from arch/mips/configs/fulong_defconfig)473
-rw-r--r--arch/mips/configs/ip22_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/ip28_defconfig1
-rw-r--r--arch/mips/configs/ip32_defconfig1
-rw-r--r--arch/mips/configs/jazz_defconfig1
-rw-r--r--arch/mips/configs/lasat_defconfig1
-rw-r--r--arch/mips/configs/malta_defconfig1
-rw-r--r--arch/mips/configs/markeins_defconfig1
-rw-r--r--arch/mips/configs/mipssim_defconfig1
-rw-r--r--arch/mips/configs/msp71xx_defconfig1
-rw-r--r--arch/mips/configs/mtx1_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/pnx8335-stb225_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig1
-rw-r--r--arch/mips/configs/rb532_defconfig1
-rw-r--r--arch/mips/configs/rbtx49xx_defconfig1
-rw-r--r--arch/mips/configs/rm200_defconfig1
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/configs/wrppmc_defconfig1
-rw-r--r--arch/mips/configs/yosemite_defconfig1
-rw-r--r--arch/mips/dec/prom/memory.c2
-rw-r--r--arch/mips/emma/markeins/setup.c2
-rw-r--r--arch/mips/fw/arc/Makefile2
-rw-r--r--arch/mips/fw/cfe/cfe_api.c4
-rw-r--r--arch/mips/include/asm/atomic.h40
-rw-r--r--arch/mips/include/asm/bitops.h34
-rw-r--r--arch/mips/include/asm/bootinfo.h12
-rw-r--r--arch/mips/include/asm/cmpxchg.h4
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h7
-rw-r--r--arch/mips/include/asm/delay.h2
-rw-r--r--arch/mips/include/asm/fixmap.h4
-rw-r--r--arch/mips/include/asm/hardirq.h12
-rw-r--r--arch/mips/include/asm/lasat/lasat.h1
-rw-r--r--arch/mips/include/asm/local.h8
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h9
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h538
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h10
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h13
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h45
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h6
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h22
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h93
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h773
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h60
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h51
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/gpio.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h25
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h12
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h1
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h (renamed from arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h)6
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h (renamed from arch/mips/include/asm/mach-lemote/dma-coherence.h)6
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h64
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h22
-rw-r--r--arch/mips/include/asm/mach-loongson/mc146818rtc.h (renamed from arch/mips/include/asm/mach-lemote/mc146818rtc.h)6
-rw-r--r--arch/mips/include/asm/mach-loongson/mem.h30
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h (renamed from arch/mips/include/asm/mach-lemote/pci.h)21
-rw-r--r--arch/mips/include/asm/mach-loongson/war.h (renamed from arch/mips/include/asm/mach-lemote/war.h)6
-rw-r--r--arch/mips/include/asm/mach-malta/cpu-feature-overrides.h4
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h2
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-rnm-defs.h88
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h2
-rw-r--r--arch/mips/include/asm/page.h5
-rw-r--r--arch/mips/include/asm/pci.h2
-rw-r--r--arch/mips/include/asm/pgtable-64.h11
-rw-r--r--arch/mips/include/asm/system.h18
-rw-r--r--arch/mips/kernel/asm-offsets.c3
-rw-r--r--arch/mips/kernel/cpu-bugs64.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c40
-rw-r--r--arch/mips/kernel/kspd.c6
-rw-r--r--arch/mips/kernel/mips-mt-fpaff.c2
-rw-r--r--arch/mips/kernel/mips-mt.c10
-rw-r--r--arch/mips/kernel/octeon_switch.S3
-rw-r--r--arch/mips/kernel/r2300_switch.S3
-rw-r--r--arch/mips/kernel/r4k_switch.S3
-rw-r--r--arch/mips/kernel/rtlx.c2
-rw-r--r--arch/mips/kernel/scall32-o32.S72
-rw-r--r--arch/mips/kernel/scall64-64.S72
-rw-r--r--arch/mips/kernel/setup.c2
-rw-r--r--arch/mips/kernel/smp.c3
-rw-r--r--arch/mips/kernel/smtc.c10
-rw-r--r--arch/mips/kernel/syscall.c112
-rw-r--r--arch/mips/kernel/traps.c5
-rw-r--r--arch/mips/kernel/vmlinux.lds.S114
-rw-r--r--arch/mips/kernel/vpe.c2
-rw-r--r--arch/mips/lemote/lm2e/Makefile7
-rw-r--r--arch/mips/lemote/lm2e/dbg_io.c146
-rw-r--r--arch/mips/lemote/lm2e/irq.c143
-rw-r--r--arch/mips/lemote/lm2e/pci.c97
-rw-r--r--arch/mips/lemote/lm2e/prom.c97
-rw-r--r--arch/mips/lemote/lm2e/reset.c41
-rw-r--r--arch/mips/lemote/lm2e/setup.c111
-rw-r--r--arch/mips/loongson/Kconfig31
-rw-r--r--arch/mips/loongson/Makefile11
-rw-r--r--arch/mips/loongson/common/Makefile11
-rw-r--r--arch/mips/loongson/common/bonito-irq.c (renamed from arch/mips/lemote/lm2e/bonito-irq.c)27
-rw-r--r--arch/mips/loongson/common/cmdline.c52
-rw-r--r--arch/mips/loongson/common/early_printk.c38
-rw-r--r--arch/mips/loongson/common/env.c58
-rw-r--r--arch/mips/loongson/common/init.c30
-rw-r--r--arch/mips/loongson/common/irq.c74
-rw-r--r--arch/mips/loongson/common/machtype.c50
-rw-r--r--arch/mips/loongson/common/mem.c (renamed from arch/mips/lemote/lm2e/mem.c)22
-rw-r--r--arch/mips/loongson/common/pci.c83
-rw-r--r--arch/mips/loongson/common/reset.c44
-rw-r--r--arch/mips/loongson/common/setup.c58
-rw-r--r--arch/mips/loongson/common/time.c27
-rw-r--r--arch/mips/loongson/fuloong-2e/Makefile7
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c71
-rw-r--r--arch/mips/loongson/fuloong-2e/reset.c23
-rw-r--r--arch/mips/mipssim/sim_setup.c2
-rw-r--r--arch/mips/mm/fault.c12
-rw-r--r--arch/mips/mm/init.c3
-rw-r--r--arch/mips/mm/pgtable-64.c3
-rw-r--r--arch/mips/mm/tlb-r4k.c2
-rw-r--r--arch/mips/mm/tlbex.c53
-rw-r--r--arch/mips/mti-malta/malta-init.c2
-rw-r--r--arch/mips/mti-malta/malta-reset.c7
-rw-r--r--arch/mips/mti-malta/malta-setup.c1
-rw-r--r--arch/mips/nxp/pnx833x/stb22x/board.c2
-rw-r--r--arch/mips/nxp/pnx8550/common/proc.c6
-rw-r--r--arch/mips/oprofile/Makefile1
-rw-r--r--arch/mips/oprofile/common.c4
-rw-r--r--arch/mips/oprofile/op_model_loongson2.c177
-rw-r--r--arch/mips/pci/Makefile4
-rw-r--r--arch/mips/pci/fixup-bcm63xx.c21
-rw-r--r--arch/mips/pci/fixup-fuloong2e.c (renamed from arch/mips/pci/fixup-lm2e.c)18
-rw-r--r--arch/mips/pci/ops-bcm63xx.c467
-rw-r--r--arch/mips/pci/ops-bonito64.c4
-rw-r--r--arch/mips/pci/pci-bcm1480.c2
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c2
-rw-r--r--arch/mips/pci/pci-bcm63xx.c224
-rw-r--r--arch/mips/pci/pci-bcm63xx.h27
-rw-r--r--arch/mips/pci/pci-sb1250.c2
-rw-r--r--arch/mips/pci/pci.c4
-rw-r--r--arch/mips/power/hibernate.S3
-rw-r--r--arch/mips/sgi-ip22/Makefile2
-rw-r--r--arch/mips/txx9/generic/pci.c13
-rw-r--r--arch/mips/txx9/generic/setup.c17
184 files changed, 7950 insertions, 1643 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3ca0fe1a9123..705a7a9170f3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -6,7 +6,7 @@ config MIPS
6 select HAVE_ARCH_KGDB 6 select HAVE_ARCH_KGDB
7 # Horrible source of confusion. Die, die, die ... 7 # Horrible source of confusion. Die, die, die ...
8 select EMBEDDED 8 select EMBEDDED
9 select RTC_LIB 9 select RTC_LIB if !LEMOTE_FULOONG2E
10 10
11mainmenu "Linux/MIPS Kernel Configuration" 11mainmenu "Linux/MIPS Kernel Configuration"
12 12
@@ -80,6 +80,21 @@ config BCM47XX
80 help 80 help
81 Support for BCM47XX based boards 81 Support for BCM47XX based boards
82 82
83config BCM63XX
84 bool "Broadcom BCM63XX based boards"
85 select CEVT_R4K
86 select CSRC_R4K
87 select DMA_NONCOHERENT
88 select IRQ_CPU
89 select SYS_HAS_CPU_MIPS32_R1
90 select SYS_SUPPORTS_32BIT_KERNEL
91 select SYS_SUPPORTS_BIG_ENDIAN
92 select SYS_HAS_EARLY_PRINTK
93 select SWAP_IO_SPACE
94 select ARCH_REQUIRE_GPIOLIB
95 help
96 Support for BCM63XX based boards
97
83config MIPS_COBALT 98config MIPS_COBALT
84 bool "Cobalt Server" 99 bool "Cobalt Server"
85 select CEVT_R4K 100 select CEVT_R4K
@@ -174,30 +189,15 @@ config LASAT
174 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN 189 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
175 select SYS_SUPPORTS_LITTLE_ENDIAN 190 select SYS_SUPPORTS_LITTLE_ENDIAN
176 191
177config LEMOTE_FULONG 192config MACH_LOONGSON
178 bool "Lemote Fulong mini-PC" 193 bool "Loongson family of machines"
179 select ARCH_SPARSEMEM_ENABLE
180 select CEVT_R4K
181 select CSRC_R4K
182 select SYS_HAS_CPU_LOONGSON2
183 select DMA_NONCOHERENT
184 select BOOT_ELF32
185 select BOARD_SCACHE
186 select HAVE_STD_PC_SERIAL_PORT
187 select HW_HAS_PCI
188 select I8259
189 select ISA
190 select IRQ_CPU
191 select SYS_SUPPORTS_32BIT_KERNEL
192 select SYS_SUPPORTS_64BIT_KERNEL
193 select SYS_SUPPORTS_LITTLE_ENDIAN
194 select SYS_SUPPORTS_HIGHMEM
195 select SYS_HAS_EARLY_PRINTK
196 select GENERIC_ISA_DMA_SUPPORT_BROKEN
197 select CPU_HAS_WB
198 help 194 help
199 Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and 195 This enables the support of Loongson family of machines.
200 an FPGA northbridge 196
197 Loongson is a family of general-purpose MIPS-compatible CPUs.
198 developed at Institute of Computing Technology (ICT),
199 Chinese Academy of Sciences (CAS) in the People's Republic
200 of China. The chief architect is Professor Weiwu Hu.
201 201
202config MIPS_MALTA 202config MIPS_MALTA
203 bool "MIPS Malta board" 203 bool "MIPS Malta board"
@@ -660,6 +660,7 @@ endchoice
660 660
661source "arch/mips/alchemy/Kconfig" 661source "arch/mips/alchemy/Kconfig"
662source "arch/mips/basler/excite/Kconfig" 662source "arch/mips/basler/excite/Kconfig"
663source "arch/mips/bcm63xx/Kconfig"
663source "arch/mips/jazz/Kconfig" 664source "arch/mips/jazz/Kconfig"
664source "arch/mips/lasat/Kconfig" 665source "arch/mips/lasat/Kconfig"
665source "arch/mips/pmc-sierra/Kconfig" 666source "arch/mips/pmc-sierra/Kconfig"
@@ -668,6 +669,7 @@ source "arch/mips/sibyte/Kconfig"
668source "arch/mips/txx9/Kconfig" 669source "arch/mips/txx9/Kconfig"
669source "arch/mips/vr41xx/Kconfig" 670source "arch/mips/vr41xx/Kconfig"
670source "arch/mips/cavium-octeon/Kconfig" 671source "arch/mips/cavium-octeon/Kconfig"
672source "arch/mips/loongson/Kconfig"
671 673
672endmenu 674endmenu
673 675
@@ -1044,12 +1046,10 @@ choice
1044 prompt "CPU type" 1046 prompt "CPU type"
1045 default CPU_R4X00 1047 default CPU_R4X00
1046 1048
1047config CPU_LOONGSON2 1049config CPU_LOONGSON2E
1048 bool "Loongson 2" 1050 bool "Loongson 2E"
1049 depends on SYS_HAS_CPU_LOONGSON2 1051 depends on SYS_HAS_CPU_LOONGSON2E
1050 select CPU_SUPPORTS_32BIT_KERNEL 1052 select CPU_LOONGSON2
1051 select CPU_SUPPORTS_64BIT_KERNEL
1052 select CPU_SUPPORTS_HIGHMEM
1053 help 1053 help
1054 The Loongson 2E processor implements the MIPS III instruction set 1054 The Loongson 2E processor implements the MIPS III instruction set
1055 with many extensions. 1055 with many extensions.
@@ -1057,7 +1057,6 @@ config CPU_LOONGSON2
1057config CPU_MIPS32_R1 1057config CPU_MIPS32_R1
1058 bool "MIPS32 Release 1" 1058 bool "MIPS32 Release 1"
1059 depends on SYS_HAS_CPU_MIPS32_R1 1059 depends on SYS_HAS_CPU_MIPS32_R1
1060 select CPU_HAS_LLSC
1061 select CPU_HAS_PREFETCH 1060 select CPU_HAS_PREFETCH
1062 select CPU_SUPPORTS_32BIT_KERNEL 1061 select CPU_SUPPORTS_32BIT_KERNEL
1063 select CPU_SUPPORTS_HIGHMEM 1062 select CPU_SUPPORTS_HIGHMEM
@@ -1075,7 +1074,6 @@ config CPU_MIPS32_R1
1075config CPU_MIPS32_R2 1074config CPU_MIPS32_R2
1076 bool "MIPS32 Release 2" 1075 bool "MIPS32 Release 2"
1077 depends on SYS_HAS_CPU_MIPS32_R2 1076 depends on SYS_HAS_CPU_MIPS32_R2
1078 select CPU_HAS_LLSC
1079 select CPU_HAS_PREFETCH 1077 select CPU_HAS_PREFETCH
1080 select CPU_SUPPORTS_32BIT_KERNEL 1078 select CPU_SUPPORTS_32BIT_KERNEL
1081 select CPU_SUPPORTS_HIGHMEM 1079 select CPU_SUPPORTS_HIGHMEM
@@ -1089,7 +1087,6 @@ config CPU_MIPS32_R2
1089config CPU_MIPS64_R1 1087config CPU_MIPS64_R1
1090 bool "MIPS64 Release 1" 1088 bool "MIPS64 Release 1"
1091 depends on SYS_HAS_CPU_MIPS64_R1 1089 depends on SYS_HAS_CPU_MIPS64_R1
1092 select CPU_HAS_LLSC
1093 select CPU_HAS_PREFETCH 1090 select CPU_HAS_PREFETCH
1094 select CPU_SUPPORTS_32BIT_KERNEL 1091 select CPU_SUPPORTS_32BIT_KERNEL
1095 select CPU_SUPPORTS_64BIT_KERNEL 1092 select CPU_SUPPORTS_64BIT_KERNEL
@@ -1109,7 +1106,6 @@ config CPU_MIPS64_R1
1109config CPU_MIPS64_R2 1106config CPU_MIPS64_R2
1110 bool "MIPS64 Release 2" 1107 bool "MIPS64 Release 2"
1111 depends on SYS_HAS_CPU_MIPS64_R2 1108 depends on SYS_HAS_CPU_MIPS64_R2
1112 select CPU_HAS_LLSC
1113 select CPU_HAS_PREFETCH 1109 select CPU_HAS_PREFETCH
1114 select CPU_SUPPORTS_32BIT_KERNEL 1110 select CPU_SUPPORTS_32BIT_KERNEL
1115 select CPU_SUPPORTS_64BIT_KERNEL 1111 select CPU_SUPPORTS_64BIT_KERNEL
@@ -1155,7 +1151,6 @@ config CPU_VR41XX
1155config CPU_R4300 1151config CPU_R4300
1156 bool "R4300" 1152 bool "R4300"
1157 depends on SYS_HAS_CPU_R4300 1153 depends on SYS_HAS_CPU_R4300
1158 select CPU_HAS_LLSC
1159 select CPU_SUPPORTS_32BIT_KERNEL 1154 select CPU_SUPPORTS_32BIT_KERNEL
1160 select CPU_SUPPORTS_64BIT_KERNEL 1155 select CPU_SUPPORTS_64BIT_KERNEL
1161 help 1156 help
@@ -1164,7 +1159,6 @@ config CPU_R4300
1164config CPU_R4X00 1159config CPU_R4X00
1165 bool "R4x00" 1160 bool "R4x00"
1166 depends on SYS_HAS_CPU_R4X00 1161 depends on SYS_HAS_CPU_R4X00
1167 select CPU_HAS_LLSC
1168 select CPU_SUPPORTS_32BIT_KERNEL 1162 select CPU_SUPPORTS_32BIT_KERNEL
1169 select CPU_SUPPORTS_64BIT_KERNEL 1163 select CPU_SUPPORTS_64BIT_KERNEL
1170 help 1164 help
@@ -1174,7 +1168,6 @@ config CPU_R4X00
1174config CPU_TX49XX 1168config CPU_TX49XX
1175 bool "R49XX" 1169 bool "R49XX"
1176 depends on SYS_HAS_CPU_TX49XX 1170 depends on SYS_HAS_CPU_TX49XX
1177 select CPU_HAS_LLSC
1178 select CPU_HAS_PREFETCH 1171 select CPU_HAS_PREFETCH
1179 select CPU_SUPPORTS_32BIT_KERNEL 1172 select CPU_SUPPORTS_32BIT_KERNEL
1180 select CPU_SUPPORTS_64BIT_KERNEL 1173 select CPU_SUPPORTS_64BIT_KERNEL
@@ -1182,7 +1175,6 @@ config CPU_TX49XX
1182config CPU_R5000 1175config CPU_R5000
1183 bool "R5000" 1176 bool "R5000"
1184 depends on SYS_HAS_CPU_R5000 1177 depends on SYS_HAS_CPU_R5000
1185 select CPU_HAS_LLSC
1186 select CPU_SUPPORTS_32BIT_KERNEL 1178 select CPU_SUPPORTS_32BIT_KERNEL
1187 select CPU_SUPPORTS_64BIT_KERNEL 1179 select CPU_SUPPORTS_64BIT_KERNEL
1188 help 1180 help
@@ -1191,14 +1183,12 @@ config CPU_R5000
1191config CPU_R5432 1183config CPU_R5432
1192 bool "R5432" 1184 bool "R5432"
1193 depends on SYS_HAS_CPU_R5432 1185 depends on SYS_HAS_CPU_R5432
1194 select CPU_HAS_LLSC
1195 select CPU_SUPPORTS_32BIT_KERNEL 1186 select CPU_SUPPORTS_32BIT_KERNEL
1196 select CPU_SUPPORTS_64BIT_KERNEL 1187 select CPU_SUPPORTS_64BIT_KERNEL
1197 1188
1198config CPU_R5500 1189config CPU_R5500
1199 bool "R5500" 1190 bool "R5500"
1200 depends on SYS_HAS_CPU_R5500 1191 depends on SYS_HAS_CPU_R5500
1201 select CPU_HAS_LLSC
1202 select CPU_SUPPORTS_32BIT_KERNEL 1192 select CPU_SUPPORTS_32BIT_KERNEL
1203 select CPU_SUPPORTS_64BIT_KERNEL 1193 select CPU_SUPPORTS_64BIT_KERNEL
1204 select CPU_SUPPORTS_HUGEPAGES 1194 select CPU_SUPPORTS_HUGEPAGES
@@ -1209,7 +1199,6 @@ config CPU_R5500
1209config CPU_R6000 1199config CPU_R6000
1210 bool "R6000" 1200 bool "R6000"
1211 depends on EXPERIMENTAL 1201 depends on EXPERIMENTAL
1212 select CPU_HAS_LLSC
1213 depends on SYS_HAS_CPU_R6000 1202 depends on SYS_HAS_CPU_R6000
1214 select CPU_SUPPORTS_32BIT_KERNEL 1203 select CPU_SUPPORTS_32BIT_KERNEL
1215 help 1204 help
@@ -1219,7 +1208,6 @@ config CPU_R6000
1219config CPU_NEVADA 1208config CPU_NEVADA
1220 bool "RM52xx" 1209 bool "RM52xx"
1221 depends on SYS_HAS_CPU_NEVADA 1210 depends on SYS_HAS_CPU_NEVADA
1222 select CPU_HAS_LLSC
1223 select CPU_SUPPORTS_32BIT_KERNEL 1211 select CPU_SUPPORTS_32BIT_KERNEL
1224 select CPU_SUPPORTS_64BIT_KERNEL 1212 select CPU_SUPPORTS_64BIT_KERNEL
1225 help 1213 help
@@ -1229,7 +1217,6 @@ config CPU_R8000
1229 bool "R8000" 1217 bool "R8000"
1230 depends on EXPERIMENTAL 1218 depends on EXPERIMENTAL
1231 depends on SYS_HAS_CPU_R8000 1219 depends on SYS_HAS_CPU_R8000
1232 select CPU_HAS_LLSC
1233 select CPU_HAS_PREFETCH 1220 select CPU_HAS_PREFETCH
1234 select CPU_SUPPORTS_64BIT_KERNEL 1221 select CPU_SUPPORTS_64BIT_KERNEL
1235 help 1222 help
@@ -1239,7 +1226,6 @@ config CPU_R8000
1239config CPU_R10000 1226config CPU_R10000
1240 bool "R10000" 1227 bool "R10000"
1241 depends on SYS_HAS_CPU_R10000 1228 depends on SYS_HAS_CPU_R10000
1242 select CPU_HAS_LLSC
1243 select CPU_HAS_PREFETCH 1229 select CPU_HAS_PREFETCH
1244 select CPU_SUPPORTS_32BIT_KERNEL 1230 select CPU_SUPPORTS_32BIT_KERNEL
1245 select CPU_SUPPORTS_64BIT_KERNEL 1231 select CPU_SUPPORTS_64BIT_KERNEL
@@ -1250,7 +1236,6 @@ config CPU_R10000
1250config CPU_RM7000 1236config CPU_RM7000
1251 bool "RM7000" 1237 bool "RM7000"
1252 depends on SYS_HAS_CPU_RM7000 1238 depends on SYS_HAS_CPU_RM7000
1253 select CPU_HAS_LLSC
1254 select CPU_HAS_PREFETCH 1239 select CPU_HAS_PREFETCH
1255 select CPU_SUPPORTS_32BIT_KERNEL 1240 select CPU_SUPPORTS_32BIT_KERNEL
1256 select CPU_SUPPORTS_64BIT_KERNEL 1241 select CPU_SUPPORTS_64BIT_KERNEL
@@ -1259,7 +1244,6 @@ config CPU_RM7000
1259config CPU_RM9000 1244config CPU_RM9000
1260 bool "RM9000" 1245 bool "RM9000"
1261 depends on SYS_HAS_CPU_RM9000 1246 depends on SYS_HAS_CPU_RM9000
1262 select CPU_HAS_LLSC
1263 select CPU_HAS_PREFETCH 1247 select CPU_HAS_PREFETCH
1264 select CPU_SUPPORTS_32BIT_KERNEL 1248 select CPU_SUPPORTS_32BIT_KERNEL
1265 select CPU_SUPPORTS_64BIT_KERNEL 1249 select CPU_SUPPORTS_64BIT_KERNEL
@@ -1269,7 +1253,6 @@ config CPU_RM9000
1269config CPU_SB1 1253config CPU_SB1
1270 bool "SB1" 1254 bool "SB1"
1271 depends on SYS_HAS_CPU_SB1 1255 depends on SYS_HAS_CPU_SB1
1272 select CPU_HAS_LLSC
1273 select CPU_SUPPORTS_32BIT_KERNEL 1256 select CPU_SUPPORTS_32BIT_KERNEL
1274 select CPU_SUPPORTS_64BIT_KERNEL 1257 select CPU_SUPPORTS_64BIT_KERNEL
1275 select CPU_SUPPORTS_HIGHMEM 1258 select CPU_SUPPORTS_HIGHMEM
@@ -1296,7 +1279,13 @@ config CPU_CAVIUM_OCTEON
1296 1279
1297endchoice 1280endchoice
1298 1281
1299config SYS_HAS_CPU_LOONGSON2 1282config CPU_LOONGSON2
1283 bool
1284 select CPU_SUPPORTS_32BIT_KERNEL
1285 select CPU_SUPPORTS_64BIT_KERNEL
1286 select CPU_SUPPORTS_HIGHMEM
1287
1288config SYS_HAS_CPU_LOONGSON2E
1300 bool 1289 bool
1301 1290
1302config SYS_HAS_CPU_MIPS32_R1 1291config SYS_HAS_CPU_MIPS32_R1
@@ -1683,9 +1672,6 @@ config SB1_PASS_2_1_WORKAROUNDS
1683config 64BIT_PHYS_ADDR 1672config 64BIT_PHYS_ADDR
1684 bool 1673 bool
1685 1674
1686config CPU_HAS_LLSC
1687 bool
1688
1689config CPU_HAS_SMARTMIPS 1675config CPU_HAS_SMARTMIPS
1690 depends on SYS_SUPPORTS_SMARTMIPS 1676 depends on SYS_SUPPORTS_SMARTMIPS
1691 bool "Support for the SmartMIPS ASE" 1677 bool "Support for the SmartMIPS ASE"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 861da514a468..c825b14b4ed0 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -120,7 +120,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
120cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap 120cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
121cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap 121cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
122cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap 122cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
123cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap 123# only gcc >= 4.4 have the loongson-specific support
124cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
125cflags-$(CONFIG_CPU_LOONGSON2E) += \
126 $(call cc-option,-march=loongson2e,-march=r4600)
127
124cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 128cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
125 -Wa,-mips32 -Wa,--trap 129 -Wa,-mips32 -Wa,--trap
126cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 130cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -314,11 +318,12 @@ cflags-$(CONFIG_WR_PPMC) += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
314load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 318load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
315 319
316# 320#
317# lemote fulong mini-PC board 321# Loongson family
318# 322#
319core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/ 323core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
320load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000 324cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
321cflags-$(CONFIG_LEMOTE_FULONG) += -I$(srctree)/arch/mips/include/asm/mach-lemote 325 -mno-branch-likely
326load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
322 327
323# 328#
324# MIPS Malta board 329# MIPS Malta board
@@ -560,6 +565,13 @@ cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
560load-$(CONFIG_BCM47XX) := 0xffffffff80001000 565load-$(CONFIG_BCM47XX) := 0xffffffff80001000
561 566
562# 567#
568# Broadcom BCM63XX boards
569#
570core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/
571cflags-$(CONFIG_BCM63XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
572load-$(CONFIG_BCM63XX) := 0xffffffff80010000
573
574#
563# SNI RM 575# SNI RM
564# 576#
565core-$(CONFIG_SNI_RM) += arch/mips/sni/ 577core-$(CONFIG_SNI_RM) += arch/mips/sni/
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 3f036b3d400e..6184baa56786 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -27,6 +27,7 @@
27 27
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/ioport.h> 29#include <linux/ioport.h>
30#include <linux/jiffies.h>
30#include <linux/module.h> 31#include <linux/module.h>
31#include <linux/pm.h> 32#include <linux/pm.h>
32 33
@@ -53,6 +54,9 @@ void __init plat_mem_setup(void)
53 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), 54 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),
54 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); 55 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
55 56
57 /* this is faster than wasting cycles trying to approximate it */
58 preset_lpj = (est_freq >> 1) / HZ;
59
56 _machine_restart = au1000_restart; 60 _machine_restart = au1000_restart;
57 _machine_halt = au1000_halt; 61 _machine_halt = au1000_halt;
58 pm_power_off = au1000_power_off; 62 pm_power_off = au1000_power_off;
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 33fbae79af5e..f34ff8601942 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -36,14 +36,13 @@
36#include <linux/interrupt.h> 36#include <linux/interrupt.h>
37#include <linux/spinlock.h> 37#include <linux/spinlock.h>
38 38
39#include <asm/processor.h>
39#include <asm/time.h> 40#include <asm/time.h>
40#include <asm/mach-au1x00/au1000.h> 41#include <asm/mach-au1x00/au1000.h>
41 42
42/* 32kHz clock enabled and detected */ 43/* 32kHz clock enabled and detected */
43#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) 44#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
44 45
45extern int allow_au1k_wait; /* default off for CP0 Counter */
46
47static cycle_t au1x_counter1_read(struct clocksource *cs) 46static cycle_t au1x_counter1_read(struct clocksource *cs)
48{ 47{
49 return au_readl(SYS_RTCREAD); 48 return au_readl(SYS_RTCREAD);
@@ -153,13 +152,17 @@ void __init plat_time_init(void)
153 152
154 printk(KERN_INFO "Alchemy clocksource installed\n"); 153 printk(KERN_INFO "Alchemy clocksource installed\n");
155 154
156 /* can now use 'wait' */
157 allow_au1k_wait = 1;
158 return; 155 return;
159 156
160cntr_err: 157cntr_err:
161 /* counters unusable, use C0 counter */ 158 /*
159 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
160 * function is called. Because the Alchemy counters are unusable
161 * the C0 timekeeping code is installed and use of the 'wait'
162 * instruction must be prohibited, which is done most easily by
163 * assigning NULL to cpu_wait.
164 */
165 cpu_wait = NULL;
162 r4k_clockevent_init(); 166 r4k_clockevent_init();
163 init_r4k_clocksource(); 167 init_r4k_clocksource();
164 allow_au1k_wait = 0;
165} 168}
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index cf50fa29b198..e2278c04459d 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -417,6 +417,20 @@ static struct platform_device ar7_udc = {
417 .num_resources = ARRAY_SIZE(usb_res), 417 .num_resources = ARRAY_SIZE(usb_res),
418}; 418};
419 419
420static struct resource ar7_wdt_res = {
421 .name = "regs",
422 .start = -1, /* Filled at runtime */
423 .end = -1, /* Filled at runtime */
424 .flags = IORESOURCE_MEM,
425};
426
427static struct platform_device ar7_wdt = {
428 .id = -1,
429 .name = "ar7_wdt",
430 .resource = &ar7_wdt_res,
431 .num_resources = 1,
432};
433
420static inline unsigned char char2hex(char h) 434static inline unsigned char char2hex(char h)
421{ 435{
422 switch (h) { 436 switch (h) {
@@ -487,6 +501,7 @@ static void __init detect_leds(void)
487 501
488static int __init ar7_register_devices(void) 502static int __init ar7_register_devices(void)
489{ 503{
504 u16 chip_id;
490 int res; 505 int res;
491#ifdef CONFIG_SERIAL_8250 506#ifdef CONFIG_SERIAL_8250
492 static struct uart_port uart_port[2]; 507 static struct uart_port uart_port[2];
@@ -565,6 +580,23 @@ static int __init ar7_register_devices(void)
565 580
566 res = platform_device_register(&ar7_udc); 581 res = platform_device_register(&ar7_udc);
567 582
583 chip_id = ar7_chip_id();
584 switch (chip_id) {
585 case AR7_CHIP_7100:
586 case AR7_CHIP_7200:
587 ar7_wdt_res.start = AR7_REGS_WDT;
588 break;
589 case AR7_CHIP_7300:
590 ar7_wdt_res.start = UR8_REGS_WDT;
591 break;
592 default:
593 break;
594 }
595
596 ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
597
598 res = platform_device_register(&ar7_wdt);
599
568 return res; 600 return res;
569} 601}
570arch_initcall(ar7_register_devices); 602arch_initcall(ar7_register_devices);
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
new file mode 100644
index 000000000000..fb177d6df066
--- /dev/null
+++ b/arch/mips/bcm63xx/Kconfig
@@ -0,0 +1,25 @@
1menu "CPU support"
2 depends on BCM63XX
3
4config BCM63XX_CPU_6338
5 bool "support 6338 CPU"
6 select HW_HAS_PCI
7 select USB_ARCH_HAS_OHCI
8 select USB_OHCI_BIG_ENDIAN_DESC
9 select USB_OHCI_BIG_ENDIAN_MMIO
10
11config BCM63XX_CPU_6345
12 bool "support 6345 CPU"
13 select USB_OHCI_BIG_ENDIAN_DESC
14 select USB_OHCI_BIG_ENDIAN_MMIO
15
16config BCM63XX_CPU_6348
17 bool "support 6348 CPU"
18 select HW_HAS_PCI
19
20config BCM63XX_CPU_6358
21 bool "support 6358 CPU"
22 select HW_HAS_PCI
23endmenu
24
25source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
new file mode 100644
index 000000000000..aaa585cf26e3
--- /dev/null
+++ b/arch/mips/bcm63xx/Makefile
@@ -0,0 +1,7 @@
1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
2 dev-dsp.o dev-enet.o
3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
4
5obj-y += boards/
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/boards/Kconfig b/arch/mips/bcm63xx/boards/Kconfig
new file mode 100644
index 000000000000..c6aed33d893e
--- /dev/null
+++ b/arch/mips/bcm63xx/boards/Kconfig
@@ -0,0 +1,11 @@
1choice
2 prompt "Board support"
3 depends on BCM63XX
4 default BOARD_BCM963XX
5
6config BOARD_BCM963XX
7 bool "Generic Broadcom 963xx boards"
8 select SSB
9 help
10
11endchoice
diff --git a/arch/mips/bcm63xx/boards/Makefile b/arch/mips/bcm63xx/boards/Makefile
new file mode 100644
index 000000000000..e5cc86dc1da8
--- /dev/null
+++ b/arch/mips/bcm63xx/boards/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
new file mode 100644
index 000000000000..fd77f548207a
--- /dev/null
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -0,0 +1,837 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mtd/physmap.h>
17#include <linux/ssb/ssb.h>
18#include <asm/addrspace.h>
19#include <bcm63xx_board.h>
20#include <bcm63xx_cpu.h>
21#include <bcm63xx_regs.h>
22#include <bcm63xx_io.h>
23#include <bcm63xx_board.h>
24#include <bcm63xx_dev_pci.h>
25#include <bcm63xx_dev_enet.h>
26#include <bcm63xx_dev_dsp.h>
27#include <board_bcm963xx.h>
28
29#define PFX "board_bcm963xx: "
30
31static struct bcm963xx_nvram nvram;
32static unsigned int mac_addr_used;
33static struct board_info board;
34
35/*
36 * known 6338 boards
37 */
38#ifdef CONFIG_BCM63XX_CPU_6338
39static struct board_info __initdata board_96338gw = {
40 .name = "96338GW",
41 .expected_cpu_id = 0x6338,
42
43 .has_enet0 = 1,
44 .enet0 = {
45 .force_speed_100 = 1,
46 .force_duplex_full = 1,
47 },
48
49 .has_ohci0 = 1,
50
51 .leds = {
52 {
53 .name = "adsl",
54 .gpio = 3,
55 .active_low = 1,
56 },
57 {
58 .name = "ses",
59 .gpio = 5,
60 .active_low = 1,
61 },
62 {
63 .name = "ppp-fail",
64 .gpio = 4,
65 .active_low = 1,
66 },
67 {
68 .name = "power",
69 .gpio = 0,
70 .active_low = 1,
71 .default_trigger = "default-on",
72 },
73 {
74 .name = "stop",
75 .gpio = 1,
76 .active_low = 1,
77 }
78 },
79};
80
81static struct board_info __initdata board_96338w = {
82 .name = "96338W",
83 .expected_cpu_id = 0x6338,
84
85 .has_enet0 = 1,
86 .enet0 = {
87 .force_speed_100 = 1,
88 .force_duplex_full = 1,
89 },
90
91 .leds = {
92 {
93 .name = "adsl",
94 .gpio = 3,
95 .active_low = 1,
96 },
97 {
98 .name = "ses",
99 .gpio = 5,
100 .active_low = 1,
101 },
102 {
103 .name = "ppp-fail",
104 .gpio = 4,
105 .active_low = 1,
106 },
107 {
108 .name = "power",
109 .gpio = 0,
110 .active_low = 1,
111 .default_trigger = "default-on",
112 },
113 {
114 .name = "stop",
115 .gpio = 1,
116 .active_low = 1,
117 },
118 },
119};
120#endif
121
122/*
123 * known 6345 boards
124 */
125#ifdef CONFIG_BCM63XX_CPU_6345
126static struct board_info __initdata board_96345gw2 = {
127 .name = "96345GW2",
128 .expected_cpu_id = 0x6345,
129};
130#endif
131
132/*
133 * known 6348 boards
134 */
135#ifdef CONFIG_BCM63XX_CPU_6348
136static struct board_info __initdata board_96348r = {
137 .name = "96348R",
138 .expected_cpu_id = 0x6348,
139
140 .has_enet0 = 1,
141 .has_pci = 1,
142
143 .enet0 = {
144 .has_phy = 1,
145 .use_internal_phy = 1,
146 },
147
148 .leds = {
149 {
150 .name = "adsl-fail",
151 .gpio = 2,
152 .active_low = 1,
153 },
154 {
155 .name = "ppp",
156 .gpio = 3,
157 .active_low = 1,
158 },
159 {
160 .name = "ppp-fail",
161 .gpio = 4,
162 .active_low = 1,
163 },
164 {
165 .name = "power",
166 .gpio = 0,
167 .active_low = 1,
168 .default_trigger = "default-on",
169
170 },
171 {
172 .name = "stop",
173 .gpio = 1,
174 .active_low = 1,
175 },
176 },
177};
178
179static struct board_info __initdata board_96348gw_10 = {
180 .name = "96348GW-10",
181 .expected_cpu_id = 0x6348,
182
183 .has_enet0 = 1,
184 .has_enet1 = 1,
185 .has_pci = 1,
186
187 .enet0 = {
188 .has_phy = 1,
189 .use_internal_phy = 1,
190 },
191 .enet1 = {
192 .force_speed_100 = 1,
193 .force_duplex_full = 1,
194 },
195
196 .has_ohci0 = 1,
197 .has_pccard = 1,
198 .has_ehci0 = 1,
199
200 .has_dsp = 1,
201 .dsp = {
202 .gpio_rst = 6,
203 .gpio_int = 34,
204 .cs = 2,
205 .ext_irq = 2,
206 },
207
208 .leds = {
209 {
210 .name = "adsl-fail",
211 .gpio = 2,
212 .active_low = 1,
213 },
214 {
215 .name = "ppp",
216 .gpio = 3,
217 .active_low = 1,
218 },
219 {
220 .name = "ppp-fail",
221 .gpio = 4,
222 .active_low = 1,
223 },
224 {
225 .name = "power",
226 .gpio = 0,
227 .active_low = 1,
228 .default_trigger = "default-on",
229 },
230 {
231 .name = "stop",
232 .gpio = 1,
233 .active_low = 1,
234 },
235 },
236};
237
238static struct board_info __initdata board_96348gw_11 = {
239 .name = "96348GW-11",
240 .expected_cpu_id = 0x6348,
241
242 .has_enet0 = 1,
243 .has_enet1 = 1,
244 .has_pci = 1,
245
246 .enet0 = {
247 .has_phy = 1,
248 .use_internal_phy = 1,
249 },
250
251 .enet1 = {
252 .force_speed_100 = 1,
253 .force_duplex_full = 1,
254 },
255
256
257 .has_ohci0 = 1,
258 .has_pccard = 1,
259 .has_ehci0 = 1,
260
261 .leds = {
262 {
263 .name = "adsl-fail",
264 .gpio = 2,
265 .active_low = 1,
266 },
267 {
268 .name = "ppp",
269 .gpio = 3,
270 .active_low = 1,
271 },
272 {
273 .name = "ppp-fail",
274 .gpio = 4,
275 .active_low = 1,
276 },
277 {
278 .name = "power",
279 .gpio = 0,
280 .active_low = 1,
281 .default_trigger = "default-on",
282 },
283 {
284 .name = "stop",
285 .gpio = 1,
286 .active_low = 1,
287 },
288 },
289};
290
291static struct board_info __initdata board_96348gw = {
292 .name = "96348GW",
293 .expected_cpu_id = 0x6348,
294
295 .has_enet0 = 1,
296 .has_enet1 = 1,
297 .has_pci = 1,
298
299 .enet0 = {
300 .has_phy = 1,
301 .use_internal_phy = 1,
302 },
303 .enet1 = {
304 .force_speed_100 = 1,
305 .force_duplex_full = 1,
306 },
307
308 .has_ohci0 = 1,
309
310 .has_dsp = 1,
311 .dsp = {
312 .gpio_rst = 6,
313 .gpio_int = 34,
314 .ext_irq = 2,
315 .cs = 2,
316 },
317
318 .leds = {
319 {
320 .name = "adsl-fail",
321 .gpio = 2,
322 .active_low = 1,
323 },
324 {
325 .name = "ppp",
326 .gpio = 3,
327 .active_low = 1,
328 },
329 {
330 .name = "ppp-fail",
331 .gpio = 4,
332 .active_low = 1,
333 },
334 {
335 .name = "power",
336 .gpio = 0,
337 .active_low = 1,
338 .default_trigger = "default-on",
339 },
340 {
341 .name = "stop",
342 .gpio = 1,
343 .active_low = 1,
344 },
345 },
346};
347
348static struct board_info __initdata board_FAST2404 = {
349 .name = "F@ST2404",
350 .expected_cpu_id = 0x6348,
351
352 .has_enet0 = 1,
353 .has_enet1 = 1,
354 .has_pci = 1,
355
356 .enet0 = {
357 .has_phy = 1,
358 .use_internal_phy = 1,
359 },
360
361 .enet1 = {
362 .force_speed_100 = 1,
363 .force_duplex_full = 1,
364 },
365
366
367 .has_ohci0 = 1,
368 .has_pccard = 1,
369 .has_ehci0 = 1,
370};
371
372static struct board_info __initdata board_DV201AMR = {
373 .name = "DV201AMR",
374 .expected_cpu_id = 0x6348,
375
376 .has_pci = 1,
377 .has_ohci0 = 1,
378
379 .has_enet0 = 1,
380 .has_enet1 = 1,
381 .enet0 = {
382 .has_phy = 1,
383 .use_internal_phy = 1,
384 },
385 .enet1 = {
386 .force_speed_100 = 1,
387 .force_duplex_full = 1,
388 },
389};
390
391static struct board_info __initdata board_96348gw_a = {
392 .name = "96348GW-A",
393 .expected_cpu_id = 0x6348,
394
395 .has_enet0 = 1,
396 .has_enet1 = 1,
397 .has_pci = 1,
398
399 .enet0 = {
400 .has_phy = 1,
401 .use_internal_phy = 1,
402 },
403 .enet1 = {
404 .force_speed_100 = 1,
405 .force_duplex_full = 1,
406 },
407
408 .has_ohci0 = 1,
409};
410#endif
411
412/*
413 * known 6358 boards
414 */
415#ifdef CONFIG_BCM63XX_CPU_6358
416static struct board_info __initdata board_96358vw = {
417 .name = "96358VW",
418 .expected_cpu_id = 0x6358,
419
420 .has_enet0 = 1,
421 .has_enet1 = 1,
422 .has_pci = 1,
423
424 .enet0 = {
425 .has_phy = 1,
426 .use_internal_phy = 1,
427 },
428
429 .enet1 = {
430 .force_speed_100 = 1,
431 .force_duplex_full = 1,
432 },
433
434
435 .has_ohci0 = 1,
436 .has_pccard = 1,
437 .has_ehci0 = 1,
438
439 .leds = {
440 {
441 .name = "adsl-fail",
442 .gpio = 15,
443 .active_low = 1,
444 },
445 {
446 .name = "ppp",
447 .gpio = 22,
448 .active_low = 1,
449 },
450 {
451 .name = "ppp-fail",
452 .gpio = 23,
453 .active_low = 1,
454 },
455 {
456 .name = "power",
457 .gpio = 4,
458 .default_trigger = "default-on",
459 },
460 {
461 .name = "stop",
462 .gpio = 5,
463 },
464 },
465};
466
467static struct board_info __initdata board_96358vw2 = {
468 .name = "96358VW2",
469 .expected_cpu_id = 0x6358,
470
471 .has_enet0 = 1,
472 .has_enet1 = 1,
473 .has_pci = 1,
474
475 .enet0 = {
476 .has_phy = 1,
477 .use_internal_phy = 1,
478 },
479
480 .enet1 = {
481 .force_speed_100 = 1,
482 .force_duplex_full = 1,
483 },
484
485
486 .has_ohci0 = 1,
487 .has_pccard = 1,
488 .has_ehci0 = 1,
489
490 .leds = {
491 {
492 .name = "adsl",
493 .gpio = 22,
494 .active_low = 1,
495 },
496 {
497 .name = "ppp-fail",
498 .gpio = 23,
499 },
500 {
501 .name = "power",
502 .gpio = 5,
503 .active_low = 1,
504 .default_trigger = "default-on",
505 },
506 {
507 .name = "stop",
508 .gpio = 4,
509 .active_low = 1,
510 },
511 },
512};
513
514static struct board_info __initdata board_AGPFS0 = {
515 .name = "AGPF-S0",
516 .expected_cpu_id = 0x6358,
517
518 .has_enet0 = 1,
519 .has_enet1 = 1,
520 .has_pci = 1,
521
522 .enet0 = {
523 .has_phy = 1,
524 .use_internal_phy = 1,
525 },
526
527 .enet1 = {
528 .force_speed_100 = 1,
529 .force_duplex_full = 1,
530 },
531
532 .has_ohci0 = 1,
533 .has_ehci0 = 1,
534};
535#endif
536
537/*
538 * all boards
539 */
540static const struct board_info __initdata *bcm963xx_boards[] = {
541#ifdef CONFIG_BCM63XX_CPU_6338
542 &board_96338gw,
543 &board_96338w,
544#endif
545#ifdef CONFIG_BCM63XX_CPU_6345
546 &board_96345gw2,
547#endif
548#ifdef CONFIG_BCM63XX_CPU_6348
549 &board_96348r,
550 &board_96348gw,
551 &board_96348gw_10,
552 &board_96348gw_11,
553 &board_FAST2404,
554 &board_DV201AMR,
555 &board_96348gw_a,
556#endif
557
558#ifdef CONFIG_BCM63XX_CPU_6358
559 &board_96358vw,
560 &board_96358vw2,
561 &board_AGPFS0,
562#endif
563};
564
565/*
566 * early init callback, read nvram data from flash and checksum it
567 */
568void __init board_prom_init(void)
569{
570 unsigned int check_len, i;
571 u8 *boot_addr, *cfe, *p;
572 char cfe_version[32];
573 u32 val;
574
575 /* read base address of boot chip select (0)
576 * 6345 does not have MPI but boots from standard
577 * MIPS Flash address */
578 if (BCMCPU_IS_6345())
579 val = 0x1fc00000;
580 else {
581 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
582 val &= MPI_CSBASE_BASE_MASK;
583 }
584 boot_addr = (u8 *)KSEG1ADDR(val);
585
586 /* dump cfe version */
587 cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
588 if (!memcmp(cfe, "cfe-v", 5))
589 snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
590 cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
591 else
592 strcpy(cfe_version, "unknown");
593 printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
594
595 /* extract nvram data */
596 memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram));
597
598 /* check checksum before using data */
599 if (nvram.version <= 4)
600 check_len = offsetof(struct bcm963xx_nvram, checksum_old);
601 else
602 check_len = sizeof(nvram);
603 val = 0;
604 p = (u8 *)&nvram;
605 while (check_len--)
606 val += *p;
607 if (val) {
608 printk(KERN_ERR PFX "invalid nvram checksum\n");
609 return;
610 }
611
612 /* find board by name */
613 for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
614 if (strncmp(nvram.name, bcm963xx_boards[i]->name,
615 sizeof(nvram.name)))
616 continue;
617 /* copy, board desc array is marked initdata */
618 memcpy(&board, bcm963xx_boards[i], sizeof(board));
619 break;
620 }
621
622 /* bail out if board is not found, will complain later */
623 if (!board.name[0]) {
624 char name[17];
625 memcpy(name, nvram.name, 16);
626 name[16] = 0;
627 printk(KERN_ERR PFX "unknown bcm963xx board: %s\n",
628 name);
629 return;
630 }
631
632 /* setup pin multiplexing depending on board enabled device,
633 * this has to be done this early since PCI init is done
634 * inside arch_initcall */
635 val = 0;
636
637#ifdef CONFIG_PCI
638 if (board.has_pci) {
639 bcm63xx_pci_enabled = 1;
640 if (BCMCPU_IS_6348())
641 val |= GPIO_MODE_6348_G2_PCI;
642 }
643#endif
644
645 if (board.has_pccard) {
646 if (BCMCPU_IS_6348())
647 val |= GPIO_MODE_6348_G1_MII_PCCARD;
648 }
649
650 if (board.has_enet0 && !board.enet0.use_internal_phy) {
651 if (BCMCPU_IS_6348())
652 val |= GPIO_MODE_6348_G3_EXT_MII |
653 GPIO_MODE_6348_G0_EXT_MII;
654 }
655
656 if (board.has_enet1 && !board.enet1.use_internal_phy) {
657 if (BCMCPU_IS_6348())
658 val |= GPIO_MODE_6348_G3_EXT_MII |
659 GPIO_MODE_6348_G0_EXT_MII;
660 }
661
662 bcm_gpio_writel(val, GPIO_MODE_REG);
663}
664
665/*
666 * second stage init callback, good time to panic if we couldn't
667 * identify on which board we're running since early printk is working
668 */
669void __init board_setup(void)
670{
671 if (!board.name[0])
672 panic("unable to detect bcm963xx board");
673 printk(KERN_INFO PFX "board name: %s\n", board.name);
674
675 /* make sure we're running on expected cpu */
676 if (bcm63xx_get_cpu_id() != board.expected_cpu_id)
677 panic("unexpected CPU for bcm963xx board");
678}
679
680/*
681 * return board name for /proc/cpuinfo
682 */
683const char *board_get_name(void)
684{
685 return board.name;
686}
687
688/*
689 * register & return a new board mac address
690 */
691static int board_get_mac_address(u8 *mac)
692{
693 u8 *p;
694 int count;
695
696 if (mac_addr_used >= nvram.mac_addr_count) {
697 printk(KERN_ERR PFX "not enough mac address\n");
698 return -ENODEV;
699 }
700
701 memcpy(mac, nvram.mac_addr_base, ETH_ALEN);
702 p = mac + ETH_ALEN - 1;
703 count = mac_addr_used;
704
705 while (count--) {
706 do {
707 (*p)++;
708 if (*p != 0)
709 break;
710 p--;
711 } while (p != mac);
712 }
713
714 if (p == mac) {
715 printk(KERN_ERR PFX "unable to fetch mac address\n");
716 return -ENODEV;
717 }
718
719 mac_addr_used++;
720 return 0;
721}
722
723static struct mtd_partition mtd_partitions[] = {
724 {
725 .name = "cfe",
726 .offset = 0x0,
727 .size = 0x40000,
728 }
729};
730
731static struct physmap_flash_data flash_data = {
732 .width = 2,
733 .nr_parts = ARRAY_SIZE(mtd_partitions),
734 .parts = mtd_partitions,
735};
736
737static struct resource mtd_resources[] = {
738 {
739 .start = 0, /* filled at runtime */
740 .end = 0, /* filled at runtime */
741 .flags = IORESOURCE_MEM,
742 }
743};
744
745static struct platform_device mtd_dev = {
746 .name = "physmap-flash",
747 .resource = mtd_resources,
748 .num_resources = ARRAY_SIZE(mtd_resources),
749 .dev = {
750 .platform_data = &flash_data,
751 },
752};
753
754/*
755 * Register a sane SPROMv2 to make the on-board
756 * bcm4318 WLAN work
757 */
758#ifdef CONFIG_SSB_PCIHOST
759static struct ssb_sprom bcm63xx_sprom = {
760 .revision = 0x02,
761 .board_rev = 0x17,
762 .country_code = 0x0,
763 .ant_available_bg = 0x3,
764 .pa0b0 = 0x15ae,
765 .pa0b1 = 0xfa85,
766 .pa0b2 = 0xfe8d,
767 .pa1b0 = 0xffff,
768 .pa1b1 = 0xffff,
769 .pa1b2 = 0xffff,
770 .gpio0 = 0xff,
771 .gpio1 = 0xff,
772 .gpio2 = 0xff,
773 .gpio3 = 0xff,
774 .maxpwr_bg = 0x004c,
775 .itssi_bg = 0x00,
776 .boardflags_lo = 0x2848,
777 .boardflags_hi = 0x0000,
778};
779#endif
780
781static struct gpio_led_platform_data bcm63xx_led_data;
782
783static struct platform_device bcm63xx_gpio_leds = {
784 .name = "leds-gpio",
785 .id = 0,
786 .dev.platform_data = &bcm63xx_led_data,
787};
788
789/*
790 * third stage init callback, register all board devices.
791 */
792int __init board_register_devices(void)
793{
794 u32 val;
795
796 if (board.has_enet0 &&
797 !board_get_mac_address(board.enet0.mac_addr))
798 bcm63xx_enet_register(0, &board.enet0);
799
800 if (board.has_enet1 &&
801 !board_get_mac_address(board.enet1.mac_addr))
802 bcm63xx_enet_register(1, &board.enet1);
803
804 if (board.has_dsp)
805 bcm63xx_dsp_register(&board.dsp);
806
807 /* Generate MAC address for WLAN and
808 * register our SPROM */
809#ifdef CONFIG_SSB_PCIHOST
810 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
811 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
812 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
813 if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0)
814 printk(KERN_ERR "failed to register fallback SPROM\n");
815 }
816#endif
817
818 /* read base address of boot chip select (0) */
819 if (BCMCPU_IS_6345())
820 val = 0x1fc00000;
821 else {
822 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
823 val &= MPI_CSBASE_BASE_MASK;
824 }
825 mtd_resources[0].start = val;
826 mtd_resources[0].end = 0x1FFFFFFF;
827
828 platform_device_register(&mtd_dev);
829
830 bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
831 bcm63xx_led_data.leds = board.leds;
832
833 platform_device_register(&bcm63xx_gpio_leds);
834
835 return 0;
836}
837
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
new file mode 100644
index 000000000000..2c68ee9ccee2
--- /dev/null
+++ b/arch/mips/bcm63xx/clk.c
@@ -0,0 +1,226 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/module.h>
10#include <linux/mutex.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h>
16#include <bcm63xx_clk.h>
17
18static DEFINE_MUTEX(clocks_mutex);
19
20
21static void clk_enable_unlocked(struct clk *clk)
22{
23 if (clk->set && (clk->usage++) == 0)
24 clk->set(clk, 1);
25}
26
27static void clk_disable_unlocked(struct clk *clk)
28{
29 if (clk->set && (--clk->usage) == 0)
30 clk->set(clk, 0);
31}
32
33static void bcm_hwclock_set(u32 mask, int enable)
34{
35 u32 reg;
36
37 reg = bcm_perf_readl(PERF_CKCTL_REG);
38 if (enable)
39 reg |= mask;
40 else
41 reg &= ~mask;
42 bcm_perf_writel(reg, PERF_CKCTL_REG);
43}
44
45/*
46 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
47 */
48static void enet_misc_set(struct clk *clk, int enable)
49{
50 u32 mask;
51
52 if (BCMCPU_IS_6338())
53 mask = CKCTL_6338_ENET_EN;
54 else if (BCMCPU_IS_6345())
55 mask = CKCTL_6345_ENET_EN;
56 else if (BCMCPU_IS_6348())
57 mask = CKCTL_6348_ENET_EN;
58 else
59 /* BCMCPU_IS_6358 */
60 mask = CKCTL_6358_EMUSB_EN;
61 bcm_hwclock_set(mask, enable);
62}
63
64static struct clk clk_enet_misc = {
65 .set = enet_misc_set,
66};
67
68/*
69 * Ethernet MAC clocks: only revelant on 6358, silently enable misc
70 * clocks
71 */
72static void enetx_set(struct clk *clk, int enable)
73{
74 if (enable)
75 clk_enable_unlocked(&clk_enet_misc);
76 else
77 clk_disable_unlocked(&clk_enet_misc);
78
79 if (BCMCPU_IS_6358()) {
80 u32 mask;
81
82 if (clk->id == 0)
83 mask = CKCTL_6358_ENET0_EN;
84 else
85 mask = CKCTL_6358_ENET1_EN;
86 bcm_hwclock_set(mask, enable);
87 }
88}
89
90static struct clk clk_enet0 = {
91 .id = 0,
92 .set = enetx_set,
93};
94
95static struct clk clk_enet1 = {
96 .id = 1,
97 .set = enetx_set,
98};
99
100/*
101 * Ethernet PHY clock
102 */
103static void ephy_set(struct clk *clk, int enable)
104{
105 if (!BCMCPU_IS_6358())
106 return;
107 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
108}
109
110
111static struct clk clk_ephy = {
112 .set = ephy_set,
113};
114
115/*
116 * PCM clock
117 */
118static void pcm_set(struct clk *clk, int enable)
119{
120 if (!BCMCPU_IS_6358())
121 return;
122 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
123}
124
125static struct clk clk_pcm = {
126 .set = pcm_set,
127};
128
129/*
130 * USB host clock
131 */
132static void usbh_set(struct clk *clk, int enable)
133{
134 if (!BCMCPU_IS_6348())
135 return;
136 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
137}
138
139static struct clk clk_usbh = {
140 .set = usbh_set,
141};
142
143/*
144 * SPI clock
145 */
146static void spi_set(struct clk *clk, int enable)
147{
148 u32 mask;
149
150 if (BCMCPU_IS_6338())
151 mask = CKCTL_6338_SPI_EN;
152 else if (BCMCPU_IS_6348())
153 mask = CKCTL_6348_SPI_EN;
154 else
155 /* BCMCPU_IS_6358 */
156 mask = CKCTL_6358_SPI_EN;
157 bcm_hwclock_set(mask, enable);
158}
159
160static struct clk clk_spi = {
161 .set = spi_set,
162};
163
164/*
165 * Internal peripheral clock
166 */
167static struct clk clk_periph = {
168 .rate = (50 * 1000 * 1000),
169};
170
171
172/*
173 * Linux clock API implementation
174 */
175int clk_enable(struct clk *clk)
176{
177 mutex_lock(&clocks_mutex);
178 clk_enable_unlocked(clk);
179 mutex_unlock(&clocks_mutex);
180 return 0;
181}
182
183EXPORT_SYMBOL(clk_enable);
184
185void clk_disable(struct clk *clk)
186{
187 mutex_lock(&clocks_mutex);
188 clk_disable_unlocked(clk);
189 mutex_unlock(&clocks_mutex);
190}
191
192EXPORT_SYMBOL(clk_disable);
193
194unsigned long clk_get_rate(struct clk *clk)
195{
196 return clk->rate;
197}
198
199EXPORT_SYMBOL(clk_get_rate);
200
201struct clk *clk_get(struct device *dev, const char *id)
202{
203 if (!strcmp(id, "enet0"))
204 return &clk_enet0;
205 if (!strcmp(id, "enet1"))
206 return &clk_enet1;
207 if (!strcmp(id, "ephy"))
208 return &clk_ephy;
209 if (!strcmp(id, "usbh"))
210 return &clk_usbh;
211 if (!strcmp(id, "spi"))
212 return &clk_spi;
213 if (!strcmp(id, "periph"))
214 return &clk_periph;
215 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
216 return &clk_pcm;
217 return ERR_PTR(-ENOENT);
218}
219
220EXPORT_SYMBOL(clk_get);
221
222void clk_put(struct clk *clk)
223{
224}
225
226EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
new file mode 100644
index 000000000000..6dc43f0483e8
--- /dev/null
+++ b/arch/mips/bcm63xx/cpu.c
@@ -0,0 +1,345 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/cpu.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_regs.h>
15#include <bcm63xx_io.h>
16#include <bcm63xx_irq.h>
17
18const unsigned long *bcm63xx_regs_base;
19EXPORT_SYMBOL(bcm63xx_regs_base);
20
21const int *bcm63xx_irqs;
22EXPORT_SYMBOL(bcm63xx_irqs);
23
24static u16 bcm63xx_cpu_id;
25static u16 bcm63xx_cpu_rev;
26static unsigned int bcm63xx_cpu_freq;
27static unsigned int bcm63xx_memory_size;
28
29/*
30 * 6338 register sets and irqs
31 */
32static const unsigned long bcm96338_regs_base[] = {
33 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
34 [RSET_PERF] = BCM_6338_PERF_BASE,
35 [RSET_TIMER] = BCM_6338_TIMER_BASE,
36 [RSET_WDT] = BCM_6338_WDT_BASE,
37 [RSET_UART0] = BCM_6338_UART0_BASE,
38 [RSET_GPIO] = BCM_6338_GPIO_BASE,
39 [RSET_SPI] = BCM_6338_SPI_BASE,
40 [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
41 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
42 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
43 [RSET_UDC0] = BCM_6338_UDC0_BASE,
44 [RSET_MPI] = BCM_6338_MPI_BASE,
45 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
46 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
47 [RSET_DSL] = BCM_6338_DSL_BASE,
48 [RSET_ENET0] = BCM_6338_ENET0_BASE,
49 [RSET_ENET1] = BCM_6338_ENET1_BASE,
50 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
51 [RSET_MEMC] = BCM_6338_MEMC_BASE,
52 [RSET_DDR] = BCM_6338_DDR_BASE,
53};
54
55static const int bcm96338_irqs[] = {
56 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
57 [IRQ_UART0] = BCM_6338_UART0_IRQ,
58 [IRQ_DSL] = BCM_6338_DSL_IRQ,
59 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
60 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
61 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
62 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
63};
64
65/*
66 * 6345 register sets and irqs
67 */
68static const unsigned long bcm96345_regs_base[] = {
69 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
70 [RSET_PERF] = BCM_6345_PERF_BASE,
71 [RSET_TIMER] = BCM_6345_TIMER_BASE,
72 [RSET_WDT] = BCM_6345_WDT_BASE,
73 [RSET_UART0] = BCM_6345_UART0_BASE,
74 [RSET_GPIO] = BCM_6345_GPIO_BASE,
75 [RSET_SPI] = BCM_6345_SPI_BASE,
76 [RSET_UDC0] = BCM_6345_UDC0_BASE,
77 [RSET_OHCI0] = BCM_6345_OHCI0_BASE,
78 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
79 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
80 [RSET_MPI] = BCM_6345_MPI_BASE,
81 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
82 [RSET_DSL] = BCM_6345_DSL_BASE,
83 [RSET_ENET0] = BCM_6345_ENET0_BASE,
84 [RSET_ENET1] = BCM_6345_ENET1_BASE,
85 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
86 [RSET_EHCI0] = BCM_6345_EHCI0_BASE,
87 [RSET_SDRAM] = BCM_6345_SDRAM_BASE,
88 [RSET_MEMC] = BCM_6345_MEMC_BASE,
89 [RSET_DDR] = BCM_6345_DDR_BASE,
90};
91
92static const int bcm96345_irqs[] = {
93 [IRQ_TIMER] = BCM_6345_TIMER_IRQ,
94 [IRQ_UART0] = BCM_6345_UART0_IRQ,
95 [IRQ_DSL] = BCM_6345_DSL_IRQ,
96 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
97 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
98 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
99 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
100};
101
102/*
103 * 6348 register sets and irqs
104 */
105static const unsigned long bcm96348_regs_base[] = {
106 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
107 [RSET_PERF] = BCM_6348_PERF_BASE,
108 [RSET_TIMER] = BCM_6348_TIMER_BASE,
109 [RSET_WDT] = BCM_6348_WDT_BASE,
110 [RSET_UART0] = BCM_6348_UART0_BASE,
111 [RSET_GPIO] = BCM_6348_GPIO_BASE,
112 [RSET_SPI] = BCM_6348_SPI_BASE,
113 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
114 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
115 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
116 [RSET_MPI] = BCM_6348_MPI_BASE,
117 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
118 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
119 [RSET_DSL] = BCM_6348_DSL_BASE,
120 [RSET_ENET0] = BCM_6348_ENET0_BASE,
121 [RSET_ENET1] = BCM_6348_ENET1_BASE,
122 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
123 [RSET_MEMC] = BCM_6348_MEMC_BASE,
124 [RSET_DDR] = BCM_6348_DDR_BASE,
125};
126
127static const int bcm96348_irqs[] = {
128 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
129 [IRQ_UART0] = BCM_6348_UART0_IRQ,
130 [IRQ_DSL] = BCM_6348_DSL_IRQ,
131 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
132 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
133 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
134 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
135 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
136 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
137 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
138 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
139 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
140 [IRQ_PCI] = BCM_6348_PCI_IRQ,
141};
142
143/*
144 * 6358 register sets and irqs
145 */
146static const unsigned long bcm96358_regs_base[] = {
147 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
148 [RSET_PERF] = BCM_6358_PERF_BASE,
149 [RSET_TIMER] = BCM_6358_TIMER_BASE,
150 [RSET_WDT] = BCM_6358_WDT_BASE,
151 [RSET_UART0] = BCM_6358_UART0_BASE,
152 [RSET_GPIO] = BCM_6358_GPIO_BASE,
153 [RSET_SPI] = BCM_6358_SPI_BASE,
154 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
155 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
156 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
157 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
158 [RSET_MPI] = BCM_6358_MPI_BASE,
159 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
160 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
161 [RSET_DSL] = BCM_6358_DSL_BASE,
162 [RSET_ENET0] = BCM_6358_ENET0_BASE,
163 [RSET_ENET1] = BCM_6358_ENET1_BASE,
164 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
165 [RSET_MEMC] = BCM_6358_MEMC_BASE,
166 [RSET_DDR] = BCM_6358_DDR_BASE,
167};
168
169static const int bcm96358_irqs[] = {
170 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
171 [IRQ_UART0] = BCM_6358_UART0_IRQ,
172 [IRQ_DSL] = BCM_6358_DSL_IRQ,
173 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
174 [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
175 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
176 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
177 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
178 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
179 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
180 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
181 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
182 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
183 [IRQ_PCI] = BCM_6358_PCI_IRQ,
184};
185
186u16 __bcm63xx_get_cpu_id(void)
187{
188 return bcm63xx_cpu_id;
189}
190
191EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
192
193u16 bcm63xx_get_cpu_rev(void)
194{
195 return bcm63xx_cpu_rev;
196}
197
198EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
199
200unsigned int bcm63xx_get_cpu_freq(void)
201{
202 return bcm63xx_cpu_freq;
203}
204
205unsigned int bcm63xx_get_memory_size(void)
206{
207 return bcm63xx_memory_size;
208}
209
210static unsigned int detect_cpu_clock(void)
211{
212 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
213
214 /* BCM6338 has a fixed 240 Mhz frequency */
215 if (BCMCPU_IS_6338())
216 return 240000000;
217
218 /* BCM6345 has a fixed 140Mhz frequency */
219 if (BCMCPU_IS_6345())
220 return 140000000;
221
222 /*
223 * frequency depends on PLL configuration:
224 */
225 if (BCMCPU_IS_6348()) {
226 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
227 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
228 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
229 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
230 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
231 n1 += 1;
232 n2 += 2;
233 m1 += 1;
234 }
235
236 if (BCMCPU_IS_6358()) {
237 /* 16MHz * N1 * N2 / M1_CPU */
238 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
239 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
240 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
241 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
242 }
243
244 return (16 * 1000000 * n1 * n2) / m1;
245}
246
247/*
248 * attempt to detect the amount of memory installed
249 */
250static unsigned int detect_memory_size(void)
251{
252 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
253 u32 val;
254
255 if (BCMCPU_IS_6345())
256 return (8 * 1024 * 1024);
257
258 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
259 val = bcm_sdram_readl(SDRAM_CFG_REG);
260 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
261 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
262 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
263 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
264 }
265
266 if (BCMCPU_IS_6358()) {
267 val = bcm_memc_readl(MEMC_CFG_REG);
268 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
269 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
270 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
271 banks = 2;
272 }
273
274 /* 0 => 11 address bits ... 2 => 13 address bits */
275 rows += 11;
276
277 /* 0 => 8 address bits ... 2 => 10 address bits */
278 cols += 8;
279
280 return 1 << (cols + rows + (is_32bits + 1) + banks);
281}
282
283void __init bcm63xx_cpu_init(void)
284{
285 unsigned int tmp, expected_cpu_id;
286 struct cpuinfo_mips *c = &current_cpu_data;
287
288 /* soc registers location depends on cpu type */
289 expected_cpu_id = 0;
290
291 switch (c->cputype) {
292 /*
293 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
294 */
295 case CPU_BCM3302:
296 expected_cpu_id = BCM6338_CPU_ID;
297 bcm63xx_regs_base = bcm96338_regs_base;
298 bcm63xx_irqs = bcm96338_irqs;
299 break;
300 case CPU_BCM6345:
301 expected_cpu_id = BCM6345_CPU_ID;
302 bcm63xx_regs_base = bcm96345_regs_base;
303 bcm63xx_irqs = bcm96345_irqs;
304 break;
305 case CPU_BCM6348:
306 expected_cpu_id = BCM6348_CPU_ID;
307 bcm63xx_regs_base = bcm96348_regs_base;
308 bcm63xx_irqs = bcm96348_irqs;
309 break;
310 case CPU_BCM6358:
311 expected_cpu_id = BCM6358_CPU_ID;
312 bcm63xx_regs_base = bcm96358_regs_base;
313 bcm63xx_irqs = bcm96358_irqs;
314 break;
315 }
316
317 /*
318 * really early to panic, but delaying panic would not help since we
319 * will never get any working console
320 */
321 if (!expected_cpu_id)
322 panic("unsupported Broadcom CPU");
323
324 /*
325 * bcm63xx_regs_base is set, we can access soc registers
326 */
327
328 /* double check CPU type */
329 tmp = bcm_perf_readl(PERF_REV_REG);
330 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
331 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
332
333 if (bcm63xx_cpu_id != expected_cpu_id)
334 panic("bcm63xx CPU id mismatch");
335
336 bcm63xx_cpu_freq = detect_cpu_clock();
337 bcm63xx_memory_size = detect_memory_size();
338
339 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
340 bcm63xx_cpu_id, bcm63xx_cpu_rev);
341 printk(KERN_INFO "CPU frequency is %u MHz\n",
342 bcm63xx_cpu_freq / 1000000);
343 printk(KERN_INFO "%uMB of RAM installed\n",
344 bcm63xx_memory_size >> 20);
345}
diff --git a/arch/mips/bcm63xx/cs.c b/arch/mips/bcm63xx/cs.c
new file mode 100644
index 000000000000..50d8190bbf7b
--- /dev/null
+++ b/arch/mips/bcm63xx/cs.c
@@ -0,0 +1,144 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <linux/log2.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h>
16#include <bcm63xx_cs.h>
17
18static DEFINE_SPINLOCK(bcm63xx_cs_lock);
19
20/*
21 * check if given chip select exists
22 */
23static int is_valid_cs(unsigned int cs)
24{
25 if (cs > 6)
26 return 0;
27 return 1;
28}
29
30/*
31 * Configure chipselect base address and size (bytes).
32 * Size must be a power of two between 8k and 256M.
33 */
34int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
35{
36 unsigned long flags;
37 u32 val;
38
39 if (!is_valid_cs(cs))
40 return -EINVAL;
41
42 /* sanity check on size */
43 if (size != roundup_pow_of_two(size))
44 return -EINVAL;
45
46 if (size < 8 * 1024 || size > 256 * 1024 * 1024)
47 return -EINVAL;
48
49 val = (base & MPI_CSBASE_BASE_MASK);
50 /* 8k => 0 - 256M => 15 */
51 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
52
53 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
54 bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
55 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
56
57 return 0;
58}
59
60EXPORT_SYMBOL(bcm63xx_set_cs_base);
61
62/*
63 * configure chipselect timing (ns)
64 */
65int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
66 unsigned int setup, unsigned int hold)
67{
68 unsigned long flags;
69 u32 val;
70
71 if (!is_valid_cs(cs))
72 return -EINVAL;
73
74 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
75 val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
76 val &= ~(MPI_CSCTL_WAIT_MASK);
77 val &= ~(MPI_CSCTL_SETUP_MASK);
78 val &= ~(MPI_CSCTL_HOLD_MASK);
79 val |= wait << MPI_CSCTL_WAIT_SHIFT;
80 val |= setup << MPI_CSCTL_SETUP_SHIFT;
81 val |= hold << MPI_CSCTL_HOLD_SHIFT;
82 bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
83 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
84
85 return 0;
86}
87
88EXPORT_SYMBOL(bcm63xx_set_cs_timing);
89
90/*
91 * configure other chipselect parameter (data bus size, ...)
92 */
93int bcm63xx_set_cs_param(unsigned int cs, u32 params)
94{
95 unsigned long flags;
96 u32 val;
97
98 if (!is_valid_cs(cs))
99 return -EINVAL;
100
101 /* none of this fields apply to pcmcia */
102 if (cs == MPI_CS_PCMCIA_COMMON ||
103 cs == MPI_CS_PCMCIA_ATTR ||
104 cs == MPI_CS_PCMCIA_IO)
105 return -EINVAL;
106
107 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
108 val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
109 val &= ~(MPI_CSCTL_DATA16_MASK);
110 val &= ~(MPI_CSCTL_SYNCMODE_MASK);
111 val &= ~(MPI_CSCTL_TSIZE_MASK);
112 val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
113 val |= params;
114 bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
115 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
116
117 return 0;
118}
119
120EXPORT_SYMBOL(bcm63xx_set_cs_param);
121
122/*
123 * set cs status (enable/disable)
124 */
125int bcm63xx_set_cs_status(unsigned int cs, int enable)
126{
127 unsigned long flags;
128 u32 val;
129
130 if (!is_valid_cs(cs))
131 return -EINVAL;
132
133 spin_lock_irqsave(&bcm63xx_cs_lock, flags);
134 val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
135 if (enable)
136 val |= MPI_CSCTL_ENABLE_MASK;
137 else
138 val &= ~MPI_CSCTL_ENABLE_MASK;
139 bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
140 spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
141 return 0;
142}
143
144EXPORT_SYMBOL(bcm63xx_set_cs_status);
diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c
new file mode 100644
index 000000000000..da46d1d3c77c
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-dsp.c
@@ -0,0 +1,56 @@
1/*
2 * Broadcom BCM63xx VoIP DSP registration
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14
15#include <bcm63xx_cpu.h>
16#include <bcm63xx_dev_dsp.h>
17#include <bcm63xx_regs.h>
18#include <bcm63xx_io.h>
19
20static struct resource voip_dsp_resources[] = {
21 {
22 .start = -1, /* filled at runtime */
23 .end = -1, /* filled at runtime */
24 .flags = IORESOURCE_MEM,
25 },
26 {
27 .start = -1, /* filled at runtime */
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32static struct platform_device bcm63xx_voip_dsp_device = {
33 .name = "bcm63xx-voip-dsp",
34 .id = 0,
35 .num_resources = ARRAY_SIZE(voip_dsp_resources),
36 .resource = voip_dsp_resources,
37};
38
39int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd)
40{
41 struct bcm63xx_dsp_platform_data *dpd;
42 u32 val;
43
44 /* Get the memory window */
45 val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1));
46 val &= MPI_CSBASE_BASE_MASK;
47 voip_dsp_resources[0].start = val;
48 voip_dsp_resources[0].end = val + 0xFFFFFFF;
49 voip_dsp_resources[1].start = pd->ext_irq;
50
51 /* copy given platform data */
52 dpd = bcm63xx_voip_dsp_device.dev.platform_data;
53 memcpy(dpd, pd, sizeof (*pd));
54
55 return platform_device_register(&bcm63xx_voip_dsp_device);
56}
diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c
new file mode 100644
index 000000000000..9f544badd0b4
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-enet.c
@@ -0,0 +1,159 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <bcm63xx_dev_enet.h>
13#include <bcm63xx_io.h>
14#include <bcm63xx_regs.h>
15
16static struct resource shared_res[] = {
17 {
18 .start = -1, /* filled at runtime */
19 .end = -1, /* filled at runtime */
20 .flags = IORESOURCE_MEM,
21 },
22};
23
24static struct platform_device bcm63xx_enet_shared_device = {
25 .name = "bcm63xx_enet_shared",
26 .id = 0,
27 .num_resources = ARRAY_SIZE(shared_res),
28 .resource = shared_res,
29};
30
31static int shared_device_registered;
32
33static struct resource enet0_res[] = {
34 {
35 .start = -1, /* filled at runtime */
36 .end = -1, /* filled at runtime */
37 .flags = IORESOURCE_MEM,
38 },
39 {
40 .start = -1, /* filled at runtime */
41 .flags = IORESOURCE_IRQ,
42 },
43 {
44 .start = -1, /* filled at runtime */
45 .flags = IORESOURCE_IRQ,
46 },
47 {
48 .start = -1, /* filled at runtime */
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct bcm63xx_enet_platform_data enet0_pd;
54
55static struct platform_device bcm63xx_enet0_device = {
56 .name = "bcm63xx_enet",
57 .id = 0,
58 .num_resources = ARRAY_SIZE(enet0_res),
59 .resource = enet0_res,
60 .dev = {
61 .platform_data = &enet0_pd,
62 },
63};
64
65static struct resource enet1_res[] = {
66 {
67 .start = -1, /* filled at runtime */
68 .end = -1, /* filled at runtime */
69 .flags = IORESOURCE_MEM,
70 },
71 {
72 .start = -1, /* filled at runtime */
73 .flags = IORESOURCE_IRQ,
74 },
75 {
76 .start = -1, /* filled at runtime */
77 .flags = IORESOURCE_IRQ,
78 },
79 {
80 .start = -1, /* filled at runtime */
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct bcm63xx_enet_platform_data enet1_pd;
86
87static struct platform_device bcm63xx_enet1_device = {
88 .name = "bcm63xx_enet",
89 .id = 1,
90 .num_resources = ARRAY_SIZE(enet1_res),
91 .resource = enet1_res,
92 .dev = {
93 .platform_data = &enet1_pd,
94 },
95};
96
97int __init bcm63xx_enet_register(int unit,
98 const struct bcm63xx_enet_platform_data *pd)
99{
100 struct platform_device *pdev;
101 struct bcm63xx_enet_platform_data *dpd;
102 int ret;
103
104 if (unit > 1)
105 return -ENODEV;
106
107 if (!shared_device_registered) {
108 shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
109 shared_res[0].end = shared_res[0].start;
110 if (BCMCPU_IS_6338())
111 shared_res[0].end += (RSET_ENETDMA_SIZE / 2) - 1;
112 else
113 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
114
115 ret = platform_device_register(&bcm63xx_enet_shared_device);
116 if (ret)
117 return ret;
118 shared_device_registered = 1;
119 }
120
121 if (unit == 0) {
122 enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
123 enet0_res[0].end = enet0_res[0].start;
124 enet0_res[0].end += RSET_ENET_SIZE - 1;
125 enet0_res[1].start = bcm63xx_get_irq_number(IRQ_ENET0);
126 enet0_res[2].start = bcm63xx_get_irq_number(IRQ_ENET0_RXDMA);
127 enet0_res[3].start = bcm63xx_get_irq_number(IRQ_ENET0_TXDMA);
128 pdev = &bcm63xx_enet0_device;
129 } else {
130 enet1_res[0].start = bcm63xx_regset_address(RSET_ENET1);
131 enet1_res[0].end = enet1_res[0].start;
132 enet1_res[0].end += RSET_ENET_SIZE - 1;
133 enet1_res[1].start = bcm63xx_get_irq_number(IRQ_ENET1);
134 enet1_res[2].start = bcm63xx_get_irq_number(IRQ_ENET1_RXDMA);
135 enet1_res[3].start = bcm63xx_get_irq_number(IRQ_ENET1_TXDMA);
136 pdev = &bcm63xx_enet1_device;
137 }
138
139 /* copy given platform data */
140 dpd = pdev->dev.platform_data;
141 memcpy(dpd, pd, sizeof(*pd));
142
143 /* adjust them in case internal phy is used */
144 if (dpd->use_internal_phy) {
145
146 /* internal phy only exists for enet0 */
147 if (unit == 1)
148 return -ENODEV;
149
150 dpd->phy_id = 1;
151 dpd->has_phy_interrupt = 1;
152 dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
153 }
154
155 ret = platform_device_register(pdev);
156 if (ret)
157 return ret;
158 return 0;
159}
diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
new file mode 100644
index 000000000000..bf353c937df2
--- /dev/null
+++ b/arch/mips/bcm63xx/early_printk.c
@@ -0,0 +1,30 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <bcm63xx_io.h>
11#include <bcm63xx_regs.h>
12
13static void __init wait_xfered(void)
14{
15 unsigned int val;
16
17 /* wait for any previous char to be transmitted */
18 do {
19 val = bcm_uart0_readl(UART_IR_REG);
20 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
21 break;
22 } while (1);
23}
24
25void __init prom_putchar(char c)
26{
27 wait_xfered();
28 bcm_uart0_writel(c, UART_FIFO_REG);
29 wait_xfered();
30}
diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
new file mode 100644
index 000000000000..87ca39046334
--- /dev/null
+++ b/arch/mips/bcm63xx/gpio.c
@@ -0,0 +1,134 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/spinlock.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15
16#include <bcm63xx_cpu.h>
17#include <bcm63xx_gpio.h>
18#include <bcm63xx_io.h>
19#include <bcm63xx_regs.h>
20
21static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
22static u32 gpio_out_low, gpio_out_high;
23
24static void bcm63xx_gpio_set(struct gpio_chip *chip,
25 unsigned gpio, int val)
26{
27 u32 reg;
28 u32 mask;
29 u32 *v;
30 unsigned long flags;
31
32 if (gpio >= chip->ngpio)
33 BUG();
34
35 if (gpio < 32) {
36 reg = GPIO_DATA_LO_REG;
37 mask = 1 << gpio;
38 v = &gpio_out_low;
39 } else {
40 reg = GPIO_DATA_HI_REG;
41 mask = 1 << (gpio - 32);
42 v = &gpio_out_high;
43 }
44
45 spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
46 if (val)
47 *v |= mask;
48 else
49 *v &= ~mask;
50 bcm_gpio_writel(*v, reg);
51 spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
52}
53
54static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
55{
56 u32 reg;
57 u32 mask;
58
59 if (gpio >= chip->ngpio)
60 BUG();
61
62 if (gpio < 32) {
63 reg = GPIO_DATA_LO_REG;
64 mask = 1 << gpio;
65 } else {
66 reg = GPIO_DATA_HI_REG;
67 mask = 1 << (gpio - 32);
68 }
69
70 return !!(bcm_gpio_readl(reg) & mask);
71}
72
73static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,
74 unsigned gpio, int dir)
75{
76 u32 reg;
77 u32 mask;
78 u32 tmp;
79 unsigned long flags;
80
81 if (gpio >= chip->ngpio)
82 BUG();
83
84 if (gpio < 32) {
85 reg = GPIO_CTL_LO_REG;
86 mask = 1 << gpio;
87 } else {
88 reg = GPIO_CTL_HI_REG;
89 mask = 1 << (gpio - 32);
90 }
91
92 spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
93 tmp = bcm_gpio_readl(reg);
94 if (dir == GPIO_DIR_IN)
95 tmp &= ~mask;
96 else
97 tmp |= mask;
98 bcm_gpio_writel(tmp, reg);
99 spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
100
101 return 0;
102}
103
104static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
105{
106 return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_IN);
107}
108
109static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,
110 unsigned gpio, int value)
111{
112 bcm63xx_gpio_set(chip, gpio, value);
113 return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT);
114}
115
116
117static struct gpio_chip bcm63xx_gpio_chip = {
118 .label = "bcm63xx-gpio",
119 .direction_input = bcm63xx_gpio_direction_input,
120 .direction_output = bcm63xx_gpio_direction_output,
121 .get = bcm63xx_gpio_get,
122 .set = bcm63xx_gpio_set,
123 .base = 0,
124};
125
126int __init bcm63xx_gpio_init(void)
127{
128 bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
129 pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
130
131 return gpiochip_add(&bcm63xx_gpio_chip);
132}
133
134arch_initcall(bcm63xx_gpio_init);
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
new file mode 100644
index 000000000000..a0c5cd18c192
--- /dev/null
+++ b/arch/mips/bcm63xx/irq.c
@@ -0,0 +1,253 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <asm/irq_cpu.h>
15#include <asm/mipsregs.h>
16#include <bcm63xx_cpu.h>
17#include <bcm63xx_regs.h>
18#include <bcm63xx_io.h>
19#include <bcm63xx_irq.h>
20
21/*
22 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
23 * prioritize any interrupt relatively to another. the static counter
24 * will resume the loop where it ended the last time we left this
25 * function.
26 */
27static void bcm63xx_irq_dispatch_internal(void)
28{
29 u32 pending;
30 static int i;
31
32 pending = bcm_perf_readl(PERF_IRQMASK_REG) &
33 bcm_perf_readl(PERF_IRQSTAT_REG);
34
35 if (!pending)
36 return ;
37
38 while (1) {
39 int to_call = i;
40
41 i = (i + 1) & 0x1f;
42 if (pending & (1 << to_call)) {
43 do_IRQ(to_call + IRQ_INTERNAL_BASE);
44 break;
45 }
46 }
47}
48
49asmlinkage void plat_irq_dispatch(void)
50{
51 u32 cause;
52
53 do {
54 cause = read_c0_cause() & read_c0_status() & ST0_IM;
55
56 if (!cause)
57 break;
58
59 if (cause & CAUSEF_IP7)
60 do_IRQ(7);
61 if (cause & CAUSEF_IP2)
62 bcm63xx_irq_dispatch_internal();
63 if (cause & CAUSEF_IP3)
64 do_IRQ(IRQ_EXT_0);
65 if (cause & CAUSEF_IP4)
66 do_IRQ(IRQ_EXT_1);
67 if (cause & CAUSEF_IP5)
68 do_IRQ(IRQ_EXT_2);
69 if (cause & CAUSEF_IP6)
70 do_IRQ(IRQ_EXT_3);
71 } while (1);
72}
73
74/*
75 * internal IRQs operations: only mask/unmask on PERF irq mask
76 * register.
77 */
78static inline void bcm63xx_internal_irq_mask(unsigned int irq)
79{
80 u32 mask;
81
82 irq -= IRQ_INTERNAL_BASE;
83 mask = bcm_perf_readl(PERF_IRQMASK_REG);
84 mask &= ~(1 << irq);
85 bcm_perf_writel(mask, PERF_IRQMASK_REG);
86}
87
88static void bcm63xx_internal_irq_unmask(unsigned int irq)
89{
90 u32 mask;
91
92 irq -= IRQ_INTERNAL_BASE;
93 mask = bcm_perf_readl(PERF_IRQMASK_REG);
94 mask |= (1 << irq);
95 bcm_perf_writel(mask, PERF_IRQMASK_REG);
96}
97
98static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
99{
100 bcm63xx_internal_irq_unmask(irq);
101 return 0;
102}
103
104/*
105 * external IRQs operations: mask/unmask and clear on PERF external
106 * irq control register.
107 */
108static void bcm63xx_external_irq_mask(unsigned int irq)
109{
110 u32 reg;
111
112 irq -= IRQ_EXT_BASE;
113 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
114 reg &= ~EXTIRQ_CFG_MASK(irq);
115 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
116}
117
118static void bcm63xx_external_irq_unmask(unsigned int irq)
119{
120 u32 reg;
121
122 irq -= IRQ_EXT_BASE;
123 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
124 reg |= EXTIRQ_CFG_MASK(irq);
125 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
126}
127
128static void bcm63xx_external_irq_clear(unsigned int irq)
129{
130 u32 reg;
131
132 irq -= IRQ_EXT_BASE;
133 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
134 reg |= EXTIRQ_CFG_CLEAR(irq);
135 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
136}
137
138static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
139{
140 set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
141 irq_enable_hazard();
142 bcm63xx_external_irq_unmask(irq);
143 return 0;
144}
145
146static void bcm63xx_external_irq_shutdown(unsigned int irq)
147{
148 bcm63xx_external_irq_mask(irq);
149 clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
150 irq_disable_hazard();
151}
152
153static int bcm63xx_external_irq_set_type(unsigned int irq,
154 unsigned int flow_type)
155{
156 u32 reg;
157 struct irq_desc *desc = irq_desc + irq;
158
159 irq -= IRQ_EXT_BASE;
160
161 flow_type &= IRQ_TYPE_SENSE_MASK;
162
163 if (flow_type == IRQ_TYPE_NONE)
164 flow_type = IRQ_TYPE_LEVEL_LOW;
165
166 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
167 switch (flow_type) {
168 case IRQ_TYPE_EDGE_BOTH:
169 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
170 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
171 break;
172
173 case IRQ_TYPE_EDGE_RISING:
174 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
175 reg |= EXTIRQ_CFG_SENSE(irq);
176 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
177 break;
178
179 case IRQ_TYPE_EDGE_FALLING:
180 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
181 reg &= ~EXTIRQ_CFG_SENSE(irq);
182 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
183 break;
184
185 case IRQ_TYPE_LEVEL_HIGH:
186 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
187 reg |= EXTIRQ_CFG_SENSE(irq);
188 break;
189
190 case IRQ_TYPE_LEVEL_LOW:
191 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
192 reg &= ~EXTIRQ_CFG_SENSE(irq);
193 break;
194
195 default:
196 printk(KERN_ERR "bogus flow type combination given !\n");
197 return -EINVAL;
198 }
199 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
200
201 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
202 desc->status |= IRQ_LEVEL;
203 desc->handle_irq = handle_level_irq;
204 } else {
205 desc->handle_irq = handle_edge_irq;
206 }
207
208 return 0;
209}
210
211static struct irq_chip bcm63xx_internal_irq_chip = {
212 .name = "bcm63xx_ipic",
213 .startup = bcm63xx_internal_irq_startup,
214 .shutdown = bcm63xx_internal_irq_mask,
215
216 .mask = bcm63xx_internal_irq_mask,
217 .mask_ack = bcm63xx_internal_irq_mask,
218 .unmask = bcm63xx_internal_irq_unmask,
219};
220
221static struct irq_chip bcm63xx_external_irq_chip = {
222 .name = "bcm63xx_epic",
223 .startup = bcm63xx_external_irq_startup,
224 .shutdown = bcm63xx_external_irq_shutdown,
225
226 .ack = bcm63xx_external_irq_clear,
227
228 .mask = bcm63xx_external_irq_mask,
229 .unmask = bcm63xx_external_irq_unmask,
230
231 .set_type = bcm63xx_external_irq_set_type,
232};
233
234static struct irqaction cpu_ip2_cascade_action = {
235 .handler = no_action,
236 .name = "cascade_ip2",
237};
238
239void __init arch_init_irq(void)
240{
241 int i;
242
243 mips_cpu_irq_init();
244 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
245 set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
246 handle_level_irq);
247
248 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
249 set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
250 handle_edge_irq);
251
252 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
253}
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
new file mode 100644
index 000000000000..fb284fbc5853
--- /dev/null
+++ b/arch/mips/bcm63xx/prom.c
@@ -0,0 +1,55 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <linux/bootmem.h>
11#include <asm/bootinfo.h>
12#include <bcm63xx_board.h>
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h>
16#include <bcm63xx_gpio.h>
17
18void __init prom_init(void)
19{
20 u32 reg, mask;
21
22 bcm63xx_cpu_init();
23
24 /* stop any running watchdog */
25 bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
27
28 /* disable all hardware blocks clock for now */
29 if (BCMCPU_IS_6338())
30 mask = CKCTL_6338_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6345())
32 mask = CKCTL_6345_ALL_SAFE_EN;
33 else if (BCMCPU_IS_6348())
34 mask = CKCTL_6348_ALL_SAFE_EN;
35 else
36 /* BCMCPU_IS_6358() */
37 mask = CKCTL_6358_ALL_SAFE_EN;
38
39 reg = bcm_perf_readl(PERF_CKCTL_REG);
40 reg &= ~mask;
41 bcm_perf_writel(reg, PERF_CKCTL_REG);
42
43 /* assign command line from kernel config */
44 strcpy(arcs_cmdline, CONFIG_CMDLINE);
45
46 /* register gpiochip */
47 bcm63xx_gpio_init();
48
49 /* do low level board init */
50 board_prom_init();
51}
52
53void __init prom_free_prom_memory(void)
54{
55}
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
new file mode 100644
index 000000000000..b18a0ca926fa
--- /dev/null
+++ b/arch/mips/bcm63xx/setup.c
@@ -0,0 +1,125 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/bootmem.h>
13#include <linux/ioport.h>
14#include <linux/pm.h>
15#include <asm/bootinfo.h>
16#include <asm/time.h>
17#include <asm/reboot.h>
18#include <asm/cacheflush.h>
19#include <bcm63xx_board.h>
20#include <bcm63xx_cpu.h>
21#include <bcm63xx_regs.h>
22#include <bcm63xx_io.h>
23
24void bcm63xx_machine_halt(void)
25{
26 printk(KERN_INFO "System halted\n");
27 while (1)
28 ;
29}
30
31static void bcm6348_a1_reboot(void)
32{
33 u32 reg;
34
35 /* soft reset all blocks */
36 printk(KERN_INFO "soft-reseting all blocks ...\n");
37 reg = bcm_perf_readl(PERF_SOFTRESET_REG);
38 reg &= ~SOFTRESET_6348_ALL;
39 bcm_perf_writel(reg, PERF_SOFTRESET_REG);
40 mdelay(10);
41
42 reg = bcm_perf_readl(PERF_SOFTRESET_REG);
43 reg |= SOFTRESET_6348_ALL;
44 bcm_perf_writel(reg, PERF_SOFTRESET_REG);
45 mdelay(10);
46
47 /* Jump to the power on address. */
48 printk(KERN_INFO "jumping to reset vector.\n");
49 /* set high vectors (base at 0xbfc00000 */
50 set_c0_status(ST0_BEV | ST0_ERL);
51 /* run uncached in kseg0 */
52 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
53 __flush_cache_all();
54 /* remove all wired TLB entries */
55 write_c0_wired(0);
56 __asm__ __volatile__(
57 "jr\t%0"
58 :
59 : "r" (0xbfc00000));
60 while (1)
61 ;
62}
63
64void bcm63xx_machine_reboot(void)
65{
66 u32 reg;
67
68 /* mask and clear all external irq */
69 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
70 reg &= ~EXTIRQ_CFG_MASK_ALL;
71 reg |= EXTIRQ_CFG_CLEAR_ALL;
72 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
73
74 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
75 bcm6348_a1_reboot();
76
77 printk(KERN_INFO "triggering watchdog soft-reset...\n");
78 bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
79 while (1)
80 ;
81}
82
83static void __bcm63xx_machine_reboot(char *p)
84{
85 bcm63xx_machine_reboot();
86}
87
88/*
89 * return system type in /proc/cpuinfo
90 */
91const char *get_system_type(void)
92{
93 static char buf[128];
94 snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
95 board_get_name(),
96 bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
97 return buf;
98}
99
100void __init plat_time_init(void)
101{
102 mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
103}
104
105void __init plat_mem_setup(void)
106{
107 add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
108
109 _machine_halt = bcm63xx_machine_halt;
110 _machine_restart = __bcm63xx_machine_reboot;
111 pm_power_off = bcm63xx_machine_halt;
112
113 set_io_port_base(0);
114 ioport_resource.start = 0;
115 ioport_resource.end = ~0;
116
117 board_setup();
118}
119
120int __init bcm63xx_register_devices(void)
121{
122 return board_register_devices();
123}
124
125arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/bcm63xx/timer.c b/arch/mips/bcm63xx/timer.c
new file mode 100644
index 000000000000..ba522bdcde4b
--- /dev/null
+++ b/arch/mips/bcm63xx/timer.c
@@ -0,0 +1,205 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/kernel.h>
10#include <linux/err.h>
11#include <linux/module.h>
12#include <linux/spinlock.h>
13#include <linux/interrupt.h>
14#include <linux/clk.h>
15#include <bcm63xx_cpu.h>
16#include <bcm63xx_io.h>
17#include <bcm63xx_timer.h>
18#include <bcm63xx_regs.h>
19
20static DEFINE_SPINLOCK(timer_reg_lock);
21static DEFINE_SPINLOCK(timer_data_lock);
22static struct clk *periph_clk;
23
24static struct timer_data {
25 void (*cb)(void *);
26 void *data;
27} timer_data[BCM63XX_TIMER_COUNT];
28
29static irqreturn_t timer_interrupt(int irq, void *dev_id)
30{
31 u32 stat;
32 int i;
33
34 spin_lock(&timer_reg_lock);
35 stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
36 bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
37 spin_unlock(&timer_reg_lock);
38
39 for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
40 if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
41 continue;
42
43 spin_lock(&timer_data_lock);
44 if (!timer_data[i].cb) {
45 spin_unlock(&timer_data_lock);
46 continue;
47 }
48
49 timer_data[i].cb(timer_data[i].data);
50 spin_unlock(&timer_data_lock);
51 }
52
53 return IRQ_HANDLED;
54}
55
56int bcm63xx_timer_enable(int id)
57{
58 u32 reg;
59 unsigned long flags;
60
61 if (id >= BCM63XX_TIMER_COUNT)
62 return -EINVAL;
63
64 spin_lock_irqsave(&timer_reg_lock, flags);
65
66 reg = bcm_timer_readl(TIMER_CTLx_REG(id));
67 reg |= TIMER_CTL_ENABLE_MASK;
68 bcm_timer_writel(reg, TIMER_CTLx_REG(id));
69
70 reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
71 reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
72 bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
73
74 spin_unlock_irqrestore(&timer_reg_lock, flags);
75 return 0;
76}
77
78EXPORT_SYMBOL(bcm63xx_timer_enable);
79
80int bcm63xx_timer_disable(int id)
81{
82 u32 reg;
83 unsigned long flags;
84
85 if (id >= BCM63XX_TIMER_COUNT)
86 return -EINVAL;
87
88 spin_lock_irqsave(&timer_reg_lock, flags);
89
90 reg = bcm_timer_readl(TIMER_CTLx_REG(id));
91 reg &= ~TIMER_CTL_ENABLE_MASK;
92 bcm_timer_writel(reg, TIMER_CTLx_REG(id));
93
94 reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
95 reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
96 bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
97
98 spin_unlock_irqrestore(&timer_reg_lock, flags);
99 return 0;
100}
101
102EXPORT_SYMBOL(bcm63xx_timer_disable);
103
104int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
105{
106 unsigned long flags;
107 int ret;
108
109 if (id >= BCM63XX_TIMER_COUNT || !callback)
110 return -EINVAL;
111
112 ret = 0;
113 spin_lock_irqsave(&timer_data_lock, flags);
114 if (timer_data[id].cb) {
115 ret = -EBUSY;
116 goto out;
117 }
118
119 timer_data[id].cb = callback;
120 timer_data[id].data = data;
121
122out:
123 spin_unlock_irqrestore(&timer_data_lock, flags);
124 return ret;
125}
126
127EXPORT_SYMBOL(bcm63xx_timer_register);
128
129void bcm63xx_timer_unregister(int id)
130{
131 unsigned long flags;
132
133 if (id >= BCM63XX_TIMER_COUNT)
134 return;
135
136 spin_lock_irqsave(&timer_data_lock, flags);
137 timer_data[id].cb = NULL;
138 spin_unlock_irqrestore(&timer_data_lock, flags);
139}
140
141EXPORT_SYMBOL(bcm63xx_timer_unregister);
142
143unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
144{
145 return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
146}
147
148EXPORT_SYMBOL(bcm63xx_timer_countdown);
149
150int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
151{
152 u32 reg, countdown;
153 unsigned long flags;
154
155 if (id >= BCM63XX_TIMER_COUNT)
156 return -EINVAL;
157
158 countdown = bcm63xx_timer_countdown(countdown_us);
159 if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
160 return -EINVAL;
161
162 spin_lock_irqsave(&timer_reg_lock, flags);
163 reg = bcm_timer_readl(TIMER_CTLx_REG(id));
164
165 if (monotonic)
166 reg &= ~TIMER_CTL_MONOTONIC_MASK;
167 else
168 reg |= TIMER_CTL_MONOTONIC_MASK;
169
170 reg &= ~TIMER_CTL_COUNTDOWN_MASK;
171 reg |= countdown;
172 bcm_timer_writel(reg, TIMER_CTLx_REG(id));
173
174 spin_unlock_irqrestore(&timer_reg_lock, flags);
175 return 0;
176}
177
178EXPORT_SYMBOL(bcm63xx_timer_set);
179
180int bcm63xx_timer_init(void)
181{
182 int ret, irq;
183 u32 reg;
184
185 reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
186 reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
187 reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
188 reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
189 bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
190
191 periph_clk = clk_get(NULL, "periph");
192 if (IS_ERR(periph_clk))
193 return -ENODEV;
194
195 irq = bcm63xx_get_irq_number(IRQ_TIMER);
196 ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
197 if (ret) {
198 printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
199 return ret;
200 }
201
202 return 0;
203}
204
205arch_initcall(bcm63xx_timer_init);
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index c5a7f308c405..e19d906236af 100644
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -59,8 +59,8 @@ struct sect {
59}; 59};
60 60
61int *symTypeTable; 61int *symTypeTable;
62int must_convert_endian = 0; 62int must_convert_endian;
63int format_bigendian = 0; 63int format_bigendian;
64 64
65static void copy(int out, int in, off_t offset, off_t size) 65static void copy(int out, int in, off_t offset, off_t size)
66{ 66{
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index d6903c3f3d51..139436280520 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -6,10 +6,10 @@
6# License. See the file "COPYING" in the main directory of this archive 6# License. See the file "COPYING" in the main directory of this archive
7# for more details. 7# for more details.
8# 8#
9# Copyright (C) 2005-2008 Cavium Networks 9# Copyright (C) 2005-2009 Cavium Networks
10# 10#
11 11
12obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o 12obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o 13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
new file mode 100644
index 000000000000..be711dd2d918
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -0,0 +1,164 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2009 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10#include <linux/init.h>
11#include <linux/irq.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-rnm-defs.h>
17
18static struct octeon_cf_data octeon_cf_data;
19
20static int __init octeon_cf_device_init(void)
21{
22 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
23 unsigned long base_ptr, region_base, region_size;
24 struct platform_device *pd;
25 struct resource cf_resources[3];
26 unsigned int num_resources;
27 int i;
28 int ret = 0;
29
30 /* Setup octeon-cf platform device if present. */
31 base_ptr = 0;
32 if (octeon_bootinfo->major_version == 1
33 && octeon_bootinfo->minor_version >= 1) {
34 if (octeon_bootinfo->compact_flash_common_base_addr)
35 base_ptr =
36 octeon_bootinfo->compact_flash_common_base_addr;
37 } else {
38 base_ptr = 0x1d000800;
39 }
40
41 if (!base_ptr)
42 return ret;
43
44 /* Find CS0 region. */
45 for (i = 0; i < 8; i++) {
46 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
47 region_base = mio_boot_reg_cfg.s.base << 16;
48 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
49 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
50 && base_ptr < region_base + region_size)
51 break;
52 }
53 if (i >= 7) {
54 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
55 goto out;
56 }
57 octeon_cf_data.base_region = i;
58 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
59 octeon_cf_data.base_region_bias = base_ptr - region_base;
60 memset(cf_resources, 0, sizeof(cf_resources));
61 num_resources = 0;
62 cf_resources[num_resources].flags = IORESOURCE_MEM;
63 cf_resources[num_resources].start = region_base;
64 cf_resources[num_resources].end = region_base + region_size - 1;
65 num_resources++;
66
67
68 if (!(base_ptr & 0xfffful)) {
69 /*
70 * Boot loader signals availability of DMA (true_ide
71 * mode) by setting low order bits of base_ptr to
72 * zero.
73 */
74
75 /* Asume that CS1 immediately follows. */
76 mio_boot_reg_cfg.u64 =
77 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
78 region_base = mio_boot_reg_cfg.s.base << 16;
79 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
80 if (!mio_boot_reg_cfg.s.en)
81 goto out;
82
83 cf_resources[num_resources].flags = IORESOURCE_MEM;
84 cf_resources[num_resources].start = region_base;
85 cf_resources[num_resources].end = region_base + region_size - 1;
86 num_resources++;
87
88 octeon_cf_data.dma_engine = 0;
89 cf_resources[num_resources].flags = IORESOURCE_IRQ;
90 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
91 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
92 num_resources++;
93 } else {
94 octeon_cf_data.dma_engine = -1;
95 }
96
97 pd = platform_device_alloc("pata_octeon_cf", -1);
98 if (!pd) {
99 ret = -ENOMEM;
100 goto out;
101 }
102 pd->dev.platform_data = &octeon_cf_data;
103
104 ret = platform_device_add_resources(pd, cf_resources, num_resources);
105 if (ret)
106 goto fail;
107
108 ret = platform_device_add(pd);
109 if (ret)
110 goto fail;
111
112 return ret;
113fail:
114 platform_device_put(pd);
115out:
116 return ret;
117}
118device_initcall(octeon_cf_device_init);
119
120/* Octeon Random Number Generator. */
121static int __init octeon_rng_device_init(void)
122{
123 struct platform_device *pd;
124 int ret = 0;
125
126 struct resource rng_resources[] = {
127 {
128 .flags = IORESOURCE_MEM,
129 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
130 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
131 }, {
132 .flags = IORESOURCE_MEM,
133 .start = cvmx_build_io_address(8, 0),
134 .end = cvmx_build_io_address(8, 0) + 0x7
135 }
136 };
137
138 pd = platform_device_alloc("octeon_rng", -1);
139 if (!pd) {
140 ret = -ENOMEM;
141 goto out;
142 }
143
144 ret = platform_device_add_resources(pd, rng_resources,
145 ARRAY_SIZE(rng_resources));
146 if (ret)
147 goto fail;
148
149 ret = platform_device_add(pd);
150 if (ret)
151 goto fail;
152
153 return ret;
154fail:
155 platform_device_put(pd);
156
157out:
158 return ret;
159}
160device_initcall(octeon_rng_device_init);
161
162MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
163MODULE_LICENSE("GPL");
164MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index da559249cc2f..b321d3b16877 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -11,7 +11,6 @@
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/serial.h> 14#include <linux/serial.h>
16#include <linux/smp.h> 15#include <linux/smp.h>
17#include <linux/types.h> 16#include <linux/types.h>
@@ -824,105 +823,3 @@ void prom_free_prom_memory(void)
824 CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */ 823 CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
825 octeon_hal_setup_reserved32(); 824 octeon_hal_setup_reserved32();
826} 825}
827
828static struct octeon_cf_data octeon_cf_data;
829
830static int __init octeon_cf_device_init(void)
831{
832 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
833 unsigned long base_ptr, region_base, region_size;
834 struct platform_device *pd;
835 struct resource cf_resources[3];
836 unsigned int num_resources;
837 int i;
838 int ret = 0;
839
840 /* Setup octeon-cf platform device if present. */
841 base_ptr = 0;
842 if (octeon_bootinfo->major_version == 1
843 && octeon_bootinfo->minor_version >= 1) {
844 if (octeon_bootinfo->compact_flash_common_base_addr)
845 base_ptr =
846 octeon_bootinfo->compact_flash_common_base_addr;
847 } else {
848 base_ptr = 0x1d000800;
849 }
850
851 if (!base_ptr)
852 return ret;
853
854 /* Find CS0 region. */
855 for (i = 0; i < 8; i++) {
856 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
857 region_base = mio_boot_reg_cfg.s.base << 16;
858 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
859 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
860 && base_ptr < region_base + region_size)
861 break;
862 }
863 if (i >= 7) {
864 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
865 goto out;
866 }
867 octeon_cf_data.base_region = i;
868 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
869 octeon_cf_data.base_region_bias = base_ptr - region_base;
870 memset(cf_resources, 0, sizeof(cf_resources));
871 num_resources = 0;
872 cf_resources[num_resources].flags = IORESOURCE_MEM;
873 cf_resources[num_resources].start = region_base;
874 cf_resources[num_resources].end = region_base + region_size - 1;
875 num_resources++;
876
877
878 if (!(base_ptr & 0xfffful)) {
879 /*
880 * Boot loader signals availability of DMA (true_ide
881 * mode) by setting low order bits of base_ptr to
882 * zero.
883 */
884
885 /* Asume that CS1 immediately follows. */
886 mio_boot_reg_cfg.u64 =
887 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
888 region_base = mio_boot_reg_cfg.s.base << 16;
889 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
890 if (!mio_boot_reg_cfg.s.en)
891 goto out;
892
893 cf_resources[num_resources].flags = IORESOURCE_MEM;
894 cf_resources[num_resources].start = region_base;
895 cf_resources[num_resources].end = region_base + region_size - 1;
896 num_resources++;
897
898 octeon_cf_data.dma_engine = 0;
899 cf_resources[num_resources].flags = IORESOURCE_IRQ;
900 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
901 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
902 num_resources++;
903 } else {
904 octeon_cf_data.dma_engine = -1;
905 }
906
907 pd = platform_device_alloc("pata_octeon_cf", -1);
908 if (!pd) {
909 ret = -ENOMEM;
910 goto out;
911 }
912 pd->dev.platform_data = &octeon_cf_data;
913
914 ret = platform_device_add_resources(pd, cf_resources, num_resources);
915 if (ret)
916 goto fail;
917
918 ret = platform_device_add(pd);
919 if (ret)
920 goto fail;
921
922 return ret;
923fail:
924 platform_device_put(pd);
925out:
926 return ret;
927}
928device_initcall(octeon_cf_device_init);
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index dad5b6769d74..35648302f7cc 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -125,7 +125,6 @@ CONFIG_CPU_HAS_PREFETCH=y
125CONFIG_MIPS_MT_DISABLED=y 125CONFIG_MIPS_MT_DISABLED=y
126# CONFIG_MIPS_MT_SMP is not set 126# CONFIG_MIPS_MT_SMP is not set
127# CONFIG_MIPS_MT_SMTC is not set 127# CONFIG_MIPS_MT_SMTC is not set
128CONFIG_CPU_HAS_LLSC=y
129CONFIG_CPU_HAS_SYNC=y 128CONFIG_CPU_HAS_SYNC=y
130CONFIG_GENERIC_HARDIRQS=y 129CONFIG_GENERIC_HARDIRQS=y
131CONFIG_GENERIC_IRQ_PROBE=y 130CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index d8694332b344..94b7d57f906d 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -111,7 +111,6 @@ CONFIG_CPU_HAS_PREFETCH=y
111CONFIG_MIPS_MT_DISABLED=y 111CONFIG_MIPS_MT_DISABLED=y
112# CONFIG_MIPS_MT_SMP is not set 112# CONFIG_MIPS_MT_SMP is not set
113# CONFIG_MIPS_MT_SMTC is not set 113# CONFIG_MIPS_MT_SMTC is not set
114CONFIG_CPU_HAS_LLSC=y
115CONFIG_CPU_HAS_SYNC=y 114CONFIG_CPU_HAS_SYNC=y
116CONFIG_GENERIC_HARDIRQS=y 115CONFIG_GENERIC_HARDIRQS=y
117CONFIG_GENERIC_IRQ_PROBE=y 116CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
new file mode 100644
index 000000000000..ea00c18d1f7b
--- /dev/null
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -0,0 +1,972 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc6
4# Sun May 31 20:17:18 2009
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14CONFIG_BCM63XX=y
15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set
18# CONFIG_LASAT is not set
19# CONFIG_LEMOTE_FULONG is not set
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_NEC_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
26# CONFIG_PNX8550_JBS is not set
27# CONFIG_PNX8550_STB810 is not set
28# CONFIG_PMC_MSP is not set
29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP28 is not set
33# CONFIG_SGI_IP32 is not set
34# CONFIG_SIBYTE_CRHINE is not set
35# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_CRHONE is not set
37# CONFIG_SIBYTE_RHONE is not set
38# CONFIG_SIBYTE_SWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_SENTOSA is not set
41# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_MACH_TX39XX is not set
44# CONFIG_MACH_TX49XX is not set
45# CONFIG_MIKROTIK_RB532 is not set
46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49
50#
51# CPU support
52#
53CONFIG_BCM63XX_CPU_6348=y
54CONFIG_BCM63XX_CPU_6358=y
55CONFIG_BOARD_BCM963XX=y
56CONFIG_RWSEM_GENERIC_SPINLOCK=y
57# CONFIG_ARCH_HAS_ILOG2_U32 is not set
58# CONFIG_ARCH_HAS_ILOG2_U64 is not set
59CONFIG_ARCH_SUPPORTS_OPROFILE=y
60CONFIG_GENERIC_FIND_NEXT_BIT=y
61CONFIG_GENERIC_HWEIGHT=y
62CONFIG_GENERIC_CALIBRATE_DELAY=y
63CONFIG_GENERIC_CLOCKEVENTS=y
64CONFIG_GENERIC_TIME=y
65CONFIG_GENERIC_CMOS_UPDATE=y
66CONFIG_SCHED_OMIT_FRAME_POINTER=y
67CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
68CONFIG_CEVT_R4K_LIB=y
69CONFIG_CEVT_R4K=y
70CONFIG_CSRC_R4K_LIB=y
71CONFIG_CSRC_R4K=y
72CONFIG_DMA_NONCOHERENT=y
73CONFIG_DMA_NEED_PCI_MAP_STATE=y
74CONFIG_EARLY_PRINTK=y
75CONFIG_SYS_HAS_EARLY_PRINTK=y
76# CONFIG_HOTPLUG_CPU is not set
77# CONFIG_NO_IOPORT is not set
78CONFIG_GENERIC_GPIO=y
79CONFIG_CPU_BIG_ENDIAN=y
80# CONFIG_CPU_LITTLE_ENDIAN is not set
81CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
82CONFIG_IRQ_CPU=y
83CONFIG_SWAP_IO_SPACE=y
84CONFIG_MIPS_L1_CACHE_SHIFT=5
85
86#
87# CPU selection
88#
89# CONFIG_CPU_LOONGSON2 is not set
90CONFIG_CPU_MIPS32_R1=y
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100# CONFIG_CPU_R5000 is not set
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R5500 is not set
103# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set
107# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set
110# CONFIG_CPU_CAVIUM_OCTEON is not set
111CONFIG_SYS_HAS_CPU_MIPS32_R1=y
112CONFIG_CPU_MIPS32=y
113CONFIG_CPU_MIPSR1=y
114CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
115CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
116CONFIG_HARDWARE_WATCHPOINTS=y
117
118#
119# Kernel type
120#
121CONFIG_32BIT=y
122# CONFIG_64BIT is not set
123CONFIG_PAGE_SIZE_4KB=y
124# CONFIG_PAGE_SIZE_8KB is not set
125# CONFIG_PAGE_SIZE_16KB is not set
126# CONFIG_PAGE_SIZE_32KB is not set
127# CONFIG_PAGE_SIZE_64KB is not set
128CONFIG_CPU_HAS_PREFETCH=y
129CONFIG_MIPS_MT_DISABLED=y
130# CONFIG_MIPS_MT_SMP is not set
131# CONFIG_MIPS_MT_SMTC is not set
132CONFIG_CPU_HAS_LLSC=y
133CONFIG_CPU_HAS_SYNC=y
134CONFIG_GENERIC_HARDIRQS=y
135CONFIG_GENERIC_IRQ_PROBE=y
136CONFIG_CPU_SUPPORTS_HIGHMEM=y
137CONFIG_ARCH_FLATMEM_ENABLE=y
138CONFIG_ARCH_POPULATES_NODE_MAP=y
139CONFIG_SELECT_MEMORY_MODEL=y
140CONFIG_FLATMEM_MANUAL=y
141# CONFIG_DISCONTIGMEM_MANUAL is not set
142# CONFIG_SPARSEMEM_MANUAL is not set
143CONFIG_FLATMEM=y
144CONFIG_FLAT_NODE_MEM_MAP=y
145CONFIG_PAGEFLAGS_EXTENDED=y
146CONFIG_SPLIT_PTLOCK_CPUS=4
147# CONFIG_PHYS_ADDR_T_64BIT is not set
148CONFIG_ZONE_DMA_FLAG=0
149CONFIG_VIRT_TO_BUS=y
150CONFIG_UNEVICTABLE_LRU=y
151CONFIG_HAVE_MLOCK=y
152CONFIG_HAVE_MLOCKED_PAGE_BIT=y
153CONFIG_TICK_ONESHOT=y
154CONFIG_NO_HZ=y
155# CONFIG_HIGH_RES_TIMERS is not set
156CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
157# CONFIG_HZ_48 is not set
158# CONFIG_HZ_100 is not set
159# CONFIG_HZ_128 is not set
160CONFIG_HZ_250=y
161# CONFIG_HZ_256 is not set
162# CONFIG_HZ_1000 is not set
163# CONFIG_HZ_1024 is not set
164CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
165CONFIG_HZ=250
166CONFIG_PREEMPT_NONE=y
167# CONFIG_PREEMPT_VOLUNTARY is not set
168# CONFIG_PREEMPT is not set
169# CONFIG_KEXEC is not set
170# CONFIG_SECCOMP is not set
171CONFIG_LOCKDEP_SUPPORT=y
172CONFIG_STACKTRACE_SUPPORT=y
173CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
174
175#
176# General setup
177#
178CONFIG_EXPERIMENTAL=y
179CONFIG_BROKEN_ON_SMP=y
180CONFIG_INIT_ENV_ARG_LIMIT=32
181CONFIG_LOCALVERSION=""
182# CONFIG_LOCALVERSION_AUTO is not set
183# CONFIG_SWAP is not set
184# CONFIG_SYSVIPC is not set
185# CONFIG_POSIX_MQUEUE is not set
186# CONFIG_BSD_PROCESS_ACCT is not set
187# CONFIG_TASKSTATS is not set
188# CONFIG_AUDIT is not set
189
190#
191# RCU Subsystem
192#
193CONFIG_CLASSIC_RCU=y
194# CONFIG_TREE_RCU is not set
195# CONFIG_PREEMPT_RCU is not set
196# CONFIG_TREE_RCU_TRACE is not set
197# CONFIG_PREEMPT_RCU_TRACE is not set
198# CONFIG_IKCONFIG is not set
199CONFIG_LOG_BUF_SHIFT=17
200# CONFIG_GROUP_SCHED is not set
201# CONFIG_CGROUPS is not set
202CONFIG_SYSFS_DEPRECATED=y
203CONFIG_SYSFS_DEPRECATED_V2=y
204# CONFIG_RELAY is not set
205# CONFIG_NAMESPACES is not set
206# CONFIG_BLK_DEV_INITRD is not set
207CONFIG_CC_OPTIMIZE_FOR_SIZE=y
208CONFIG_SYSCTL=y
209CONFIG_EMBEDDED=y
210CONFIG_SYSCTL_SYSCALL=y
211CONFIG_KALLSYMS=y
212# CONFIG_KALLSYMS_EXTRA_PASS is not set
213# CONFIG_STRIP_ASM_SYMS is not set
214CONFIG_HOTPLUG=y
215CONFIG_PRINTK=y
216CONFIG_BUG=y
217CONFIG_ELF_CORE=y
218# CONFIG_PCSPKR_PLATFORM is not set
219CONFIG_BASE_FULL=y
220# CONFIG_FUTEX is not set
221# CONFIG_EPOLL is not set
222# CONFIG_SIGNALFD is not set
223# CONFIG_TIMERFD is not set
224# CONFIG_EVENTFD is not set
225# CONFIG_SHMEM is not set
226# CONFIG_AIO is not set
227# CONFIG_VM_EVENT_COUNTERS is not set
228CONFIG_PCI_QUIRKS=y
229# CONFIG_SLUB_DEBUG is not set
230CONFIG_COMPAT_BRK=y
231# CONFIG_SLAB is not set
232CONFIG_SLUB=y
233# CONFIG_SLOB is not set
234# CONFIG_PROFILING is not set
235# CONFIG_MARKERS is not set
236CONFIG_HAVE_OPROFILE=y
237# CONFIG_SLOW_WORK is not set
238# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
239CONFIG_BASE_SMALL=0
240# CONFIG_MODULES is not set
241CONFIG_BLOCK=y
242# CONFIG_LBD is not set
243# CONFIG_BLK_DEV_BSG is not set
244# CONFIG_BLK_DEV_INTEGRITY is not set
245
246#
247# IO Schedulers
248#
249CONFIG_IOSCHED_NOOP=y
250# CONFIG_IOSCHED_AS is not set
251# CONFIG_IOSCHED_DEADLINE is not set
252# CONFIG_IOSCHED_CFQ is not set
253# CONFIG_DEFAULT_AS is not set
254# CONFIG_DEFAULT_DEADLINE is not set
255# CONFIG_DEFAULT_CFQ is not set
256CONFIG_DEFAULT_NOOP=y
257CONFIG_DEFAULT_IOSCHED="noop"
258# CONFIG_FREEZER is not set
259
260#
261# Bus options (PCI, PCMCIA, EISA, ISA, TC)
262#
263CONFIG_HW_HAS_PCI=y
264CONFIG_PCI=y
265CONFIG_PCI_DOMAINS=y
266# CONFIG_ARCH_SUPPORTS_MSI is not set
267# CONFIG_PCI_LEGACY is not set
268# CONFIG_PCI_STUB is not set
269# CONFIG_PCI_IOV is not set
270CONFIG_MMU=y
271CONFIG_PCCARD=y
272# CONFIG_PCMCIA_DEBUG is not set
273CONFIG_PCMCIA=y
274CONFIG_PCMCIA_LOAD_CIS=y
275CONFIG_PCMCIA_IOCTL=y
276CONFIG_CARDBUS=y
277
278#
279# PC-card bridges
280#
281# CONFIG_YENTA is not set
282# CONFIG_PD6729 is not set
283# CONFIG_I82092 is not set
284CONFIG_PCMCIA_BCM63XX=y
285# CONFIG_HOTPLUG_PCI is not set
286
287#
288# Executable file formats
289#
290CONFIG_BINFMT_ELF=y
291# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
292# CONFIG_HAVE_AOUT is not set
293# CONFIG_BINFMT_MISC is not set
294CONFIG_TRAD_SIGNALS=y
295
296#
297# Power management options
298#
299CONFIG_ARCH_SUSPEND_POSSIBLE=y
300# CONFIG_PM is not set
301CONFIG_NET=y
302
303#
304# Networking options
305#
306# CONFIG_PACKET is not set
307CONFIG_UNIX=y
308# CONFIG_NET_KEY is not set
309CONFIG_INET=y
310# CONFIG_IP_MULTICAST is not set
311# CONFIG_IP_ADVANCED_ROUTER is not set
312CONFIG_IP_FIB_HASH=y
313# CONFIG_IP_PNP is not set
314# CONFIG_NET_IPIP is not set
315# CONFIG_NET_IPGRE is not set
316# CONFIG_ARPD is not set
317# CONFIG_SYN_COOKIES is not set
318# CONFIG_INET_AH is not set
319# CONFIG_INET_ESP is not set
320# CONFIG_INET_IPCOMP is not set
321# CONFIG_INET_XFRM_TUNNEL is not set
322# CONFIG_INET_TUNNEL is not set
323# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
324# CONFIG_INET_XFRM_MODE_TUNNEL is not set
325# CONFIG_INET_XFRM_MODE_BEET is not set
326# CONFIG_INET_LRO is not set
327# CONFIG_INET_DIAG is not set
328# CONFIG_TCP_CONG_ADVANCED is not set
329CONFIG_TCP_CONG_CUBIC=y
330CONFIG_DEFAULT_TCP_CONG="cubic"
331# CONFIG_TCP_MD5SIG is not set
332# CONFIG_IPV6 is not set
333# CONFIG_NETWORK_SECMARK is not set
334# CONFIG_NETFILTER is not set
335# CONFIG_IP_DCCP is not set
336# CONFIG_IP_SCTP is not set
337# CONFIG_TIPC is not set
338# CONFIG_ATM is not set
339# CONFIG_BRIDGE is not set
340# CONFIG_NET_DSA is not set
341# CONFIG_VLAN_8021Q is not set
342# CONFIG_DECNET is not set
343# CONFIG_LLC2 is not set
344# CONFIG_IPX is not set
345# CONFIG_ATALK is not set
346# CONFIG_X25 is not set
347# CONFIG_LAPB is not set
348# CONFIG_ECONET is not set
349# CONFIG_WAN_ROUTER is not set
350# CONFIG_PHONET is not set
351# CONFIG_NET_SCHED is not set
352# CONFIG_DCB is not set
353
354#
355# Network testing
356#
357# CONFIG_NET_PKTGEN is not set
358# CONFIG_HAMRADIO is not set
359# CONFIG_CAN is not set
360# CONFIG_IRDA is not set
361# CONFIG_BT is not set
362# CONFIG_AF_RXRPC is not set
363# CONFIG_WIRELESS is not set
364# CONFIG_WIMAX is not set
365# CONFIG_RFKILL is not set
366# CONFIG_NET_9P is not set
367
368#
369# Device Drivers
370#
371
372#
373# Generic Driver Options
374#
375CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
376# CONFIG_STANDALONE is not set
377# CONFIG_PREVENT_FIRMWARE_BUILD is not set
378CONFIG_FW_LOADER=y
379CONFIG_FIRMWARE_IN_KERNEL=y
380CONFIG_EXTRA_FIRMWARE=""
381# CONFIG_SYS_HYPERVISOR is not set
382# CONFIG_CONNECTOR is not set
383CONFIG_MTD=y
384# CONFIG_MTD_DEBUG is not set
385# CONFIG_MTD_CONCAT is not set
386CONFIG_MTD_PARTITIONS=y
387# CONFIG_MTD_REDBOOT_PARTS is not set
388# CONFIG_MTD_CMDLINE_PARTS is not set
389# CONFIG_MTD_AR7_PARTS is not set
390
391#
392# User Modules And Translation Layers
393#
394# CONFIG_MTD_CHAR is not set
395# CONFIG_MTD_BLKDEVS is not set
396# CONFIG_MTD_BLOCK is not set
397# CONFIG_MTD_BLOCK_RO is not set
398# CONFIG_FTL is not set
399# CONFIG_NFTL is not set
400# CONFIG_INFTL is not set
401# CONFIG_RFD_FTL is not set
402# CONFIG_SSFDC is not set
403# CONFIG_MTD_OOPS is not set
404
405#
406# RAM/ROM/Flash chip drivers
407#
408CONFIG_MTD_CFI=y
409# CONFIG_MTD_JEDECPROBE is not set
410CONFIG_MTD_GEN_PROBE=y
411# CONFIG_MTD_CFI_ADV_OPTIONS is not set
412CONFIG_MTD_MAP_BANK_WIDTH_1=y
413CONFIG_MTD_MAP_BANK_WIDTH_2=y
414CONFIG_MTD_MAP_BANK_WIDTH_4=y
415# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
416# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
417# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
418CONFIG_MTD_CFI_I1=y
419CONFIG_MTD_CFI_I2=y
420# CONFIG_MTD_CFI_I4 is not set
421# CONFIG_MTD_CFI_I8 is not set
422CONFIG_MTD_CFI_INTELEXT=y
423CONFIG_MTD_CFI_AMDSTD=y
424# CONFIG_MTD_CFI_STAA is not set
425CONFIG_MTD_CFI_UTIL=y
426# CONFIG_MTD_RAM is not set
427# CONFIG_MTD_ROM is not set
428# CONFIG_MTD_ABSENT is not set
429
430#
431# Mapping drivers for chip access
432#
433# CONFIG_MTD_COMPLEX_MAPPINGS is not set
434CONFIG_MTD_PHYSMAP=y
435# CONFIG_MTD_PHYSMAP_COMPAT is not set
436# CONFIG_MTD_INTEL_VR_NOR is not set
437# CONFIG_MTD_PLATRAM is not set
438
439#
440# Self-contained MTD device drivers
441#
442# CONFIG_MTD_PMC551 is not set
443# CONFIG_MTD_SLRAM is not set
444# CONFIG_MTD_PHRAM is not set
445# CONFIG_MTD_MTDRAM is not set
446# CONFIG_MTD_BLOCK2MTD is not set
447
448#
449# Disk-On-Chip Device Drivers
450#
451# CONFIG_MTD_DOC2000 is not set
452# CONFIG_MTD_DOC2001 is not set
453# CONFIG_MTD_DOC2001PLUS is not set
454# CONFIG_MTD_NAND is not set
455# CONFIG_MTD_ONENAND is not set
456
457#
458# LPDDR flash memory drivers
459#
460# CONFIG_MTD_LPDDR is not set
461
462#
463# UBI - Unsorted block images
464#
465# CONFIG_MTD_UBI is not set
466# CONFIG_PARPORT is not set
467# CONFIG_BLK_DEV is not set
468# CONFIG_MISC_DEVICES is not set
469CONFIG_HAVE_IDE=y
470# CONFIG_IDE is not set
471
472#
473# SCSI device support
474#
475# CONFIG_RAID_ATTRS is not set
476# CONFIG_SCSI is not set
477# CONFIG_SCSI_DMA is not set
478# CONFIG_SCSI_NETLINK is not set
479# CONFIG_ATA is not set
480# CONFIG_MD is not set
481# CONFIG_FUSION is not set
482
483#
484# IEEE 1394 (FireWire) support
485#
486
487#
488# Enable only one of the two stacks, unless you know what you are doing
489#
490# CONFIG_FIREWIRE is not set
491# CONFIG_IEEE1394 is not set
492# CONFIG_I2O is not set
493CONFIG_NETDEVICES=y
494CONFIG_COMPAT_NET_DEV_OPS=y
495# CONFIG_DUMMY is not set
496# CONFIG_BONDING is not set
497# CONFIG_MACVLAN is not set
498# CONFIG_EQUALIZER is not set
499# CONFIG_TUN is not set
500# CONFIG_VETH is not set
501# CONFIG_ARCNET is not set
502CONFIG_PHYLIB=y
503
504#
505# MII PHY device drivers
506#
507# CONFIG_MARVELL_PHY is not set
508# CONFIG_DAVICOM_PHY is not set
509# CONFIG_QSEMI_PHY is not set
510# CONFIG_LXT_PHY is not set
511# CONFIG_CICADA_PHY is not set
512# CONFIG_VITESSE_PHY is not set
513# CONFIG_SMSC_PHY is not set
514# CONFIG_BROADCOM_PHY is not set
515CONFIG_BCM63XX_PHY=y
516# CONFIG_ICPLUS_PHY is not set
517# CONFIG_REALTEK_PHY is not set
518# CONFIG_NATIONAL_PHY is not set
519# CONFIG_STE10XP is not set
520# CONFIG_LSI_ET1011C_PHY is not set
521# CONFIG_FIXED_PHY is not set
522# CONFIG_MDIO_BITBANG is not set
523CONFIG_NET_ETHERNET=y
524CONFIG_MII=y
525# CONFIG_AX88796 is not set
526# CONFIG_HAPPYMEAL is not set
527# CONFIG_SUNGEM is not set
528# CONFIG_CASSINI is not set
529# CONFIG_NET_VENDOR_3COM is not set
530# CONFIG_SMC91X is not set
531# CONFIG_DM9000 is not set
532# CONFIG_ETHOC is not set
533# CONFIG_DNET is not set
534# CONFIG_NET_TULIP is not set
535# CONFIG_HP100 is not set
536# CONFIG_IBM_NEW_EMAC_ZMII is not set
537# CONFIG_IBM_NEW_EMAC_RGMII is not set
538# CONFIG_IBM_NEW_EMAC_TAH is not set
539# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
540# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
541# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
542# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
543# CONFIG_NET_PCI is not set
544# CONFIG_B44 is not set
545# CONFIG_ATL2 is not set
546CONFIG_BCM63XX_ENET=y
547# CONFIG_NETDEV_1000 is not set
548# CONFIG_NETDEV_10000 is not set
549# CONFIG_TR is not set
550
551#
552# Wireless LAN
553#
554# CONFIG_WLAN_PRE80211 is not set
555# CONFIG_WLAN_80211 is not set
556
557#
558# Enable WiMAX (Networking options) to see the WiMAX drivers
559#
560
561#
562# USB Network Adapters
563#
564# CONFIG_USB_CATC is not set
565# CONFIG_USB_KAWETH is not set
566# CONFIG_USB_PEGASUS is not set
567# CONFIG_USB_RTL8150 is not set
568# CONFIG_USB_USBNET is not set
569# CONFIG_NET_PCMCIA is not set
570# CONFIG_WAN is not set
571# CONFIG_FDDI is not set
572# CONFIG_HIPPI is not set
573# CONFIG_PPP is not set
574# CONFIG_SLIP is not set
575# CONFIG_NETCONSOLE is not set
576# CONFIG_NETPOLL is not set
577# CONFIG_NET_POLL_CONTROLLER is not set
578# CONFIG_ISDN is not set
579# CONFIG_PHONE is not set
580
581#
582# Input device support
583#
584# CONFIG_INPUT is not set
585
586#
587# Hardware I/O ports
588#
589# CONFIG_SERIO is not set
590# CONFIG_GAMEPORT is not set
591
592#
593# Character devices
594#
595# CONFIG_VT is not set
596# CONFIG_DEVKMEM is not set
597# CONFIG_SERIAL_NONSTANDARD is not set
598# CONFIG_NOZOMI is not set
599
600#
601# Serial drivers
602#
603# CONFIG_SERIAL_8250 is not set
604
605#
606# Non-8250 serial port support
607#
608CONFIG_SERIAL_CORE=y
609CONFIG_SERIAL_CORE_CONSOLE=y
610# CONFIG_SERIAL_JSM is not set
611CONFIG_SERIAL_BCM63XX=y
612CONFIG_SERIAL_BCM63XX_CONSOLE=y
613# CONFIG_UNIX98_PTYS is not set
614CONFIG_LEGACY_PTYS=y
615CONFIG_LEGACY_PTY_COUNT=256
616# CONFIG_IPMI_HANDLER is not set
617# CONFIG_HW_RANDOM is not set
618# CONFIG_R3964 is not set
619# CONFIG_APPLICOM is not set
620
621#
622# PCMCIA character devices
623#
624# CONFIG_SYNCLINK_CS is not set
625# CONFIG_CARDMAN_4000 is not set
626# CONFIG_CARDMAN_4040 is not set
627# CONFIG_IPWIRELESS is not set
628# CONFIG_RAW_DRIVER is not set
629# CONFIG_TCG_TPM is not set
630CONFIG_DEVPORT=y
631# CONFIG_I2C is not set
632# CONFIG_SPI is not set
633CONFIG_ARCH_REQUIRE_GPIOLIB=y
634CONFIG_GPIOLIB=y
635# CONFIG_GPIO_SYSFS is not set
636
637#
638# Memory mapped GPIO expanders:
639#
640
641#
642# I2C GPIO expanders:
643#
644
645#
646# PCI GPIO expanders:
647#
648# CONFIG_GPIO_BT8XX is not set
649
650#
651# SPI GPIO expanders:
652#
653# CONFIG_W1 is not set
654# CONFIG_POWER_SUPPLY is not set
655# CONFIG_HWMON is not set
656# CONFIG_THERMAL is not set
657# CONFIG_THERMAL_HWMON is not set
658# CONFIG_WATCHDOG is not set
659CONFIG_SSB_POSSIBLE=y
660
661#
662# Sonics Silicon Backplane
663#
664CONFIG_SSB=y
665CONFIG_SSB_SPROM=y
666CONFIG_SSB_PCIHOST_POSSIBLE=y
667CONFIG_SSB_PCIHOST=y
668# CONFIG_SSB_B43_PCI_BRIDGE is not set
669CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
670# CONFIG_SSB_PCMCIAHOST is not set
671# CONFIG_SSB_SILENT is not set
672# CONFIG_SSB_DEBUG is not set
673CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
674# CONFIG_SSB_DRIVER_PCICORE is not set
675# CONFIG_SSB_DRIVER_MIPS is not set
676
677#
678# Multifunction device drivers
679#
680# CONFIG_MFD_CORE is not set
681# CONFIG_MFD_SM501 is not set
682# CONFIG_HTC_PASIC3 is not set
683# CONFIG_MFD_TMIO is not set
684# CONFIG_REGULATOR is not set
685
686#
687# Multimedia devices
688#
689
690#
691# Multimedia core support
692#
693# CONFIG_VIDEO_DEV is not set
694# CONFIG_DVB_CORE is not set
695# CONFIG_VIDEO_MEDIA is not set
696
697#
698# Multimedia drivers
699#
700# CONFIG_DAB is not set
701
702#
703# Graphics support
704#
705# CONFIG_DRM is not set
706# CONFIG_VGASTATE is not set
707# CONFIG_VIDEO_OUTPUT_CONTROL is not set
708# CONFIG_FB is not set
709# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
710
711#
712# Display device support
713#
714CONFIG_DISPLAY_SUPPORT=y
715
716#
717# Display hardware drivers
718#
719# CONFIG_SOUND is not set
720CONFIG_USB_SUPPORT=y
721CONFIG_USB_ARCH_HAS_HCD=y
722CONFIG_USB_ARCH_HAS_OHCI=y
723CONFIG_USB_ARCH_HAS_EHCI=y
724CONFIG_USB=y
725# CONFIG_USB_DEBUG is not set
726# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
727
728#
729# Miscellaneous USB options
730#
731# CONFIG_USB_DEVICEFS is not set
732# CONFIG_USB_DEVICE_CLASS is not set
733# CONFIG_USB_DYNAMIC_MINORS is not set
734# CONFIG_USB_OTG is not set
735# CONFIG_USB_OTG_WHITELIST is not set
736# CONFIG_USB_OTG_BLACKLIST_HUB is not set
737# CONFIG_USB_MON is not set
738# CONFIG_USB_WUSB is not set
739# CONFIG_USB_WUSB_CBAF is not set
740
741#
742# USB Host Controller Drivers
743#
744# CONFIG_USB_C67X00_HCD is not set
745CONFIG_USB_EHCI_HCD=y
746# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
747# CONFIG_USB_EHCI_TT_NEWSCHED is not set
748CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
749# CONFIG_USB_OXU210HP_HCD is not set
750# CONFIG_USB_ISP116X_HCD is not set
751# CONFIG_USB_ISP1760_HCD is not set
752CONFIG_USB_OHCI_HCD=y
753# CONFIG_USB_OHCI_HCD_SSB is not set
754CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
755CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
756CONFIG_USB_OHCI_LITTLE_ENDIAN=y
757# CONFIG_USB_UHCI_HCD is not set
758# CONFIG_USB_SL811_HCD is not set
759# CONFIG_USB_R8A66597_HCD is not set
760# CONFIG_USB_WHCI_HCD is not set
761# CONFIG_USB_HWA_HCD is not set
762
763#
764# USB Device Class drivers
765#
766# CONFIG_USB_ACM is not set
767# CONFIG_USB_PRINTER is not set
768# CONFIG_USB_WDM is not set
769# CONFIG_USB_TMC is not set
770
771#
772# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
773#
774
775#
776# also be needed; see USB_STORAGE Help for more info
777#
778# CONFIG_USB_LIBUSUAL is not set
779
780#
781# USB Imaging devices
782#
783# CONFIG_USB_MDC800 is not set
784
785#
786# USB port drivers
787#
788# CONFIG_USB_SERIAL is not set
789
790#
791# USB Miscellaneous drivers
792#
793# CONFIG_USB_EMI62 is not set
794# CONFIG_USB_EMI26 is not set
795# CONFIG_USB_ADUTUX is not set
796# CONFIG_USB_SEVSEG is not set
797# CONFIG_USB_RIO500 is not set
798# CONFIG_USB_LEGOTOWER is not set
799# CONFIG_USB_LCD is not set
800# CONFIG_USB_BERRY_CHARGE is not set
801# CONFIG_USB_LED is not set
802# CONFIG_USB_CYPRESS_CY7C63 is not set
803# CONFIG_USB_CYTHERM is not set
804# CONFIG_USB_IDMOUSE is not set
805# CONFIG_USB_FTDI_ELAN is not set
806# CONFIG_USB_APPLEDISPLAY is not set
807# CONFIG_USB_SISUSBVGA is not set
808# CONFIG_USB_LD is not set
809# CONFIG_USB_TRANCEVIBRATOR is not set
810# CONFIG_USB_IOWARRIOR is not set
811# CONFIG_USB_ISIGHTFW is not set
812# CONFIG_USB_VST is not set
813# CONFIG_USB_GADGET is not set
814
815#
816# OTG and related infrastructure
817#
818# CONFIG_USB_GPIO_VBUS is not set
819# CONFIG_NOP_USB_XCEIV is not set
820# CONFIG_UWB is not set
821# CONFIG_MMC is not set
822# CONFIG_MEMSTICK is not set
823# CONFIG_NEW_LEDS is not set
824# CONFIG_ACCESSIBILITY is not set
825# CONFIG_INFINIBAND is not set
826CONFIG_RTC_LIB=y
827# CONFIG_RTC_CLASS is not set
828# CONFIG_DMADEVICES is not set
829# CONFIG_AUXDISPLAY is not set
830# CONFIG_UIO is not set
831# CONFIG_STAGING is not set
832
833#
834# File systems
835#
836# CONFIG_EXT2_FS is not set
837# CONFIG_EXT3_FS is not set
838# CONFIG_EXT4_FS is not set
839# CONFIG_REISERFS_FS is not set
840# CONFIG_JFS_FS is not set
841# CONFIG_FS_POSIX_ACL is not set
842# CONFIG_FILE_LOCKING is not set
843# CONFIG_XFS_FS is not set
844# CONFIG_OCFS2_FS is not set
845# CONFIG_BTRFS_FS is not set
846# CONFIG_DNOTIFY is not set
847# CONFIG_INOTIFY is not set
848# CONFIG_QUOTA is not set
849# CONFIG_AUTOFS_FS is not set
850# CONFIG_AUTOFS4_FS is not set
851# CONFIG_FUSE_FS is not set
852
853#
854# Caches
855#
856# CONFIG_FSCACHE is not set
857
858#
859# CD-ROM/DVD Filesystems
860#
861# CONFIG_ISO9660_FS is not set
862# CONFIG_UDF_FS is not set
863
864#
865# DOS/FAT/NT Filesystems
866#
867# CONFIG_MSDOS_FS is not set
868# CONFIG_VFAT_FS is not set
869# CONFIG_NTFS_FS is not set
870
871#
872# Pseudo filesystems
873#
874CONFIG_PROC_FS=y
875CONFIG_PROC_KCORE=y
876CONFIG_PROC_SYSCTL=y
877CONFIG_PROC_PAGE_MONITOR=y
878CONFIG_SYSFS=y
879CONFIG_TMPFS=y
880# CONFIG_TMPFS_POSIX_ACL is not set
881# CONFIG_HUGETLB_PAGE is not set
882# CONFIG_CONFIGFS_FS is not set
883CONFIG_MISC_FILESYSTEMS=y
884# CONFIG_ADFS_FS is not set
885# CONFIG_AFFS_FS is not set
886# CONFIG_HFS_FS is not set
887# CONFIG_HFSPLUS_FS is not set
888# CONFIG_BEFS_FS is not set
889# CONFIG_BFS_FS is not set
890# CONFIG_EFS_FS is not set
891# CONFIG_JFFS2_FS is not set
892# CONFIG_CRAMFS is not set
893# CONFIG_SQUASHFS is not set
894# CONFIG_VXFS_FS is not set
895# CONFIG_MINIX_FS is not set
896# CONFIG_OMFS_FS is not set
897# CONFIG_HPFS_FS is not set
898# CONFIG_QNX4FS_FS is not set
899# CONFIG_ROMFS_FS is not set
900# CONFIG_SYSV_FS is not set
901# CONFIG_UFS_FS is not set
902# CONFIG_NILFS2_FS is not set
903# CONFIG_NETWORK_FILESYSTEMS is not set
904
905#
906# Partition Types
907#
908# CONFIG_PARTITION_ADVANCED is not set
909CONFIG_MSDOS_PARTITION=y
910# CONFIG_NLS is not set
911# CONFIG_DLM is not set
912
913#
914# Kernel hacking
915#
916CONFIG_TRACE_IRQFLAGS_SUPPORT=y
917# CONFIG_PRINTK_TIME is not set
918CONFIG_ENABLE_WARN_DEPRECATED=y
919CONFIG_ENABLE_MUST_CHECK=y
920CONFIG_FRAME_WARN=1024
921CONFIG_MAGIC_SYSRQ=y
922# CONFIG_UNUSED_SYMBOLS is not set
923# CONFIG_DEBUG_FS is not set
924# CONFIG_HEADERS_CHECK is not set
925# CONFIG_DEBUG_KERNEL is not set
926# CONFIG_DEBUG_MEMORY_INIT is not set
927# CONFIG_RCU_CPU_STALL_DETECTOR is not set
928CONFIG_SYSCTL_SYSCALL_CHECK=y
929CONFIG_TRACING_SUPPORT=y
930
931#
932# Tracers
933#
934# CONFIG_IRQSOFF_TRACER is not set
935# CONFIG_SCHED_TRACER is not set
936# CONFIG_CONTEXT_SWITCH_TRACER is not set
937# CONFIG_EVENT_TRACER is not set
938# CONFIG_BOOT_TRACER is not set
939# CONFIG_TRACE_BRANCH_PROFILING is not set
940# CONFIG_KMEMTRACE is not set
941# CONFIG_WORKQUEUE_TRACER is not set
942# CONFIG_BLK_DEV_IO_TRACE is not set
943# CONFIG_SAMPLES is not set
944CONFIG_HAVE_ARCH_KGDB=y
945CONFIG_CMDLINE="console=ttyS0,115200"
946
947#
948# Security options
949#
950# CONFIG_KEYS is not set
951# CONFIG_SECURITY is not set
952# CONFIG_SECURITYFS is not set
953# CONFIG_SECURITY_FILE_CAPABILITIES is not set
954# CONFIG_CRYPTO is not set
955# CONFIG_BINARY_PRINTF is not set
956
957#
958# Library routines
959#
960CONFIG_BITREVERSE=y
961CONFIG_GENERIC_FIND_LAST_BIT=y
962# CONFIG_CRC_CCITT is not set
963# CONFIG_CRC16 is not set
964# CONFIG_CRC_T10DIF is not set
965# CONFIG_CRC_ITU_T is not set
966CONFIG_CRC32=y
967# CONFIG_CRC7 is not set
968# CONFIG_LIBCRC32C is not set
969CONFIG_HAS_IOMEM=y
970CONFIG_HAS_IOPORT=y
971CONFIG_HAS_DMA=y
972CONFIG_NLATTR=y
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index d6d35b2e5fe8..13d9eb4736c0 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -129,7 +129,6 @@ CONFIG_PAGE_SIZE_4KB=y
129CONFIG_MIPS_MT_DISABLED=y 129CONFIG_MIPS_MT_DISABLED=y
130# CONFIG_MIPS_MT_SMP is not set 130# CONFIG_MIPS_MT_SMP is not set
131# CONFIG_MIPS_MT_SMTC is not set 131# CONFIG_MIPS_MT_SMTC is not set
132CONFIG_CPU_HAS_LLSC=y
133CONFIG_CPU_HAS_SYNC=y 132CONFIG_CPU_HAS_SYNC=y
134CONFIG_GENERIC_HARDIRQS=y 133CONFIG_GENERIC_HARDIRQS=y
135CONFIG_GENERIC_IRQ_PROBE=y 134CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index eb44b72254af..6c8cca8589ba 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -112,7 +112,6 @@ CONFIG_PAGE_SIZE_4KB=y
112CONFIG_MIPS_MT_DISABLED=y 112CONFIG_MIPS_MT_DISABLED=y
113# CONFIG_MIPS_MT_SMP is not set 113# CONFIG_MIPS_MT_SMP is not set
114# CONFIG_MIPS_MT_SMTC is not set 114# CONFIG_MIPS_MT_SMTC is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_HAS_SYNC=y 115CONFIG_CPU_HAS_SYNC=y
117CONFIG_GENERIC_HARDIRQS=y 116CONFIG_GENERIC_HARDIRQS=y
118CONFIG_GENERIC_IRQ_PROBE=y 117CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index a279165e3a7d..dbdf3bb1a34a 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMTC is not set 114# CONFIG_MIPS_MT_SMTC is not set
115# CONFIG_MIPS_VPE_LOADER is not set 115# CONFIG_MIPS_VPE_LOADER is not set
116CONFIG_64BIT_PHYS_ADDR=y 116CONFIG_64BIT_PHYS_ADDR=y
117CONFIG_CPU_HAS_LLSC=y
118CONFIG_CPU_HAS_SYNC=y 117CONFIG_CPU_HAS_SYNC=y
119CONFIG_GENERIC_HARDIRQS=y 118CONFIG_GENERIC_HARDIRQS=y
120CONFIG_GENERIC_IRQ_PROBE=y 119CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 8944d15caf13..fa6814475898 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMTC is not set 114# CONFIG_MIPS_MT_SMTC is not set
115# CONFIG_MIPS_VPE_LOADER is not set 115# CONFIG_MIPS_VPE_LOADER is not set
116CONFIG_64BIT_PHYS_ADDR=y 116CONFIG_64BIT_PHYS_ADDR=y
117CONFIG_CPU_HAS_LLSC=y
118CONFIG_CPU_HAS_SYNC=y 117CONFIG_CPU_HAS_SYNC=y
119CONFIG_GENERIC_HARDIRQS=y 118CONFIG_GENERIC_HARDIRQS=y
120CONFIG_GENERIC_IRQ_PROBE=y 119CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index ab17973107fd..d73f1de43b5d 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMTC is not set 114# CONFIG_MIPS_MT_SMTC is not set
115# CONFIG_MIPS_VPE_LOADER is not set 115# CONFIG_MIPS_VPE_LOADER is not set
116CONFIG_64BIT_PHYS_ADDR=y 116CONFIG_64BIT_PHYS_ADDR=y
117CONFIG_CPU_HAS_LLSC=y
118CONFIG_CPU_HAS_SYNC=y 117CONFIG_CPU_HAS_SYNC=y
119CONFIG_GENERIC_HARDIRQS=y 118CONFIG_GENERIC_HARDIRQS=y
120CONFIG_GENERIC_IRQ_PROBE=y 119CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index b65803f19352..ec3e028a5b2e 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -116,7 +116,6 @@ CONFIG_MIPS_MT_DISABLED=y
116# CONFIG_MIPS_MT_SMTC is not set 116# CONFIG_MIPS_MT_SMTC is not set
117# CONFIG_MIPS_VPE_LOADER is not set 117# CONFIG_MIPS_VPE_LOADER is not set
118CONFIG_64BIT_PHYS_ADDR=y 118CONFIG_64BIT_PHYS_ADDR=y
119CONFIG_CPU_HAS_LLSC=y
120CONFIG_CPU_HAS_SYNC=y 119CONFIG_CPU_HAS_SYNC=y
121CONFIG_GENERIC_HARDIRQS=y 120CONFIG_GENERIC_HARDIRQS=y
122CONFIG_GENERIC_IRQ_PROBE=y 121CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index a190ac07740b..7631dae51be9 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
115# CONFIG_MIPS_MT_SMTC is not set 115# CONFIG_MIPS_MT_SMTC is not set
116# CONFIG_MIPS_VPE_LOADER is not set 116# CONFIG_MIPS_VPE_LOADER is not set
117CONFIG_64BIT_PHYS_ADDR=y 117CONFIG_64BIT_PHYS_ADDR=y
118CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_SYNC=y 118CONFIG_CPU_HAS_SYNC=y
120CONFIG_GENERIC_HARDIRQS=y 119CONFIG_GENERIC_HARDIRQS=y
121CONFIG_GENERIC_IRQ_PROBE=y 120CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 4e465e945991..1995d43a2ed1 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -118,7 +118,6 @@ CONFIG_MIPS_MT_DISABLED=y
118# CONFIG_MIPS_MT_SMTC is not set 118# CONFIG_MIPS_MT_SMTC is not set
119# CONFIG_MIPS_VPE_LOADER is not set 119# CONFIG_MIPS_VPE_LOADER is not set
120# CONFIG_64BIT_PHYS_ADDR is not set 120# CONFIG_64BIT_PHYS_ADDR is not set
121CONFIG_CPU_HAS_LLSC=y
122CONFIG_CPU_HAS_SYNC=y 121CONFIG_CPU_HAS_SYNC=y
123CONFIG_GENERIC_HARDIRQS=y 122CONFIG_GENERIC_HARDIRQS=y
124CONFIG_GENERIC_IRQ_PROBE=y 123CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fuloong2e_defconfig
index 786a9bc9a696..0197f0de6b3f 100644
--- a/arch/mips/configs/fulong_defconfig
+++ b/arch/mips/configs/fuloong2e_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc6 3# Linux kernel version: 2.6.31-rc1
4# Fri Nov 28 17:53:48 2008 4# Thu Jul 2 22:37:00 2009
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -9,16 +9,17 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set
12# CONFIG_BASLER_EXCITE is not set 13# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 14# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set 18# CONFIG_LASAT is not set
18CONFIG_LEMOTE_FULONG=y 19CONFIG_MACH_LOONGSON=y
19# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
21# CONFIG_MACH_EMMA is not set 22# CONFIG_NEC_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set 23# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set 24# CONFIG_NXP_STB220 is not set
24# CONFIG_NXP_STB225 is not set 25# CONFIG_NXP_STB225 is not set
@@ -43,6 +44,11 @@ CONFIG_LEMOTE_FULONG=y
43# CONFIG_MACH_TX49XX is not set 44# CONFIG_MACH_TX49XX is not set
44# CONFIG_MIKROTIK_RB532 is not set 45# CONFIG_MIKROTIK_RB532 is not set
45# CONFIG_WR_PPMC is not set 46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50CONFIG_ARCH_SPARSEMEM_ENABLE=y
51CONFIG_LEMOTE_FULOONG2E=y
46CONFIG_RWSEM_GENERIC_SPINLOCK=y 52CONFIG_RWSEM_GENERIC_SPINLOCK=y
47# CONFIG_ARCH_HAS_ILOG2_U32 is not set 53# CONFIG_ARCH_HAS_ILOG2_U32 is not set
48# CONFIG_ARCH_HAS_ILOG2_U64 is not set 54# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -53,15 +59,16 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
53CONFIG_GENERIC_CLOCKEVENTS=y 59CONFIG_GENERIC_CLOCKEVENTS=y
54CONFIG_GENERIC_TIME=y 60CONFIG_GENERIC_TIME=y
55CONFIG_GENERIC_CMOS_UPDATE=y 61CONFIG_GENERIC_CMOS_UPDATE=y
56CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 62CONFIG_SCHED_OMIT_FRAME_POINTER=y
57CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 63CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
64CONFIG_CEVT_R4K_LIB=y
58CONFIG_CEVT_R4K=y 65CONFIG_CEVT_R4K=y
66CONFIG_CSRC_R4K_LIB=y
59CONFIG_CSRC_R4K=y 67CONFIG_CSRC_R4K=y
60CONFIG_DMA_NONCOHERENT=y 68CONFIG_DMA_NONCOHERENT=y
61CONFIG_DMA_NEED_PCI_MAP_STATE=y 69CONFIG_DMA_NEED_PCI_MAP_STATE=y
62CONFIG_EARLY_PRINTK=y 70CONFIG_EARLY_PRINTK=y
63CONFIG_SYS_HAS_EARLY_PRINTK=y 71CONFIG_SYS_HAS_EARLY_PRINTK=y
64# CONFIG_HOTPLUG_CPU is not set
65CONFIG_I8259=y 72CONFIG_I8259=y
66# CONFIG_NO_IOPORT is not set 73# CONFIG_NO_IOPORT is not set
67CONFIG_GENERIC_ISA_DMA=y 74CONFIG_GENERIC_ISA_DMA=y
@@ -72,12 +79,11 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
72CONFIG_IRQ_CPU=y 79CONFIG_IRQ_CPU=y
73CONFIG_BOOT_ELF32=y 80CONFIG_BOOT_ELF32=y
74CONFIG_MIPS_L1_CACHE_SHIFT=5 81CONFIG_MIPS_L1_CACHE_SHIFT=5
75CONFIG_HAVE_STD_PC_SERIAL_PORT=y
76 82
77# 83#
78# CPU selection 84# CPU selection
79# 85#
80CONFIG_CPU_LOONGSON2=y 86CONFIG_CPU_LOONGSON2E=y
81# CONFIG_CPU_MIPS32_R1 is not set 87# CONFIG_CPU_MIPS32_R1 is not set
82# CONFIG_CPU_MIPS32_R2 is not set 88# CONFIG_CPU_MIPS32_R2 is not set
83# CONFIG_CPU_MIPS64_R1 is not set 89# CONFIG_CPU_MIPS64_R1 is not set
@@ -98,7 +104,9 @@ CONFIG_CPU_LOONGSON2=y
98# CONFIG_CPU_RM7000 is not set 104# CONFIG_CPU_RM7000 is not set
99# CONFIG_CPU_RM9000 is not set 105# CONFIG_CPU_RM9000 is not set
100# CONFIG_CPU_SB1 is not set 106# CONFIG_CPU_SB1 is not set
101CONFIG_SYS_HAS_CPU_LOONGSON2=y 107# CONFIG_CPU_CAVIUM_OCTEON is not set
108CONFIG_CPU_LOONGSON2=y
109CONFIG_SYS_HAS_CPU_LOONGSON2E=y
102CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 110CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
103CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y 111CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
104CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 112CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
@@ -112,6 +120,7 @@ CONFIG_64BIT=y
112# CONFIG_PAGE_SIZE_4KB is not set 120# CONFIG_PAGE_SIZE_4KB is not set
113# CONFIG_PAGE_SIZE_8KB is not set 121# CONFIG_PAGE_SIZE_8KB is not set
114CONFIG_PAGE_SIZE_16KB=y 122CONFIG_PAGE_SIZE_16KB=y
123# CONFIG_PAGE_SIZE_32KB is not set
115# CONFIG_PAGE_SIZE_64KB is not set 124# CONFIG_PAGE_SIZE_64KB is not set
116CONFIG_BOARD_SCACHE=y 125CONFIG_BOARD_SCACHE=y
117CONFIG_MIPS_MT_DISABLED=y 126CONFIG_MIPS_MT_DISABLED=y
@@ -125,7 +134,6 @@ CONFIG_CPU_SUPPORTS_HIGHMEM=y
125CONFIG_SYS_SUPPORTS_HIGHMEM=y 134CONFIG_SYS_SUPPORTS_HIGHMEM=y
126CONFIG_ARCH_FLATMEM_ENABLE=y 135CONFIG_ARCH_FLATMEM_ENABLE=y
127CONFIG_ARCH_POPULATES_NODE_MAP=y 136CONFIG_ARCH_POPULATES_NODE_MAP=y
128CONFIG_ARCH_SPARSEMEM_ENABLE=y
129CONFIG_SELECT_MEMORY_MODEL=y 137CONFIG_SELECT_MEMORY_MODEL=y
130CONFIG_FLATMEM_MANUAL=y 138CONFIG_FLATMEM_MANUAL=y
131# CONFIG_DISCONTIGMEM_MANUAL is not set 139# CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -135,11 +143,12 @@ CONFIG_FLAT_NODE_MEM_MAP=y
135CONFIG_SPARSEMEM_STATIC=y 143CONFIG_SPARSEMEM_STATIC=y
136CONFIG_PAGEFLAGS_EXTENDED=y 144CONFIG_PAGEFLAGS_EXTENDED=y
137CONFIG_SPLIT_PTLOCK_CPUS=4 145CONFIG_SPLIT_PTLOCK_CPUS=4
138CONFIG_RESOURCES_64BIT=y
139CONFIG_PHYS_ADDR_T_64BIT=y 146CONFIG_PHYS_ADDR_T_64BIT=y
140CONFIG_ZONE_DMA_FLAG=0 147CONFIG_ZONE_DMA_FLAG=0
141CONFIG_VIRT_TO_BUS=y 148CONFIG_VIRT_TO_BUS=y
142CONFIG_UNEVICTABLE_LRU=y 149CONFIG_HAVE_MLOCK=y
150CONFIG_HAVE_MLOCKED_PAGE_BIT=y
151CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
143CONFIG_TICK_ONESHOT=y 152CONFIG_TICK_ONESHOT=y
144CONFIG_NO_HZ=y 153CONFIG_NO_HZ=y
145CONFIG_HIGH_RES_TIMERS=y 154CONFIG_HIGH_RES_TIMERS=y
@@ -161,6 +170,7 @@ CONFIG_SECCOMP=y
161CONFIG_LOCKDEP_SUPPORT=y 170CONFIG_LOCKDEP_SUPPORT=y
162CONFIG_STACKTRACE_SUPPORT=y 171CONFIG_STACKTRACE_SUPPORT=y
163CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 172CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
173CONFIG_CONSTRUCTORS=y
164 174
165# 175#
166# General setup 176# General setup
@@ -168,21 +178,31 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
168CONFIG_EXPERIMENTAL=y 178CONFIG_EXPERIMENTAL=y
169CONFIG_BROKEN_ON_SMP=y 179CONFIG_BROKEN_ON_SMP=y
170CONFIG_INIT_ENV_ARG_LIMIT=32 180CONFIG_INIT_ENV_ARG_LIMIT=32
171CONFIG_LOCALVERSION="lm32" 181CONFIG_LOCALVERSION="-fuloong2e"
172# CONFIG_LOCALVERSION_AUTO is not set 182# CONFIG_LOCALVERSION_AUTO is not set
173CONFIG_SWAP=y 183CONFIG_SWAP=y
174CONFIG_SYSVIPC=y 184CONFIG_SYSVIPC=y
175CONFIG_SYSVIPC_SYSCTL=y 185CONFIG_SYSVIPC_SYSCTL=y
176CONFIG_POSIX_MQUEUE=y 186CONFIG_POSIX_MQUEUE=y
187CONFIG_POSIX_MQUEUE_SYSCTL=y
177CONFIG_BSD_PROCESS_ACCT=y 188CONFIG_BSD_PROCESS_ACCT=y
178# CONFIG_BSD_PROCESS_ACCT_V3 is not set 189# CONFIG_BSD_PROCESS_ACCT_V3 is not set
179# CONFIG_TASKSTATS is not set 190# CONFIG_TASKSTATS is not set
180# CONFIG_AUDIT is not set 191# CONFIG_AUDIT is not set
192
193#
194# RCU Subsystem
195#
196CONFIG_CLASSIC_RCU=y
197# CONFIG_TREE_RCU is not set
198# CONFIG_PREEMPT_RCU is not set
199# CONFIG_TREE_RCU_TRACE is not set
200# CONFIG_PREEMPT_RCU_TRACE is not set
181CONFIG_IKCONFIG=y 201CONFIG_IKCONFIG=y
182CONFIG_IKCONFIG_PROC=y 202CONFIG_IKCONFIG_PROC=y
183CONFIG_LOG_BUF_SHIFT=14 203CONFIG_LOG_BUF_SHIFT=14
184# CONFIG_CGROUPS is not set
185# CONFIG_GROUP_SCHED is not set 204# CONFIG_GROUP_SCHED is not set
205# CONFIG_CGROUPS is not set
186CONFIG_SYSFS_DEPRECATED=y 206CONFIG_SYSFS_DEPRECATED=y
187CONFIG_SYSFS_DEPRECATED_V2=y 207CONFIG_SYSFS_DEPRECATED_V2=y
188# CONFIG_RELAY is not set 208# CONFIG_RELAY is not set
@@ -191,9 +211,11 @@ CONFIG_NAMESPACES=y
191# CONFIG_IPC_NS is not set 211# CONFIG_IPC_NS is not set
192CONFIG_USER_NS=y 212CONFIG_USER_NS=y
193CONFIG_PID_NS=y 213CONFIG_PID_NS=y
214# CONFIG_NET_NS is not set
194# CONFIG_BLK_DEV_INITRD is not set 215# CONFIG_BLK_DEV_INITRD is not set
195# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 216# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
196CONFIG_SYSCTL=y 217CONFIG_SYSCTL=y
218CONFIG_ANON_INODES=y
197CONFIG_EMBEDDED=y 219CONFIG_EMBEDDED=y
198CONFIG_SYSCTL_SYSCALL=y 220CONFIG_SYSCTL_SYSCALL=y
199CONFIG_KALLSYMS=y 221CONFIG_KALLSYMS=y
@@ -203,29 +225,40 @@ CONFIG_PRINTK=y
203CONFIG_BUG=y 225CONFIG_BUG=y
204CONFIG_ELF_CORE=y 226CONFIG_ELF_CORE=y
205# CONFIG_PCSPKR_PLATFORM is not set 227# CONFIG_PCSPKR_PLATFORM is not set
206# CONFIG_COMPAT_BRK is not set
207CONFIG_BASE_FULL=y 228CONFIG_BASE_FULL=y
208CONFIG_FUTEX=y 229CONFIG_FUTEX=y
209CONFIG_ANON_INODES=y
210CONFIG_EPOLL=y 230CONFIG_EPOLL=y
211CONFIG_SIGNALFD=y 231CONFIG_SIGNALFD=y
212CONFIG_TIMERFD=y 232CONFIG_TIMERFD=y
213CONFIG_EVENTFD=y 233CONFIG_EVENTFD=y
214CONFIG_SHMEM=y 234CONFIG_SHMEM=y
215CONFIG_AIO=y 235CONFIG_AIO=y
236
237#
238# Performance Counters
239#
216CONFIG_VM_EVENT_COUNTERS=y 240CONFIG_VM_EVENT_COUNTERS=y
217CONFIG_PCI_QUIRKS=y 241CONFIG_PCI_QUIRKS=y
242# CONFIG_STRIP_ASM_SYMS is not set
243# CONFIG_COMPAT_BRK is not set
218CONFIG_SLAB=y 244CONFIG_SLAB=y
219# CONFIG_SLUB is not set 245# CONFIG_SLUB is not set
220# CONFIG_SLOB is not set 246# CONFIG_SLOB is not set
221CONFIG_PROFILING=y 247CONFIG_PROFILING=y
222# CONFIG_MARKERS is not set 248CONFIG_TRACEPOINTS=y
249CONFIG_MARKERS=y
223CONFIG_OPROFILE=m 250CONFIG_OPROFILE=m
224CONFIG_HAVE_OPROFILE=y 251CONFIG_HAVE_OPROFILE=y
252CONFIG_HAVE_SYSCALL_WRAPPERS=y
253
254#
255# GCOV-based kernel profiling
256#
257# CONFIG_GCOV_KERNEL is not set
258# CONFIG_SLOW_WORK is not set
225# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 259# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
226CONFIG_SLABINFO=y 260CONFIG_SLABINFO=y
227CONFIG_RT_MUTEXES=y 261CONFIG_RT_MUTEXES=y
228# CONFIG_TINY_SHMEM is not set
229CONFIG_BASE_SMALL=0 262CONFIG_BASE_SMALL=0
230CONFIG_MODULES=y 263CONFIG_MODULES=y
231# CONFIG_MODULE_FORCE_LOAD is not set 264# CONFIG_MODULE_FORCE_LOAD is not set
@@ -233,9 +266,7 @@ CONFIG_MODULE_UNLOAD=y
233CONFIG_MODULE_FORCE_UNLOAD=y 266CONFIG_MODULE_FORCE_UNLOAD=y
234# CONFIG_MODVERSIONS is not set 267# CONFIG_MODVERSIONS is not set
235# CONFIG_MODULE_SRCVERSION_ALL is not set 268# CONFIG_MODULE_SRCVERSION_ALL is not set
236CONFIG_KMOD=y
237CONFIG_BLOCK=y 269CONFIG_BLOCK=y
238# CONFIG_BLK_DEV_IO_TRACE is not set
239CONFIG_BLK_DEV_BSG=y 270CONFIG_BLK_DEV_BSG=y
240# CONFIG_BLK_DEV_INTEGRITY is not set 271# CONFIG_BLK_DEV_INTEGRITY is not set
241CONFIG_BLOCK_COMPAT=y 272CONFIG_BLOCK_COMPAT=y
@@ -252,8 +283,7 @@ CONFIG_IOSCHED_CFQ=y
252CONFIG_DEFAULT_CFQ=y 283CONFIG_DEFAULT_CFQ=y
253# CONFIG_DEFAULT_NOOP is not set 284# CONFIG_DEFAULT_NOOP is not set
254CONFIG_DEFAULT_IOSCHED="cfq" 285CONFIG_DEFAULT_IOSCHED="cfq"
255CONFIG_CLASSIC_RCU=y 286# CONFIG_FREEZER is not set
256CONFIG_FREEZER=y
257 287
258# 288#
259# Bus options (PCI, PCMCIA, EISA, ISA, TC) 289# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -263,6 +293,8 @@ CONFIG_PCI=y
263CONFIG_PCI_DOMAINS=y 293CONFIG_PCI_DOMAINS=y
264# CONFIG_ARCH_SUPPORTS_MSI is not set 294# CONFIG_ARCH_SUPPORTS_MSI is not set
265CONFIG_PCI_LEGACY=y 295CONFIG_PCI_LEGACY=y
296# CONFIG_PCI_STUB is not set
297# CONFIG_PCI_IOV is not set
266CONFIG_ISA=y 298CONFIG_ISA=y
267CONFIG_MMU=y 299CONFIG_MMU=y
268# CONFIG_PCCARD is not set 300# CONFIG_PCCARD is not set
@@ -285,12 +317,12 @@ CONFIG_BINFMT_ELF32=y
285# 317#
286# Power management options 318# Power management options
287# 319#
320CONFIG_ARCH_HIBERNATION_POSSIBLE=y
288CONFIG_ARCH_SUSPEND_POSSIBLE=y 321CONFIG_ARCH_SUSPEND_POSSIBLE=y
289CONFIG_PM=y 322CONFIG_PM=y
290# CONFIG_PM_DEBUG is not set 323# CONFIG_PM_DEBUG is not set
291CONFIG_PM_SLEEP=y 324# CONFIG_SUSPEND is not set
292CONFIG_SUSPEND=y 325# CONFIG_HIBERNATION is not set
293CONFIG_SUSPEND_FREEZER=y
294CONFIG_NET=y 326CONFIG_NET=y
295 327
296# 328#
@@ -346,9 +378,11 @@ CONFIG_NETFILTER_NETLINK=m
346CONFIG_NETFILTER_NETLINK_QUEUE=m 378CONFIG_NETFILTER_NETLINK_QUEUE=m
347CONFIG_NETFILTER_NETLINK_LOG=m 379CONFIG_NETFILTER_NETLINK_LOG=m
348# CONFIG_NF_CONNTRACK is not set 380# CONFIG_NF_CONNTRACK is not set
381# CONFIG_NETFILTER_TPROXY is not set
349CONFIG_NETFILTER_XTABLES=m 382CONFIG_NETFILTER_XTABLES=m
350CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m 383CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
351# CONFIG_NETFILTER_XT_TARGET_DSCP is not set 384# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
385CONFIG_NETFILTER_XT_TARGET_HL=m
352CONFIG_NETFILTER_XT_TARGET_MARK=m 386CONFIG_NETFILTER_XT_TARGET_MARK=m
353# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set 387# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
354CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 388CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
@@ -361,6 +395,7 @@ CONFIG_NETFILTER_XT_MATCH_DCCP=m
361# CONFIG_NETFILTER_XT_MATCH_DSCP is not set 395# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
362CONFIG_NETFILTER_XT_MATCH_ESP=m 396CONFIG_NETFILTER_XT_MATCH_ESP=m
363# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set 397# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
398CONFIG_NETFILTER_XT_MATCH_HL=m
364CONFIG_NETFILTER_XT_MATCH_IPRANGE=m 399CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
365CONFIG_NETFILTER_XT_MATCH_LENGTH=m 400CONFIG_NETFILTER_XT_MATCH_LENGTH=m
366CONFIG_NETFILTER_XT_MATCH_LIMIT=m 401CONFIG_NETFILTER_XT_MATCH_LIMIT=m
@@ -381,6 +416,7 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
381CONFIG_NETFILTER_XT_MATCH_TCPMSS=m 416CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
382CONFIG_NETFILTER_XT_MATCH_TIME=m 417CONFIG_NETFILTER_XT_MATCH_TIME=m
383CONFIG_NETFILTER_XT_MATCH_U32=m 418CONFIG_NETFILTER_XT_MATCH_U32=m
419# CONFIG_NETFILTER_XT_MATCH_OSF is not set
384# CONFIG_IP_VS is not set 420# CONFIG_IP_VS is not set
385 421
386# 422#
@@ -419,30 +455,34 @@ CONFIG_IP_NF_ARP_MANGLE=m
419# CONFIG_LAPB is not set 455# CONFIG_LAPB is not set
420# CONFIG_ECONET is not set 456# CONFIG_ECONET is not set
421# CONFIG_WAN_ROUTER is not set 457# CONFIG_WAN_ROUTER is not set
458CONFIG_PHONET=m
459# CONFIG_IEEE802154 is not set
422# CONFIG_NET_SCHED is not set 460# CONFIG_NET_SCHED is not set
423CONFIG_NET_CLS_ROUTE=y 461CONFIG_NET_CLS_ROUTE=y
462# CONFIG_DCB is not set
424 463
425# 464#
426# Network testing 465# Network testing
427# 466#
428# CONFIG_NET_PKTGEN is not set 467# CONFIG_NET_PKTGEN is not set
468# CONFIG_NET_DROP_MONITOR is not set
429# CONFIG_HAMRADIO is not set 469# CONFIG_HAMRADIO is not set
430# CONFIG_CAN is not set 470# CONFIG_CAN is not set
431# CONFIG_IRDA is not set 471# CONFIG_IRDA is not set
432# CONFIG_BT is not set 472# CONFIG_BT is not set
433# CONFIG_AF_RXRPC is not set 473# CONFIG_AF_RXRPC is not set
434CONFIG_PHONET=m
435CONFIG_WIRELESS=y 474CONFIG_WIRELESS=y
436# CONFIG_CFG80211 is not set 475# CONFIG_CFG80211 is not set
437CONFIG_WIRELESS_OLD_REGULATORY=y 476CONFIG_WIRELESS_OLD_REGULATORY=y
438CONFIG_WIRELESS_EXT=y 477CONFIG_WIRELESS_EXT=y
439CONFIG_WIRELESS_EXT_SYSFS=y 478CONFIG_WIRELESS_EXT_SYSFS=y
440# CONFIG_MAC80211 is not set 479# CONFIG_LIB80211 is not set
441CONFIG_IEEE80211=m 480
442# CONFIG_IEEE80211_DEBUG is not set 481#
443CONFIG_IEEE80211_CRYPT_WEP=m 482# CFG80211 needs to be enabled for MAC80211
444# CONFIG_IEEE80211_CRYPT_CCMP is not set 483#
445# CONFIG_IEEE80211_CRYPT_TKIP is not set 484CONFIG_MAC80211_DEFAULT_PS_VALUE=0
485# CONFIG_WIMAX is not set
446# CONFIG_RFKILL is not set 486# CONFIG_RFKILL is not set
447CONFIG_NET_9P=m 487CONFIG_NET_9P=m
448# CONFIG_NET_9P_DEBUG is not set 488# CONFIG_NET_9P_DEBUG is not set
@@ -466,6 +506,7 @@ CONFIG_MTD=m
466# CONFIG_MTD_DEBUG is not set 506# CONFIG_MTD_DEBUG is not set
467# CONFIG_MTD_CONCAT is not set 507# CONFIG_MTD_CONCAT is not set
468# CONFIG_MTD_PARTITIONS is not set 508# CONFIG_MTD_PARTITIONS is not set
509# CONFIG_MTD_TESTS is not set
469 510
470# 511#
471# User Modules And Translation Layers 512# User Modules And Translation Layers
@@ -516,9 +557,7 @@ CONFIG_MTD_CFI_UTIL=m
516# 557#
517# CONFIG_MTD_COMPLEX_MAPPINGS is not set 558# CONFIG_MTD_COMPLEX_MAPPINGS is not set
518CONFIG_MTD_PHYSMAP=m 559CONFIG_MTD_PHYSMAP=m
519CONFIG_MTD_PHYSMAP_START=0x1fc00000 560# CONFIG_MTD_PHYSMAP_COMPAT is not set
520CONFIG_MTD_PHYSMAP_LEN=0x80000
521CONFIG_MTD_PHYSMAP_BANKWIDTH=1
522# CONFIG_MTD_INTEL_VR_NOR is not set 561# CONFIG_MTD_INTEL_VR_NOR is not set
523# CONFIG_MTD_PLATRAM is not set 562# CONFIG_MTD_PLATRAM is not set
524 563
@@ -541,6 +580,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
541# CONFIG_MTD_ONENAND is not set 580# CONFIG_MTD_ONENAND is not set
542 581
543# 582#
583# LPDDR flash memory drivers
584#
585# CONFIG_MTD_LPDDR is not set
586
587#
544# UBI - Unsorted block images 588# UBI - Unsorted block images
545# 589#
546# CONFIG_MTD_UBI is not set 590# CONFIG_MTD_UBI is not set
@@ -573,6 +617,7 @@ CONFIG_IDE=y
573# 617#
574# Please see Documentation/ide/ide.txt for help/info on IDE drives 618# Please see Documentation/ide/ide.txt for help/info on IDE drives
575# 619#
620CONFIG_IDE_XFER_MODE=y
576CONFIG_IDE_TIMINGS=y 621CONFIG_IDE_TIMINGS=y
577CONFIG_IDE_ATAPI=y 622CONFIG_IDE_ATAPI=y
578# CONFIG_BLK_DEV_IDE_SATA is not set 623# CONFIG_BLK_DEV_IDE_SATA is not set
@@ -582,7 +627,6 @@ CONFIG_IDE_GD_ATA=y
582CONFIG_BLK_DEV_IDECD=y 627CONFIG_BLK_DEV_IDECD=y
583CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y 628CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
584# CONFIG_BLK_DEV_IDETAPE is not set 629# CONFIG_BLK_DEV_IDETAPE is not set
585CONFIG_BLK_DEV_IDESCSI=y
586CONFIG_IDE_TASK_IOCTL=y 630CONFIG_IDE_TASK_IOCTL=y
587CONFIG_IDE_PROC_FS=y 631CONFIG_IDE_PROC_FS=y
588 632
@@ -613,6 +657,7 @@ CONFIG_BLK_DEV_IDEDMA_PCI=y
613# CONFIG_BLK_DEV_JMICRON is not set 657# CONFIG_BLK_DEV_JMICRON is not set
614# CONFIG_BLK_DEV_SC1200 is not set 658# CONFIG_BLK_DEV_SC1200 is not set
615# CONFIG_BLK_DEV_PIIX is not set 659# CONFIG_BLK_DEV_PIIX is not set
660# CONFIG_BLK_DEV_IT8172 is not set
616# CONFIG_BLK_DEV_IT8213 is not set 661# CONFIG_BLK_DEV_IT8213 is not set
617# CONFIG_BLK_DEV_IT821X is not set 662# CONFIG_BLK_DEV_IT821X is not set
618# CONFIG_BLK_DEV_NS87415 is not set 663# CONFIG_BLK_DEV_NS87415 is not set
@@ -660,10 +705,6 @@ CONFIG_BLK_DEV_SR=y
660CONFIG_BLK_DEV_SR_VENDOR=y 705CONFIG_BLK_DEV_SR_VENDOR=y
661CONFIG_CHR_DEV_SG=y 706CONFIG_CHR_DEV_SG=y
662# CONFIG_CHR_DEV_SCH is not set 707# CONFIG_CHR_DEV_SCH is not set
663
664#
665# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
666#
667# CONFIG_SCSI_MULTI_LUN is not set 708# CONFIG_SCSI_MULTI_LUN is not set
668CONFIG_SCSI_CONSTANTS=y 709CONFIG_SCSI_CONSTANTS=y
669# CONFIG_SCSI_LOGGING is not set 710# CONFIG_SCSI_LOGGING is not set
@@ -681,6 +722,7 @@ CONFIG_SCSI_WAIT_SCAN=m
681# CONFIG_SCSI_SRP_ATTRS is not set 722# CONFIG_SCSI_SRP_ATTRS is not set
682# CONFIG_SCSI_LOWLEVEL is not set 723# CONFIG_SCSI_LOWLEVEL is not set
683# CONFIG_SCSI_DH is not set 724# CONFIG_SCSI_DH is not set
725# CONFIG_SCSI_OSD_INITIATOR is not set
684# CONFIG_ATA is not set 726# CONFIG_ATA is not set
685# CONFIG_MD is not set 727# CONFIG_MD is not set
686# CONFIG_FUSION is not set 728# CONFIG_FUSION is not set
@@ -690,7 +732,11 @@ CONFIG_SCSI_WAIT_SCAN=m
690# 732#
691 733
692# 734#
693# Enable only one of the two stacks, unless you know what you are doing 735# You can enable one or both FireWire driver stacks.
736#
737
738#
739# See the help texts for more information.
694# 740#
695# CONFIG_FIREWIRE is not set 741# CONFIG_FIREWIRE is not set
696# CONFIG_IEEE1394 is not set 742# CONFIG_IEEE1394 is not set
@@ -718,6 +764,9 @@ CONFIG_CICADA_PHY=m
718# CONFIG_BROADCOM_PHY is not set 764# CONFIG_BROADCOM_PHY is not set
719# CONFIG_ICPLUS_PHY is not set 765# CONFIG_ICPLUS_PHY is not set
720# CONFIG_REALTEK_PHY is not set 766# CONFIG_REALTEK_PHY is not set
767# CONFIG_NATIONAL_PHY is not set
768# CONFIG_STE10XP is not set
769# CONFIG_LSI_ET1011C_PHY is not set
721# CONFIG_MDIO_BITBANG is not set 770# CONFIG_MDIO_BITBANG is not set
722CONFIG_NET_ETHERNET=y 771CONFIG_NET_ETHERNET=y
723CONFIG_MII=y 772CONFIG_MII=y
@@ -729,7 +778,9 @@ CONFIG_MII=y
729# CONFIG_NET_VENDOR_SMC is not set 778# CONFIG_NET_VENDOR_SMC is not set
730# CONFIG_SMC91X is not set 779# CONFIG_SMC91X is not set
731# CONFIG_DM9000 is not set 780# CONFIG_DM9000 is not set
781# CONFIG_ETHOC is not set
732# CONFIG_NET_VENDOR_RACAL is not set 782# CONFIG_NET_VENDOR_RACAL is not set
783# CONFIG_DNET is not set
733# CONFIG_NET_TULIP is not set 784# CONFIG_NET_TULIP is not set
734# CONFIG_AT1700 is not set 785# CONFIG_AT1700 is not set
735# CONFIG_DEPCA is not set 786# CONFIG_DEPCA is not set
@@ -752,7 +803,6 @@ CONFIG_NET_PCI=y
752# CONFIG_FORCEDETH is not set 803# CONFIG_FORCEDETH is not set
753# CONFIG_CS89x0 is not set 804# CONFIG_CS89x0 is not set
754# CONFIG_TC35815 is not set 805# CONFIG_TC35815 is not set
755# CONFIG_EEPRO100 is not set
756# CONFIG_E100 is not set 806# CONFIG_E100 is not set
757# CONFIG_FEALNX is not set 807# CONFIG_FEALNX is not set
758# CONFIG_NATSEMI is not set 808# CONFIG_NATSEMI is not set
@@ -766,8 +816,10 @@ CONFIG_8139TOO=y
766# CONFIG_R6040 is not set 816# CONFIG_R6040 is not set
767# CONFIG_SIS900 is not set 817# CONFIG_SIS900 is not set
768# CONFIG_EPIC100 is not set 818# CONFIG_EPIC100 is not set
819# CONFIG_SMSC9420 is not set
769# CONFIG_SUNDANCE is not set 820# CONFIG_SUNDANCE is not set
770# CONFIG_TLAN is not set 821# CONFIG_TLAN is not set
822# CONFIG_KS8842 is not set
771# CONFIG_VIA_RHINE is not set 823# CONFIG_VIA_RHINE is not set
772# CONFIG_SC92031 is not set 824# CONFIG_SC92031 is not set
773# CONFIG_ATL2 is not set 825# CONFIG_ATL2 is not set
@@ -778,6 +830,7 @@ CONFIG_NETDEV_1000=y
778# CONFIG_E1000E is not set 830# CONFIG_E1000E is not set
779# CONFIG_IP1000 is not set 831# CONFIG_IP1000 is not set
780# CONFIG_IGB is not set 832# CONFIG_IGB is not set
833# CONFIG_IGBVF is not set
781# CONFIG_NS83820 is not set 834# CONFIG_NS83820 is not set
782# CONFIG_HAMACHI is not set 835# CONFIG_HAMACHI is not set
783# CONFIG_YELLOWFIN is not set 836# CONFIG_YELLOWFIN is not set
@@ -788,17 +841,21 @@ CONFIG_NETDEV_1000=y
788# CONFIG_VIA_VELOCITY is not set 841# CONFIG_VIA_VELOCITY is not set
789# CONFIG_TIGON3 is not set 842# CONFIG_TIGON3 is not set
790# CONFIG_BNX2 is not set 843# CONFIG_BNX2 is not set
844# CONFIG_CNIC is not set
791# CONFIG_QLA3XXX is not set 845# CONFIG_QLA3XXX is not set
792# CONFIG_ATL1 is not set 846# CONFIG_ATL1 is not set
793# CONFIG_ATL1E is not set 847# CONFIG_ATL1E is not set
848# CONFIG_ATL1C is not set
794# CONFIG_JME is not set 849# CONFIG_JME is not set
795CONFIG_NETDEV_10000=y 850CONFIG_NETDEV_10000=y
796# CONFIG_CHELSIO_T1 is not set 851# CONFIG_CHELSIO_T1 is not set
852CONFIG_CHELSIO_T3_DEPENDS=y
797# CONFIG_CHELSIO_T3 is not set 853# CONFIG_CHELSIO_T3 is not set
798# CONFIG_ENIC is not set 854# CONFIG_ENIC is not set
799# CONFIG_IXGBE is not set 855# CONFIG_IXGBE is not set
800# CONFIG_IXGB is not set 856# CONFIG_IXGB is not set
801# CONFIG_S2IO is not set 857# CONFIG_S2IO is not set
858# CONFIG_VXGE is not set
802# CONFIG_MYRI10GE is not set 859# CONFIG_MYRI10GE is not set
803# CONFIG_NETXEN_NIC is not set 860# CONFIG_NETXEN_NIC is not set
804# CONFIG_NIU is not set 861# CONFIG_NIU is not set
@@ -808,6 +865,7 @@ CONFIG_NETDEV_10000=y
808# CONFIG_BNX2X is not set 865# CONFIG_BNX2X is not set
809# CONFIG_QLGE is not set 866# CONFIG_QLGE is not set
810# CONFIG_SFC is not set 867# CONFIG_SFC is not set
868# CONFIG_BE2NET is not set
811# CONFIG_TR is not set 869# CONFIG_TR is not set
812 870
813# 871#
@@ -815,7 +873,10 @@ CONFIG_NETDEV_10000=y
815# 873#
816# CONFIG_WLAN_PRE80211 is not set 874# CONFIG_WLAN_PRE80211 is not set
817# CONFIG_WLAN_80211 is not set 875# CONFIG_WLAN_80211 is not set
818# CONFIG_IWLWIFI_LEDS is not set 876
877#
878# Enable WiMAX (Networking options) to see the WiMAX drivers
879#
819 880
820# 881#
821# USB Network Adapters 882# USB Network Adapters
@@ -872,7 +933,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
872# Input Device Drivers 933# Input Device Drivers
873# 934#
874CONFIG_INPUT_KEYBOARD=y 935CONFIG_INPUT_KEYBOARD=y
875CONFIG_KEYBOARD_ATKBD=m 936CONFIG_KEYBOARD_ATKBD=y
876# CONFIG_KEYBOARD_SUNKBD is not set 937# CONFIG_KEYBOARD_SUNKBD is not set
877# CONFIG_KEYBOARD_LKKBD is not set 938# CONFIG_KEYBOARD_LKKBD is not set
878# CONFIG_KEYBOARD_XTKBD is not set 939# CONFIG_KEYBOARD_XTKBD is not set
@@ -883,7 +944,6 @@ CONFIG_MOUSE_PS2=y
883CONFIG_MOUSE_PS2_ALPS=y 944CONFIG_MOUSE_PS2_ALPS=y
884CONFIG_MOUSE_PS2_LOGIPS2PP=y 945CONFIG_MOUSE_PS2_LOGIPS2PP=y
885CONFIG_MOUSE_PS2_SYNAPTICS=y 946CONFIG_MOUSE_PS2_SYNAPTICS=y
886CONFIG_MOUSE_PS2_LIFEBOOK=y
887CONFIG_MOUSE_PS2_TRACKPOINT=y 947CONFIG_MOUSE_PS2_TRACKPOINT=y
888# CONFIG_MOUSE_PS2_ELANTECH is not set 948# CONFIG_MOUSE_PS2_ELANTECH is not set
889# CONFIG_MOUSE_PS2_TOUCHKIT is not set 949# CONFIG_MOUSE_PS2_TOUCHKIT is not set
@@ -894,6 +954,7 @@ CONFIG_MOUSE_SERIAL=y
894# CONFIG_MOUSE_LOGIBM is not set 954# CONFIG_MOUSE_LOGIBM is not set
895# CONFIG_MOUSE_PC110PAD is not set 955# CONFIG_MOUSE_PC110PAD is not set
896# CONFIG_MOUSE_VSXXXAA is not set 956# CONFIG_MOUSE_VSXXXAA is not set
957# CONFIG_MOUSE_SYNAPTICS_I2C is not set
897# CONFIG_INPUT_JOYSTICK is not set 958# CONFIG_INPUT_JOYSTICK is not set
898# CONFIG_INPUT_TABLET is not set 959# CONFIG_INPUT_TABLET is not set
899# CONFIG_INPUT_TOUCHSCREEN is not set 960# CONFIG_INPUT_TOUCHSCREEN is not set
@@ -939,10 +1000,13 @@ CONFIG_SERIAL_CORE=y
939CONFIG_SERIAL_CORE_CONSOLE=y 1000CONFIG_SERIAL_CORE_CONSOLE=y
940# CONFIG_SERIAL_JSM is not set 1001# CONFIG_SERIAL_JSM is not set
941CONFIG_UNIX98_PTYS=y 1002CONFIG_UNIX98_PTYS=y
1003# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
942CONFIG_LEGACY_PTYS=y 1004CONFIG_LEGACY_PTYS=y
943CONFIG_LEGACY_PTY_COUNT=256 1005CONFIG_LEGACY_PTY_COUNT=256
944# CONFIG_IPMI_HANDLER is not set 1006# CONFIG_IPMI_HANDLER is not set
945CONFIG_HW_RANDOM=y 1007CONFIG_HW_RANDOM=y
1008# CONFIG_HW_RANDOM_TIMERIOMEM is not set
1009CONFIG_RTC=y
946# CONFIG_DTLK is not set 1010# CONFIG_DTLK is not set
947# CONFIG_R3964 is not set 1011# CONFIG_R3964 is not set
948# CONFIG_APPLICOM is not set 1012# CONFIG_APPLICOM is not set
@@ -1006,19 +1070,20 @@ CONFIG_I2C_VIAPRO=m
1006# Miscellaneous I2C Chip support 1070# Miscellaneous I2C Chip support
1007# 1071#
1008# CONFIG_DS1682 is not set 1072# CONFIG_DS1682 is not set
1009# CONFIG_EEPROM_AT24 is not set
1010# CONFIG_EEPROM_LEGACY is not set
1011# CONFIG_SENSORS_PCF8574 is not set 1073# CONFIG_SENSORS_PCF8574 is not set
1012# CONFIG_PCF8575 is not set 1074# CONFIG_PCF8575 is not set
1013# CONFIG_SENSORS_PCA9539 is not set 1075# CONFIG_SENSORS_PCA9539 is not set
1014# CONFIG_SENSORS_PCF8591 is not set
1015# CONFIG_SENSORS_MAX6875 is not set
1016# CONFIG_SENSORS_TSL2550 is not set 1076# CONFIG_SENSORS_TSL2550 is not set
1017# CONFIG_I2C_DEBUG_CORE is not set 1077# CONFIG_I2C_DEBUG_CORE is not set
1018# CONFIG_I2C_DEBUG_ALGO is not set 1078# CONFIG_I2C_DEBUG_ALGO is not set
1019# CONFIG_I2C_DEBUG_BUS is not set 1079# CONFIG_I2C_DEBUG_BUS is not set
1020# CONFIG_I2C_DEBUG_CHIP is not set 1080# CONFIG_I2C_DEBUG_CHIP is not set
1021# CONFIG_SPI is not set 1081# CONFIG_SPI is not set
1082
1083#
1084# PPS support
1085#
1086# CONFIG_PPS is not set
1022# CONFIG_W1 is not set 1087# CONFIG_W1 is not set
1023# CONFIG_POWER_SUPPLY is not set 1088# CONFIG_POWER_SUPPLY is not set
1024# CONFIG_HWMON is not set 1089# CONFIG_HWMON is not set
@@ -1041,140 +1106,10 @@ CONFIG_SSB_POSSIBLE=y
1041# CONFIG_MFD_TMIO is not set 1106# CONFIG_MFD_TMIO is not set
1042# CONFIG_MFD_WM8400 is not set 1107# CONFIG_MFD_WM8400 is not set
1043# CONFIG_MFD_WM8350_I2C is not set 1108# CONFIG_MFD_WM8350_I2C is not set
1109# CONFIG_MFD_PCF50633 is not set
1110# CONFIG_AB3100_CORE is not set
1044# CONFIG_REGULATOR is not set 1111# CONFIG_REGULATOR is not set
1045 1112# CONFIG_MEDIA_SUPPORT is not set
1046#
1047# Multimedia devices
1048#
1049
1050#
1051# Multimedia core support
1052#
1053CONFIG_VIDEO_DEV=m
1054CONFIG_VIDEO_V4L2_COMMON=m
1055CONFIG_VIDEO_ALLOW_V4L1=y
1056CONFIG_VIDEO_V4L1_COMPAT=y
1057# CONFIG_DVB_CORE is not set
1058CONFIG_VIDEO_MEDIA=m
1059
1060#
1061# Multimedia drivers
1062#
1063CONFIG_MEDIA_ATTACH=y
1064CONFIG_MEDIA_TUNER=m
1065CONFIG_MEDIA_TUNER_CUSTOMIZE=y
1066CONFIG_MEDIA_TUNER_SIMPLE=m
1067CONFIG_MEDIA_TUNER_TDA8290=m
1068CONFIG_MEDIA_TUNER_TDA827X=m
1069CONFIG_MEDIA_TUNER_TDA18271=m
1070CONFIG_MEDIA_TUNER_TDA9887=m
1071CONFIG_MEDIA_TUNER_TEA5761=m
1072CONFIG_MEDIA_TUNER_TEA5767=m
1073CONFIG_MEDIA_TUNER_MT20XX=m
1074CONFIG_MEDIA_TUNER_MT2060=m
1075CONFIG_MEDIA_TUNER_MT2266=m
1076CONFIG_MEDIA_TUNER_MT2131=m
1077CONFIG_MEDIA_TUNER_QT1010=m
1078CONFIG_MEDIA_TUNER_XC2028=m
1079CONFIG_MEDIA_TUNER_XC5000=m
1080CONFIG_MEDIA_TUNER_MXL5005S=m
1081CONFIG_MEDIA_TUNER_MXL5007T=m
1082CONFIG_VIDEO_V4L2=m
1083CONFIG_VIDEO_V4L1=m
1084CONFIG_VIDEOBUF_GEN=m
1085CONFIG_VIDEOBUF_VMALLOC=m
1086CONFIG_VIDEOBUF_DMA_CONTIG=m
1087CONFIG_VIDEO_CAPTURE_DRIVERS=y
1088# CONFIG_VIDEO_ADV_DEBUG is not set
1089# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
1090CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1091# CONFIG_VIDEO_VIVI is not set
1092# CONFIG_VIDEO_BT848 is not set
1093# CONFIG_VIDEO_PMS is not set
1094# CONFIG_VIDEO_CPIA is not set
1095# CONFIG_VIDEO_CPIA2 is not set
1096# CONFIG_VIDEO_SAA5246A is not set
1097# CONFIG_VIDEO_SAA5249 is not set
1098# CONFIG_VIDEO_STRADIS is not set
1099# CONFIG_VIDEO_SAA7134 is not set
1100# CONFIG_VIDEO_MXB is not set
1101# CONFIG_VIDEO_HEXIUM_ORION is not set
1102# CONFIG_VIDEO_HEXIUM_GEMINI is not set
1103# CONFIG_VIDEO_CX88 is not set
1104# CONFIG_VIDEO_IVTV is not set
1105# CONFIG_VIDEO_CAFE_CCIC is not set
1106CONFIG_SOC_CAMERA=m
1107CONFIG_SOC_CAMERA_MT9M001=m
1108CONFIG_SOC_CAMERA_MT9M111=m
1109CONFIG_SOC_CAMERA_MT9V022=m
1110CONFIG_SOC_CAMERA_PLATFORM=m
1111CONFIG_VIDEO_SH_MOBILE_CEU=m
1112CONFIG_V4L_USB_DRIVERS=y
1113CONFIG_USB_VIDEO_CLASS=m
1114CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
1115CONFIG_USB_GSPCA=m
1116CONFIG_USB_M5602=m
1117CONFIG_USB_GSPCA_CONEX=m
1118CONFIG_USB_GSPCA_ETOMS=m
1119CONFIG_USB_GSPCA_FINEPIX=m
1120CONFIG_USB_GSPCA_MARS=m
1121CONFIG_USB_GSPCA_OV519=m
1122CONFIG_USB_GSPCA_PAC207=m
1123CONFIG_USB_GSPCA_PAC7311=m
1124CONFIG_USB_GSPCA_SONIXB=m
1125CONFIG_USB_GSPCA_SONIXJ=m
1126CONFIG_USB_GSPCA_SPCA500=m
1127CONFIG_USB_GSPCA_SPCA501=m
1128CONFIG_USB_GSPCA_SPCA505=m
1129CONFIG_USB_GSPCA_SPCA506=m
1130CONFIG_USB_GSPCA_SPCA508=m
1131CONFIG_USB_GSPCA_SPCA561=m
1132CONFIG_USB_GSPCA_STK014=m
1133CONFIG_USB_GSPCA_SUNPLUS=m
1134CONFIG_USB_GSPCA_T613=m
1135CONFIG_USB_GSPCA_TV8532=m
1136CONFIG_USB_GSPCA_VC032X=m
1137CONFIG_USB_GSPCA_ZC3XX=m
1138# CONFIG_VIDEO_PVRUSB2 is not set
1139# CONFIG_VIDEO_EM28XX is not set
1140# CONFIG_VIDEO_USBVISION is not set
1141CONFIG_VIDEO_USBVIDEO=m
1142CONFIG_USB_VICAM=m
1143CONFIG_USB_IBMCAM=m
1144CONFIG_USB_KONICAWC=m
1145CONFIG_USB_QUICKCAM_MESSENGER=m
1146CONFIG_USB_ET61X251=m
1147# CONFIG_VIDEO_OVCAMCHIP is not set
1148CONFIG_USB_OV511=m
1149CONFIG_USB_SE401=m
1150CONFIG_USB_SN9C102=m
1151CONFIG_USB_STV680=m
1152CONFIG_USB_ZC0301=m
1153CONFIG_USB_PWC=m
1154# CONFIG_USB_PWC_DEBUG is not set
1155# CONFIG_USB_ZR364XX is not set
1156CONFIG_USB_STKWEBCAM=m
1157CONFIG_USB_S2255=m
1158CONFIG_RADIO_ADAPTERS=y
1159# CONFIG_RADIO_CADET is not set
1160# CONFIG_RADIO_RTRACK is not set
1161# CONFIG_RADIO_RTRACK2 is not set
1162# CONFIG_RADIO_AZTECH is not set
1163# CONFIG_RADIO_GEMTEK is not set
1164# CONFIG_RADIO_GEMTEK_PCI is not set
1165# CONFIG_RADIO_MAXIRADIO is not set
1166# CONFIG_RADIO_MAESTRO is not set
1167# CONFIG_RADIO_SF16FMI is not set
1168# CONFIG_RADIO_SF16FMR2 is not set
1169# CONFIG_RADIO_TERRATEC is not set
1170# CONFIG_RADIO_TRUST is not set
1171# CONFIG_RADIO_TYPHOON is not set
1172# CONFIG_RADIO_ZOLTRIX is not set
1173# CONFIG_USB_DSBR is not set
1174CONFIG_USB_SI470X=m
1175CONFIG_USB_MR800=m
1176CONFIG_DAB=y
1177# CONFIG_USB_DABUSB is not set
1178 1113
1179# 1114#
1180# Graphics support 1115# Graphics support
@@ -1235,12 +1170,13 @@ CONFIG_FB_RADEON_BACKLIGHT=y
1235# CONFIG_FB_VIRTUAL is not set 1170# CONFIG_FB_VIRTUAL is not set
1236# CONFIG_FB_METRONOME is not set 1171# CONFIG_FB_METRONOME is not set
1237# CONFIG_FB_MB862XX is not set 1172# CONFIG_FB_MB862XX is not set
1173# CONFIG_FB_BROADSHEET is not set
1238CONFIG_BACKLIGHT_LCD_SUPPORT=y 1174CONFIG_BACKLIGHT_LCD_SUPPORT=y
1239CONFIG_LCD_CLASS_DEVICE=m 1175CONFIG_LCD_CLASS_DEVICE=m
1240# CONFIG_LCD_ILI9320 is not set 1176# CONFIG_LCD_ILI9320 is not set
1241# CONFIG_LCD_PLATFORM is not set 1177# CONFIG_LCD_PLATFORM is not set
1242CONFIG_BACKLIGHT_CLASS_DEVICE=y 1178CONFIG_BACKLIGHT_CLASS_DEVICE=y
1243# CONFIG_BACKLIGHT_CORGI is not set 1179CONFIG_BACKLIGHT_GENERIC=y
1244 1180
1245# 1181#
1246# Display device support 1182# Display device support
@@ -1273,12 +1209,19 @@ CONFIG_SND_MIXER_OSS=m
1273CONFIG_SND_PCM_OSS=m 1209CONFIG_SND_PCM_OSS=m
1274CONFIG_SND_PCM_OSS_PLUGINS=y 1210CONFIG_SND_PCM_OSS_PLUGINS=y
1275CONFIG_SND_SEQUENCER_OSS=y 1211CONFIG_SND_SEQUENCER_OSS=y
1212# CONFIG_SND_HRTIMER is not set
1213# CONFIG_SND_RTCTIMER is not set
1276# CONFIG_SND_DYNAMIC_MINORS is not set 1214# CONFIG_SND_DYNAMIC_MINORS is not set
1277CONFIG_SND_SUPPORT_OLD_API=y 1215CONFIG_SND_SUPPORT_OLD_API=y
1278CONFIG_SND_VERBOSE_PROCFS=y 1216CONFIG_SND_VERBOSE_PROCFS=y
1279# CONFIG_SND_VERBOSE_PRINTK is not set 1217# CONFIG_SND_VERBOSE_PRINTK is not set
1280# CONFIG_SND_DEBUG is not set 1218# CONFIG_SND_DEBUG is not set
1281CONFIG_SND_VMASTER=y 1219CONFIG_SND_VMASTER=y
1220CONFIG_SND_RAWMIDI_SEQ=m
1221# CONFIG_SND_OPL3_LIB_SEQ is not set
1222# CONFIG_SND_OPL4_LIB_SEQ is not set
1223# CONFIG_SND_SBAWE_SEQ is not set
1224# CONFIG_SND_EMU10K1_SEQ is not set
1282CONFIG_SND_MPU401_UART=m 1225CONFIG_SND_MPU401_UART=m
1283CONFIG_SND_AC97_CODEC=m 1226CONFIG_SND_AC97_CODEC=m
1284CONFIG_SND_DRIVERS=y 1227CONFIG_SND_DRIVERS=y
@@ -1305,6 +1248,7 @@ CONFIG_SND_PCI=y
1305# CONFIG_SND_OXYGEN is not set 1248# CONFIG_SND_OXYGEN is not set
1306# CONFIG_SND_CS4281 is not set 1249# CONFIG_SND_CS4281 is not set
1307# CONFIG_SND_CS46XX is not set 1250# CONFIG_SND_CS46XX is not set
1251# CONFIG_SND_CTXFI is not set
1308# CONFIG_SND_DARLA20 is not set 1252# CONFIG_SND_DARLA20 is not set
1309# CONFIG_SND_GINA20 is not set 1253# CONFIG_SND_GINA20 is not set
1310# CONFIG_SND_LAYLA20 is not set 1254# CONFIG_SND_LAYLA20 is not set
@@ -1317,6 +1261,8 @@ CONFIG_SND_PCI=y
1317# CONFIG_SND_INDIGO is not set 1261# CONFIG_SND_INDIGO is not set
1318# CONFIG_SND_INDIGOIO is not set 1262# CONFIG_SND_INDIGOIO is not set
1319# CONFIG_SND_INDIGODJ is not set 1263# CONFIG_SND_INDIGODJ is not set
1264# CONFIG_SND_INDIGOIOX is not set
1265# CONFIG_SND_INDIGODJX is not set
1320# CONFIG_SND_EMU10K1 is not set 1266# CONFIG_SND_EMU10K1 is not set
1321# CONFIG_SND_EMU10K1X is not set 1267# CONFIG_SND_EMU10K1X is not set
1322# CONFIG_SND_ENS1370 is not set 1268# CONFIG_SND_ENS1370 is not set
@@ -1333,6 +1279,7 @@ CONFIG_SND_PCI=y
1333# CONFIG_SND_INTEL8X0 is not set 1279# CONFIG_SND_INTEL8X0 is not set
1334# CONFIG_SND_INTEL8X0M is not set 1280# CONFIG_SND_INTEL8X0M is not set
1335# CONFIG_SND_KORG1212 is not set 1281# CONFIG_SND_KORG1212 is not set
1282# CONFIG_SND_LX6464ES is not set
1336# CONFIG_SND_MAESTRO3 is not set 1283# CONFIG_SND_MAESTRO3 is not set
1337# CONFIG_SND_MIXART is not set 1284# CONFIG_SND_MIXART is not set
1338# CONFIG_SND_NM256 is not set 1285# CONFIG_SND_NM256 is not set
@@ -1363,43 +1310,18 @@ CONFIG_HIDRAW=y
1363# 1310#
1364# USB Input Devices 1311# USB Input Devices
1365# 1312#
1366CONFIG_USB_HID=m 1313# CONFIG_USB_HID is not set
1367CONFIG_HID_PID=y 1314CONFIG_HID_PID=y
1368CONFIG_USB_HIDDEV=y
1369 1315
1370# 1316#
1371# USB HID Boot Protocol drivers 1317# USB HID Boot Protocol drivers
1372# 1318#
1373# CONFIG_USB_KBD is not set 1319CONFIG_USB_KBD=y
1374# CONFIG_USB_MOUSE is not set 1320CONFIG_USB_MOUSE=y
1375 1321
1376# 1322#
1377# Special HID drivers 1323# Special HID drivers
1378# 1324#
1379CONFIG_HID_COMPAT=y
1380CONFIG_HID_A4TECH=m
1381CONFIG_HID_APPLE=m
1382CONFIG_HID_BELKIN=m
1383CONFIG_HID_BRIGHT=m
1384CONFIG_HID_CHERRY=m
1385CONFIG_HID_CHICONY=m
1386CONFIG_HID_CYPRESS=m
1387CONFIG_HID_DELL=m
1388CONFIG_HID_EZKEY=m
1389CONFIG_HID_GYRATION=m
1390CONFIG_HID_LOGITECH=m
1391CONFIG_LOGITECH_FF=y
1392CONFIG_LOGIRUMBLEPAD2_FF=y
1393CONFIG_HID_MICROSOFT=m
1394CONFIG_HID_MONTEREY=m
1395CONFIG_HID_PANTHERLORD=m
1396# CONFIG_PANTHERLORD_FF is not set
1397CONFIG_HID_PETALYNX=m
1398CONFIG_HID_SAMSUNG=m
1399CONFIG_HID_SONY=m
1400CONFIG_HID_SUNPLUS=m
1401# CONFIG_THRUSTMASTER_FF is not set
1402CONFIG_ZEROPLUS_FF=m
1403CONFIG_USB_SUPPORT=y 1325CONFIG_USB_SUPPORT=y
1404CONFIG_USB_ARCH_HAS_HCD=y 1326CONFIG_USB_ARCH_HAS_HCD=y
1405CONFIG_USB_ARCH_HAS_OHCI=y 1327CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1427,9 +1349,11 @@ CONFIG_USB_WUSB_CBAF=m
1427# USB Host Controller Drivers 1349# USB Host Controller Drivers
1428# 1350#
1429CONFIG_USB_C67X00_HCD=m 1351CONFIG_USB_C67X00_HCD=m
1352# CONFIG_USB_XHCI_HCD is not set
1430CONFIG_USB_EHCI_HCD=y 1353CONFIG_USB_EHCI_HCD=y
1431CONFIG_USB_EHCI_ROOT_HUB_TT=y 1354CONFIG_USB_EHCI_ROOT_HUB_TT=y
1432CONFIG_USB_EHCI_TT_NEWSCHED=y 1355CONFIG_USB_EHCI_TT_NEWSCHED=y
1356# CONFIG_USB_OXU210HP_HCD is not set
1433# CONFIG_USB_ISP116X_HCD is not set 1357# CONFIG_USB_ISP116X_HCD is not set
1434CONFIG_USB_ISP1760_HCD=m 1358CONFIG_USB_ISP1760_HCD=m
1435CONFIG_USB_OHCI_HCD=y 1359CONFIG_USB_OHCI_HCD=y
@@ -1451,18 +1375,17 @@ CONFIG_USB_WDM=m
1451CONFIG_USB_TMC=m 1375CONFIG_USB_TMC=m
1452 1376
1453# 1377#
1454# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; 1378# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1455# 1379#
1456 1380
1457# 1381#
1458# see USB_STORAGE Help for more information 1382# also be needed; see USB_STORAGE Help for more info
1459# 1383#
1460CONFIG_USB_STORAGE=y 1384CONFIG_USB_STORAGE=y
1461# CONFIG_USB_STORAGE_DEBUG is not set 1385# CONFIG_USB_STORAGE_DEBUG is not set
1462# CONFIG_USB_STORAGE_DATAFAB is not set 1386# CONFIG_USB_STORAGE_DATAFAB is not set
1463# CONFIG_USB_STORAGE_FREECOM is not set 1387# CONFIG_USB_STORAGE_FREECOM is not set
1464# CONFIG_USB_STORAGE_ISD200 is not set 1388# CONFIG_USB_STORAGE_ISD200 is not set
1465# CONFIG_USB_STORAGE_DPCM is not set
1466# CONFIG_USB_STORAGE_USBAT is not set 1389# CONFIG_USB_STORAGE_USBAT is not set
1467# CONFIG_USB_STORAGE_SDDR09 is not set 1390# CONFIG_USB_STORAGE_SDDR09 is not set
1468# CONFIG_USB_STORAGE_SDDR55 is not set 1391# CONFIG_USB_STORAGE_SDDR55 is not set
@@ -1498,7 +1421,6 @@ CONFIG_USB_SEVSEG=m
1498# CONFIG_USB_LED is not set 1421# CONFIG_USB_LED is not set
1499# CONFIG_USB_CYPRESS_CY7C63 is not set 1422# CONFIG_USB_CYPRESS_CY7C63 is not set
1500# CONFIG_USB_CYTHERM is not set 1423# CONFIG_USB_CYTHERM is not set
1501# CONFIG_USB_PHIDGET is not set
1502# CONFIG_USB_IDMOUSE is not set 1424# CONFIG_USB_IDMOUSE is not set
1503# CONFIG_USB_FTDI_ELAN is not set 1425# CONFIG_USB_FTDI_ELAN is not set
1504# CONFIG_USB_APPLEDISPLAY is not set 1426# CONFIG_USB_APPLEDISPLAY is not set
@@ -1510,72 +1432,32 @@ CONFIG_USB_SEVSEG=m
1510CONFIG_USB_ISIGHTFW=m 1432CONFIG_USB_ISIGHTFW=m
1511CONFIG_USB_VST=m 1433CONFIG_USB_VST=m
1512# CONFIG_USB_GADGET is not set 1434# CONFIG_USB_GADGET is not set
1435
1436#
1437# OTG and related infrastructure
1438#
1439# CONFIG_NOP_USB_XCEIV is not set
1513# CONFIG_UWB is not set 1440# CONFIG_UWB is not set
1514# CONFIG_MMC is not set 1441# CONFIG_MMC is not set
1515# CONFIG_MEMSTICK is not set 1442# CONFIG_MEMSTICK is not set
1516# CONFIG_NEW_LEDS is not set 1443# CONFIG_NEW_LEDS is not set
1517# CONFIG_ACCESSIBILITY is not set 1444# CONFIG_ACCESSIBILITY is not set
1518# CONFIG_INFINIBAND is not set 1445# CONFIG_INFINIBAND is not set
1519CONFIG_RTC_LIB=y 1446# CONFIG_RTC_CLASS is not set
1520CONFIG_RTC_CLASS=m
1521
1522#
1523# RTC interfaces
1524#
1525CONFIG_RTC_INTF_SYSFS=y
1526CONFIG_RTC_INTF_PROC=y
1527CONFIG_RTC_INTF_DEV=y
1528CONFIG_RTC_INTF_DEV_UIE_EMUL=y
1529# CONFIG_RTC_DRV_TEST is not set
1530
1531#
1532# I2C RTC drivers
1533#
1534# CONFIG_RTC_DRV_DS1307 is not set
1535# CONFIG_RTC_DRV_DS1374 is not set
1536# CONFIG_RTC_DRV_DS1672 is not set
1537# CONFIG_RTC_DRV_MAX6900 is not set
1538# CONFIG_RTC_DRV_RS5C372 is not set
1539# CONFIG_RTC_DRV_ISL1208 is not set
1540# CONFIG_RTC_DRV_X1205 is not set
1541# CONFIG_RTC_DRV_PCF8563 is not set
1542# CONFIG_RTC_DRV_PCF8583 is not set
1543# CONFIG_RTC_DRV_M41T80 is not set
1544# CONFIG_RTC_DRV_S35390A is not set
1545# CONFIG_RTC_DRV_FM3130 is not set
1546# CONFIG_RTC_DRV_RX8581 is not set
1547
1548#
1549# SPI RTC drivers
1550#
1551
1552#
1553# Platform RTC drivers
1554#
1555CONFIG_RTC_DRV_CMOS=m
1556# CONFIG_RTC_DRV_DS1286 is not set
1557# CONFIG_RTC_DRV_DS1511 is not set
1558# CONFIG_RTC_DRV_DS1553 is not set
1559# CONFIG_RTC_DRV_DS1742 is not set
1560# CONFIG_RTC_DRV_STK17TA8 is not set
1561# CONFIG_RTC_DRV_M48T86 is not set
1562# CONFIG_RTC_DRV_M48T35 is not set
1563# CONFIG_RTC_DRV_M48T59 is not set
1564# CONFIG_RTC_DRV_BQ4802 is not set
1565# CONFIG_RTC_DRV_V3020 is not set
1566
1567#
1568# on-CPU RTC drivers
1569#
1570# CONFIG_DMADEVICES is not set 1447# CONFIG_DMADEVICES is not set
1448# CONFIG_AUXDISPLAY is not set
1571CONFIG_UIO=m 1449CONFIG_UIO=m
1572CONFIG_UIO_CIF=m 1450CONFIG_UIO_CIF=m
1573# CONFIG_UIO_PDRV is not set 1451# CONFIG_UIO_PDRV is not set
1574# CONFIG_UIO_PDRV_GENIRQ is not set 1452# CONFIG_UIO_PDRV_GENIRQ is not set
1575# CONFIG_UIO_SMX is not set 1453# CONFIG_UIO_SMX is not set
1454# CONFIG_UIO_AEC is not set
1576# CONFIG_UIO_SERCOS3 is not set 1455# CONFIG_UIO_SERCOS3 is not set
1456
1457#
1458# TI VLYNQ
1459#
1577# CONFIG_STAGING is not set 1460# CONFIG_STAGING is not set
1578CONFIG_STAGING_EXCLUDE_BUILD=y
1579 1461
1580# 1462#
1581# File systems 1463# File systems
@@ -1584,6 +1466,7 @@ CONFIG_EXT2_FS=y
1584# CONFIG_EXT2_FS_XATTR is not set 1466# CONFIG_EXT2_FS_XATTR is not set
1585CONFIG_EXT2_FS_XIP=y 1467CONFIG_EXT2_FS_XIP=y
1586CONFIG_EXT3_FS=y 1468CONFIG_EXT3_FS=y
1469# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1587# CONFIG_EXT3_FS_XATTR is not set 1470# CONFIG_EXT3_FS_XATTR is not set
1588CONFIG_EXT4_FS=m 1471CONFIG_EXT4_FS=m
1589CONFIG_EXT4DEV_COMPAT=y 1472CONFIG_EXT4DEV_COMPAT=y
@@ -1592,7 +1475,9 @@ CONFIG_EXT4_FS_POSIX_ACL=y
1592CONFIG_EXT4_FS_SECURITY=y 1475CONFIG_EXT4_FS_SECURITY=y
1593CONFIG_FS_XIP=y 1476CONFIG_FS_XIP=y
1594CONFIG_JBD=y 1477CONFIG_JBD=y
1478# CONFIG_JBD_DEBUG is not set
1595CONFIG_JBD2=m 1479CONFIG_JBD2=m
1480# CONFIG_JBD2_DEBUG is not set
1596CONFIG_FS_MBCACHE=m 1481CONFIG_FS_MBCACHE=m
1597CONFIG_REISERFS_FS=m 1482CONFIG_REISERFS_FS=m
1598# CONFIG_REISERFS_CHECK is not set 1483# CONFIG_REISERFS_CHECK is not set
@@ -1600,10 +1485,12 @@ CONFIG_REISERFS_FS=m
1600# CONFIG_REISERFS_FS_XATTR is not set 1485# CONFIG_REISERFS_FS_XATTR is not set
1601# CONFIG_JFS_FS is not set 1486# CONFIG_JFS_FS is not set
1602CONFIG_FS_POSIX_ACL=y 1487CONFIG_FS_POSIX_ACL=y
1603CONFIG_FILE_LOCKING=y
1604# CONFIG_XFS_FS is not set 1488# CONFIG_XFS_FS is not set
1605# CONFIG_GFS2_FS is not set 1489# CONFIG_GFS2_FS is not set
1606# CONFIG_OCFS2_FS is not set 1490# CONFIG_OCFS2_FS is not set
1491# CONFIG_BTRFS_FS is not set
1492CONFIG_FILE_LOCKING=y
1493CONFIG_FSNOTIFY=y
1607CONFIG_DNOTIFY=y 1494CONFIG_DNOTIFY=y
1608CONFIG_INOTIFY=y 1495CONFIG_INOTIFY=y
1609CONFIG_INOTIFY_USER=y 1496CONFIG_INOTIFY_USER=y
@@ -1611,6 +1498,12 @@ CONFIG_INOTIFY_USER=y
1611CONFIG_AUTOFS_FS=y 1498CONFIG_AUTOFS_FS=y
1612CONFIG_AUTOFS4_FS=y 1499CONFIG_AUTOFS4_FS=y
1613CONFIG_FUSE_FS=y 1500CONFIG_FUSE_FS=y
1501# CONFIG_CUSE is not set
1502
1503#
1504# Caches
1505#
1506# CONFIG_FSCACHE is not set
1614 1507
1615# 1508#
1616# CD-ROM/DVD Filesystems 1509# CD-ROM/DVD Filesystems
@@ -1645,10 +1538,7 @@ CONFIG_TMPFS=y
1645# CONFIG_TMPFS_POSIX_ACL is not set 1538# CONFIG_TMPFS_POSIX_ACL is not set
1646# CONFIG_HUGETLB_PAGE is not set 1539# CONFIG_HUGETLB_PAGE is not set
1647# CONFIG_CONFIGFS_FS is not set 1540# CONFIG_CONFIGFS_FS is not set
1648 1541CONFIG_MISC_FILESYSTEMS=y
1649#
1650# Miscellaneous filesystems
1651#
1652# CONFIG_ADFS_FS is not set 1542# CONFIG_ADFS_FS is not set
1653# CONFIG_AFFS_FS is not set 1543# CONFIG_AFFS_FS is not set
1654# CONFIG_HFS_FS is not set 1544# CONFIG_HFS_FS is not set
@@ -1658,6 +1548,7 @@ CONFIG_TMPFS=y
1658# CONFIG_EFS_FS is not set 1548# CONFIG_EFS_FS is not set
1659# CONFIG_JFFS2_FS is not set 1549# CONFIG_JFFS2_FS is not set
1660# CONFIG_CRAMFS is not set 1550# CONFIG_CRAMFS is not set
1551# CONFIG_SQUASHFS is not set
1661# CONFIG_VXFS_FS is not set 1552# CONFIG_VXFS_FS is not set
1662# CONFIG_MINIX_FS is not set 1553# CONFIG_MINIX_FS is not set
1663CONFIG_OMFS_FS=m 1554CONFIG_OMFS_FS=m
@@ -1666,11 +1557,13 @@ CONFIG_OMFS_FS=m
1666# CONFIG_ROMFS_FS is not set 1557# CONFIG_ROMFS_FS is not set
1667# CONFIG_SYSV_FS is not set 1558# CONFIG_SYSV_FS is not set
1668# CONFIG_UFS_FS is not set 1559# CONFIG_UFS_FS is not set
1560# CONFIG_NILFS2_FS is not set
1669CONFIG_NETWORK_FILESYSTEMS=y 1561CONFIG_NETWORK_FILESYSTEMS=y
1670CONFIG_NFS_FS=m 1562CONFIG_NFS_FS=m
1671CONFIG_NFS_V3=y 1563CONFIG_NFS_V3=y
1672CONFIG_NFS_V3_ACL=y 1564CONFIG_NFS_V3_ACL=y
1673CONFIG_NFS_V4=y 1565CONFIG_NFS_V4=y
1566# CONFIG_NFS_V4_1 is not set
1674CONFIG_NFSD=m 1567CONFIG_NFSD=m
1675CONFIG_NFSD_V2_ACL=y 1568CONFIG_NFSD_V2_ACL=y
1676CONFIG_NFSD_V3=y 1569CONFIG_NFSD_V3=y
@@ -1683,7 +1576,6 @@ CONFIG_NFS_ACL_SUPPORT=m
1683CONFIG_NFS_COMMON=y 1576CONFIG_NFS_COMMON=y
1684CONFIG_SUNRPC=m 1577CONFIG_SUNRPC=m
1685CONFIG_SUNRPC_GSS=m 1578CONFIG_SUNRPC_GSS=m
1686# CONFIG_SUNRPC_REGISTER_V4 is not set
1687CONFIG_RPCSEC_GSS_KRB5=m 1579CONFIG_RPCSEC_GSS_KRB5=m
1688# CONFIG_RPCSEC_GSS_SPKM3 is not set 1580# CONFIG_RPCSEC_GSS_SPKM3 is not set
1689CONFIG_SMB_FS=m 1581CONFIG_SMB_FS=m
@@ -1775,17 +1667,21 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
1775CONFIG_FRAME_WARN=2048 1667CONFIG_FRAME_WARN=2048
1776# CONFIG_MAGIC_SYSRQ is not set 1668# CONFIG_MAGIC_SYSRQ is not set
1777# CONFIG_UNUSED_SYMBOLS is not set 1669# CONFIG_UNUSED_SYMBOLS is not set
1778# CONFIG_DEBUG_FS is not set 1670CONFIG_DEBUG_FS=y
1779# CONFIG_HEADERS_CHECK is not set 1671# CONFIG_HEADERS_CHECK is not set
1780# CONFIG_DEBUG_KERNEL is not set 1672# CONFIG_DEBUG_KERNEL is not set
1673CONFIG_STACKTRACE=y
1781# CONFIG_DEBUG_MEMORY_INIT is not set 1674# CONFIG_DEBUG_MEMORY_INIT is not set
1782# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1675# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1783CONFIG_SYSCTL_SYSCALL_CHECK=y 1676CONFIG_SYSCTL_SYSCALL_CHECK=y
1784 1677CONFIG_NOP_TRACER=y
1785# 1678CONFIG_RING_BUFFER=y
1786# Tracers 1679CONFIG_EVENT_TRACING=y
1787# 1680CONFIG_CONTEXT_SWITCH_TRACER=y
1788CONFIG_DYNAMIC_PRINTK_DEBUG=y 1681CONFIG_TRACING=y
1682CONFIG_TRACING_SUPPORT=y
1683# CONFIG_FTRACE is not set
1684# CONFIG_DYNAMIC_DEBUG is not set
1789# CONFIG_SAMPLES is not set 1685# CONFIG_SAMPLES is not set
1790CONFIG_HAVE_ARCH_KGDB=y 1686CONFIG_HAVE_ARCH_KGDB=y
1791CONFIG_CMDLINE="" 1687CONFIG_CMDLINE=""
@@ -1804,13 +1700,21 @@ CONFIG_CRYPTO=y
1804# 1700#
1805CONFIG_CRYPTO_FIPS=y 1701CONFIG_CRYPTO_FIPS=y
1806CONFIG_CRYPTO_ALGAPI=y 1702CONFIG_CRYPTO_ALGAPI=y
1807CONFIG_CRYPTO_AEAD=y 1703CONFIG_CRYPTO_ALGAPI2=y
1808CONFIG_CRYPTO_BLKCIPHER=y 1704CONFIG_CRYPTO_AEAD=m
1705CONFIG_CRYPTO_AEAD2=y
1706CONFIG_CRYPTO_BLKCIPHER=m
1707CONFIG_CRYPTO_BLKCIPHER2=y
1809CONFIG_CRYPTO_HASH=y 1708CONFIG_CRYPTO_HASH=y
1810CONFIG_CRYPTO_RNG=y 1709CONFIG_CRYPTO_HASH2=y
1710CONFIG_CRYPTO_RNG=m
1711CONFIG_CRYPTO_RNG2=y
1712CONFIG_CRYPTO_PCOMP=y
1811CONFIG_CRYPTO_MANAGER=y 1713CONFIG_CRYPTO_MANAGER=y
1714CONFIG_CRYPTO_MANAGER2=y
1812CONFIG_CRYPTO_GF128MUL=m 1715CONFIG_CRYPTO_GF128MUL=m
1813# CONFIG_CRYPTO_NULL is not set 1716# CONFIG_CRYPTO_NULL is not set
1717CONFIG_CRYPTO_WORKQUEUE=y
1814# CONFIG_CRYPTO_CRYPTD is not set 1718# CONFIG_CRYPTO_CRYPTD is not set
1815CONFIG_CRYPTO_AUTHENC=m 1719CONFIG_CRYPTO_AUTHENC=m
1816# CONFIG_CRYPTO_TEST is not set 1720# CONFIG_CRYPTO_TEST is not set
@@ -1879,6 +1783,7 @@ CONFIG_CRYPTO_SEED=m
1879# Compression 1783# Compression
1880# 1784#
1881CONFIG_CRYPTO_DEFLATE=m 1785CONFIG_CRYPTO_DEFLATE=m
1786# CONFIG_CRYPTO_ZLIB is not set
1882CONFIG_CRYPTO_LZO=m 1787CONFIG_CRYPTO_LZO=m
1883 1788
1884# 1789#
@@ -1886,11 +1791,13 @@ CONFIG_CRYPTO_LZO=m
1886# 1791#
1887CONFIG_CRYPTO_ANSI_CPRNG=m 1792CONFIG_CRYPTO_ANSI_CPRNG=m
1888# CONFIG_CRYPTO_HW is not set 1793# CONFIG_CRYPTO_HW is not set
1794CONFIG_BINARY_PRINTF=y
1889 1795
1890# 1796#
1891# Library routines 1797# Library routines
1892# 1798#
1893CONFIG_BITREVERSE=y 1799CONFIG_BITREVERSE=y
1800CONFIG_GENERIC_FIND_LAST_BIT=y
1894CONFIG_CRC_CCITT=y 1801CONFIG_CRC_CCITT=y
1895CONFIG_CRC16=m 1802CONFIG_CRC16=m
1896# CONFIG_CRC_T10DIF is not set 1803# CONFIG_CRC_T10DIF is not set
@@ -1906,7 +1813,7 @@ CONFIG_TEXTSEARCH=y
1906CONFIG_TEXTSEARCH_KMP=m 1813CONFIG_TEXTSEARCH_KMP=m
1907CONFIG_TEXTSEARCH_BM=m 1814CONFIG_TEXTSEARCH_BM=m
1908CONFIG_TEXTSEARCH_FSM=m 1815CONFIG_TEXTSEARCH_FSM=m
1909CONFIG_PLIST=y
1910CONFIG_HAS_IOMEM=y 1816CONFIG_HAS_IOMEM=y
1911CONFIG_HAS_IOPORT=y 1817CONFIG_HAS_IOPORT=y
1912CONFIG_HAS_DMA=y 1818CONFIG_HAS_DMA=y
1819CONFIG_NLATTR=y
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 115822876417..f14d38ba6034 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -130,7 +130,6 @@ CONFIG_IP22_CPU_SCACHE=y
130CONFIG_MIPS_MT_DISABLED=y 130CONFIG_MIPS_MT_DISABLED=y
131# CONFIG_MIPS_MT_SMP is not set 131# CONFIG_MIPS_MT_SMP is not set
132# CONFIG_MIPS_MT_SMTC is not set 132# CONFIG_MIPS_MT_SMTC is not set
133CONFIG_CPU_HAS_LLSC=y
134CONFIG_CPU_HAS_SYNC=y 133CONFIG_CPU_HAS_SYNC=y
135CONFIG_GENERIC_HARDIRQS=y 134CONFIG_GENERIC_HARDIRQS=y
136CONFIG_GENERIC_IRQ_PROBE=y 135CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 0208723adf28..1fc73aa7b509 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -105,7 +105,6 @@ CONFIG_CPU_HAS_PREFETCH=y
105CONFIG_MIPS_MT_DISABLED=y 105CONFIG_MIPS_MT_DISABLED=y
106# CONFIG_MIPS_MT_SMP is not set 106# CONFIG_MIPS_MT_SMP is not set
107# CONFIG_MIPS_MT_SMTC is not set 107# CONFIG_MIPS_MT_SMTC is not set
108CONFIG_CPU_HAS_LLSC=y
109CONFIG_CPU_HAS_SYNC=y 108CONFIG_CPU_HAS_SYNC=y
110CONFIG_GENERIC_HARDIRQS=y 109CONFIG_GENERIC_HARDIRQS=y
111CONFIG_GENERIC_IRQ_PROBE=y 110CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 70a744e9a8c5..539dccb0345d 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -123,7 +123,6 @@ CONFIG_CPU_HAS_PREFETCH=y
123CONFIG_MIPS_MT_DISABLED=y 123CONFIG_MIPS_MT_DISABLED=y
124# CONFIG_MIPS_MT_SMP is not set 124# CONFIG_MIPS_MT_SMP is not set
125# CONFIG_MIPS_MT_SMTC is not set 125# CONFIG_MIPS_MT_SMTC is not set
126CONFIG_CPU_HAS_LLSC=y
127CONFIG_CPU_HAS_SYNC=y 126CONFIG_CPU_HAS_SYNC=y
128CONFIG_GENERIC_HARDIRQS=y 127CONFIG_GENERIC_HARDIRQS=y
129CONFIG_GENERIC_IRQ_PROBE=y 128CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index de4c7a0a96dd..d934bdefb393 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -118,7 +118,6 @@ CONFIG_RM7000_CPU_SCACHE=y
118CONFIG_MIPS_MT_DISABLED=y 118CONFIG_MIPS_MT_DISABLED=y
119# CONFIG_MIPS_MT_SMP is not set 119# CONFIG_MIPS_MT_SMP is not set
120# CONFIG_MIPS_MT_SMTC is not set 120# CONFIG_MIPS_MT_SMTC is not set
121CONFIG_CPU_HAS_LLSC=y
122CONFIG_CPU_HAS_SYNC=y 121CONFIG_CPU_HAS_SYNC=y
123CONFIG_GENERIC_HARDIRQS=y 122CONFIG_GENERIC_HARDIRQS=y
124CONFIG_GENERIC_IRQ_PROBE=y 123CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index bbacc35d804f..d22df61833a8 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -119,7 +119,6 @@ CONFIG_MIPS_MT_DISABLED=y
119# CONFIG_MIPS_MT_SMTC is not set 119# CONFIG_MIPS_MT_SMTC is not set
120# CONFIG_MIPS_VPE_LOADER is not set 120# CONFIG_MIPS_VPE_LOADER is not set
121# CONFIG_64BIT_PHYS_ADDR is not set 121# CONFIG_64BIT_PHYS_ADDR is not set
122CONFIG_CPU_HAS_LLSC=y
123CONFIG_CPU_HAS_SYNC=y 122CONFIG_CPU_HAS_SYNC=y
124CONFIG_GENERIC_HARDIRQS=y 123CONFIG_GENERIC_HARDIRQS=y
125CONFIG_GENERIC_IRQ_PROBE=y 124CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index bc9159fda728..044074db7e55 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -108,7 +108,6 @@ CONFIG_R5000_CPU_SCACHE=y
108CONFIG_MIPS_MT_DISABLED=y 108CONFIG_MIPS_MT_DISABLED=y
109# CONFIG_MIPS_MT_SMP is not set 109# CONFIG_MIPS_MT_SMP is not set
110# CONFIG_MIPS_MT_SMTC is not set 110# CONFIG_MIPS_MT_SMTC is not set
111CONFIG_CPU_HAS_LLSC=y
112CONFIG_CPU_HAS_SYNC=y 111CONFIG_CPU_HAS_SYNC=y
113CONFIG_GENERIC_HARDIRQS=y 112CONFIG_GENERIC_HARDIRQS=y
114CONFIG_GENERIC_IRQ_PROBE=y 113CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 1ecdd3b65dc7..3f01870b4d65 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -139,7 +139,6 @@ CONFIG_SYS_SUPPORTS_SCHED_SMT=y
139CONFIG_SYS_SUPPORTS_MULTITHREADING=y 139CONFIG_SYS_SUPPORTS_MULTITHREADING=y
140CONFIG_MIPS_MT_FPAFF=y 140CONFIG_MIPS_MT_FPAFF=y
141# CONFIG_MIPS_VPE_LOADER is not set 141# CONFIG_MIPS_VPE_LOADER is not set
142CONFIG_CPU_HAS_LLSC=y
143# CONFIG_CPU_HAS_SMARTMIPS is not set 142# CONFIG_CPU_HAS_SMARTMIPS is not set
144CONFIG_CPU_MIPSR2_IRQ_VI=y 143CONFIG_CPU_MIPSR2_IRQ_VI=y
145CONFIG_CPU_MIPSR2_IRQ_EI=y 144CONFIG_CPU_MIPSR2_IRQ_EI=y
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index bad8901f8f3c..d001f7e87418 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -112,7 +112,6 @@ CONFIG_MIPS_MT_DISABLED=y
112# CONFIG_MIPS_MT_SMTC is not set 112# CONFIG_MIPS_MT_SMTC is not set
113# CONFIG_MIPS_VPE_LOADER is not set 113# CONFIG_MIPS_VPE_LOADER is not set
114# CONFIG_64BIT_PHYS_ADDR is not set 114# CONFIG_64BIT_PHYS_ADDR is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_HAS_SYNC=y 115CONFIG_CPU_HAS_SYNC=y
117CONFIG_GENERIC_HARDIRQS=y 116CONFIG_GENERIC_HARDIRQS=y
118CONFIG_GENERIC_IRQ_PROBE=y 117CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 2c0a6314e901..7358454deaa6 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
115# CONFIG_MIPS_MT_SMTC is not set 115# CONFIG_MIPS_MT_SMTC is not set
116CONFIG_SYS_SUPPORTS_MULTITHREADING=y 116CONFIG_SYS_SUPPORTS_MULTITHREADING=y
117# CONFIG_MIPS_VPE_LOADER is not set 117# CONFIG_MIPS_VPE_LOADER is not set
118CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_SYNC=y 118CONFIG_CPU_HAS_SYNC=y
120CONFIG_GENERIC_HARDIRQS=y 119CONFIG_GENERIC_HARDIRQS=y
121CONFIG_GENERIC_IRQ_PROBE=y 120CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 84d6491b3d41..ecbc030b7b6c 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -129,7 +129,6 @@ CONFIG_MIPS_MT_DISABLED=y
129# CONFIG_MIPS_VPE_LOADER is not set 129# CONFIG_MIPS_VPE_LOADER is not set
130CONFIG_SYS_SUPPORTS_MULTITHREADING=y 130CONFIG_SYS_SUPPORTS_MULTITHREADING=y
131# CONFIG_64BIT_PHYS_ADDR is not set 131# CONFIG_64BIT_PHYS_ADDR is not set
132CONFIG_CPU_HAS_LLSC=y
133CONFIG_CPU_HAS_SYNC=y 132CONFIG_CPU_HAS_SYNC=y
134CONFIG_GENERIC_HARDIRQS=y 133CONFIG_GENERIC_HARDIRQS=y
135CONFIG_GENERIC_IRQ_PROBE=y 134CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index fadb351d249b..9477f040796d 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -116,7 +116,6 @@ CONFIG_MIPS_MT_DISABLED=y
116# CONFIG_MIPS_MT_SMP is not set 116# CONFIG_MIPS_MT_SMP is not set
117# CONFIG_MIPS_MT_SMTC is not set 117# CONFIG_MIPS_MT_SMTC is not set
118CONFIG_64BIT_PHYS_ADDR=y 118CONFIG_64BIT_PHYS_ADDR=y
119CONFIG_CPU_HAS_LLSC=y
120CONFIG_CPU_HAS_SYNC=y 119CONFIG_CPU_HAS_SYNC=y
121CONFIG_GENERIC_HARDIRQS=y 120CONFIG_GENERIC_HARDIRQS=y
122CONFIG_GENERIC_IRQ_PROBE=y 121CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 9e21e333a2fc..be8091ef0a79 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
115# CONFIG_MIPS_MT_SMTC is not set 115# CONFIG_MIPS_MT_SMTC is not set
116# CONFIG_MIPS_VPE_LOADER is not set 116# CONFIG_MIPS_VPE_LOADER is not set
117CONFIG_64BIT_PHYS_ADDR=y 117CONFIG_64BIT_PHYS_ADDR=y
118CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_SYNC=y 118CONFIG_CPU_HAS_SYNC=y
120CONFIG_GENERIC_HARDIRQS=y 119CONFIG_GENERIC_HARDIRQS=y
121CONFIG_GENERIC_IRQ_PROBE=y 120CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index af67ed4f71ae..e74ba794c789 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMTC is not set 114# CONFIG_MIPS_MT_SMTC is not set
115# CONFIG_MIPS_VPE_LOADER is not set 115# CONFIG_MIPS_VPE_LOADER is not set
116CONFIG_64BIT_PHYS_ADDR=y 116CONFIG_64BIT_PHYS_ADDR=y
117CONFIG_CPU_HAS_LLSC=y
118CONFIG_CPU_HAS_SYNC=y 117CONFIG_CPU_HAS_SYNC=y
119CONFIG_GENERIC_HARDIRQS=y 118CONFIG_GENERIC_HARDIRQS=y
120CONFIG_GENERIC_IRQ_PROBE=y 119CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 7956f56cbf3e..1d896fd830da 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
115# CONFIG_MIPS_MT_SMTC is not set 115# CONFIG_MIPS_MT_SMTC is not set
116# CONFIG_MIPS_VPE_LOADER is not set 116# CONFIG_MIPS_VPE_LOADER is not set
117CONFIG_64BIT_PHYS_ADDR=y 117CONFIG_64BIT_PHYS_ADDR=y
118CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_SYNC=y 118CONFIG_CPU_HAS_SYNC=y
120CONFIG_GENERIC_HARDIRQS=y 119CONFIG_GENERIC_HARDIRQS=y
121CONFIG_GENERIC_IRQ_PROBE=y 120CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
index 2728caa6c2fb..fef4d31c2055 100644
--- a/arch/mips/configs/pnx8335-stb225_defconfig
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -112,7 +112,6 @@ CONFIG_CPU_HAS_PREFETCH=y
112CONFIG_MIPS_MT_DISABLED=y 112CONFIG_MIPS_MT_DISABLED=y
113# CONFIG_MIPS_MT_SMP is not set 113# CONFIG_MIPS_MT_SMP is not set
114# CONFIG_MIPS_MT_SMTC is not set 114# CONFIG_MIPS_MT_SMTC is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_MIPSR2_IRQ_VI=y 115CONFIG_CPU_MIPSR2_IRQ_VI=y
117CONFIG_CPU_HAS_SYNC=y 116CONFIG_CPU_HAS_SYNC=y
118CONFIG_GENERIC_HARDIRQS=y 117CONFIG_GENERIC_HARDIRQS=y
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 723bd5176a35..e10c7116c3c2 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -112,7 +112,6 @@ CONFIG_MIPS_MT_DISABLED=y
112# CONFIG_MIPS_MT_SMTC is not set 112# CONFIG_MIPS_MT_SMTC is not set
113# CONFIG_MIPS_VPE_LOADER is not set 113# CONFIG_MIPS_VPE_LOADER is not set
114# CONFIG_64BIT_PHYS_ADDR is not set 114# CONFIG_64BIT_PHYS_ADDR is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_HAS_SYNC=y 115CONFIG_CPU_HAS_SYNC=y
117CONFIG_GENERIC_HARDIRQS=y 116CONFIG_GENERIC_HARDIRQS=y
118CONFIG_GENERIC_IRQ_PROBE=y 117CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index b5052fb42e9e..5ed3c8dfa0a1 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -112,7 +112,6 @@ CONFIG_MIPS_MT_DISABLED=y
112# CONFIG_MIPS_MT_SMTC is not set 112# CONFIG_MIPS_MT_SMTC is not set
113# CONFIG_MIPS_VPE_LOADER is not set 113# CONFIG_MIPS_VPE_LOADER is not set
114# CONFIG_64BIT_PHYS_ADDR is not set 114# CONFIG_64BIT_PHYS_ADDR is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_HAS_SYNC=y 115CONFIG_CPU_HAS_SYNC=y
117CONFIG_GENERIC_HARDIRQS=y 116CONFIG_GENERIC_HARDIRQS=y
118CONFIG_GENERIC_IRQ_PROBE=y 117CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index f28dc32974e5..f40c3a04739d 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -113,7 +113,6 @@ CONFIG_CPU_HAS_PREFETCH=y
113CONFIG_MIPS_MT_DISABLED=y 113CONFIG_MIPS_MT_DISABLED=y
114# CONFIG_MIPS_MT_SMP is not set 114# CONFIG_MIPS_MT_SMP is not set
115# CONFIG_MIPS_MT_SMTC is not set 115# CONFIG_MIPS_MT_SMTC is not set
116CONFIG_CPU_HAS_LLSC=y
117CONFIG_CPU_HAS_SYNC=y 116CONFIG_CPU_HAS_SYNC=y
118CONFIG_GENERIC_HARDIRQS=y 117CONFIG_GENERIC_HARDIRQS=y
119CONFIG_GENERIC_IRQ_PROBE=y 118CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 1efe977497dd..c69813b8488c 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -142,7 +142,6 @@ CONFIG_CPU_HAS_PREFETCH=y
142CONFIG_MIPS_MT_DISABLED=y 142CONFIG_MIPS_MT_DISABLED=y
143# CONFIG_MIPS_MT_SMP is not set 143# CONFIG_MIPS_MT_SMP is not set
144# CONFIG_MIPS_MT_SMTC is not set 144# CONFIG_MIPS_MT_SMTC is not set
145CONFIG_CPU_HAS_LLSC=y
146CONFIG_CPU_HAS_SYNC=y 145CONFIG_CPU_HAS_SYNC=y
147CONFIG_GENERIC_HARDIRQS=y 146CONFIG_GENERIC_HARDIRQS=y
148CONFIG_GENERIC_IRQ_PROBE=y 147CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 0f4da0325ea4..e53b8d096cfc 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -124,7 +124,6 @@ CONFIG_MIPS_MT_DISABLED=y
124# CONFIG_MIPS_MT_SMTC is not set 124# CONFIG_MIPS_MT_SMTC is not set
125# CONFIG_MIPS_VPE_LOADER is not set 125# CONFIG_MIPS_VPE_LOADER is not set
126# CONFIG_64BIT_PHYS_ADDR is not set 126# CONFIG_64BIT_PHYS_ADDR is not set
127CONFIG_CPU_HAS_LLSC=y
128CONFIG_CPU_HAS_SYNC=y 127CONFIG_CPU_HAS_SYNC=y
129CONFIG_GENERIC_HARDIRQS=y 128CONFIG_GENERIC_HARDIRQS=y
130CONFIG_GENERIC_IRQ_PROBE=y 129CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index a9acaa2f9da3..7f38c0b956f3 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -133,7 +133,6 @@ CONFIG_MIPS_MT_DISABLED=y
133# CONFIG_MIPS_MT_SMP is not set 133# CONFIG_MIPS_MT_SMP is not set
134# CONFIG_MIPS_MT_SMTC is not set 134# CONFIG_MIPS_MT_SMTC is not set
135CONFIG_SB1_PASS_2_WORKAROUNDS=y 135CONFIG_SB1_PASS_2_WORKAROUNDS=y
136CONFIG_CPU_HAS_LLSC=y
137CONFIG_CPU_HAS_SYNC=y 136CONFIG_CPU_HAS_SYNC=y
138CONFIG_GENERIC_HARDIRQS=y 137CONFIG_GENERIC_HARDIRQS=y
139CONFIG_GENERIC_IRQ_PROBE=y 138CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index fc2c56731b98..06acc7482e4c 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -120,7 +120,6 @@ CONFIG_MIPS_MT_DISABLED=y
120# CONFIG_MIPS_MT_SMTC is not set 120# CONFIG_MIPS_MT_SMTC is not set
121# CONFIG_MIPS_VPE_LOADER is not set 121# CONFIG_MIPS_VPE_LOADER is not set
122# CONFIG_64BIT_PHYS_ADDR is not set 122# CONFIG_64BIT_PHYS_ADDR is not set
123CONFIG_CPU_HAS_LLSC=y
124CONFIG_CPU_HAS_SYNC=y 123CONFIG_CPU_HAS_SYNC=y
125CONFIG_GENERIC_HARDIRQS=y 124CONFIG_GENERIC_HARDIRQS=y
126CONFIG_GENERIC_IRQ_PROBE=y 125CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index ea8249c75b3f..69feaf88b510 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
115# CONFIG_MIPS_MT_SMTC is not set 115# CONFIG_MIPS_MT_SMTC is not set
116# CONFIG_MIPS_VPE_LOADER is not set 116# CONFIG_MIPS_VPE_LOADER is not set
117# CONFIG_64BIT_PHYS_ADDR is not set 117# CONFIG_64BIT_PHYS_ADDR is not set
118CONFIG_CPU_HAS_LLSC=y
119CONFIG_CPU_HAS_SYNC=y 118CONFIG_CPU_HAS_SYNC=y
120CONFIG_GENERIC_HARDIRQS=y 119CONFIG_GENERIC_HARDIRQS=y
121CONFIG_GENERIC_IRQ_PROBE=y 120CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index 5a557e268f78..e95ff3054ff6 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -18,7 +18,7 @@
18#include <asm/sections.h> 18#include <asm/sections.h>
19 19
20 20
21volatile unsigned long mem_err = 0; /* So we know an error occurred */ 21volatile unsigned long mem_err; /* So we know an error occurred */
22 22
23/* 23/*
24 * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen 24 * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen
diff --git a/arch/mips/emma/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index 335dc8c1a1bb..9b3f51e5f140 100644
--- a/arch/mips/emma/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -32,7 +32,7 @@
32 32
33extern void markeins_led(const char *); 33extern void markeins_led(const char *);
34 34
35static int bus_frequency = 0; 35static int bus_frequency;
36 36
37static void markeins_machine_restart(char *command) 37static void markeins_machine_restart(char *command)
38{ 38{
diff --git a/arch/mips/fw/arc/Makefile b/arch/mips/fw/arc/Makefile
index 4f349ec1ea2d..e0aaad482b0e 100644
--- a/arch/mips/fw/arc/Makefile
+++ b/arch/mips/fw/arc/Makefile
@@ -8,3 +8,5 @@ lib-y += cmdline.o env.o file.o identify.o init.o \
8lib-$(CONFIG_ARC_MEMORY) += memory.o 8lib-$(CONFIG_ARC_MEMORY) += memory.o
9lib-$(CONFIG_ARC_CONSOLE) += arc_con.o 9lib-$(CONFIG_ARC_CONSOLE) += arc_con.o
10lib-$(CONFIG_ARC_PROMLIB) += promlib.o 10lib-$(CONFIG_ARC_PROMLIB) += promlib.o
11
12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
index 717db74f7c6e..d06dc5a6b8d3 100644
--- a/arch/mips/fw/cfe/cfe_api.c
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -45,8 +45,8 @@ int cfe_iocb_dispatch(struct cfe_xiocb *xiocb);
45 * passed in two registers each, and CFE expects one. 45 * passed in two registers each, and CFE expects one.
46 */ 46 */
47 47
48static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; 48static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb);
49static u64 cfe_handle = 0; 49static u64 cfe_handle;
50 50
51int cfe_init(u64 handle, u64 ept) 51int cfe_init(u64 handle, u64 ept)
52{ 52{
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index eb7f01cfd1ac..dd75d673447e 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -49,7 +49,7 @@
49 */ 49 */
50static __inline__ void atomic_add(int i, atomic_t * v) 50static __inline__ void atomic_add(int i, atomic_t * v)
51{ 51{
52 if (cpu_has_llsc && R10000_LLSC_WAR) { 52 if (kernel_uses_llsc && R10000_LLSC_WAR) {
53 int temp; 53 int temp;
54 54
55 __asm__ __volatile__( 55 __asm__ __volatile__(
@@ -61,7 +61,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
61 " .set mips0 \n" 61 " .set mips0 \n"
62 : "=&r" (temp), "=m" (v->counter) 62 : "=&r" (temp), "=m" (v->counter)
63 : "Ir" (i), "m" (v->counter)); 63 : "Ir" (i), "m" (v->counter));
64 } else if (cpu_has_llsc) { 64 } else if (kernel_uses_llsc) {
65 int temp; 65 int temp;
66 66
67 __asm__ __volatile__( 67 __asm__ __volatile__(
@@ -94,7 +94,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
94 */ 94 */
95static __inline__ void atomic_sub(int i, atomic_t * v) 95static __inline__ void atomic_sub(int i, atomic_t * v)
96{ 96{
97 if (cpu_has_llsc && R10000_LLSC_WAR) { 97 if (kernel_uses_llsc && R10000_LLSC_WAR) {
98 int temp; 98 int temp;
99 99
100 __asm__ __volatile__( 100 __asm__ __volatile__(
@@ -106,7 +106,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
106 " .set mips0 \n" 106 " .set mips0 \n"
107 : "=&r" (temp), "=m" (v->counter) 107 : "=&r" (temp), "=m" (v->counter)
108 : "Ir" (i), "m" (v->counter)); 108 : "Ir" (i), "m" (v->counter));
109 } else if (cpu_has_llsc) { 109 } else if (kernel_uses_llsc) {
110 int temp; 110 int temp;
111 111
112 __asm__ __volatile__( 112 __asm__ __volatile__(
@@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
139 139
140 smp_llsc_mb(); 140 smp_llsc_mb();
141 141
142 if (cpu_has_llsc && R10000_LLSC_WAR) { 142 if (kernel_uses_llsc && R10000_LLSC_WAR) {
143 int temp; 143 int temp;
144 144
145 __asm__ __volatile__( 145 __asm__ __volatile__(
@@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
153 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 153 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
154 : "Ir" (i), "m" (v->counter) 154 : "Ir" (i), "m" (v->counter)
155 : "memory"); 155 : "memory");
156 } else if (cpu_has_llsc) { 156 } else if (kernel_uses_llsc) {
157 int temp; 157 int temp;
158 158
159 __asm__ __volatile__( 159 __asm__ __volatile__(
@@ -191,7 +191,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
191 191
192 smp_llsc_mb(); 192 smp_llsc_mb();
193 193
194 if (cpu_has_llsc && R10000_LLSC_WAR) { 194 if (kernel_uses_llsc && R10000_LLSC_WAR) {
195 int temp; 195 int temp;
196 196
197 __asm__ __volatile__( 197 __asm__ __volatile__(
@@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
205 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 205 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
206 : "Ir" (i), "m" (v->counter) 206 : "Ir" (i), "m" (v->counter)
207 : "memory"); 207 : "memory");
208 } else if (cpu_has_llsc) { 208 } else if (kernel_uses_llsc) {
209 int temp; 209 int temp;
210 210
211 __asm__ __volatile__( 211 __asm__ __volatile__(
@@ -251,7 +251,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
251 251
252 smp_llsc_mb(); 252 smp_llsc_mb();
253 253
254 if (cpu_has_llsc && R10000_LLSC_WAR) { 254 if (kernel_uses_llsc && R10000_LLSC_WAR) {
255 int temp; 255 int temp;
256 256
257 __asm__ __volatile__( 257 __asm__ __volatile__(
@@ -269,7 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
269 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 269 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
270 : "Ir" (i), "m" (v->counter) 270 : "Ir" (i), "m" (v->counter)
271 : "memory"); 271 : "memory");
272 } else if (cpu_has_llsc) { 272 } else if (kernel_uses_llsc) {
273 int temp; 273 int temp;
274 274
275 __asm__ __volatile__( 275 __asm__ __volatile__(
@@ -428,7 +428,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
428 */ 428 */
429static __inline__ void atomic64_add(long i, atomic64_t * v) 429static __inline__ void atomic64_add(long i, atomic64_t * v)
430{ 430{
431 if (cpu_has_llsc && R10000_LLSC_WAR) { 431 if (kernel_uses_llsc && R10000_LLSC_WAR) {
432 long temp; 432 long temp;
433 433
434 __asm__ __volatile__( 434 __asm__ __volatile__(
@@ -440,7 +440,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
440 " .set mips0 \n" 440 " .set mips0 \n"
441 : "=&r" (temp), "=m" (v->counter) 441 : "=&r" (temp), "=m" (v->counter)
442 : "Ir" (i), "m" (v->counter)); 442 : "Ir" (i), "m" (v->counter));
443 } else if (cpu_has_llsc) { 443 } else if (kernel_uses_llsc) {
444 long temp; 444 long temp;
445 445
446 __asm__ __volatile__( 446 __asm__ __volatile__(
@@ -473,7 +473,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
473 */ 473 */
474static __inline__ void atomic64_sub(long i, atomic64_t * v) 474static __inline__ void atomic64_sub(long i, atomic64_t * v)
475{ 475{
476 if (cpu_has_llsc && R10000_LLSC_WAR) { 476 if (kernel_uses_llsc && R10000_LLSC_WAR) {
477 long temp; 477 long temp;
478 478
479 __asm__ __volatile__( 479 __asm__ __volatile__(
@@ -485,7 +485,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
485 " .set mips0 \n" 485 " .set mips0 \n"
486 : "=&r" (temp), "=m" (v->counter) 486 : "=&r" (temp), "=m" (v->counter)
487 : "Ir" (i), "m" (v->counter)); 487 : "Ir" (i), "m" (v->counter));
488 } else if (cpu_has_llsc) { 488 } else if (kernel_uses_llsc) {
489 long temp; 489 long temp;
490 490
491 __asm__ __volatile__( 491 __asm__ __volatile__(
@@ -518,7 +518,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
518 518
519 smp_llsc_mb(); 519 smp_llsc_mb();
520 520
521 if (cpu_has_llsc && R10000_LLSC_WAR) { 521 if (kernel_uses_llsc && R10000_LLSC_WAR) {
522 long temp; 522 long temp;
523 523
524 __asm__ __volatile__( 524 __asm__ __volatile__(
@@ -532,7 +532,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
532 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 532 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
533 : "Ir" (i), "m" (v->counter) 533 : "Ir" (i), "m" (v->counter)
534 : "memory"); 534 : "memory");
535 } else if (cpu_has_llsc) { 535 } else if (kernel_uses_llsc) {
536 long temp; 536 long temp;
537 537
538 __asm__ __volatile__( 538 __asm__ __volatile__(
@@ -570,7 +570,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
570 570
571 smp_llsc_mb(); 571 smp_llsc_mb();
572 572
573 if (cpu_has_llsc && R10000_LLSC_WAR) { 573 if (kernel_uses_llsc && R10000_LLSC_WAR) {
574 long temp; 574 long temp;
575 575
576 __asm__ __volatile__( 576 __asm__ __volatile__(
@@ -584,7 +584,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
584 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 584 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
585 : "Ir" (i), "m" (v->counter) 585 : "Ir" (i), "m" (v->counter)
586 : "memory"); 586 : "memory");
587 } else if (cpu_has_llsc) { 587 } else if (kernel_uses_llsc) {
588 long temp; 588 long temp;
589 589
590 __asm__ __volatile__( 590 __asm__ __volatile__(
@@ -630,7 +630,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
630 630
631 smp_llsc_mb(); 631 smp_llsc_mb();
632 632
633 if (cpu_has_llsc && R10000_LLSC_WAR) { 633 if (kernel_uses_llsc && R10000_LLSC_WAR) {
634 long temp; 634 long temp;
635 635
636 __asm__ __volatile__( 636 __asm__ __volatile__(
@@ -648,7 +648,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
648 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 648 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
649 : "Ir" (i), "m" (v->counter) 649 : "Ir" (i), "m" (v->counter)
650 : "memory"); 650 : "memory");
651 } else if (cpu_has_llsc) { 651 } else if (kernel_uses_llsc) {
652 long temp; 652 long temp;
653 653
654 __asm__ __volatile__( 654 __asm__ __volatile__(
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index b1e9e97a9c78..84a383806b2c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -61,7 +61,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
61 unsigned short bit = nr & SZLONG_MASK; 61 unsigned short bit = nr & SZLONG_MASK;
62 unsigned long temp; 62 unsigned long temp;
63 63
64 if (cpu_has_llsc && R10000_LLSC_WAR) { 64 if (kernel_uses_llsc && R10000_LLSC_WAR) {
65 __asm__ __volatile__( 65 __asm__ __volatile__(
66 " .set mips3 \n" 66 " .set mips3 \n"
67 "1: " __LL "%0, %1 # set_bit \n" 67 "1: " __LL "%0, %1 # set_bit \n"
@@ -72,7 +72,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
72 : "=&r" (temp), "=m" (*m) 72 : "=&r" (temp), "=m" (*m)
73 : "ir" (1UL << bit), "m" (*m)); 73 : "ir" (1UL << bit), "m" (*m));
74#ifdef CONFIG_CPU_MIPSR2 74#ifdef CONFIG_CPU_MIPSR2
75 } else if (__builtin_constant_p(bit)) { 75 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
76 __asm__ __volatile__( 76 __asm__ __volatile__(
77 "1: " __LL "%0, %1 # set_bit \n" 77 "1: " __LL "%0, %1 # set_bit \n"
78 " " __INS "%0, %4, %2, 1 \n" 78 " " __INS "%0, %4, %2, 1 \n"
@@ -84,7 +84,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
84 : "=&r" (temp), "=m" (*m) 84 : "=&r" (temp), "=m" (*m)
85 : "ir" (bit), "m" (*m), "r" (~0)); 85 : "ir" (bit), "m" (*m), "r" (~0));
86#endif /* CONFIG_CPU_MIPSR2 */ 86#endif /* CONFIG_CPU_MIPSR2 */
87 } else if (cpu_has_llsc) { 87 } else if (kernel_uses_llsc) {
88 __asm__ __volatile__( 88 __asm__ __volatile__(
89 " .set mips3 \n" 89 " .set mips3 \n"
90 "1: " __LL "%0, %1 # set_bit \n" 90 "1: " __LL "%0, %1 # set_bit \n"
@@ -126,7 +126,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
126 unsigned short bit = nr & SZLONG_MASK; 126 unsigned short bit = nr & SZLONG_MASK;
127 unsigned long temp; 127 unsigned long temp;
128 128
129 if (cpu_has_llsc && R10000_LLSC_WAR) { 129 if (kernel_uses_llsc && R10000_LLSC_WAR) {
130 __asm__ __volatile__( 130 __asm__ __volatile__(
131 " .set mips3 \n" 131 " .set mips3 \n"
132 "1: " __LL "%0, %1 # clear_bit \n" 132 "1: " __LL "%0, %1 # clear_bit \n"
@@ -137,7 +137,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
137 : "=&r" (temp), "=m" (*m) 137 : "=&r" (temp), "=m" (*m)
138 : "ir" (~(1UL << bit)), "m" (*m)); 138 : "ir" (~(1UL << bit)), "m" (*m));
139#ifdef CONFIG_CPU_MIPSR2 139#ifdef CONFIG_CPU_MIPSR2
140 } else if (__builtin_constant_p(bit)) { 140 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
141 __asm__ __volatile__( 141 __asm__ __volatile__(
142 "1: " __LL "%0, %1 # clear_bit \n" 142 "1: " __LL "%0, %1 # clear_bit \n"
143 " " __INS "%0, $0, %2, 1 \n" 143 " " __INS "%0, $0, %2, 1 \n"
@@ -149,7 +149,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
149 : "=&r" (temp), "=m" (*m) 149 : "=&r" (temp), "=m" (*m)
150 : "ir" (bit), "m" (*m)); 150 : "ir" (bit), "m" (*m));
151#endif /* CONFIG_CPU_MIPSR2 */ 151#endif /* CONFIG_CPU_MIPSR2 */
152 } else if (cpu_has_llsc) { 152 } else if (kernel_uses_llsc) {
153 __asm__ __volatile__( 153 __asm__ __volatile__(
154 " .set mips3 \n" 154 " .set mips3 \n"
155 "1: " __LL "%0, %1 # clear_bit \n" 155 "1: " __LL "%0, %1 # clear_bit \n"
@@ -202,7 +202,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
202{ 202{
203 unsigned short bit = nr & SZLONG_MASK; 203 unsigned short bit = nr & SZLONG_MASK;
204 204
205 if (cpu_has_llsc && R10000_LLSC_WAR) { 205 if (kernel_uses_llsc && R10000_LLSC_WAR) {
206 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 206 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
207 unsigned long temp; 207 unsigned long temp;
208 208
@@ -215,7 +215,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
215 " .set mips0 \n" 215 " .set mips0 \n"
216 : "=&r" (temp), "=m" (*m) 216 : "=&r" (temp), "=m" (*m)
217 : "ir" (1UL << bit), "m" (*m)); 217 : "ir" (1UL << bit), "m" (*m));
218 } else if (cpu_has_llsc) { 218 } else if (kernel_uses_llsc) {
219 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 219 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
220 unsigned long temp; 220 unsigned long temp;
221 221
@@ -260,7 +260,7 @@ static inline int test_and_set_bit(unsigned long nr,
260 260
261 smp_llsc_mb(); 261 smp_llsc_mb();
262 262
263 if (cpu_has_llsc && R10000_LLSC_WAR) { 263 if (kernel_uses_llsc && R10000_LLSC_WAR) {
264 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 264 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
265 unsigned long temp; 265 unsigned long temp;
266 266
@@ -275,7 +275,7 @@ static inline int test_and_set_bit(unsigned long nr,
275 : "=&r" (temp), "=m" (*m), "=&r" (res) 275 : "=&r" (temp), "=m" (*m), "=&r" (res)
276 : "r" (1UL << bit), "m" (*m) 276 : "r" (1UL << bit), "m" (*m)
277 : "memory"); 277 : "memory");
278 } else if (cpu_has_llsc) { 278 } else if (kernel_uses_llsc) {
279 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 279 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
280 unsigned long temp; 280 unsigned long temp;
281 281
@@ -328,7 +328,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
328 unsigned short bit = nr & SZLONG_MASK; 328 unsigned short bit = nr & SZLONG_MASK;
329 unsigned long res; 329 unsigned long res;
330 330
331 if (cpu_has_llsc && R10000_LLSC_WAR) { 331 if (kernel_uses_llsc && R10000_LLSC_WAR) {
332 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 332 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
333 unsigned long temp; 333 unsigned long temp;
334 334
@@ -343,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
343 : "=&r" (temp), "=m" (*m), "=&r" (res) 343 : "=&r" (temp), "=m" (*m), "=&r" (res)
344 : "r" (1UL << bit), "m" (*m) 344 : "r" (1UL << bit), "m" (*m)
345 : "memory"); 345 : "memory");
346 } else if (cpu_has_llsc) { 346 } else if (kernel_uses_llsc) {
347 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 347 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
348 unsigned long temp; 348 unsigned long temp;
349 349
@@ -397,7 +397,7 @@ static inline int test_and_clear_bit(unsigned long nr,
397 397
398 smp_llsc_mb(); 398 smp_llsc_mb();
399 399
400 if (cpu_has_llsc && R10000_LLSC_WAR) { 400 if (kernel_uses_llsc && R10000_LLSC_WAR) {
401 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 401 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
402 unsigned long temp; 402 unsigned long temp;
403 403
@@ -414,7 +414,7 @@ static inline int test_and_clear_bit(unsigned long nr,
414 : "r" (1UL << bit), "m" (*m) 414 : "r" (1UL << bit), "m" (*m)
415 : "memory"); 415 : "memory");
416#ifdef CONFIG_CPU_MIPSR2 416#ifdef CONFIG_CPU_MIPSR2
417 } else if (__builtin_constant_p(nr)) { 417 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
418 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 418 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
419 unsigned long temp; 419 unsigned long temp;
420 420
@@ -431,7 +431,7 @@ static inline int test_and_clear_bit(unsigned long nr,
431 : "ir" (bit), "m" (*m) 431 : "ir" (bit), "m" (*m)
432 : "memory"); 432 : "memory");
433#endif 433#endif
434 } else if (cpu_has_llsc) { 434 } else if (kernel_uses_llsc) {
435 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 435 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
436 unsigned long temp; 436 unsigned long temp;
437 437
@@ -487,7 +487,7 @@ static inline int test_and_change_bit(unsigned long nr,
487 487
488 smp_llsc_mb(); 488 smp_llsc_mb();
489 489
490 if (cpu_has_llsc && R10000_LLSC_WAR) { 490 if (kernel_uses_llsc && R10000_LLSC_WAR) {
491 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 491 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
492 unsigned long temp; 492 unsigned long temp;
493 493
@@ -502,7 +502,7 @@ static inline int test_and_change_bit(unsigned long nr,
502 : "=&r" (temp), "=m" (*m), "=&r" (res) 502 : "=&r" (temp), "=m" (*m), "=&r" (res)
503 : "r" (1UL << bit), "m" (*m) 503 : "r" (1UL << bit), "m" (*m)
504 : "memory"); 504 : "memory");
505 } else if (cpu_has_llsc) { 505 } else if (kernel_uses_llsc) {
506 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 506 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
507 unsigned long temp; 507 unsigned long temp;
508 508
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 610fe3af7a03..f5dfaf6a1606 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -7,6 +7,7 @@
7 * Copyright (C) 1995, 1996 Andreas Busse 7 * Copyright (C) 1995, 1996 Andreas Busse
8 * Copyright (C) 1995, 1996 Stoned Elipot 8 * Copyright (C) 1995, 1996 Stoned Elipot
9 * Copyright (C) 1995, 1996 Paul M. Antoine. 9 * Copyright (C) 1995, 1996 Paul M. Antoine.
10 * Copyright (C) 2009 Zhang Le
10 */ 11 */
11#ifndef _ASM_BOOTINFO_H 12#ifndef _ASM_BOOTINFO_H
12#define _ASM_BOOTINFO_H 13#define _ASM_BOOTINFO_H
@@ -57,6 +58,17 @@
57#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ 58#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
58#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ 59#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
59 60
61/*
62 * Valid machtype for Loongson family
63 */
64#define MACH_LOONGSON_UNKNOWN 0
65#define MACH_LEMOTE_FL2E 1
66#define MACH_LEMOTE_FL2F 2
67#define MACH_LEMOTE_ML2F7 3
68#define MACH_LEMOTE_YL2F89 4
69#define MACH_DEXXON_GDIUM2F10 5
70#define MACH_LOONGSON_END 6
71
60#define CL_SIZE COMMAND_LINE_SIZE 72#define CL_SIZE COMMAND_LINE_SIZE
61 73
62extern char *system_type; 74extern char *system_type;
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 4a812c3ceb90..815a438a268d 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -16,7 +16,7 @@
16({ \ 16({ \
17 __typeof(*(m)) __ret; \ 17 __typeof(*(m)) __ret; \
18 \ 18 \
19 if (cpu_has_llsc && R10000_LLSC_WAR) { \ 19 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
20 __asm__ __volatile__( \ 20 __asm__ __volatile__( \
21 " .set push \n" \ 21 " .set push \n" \
22 " .set noat \n" \ 22 " .set noat \n" \
@@ -33,7 +33,7 @@
33 : "=&r" (__ret), "=R" (*m) \ 33 : "=&r" (__ret), "=R" (*m) \
34 : "R" (*m), "Jr" (old), "Jr" (new) \ 34 : "R" (*m), "Jr" (old), "Jr" (new) \
35 : "memory"); \ 35 : "memory"); \
36 } else if (cpu_has_llsc) { \ 36 } else if (kernel_uses_llsc) { \
37 __asm__ __volatile__( \ 37 __asm__ __volatile__( \
38 " .set push \n" \ 38 " .set push \n" \
39 " .set noat \n" \ 39 " .set noat \n" \
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 8ab1d12ba7f4..1f4df647c384 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -80,6 +80,9 @@
80#ifndef cpu_has_llsc 80#ifndef cpu_has_llsc
81#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 81#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
82#endif 82#endif
83#ifndef kernel_uses_llsc
84#define kernel_uses_llsc cpu_has_llsc
85#endif
83#ifndef cpu_has_mips16 86#ifndef cpu_has_mips16
84#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 87#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
85#endif 88#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 3bdc0e3d89cc..4b96d1a36056 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -113,6 +113,12 @@
113 113
114#define PRID_IMP_BCM4710 0x4000 114#define PRID_IMP_BCM4710 0x4000
115#define PRID_IMP_BCM3302 0x9000 115#define PRID_IMP_BCM3302 0x9000
116#define PRID_IMP_BCM6338 0x9000
117#define PRID_IMP_BCM6345 0x8000
118#define PRID_IMP_BCM6348 0x9100
119#define PRID_IMP_BCM4350 0xA000
120#define PRID_REV_BCM6358 0x0010
121#define PRID_REV_BCM6368 0x0030
116 122
117/* 123/*
118 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 124 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
@@ -210,6 +216,7 @@ enum cpu_type_enum {
210 */ 216 */
211 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 217 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
212 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, 218 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
219 CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
213 220
214 /* 221 /*
215 * MIPS64 class processors 222 * MIPS64 class processors
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
index d2d8949be6b7..e7cd78277c23 100644
--- a/arch/mips/include/asm/delay.h
+++ b/arch/mips/include/asm/delay.h
@@ -11,6 +11,8 @@
11#ifndef _ASM_DELAY_H 11#ifndef _ASM_DELAY_H
12#define _ASM_DELAY_H 12#define _ASM_DELAY_H
13 13
14#include <linux/param.h>
15
14extern void __delay(unsigned int loops); 16extern void __delay(unsigned int loops);
15extern void __ndelay(unsigned int ns); 17extern void __ndelay(unsigned int ns);
16extern void __udelay(unsigned int us); 18extern void __udelay(unsigned int us);
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index 0f5caa1307f1..efeddc8db8b1 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -67,11 +67,15 @@ enum fixed_addresses {
67 * the start of the fixmap, and leave one page empty 67 * the start of the fixmap, and leave one page empty
68 * at the top of mem.. 68 * at the top of mem..
69 */ 69 */
70#ifdef CONFIG_BCM63XX
71#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
72#else
70#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) 73#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
71#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) 74#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000))
72#else 75#else
73#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) 76#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
74#endif 77#endif
78#endif
75#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) 79#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
76#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 80#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
77 81
diff --git a/arch/mips/include/asm/hardirq.h b/arch/mips/include/asm/hardirq.h
index 90bf399e6dd9..c977a86c2c65 100644
--- a/arch/mips/include/asm/hardirq.h
+++ b/arch/mips/include/asm/hardirq.h
@@ -10,15 +10,9 @@
10#ifndef _ASM_HARDIRQ_H 10#ifndef _ASM_HARDIRQ_H
11#define _ASM_HARDIRQ_H 11#define _ASM_HARDIRQ_H
12 12
13#include <linux/threads.h>
14#include <linux/irq.h>
15
16typedef struct {
17 unsigned int __softirq_pending;
18} ____cacheline_aligned irq_cpustat_t;
19
20#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
21
22extern void ack_bad_irq(unsigned int irq); 13extern void ack_bad_irq(unsigned int irq);
14#define ack_bad_irq ack_bad_irq
15
16#include <asm-generic/hardirq.h>
23 17
24#endif /* _ASM_HARDIRQ_H */ 18#endif /* _ASM_HARDIRQ_H */
diff --git a/arch/mips/include/asm/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h
index caeba1e302a2..a1ada1c27c16 100644
--- a/arch/mips/include/asm/lasat/lasat.h
+++ b/arch/mips/include/asm/lasat/lasat.h
@@ -227,6 +227,7 @@ extern void lasat_write_eeprom_info(void);
227 * It is used for the bit-banging rtc and eeprom drivers */ 227 * It is used for the bit-banging rtc and eeprom drivers */
228 228
229#include <linux/delay.h> 229#include <linux/delay.h>
230#include <linux/smp.h>
230 231
231/* calculating with the slowest board with 100 MHz clock */ 232/* calculating with the slowest board with 100 MHz clock */
232#define LASAT_100_DIVIDER 20 233#define LASAT_100_DIVIDER 20
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index f96fd59e0845..361f4f16c30c 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -29,7 +29,7 @@ static __inline__ long local_add_return(long i, local_t * l)
29{ 29{
30 unsigned long result; 30 unsigned long result;
31 31
32 if (cpu_has_llsc && R10000_LLSC_WAR) { 32 if (kernel_uses_llsc && R10000_LLSC_WAR) {
33 unsigned long temp; 33 unsigned long temp;
34 34
35 __asm__ __volatile__( 35 __asm__ __volatile__(
@@ -43,7 +43,7 @@ static __inline__ long local_add_return(long i, local_t * l)
43 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) 43 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
44 : "Ir" (i), "m" (l->a.counter) 44 : "Ir" (i), "m" (l->a.counter)
45 : "memory"); 45 : "memory");
46 } else if (cpu_has_llsc) { 46 } else if (kernel_uses_llsc) {
47 unsigned long temp; 47 unsigned long temp;
48 48
49 __asm__ __volatile__( 49 __asm__ __volatile__(
@@ -74,7 +74,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
74{ 74{
75 unsigned long result; 75 unsigned long result;
76 76
77 if (cpu_has_llsc && R10000_LLSC_WAR) { 77 if (kernel_uses_llsc && R10000_LLSC_WAR) {
78 unsigned long temp; 78 unsigned long temp;
79 79
80 __asm__ __volatile__( 80 __asm__ __volatile__(
@@ -88,7 +88,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
88 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter) 88 : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
89 : "Ir" (i), "m" (l->a.counter) 89 : "Ir" (i), "m" (l->a.counter)
90 : "memory"); 90 : "memory");
91 } else if (cpu_has_llsc) { 91 } else if (kernel_uses_llsc) {
92 unsigned long temp; 92 unsigned long temp;
93 93
94 __asm__ __volatile__( 94 __asm__ __volatile__(
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 127d4ed9f073..feea00148b5d 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -578,6 +578,15 @@ static inline int irq_to_gpio(int irq)
578 return alchemy_irq_to_gpio(irq); 578 return alchemy_irq_to_gpio(irq);
579} 579}
580 580
581static inline int gpio_request(unsigned gpio, const char *label)
582{
583 return 0;
584}
585
586static inline void gpio_free(unsigned gpio)
587{
588}
589
581#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ 590#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
582 591
583 592
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
new file mode 100644
index 000000000000..fa3e7e617b09
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
@@ -0,0 +1,12 @@
1#ifndef BCM63XX_BOARD_H_
2#define BCM63XX_BOARD_H_
3
4const char *board_get_name(void);
5
6void board_prom_init(void);
7
8void board_setup(void);
9
10int board_register_devices(void);
11
12#endif /* ! BCM63XX_BOARD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
new file mode 100644
index 000000000000..8fcf8df4418a
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
@@ -0,0 +1,11 @@
1#ifndef BCM63XX_CLK_H_
2#define BCM63XX_CLK_H_
3
4struct clk {
5 void (*set)(struct clk *, int);
6 unsigned int rate;
7 unsigned int usage;
8 int id;
9};
10
11#endif /* ! BCM63XX_CLK_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
new file mode 100644
index 000000000000..b12c4aca2cc9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -0,0 +1,538 @@
1#ifndef BCM63XX_CPU_H_
2#define BCM63XX_CPU_H_
3
4#include <linux/types.h>
5#include <linux/init.h>
6
7/*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358
16
17void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void);
19u16 bcm63xx_get_cpu_rev(void);
20unsigned int bcm63xx_get_cpu_freq(void);
21
22#ifdef CONFIG_BCM63XX_CPU_6338
23# ifdef bcm63xx_get_cpu_id
24# undef bcm63xx_get_cpu_id
25# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
26# define BCMCPU_RUNTIME_DETECT
27# else
28# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
29# endif
30# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
31#else
32# define BCMCPU_IS_6338() (0)
33#endif
34
35#ifdef CONFIG_BCM63XX_CPU_6345
36# ifdef bcm63xx_get_cpu_id
37# undef bcm63xx_get_cpu_id
38# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
39# define BCMCPU_RUNTIME_DETECT
40# else
41# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
42# endif
43# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
44#else
45# define BCMCPU_IS_6345() (0)
46#endif
47
48#ifdef CONFIG_BCM63XX_CPU_6348
49# ifdef bcm63xx_get_cpu_id
50# undef bcm63xx_get_cpu_id
51# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
52# define BCMCPU_RUNTIME_DETECT
53# else
54# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
55# endif
56# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
57#else
58# define BCMCPU_IS_6348() (0)
59#endif
60
61#ifdef CONFIG_BCM63XX_CPU_6358
62# ifdef bcm63xx_get_cpu_id
63# undef bcm63xx_get_cpu_id
64# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
65# define BCMCPU_RUNTIME_DETECT
66# else
67# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
68# endif
69# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
70#else
71# define BCMCPU_IS_6358() (0)
72#endif
73
74#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured"
76#endif
77
78/*
79 * While registers sets are (mostly) the same across 63xx CPU, base
80 * address of these sets do change.
81 */
82enum bcm63xx_regs_set {
83 RSET_DSL_LMEM = 0,
84 RSET_PERF,
85 RSET_TIMER,
86 RSET_WDT,
87 RSET_UART0,
88 RSET_GPIO,
89 RSET_SPI,
90 RSET_UDC0,
91 RSET_OHCI0,
92 RSET_OHCI_PRIV,
93 RSET_USBH_PRIV,
94 RSET_MPI,
95 RSET_PCMCIA,
96 RSET_DSL,
97 RSET_ENET0,
98 RSET_ENET1,
99 RSET_ENETDMA,
100 RSET_EHCI0,
101 RSET_SDRAM,
102 RSET_MEMC,
103 RSET_DDR,
104};
105
106#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
107#define RSET_DSL_SIZE 4096
108#define RSET_WDT_SIZE 12
109#define RSET_ENET_SIZE 2048
110#define RSET_ENETDMA_SIZE 2048
111#define RSET_UART_SIZE 24
112#define RSET_UDC_SIZE 256
113#define RSET_OHCI_SIZE 256
114#define RSET_EHCI_SIZE 256
115#define RSET_PCMCIA_SIZE 12
116
117/*
118 * 6338 register sets base address
119 */
120#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
121#define BCM_6338_PERF_BASE (0xfffe0000)
122#define BCM_6338_BB_BASE (0xfffe0100)
123#define BCM_6338_TIMER_BASE (0xfffe0200)
124#define BCM_6338_WDT_BASE (0xfffe021c)
125#define BCM_6338_UART0_BASE (0xfffe0300)
126#define BCM_6338_GPIO_BASE (0xfffe0400)
127#define BCM_6338_SPI_BASE (0xfffe0c00)
128#define BCM_6338_UDC0_BASE (0xdeadbeef)
129#define BCM_6338_USBDMA_BASE (0xfffe2400)
130#define BCM_6338_OHCI0_BASE (0xdeadbeef)
131#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
132#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
133#define BCM_6338_MPI_BASE (0xfffe3160)
134#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
135#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
136#define BCM_6338_DSL_BASE (0xfffe1000)
137#define BCM_6338_SAR_BASE (0xfffe2000)
138#define BCM_6338_UBUS_BASE (0xdeadbeef)
139#define BCM_6338_ENET0_BASE (0xfffe2800)
140#define BCM_6338_ENET1_BASE (0xdeadbeef)
141#define BCM_6338_ENETDMA_BASE (0xfffe2400)
142#define BCM_6338_EHCI0_BASE (0xdeadbeef)
143#define BCM_6338_SDRAM_BASE (0xfffe3100)
144#define BCM_6338_MEMC_BASE (0xdeadbeef)
145#define BCM_6338_DDR_BASE (0xdeadbeef)
146
147/*
148 * 6345 register sets base address
149 */
150#define BCM_6345_DSL_LMEM_BASE (0xfff00000)
151#define BCM_6345_PERF_BASE (0xfffe0000)
152#define BCM_6345_BB_BASE (0xfffe0100)
153#define BCM_6345_TIMER_BASE (0xfffe0200)
154#define BCM_6345_WDT_BASE (0xfffe021c)
155#define BCM_6345_UART0_BASE (0xfffe0300)
156#define BCM_6345_GPIO_BASE (0xfffe0400)
157#define BCM_6345_SPI_BASE (0xdeadbeef)
158#define BCM_6345_UDC0_BASE (0xdeadbeef)
159#define BCM_6345_USBDMA_BASE (0xfffe2800)
160#define BCM_6345_ENET0_BASE (0xfffe1800)
161#define BCM_6345_ENETDMA_BASE (0xfffe2800)
162#define BCM_6345_PCMCIA_BASE (0xfffe2028)
163#define BCM_6345_MPI_BASE (0xdeadbeef)
164#define BCM_6345_OHCI0_BASE (0xfffe2100)
165#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
166#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
167#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
168#define BCM_6345_DSL_BASE (0xdeadbeef)
169#define BCM_6345_SAR_BASE (0xdeadbeef)
170#define BCM_6345_UBUS_BASE (0xdeadbeef)
171#define BCM_6345_ENET1_BASE (0xdeadbeef)
172#define BCM_6345_EHCI0_BASE (0xdeadbeef)
173#define BCM_6345_SDRAM_BASE (0xfffe2300)
174#define BCM_6345_MEMC_BASE (0xdeadbeef)
175#define BCM_6345_DDR_BASE (0xdeadbeef)
176
177/*
178 * 6348 register sets base address
179 */
180#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
181#define BCM_6348_PERF_BASE (0xfffe0000)
182#define BCM_6348_TIMER_BASE (0xfffe0200)
183#define BCM_6348_WDT_BASE (0xfffe021c)
184#define BCM_6348_UART0_BASE (0xfffe0300)
185#define BCM_6348_GPIO_BASE (0xfffe0400)
186#define BCM_6348_SPI_BASE (0xfffe0c00)
187#define BCM_6348_UDC0_BASE (0xfffe1000)
188#define BCM_6348_OHCI0_BASE (0xfffe1b00)
189#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
190#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
191#define BCM_6348_MPI_BASE (0xfffe2000)
192#define BCM_6348_PCMCIA_BASE (0xfffe2054)
193#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
194#define BCM_6348_DSL_BASE (0xfffe3000)
195#define BCM_6348_ENET0_BASE (0xfffe6000)
196#define BCM_6348_ENET1_BASE (0xfffe6800)
197#define BCM_6348_ENETDMA_BASE (0xfffe7000)
198#define BCM_6348_EHCI0_BASE (0xdeadbeef)
199#define BCM_6348_SDRAM_BASE (0xfffe2300)
200#define BCM_6348_MEMC_BASE (0xdeadbeef)
201#define BCM_6348_DDR_BASE (0xdeadbeef)
202
203/*
204 * 6358 register sets base address
205 */
206#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
207#define BCM_6358_PERF_BASE (0xfffe0000)
208#define BCM_6358_TIMER_BASE (0xfffe0040)
209#define BCM_6358_WDT_BASE (0xfffe005c)
210#define BCM_6358_UART0_BASE (0xfffe0100)
211#define BCM_6358_GPIO_BASE (0xfffe0080)
212#define BCM_6358_SPI_BASE (0xdeadbeef)
213#define BCM_6358_UDC0_BASE (0xfffe0800)
214#define BCM_6358_OHCI0_BASE (0xfffe1400)
215#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
216#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
217#define BCM_6358_MPI_BASE (0xfffe1000)
218#define BCM_6358_PCMCIA_BASE (0xfffe1054)
219#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
220#define BCM_6358_DSL_BASE (0xfffe3000)
221#define BCM_6358_ENET0_BASE (0xfffe4000)
222#define BCM_6358_ENET1_BASE (0xfffe4800)
223#define BCM_6358_ENETDMA_BASE (0xfffe5000)
224#define BCM_6358_EHCI0_BASE (0xfffe1300)
225#define BCM_6358_SDRAM_BASE (0xdeadbeef)
226#define BCM_6358_MEMC_BASE (0xfffe1200)
227#define BCM_6358_DDR_BASE (0xfffe12a0)
228
229
230extern const unsigned long *bcm63xx_regs_base;
231
232static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
233{
234#ifdef BCMCPU_RUNTIME_DETECT
235 return bcm63xx_regs_base[set];
236#else
237#ifdef CONFIG_BCM63XX_CPU_6338
238 switch (set) {
239 case RSET_DSL_LMEM:
240 return BCM_6338_DSL_LMEM_BASE;
241 case RSET_PERF:
242 return BCM_6338_PERF_BASE;
243 case RSET_TIMER:
244 return BCM_6338_TIMER_BASE;
245 case RSET_WDT:
246 return BCM_6338_WDT_BASE;
247 case RSET_UART0:
248 return BCM_6338_UART0_BASE;
249 case RSET_GPIO:
250 return BCM_6338_GPIO_BASE;
251 case RSET_SPI:
252 return BCM_6338_SPI_BASE;
253 case RSET_UDC0:
254 return BCM_6338_UDC0_BASE;
255 case RSET_OHCI0:
256 return BCM_6338_OHCI0_BASE;
257 case RSET_OHCI_PRIV:
258 return BCM_6338_OHCI_PRIV_BASE;
259 case RSET_USBH_PRIV:
260 return BCM_6338_USBH_PRIV_BASE;
261 case RSET_MPI:
262 return BCM_6338_MPI_BASE;
263 case RSET_PCMCIA:
264 return BCM_6338_PCMCIA_BASE;
265 case RSET_DSL:
266 return BCM_6338_DSL_BASE;
267 case RSET_ENET0:
268 return BCM_6338_ENET0_BASE;
269 case RSET_ENET1:
270 return BCM_6338_ENET1_BASE;
271 case RSET_ENETDMA:
272 return BCM_6338_ENETDMA_BASE;
273 case RSET_EHCI0:
274 return BCM_6338_EHCI0_BASE;
275 case RSET_SDRAM:
276 return BCM_6338_SDRAM_BASE;
277 case RSET_MEMC:
278 return BCM_6338_MEMC_BASE;
279 case RSET_DDR:
280 return BCM_6338_DDR_BASE;
281 }
282#endif
283#ifdef CONFIG_BCM63XX_CPU_6345
284 switch (set) {
285 case RSET_DSL_LMEM:
286 return BCM_6345_DSL_LMEM_BASE;
287 case RSET_PERF:
288 return BCM_6345_PERF_BASE;
289 case RSET_TIMER:
290 return BCM_6345_TIMER_BASE;
291 case RSET_WDT:
292 return BCM_6345_WDT_BASE;
293 case RSET_UART0:
294 return BCM_6345_UART0_BASE;
295 case RSET_GPIO:
296 return BCM_6345_GPIO_BASE;
297 case RSET_SPI:
298 return BCM_6345_SPI_BASE;
299 case RSET_UDC0:
300 return BCM_6345_UDC0_BASE;
301 case RSET_OHCI0:
302 return BCM_6345_OHCI0_BASE;
303 case RSET_OHCI_PRIV:
304 return BCM_6345_OHCI_PRIV_BASE;
305 case RSET_USBH_PRIV:
306 return BCM_6345_USBH_PRIV_BASE;
307 case RSET_MPI:
308 return BCM_6345_MPI_BASE;
309 case RSET_PCMCIA:
310 return BCM_6345_PCMCIA_BASE;
311 case RSET_DSL:
312 return BCM_6345_DSL_BASE;
313 case RSET_ENET0:
314 return BCM_6345_ENET0_BASE;
315 case RSET_ENET1:
316 return BCM_6345_ENET1_BASE;
317 case RSET_ENETDMA:
318 return BCM_6345_ENETDMA_BASE;
319 case RSET_EHCI0:
320 return BCM_6345_EHCI0_BASE;
321 case RSET_SDRAM:
322 return BCM_6345_SDRAM_BASE;
323 case RSET_MEMC:
324 return BCM_6345_MEMC_BASE;
325 case RSET_DDR:
326 return BCM_6345_DDR_BASE;
327 }
328#endif
329#ifdef CONFIG_BCM63XX_CPU_6348
330 switch (set) {
331 case RSET_DSL_LMEM:
332 return BCM_6348_DSL_LMEM_BASE;
333 case RSET_PERF:
334 return BCM_6348_PERF_BASE;
335 case RSET_TIMER:
336 return BCM_6348_TIMER_BASE;
337 case RSET_WDT:
338 return BCM_6348_WDT_BASE;
339 case RSET_UART0:
340 return BCM_6348_UART0_BASE;
341 case RSET_GPIO:
342 return BCM_6348_GPIO_BASE;
343 case RSET_SPI:
344 return BCM_6348_SPI_BASE;
345 case RSET_UDC0:
346 return BCM_6348_UDC0_BASE;
347 case RSET_OHCI0:
348 return BCM_6348_OHCI0_BASE;
349 case RSET_OHCI_PRIV:
350 return BCM_6348_OHCI_PRIV_BASE;
351 case RSET_USBH_PRIV:
352 return BCM_6348_USBH_PRIV_BASE;
353 case RSET_MPI:
354 return BCM_6348_MPI_BASE;
355 case RSET_PCMCIA:
356 return BCM_6348_PCMCIA_BASE;
357 case RSET_DSL:
358 return BCM_6348_DSL_BASE;
359 case RSET_ENET0:
360 return BCM_6348_ENET0_BASE;
361 case RSET_ENET1:
362 return BCM_6348_ENET1_BASE;
363 case RSET_ENETDMA:
364 return BCM_6348_ENETDMA_BASE;
365 case RSET_EHCI0:
366 return BCM_6348_EHCI0_BASE;
367 case RSET_SDRAM:
368 return BCM_6348_SDRAM_BASE;
369 case RSET_MEMC:
370 return BCM_6348_MEMC_BASE;
371 case RSET_DDR:
372 return BCM_6348_DDR_BASE;
373 }
374#endif
375#ifdef CONFIG_BCM63XX_CPU_6358
376 switch (set) {
377 case RSET_DSL_LMEM:
378 return BCM_6358_DSL_LMEM_BASE;
379 case RSET_PERF:
380 return BCM_6358_PERF_BASE;
381 case RSET_TIMER:
382 return BCM_6358_TIMER_BASE;
383 case RSET_WDT:
384 return BCM_6358_WDT_BASE;
385 case RSET_UART0:
386 return BCM_6358_UART0_BASE;
387 case RSET_GPIO:
388 return BCM_6358_GPIO_BASE;
389 case RSET_SPI:
390 return BCM_6358_SPI_BASE;
391 case RSET_UDC0:
392 return BCM_6358_UDC0_BASE;
393 case RSET_OHCI0:
394 return BCM_6358_OHCI0_BASE;
395 case RSET_OHCI_PRIV:
396 return BCM_6358_OHCI_PRIV_BASE;
397 case RSET_USBH_PRIV:
398 return BCM_6358_USBH_PRIV_BASE;
399 case RSET_MPI:
400 return BCM_6358_MPI_BASE;
401 case RSET_PCMCIA:
402 return BCM_6358_PCMCIA_BASE;
403 case RSET_ENET0:
404 return BCM_6358_ENET0_BASE;
405 case RSET_ENET1:
406 return BCM_6358_ENET1_BASE;
407 case RSET_ENETDMA:
408 return BCM_6358_ENETDMA_BASE;
409 case RSET_DSL:
410 return BCM_6358_DSL_BASE;
411 case RSET_EHCI0:
412 return BCM_6358_EHCI0_BASE;
413 case RSET_SDRAM:
414 return BCM_6358_SDRAM_BASE;
415 case RSET_MEMC:
416 return BCM_6358_MEMC_BASE;
417 case RSET_DDR:
418 return BCM_6358_DDR_BASE;
419 }
420#endif
421#endif
422 /* unreached */
423 return 0;
424}
425
426/*
427 * IRQ number changes across CPU too
428 */
429enum bcm63xx_irq {
430 IRQ_TIMER = 0,
431 IRQ_UART0,
432 IRQ_DSL,
433 IRQ_ENET0,
434 IRQ_ENET1,
435 IRQ_ENET_PHY,
436 IRQ_OHCI0,
437 IRQ_EHCI0,
438 IRQ_PCMCIA0,
439 IRQ_ENET0_RXDMA,
440 IRQ_ENET0_TXDMA,
441 IRQ_ENET1_RXDMA,
442 IRQ_ENET1_TXDMA,
443 IRQ_PCI,
444 IRQ_PCMCIA,
445};
446
447/*
448 * 6338 irqs
449 */
450#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
451#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
452#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
453#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
454#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
455#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
456#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
457#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
458#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
459#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
460#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
461#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
462#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
463#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
464#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
465#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
466#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
467
468/*
469 * 6345 irqs
470 */
471#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
472#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
473#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
474#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
475#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
476#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
477#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
478#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
479#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
480#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
481#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
482#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
483#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
484#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
485#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
486#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
487#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
488#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
489#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
490
491/*
492 * 6348 irqs
493 */
494#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
495#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
496#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
497#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
498#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
499#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
500#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
501#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
502#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
503#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
504#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
505#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
506#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
507
508/*
509 * 6358 irqs
510 */
511#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
512#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
513#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
514#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
515#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
517#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
518#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
519#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
520#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
521#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
522#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
523#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
524#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
525
526extern const int *bcm63xx_irqs;
527
528static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
529{
530 return bcm63xx_irqs[irq];
531}
532
533/*
534 * return installed memory size
535 */
536unsigned int bcm63xx_get_memory_size(void);
537
538#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
new file mode 100644
index 000000000000..b1821c866e53
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h
@@ -0,0 +1,10 @@
1#ifndef BCM63XX_CS_H
2#define BCM63XX_CS_H
3
4int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
5int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
6 unsigned int setup, unsigned int hold);
7int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
8int bcm63xx_set_cs_status(unsigned int cs, int enable);
9
10#endif /* !BCM63XX_CS_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
new file mode 100644
index 000000000000..b587d45c3045
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
@@ -0,0 +1,13 @@
1#ifndef __BCM63XX_DSP_H
2#define __BCM63XX_DSP_H
3
4struct bcm63xx_dsp_platform_data {
5 unsigned gpio_rst;
6 unsigned gpio_int;
7 unsigned cs;
8 unsigned ext_irq;
9};
10
11int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd);
12
13#endif /* __BCM63XX_DSP_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
new file mode 100644
index 000000000000..d53f611184b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -0,0 +1,45 @@
1#ifndef BCM63XX_DEV_ENET_H_
2#define BCM63XX_DEV_ENET_H_
3
4#include <linux/if_ether.h>
5#include <linux/init.h>
6
7/*
8 * on board ethernet platform data
9 */
10struct bcm63xx_enet_platform_data {
11 char mac_addr[ETH_ALEN];
12
13 int has_phy;
14
15 /* if has_phy, then set use_internal_phy */
16 int use_internal_phy;
17
18 /* or fill phy info to use an external one */
19 int phy_id;
20 int has_phy_interrupt;
21 int phy_interrupt;
22
23 /* if has_phy, use autonegociated pause parameters or force
24 * them */
25 int pause_auto;
26 int pause_rx;
27 int pause_tx;
28
29 /* if !has_phy, set desired forced speed/duplex */
30 int force_speed_100;
31 int force_duplex_full;
32
33 /* if !has_phy, set callback to perform mii device
34 * init/remove */
35 int (*mii_config)(struct net_device *dev, int probe,
36 int (*mii_read)(struct net_device *dev,
37 int phy_id, int reg),
38 void (*mii_write)(struct net_device *dev,
39 int phy_id, int reg, int val));
40};
41
42int __init bcm63xx_enet_register(int unit,
43 const struct bcm63xx_enet_platform_data *pd);
44
45#endif /* ! BCM63XX_DEV_ENET_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
new file mode 100644
index 000000000000..c549344b70ad
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h
@@ -0,0 +1,6 @@
1#ifndef BCM63XX_DEV_PCI_H_
2#define BCM63XX_DEV_PCI_H_
3
4extern int bcm63xx_pci_enabled;
5
6#endif /* BCM63XX_DEV_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
new file mode 100644
index 000000000000..76a0b7216af5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -0,0 +1,22 @@
1#ifndef BCM63XX_GPIO_H
2#define BCM63XX_GPIO_H
3
4#include <linux/init.h>
5
6int __init bcm63xx_gpio_init(void);
7
8static inline unsigned long bcm63xx_gpio_count(void)
9{
10 switch (bcm63xx_get_cpu_id()) {
11 case BCM6358_CPU_ID:
12 return 40;
13 case BCM6348_CPU_ID:
14 default:
15 return 37;
16 }
17}
18
19#define GPIO_DIR_OUT 0x0
20#define GPIO_DIR_IN 0x1
21
22#endif /* !BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
new file mode 100644
index 000000000000..91180fac6ed9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -0,0 +1,93 @@
1#ifndef BCM63XX_IO_H_
2#define BCM63XX_IO_H_
3
4#include "bcm63xx_cpu.h"
5
6/*
7 * Physical memory map, RAM is mapped at 0x0.
8 *
9 * Note that size MUST be a power of two.
10 */
11#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000)
12#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024)
13#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \
14 BCM_PCMCIA_COMMON_SIZE - 1)
15
16#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000)
17#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024)
18#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \
19 BCM_PCMCIA_ATTR_SIZE - 1)
20
21#define BCM_PCMCIA_IO_BASE_PA (0x22000000)
22#define BCM_PCMCIA_IO_SIZE (64 * 1024)
23#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \
24 BCM_PCMCIA_IO_SIZE - 1)
25
26#define BCM_PCI_MEM_BASE_PA (0x30000000)
27#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024)
28#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \
29 BCM_PCI_MEM_SIZE - 1)
30
31#define BCM_PCI_IO_BASE_PA (0x08000000)
32#define BCM_PCI_IO_SIZE (64 * 1024)
33#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \
34 BCM_PCI_IO_SIZE - 1)
35#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \
36 (BCM_PCI_IO_SIZE / 2) - 1)
37
38#define BCM_CB_MEM_BASE_PA (0x38000000)
39#define BCM_CB_MEM_SIZE (128 * 1024 * 1024)
40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
41 BCM_CB_MEM_SIZE - 1)
42
43
44/*
45 * Internal registers are accessed through KSEG3
46 */
47#define BCM_REGS_VA(x) ((void __iomem *)(x))
48
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
55
56/*
57 * IO helpers to access register set for current CPU
58 */
59#define bcm_rset_readb(s, o) bcm_readb(bcm63xx_regset_address(s) + (o))
60#define bcm_rset_readw(s, o) bcm_readw(bcm63xx_regset_address(s) + (o))
61#define bcm_rset_readl(s, o) bcm_readl(bcm63xx_regset_address(s) + (o))
62#define bcm_rset_writeb(s, v, o) bcm_writeb((v), \
63 bcm63xx_regset_address(s) + (o))
64#define bcm_rset_writew(s, v, o) bcm_writew((v), \
65 bcm63xx_regset_address(s) + (o))
66#define bcm_rset_writel(s, v, o) bcm_writel((v), \
67 bcm63xx_regset_address(s) + (o))
68
69/*
70 * helpers for frequently used register sets
71 */
72#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o))
73#define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o))
74#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o))
75#define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o))
76#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o))
77#define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o))
78#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o))
79#define bcm_gpio_writel(v, o) bcm_rset_writel(RSET_GPIO, (v), (o))
80#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o))
81#define bcm_uart0_writel(v, o) bcm_rset_writel(RSET_UART0, (v), (o))
82#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o))
83#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
84#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
85#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
86#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
87#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
88#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
89#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
90#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
91#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
92
93#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
new file mode 100644
index 000000000000..5f95577c8213
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -0,0 +1,15 @@
1#ifndef BCM63XX_IRQ_H_
2#define BCM63XX_IRQ_H_
3
4#include <bcm63xx_cpu.h>
5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8
8
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14
15#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
new file mode 100644
index 000000000000..ed4ccec87dd4
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -0,0 +1,773 @@
1#ifndef BCM63XX_REGS_H_
2#define BCM63XX_REGS_H_
3
4/*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
7
8/* Chip Identifier / Revision register */
9#define PERF_REV_REG 0x0
10#define REV_CHIPID_SHIFT 16
11#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12#define REV_REVID_SHIFT 0
13#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
14
15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4
17
18#define CKCTL_6338_ADSLPHY_EN (1 << 0)
19#define CKCTL_6338_MPI_EN (1 << 1)
20#define CKCTL_6338_DRAM_EN (1 << 2)
21#define CKCTL_6338_ENET_EN (1 << 4)
22#define CKCTL_6338_USBS_EN (1 << 4)
23#define CKCTL_6338_SAR_EN (1 << 5)
24#define CKCTL_6338_SPI_EN (1 << 9)
25
26#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
27 CKCTL_6338_MPI_EN | \
28 CKCTL_6338_ENET_EN | \
29 CKCTL_6338_SAR_EN | \
30 CKCTL_6338_SPI_EN)
31
32#define CKCTL_6345_CPU_EN (1 << 0)
33#define CKCTL_6345_BUS_EN (1 << 1)
34#define CKCTL_6345_EBI_EN (1 << 2)
35#define CKCTL_6345_UART_EN (1 << 3)
36#define CKCTL_6345_ADSLPHY_EN (1 << 4)
37#define CKCTL_6345_ENET_EN (1 << 7)
38#define CKCTL_6345_USBH_EN (1 << 8)
39
40#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
41 CKCTL_6345_USBH_EN | \
42 CKCTL_6345_ADSLPHY_EN)
43
44#define CKCTL_6348_ADSLPHY_EN (1 << 0)
45#define CKCTL_6348_MPI_EN (1 << 1)
46#define CKCTL_6348_SDRAM_EN (1 << 2)
47#define CKCTL_6348_M2M_EN (1 << 3)
48#define CKCTL_6348_ENET_EN (1 << 4)
49#define CKCTL_6348_SAR_EN (1 << 5)
50#define CKCTL_6348_USBS_EN (1 << 6)
51#define CKCTL_6348_USBH_EN (1 << 8)
52#define CKCTL_6348_SPI_EN (1 << 9)
53
54#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
55 CKCTL_6348_M2M_EN | \
56 CKCTL_6348_ENET_EN | \
57 CKCTL_6348_SAR_EN | \
58 CKCTL_6348_USBS_EN | \
59 CKCTL_6348_USBH_EN | \
60 CKCTL_6348_SPI_EN)
61
62#define CKCTL_6358_ENET_EN (1 << 4)
63#define CKCTL_6358_ADSLPHY_EN (1 << 5)
64#define CKCTL_6358_PCM_EN (1 << 8)
65#define CKCTL_6358_SPI_EN (1 << 9)
66#define CKCTL_6358_USBS_EN (1 << 10)
67#define CKCTL_6358_SAR_EN (1 << 11)
68#define CKCTL_6358_EMUSB_EN (1 << 17)
69#define CKCTL_6358_ENET0_EN (1 << 18)
70#define CKCTL_6358_ENET1_EN (1 << 19)
71#define CKCTL_6358_USBSU_EN (1 << 20)
72#define CKCTL_6358_EPHY_EN (1 << 21)
73
74#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
75 CKCTL_6358_ADSLPHY_EN | \
76 CKCTL_6358_PCM_EN | \
77 CKCTL_6358_SPI_EN | \
78 CKCTL_6358_USBS_EN | \
79 CKCTL_6358_SAR_EN | \
80 CKCTL_6358_EMUSB_EN | \
81 CKCTL_6358_ENET0_EN | \
82 CKCTL_6358_ENET1_EN | \
83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN)
85
86/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1
89
90/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc
92#define PERF_IRQSTAT_REG 0x10
93
94/* Interrupt Status register */
95#define PERF_IRQSTAT_REG 0x10
96
97/* External Interrupt Configuration register */
98#define PERF_EXTIRQ_CFG_REG 0x14
99#define EXTIRQ_CFG_SENSE(x) (1 << (x))
100#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
101#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
102#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
103#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
104#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
105
106#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
107#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
108
109/* Soft Reset register */
110#define PERF_SOFTRESET_REG 0x28
111
112#define SOFTRESET_6338_SPI_MASK (1 << 0)
113#define SOFTRESET_6338_ENET_MASK (1 << 2)
114#define SOFTRESET_6338_USBH_MASK (1 << 3)
115#define SOFTRESET_6338_USBS_MASK (1 << 4)
116#define SOFTRESET_6338_ADSL_MASK (1 << 5)
117#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
118#define SOFTRESET_6338_SAR_MASK (1 << 7)
119#define SOFTRESET_6338_ACLC_MASK (1 << 8)
120#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
121#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
122 SOFTRESET_6338_ENET_MASK | \
123 SOFTRESET_6338_USBH_MASK | \
124 SOFTRESET_6338_USBS_MASK | \
125 SOFTRESET_6338_ADSL_MASK | \
126 SOFTRESET_6338_DMAMEM_MASK | \
127 SOFTRESET_6338_SAR_MASK | \
128 SOFTRESET_6338_ACLC_MASK | \
129 SOFTRESET_6338_ADSLMIPSPLL_MASK)
130
131#define SOFTRESET_6348_SPI_MASK (1 << 0)
132#define SOFTRESET_6348_ENET_MASK (1 << 2)
133#define SOFTRESET_6348_USBH_MASK (1 << 3)
134#define SOFTRESET_6348_USBS_MASK (1 << 4)
135#define SOFTRESET_6348_ADSL_MASK (1 << 5)
136#define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
137#define SOFTRESET_6348_SAR_MASK (1 << 7)
138#define SOFTRESET_6348_ACLC_MASK (1 << 8)
139#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
140
141#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
142 SOFTRESET_6348_ENET_MASK | \
143 SOFTRESET_6348_USBH_MASK | \
144 SOFTRESET_6348_USBS_MASK | \
145 SOFTRESET_6348_ADSL_MASK | \
146 SOFTRESET_6348_DMAMEM_MASK | \
147 SOFTRESET_6348_SAR_MASK | \
148 SOFTRESET_6348_ACLC_MASK | \
149 SOFTRESET_6348_ADSLMIPSPLL_MASK)
150
151/* MIPS PLL control register */
152#define PERF_MIPSPLLCTL_REG 0x34
153#define MIPSPLLCTL_N1_SHIFT 20
154#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
155#define MIPSPLLCTL_N2_SHIFT 15
156#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
157#define MIPSPLLCTL_M1REF_SHIFT 12
158#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
159#define MIPSPLLCTL_M2REF_SHIFT 9
160#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
161#define MIPSPLLCTL_M1CPU_SHIFT 6
162#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
163#define MIPSPLLCTL_M1BUS_SHIFT 3
164#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
165#define MIPSPLLCTL_M2BUS_SHIFT 0
166#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
167
168/* ADSL PHY PLL Control register */
169#define PERF_ADSLPLLCTL_REG 0x38
170#define ADSLPLLCTL_N1_SHIFT 20
171#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
172#define ADSLPLLCTL_N2_SHIFT 15
173#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
174#define ADSLPLLCTL_M1REF_SHIFT 12
175#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
176#define ADSLPLLCTL_M2REF_SHIFT 9
177#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
178#define ADSLPLLCTL_M1CPU_SHIFT 6
179#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
180#define ADSLPLLCTL_M1BUS_SHIFT 3
181#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
182#define ADSLPLLCTL_M2BUS_SHIFT 0
183#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
184
185#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
186 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
187 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
188 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
189 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
190 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
191 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
192 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
193
194
195/*************************************************************************
196 * _REG relative to RSET_TIMER
197 *************************************************************************/
198
199#define BCM63XX_TIMER_COUNT 4
200#define TIMER_T0_ID 0
201#define TIMER_T1_ID 1
202#define TIMER_T2_ID 2
203#define TIMER_WDT_ID 3
204
205/* Timer irqstat register */
206#define TIMER_IRQSTAT_REG 0
207#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
208#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
209#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
210#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
211#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
212#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
213#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
214#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
215#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
216
217/* Timer control register */
218#define TIMER_CTLx_REG(x) (0x4 + (x * 4))
219#define TIMER_CTL0_REG 0x4
220#define TIMER_CTL1_REG 0x8
221#define TIMER_CTL2_REG 0xC
222#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
223#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
224#define TIMER_CTL_ENABLE_MASK (1 << 31)
225
226
227/*************************************************************************
228 * _REG relative to RSET_WDT
229 *************************************************************************/
230
231/* Watchdog default count register */
232#define WDT_DEFVAL_REG 0x0
233
234/* Watchdog control register */
235#define WDT_CTL_REG 0x4
236
237/* Watchdog control register constants */
238#define WDT_START_1 (0xff00)
239#define WDT_START_2 (0x00ff)
240#define WDT_STOP_1 (0xee00)
241#define WDT_STOP_2 (0x00ee)
242
243/* Watchdog reset length register */
244#define WDT_RSTLEN_REG 0x8
245
246
247/*************************************************************************
248 * _REG relative to RSET_UARTx
249 *************************************************************************/
250
251/* UART Control Register */
252#define UART_CTL_REG 0x0
253#define UART_CTL_RXTMOUTCNT_SHIFT 0
254#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
255#define UART_CTL_RSTTXDN_SHIFT 5
256#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
257#define UART_CTL_RSTRXFIFO_SHIFT 6
258#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
259#define UART_CTL_RSTTXFIFO_SHIFT 7
260#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
261#define UART_CTL_STOPBITS_SHIFT 8
262#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
263#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
264#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
265#define UART_CTL_BITSPERSYM_SHIFT 12
266#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
267#define UART_CTL_XMITBRK_SHIFT 14
268#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
269#define UART_CTL_RSVD_SHIFT 15
270#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
271#define UART_CTL_RXPAREVEN_SHIFT 16
272#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
273#define UART_CTL_RXPAREN_SHIFT 17
274#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
275#define UART_CTL_TXPAREVEN_SHIFT 18
276#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
277#define UART_CTL_TXPAREN_SHIFT 18
278#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
279#define UART_CTL_LOOPBACK_SHIFT 20
280#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
281#define UART_CTL_RXEN_SHIFT 21
282#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
283#define UART_CTL_TXEN_SHIFT 22
284#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
285#define UART_CTL_BRGEN_SHIFT 23
286#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
287
288/* UART Baudword register */
289#define UART_BAUD_REG 0x4
290
291/* UART Misc Control register */
292#define UART_MCTL_REG 0x8
293#define UART_MCTL_DTR_SHIFT 0
294#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
295#define UART_MCTL_RTS_SHIFT 1
296#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
297#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
298#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
299#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
300#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
301#define UART_MCTL_RXFIFOFILL_SHIFT 16
302#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
303#define UART_MCTL_TXFIFOFILL_SHIFT 24
304#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
305
306/* UART External Input Configuration register */
307#define UART_EXTINP_REG 0xc
308#define UART_EXTINP_RI_SHIFT 0
309#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
310#define UART_EXTINP_CTS_SHIFT 1
311#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
312#define UART_EXTINP_DCD_SHIFT 2
313#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
314#define UART_EXTINP_DSR_SHIFT 3
315#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
316#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
317#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
318#define UART_EXTINP_IR_RI 0
319#define UART_EXTINP_IR_CTS 1
320#define UART_EXTINP_IR_DCD 2
321#define UART_EXTINP_IR_DSR 3
322#define UART_EXTINP_RI_NOSENSE_SHIFT 16
323#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
324#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
325#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
326#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
327#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
328#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
329#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
330
331/* UART Interrupt register */
332#define UART_IR_REG 0x10
333#define UART_IR_MASK(x) (1 << (x + 16))
334#define UART_IR_STAT(x) (1 << (x))
335#define UART_IR_EXTIP 0
336#define UART_IR_TXUNDER 1
337#define UART_IR_TXOVER 2
338#define UART_IR_TXTRESH 3
339#define UART_IR_TXRDLATCH 4
340#define UART_IR_TXEMPTY 5
341#define UART_IR_RXUNDER 6
342#define UART_IR_RXOVER 7
343#define UART_IR_RXTIMEOUT 8
344#define UART_IR_RXFULL 9
345#define UART_IR_RXTHRESH 10
346#define UART_IR_RXNOTEMPTY 11
347#define UART_IR_RXFRAMEERR 12
348#define UART_IR_RXPARERR 13
349#define UART_IR_RXBRK 14
350#define UART_IR_TXDONE 15
351
352/* UART Fifo register */
353#define UART_FIFO_REG 0x14
354#define UART_FIFO_VALID_SHIFT 0
355#define UART_FIFO_VALID_MASK 0xff
356#define UART_FIFO_FRAMEERR_SHIFT 8
357#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
358#define UART_FIFO_PARERR_SHIFT 9
359#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
360#define UART_FIFO_BRKDET_SHIFT 10
361#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
362#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
363 UART_FIFO_PARERR_MASK | \
364 UART_FIFO_BRKDET_MASK)
365
366
367/*************************************************************************
368 * _REG relative to RSET_GPIO
369 *************************************************************************/
370
371/* GPIO registers */
372#define GPIO_CTL_HI_REG 0x0
373#define GPIO_CTL_LO_REG 0x4
374#define GPIO_DATA_HI_REG 0x8
375#define GPIO_DATA_LO_REG 0xC
376
377/* GPIO mux registers and constants */
378#define GPIO_MODE_REG 0x18
379
380#define GPIO_MODE_6348_G4_DIAG 0x00090000
381#define GPIO_MODE_6348_G4_UTOPIA 0x00080000
382#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
383#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
384#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
385#define GPIO_MODE_6348_G3_DIAG 0x00009000
386#define GPIO_MODE_6348_G3_UTOPIA 0x00008000
387#define GPIO_MODE_6348_G3_EXT_MII 0x00007000
388#define GPIO_MODE_6348_G2_DIAG 0x00000900
389#define GPIO_MODE_6348_G2_PCI 0x00000500
390#define GPIO_MODE_6348_G1_DIAG 0x00000090
391#define GPIO_MODE_6348_G1_UTOPIA 0x00000080
392#define GPIO_MODE_6348_G1_SPI_UART 0x00000060
393#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
394#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
395#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
396#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
397#define GPIO_MODE_6348_G0_DIAG 0x00000009
398#define GPIO_MODE_6348_G0_EXT_MII 0x00000007
399
400#define GPIO_MODE_6358_EXTRACS (1 << 5)
401#define GPIO_MODE_6358_UART1 (1 << 6)
402#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
403#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
404#define GPIO_MODE_6358_UTOPIA (1 << 12)
405
406
407/*************************************************************************
408 * _REG relative to RSET_ENET
409 *************************************************************************/
410
411/* Receiver Configuration register */
412#define ENET_RXCFG_REG 0x0
413#define ENET_RXCFG_ALLMCAST_SHIFT 1
414#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
415#define ENET_RXCFG_PROMISC_SHIFT 3
416#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
417#define ENET_RXCFG_LOOPBACK_SHIFT 4
418#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
419#define ENET_RXCFG_ENFLOW_SHIFT 5
420#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
421
422/* Receive Maximum Length register */
423#define ENET_RXMAXLEN_REG 0x4
424#define ENET_RXMAXLEN_SHIFT 0
425#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
426
427/* Transmit Maximum Length register */
428#define ENET_TXMAXLEN_REG 0x8
429#define ENET_TXMAXLEN_SHIFT 0
430#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
431
432/* MII Status/Control register */
433#define ENET_MIISC_REG 0x10
434#define ENET_MIISC_MDCFREQDIV_SHIFT 0
435#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
436#define ENET_MIISC_PREAMBLEEN_SHIFT 7
437#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
438
439/* MII Data register */
440#define ENET_MIIDATA_REG 0x14
441#define ENET_MIIDATA_DATA_SHIFT 0
442#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
443#define ENET_MIIDATA_TA_SHIFT 16
444#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
445#define ENET_MIIDATA_REG_SHIFT 18
446#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
447#define ENET_MIIDATA_PHYID_SHIFT 23
448#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
449#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
450#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
451
452/* Ethernet Interrupt Mask register */
453#define ENET_IRMASK_REG 0x18
454
455/* Ethernet Interrupt register */
456#define ENET_IR_REG 0x1c
457#define ENET_IR_MII (1 << 0)
458#define ENET_IR_MIB (1 << 1)
459#define ENET_IR_FLOWC (1 << 2)
460
461/* Ethernet Control register */
462#define ENET_CTL_REG 0x2c
463#define ENET_CTL_ENABLE_SHIFT 0
464#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
465#define ENET_CTL_DISABLE_SHIFT 1
466#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
467#define ENET_CTL_SRESET_SHIFT 2
468#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
469#define ENET_CTL_EPHYSEL_SHIFT 3
470#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
471
472/* Transmit Control register */
473#define ENET_TXCTL_REG 0x30
474#define ENET_TXCTL_FD_SHIFT 0
475#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
476
477/* Transmit Watermask register */
478#define ENET_TXWMARK_REG 0x34
479#define ENET_TXWMARK_WM_SHIFT 0
480#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
481
482/* MIB Control register */
483#define ENET_MIBCTL_REG 0x38
484#define ENET_MIBCTL_RDCLEAR_SHIFT 0
485#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
486
487/* Perfect Match Data Low register */
488#define ENET_PML_REG(x) (0x58 + (x) * 8)
489#define ENET_PMH_REG(x) (0x5c + (x) * 8)
490#define ENET_PMH_DATAVALID_SHIFT 16
491#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
492
493/* MIB register */
494#define ENET_MIB_REG(x) (0x200 + (x) * 4)
495#define ENET_MIB_REG_COUNT 55
496
497
498/*************************************************************************
499 * _REG relative to RSET_ENETDMA
500 *************************************************************************/
501
502/* Controller Configuration Register */
503#define ENETDMA_CFG_REG (0x0)
504#define ENETDMA_CFG_EN_SHIFT 0
505#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
506#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
507
508/* Flow Control Descriptor Low Threshold register */
509#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
510
511/* Flow Control Descriptor High Threshold register */
512#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
513
514/* Flow Control Descriptor Buffer Alloca Threshold register */
515#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
516#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
517#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
518
519/* Channel Configuration register */
520#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
521#define ENETDMA_CHANCFG_EN_SHIFT 0
522#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
523#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
524#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
525
526/* Interrupt Control/Status register */
527#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
528#define ENETDMA_IR_BUFDONE_MASK (1 << 0)
529#define ENETDMA_IR_PKTDONE_MASK (1 << 1)
530#define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
531
532/* Interrupt Mask register */
533#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
534
535/* Maximum Burst Length */
536#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
537
538/* Ring Start Address register */
539#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
540
541/* State Ram Word 2 */
542#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
543
544/* State Ram Word 3 */
545#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
546
547/* State Ram Word 4 */
548#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
549
550
551/*************************************************************************
552 * _REG relative to RSET_OHCI_PRIV
553 *************************************************************************/
554
555#define OHCI_PRIV_REG 0x0
556#define OHCI_PRIV_PORT1_HOST_SHIFT 0
557#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
558#define OHCI_PRIV_REG_SWAP_SHIFT 3
559#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
560
561
562/*************************************************************************
563 * _REG relative to RSET_USBH_PRIV
564 *************************************************************************/
565
566#define USBH_PRIV_SWAP_REG 0x0
567#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
568#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
569#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
570#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
571#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
572#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
573#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
574#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
575
576#define USBH_PRIV_TEST_REG 0x24
577
578
579/*************************************************************************
580 * _REG relative to RSET_MPI
581 *************************************************************************/
582
583/* well known (hard wired) chip select */
584#define MPI_CS_PCMCIA_COMMON 4
585#define MPI_CS_PCMCIA_ATTR 5
586#define MPI_CS_PCMCIA_IO 6
587
588/* Chip select base register */
589#define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
590#define MPI_CSBASE_BASE_SHIFT 13
591#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
592#define MPI_CSBASE_SIZE_SHIFT 0
593#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
594
595#define MPI_CSBASE_SIZE_8K 0
596#define MPI_CSBASE_SIZE_16K 1
597#define MPI_CSBASE_SIZE_32K 2
598#define MPI_CSBASE_SIZE_64K 3
599#define MPI_CSBASE_SIZE_128K 4
600#define MPI_CSBASE_SIZE_256K 5
601#define MPI_CSBASE_SIZE_512K 6
602#define MPI_CSBASE_SIZE_1M 7
603#define MPI_CSBASE_SIZE_2M 8
604#define MPI_CSBASE_SIZE_4M 9
605#define MPI_CSBASE_SIZE_8M 10
606#define MPI_CSBASE_SIZE_16M 11
607#define MPI_CSBASE_SIZE_32M 12
608#define MPI_CSBASE_SIZE_64M 13
609#define MPI_CSBASE_SIZE_128M 14
610#define MPI_CSBASE_SIZE_256M 15
611
612/* Chip select control register */
613#define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
614#define MPI_CSCTL_ENABLE_MASK (1 << 0)
615#define MPI_CSCTL_WAIT_SHIFT 1
616#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
617#define MPI_CSCTL_DATA16_MASK (1 << 4)
618#define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
619#define MPI_CSCTL_TSIZE_MASK (1 << 8)
620#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
621#define MPI_CSCTL_SETUP_SHIFT 16
622#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
623#define MPI_CSCTL_HOLD_SHIFT 20
624#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
625
626/* PCI registers */
627#define MPI_SP0_RANGE_REG 0x100
628#define MPI_SP0_REMAP_REG 0x104
629#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
630#define MPI_SP1_RANGE_REG 0x10C
631#define MPI_SP1_REMAP_REG 0x110
632#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
633
634#define MPI_L2PCFG_REG 0x11C
635#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
636#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
637#define MPI_L2PCFG_REG_SHIFT 2
638#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
639#define MPI_L2PCFG_FUNC_SHIFT 8
640#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
641#define MPI_L2PCFG_DEVNUM_SHIFT 11
642#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
643#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
644#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
645
646#define MPI_L2PMEMRANGE1_REG 0x120
647#define MPI_L2PMEMBASE1_REG 0x124
648#define MPI_L2PMEMREMAP1_REG 0x128
649#define MPI_L2PMEMRANGE2_REG 0x12C
650#define MPI_L2PMEMBASE2_REG 0x130
651#define MPI_L2PMEMREMAP2_REG 0x134
652#define MPI_L2PIORANGE_REG 0x138
653#define MPI_L2PIOBASE_REG 0x13C
654#define MPI_L2PIOREMAP_REG 0x140
655#define MPI_L2P_BASE_MASK (0xffff8000)
656#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
657#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
658
659#define MPI_PCIMODESEL_REG 0x144
660#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
661#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
662#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
663#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
664#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
665
666#define MPI_LOCBUSCTL_REG 0x14C
667#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
668#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
669
670#define MPI_LOCINT_REG 0x150
671#define MPI_LOCINT_MASK(x) (1 << (x + 16))
672#define MPI_LOCINT_STAT(x) (1 << (x))
673#define MPI_LOCINT_DIR_FAILED 6
674#define MPI_LOCINT_EXT_PCI_INT 7
675#define MPI_LOCINT_SERR 8
676#define MPI_LOCINT_CSERR 9
677
678#define MPI_PCICFGCTL_REG 0x178
679#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
680#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
681#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
682
683#define MPI_PCICFGDATA_REG 0x17C
684
685/* PCI host bridge custom register */
686#define BCMPCI_REG_TIMERS 0x40
687#define REG_TIMER_TRDY_SHIFT 0
688#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
689#define REG_TIMER_RETRY_SHIFT 8
690#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
691
692
693/*************************************************************************
694 * _REG relative to RSET_PCMCIA
695 *************************************************************************/
696
697#define PCMCIA_C1_REG 0x0
698#define PCMCIA_C1_CD1_MASK (1 << 0)
699#define PCMCIA_C1_CD2_MASK (1 << 1)
700#define PCMCIA_C1_VS1_MASK (1 << 2)
701#define PCMCIA_C1_VS2_MASK (1 << 3)
702#define PCMCIA_C1_VS1OE_MASK (1 << 6)
703#define PCMCIA_C1_VS2OE_MASK (1 << 7)
704#define PCMCIA_C1_CBIDSEL_SHIFT (8)
705#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
706#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
707#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
708#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
709#define PCMCIA_C1_RESET_MASK (1 << 18)
710
711#define PCMCIA_C2_REG 0x8
712#define PCMCIA_C2_DATA16_MASK (1 << 0)
713#define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
714#define PCMCIA_C2_RWCOUNT_SHIFT 2
715#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
716#define PCMCIA_C2_INACTIVE_SHIFT 8
717#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
718#define PCMCIA_C2_SETUP_SHIFT 16
719#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
720#define PCMCIA_C2_HOLD_SHIFT 24
721#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
722
723
724/*************************************************************************
725 * _REG relative to RSET_SDRAM
726 *************************************************************************/
727
728#define SDRAM_CFG_REG 0x0
729#define SDRAM_CFG_ROW_SHIFT 4
730#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
731#define SDRAM_CFG_COL_SHIFT 6
732#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
733#define SDRAM_CFG_32B_SHIFT 10
734#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
735#define SDRAM_CFG_BANK_SHIFT 13
736#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
737
738#define SDRAM_PRIO_REG 0x2C
739#define SDRAM_PRIO_MIPS_SHIFT 29
740#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
741#define SDRAM_PRIO_ADSL_SHIFT 30
742#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
743#define SDRAM_PRIO_EN_SHIFT 31
744#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
745
746
747/*************************************************************************
748 * _REG relative to RSET_MEMC
749 *************************************************************************/
750
751#define MEMC_CFG_REG 0x4
752#define MEMC_CFG_32B_SHIFT 1
753#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
754#define MEMC_CFG_COL_SHIFT 3
755#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
756#define MEMC_CFG_ROW_SHIFT 6
757#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
758
759
760/*************************************************************************
761 * _REG relative to RSET_DDR
762 *************************************************************************/
763
764#define DDR_DMIPSPLLCFG_REG 0x18
765#define DMIPSPLLCFG_M1_SHIFT 0
766#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
767#define DMIPSPLLCFG_N1_SHIFT 23
768#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
769#define DMIPSPLLCFG_N2_SHIFT 29
770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
771
772#endif /* BCM63XX_REGS_H_ */
773
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
new file mode 100644
index 000000000000..c0fce833c9ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h
@@ -0,0 +1,11 @@
1#ifndef BCM63XX_TIMER_H_
2#define BCM63XX_TIMER_H_
3
4int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
5void bcm63xx_timer_unregister(int id);
6int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
7int bcm63xx_timer_enable(int id);
8int bcm63xx_timer_disable(int id);
9unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
10
11#endif /* !BCM63XX_TIMER_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
new file mode 100644
index 000000000000..6479090a4106
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -0,0 +1,60 @@
1#ifndef BOARD_BCM963XX_H_
2#define BOARD_BCM963XX_H_
3
4#include <linux/types.h>
5#include <linux/gpio.h>
6#include <linux/leds.h>
7#include <bcm63xx_dev_enet.h>
8#include <bcm63xx_dev_dsp.h>
9
10/*
11 * flash mapping
12 */
13#define BCM963XX_CFE_VERSION_OFFSET 0x570
14#define BCM963XX_NVRAM_OFFSET 0x580
15
16/*
17 * nvram structure
18 */
19struct bcm963xx_nvram {
20 u32 version;
21 u8 reserved1[256];
22 u8 name[16];
23 u32 main_tp_number;
24 u32 psi_size;
25 u32 mac_addr_count;
26 u8 mac_addr_base[6];
27 u8 reserved2[2];
28 u32 checksum_old;
29 u8 reserved3[720];
30 u32 checksum_high;
31};
32
33/*
34 * board definition
35 */
36struct board_info {
37 u8 name[16];
38 unsigned int expected_cpu_id;
39
40 /* enabled feature/device */
41 unsigned int has_enet0:1;
42 unsigned int has_enet1:1;
43 unsigned int has_pci:1;
44 unsigned int has_pccard:1;
45 unsigned int has_ohci0:1;
46 unsigned int has_ehci0:1;
47 unsigned int has_dsp:1;
48
49 /* ethernet config */
50 struct bcm63xx_enet_platform_data enet0;
51 struct bcm63xx_enet_platform_data enet1;
52
53 /* DSP config */
54 struct bcm63xx_dsp_platform_data dsp;
55
56 /* GPIO LEDs */
57 struct gpio_led leds[5];
58};
59
60#endif /* ! BOARD_BCM963XX_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..71742bac940d
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
1#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
3
4#include <bcm63xx_cpu.h>
5
6#define cpu_has_tlb 1
7#define cpu_has_4kex 1
8#define cpu_has_4k_cache 1
9#define cpu_has_fpu 0
10#define cpu_has_32fpr 0
11#define cpu_has_counter 1
12#define cpu_has_watch 0
13#define cpu_has_divec 1
14#define cpu_has_vce 0
15#define cpu_has_cache_cdex_p 0
16#define cpu_has_cache_cdex_s 0
17#define cpu_has_prefetch 1
18#define cpu_has_mcheck 1
19#define cpu_has_ejtag 1
20#define cpu_has_llsc 1
21#define cpu_has_mips16 0
22#define cpu_has_mdmx 0
23#define cpu_has_mips3d 0
24#define cpu_has_smartmips 0
25#define cpu_has_vtag_icache 0
26
27#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345))
28#define cpu_has_dc_aliases 0
29#endif
30
31#define cpu_has_ic_fills_f_dc 0
32#define cpu_has_pindexed_dcache 0
33
34#define cpu_has_mips32r1 1
35#define cpu_has_mips32r2 0
36#define cpu_has_mips64r1 0
37#define cpu_has_mips64r2 0
38
39#define cpu_has_dsp 0
40#define cpu_has_mipsmt 0
41#define cpu_has_userlocal 0
42
43#define cpu_has_nofpuex 0
44#define cpu_has_64bits 0
45#define cpu_has_64bit_zero_reg 0
46
47#define cpu_dcache_line_size() 16
48#define cpu_icache_line_size() 16
49#define cpu_scache_line_size() 0
50
51#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/gpio.h b/arch/mips/include/asm/mach-bcm63xx/gpio.h
new file mode 100644
index 000000000000..7cda8c0a3979
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/gpio.h
@@ -0,0 +1,15 @@
1#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
2#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
3
4#include <bcm63xx_gpio.h>
5
6#define gpio_to_irq(gpio) NULL
7
8#define gpio_get_value __gpio_get_value
9#define gpio_set_value __gpio_set_value
10
11#define gpio_cansleep __gpio_cansleep
12
13#include <asm-generic/gpio.h>
14
15#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
new file mode 100644
index 000000000000..8e3f3fdf3209
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
9#define __ASM_MIPS_MACH_BCM63XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 3d830756b13a..425e708d4fb9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -31,12 +31,16 @@
31#define cpu_has_cache_cdex_s 0 31#define cpu_has_cache_cdex_s 0
32#define cpu_has_prefetch 1 32#define cpu_has_prefetch 1
33 33
34#define cpu_has_llsc 1
34/* 35/*
35 * We should disable LL/SC on non SMP systems as it is faster to 36 * We Disable LL/SC on non SMP systems as it is faster to disable
36 * disable interrupts for atomic access than a LL/SC. Unfortunatly we 37 * interrupts for atomic access than a LL/SC.
37 * cannot as this breaks asm/futex.h
38 */ 38 */
39#define cpu_has_llsc 1 39#ifdef CONFIG_SMP
40# define kernel_uses_llsc 1
41#else
42# define kernel_uses_llsc 0
43#endif
40#define cpu_has_vtag_icache 1 44#define cpu_has_vtag_icache 1
41#define cpu_has_dc_aliases 0 45#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0 46#define cpu_has_ic_fills_f_dc 0
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 07547231e078..230591707005 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -48,7 +48,6 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
48 .cache_nice_tries = 1, \ 48 .cache_nice_tries = 1, \
49 .flags = SD_LOAD_BALANCE \ 49 .flags = SD_LOAD_BALANCE \
50 | SD_BALANCE_EXEC \ 50 | SD_BALANCE_EXEC \
51 | SD_WAKE_BALANCE, \
52 .last_balance = jiffies, \ 51 .last_balance = jiffies, \
53 .balance_interval = 1, \ 52 .balance_interval = 1, \
54 .nr_balance_failed = 0, \ 53 .nr_balance_failed = 0, \
diff --git a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 550a10dc9dba..ce5b6e270e3f 100644
--- a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -13,8 +13,8 @@
13 * loongson2f user manual. 13 * loongson2f user manual.
14 */ 14 */
15 15
16#ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H 16#ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
17#define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H 17#define __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
18 18
19#define cpu_dcache_line_size() 32 19#define cpu_dcache_line_size() 32
20#define cpu_icache_line_size() 32 20#define cpu_icache_line_size() 32
@@ -56,4 +56,4 @@
56#define cpu_has_watch 1 56#define cpu_has_watch 1
57#define cpu_icache_snoops_remote_store 1 57#define cpu_icache_snoops_remote_store 1
58 58
59#endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */ 59#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index c8de5e750777..71a6851ba833 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -8,8 +8,8 @@
8 * Author: Fuxin Zhang, zhangfx@lemote.com 8 * Author: Fuxin Zhang, zhangfx@lemote.com
9 * 9 *
10 */ 10 */
11#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H 11#ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H
12#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H 12#define __ASM_MACH_LOONGSON_DMA_COHERENCE_H
13 13
14struct device; 14struct device;
15 15
@@ -65,4 +65,4 @@ static inline int plat_device_is_coherent(struct device *dev)
65 return 0; 65 return 0;
66} 66}
67 67
68#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */ 68#endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
new file mode 100644
index 000000000000..da70bcf2304e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 */
11
12#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
13#define __ASM_MACH_LOONGSON_LOONGSON_H
14
15#include <linux/io.h>
16#include <linux/init.h>
17
18/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19#include <asm/mips-boards/bonito64.h>
20
21/* loongson internal northbridge initialization */
22extern void bonito_irq_init(void);
23
24/* machine-specific reboot/halt operation */
25extern void mach_prepare_reboot(void);
26extern void mach_prepare_shutdown(void);
27
28/* environment arguments from bootloader */
29extern unsigned long bus_clock, cpu_clock_freq;
30extern unsigned long memsize, highmemsize;
31
32/* loongson-specific command line, env and memory initialization */
33extern void __init prom_init_memory(void);
34extern void __init prom_init_cmdline(void);
35extern void __init prom_init_env(void);
36
37/* irq operation functions */
38extern void bonito_irqdispatch(void);
39extern void __init bonito_irq_init(void);
40extern void __init set_irq_trigger_mode(void);
41extern void __init mach_init_irq(void);
42extern void mach_irq_dispatch(unsigned int pending);
43
44/* PCI Configuration Registers */
45#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c)
46
47/* PCI_Hit*_Sel_* */
48
49#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50)
50#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54)
51#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58)
52#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c)
53#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60)
54#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64)
55
56/* PXArb Config & Status */
57
58#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68)
59#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c)
60
61/* loongson2-specific perf counter IRQ */
62#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
63
64#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
new file mode 100644
index 000000000000..206ea2067916
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __ASM_MACH_LOONGSON_MACHINE_H
12#define __ASM_MACH_LOONGSON_MACHINE_H
13
14#ifdef CONFIG_LEMOTE_FULOONG2E
15
16#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
17
18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
19
20#endif
21
22#endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-lemote/mc146818rtc.h b/arch/mips/include/asm/mach-loongson/mc146818rtc.h
index ed5147e11085..ed7fe978335a 100644
--- a/arch/mips/include/asm/mach-lemote/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-loongson/mc146818rtc.h
@@ -7,8 +7,8 @@
7 * 7 *
8 * RTC routines for PC style attached Dallas chip. 8 * RTC routines for PC style attached Dallas chip.
9 */ 9 */
10#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H 10#ifndef __ASM_MACH_LOONGSON_MC146818RTC_H
11#define __ASM_MACH_LEMOTE_MC146818RTC_H 11#define __ASM_MACH_LOONGSON_MC146818RTC_H
12 12
13#include <linux/io.h> 13#include <linux/io.h>
14 14
@@ -33,4 +33,4 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
33#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) 33#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
34#endif 34#endif
35 35
36#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */ 36#endif /* __ASM_MACH_LOONGSON_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
new file mode 100644
index 000000000000..bd7b3cba7e35
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __ASM_MACH_LOONGSON_MEM_H
12#define __ASM_MACH_LOONGSON_MEM_H
13
14/*
15 * On Lemote Loongson 2e
16 *
17 * the high memory space starts from 512M.
18 * the peripheral registers reside between 0x1000:0000 and 0x2000:0000.
19 */
20
21#ifdef CONFIG_LEMOTE_FULOONG2E
22
23#define LOONGSON_HIGHMEM_START 0x20000000
24
25#define LOONGSON_MMIO_MEM_START 0x10000000
26#define LOONGSON_MMIO_MEM_END 0x20000000
27
28#endif
29
30#endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index ea6aa143b78e..f1663ca81da0 100644
--- a/arch/mips/include/asm/mach-lemote/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -19,12 +19,19 @@
19 * 02139, USA. 19 * 02139, USA.
20 */ 20 */
21 21
22#ifndef _LEMOTE_PCI_H_ 22#ifndef __ASM_MACH_LOONGSON_PCI_H_
23#define _LEMOTE_PCI_H_ 23#define __ASM_MACH_LOONGSON_PCI_H_
24 24
25#define LOONGSON2E_PCI_MEM_START 0x14000000UL 25extern struct pci_ops bonito64_pci_ops;
26#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL
27#define LOONGSON2E_PCI_IO_START 0x00004000UL
28#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL
29 26
30#endif /* !_LEMOTE_PCI_H_ */ 27#ifdef CONFIG_LEMOTE_FULOONG2E
28
29/* this pci memory space is mapped by pcimap in pci.c */
30#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE
31#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2)
32/* this is an offset from mips_io_port_base */
33#define LOONGSON_PCI_IO_START 0x00004000UL
34
35#endif
36
37#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-lemote/war.h b/arch/mips/include/asm/mach-loongson/war.h
index 05f89e0f2a11..4b971c3ffd8d 100644
--- a/arch/mips/include/asm/mach-lemote/war.h
+++ b/arch/mips/include/asm/mach-loongson/war.h
@@ -5,8 +5,8 @@
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */ 7 */
8#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H 8#ifndef __ASM_MACH_LOONGSON_WAR_H
9#define __ASM_MIPS_MACH_LEMOTE_WAR_H 9#define __ASM_MACH_LOONGSON_WAR_H
10 10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 12#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -22,4 +22,4 @@
22#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
24 24
25#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ 25#endif /* __ASM_MACH_LEMOTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
index 7f3e3f9bd23a..2848cea42bce 100644
--- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
@@ -28,11 +28,7 @@
28/* #define cpu_has_prefetch ? */ 28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1 29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */ 30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_HAS_LLSC
32#define cpu_has_llsc 1 31#define cpu_has_llsc 1
33#else
34#define cpu_has_llsc 0
35#endif
36/* #define cpu_has_vtag_icache ? */ 32/* #define cpu_has_vtag_icache ? */
37/* #define cpu_has_dc_aliases ? */ 33/* #define cpu_has_dc_aliases ? */
38/* #define cpu_has_ic_fills_f_dc ? */ 34/* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a0f04bb99c99..a576ce044c3c 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,7 +26,7 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#elif defined(CONFIG_LEMOTE_FULONG) 29#elif defined(CONFIG_LEMOTE_FULOONG2E)
30 30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) 31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32 32#define BONITO_IRQ_BASE 32
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index c0da1a881e3d..46c08563e532 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -87,8 +87,6 @@
87 87
88extern int mips_revision_sconid; 88extern int mips_revision_sconid;
89 89
90extern void mips_reboot_setup(void);
91
92#ifdef CONFIG_PCI 90#ifdef CONFIG_PCI
93extern void mips_pcibios_init(void); 91extern void mips_pcibios_init(void);
94#else 92#else
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
new file mode 100644
index 000000000000..4586958c97be
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -0,0 +1,88 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_RNM_DEFS_H__
29#define __CVMX_RNM_DEFS_H__
30
31#include <linux/types.h>
32
33#define CVMX_RNM_BIST_STATUS \
34 CVMX_ADD_IO_SEG(0x0001180040000008ull)
35#define CVMX_RNM_CTL_STATUS \
36 CVMX_ADD_IO_SEG(0x0001180040000000ull)
37
38union cvmx_rnm_bist_status {
39 uint64_t u64;
40 struct cvmx_rnm_bist_status_s {
41 uint64_t reserved_2_63:62;
42 uint64_t rrc:1;
43 uint64_t mem:1;
44 } s;
45 struct cvmx_rnm_bist_status_s cn30xx;
46 struct cvmx_rnm_bist_status_s cn31xx;
47 struct cvmx_rnm_bist_status_s cn38xx;
48 struct cvmx_rnm_bist_status_s cn38xxp2;
49 struct cvmx_rnm_bist_status_s cn50xx;
50 struct cvmx_rnm_bist_status_s cn52xx;
51 struct cvmx_rnm_bist_status_s cn52xxp1;
52 struct cvmx_rnm_bist_status_s cn56xx;
53 struct cvmx_rnm_bist_status_s cn56xxp1;
54 struct cvmx_rnm_bist_status_s cn58xx;
55 struct cvmx_rnm_bist_status_s cn58xxp1;
56};
57
58union cvmx_rnm_ctl_status {
59 uint64_t u64;
60 struct cvmx_rnm_ctl_status_s {
61 uint64_t reserved_9_63:55;
62 uint64_t ent_sel:4;
63 uint64_t exp_ent:1;
64 uint64_t rng_rst:1;
65 uint64_t rnm_rst:1;
66 uint64_t rng_en:1;
67 uint64_t ent_en:1;
68 } s;
69 struct cvmx_rnm_ctl_status_cn30xx {
70 uint64_t reserved_4_63:60;
71 uint64_t rng_rst:1;
72 uint64_t rnm_rst:1;
73 uint64_t rng_en:1;
74 uint64_t ent_en:1;
75 } cn30xx;
76 struct cvmx_rnm_ctl_status_cn30xx cn31xx;
77 struct cvmx_rnm_ctl_status_cn30xx cn38xx;
78 struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
79 struct cvmx_rnm_ctl_status_s cn50xx;
80 struct cvmx_rnm_ctl_status_s cn52xx;
81 struct cvmx_rnm_ctl_status_s cn52xxp1;
82 struct cvmx_rnm_ctl_status_s cn56xx;
83 struct cvmx_rnm_ctl_status_s cn56xxp1;
84 struct cvmx_rnm_ctl_status_s cn58xx;
85 struct cvmx_rnm_ctl_status_s cn58xxp1;
86};
87
88#endif
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index e31e3fe14f8a..9d9381e2e3d8 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -271,7 +271,7 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
271 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT 271 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
272 * because it is fast and harmless. 272 * because it is fast and harmless.
273 */ 273 */
274 if ((csr_addr >> 40) == (0x800118)) 274 if (((csr_addr >> 40) & 0x7ffff) == (0x118))
275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); 275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
276} 276}
277 277
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 4320239cf4ef..f266295cce51 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -10,6 +10,7 @@
10#define _ASM_PAGE_H 10#define _ASM_PAGE_H
11 11
12#include <spaces.h> 12#include <spaces.h>
13#include <linux/const.h>
13 14
14/* 15/*
15 * PAGE_SHIFT determines the page size 16 * PAGE_SHIFT determines the page size
@@ -29,12 +30,12 @@
29#ifdef CONFIG_PAGE_SIZE_64KB 30#ifdef CONFIG_PAGE_SIZE_64KB
30#define PAGE_SHIFT 16 31#define PAGE_SHIFT 16
31#endif 32#endif
32#define PAGE_SIZE (1UL << PAGE_SHIFT) 33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
33#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 34#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
34 35
35#ifdef CONFIG_HUGETLB_PAGE 36#ifdef CONFIG_HUGETLB_PAGE
36#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
37#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) 38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
38#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 39#define HPAGE_MASK (~(HPAGE_SIZE - 1))
39#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
40#endif /* CONFIG_HUGETLB_PAGE */ 41#endif /* CONFIG_HUGETLB_PAGE */
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index a68d111e55e9..5ebf82572ec0 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -65,8 +65,6 @@ extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
65 65
66extern unsigned int pcibios_assign_all_busses(void); 66extern unsigned int pcibios_assign_all_busses(void);
67 67
68#define pcibios_scan_all_fns(a, b) 0
69
70extern unsigned long PCIBIOS_MIN_IO; 68extern unsigned long PCIBIOS_MIN_IO;
71extern unsigned long PCIBIOS_MIN_MEM; 69extern unsigned long PCIBIOS_MIN_MEM;
72 70
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 4ed9d1bba2ba..9cd508993956 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -109,13 +109,13 @@
109 109
110#define VMALLOC_START MAP_BASE 110#define VMALLOC_START MAP_BASE
111#define VMALLOC_END \ 111#define VMALLOC_END \
112 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) 112 (VMALLOC_START + \
113 PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32))
113#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ 114#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
114 VMALLOC_START != CKSSEG 115 VMALLOC_START != CKSSEG
115/* Load modules into 32bit-compatible segment. */ 116/* Load modules into 32bit-compatible segment. */
116#define MODULE_START CKSSEG 117#define MODULE_START CKSSEG
117#define MODULE_END (FIXADDR_START-2*PAGE_SIZE) 118#define MODULE_END (FIXADDR_START-2*PAGE_SIZE)
118extern pgd_t module_pg_dir[PTRS_PER_PGD];
119#endif 119#endif
120 120
121#define pte_ERROR(e) \ 121#define pte_ERROR(e) \
@@ -188,12 +188,7 @@ static inline void pud_clear(pud_t *pudp)
188#define __pmd_offset(address) pmd_index(address) 188#define __pmd_offset(address) pmd_index(address)
189 189
190/* to find an entry in a kernel page-table-directory */ 190/* to find an entry in a kernel page-table-directory */
191#ifdef MODULE_START 191#define pgd_offset_k(address) pgd_offset(&init_mm, address)
192#define pgd_offset_k(address) \
193 ((address) >= MODULE_START ? module_pg_dir : pgd_offset(&init_mm, 0UL))
194#else
195#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)
196#endif
197 192
198#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 193#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
199#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 194#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index cd30f83235bb..fcf5f98d90cc 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -32,6 +32,9 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti);
32 32
33struct task_struct; 33struct task_struct;
34 34
35extern unsigned int ll_bit;
36extern struct task_struct *ll_task;
37
35#ifdef CONFIG_MIPS_MT_FPAFF 38#ifdef CONFIG_MIPS_MT_FPAFF
36 39
37/* 40/*
@@ -63,11 +66,18 @@ do { \
63#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) 66#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
64#endif 67#endif
65 68
69#define __clear_software_ll_bit() \
70do { \
71 if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
72 ll_bit = 0; \
73} while (0)
74
66#define switch_to(prev, next, last) \ 75#define switch_to(prev, next, last) \
67do { \ 76do { \
68 __mips_mt_fpaff_switch_to(prev); \ 77 __mips_mt_fpaff_switch_to(prev); \
69 if (cpu_has_dsp) \ 78 if (cpu_has_dsp) \
70 __save_dsp(prev); \ 79 __save_dsp(prev); \
80 __clear_software_ll_bit(); \
71 (last) = resume(prev, next, task_thread_info(next)); \ 81 (last) = resume(prev, next, task_thread_info(next)); \
72} while (0) 82} while (0)
73 83
@@ -84,7 +94,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
84{ 94{
85 __u32 retval; 95 __u32 retval;
86 96
87 if (cpu_has_llsc && R10000_LLSC_WAR) { 97 if (kernel_uses_llsc && R10000_LLSC_WAR) {
88 unsigned long dummy; 98 unsigned long dummy;
89 99
90 __asm__ __volatile__( 100 __asm__ __volatile__(
@@ -99,7 +109,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
99 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 109 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
100 : "R" (*m), "Jr" (val) 110 : "R" (*m), "Jr" (val)
101 : "memory"); 111 : "memory");
102 } else if (cpu_has_llsc) { 112 } else if (kernel_uses_llsc) {
103 unsigned long dummy; 113 unsigned long dummy;
104 114
105 __asm__ __volatile__( 115 __asm__ __volatile__(
@@ -136,7 +146,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
136{ 146{
137 __u64 retval; 147 __u64 retval;
138 148
139 if (cpu_has_llsc && R10000_LLSC_WAR) { 149 if (kernel_uses_llsc && R10000_LLSC_WAR) {
140 unsigned long dummy; 150 unsigned long dummy;
141 151
142 __asm__ __volatile__( 152 __asm__ __volatile__(
@@ -149,7 +159,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
149 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 159 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
150 : "R" (*m), "Jr" (val) 160 : "R" (*m), "Jr" (val)
151 : "memory"); 161 : "memory");
152 } else if (cpu_has_llsc) { 162 } else if (kernel_uses_llsc) {
153 unsigned long dummy; 163 unsigned long dummy;
154 164
155 __asm__ __volatile__( 165 __asm__ __volatile__(
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 8d006ec65677..2c1e1d02338b 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -183,9 +183,6 @@ void output_mm_defines(void)
183 OFFSET(MM_PGD, mm_struct, pgd); 183 OFFSET(MM_PGD, mm_struct, pgd);
184 OFFSET(MM_CONTEXT, mm_struct, context); 184 OFFSET(MM_CONTEXT, mm_struct, context);
185 BLANK(); 185 BLANK();
186 DEFINE(_PAGE_SIZE, PAGE_SIZE);
187 DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
188 BLANK();
189 DEFINE(_PGD_T_SIZE, sizeof(pgd_t)); 186 DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
190 DEFINE(_PMD_T_SIZE, sizeof(pmd_t)); 187 DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
191 DEFINE(_PTE_T_SIZE, sizeof(pte_t)); 188 DEFINE(_PTE_T_SIZE, sizeof(pte_t));
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 02b7713cf71c..408d0a07b3a3 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -167,7 +167,7 @@ static inline void check_mult_sh(void)
167 panic(bug64hit, !R4000_WAR ? r4kwar : nowar); 167 panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
168} 168}
169 169
170static volatile int daddi_ov __cpuinitdata = 0; 170static volatile int daddi_ov __cpuinitdata;
171 171
172asmlinkage void __init do_daddi_ov(struct pt_regs *regs) 172asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
173{ 173{
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1abe9905c9c1..f709657e4dcd 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -31,7 +31,7 @@
31 * The wait instruction stops the pipeline and reduces the power consumption of 31 * The wait instruction stops the pipeline and reduces the power consumption of
32 * the CPU very much. 32 * the CPU very much.
33 */ 33 */
34void (*cpu_wait)(void) = NULL; 34void (*cpu_wait)(void);
35 35
36static void r3081_wait(void) 36static void r3081_wait(void)
37{ 37{
@@ -91,16 +91,13 @@ static void rm7k_wait_irqoff(void)
91 local_irq_enable(); 91 local_irq_enable();
92} 92}
93 93
94/* The Au1xxx wait is available only if using 32khz counter or 94/*
95 * external timer source, but specifically not CP0 Counter. */ 95 * The Au1xxx wait is available only if using 32khz counter or
96int allow_au1k_wait; 96 * external timer source, but specifically not CP0 Counter.
97 97 * alchemy/common/time.c may override cpu_wait!
98 */
98static void au1k_wait(void) 99static void au1k_wait(void)
99{ 100{
100 if (!allow_au1k_wait)
101 return;
102
103 /* using the wait instruction makes CP0 counter unusable */
104 __asm__(" .set mips3 \n" 101 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n" 102 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n" 103 " cache 0x14, 32(%0) \n"
@@ -115,7 +112,7 @@ static void au1k_wait(void)
115 : : "r" (au1k_wait)); 112 : : "r" (au1k_wait));
116} 113}
117 114
118static int __initdata nowait = 0; 115static int __initdata nowait;
119 116
120static int __init wait_disable(char *s) 117static int __init wait_disable(char *s)
121{ 118{
@@ -159,6 +156,9 @@ void __init check_wait(void)
159 case CPU_25KF: 156 case CPU_25KF:
160 case CPU_PR4450: 157 case CPU_PR4450:
161 case CPU_BCM3302: 158 case CPU_BCM3302:
159 case CPU_BCM6338:
160 case CPU_BCM6348:
161 case CPU_BCM6358:
162 case CPU_CAVIUM_OCTEON: 162 case CPU_CAVIUM_OCTEON:
163 cpu_wait = r4k_wait; 163 cpu_wait = r4k_wait;
164 break; 164 break;
@@ -857,6 +857,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
857 decode_configs(c); 857 decode_configs(c);
858 switch (c->processor_id & 0xff00) { 858 switch (c->processor_id & 0xff00) {
859 case PRID_IMP_BCM3302: 859 case PRID_IMP_BCM3302:
860 /* same as PRID_IMP_BCM6338 */
860 c->cputype = CPU_BCM3302; 861 c->cputype = CPU_BCM3302;
861 __cpu_name[cpu] = "Broadcom BCM3302"; 862 __cpu_name[cpu] = "Broadcom BCM3302";
862 break; 863 break;
@@ -864,6 +865,25 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
864 c->cputype = CPU_BCM4710; 865 c->cputype = CPU_BCM4710;
865 __cpu_name[cpu] = "Broadcom BCM4710"; 866 __cpu_name[cpu] = "Broadcom BCM4710";
866 break; 867 break;
868 case PRID_IMP_BCM6345:
869 c->cputype = CPU_BCM6345;
870 __cpu_name[cpu] = "Broadcom BCM6345";
871 break;
872 case PRID_IMP_BCM6348:
873 c->cputype = CPU_BCM6348;
874 __cpu_name[cpu] = "Broadcom BCM6348";
875 break;
876 case PRID_IMP_BCM4350:
877 switch (c->processor_id & 0xf0) {
878 case PRID_REV_BCM6358:
879 c->cputype = CPU_BCM6358;
880 __cpu_name[cpu] = "Broadcom BCM6358";
881 break;
882 default:
883 c->cputype = CPU_UNKNOWN;
884 break;
885 }
886 break;
867 } 887 }
868} 888}
869 889
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index fd6e51224034..f2397f00db43 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -31,7 +31,7 @@
31#include <asm/rtlx.h> 31#include <asm/rtlx.h>
32#include <asm/kspd.h> 32#include <asm/kspd.h>
33 33
34static struct workqueue_struct *workqueue = NULL; 34static struct workqueue_struct *workqueue;
35static struct work_struct work; 35static struct work_struct work;
36 36
37extern unsigned long cpu_khz; 37extern unsigned long cpu_khz;
@@ -58,7 +58,7 @@ struct mtsp_syscall_generic {
58}; 58};
59 59
60static struct list_head kspd_notifylist; 60static struct list_head kspd_notifylist;
61static int sp_stopping = 0; 61static int sp_stopping;
62 62
63/* these should match with those in the SDE kit */ 63/* these should match with those in the SDE kit */
64#define MTSP_SYSCALL_BASE 0 64#define MTSP_SYSCALL_BASE 0
@@ -328,7 +328,7 @@ static void sp_cleanup(void)
328 sys_chdir("/"); 328 sys_chdir("/");
329} 329}
330 330
331static int channel_open = 0; 331static int channel_open;
332 332
333/* the work handler */ 333/* the work handler */
334static void sp_work(struct work_struct *unused) 334static void sp_work(struct work_struct *unused)
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index 42461310b185..cbc6182b0065 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -18,7 +18,7 @@
18cpumask_t mt_fpu_cpumask; 18cpumask_t mt_fpu_cpumask;
19 19
20static int fpaff_threshold = -1; 20static int fpaff_threshold = -1;
21unsigned long mt_fpemul_threshold = 0; 21unsigned long mt_fpemul_threshold;
22 22
23/* 23/*
24 * Replacement functions for the sys_sched_setaffinity() and 24 * Replacement functions for the sys_sched_setaffinity() and
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index d01665a453f5..b2259e7cd829 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -125,10 +125,10 @@ void mips_mt_regdump(unsigned long mvpctl)
125 local_irq_restore(flags); 125 local_irq_restore(flags);
126} 126}
127 127
128static int mt_opt_norps = 0; 128static int mt_opt_norps;
129static int mt_opt_rpsctl = -1; 129static int mt_opt_rpsctl = -1;
130static int mt_opt_nblsu = -1; 130static int mt_opt_nblsu = -1;
131static int mt_opt_forceconfig7 = 0; 131static int mt_opt_forceconfig7;
132static int mt_opt_config7 = -1; 132static int mt_opt_config7 = -1;
133 133
134static int __init rps_disable(char *s) 134static int __init rps_disable(char *s)
@@ -161,8 +161,8 @@ static int __init config7_set(char *str)
161__setup("config7=", config7_set); 161__setup("config7=", config7_set);
162 162
163/* Experimental cache flush control parameters that should go away some day */ 163/* Experimental cache flush control parameters that should go away some day */
164int mt_protiflush = 0; 164int mt_protiflush;
165int mt_protdflush = 0; 165int mt_protdflush;
166int mt_n_iflushes = 1; 166int mt_n_iflushes = 1;
167int mt_n_dflushes = 1; 167int mt_n_dflushes = 1;
168 168
@@ -194,7 +194,7 @@ static int __init ndflush(char *s)
194} 194}
195__setup("ndflush=", ndflush); 195__setup("ndflush=", ndflush);
196 196
197static unsigned int itc_base = 0; 197static unsigned int itc_base;
198 198
199static int __init set_itc_base(char *str) 199static int __init set_itc_base(char *str)
200{ 200{
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index d52389672b06..3952b8323efa 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -36,9 +36,6 @@
36 .align 7 36 .align 7
37 LEAF(resume) 37 LEAF(resume)
38 .set arch=octeon 38 .set arch=octeon
39#ifndef CONFIG_CPU_HAS_LLSC
40 sw zero, ll_bit
41#endif
42 mfc0 t1, CP0_STATUS 39 mfc0 t1, CP0_STATUS
43 LONG_S t1, THREAD_STATUS(a0) 40 LONG_S t1, THREAD_STATUS(a0)
44 cpu_save_nonscratch a0 41 cpu_save_nonscratch a0
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 656bde2e11b1..698414b7a253 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -46,9 +46,6 @@
46 * struct thread_info *next_ti) ) 46 * struct thread_info *next_ti) )
47 */ 47 */
48LEAF(resume) 48LEAF(resume)
49#ifndef CONFIG_CPU_HAS_LLSC
50 sw zero, ll_bit
51#endif
52 mfc0 t1, CP0_STATUS 49 mfc0 t1, CP0_STATUS
53 sw t1, THREAD_STATUS(a0) 50 sw t1, THREAD_STATUS(a0)
54 cpu_save_nonscratch a0 51 cpu_save_nonscratch a0
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index d9bfae53c43f..8893ee1a2368 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -45,9 +45,6 @@
45 */ 45 */
46 .align 5 46 .align 5
47 LEAF(resume) 47 LEAF(resume)
48#ifndef CONFIG_CPU_HAS_LLSC
49 sw zero, ll_bit
50#endif
51 mfc0 t1, CP0_STATUS 48 mfc0 t1, CP0_STATUS
52 LONG_S t1, THREAD_STATUS(a0) 49 LONG_S t1, THREAD_STATUS(a0)
53 cpu_save_nonscratch a0 50 cpu_save_nonscratch a0
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 4ce93aa7b372..a10ebfdc28ae 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -57,7 +57,7 @@ static struct chan_waitqueues {
57} channel_wqs[RTLX_CHANNELS]; 57} channel_wqs[RTLX_CHANNELS];
58 58
59static struct vpe_notifications notify; 59static struct vpe_notifications notify;
60static int sp_stopping = 0; 60static int sp_stopping;
61 61
62extern void *vpe_get_shared(int index); 62extern void *vpe_get_shared(int index);
63 63
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index b57082123536..7c2de4f091c4 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -187,78 +187,6 @@ illegal_syscall:
187 j o32_syscall_exit 187 j o32_syscall_exit
188 END(handle_sys) 188 END(handle_sys)
189 189
190 LEAF(mips_atomic_set)
191 andi v0, a1, 3 # must be word aligned
192 bnez v0, bad_alignment
193
194 lw v1, TI_ADDR_LIMIT($28) # in legal address range?
195 addiu a0, a1, 4
196 or a0, a0, a1
197 and a0, a0, v1
198 bltz a0, bad_address
199
200#ifdef CONFIG_CPU_HAS_LLSC
201 /* Ok, this is the ll/sc case. World is sane :-) */
2021: ll v0, (a1)
203 move a0, a2
2042: sc a0, (a1)
205#if R10000_LLSC_WAR
206 beqzl a0, 1b
207#else
208 beqz a0, 1b
209#endif
210
211 .section __ex_table,"a"
212 PTR 1b, bad_stack
213 PTR 2b, bad_stack
214 .previous
215#else
216 sw a1, 16(sp)
217 sw a2, 20(sp)
218
219 move a0, sp
220 move a2, a1
221 li a1, 1
222 jal do_page_fault
223
224 lw a1, 16(sp)
225 lw a2, 20(sp)
226
227 /*
228 * At this point the page should be readable and writable unless
229 * there was no more memory available.
230 */
2311: lw v0, (a1)
2322: sw a2, (a1)
233
234 .section __ex_table,"a"
235 PTR 1b, no_mem
236 PTR 2b, no_mem
237 .previous
238#endif
239
240 sw zero, PT_R7(sp) # success
241 sw v0, PT_R2(sp) # result
242
243 j o32_syscall_exit # continue like a normal syscall
244
245no_mem: li v0, -ENOMEM
246 jr ra
247
248bad_address:
249 li v0, -EFAULT
250 jr ra
251
252bad_alignment:
253 li v0, -EINVAL
254 jr ra
255 END(mips_atomic_set)
256
257 LEAF(sys_sysmips)
258 beq a0, MIPS_ATOMIC_SET, mips_atomic_set
259 j _sys_sysmips
260 END(sys_sysmips)
261
262 LEAF(sys_syscall) 190 LEAF(sys_syscall)
263 subu t0, a0, __NR_O32_Linux # check syscall number 191 subu t0, a0, __NR_O32_Linux # check syscall number
264 sltiu v0, t0, __NR_O32_Linux_syscalls + 1 192 sltiu v0, t0, __NR_O32_Linux_syscalls + 1
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 3d866f24e064..b97b993846d6 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -124,78 +124,6 @@ illegal_syscall:
124 j n64_syscall_exit 124 j n64_syscall_exit
125 END(handle_sys64) 125 END(handle_sys64)
126 126
127 LEAF(mips_atomic_set)
128 andi v0, a1, 3 # must be word aligned
129 bnez v0, bad_alignment
130
131 LONG_L v1, TI_ADDR_LIMIT($28) # in legal address range?
132 LONG_ADDIU a0, a1, 4
133 or a0, a0, a1
134 and a0, a0, v1
135 bltz a0, bad_address
136
137#ifdef CONFIG_CPU_HAS_LLSC
138 /* Ok, this is the ll/sc case. World is sane :-) */
1391: ll v0, (a1)
140 move a0, a2
1412: sc a0, (a1)
142#if R10000_LLSC_WAR
143 beqzl a0, 1b
144#else
145 beqz a0, 1b
146#endif
147
148 .section __ex_table,"a"
149 PTR 1b, bad_stack
150 PTR 2b, bad_stack
151 .previous
152#else
153 sw a1, 16(sp)
154 sw a2, 20(sp)
155
156 move a0, sp
157 move a2, a1
158 li a1, 1
159 jal do_page_fault
160
161 lw a1, 16(sp)
162 lw a2, 20(sp)
163
164 /*
165 * At this point the page should be readable and writable unless
166 * there was no more memory available.
167 */
1681: lw v0, (a1)
1692: sw a2, (a1)
170
171 .section __ex_table,"a"
172 PTR 1b, no_mem
173 PTR 2b, no_mem
174 .previous
175#endif
176
177 sd zero, PT_R7(sp) # success
178 sd v0, PT_R2(sp) # result
179
180 j n64_syscall_exit # continue like a normal syscall
181
182no_mem: li v0, -ENOMEM
183 jr ra
184
185bad_address:
186 li v0, -EFAULT
187 jr ra
188
189bad_alignment:
190 li v0, -EINVAL
191 jr ra
192 END(mips_atomic_set)
193
194 LEAF(sys_sysmips)
195 beq a0, MIPS_ATOMIC_SET, mips_atomic_set
196 j _sys_sysmips
197 END(sys_sysmips)
198
199 .align 3 127 .align 3
200sys_call_table: 128sys_call_table:
201 PTR sys_read /* 5000 */ 129 PTR sys_read /* 5000 */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2950b97253b7..2b290d70083e 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -441,7 +441,7 @@ static void __init bootmem_init(void)
441 * initialization hook for anything else was introduced. 441 * initialization hook for anything else was introduced.
442 */ 442 */
443 443
444static int usermem __initdata = 0; 444static int usermem __initdata;
445 445
446static int __init early_parse_mem(char *p) 446static int __init early_parse_mem(char *p)
447{ 447{
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index bc7d9b05e2f4..64668a93248b 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -32,6 +32,7 @@
32#include <linux/cpumask.h> 32#include <linux/cpumask.h>
33#include <linux/cpu.h> 33#include <linux/cpu.h>
34#include <linux/err.h> 34#include <linux/err.h>
35#include <linux/smp.h>
35 36
36#include <asm/atomic.h> 37#include <asm/atomic.h>
37#include <asm/cpu.h> 38#include <asm/cpu.h>
@@ -49,8 +50,6 @@ volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
49int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ 50int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
50int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ 51int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
51 52
52extern void cpu_idle(void);
53
54/* Number of TCs (or siblings in Intel speak) per CPU core */ 53/* Number of TCs (or siblings in Intel speak) per CPU core */
55int smp_num_siblings = 1; 54int smp_num_siblings = 1;
56EXPORT_SYMBOL(smp_num_siblings); 55EXPORT_SYMBOL(smp_num_siblings);
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index c16bb6d6c25c..1a466baf0edf 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -95,14 +95,14 @@ void init_smtc_stats(void);
95 95
96/* Global SMTC Status */ 96/* Global SMTC Status */
97 97
98unsigned int smtc_status = 0; 98unsigned int smtc_status;
99 99
100/* Boot command line configuration overrides */ 100/* Boot command line configuration overrides */
101 101
102static int vpe0limit; 102static int vpe0limit;
103static int ipibuffers = 0; 103static int ipibuffers;
104static int nostlb = 0; 104static int nostlb;
105static int asidmask = 0; 105static int asidmask;
106unsigned long smtc_asid_mask = 0xff; 106unsigned long smtc_asid_mask = 0xff;
107 107
108static int __init vpe0tcs(char *str) 108static int __init vpe0tcs(char *str)
@@ -151,7 +151,7 @@ __setup("asidmask=", asidmask_set);
151 151
152#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 152#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
153 153
154static int hang_trig = 0; 154static int hang_trig;
155 155
156static int __init hangtrig_enable(char *s) 156static int __init hangtrig_enable(char *s)
157{ 157{
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 8cf384644040..3fe1fcfa2e73 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -28,7 +28,9 @@
28#include <linux/compiler.h> 28#include <linux/compiler.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/ipc.h> 30#include <linux/ipc.h>
31#include <linux/uaccess.h>
31 32
33#include <asm/asm.h>
32#include <asm/branch.h> 34#include <asm/branch.h>
33#include <asm/cachectl.h> 35#include <asm/cachectl.h>
34#include <asm/cacheflush.h> 36#include <asm/cacheflush.h>
@@ -290,12 +292,116 @@ SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
290 return 0; 292 return 0;
291} 293}
292 294
293asmlinkage int _sys_sysmips(long cmd, long arg1, long arg2, long arg3) 295static inline int mips_atomic_set(struct pt_regs *regs,
296 unsigned long addr, unsigned long new)
294{ 297{
298 unsigned long old, tmp;
299 unsigned int err;
300
301 if (unlikely(addr & 3))
302 return -EINVAL;
303
304 if (unlikely(!access_ok(VERIFY_WRITE, addr, 4)))
305 return -EINVAL;
306
307 if (cpu_has_llsc && R10000_LLSC_WAR) {
308 __asm__ __volatile__ (
309 " li %[err], 0 \n"
310 "1: ll %[old], (%[addr]) \n"
311 " move %[tmp], %[new] \n"
312 "2: sc %[tmp], (%[addr]) \n"
313 " beqzl %[tmp], 1b \n"
314 "3: \n"
315 " .section .fixup,\"ax\" \n"
316 "4: li %[err], %[efault] \n"
317 " j 3b \n"
318 " .previous \n"
319 " .section __ex_table,\"a\" \n"
320 " "STR(PTR)" 1b, 4b \n"
321 " "STR(PTR)" 2b, 4b \n"
322 " .previous \n"
323 : [old] "=&r" (old),
324 [err] "=&r" (err),
325 [tmp] "=&r" (tmp)
326 : [addr] "r" (addr),
327 [new] "r" (new),
328 [efault] "i" (-EFAULT)
329 : "memory");
330 } else if (cpu_has_llsc) {
331 __asm__ __volatile__ (
332 " li %[err], 0 \n"
333 "1: ll %[old], (%[addr]) \n"
334 " move %[tmp], %[new] \n"
335 "2: sc %[tmp], (%[addr]) \n"
336 " bnez %[tmp], 4f \n"
337 "3: \n"
338 " .subsection 2 \n"
339 "4: b 1b \n"
340 " .previous \n"
341 " \n"
342 " .section .fixup,\"ax\" \n"
343 "5: li %[err], %[efault] \n"
344 " j 3b \n"
345 " .previous \n"
346 " .section __ex_table,\"a\" \n"
347 " "STR(PTR)" 1b, 5b \n"
348 " "STR(PTR)" 2b, 5b \n"
349 " .previous \n"
350 : [old] "=&r" (old),
351 [err] "=&r" (err),
352 [tmp] "=&r" (tmp)
353 : [addr] "r" (addr),
354 [new] "r" (new),
355 [efault] "i" (-EFAULT)
356 : "memory");
357 } else {
358 do {
359 preempt_disable();
360 ll_bit = 1;
361 ll_task = current;
362 preempt_enable();
363
364 err = __get_user(old, (unsigned int *) addr);
365 err |= __put_user(new, (unsigned int *) addr);
366 if (err)
367 break;
368 rmb();
369 } while (!ll_bit);
370 }
371
372 if (unlikely(err))
373 return err;
374
375 regs->regs[2] = old;
376 regs->regs[7] = 0; /* No error */
377
378 /*
379 * Don't let your children do this ...
380 */
381 __asm__ __volatile__(
382 " move $29, %0 \n"
383 " j syscall_exit \n"
384 : /* no outputs */
385 : "r" (regs));
386
387 /* unreached. Honestly. */
388 while (1);
389}
390
391save_static_function(sys_sysmips);
392static int __used noinline
393_sys_sysmips(nabi_no_regargs struct pt_regs regs)
394{
395 long cmd, arg1, arg2, arg3;
396
397 cmd = regs.regs[4];
398 arg1 = regs.regs[5];
399 arg2 = regs.regs[6];
400 arg3 = regs.regs[7];
401
295 switch (cmd) { 402 switch (cmd) {
296 case MIPS_ATOMIC_SET: 403 case MIPS_ATOMIC_SET:
297 printk(KERN_CRIT "How did I get here?\n"); 404 return mips_atomic_set(&regs, arg1, arg2);
298 return -EINVAL;
299 405
300 case MIPS_FIXADE: 406 case MIPS_FIXADE:
301 if (arg1 & ~3) 407 if (arg1 & ~3)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 08f1edf355e8..0a18b4c62afb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -466,9 +466,8 @@ asmlinkage void do_be(struct pt_regs *regs)
466 * The ll_bit is cleared by r*_switch.S 466 * The ll_bit is cleared by r*_switch.S
467 */ 467 */
468 468
469unsigned long ll_bit; 469unsigned int ll_bit;
470 470struct task_struct *ll_task;
471static struct task_struct *ll_task = NULL;
472 471
473static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 472static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
474{ 473{
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 58738c8d754f..2769bed3d2af 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -1,4 +1,5 @@
1#include <asm/asm-offsets.h> 1#include <asm/asm-offsets.h>
2#include <asm/page.h>
2#include <asm-generic/vmlinux.lds.h> 3#include <asm-generic/vmlinux.lds.h>
3 4
4#undef mips 5#undef mips
@@ -42,13 +43,7 @@ SECTIONS
42 } :text = 0 43 } :text = 0
43 _etext = .; /* End of text section */ 44 _etext = .; /* End of text section */
44 45
45 /* Exception table */ 46 EXCEPTION_TABLE(16)
46 . = ALIGN(16);
47 __ex_table : {
48 __start___ex_table = .;
49 *(__ex_table)
50 __stop___ex_table = .;
51 }
52 47
53 /* Exception table for data bus errors */ 48 /* Exception table for data bus errors */
54 __dbe_table : { 49 __dbe_table : {
@@ -65,20 +60,10 @@ SECTIONS
65 /* writeable */ 60 /* writeable */
66 .data : { /* Data */ 61 .data : { /* Data */
67 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 62 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
68 /*
69 * This ALIGN is needed as a workaround for a bug a
70 * gcc bug upto 4.1 which limits the maximum alignment
71 * to at most 32kB and results in the following
72 * warning:
73 *
74 * CC arch/mips/kernel/init_task.o
75 * arch/mips/kernel/init_task.c:30: warning: alignment
76 * of ‘init_thread_union’ is greater than maximum
77 * object file alignment. Using 32768
78 */
79 . = ALIGN(_PAGE_SIZE);
80 *(.data.init_task)
81 63
64 INIT_TASK_DATA(PAGE_SIZE)
65 NOSAVE_DATA
66 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
82 DATA_DATA 67 DATA_DATA
83 CONSTRUCTORS 68 CONSTRUCTORS
84 } 69 }
@@ -95,51 +80,13 @@ SECTIONS
95 .sdata : { 80 .sdata : {
96 *(.sdata) 81 *(.sdata)
97 } 82 }
98
99 . = ALIGN(_PAGE_SIZE);
100 .data_nosave : {
101 __nosave_begin = .;
102 *(.data.nosave)
103 }
104 . = ALIGN(_PAGE_SIZE);
105 __nosave_end = .;
106
107 . = ALIGN(1 << CONFIG_MIPS_L1_CACHE_SHIFT);
108 .data.cacheline_aligned : {
109 *(.data.cacheline_aligned)
110 }
111 _edata = .; /* End of data section */ 83 _edata = .; /* End of data section */
112 84
113 /* will be freed after init */ 85 /* will be freed after init */
114 . = ALIGN(_PAGE_SIZE); /* Init code and data */ 86 . = ALIGN(PAGE_SIZE); /* Init code and data */
115 __init_begin = .; 87 __init_begin = .;
116 .init.text : { 88 INIT_TEXT_SECTION(PAGE_SIZE)
117 _sinittext = .; 89 INIT_DATA_SECTION(16)
118 INIT_TEXT
119 _einittext = .;
120 }
121 .init.data : {
122 INIT_DATA
123 }
124 . = ALIGN(16);
125 .init.setup : {
126 __setup_start = .;
127 *(.init.setup)
128 __setup_end = .;
129 }
130
131 .initcall.init : {
132 __initcall_start = .;
133 INITCALLS
134 __initcall_end = .;
135 }
136
137 .con_initcall.init : {
138 __con_initcall_start = .;
139 *(.con_initcall.init)
140 __con_initcall_end = .;
141 }
142 SECURITY_INIT
143 90
144 /* .exit.text is discarded at runtime, not link time, to deal with 91 /* .exit.text is discarded at runtime, not link time, to deal with
145 * references from .rodata 92 * references from .rodata
@@ -150,43 +97,16 @@ SECTIONS
150 .exit.data : { 97 .exit.data : {
151 EXIT_DATA 98 EXIT_DATA
152 } 99 }
153#if defined(CONFIG_BLK_DEV_INITRD) 100
154 . = ALIGN(_PAGE_SIZE); 101 PERCPU(PAGE_SIZE)
155 .init.ramfs : { 102 . = ALIGN(PAGE_SIZE);
156 __initramfs_start = .;
157 *(.init.ramfs)
158 __initramfs_end = .;
159 }
160#endif
161 PERCPU(_PAGE_SIZE)
162 . = ALIGN(_PAGE_SIZE);
163 __init_end = .; 103 __init_end = .;
164 /* freed after init ends here */ 104 /* freed after init ends here */
165 105
166 __bss_start = .; /* BSS */ 106 BSS_SECTION(0, 0, 0)
167 .sbss : {
168 *(.sbss)
169 *(.scommon)
170 }
171 .bss : {
172 *(.bss)
173 *(COMMON)
174 }
175 __bss_stop = .;
176 107
177 _end = . ; 108 _end = . ;
178 109
179 /* Sections to be discarded */
180 /DISCARD/ : {
181 *(.exitcall.exit)
182
183 /* ABI crap starts here */
184 *(.MIPS.options)
185 *(.options)
186 *(.pdr)
187 *(.reginfo)
188 }
189
190 /* These mark the ABI of the kernel for debuggers. */ 110 /* These mark the ABI of the kernel for debuggers. */
191 .mdebug.abi32 : { 111 .mdebug.abi32 : {
192 KEEP(*(.mdebug.abi32)) 112 KEEP(*(.mdebug.abi32))
@@ -212,4 +132,14 @@ SECTIONS
212 *(.gptab.bss) 132 *(.gptab.bss)
213 *(.gptab.sbss) 133 *(.gptab.sbss)
214 } 134 }
135
136 /* Sections to be discarded */
137 DISCARDS
138 /DISCARD/ : {
139 /* ABI crap starts here */
140 *(.MIPS.options)
141 *(.options)
142 *(.pdr)
143 *(.reginfo)
144 }
215} 145}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 9a1ab7e87fd4..eb6c4c5b7fbe 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -74,7 +74,7 @@ static const int minor = 1; /* fixed for now */
74 74
75#ifdef CONFIG_MIPS_APSP_KSPD 75#ifdef CONFIG_MIPS_APSP_KSPD
76static struct kspd_notifications kspd_events; 76static struct kspd_notifications kspd_events;
77static int kspd_events_reqd = 0; 77static int kspd_events_reqd;
78#endif 78#endif
79 79
80/* grab the likely amount of memory we will need. */ 80/* grab the likely amount of memory we will need. */
diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile
deleted file mode 100644
index d34671d1b899..000000000000
--- a/arch/mips/lemote/lm2e/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for Lemote Fulong mini-PC board.
3#
4
5obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c
deleted file mode 100644
index 6c95da3ca76f..000000000000
--- a/arch/mips/lemote/lm2e/dbg_io.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
5 *
6 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 */
30
31#include <linux/io.h>
32#include <linux/init.h>
33#include <linux/types.h>
34
35#include <asm/serial.h>
36
37#define UART16550_BAUD_2400 2400
38#define UART16550_BAUD_4800 4800
39#define UART16550_BAUD_9600 9600
40#define UART16550_BAUD_19200 19200
41#define UART16550_BAUD_38400 38400
42#define UART16550_BAUD_57600 57600
43#define UART16550_BAUD_115200 115200
44
45#define UART16550_PARITY_NONE 0
46#define UART16550_PARITY_ODD 0x08
47#define UART16550_PARITY_EVEN 0x18
48#define UART16550_PARITY_MARK 0x28
49#define UART16550_PARITY_SPACE 0x38
50
51#define UART16550_DATA_5BIT 0x0
52#define UART16550_DATA_6BIT 0x1
53#define UART16550_DATA_7BIT 0x2
54#define UART16550_DATA_8BIT 0x3
55
56#define UART16550_STOP_1BIT 0x0
57#define UART16550_STOP_2BIT 0x4
58
59/* ----------------------------------------------------- */
60
61/* === CONFIG === */
62#ifdef CONFIG_64BIT
63#define BASE (0xffffffffbfd003f8)
64#else
65#define BASE (0xbfd003f8)
66#endif
67
68#define MAX_BAUD BASE_BAUD
69/* === END OF CONFIG === */
70
71#define REG_OFFSET 1
72
73/* register offset */
74#define OFS_RCV_BUFFER 0
75#define OFS_TRANS_HOLD 0
76#define OFS_SEND_BUFFER 0
77#define OFS_INTR_ENABLE (1*REG_OFFSET)
78#define OFS_INTR_ID (2*REG_OFFSET)
79#define OFS_DATA_FORMAT (3*REG_OFFSET)
80#define OFS_LINE_CONTROL (3*REG_OFFSET)
81#define OFS_MODEM_CONTROL (4*REG_OFFSET)
82#define OFS_RS232_OUTPUT (4*REG_OFFSET)
83#define OFS_LINE_STATUS (5*REG_OFFSET)
84#define OFS_MODEM_STATUS (6*REG_OFFSET)
85#define OFS_RS232_INPUT (6*REG_OFFSET)
86#define OFS_SCRATCH_PAD (7*REG_OFFSET)
87
88#define OFS_DIVISOR_LSB (0*REG_OFFSET)
89#define OFS_DIVISOR_MSB (1*REG_OFFSET)
90
91/* memory-mapped read/write of the port */
92#define UART16550_READ(y) readb((char *)BASE + (y))
93#define UART16550_WRITE(y, z) writeb(z, (char *)BASE + (y))
94
95void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
96{
97 u32 divisor;
98
99 /* disable interrupts */
100 UART16550_WRITE(OFS_INTR_ENABLE, 0);
101
102 /* set up buad rate */
103 /* set DIAB bit */
104 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
105
106 /* set divisor */
107 divisor = MAX_BAUD / baud;
108 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
109 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
110
111 /* clear DIAB bit */
112 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
113
114 /* set data format */
115 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
116}
117
118static int remoteDebugInitialized;
119
120u8 getDebugChar(void)
121{
122 if (!remoteDebugInitialized) {
123 remoteDebugInitialized = 1;
124 debugInit(UART16550_BAUD_115200,
125 UART16550_DATA_8BIT,
126 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
127 }
128
129 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ;
130 return UART16550_READ(OFS_RCV_BUFFER);
131}
132
133int putDebugChar(u8 byte)
134{
135 if (!remoteDebugInitialized) {
136 remoteDebugInitialized = 1;
137 /*
138 debugInit(UART16550_BAUD_115200,
139 UART16550_DATA_8BIT,
140 UART16550_PARITY_NONE, UART16550_STOP_1BIT); */
141 }
142
143 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ;
144 UART16550_WRITE(OFS_SEND_BUFFER, byte);
145 return 1;
146}
diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c
deleted file mode 100644
index 1d0a09f3b832..000000000000
--- a/arch/mips/lemote/lm2e/irq.c
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 */
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/irq.h>
31
32#include <asm/irq_cpu.h>
33#include <asm/i8259.h>
34#include <asm/mipsregs.h>
35#include <asm/mips-boards/bonito64.h>
36
37
38/*
39 * the first level int-handler will jump here if it is a bonito irq
40 */
41static void bonito_irqdispatch(void)
42{
43 u32 int_status;
44 int i;
45
46 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
47 int_status = BONITO_INTISR;
48 if (int_status & (1 << 10)) {
49 while (int_status & (1 << 10)) {
50 udelay(1);
51 int_status = BONITO_INTISR;
52 }
53 }
54
55 /* Get pending sources, masked by current enables */
56 int_status = BONITO_INTISR & BONITO_INTEN;
57
58 if (int_status != 0) {
59 i = __ffs(int_status);
60 int_status &= ~(1 << i);
61 do_IRQ(BONITO_IRQ_BASE + i);
62 }
63}
64
65static void i8259_irqdispatch(void)
66{
67 int irq;
68
69 irq = i8259_irq();
70 if (irq >= 0) {
71 do_IRQ(irq);
72 } else {
73 spurious_interrupt();
74 }
75
76}
77
78asmlinkage void plat_irq_dispatch(void)
79{
80 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
81
82 if (pending & CAUSEF_IP7) {
83 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
84 } else if (pending & CAUSEF_IP5) {
85 i8259_irqdispatch();
86 } else if (pending & CAUSEF_IP2) {
87 bonito_irqdispatch();
88 } else {
89 spurious_interrupt();
90 }
91}
92
93static struct irqaction cascade_irqaction = {
94 .handler = no_action,
95 .name = "cascade",
96};
97
98void __init arch_init_irq(void)
99{
100 extern void bonito_irq_init(void);
101
102 /*
103 * Clear all of the interrupts while we change the able around a bit.
104 * int-handler is not on bootstrap
105 */
106 clear_c0_status(ST0_IM | ST0_BEV);
107 local_irq_disable();
108
109 /* most bonito irq should be level triggered */
110 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
111 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
112 BONITO_INTSTEER = 0;
113
114 /*
115 * Mask out all interrupt by writing "1" to all bit position in
116 * the interrupt reset reg.
117 */
118 BONITO_INTENCLR = ~0;
119
120 /* init all controller
121 * 0-15 ------> i8259 interrupt
122 * 16-23 ------> mips cpu interrupt
123 * 32-63 ------> bonito irq
124 */
125
126 /* Sets the first-level interrupt dispatcher. */
127 mips_cpu_irq_init();
128 init_i8259_irqs();
129 bonito_irq_init();
130
131 /*
132 printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE);
133 printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n",
134 BONITO_INTEN, BONITO_INTENSET,
135 BONITO_INTENCLR, BONITO_INTISR);
136 */
137
138 /* bonito irq at IP2 */
139 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
140 /* 8259 irq at IP5 */
141 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
142
143}
diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c
deleted file mode 100644
index 8be03a8e1ad4..000000000000
--- a/arch/mips/lemote/lm2e/pci.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * pci.c
3 *
4 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
5 * Author: Fuxin Zhang, zhangfx@lemote.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28#include <linux/types.h>
29#include <linux/pci.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <asm/mips-boards/bonito64.h>
33#include <asm/mach-lemote/pci.h>
34
35extern struct pci_ops bonito64_pci_ops;
36
37static struct resource loongson2e_pci_mem_resource = {
38 .name = "LOONGSON2E PCI MEM",
39 .start = LOONGSON2E_PCI_MEM_START,
40 .end = LOONGSON2E_PCI_MEM_END,
41 .flags = IORESOURCE_MEM,
42};
43
44static struct resource loongson2e_pci_io_resource = {
45 .name = "LOONGSON2E PCI IO MEM",
46 .start = LOONGSON2E_PCI_IO_START,
47 .end = IO_SPACE_LIMIT,
48 .flags = IORESOURCE_IO,
49};
50
51static struct pci_controller loongson2e_pci_controller = {
52 .pci_ops = &bonito64_pci_ops,
53 .io_resource = &loongson2e_pci_io_resource,
54 .mem_resource = &loongson2e_pci_mem_resource,
55 .mem_offset = 0x00000000UL,
56 .io_offset = 0x00000000UL,
57};
58
59static void __init ict_pcimap(void)
60{
61 /*
62 * local to PCI mapping: [256M,512M] -> [256M,512M]; differ from PMON
63 *
64 * CPU address space [256M,448M] is window for accessing pci space
65 * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M]
66 * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0
67 */
68 /* 1,00 0110 ,0001 01,00 0000 */
69 BONITO_PCIMAP = 0x46140;
70
71 /* 1, 00 0010, 0000,01, 00 0000 */
72 /* BONITO_PCIMAP = 0x42040; */
73
74 /*
75 * PCI to local mapping: [2G,2G+256M] -> [0,256M]
76 */
77 BONITO_PCIBASE0 = 0x80000000;
78 BONITO_PCIBASE1 = 0x00800000;
79 BONITO_PCIBASE2 = 0x90000000;
80
81}
82
83static int __init pcibios_init(void)
84{
85 ict_pcimap();
86
87 loongson2e_pci_controller.io_map_base =
88 (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE,
89 loongson2e_pci_io_resource.end -
90 loongson2e_pci_io_resource.start + 1);
91
92 register_pci_controller(&loongson2e_pci_controller);
93
94 return 0;
95}
96
97arch_initcall(pcibios_init);
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c
deleted file mode 100644
index 7edc15dfed6c..000000000000
--- a/arch/mips/lemote/lm2e/prom.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Based on Ocelot Linux port, which is
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright 2003 ICT CAS
7 * Author: Michael Guo <guoyi@ict.ac.cn>
8 *
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/init.h>
18#include <linux/bootmem.h>
19#include <asm/bootinfo.h>
20
21extern unsigned long bus_clock;
22extern unsigned long cpu_clock_freq;
23extern unsigned int memsize, highmemsize;
24extern int putDebugChar(unsigned char byte);
25
26static int argc;
27/* pmon passes arguments in 32bit pointers */
28static int *arg;
29static int *env;
30
31const char *get_system_type(void)
32{
33 return "lemote-fulong";
34}
35
36void __init prom_init_cmdline(void)
37{
38 int i;
39 long l;
40
41 /* arg[0] is "g", the rest is boot parameters */
42 arcs_cmdline[0] = '\0';
43 for (i = 1; i < argc; i++) {
44 l = (long)arg[i];
45 if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
46 >= sizeof(arcs_cmdline))
47 break;
48 strcat(arcs_cmdline, ((char *)l));
49 strcat(arcs_cmdline, " ");
50 }
51}
52
53void __init prom_init(void)
54{
55 long l;
56 argc = fw_arg0;
57 arg = (int *)fw_arg1;
58 env = (int *)fw_arg2;
59
60 prom_init_cmdline();
61
62 if ((strstr(arcs_cmdline, "console=")) == NULL)
63 strcat(arcs_cmdline, " console=ttyS0,115200");
64 if ((strstr(arcs_cmdline, "root=")) == NULL)
65 strcat(arcs_cmdline, " root=/dev/hda1");
66
67#define parse_even_earlier(res, option, p) \
68do { \
69 if (strncmp(option, (char *)p, strlen(option)) == 0) \
70 res = simple_strtol((char *)p + strlen(option"="), \
71 NULL, 10); \
72} while (0)
73
74 l = (long)*env;
75 while (l != 0) {
76 parse_even_earlier(bus_clock, "busclock", l);
77 parse_even_earlier(cpu_clock_freq, "cpuclock", l);
78 parse_even_earlier(memsize, "memsize", l);
79 parse_even_earlier(highmemsize, "highmemsize", l);
80 env++;
81 l = (long)*env;
82 }
83 if (memsize == 0)
84 memsize = 256;
85
86 pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n",
87 bus_clock, cpu_clock_freq, memsize, highmemsize);
88}
89
90void __init prom_free_prom_memory(void)
91{
92}
93
94void prom_putchar(char c)
95{
96 putDebugChar(c);
97}
diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c
deleted file mode 100644
index 099387a3827a..000000000000
--- a/arch/mips/lemote/lm2e/reset.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
8 * Author: Fuxin Zhang, zhangfx@lemote.com
9 */
10#include <linux/pm.h>
11
12#include <asm/reboot.h>
13
14static void loongson2e_restart(char *command)
15{
16#ifdef CONFIG_32BIT
17 *(unsigned long *)0xbfe00104 &= ~(1 << 2);
18 *(unsigned long *)0xbfe00104 |= (1 << 2);
19#else
20 *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2);
21 *(unsigned long *)0xffffffffbfe00104 |= (1 << 2);
22#endif
23 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
24}
25
26static void loongson2e_halt(void)
27{
28 while (1) ;
29}
30
31static void loongson2e_power_off(void)
32{
33 loongson2e_halt();
34}
35
36void mips_reboot_setup(void)
37{
38 _machine_restart = loongson2e_restart;
39 _machine_halt = loongson2e_halt;
40 pm_power_off = loongson2e_power_off;
41}
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
deleted file mode 100644
index ebd6ceaef2fd..000000000000
--- a/arch/mips/lemote/lm2e/setup.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * setup.c - board dependent boot routines
4 *
5 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
6 * Author: Fuxin Zhang, zhangfx@lemote.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 */
29#include <linux/bootmem.h>
30#include <linux/init.h>
31#include <linux/irq.h>
32
33#include <asm/bootinfo.h>
34#include <asm/mc146818-time.h>
35#include <asm/time.h>
36#include <asm/wbflush.h>
37#include <asm/mach-lemote/pci.h>
38
39#ifdef CONFIG_VT
40#include <linux/console.h>
41#include <linux/screen_info.h>
42#endif
43
44extern void mips_reboot_setup(void);
45
46unsigned long cpu_clock_freq;
47unsigned long bus_clock;
48unsigned int memsize;
49unsigned int highmemsize = 0;
50
51void __init plat_time_init(void)
52{
53 /* setup mips r4k timer */
54 mips_hpt_frequency = cpu_clock_freq / 2;
55}
56
57unsigned long read_persistent_clock(void)
58{
59 return mc146818_get_cmos_time();
60}
61
62void (*__wbflush)(void);
63EXPORT_SYMBOL(__wbflush);
64
65static void wbflush_loongson2e(void)
66{
67 asm(".set\tpush\n\t"
68 ".set\tnoreorder\n\t"
69 ".set mips3\n\t"
70 "sync\n\t"
71 "nop\n\t"
72 ".set\tpop\n\t"
73 ".set mips0\n\t");
74}
75
76void __init plat_mem_setup(void)
77{
78 set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE,
79 IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1));
80 mips_reboot_setup();
81
82 __wbflush = wbflush_loongson2e;
83
84 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
85#ifdef CONFIG_64BIT
86 if (highmemsize > 0) {
87 add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM);
88 }
89#endif
90
91#ifdef CONFIG_VT
92#if defined(CONFIG_VGA_CONSOLE)
93 conswitchp = &vga_con;
94
95 screen_info = (struct screen_info) {
96 0, 25, /* orig-x, orig-y */
97 0, /* unused */
98 0, /* orig-video-page */
99 0, /* orig-video-mode */
100 80, /* orig-video-cols */
101 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
102 25, /* orig-video-lines */
103 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
104 16 /* orig-video-points */
105 };
106#elif defined(CONFIG_DUMMY_CONSOLE)
107 conswitchp = &dummy_con;
108#endif
109#endif
110
111}
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
new file mode 100644
index 000000000000..d45092505fa1
--- /dev/null
+++ b/arch/mips/loongson/Kconfig
@@ -0,0 +1,31 @@
1choice
2 prompt "Machine Type"
3 depends on MACH_LOONGSON
4
5config LEMOTE_FULOONG2E
6 bool "Lemote Fuloong(2e) mini-PC"
7 select ARCH_SPARSEMEM_ENABLE
8 select CEVT_R4K
9 select CSRC_R4K
10 select SYS_HAS_CPU_LOONGSON2E
11 select DMA_NONCOHERENT
12 select BOOT_ELF32
13 select BOARD_SCACHE
14 select HW_HAS_PCI
15 select I8259
16 select ISA
17 select IRQ_CPU
18 select SYS_SUPPORTS_32BIT_KERNEL
19 select SYS_SUPPORTS_64BIT_KERNEL
20 select SYS_SUPPORTS_LITTLE_ENDIAN
21 select SYS_SUPPORTS_HIGHMEM
22 select SYS_HAS_EARLY_PRINTK
23 select GENERIC_HARDIRQS_NO__DO_IRQ
24 select GENERIC_ISA_DMA_SUPPORT_BROKEN
25 select CPU_HAS_WB
26 help
27 Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
28 an FPGA northbridge
29
30 Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
31endchoice
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
new file mode 100644
index 000000000000..39048c455d7d
--- /dev/null
+++ b/arch/mips/loongson/Makefile
@@ -0,0 +1,11 @@
1#
2# Common code for all Loongson based systems
3#
4
5obj-$(CONFIG_MACH_LOONGSON) += common/
6
7#
8# Lemote Fuloong mini-PC (Loongson 2E-based)
9#
10
11obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
new file mode 100644
index 000000000000..656b3cc0a2a6
--- /dev/null
+++ b/arch/mips/loongson/common/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for loongson based machines.
3#
4
5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6 pci.o bonito-irq.o mem.o machtype.o
7
8#
9# Early printk support
10#
11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 8fc3bce7075b..3e31e7ad713e 100644
--- a/arch/mips/lemote/lm2e/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -10,32 +10,10 @@
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 */ 13 */
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/io.h>
33#include <linux/types.h>
34#include <linux/interrupt.h> 14#include <linux/interrupt.h>
35#include <linux/irq.h>
36
37#include <asm/mips-boards/bonito64.h>
38 15
16#include <loongson.h>
39 17
40static inline void bonito_irq_enable(unsigned int irq) 18static inline void bonito_irq_enable(unsigned int irq)
41{ 19{
@@ -66,9 +44,8 @@ void bonito_irq_init(void)
66{ 44{
67 u32 i; 45 u32 i;
68 46
69 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) { 47 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++)
70 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 48 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
71 }
72 49
73 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); 50 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction);
74} 51}
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
new file mode 100644
index 000000000000..75f1b243ee4e
--- /dev/null
+++ b/arch/mips/loongson/common/cmdline.c
@@ -0,0 +1,52 @@
1/*
2 * Based on Ocelot Linux port, which is
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright 2003 ICT CAS
7 * Author: Michael Guo <guoyi@ict.ac.cn>
8 *
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 *
12 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
13 * Author: Wu Zhangjin, wuzj@lemote.com
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20#include <asm/bootinfo.h>
21
22#include <loongson.h>
23
24int prom_argc;
25/* pmon passes arguments in 32bit pointers */
26int *_prom_argv;
27
28void __init prom_init_cmdline(void)
29{
30 int i;
31 long l;
32
33 /* firmware arguments are initialized in head.S */
34 prom_argc = fw_arg0;
35 _prom_argv = (int *)fw_arg1;
36
37 /* arg[0] is "g", the rest is boot parameters */
38 arcs_cmdline[0] = '\0';
39 for (i = 1; i < prom_argc; i++) {
40 l = (long)_prom_argv[i];
41 if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
42 >= sizeof(arcs_cmdline))
43 break;
44 strcat(arcs_cmdline, ((char *)l));
45 strcat(arcs_cmdline, " ");
46 }
47
48 if ((strstr(arcs_cmdline, "console=")) == NULL)
49 strcat(arcs_cmdline, " console=ttyS0,115200");
50 if ((strstr(arcs_cmdline, "root=")) == NULL)
51 strcat(arcs_cmdline, " root=/dev/hda1");
52}
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
new file mode 100644
index 000000000000..bc73edc0cfd8
--- /dev/null
+++ b/arch/mips/loongson/common/early_printk.c
@@ -0,0 +1,38 @@
1/* early printk support
2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
5 * Author: Wu Zhangjin, wuzj@lemote.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/serial_reg.h>
13
14#include <loongson.h>
15#include <machine.h>
16
17#define PORT(base, offset) (u8 *)(base + offset)
18
19static inline unsigned int serial_in(phys_addr_t base, int offset)
20{
21 return readb(PORT(base, offset));
22}
23
24static inline void serial_out(phys_addr_t base, int offset, int value)
25{
26 writeb(value, PORT(base, offset));
27}
28
29void prom_putchar(char c)
30{
31 phys_addr_t uart_base =
32 (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8);
33
34 while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0)
35 ;
36
37 serial_out(uart_base, UART_TX, c);
38}
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
new file mode 100644
index 000000000000..b9ef50385541
--- /dev/null
+++ b/arch/mips/loongson/common/env.c
@@ -0,0 +1,58 @@
1/*
2 * Based on Ocelot Linux port, which is
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright 2003 ICT CAS
7 * Author: Michael Guo <guoyi@ict.ac.cn>
8 *
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 *
12 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
13 * Author: Wu Zhangjin, wuzj@lemote.com
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20#include <asm/bootinfo.h>
21
22#include <loongson.h>
23
24unsigned long bus_clock, cpu_clock_freq;
25unsigned long memsize, highmemsize;
26
27/* pmon passes arguments in 32bit pointers */
28int *_prom_envp;
29
30#define parse_even_earlier(res, option, p) \
31do { \
32 if (strncmp(option, (char *)p, strlen(option)) == 0) \
33 strict_strtol((char *)p + strlen(option"="), \
34 10, &res); \
35} while (0)
36
37void __init prom_init_env(void)
38{
39 long l;
40
41 /* firmware arguments are initialized in head.S */
42 _prom_envp = (int *)fw_arg2;
43
44 l = (long)*_prom_envp;
45 while (l != 0) {
46 parse_even_earlier(bus_clock, "busclock", l);
47 parse_even_earlier(cpu_clock_freq, "cpuclock", l);
48 parse_even_earlier(memsize, "memsize", l);
49 parse_even_earlier(highmemsize, "highmemsize", l);
50 _prom_envp++;
51 l = (long)*_prom_envp;
52 }
53 if (memsize == 0)
54 memsize = 256;
55
56 pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n",
57 bus_clock, cpu_clock_freq, memsize, highmemsize);
58}
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
new file mode 100644
index 000000000000..3abe927422a3
--- /dev/null
+++ b/arch/mips/loongson/common/init.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
3 * Author: Wu Zhangjin, wuzj@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/bootmem.h>
12
13#include <asm/bootinfo.h>
14
15#include <loongson.h>
16
17void __init prom_init(void)
18{
19 /* init base address of io space */
20 set_io_port_base((unsigned long)
21 ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE));
22
23 prom_init_cmdline();
24 prom_init_env();
25 prom_init_memory();
26}
27
28void __init prom_free_prom_memory(void)
29{
30}
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
new file mode 100644
index 000000000000..f368c735cbd3
--- /dev/null
+++ b/arch/mips/loongson/common/irq.c
@@ -0,0 +1,74 @@
1/*
2 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/delay.h>
11#include <linux/interrupt.h>
12
13#include <loongson.h>
14/*
15 * the first level int-handler will jump here if it is a bonito irq
16 */
17void bonito_irqdispatch(void)
18{
19 u32 int_status;
20 int i;
21
22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23 int_status = BONITO_INTISR;
24 if (int_status & (1 << 10)) {
25 while (int_status & (1 << 10)) {
26 udelay(1);
27 int_status = BONITO_INTISR;
28 }
29 }
30
31 /* Get pending sources, masked by current enables */
32 int_status = BONITO_INTISR & BONITO_INTEN;
33
34 if (int_status != 0) {
35 i = __ffs(int_status);
36 int_status &= ~(1 << i);
37 do_IRQ(BONITO_IRQ_BASE + i);
38 }
39}
40
41asmlinkage void plat_irq_dispatch(void)
42{
43 unsigned int pending;
44
45 pending = read_c0_cause() & read_c0_status() & ST0_IM;
46
47 /* machine-specific plat_irq_dispatch */
48 mach_irq_dispatch(pending);
49}
50
51void __init arch_init_irq(void)
52{
53 /*
54 * Clear all of the interrupts while we change the able around a bit.
55 * int-handler is not on bootstrap
56 */
57 clear_c0_status(ST0_IM | ST0_BEV);
58 local_irq_disable();
59
60 /* setting irq trigger mode */
61 set_irq_trigger_mode();
62
63 /* no steer */
64 BONITO_INTSTEER = 0;
65
66 /*
67 * Mask out all interrupt by writing "1" to all bit position in
68 * the interrupt reset reg.
69 */
70 BONITO_INTENCLR = ~0;
71
72 /* machine specific irq init */
73 mach_init_irq();
74}
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
new file mode 100644
index 000000000000..7b348248de7d
--- /dev/null
+++ b/arch/mips/loongson/common/machtype.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
3 * Author: Wu Zhangjin, wuzj@lemote.com
4 *
5 * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/errno.h>
13#include <asm/bootinfo.h>
14
15#include <loongson.h>
16#include <machine.h>
17
18static const char *system_types[] = {
19 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine",
20 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box",
21 [MACH_LEMOTE_FL2F] "lemote-fuloong-2f-box",
22 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches",
23 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches",
24 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches",
25 [MACH_LOONGSON_END] NULL,
26};
27
28const char *get_system_type(void)
29{
30 if (mips_machtype == MACH_UNKNOWN)
31 mips_machtype = LOONGSON_MACHTYPE;
32
33 return system_types[mips_machtype];
34}
35
36static __init int machtype_setup(char *str)
37{
38 int machtype = MACH_LEMOTE_FL2E;
39
40 if (!str)
41 return -EINVAL;
42
43 for (; system_types[machtype]; machtype++)
44 if (strstr(system_types[machtype], str)) {
45 mips_machtype = machtype;
46 break;
47 }
48 return 0;
49}
50__setup("machtype=", machtype_setup);
diff --git a/arch/mips/lemote/lm2e/mem.c b/arch/mips/loongson/common/mem.c
index 16cd21587d34..7c92f79b6480 100644
--- a/arch/mips/lemote/lm2e/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -8,16 +8,28 @@
8#include <linux/fcntl.h> 8#include <linux/fcntl.h>
9#include <linux/mm.h> 9#include <linux/mm.h>
10 10
11#include <asm/bootinfo.h>
12
13#include <loongson.h>
14#include <mem.h>
15
16void __init prom_init_memory(void)
17{
18 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
19#ifdef CONFIG_64BIT
20 if (highmemsize > 0)
21 add_memory_region(LOONGSON_HIGHMEM_START,
22 highmemsize << 20, BOOT_MEM_RAM);
23#endif /* CONFIG_64BIT */
24}
25
11/* override of arch/mips/mm/cache.c: __uncached_access */ 26/* override of arch/mips/mm/cache.c: __uncached_access */
12int __uncached_access(struct file *file, unsigned long addr) 27int __uncached_access(struct file *file, unsigned long addr)
13{ 28{
14 if (file->f_flags & O_SYNC) 29 if (file->f_flags & O_SYNC)
15 return 1; 30 return 1;
16 31
17 /*
18 * On the Lemote Loongson 2e system, the peripheral registers
19 * reside between 0x1000:0000 and 0x2000:0000.
20 */
21 return addr >= __pa(high_memory) || 32 return addr >= __pa(high_memory) ||
22 ((addr >= 0x10000000) && (addr < 0x20000000)); 33 ((addr >= LOONGSON_MMIO_MEM_START) &&
34 (addr < LOONGSON_MMIO_MEM_END));
23} 35}
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
new file mode 100644
index 000000000000..a3a4abfb6c9a
--- /dev/null
+++ b/arch/mips/loongson/common/pci.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/pci.h>
11
12#include <pci.h>
13#include <loongson.h>
14
15static struct resource loongson_pci_mem_resource = {
16 .name = "pci memory space",
17 .start = LOONGSON_PCI_MEM_START,
18 .end = LOONGSON_PCI_MEM_END,
19 .flags = IORESOURCE_MEM,
20};
21
22static struct resource loongson_pci_io_resource = {
23 .name = "pci io space",
24 .start = LOONGSON_PCI_IO_START,
25 .end = IO_SPACE_LIMIT,
26 .flags = IORESOURCE_IO,
27};
28
29static struct pci_controller loongson_pci_controller = {
30 .pci_ops = &bonito64_pci_ops,
31 .io_resource = &loongson_pci_io_resource,
32 .mem_resource = &loongson_pci_mem_resource,
33 .mem_offset = 0x00000000UL,
34 .io_offset = 0x00000000UL,
35};
36
37static void __init setup_pcimap(void)
38{
39 /*
40 * local to PCI mapping for CPU accessing PCI space
41 * CPU address space [256M,448M] is window for accessing pci space
42 * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M]
43 *
44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
45 * [<2G] [384M,448M] [320M,384M] [0M,64M]
46 */
47 BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 |
48 BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) |
49 BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) |
50 BONITO_PCIMAP_WIN(0, 0);
51
52 /*
53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
54 */
55 BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */
57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
59 LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */
60 LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul;
61 LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */
62 LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul;
63
64 /* avoid deadlock of PCI reading/writing lock operation */
65 LOONGSON_PCI_ISR4C = 0xd2000001ul;
66
67 /* can not change gnt to break pci transfer when device's gnt not
68 deassert for some broken device */
69 LOONGSON_PXARB_CFG = 0x00fe0105ul;
70}
71
72static int __init pcibios_init(void)
73{
74 setup_pcimap();
75
76 loongson_pci_controller.io_map_base = mips_io_port_base;
77
78 register_pci_controller(&loongson_pci_controller);
79
80 return 0;
81}
82
83arch_initcall(pcibios_init);
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
new file mode 100644
index 000000000000..97e918251edd
--- /dev/null
+++ b/arch/mips/loongson/common/reset.c
@@ -0,0 +1,44 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
8 * Author: Fuxin Zhang, zhangfx@lemote.com
9 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
10 * Author: Zhangjin Wu, wuzj@lemote.com
11 */
12#include <linux/init.h>
13#include <linux/pm.h>
14
15#include <asm/reboot.h>
16
17#include <loongson.h>
18
19static void loongson_restart(char *command)
20{
21 /* do preparation for reboot */
22 mach_prepare_reboot();
23
24 /* reboot via jumping to boot base address */
25 ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) ();
26}
27
28static void loongson_halt(void)
29{
30 mach_prepare_shutdown();
31 while (1)
32 ;
33}
34
35static int __init mips_reboot_setup(void)
36{
37 _machine_restart = loongson_restart;
38 _machine_halt = loongson_halt;
39 pm_power_off = loongson_halt;
40
41 return 0;
42}
43
44arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c
new file mode 100644
index 000000000000..4cd2aa9a342c
--- /dev/null
+++ b/arch/mips/loongson/common/setup.c
@@ -0,0 +1,58 @@
1/*
2 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/module.h>
11
12#include <asm/wbflush.h>
13
14#include <loongson.h>
15
16#ifdef CONFIG_VT
17#include <linux/console.h>
18#include <linux/screen_info.h>
19#endif
20
21void (*__wbflush)(void);
22EXPORT_SYMBOL(__wbflush);
23
24static void wbflush_loongson(void)
25{
26 asm(".set\tpush\n\t"
27 ".set\tnoreorder\n\t"
28 ".set mips3\n\t"
29 "sync\n\t"
30 "nop\n\t"
31 ".set\tpop\n\t"
32 ".set mips0\n\t");
33}
34
35void __init plat_mem_setup(void)
36{
37 __wbflush = wbflush_loongson;
38
39#ifdef CONFIG_VT
40#if defined(CONFIG_VGA_CONSOLE)
41 conswitchp = &vga_con;
42
43 screen_info = (struct screen_info) {
44 0, 25, /* orig-x, orig-y */
45 0, /* unused */
46 0, /* orig-video-page */
47 0, /* orig-video-mode */
48 80, /* orig-video-cols */
49 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
50 25, /* orig-video-lines */
51 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
52 16 /* orig-video-points */
53 };
54#elif defined(CONFIG_DUMMY_CONSOLE)
55 conswitchp = &dummy_con;
56#endif
57#endif
58}
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
new file mode 100644
index 000000000000..b13d17174654
--- /dev/null
+++ b/arch/mips/loongson/common/time.c
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
6 * Author: Wu Zhangjin, wuzj@lemote.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <asm/mc146818-time.h>
14#include <asm/time.h>
15
16#include <loongson.h>
17
18void __init plat_time_init(void)
19{
20 /* setup mips r4k timer */
21 mips_hpt_frequency = cpu_clock_freq / 2;
22}
23
24unsigned long read_persistent_clock(void)
25{
26 return mc146818_get_cmos_time();
27}
diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile
new file mode 100644
index 000000000000..3aba5fcc09dc
--- /dev/null
+++ b/arch/mips/loongson/fuloong-2e/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for Lemote Fuloong2e mini-PC board.
3#
4
5obj-y += irq.o reset.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
new file mode 100644
index 000000000000..7888cf69424a
--- /dev/null
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/interrupt.h>
11
12#include <asm/irq_cpu.h>
13#include <asm/i8259.h>
14
15#include <loongson.h>
16
17static void i8259_irqdispatch(void)
18{
19 int irq;
20
21 irq = i8259_irq();
22 if (irq >= 0)
23 do_IRQ(irq);
24 else
25 spurious_interrupt();
26}
27
28asmlinkage void mach_irq_dispatch(unsigned int pending)
29{
30 if (pending & CAUSEF_IP7)
31 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
32 else if (pending & CAUSEF_IP6) /* perf counter loverflow */
33 do_IRQ(LOONGSON2_PERFCNT_IRQ);
34 else if (pending & CAUSEF_IP5)
35 i8259_irqdispatch();
36 else if (pending & CAUSEF_IP2)
37 bonito_irqdispatch();
38 else
39 spurious_interrupt();
40}
41
42static struct irqaction cascade_irqaction = {
43 .handler = no_action,
44 .name = "cascade",
45};
46
47void __init set_irq_trigger_mode(void)
48{
49 /* most bonito irq should be level triggered */
50 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
51 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
52}
53
54void __init mach_init_irq(void)
55{
56 /* init all controller
57 * 0-15 ------> i8259 interrupt
58 * 16-23 ------> mips cpu interrupt
59 * 32-63 ------> bonito irq
60 */
61
62 /* Sets the first-level interrupt dispatcher. */
63 mips_cpu_irq_init();
64 init_i8259_irqs();
65 bonito_irq_init();
66
67 /* bonito irq at IP2 */
68 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
69 /* 8259 irq at IP5 */
70 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
71}
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
new file mode 100644
index 000000000000..677fe186db95
--- /dev/null
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -0,0 +1,23 @@
1/* Board-specific reboot/shutdown routines
2 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
3 *
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
5 * Author: Wu Zhangjin, wuzj@lemote.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <loongson.h>
14
15void mach_prepare_reboot(void)
16{
17 BONITO_BONGENCFG &= ~(1 << 2);
18 BONITO_BONGENCFG |= (1 << 2);
19}
20
21void mach_prepare_shutdown(void)
22{
23}
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 7c7148ef2646..2877675c5f0d 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -37,7 +37,7 @@
37 37
38 38
39static void __init serial_init(void); 39static void __init serial_init(void);
40unsigned int _isbonito = 0; 40unsigned int _isbonito;
41 41
42const char *get_system_type(void) 42const char *get_system_type(void)
43{ 43{
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index f956ecbb8136..e97a7a2fb2c0 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -58,11 +58,17 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
58 * only copy the information from the master page table, 58 * only copy the information from the master page table,
59 * nothing more. 59 * nothing more.
60 */ 60 */
61#ifdef CONFIG_64BIT
62# define VMALLOC_FAULT_TARGET no_context
63#else
64# define VMALLOC_FAULT_TARGET vmalloc_fault
65#endif
66
61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) 67 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
62 goto vmalloc_fault; 68 goto VMALLOC_FAULT_TARGET;
63#ifdef MODULE_START 69#ifdef MODULE_START
64 if (unlikely(address >= MODULE_START && address < MODULE_END)) 70 if (unlikely(address >= MODULE_START && address < MODULE_END))
65 goto vmalloc_fault; 71 goto VMALLOC_FAULT_TARGET;
66#endif 72#endif
67 73
68 /* 74 /*
@@ -203,6 +209,7 @@ do_sigbus:
203 force_sig_info(SIGBUS, &info, tsk); 209 force_sig_info(SIGBUS, &info, tsk);
204 210
205 return; 211 return;
212#ifndef CONFIG_64BIT
206vmalloc_fault: 213vmalloc_fault:
207 { 214 {
208 /* 215 /*
@@ -241,4 +248,5 @@ vmalloc_fault:
241 goto no_context; 248 goto no_context;
242 return; 249 return;
243 } 250 }
251#endif
244} 252}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 0e820508ff23..38c79c55b060 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -475,9 +475,6 @@ unsigned long pgd_current[NR_CPUS];
475 */ 475 */
476pgd_t swapper_pg_dir[_PTRS_PER_PGD] __page_aligned(_PGD_ORDER); 476pgd_t swapper_pg_dir[_PTRS_PER_PGD] __page_aligned(_PGD_ORDER);
477#ifdef CONFIG_64BIT 477#ifdef CONFIG_64BIT
478#ifdef MODULE_START
479pgd_t module_pg_dir[PTRS_PER_PGD] __page_aligned(PGD_ORDER);
480#endif
481pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned(PMD_ORDER); 478pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned(PMD_ORDER);
482#endif 479#endif
483pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER); 480pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER);
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index e4b565aeb008..1121019fa456 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -59,9 +59,6 @@ void __init pagetable_init(void)
59 59
60 /* Initialize the entire pgd. */ 60 /* Initialize the entire pgd. */
61 pgd_init((unsigned long)swapper_pg_dir); 61 pgd_init((unsigned long)swapper_pg_dir);
62#ifdef MODULE_START
63 pgd_init((unsigned long)module_pg_dir);
64#endif
65 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); 62 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table);
66 63
67 pgd_base = swapper_pg_dir; 64 pgd_base = swapper_pg_dir;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index cee502caf398..d73428b18b0a 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -475,7 +475,7 @@ static void __cpuinit probe_tlb(unsigned long config)
475 c->tlbsize = ((reg >> 25) & 0x3f) + 1; 475 c->tlbsize = ((reg >> 25) & 0x3f) + 1;
476} 476}
477 477
478static int __cpuinitdata ntlb = 0; 478static int __cpuinitdata ntlb;
479static int __init set_ntlb(char *str) 479static int __init set_ntlb(char *str)
480{ 480{
481 get_option(&str, &ntlb); 481 get_option(&str, &ntlb);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 9a17bf8395df..bb1719a55d22 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -321,6 +321,10 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
321 case CPU_BCM3302: 321 case CPU_BCM3302:
322 case CPU_BCM4710: 322 case CPU_BCM4710:
323 case CPU_LOONGSON2: 323 case CPU_LOONGSON2:
324 case CPU_BCM6338:
325 case CPU_BCM6345:
326 case CPU_BCM6348:
327 case CPU_BCM6358:
324 case CPU_R5500: 328 case CPU_R5500:
325 if (m4kc_tlbp_war()) 329 if (m4kc_tlbp_war())
326 uasm_i_nop(p); 330 uasm_i_nop(p);
@@ -499,11 +503,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
499 * The vmalloc handling is not in the hotpath. 503 * The vmalloc handling is not in the hotpath.
500 */ 504 */
501 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 505 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
502#ifdef MODULE_START
503 uasm_il_bltz(p, r, tmp, label_module_alloc);
504#else
505 uasm_il_bltz(p, r, tmp, label_vmalloc); 506 uasm_il_bltz(p, r, tmp, label_vmalloc);
506#endif
507 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 507 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
508 508
509#ifdef CONFIG_SMP 509#ifdef CONFIG_SMP
@@ -556,52 +556,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
556{ 556{
557 long swpd = (long)swapper_pg_dir; 557 long swpd = (long)swapper_pg_dir;
558 558
559#ifdef MODULE_START
560 long modd = (long)module_pg_dir;
561
562 uasm_l_module_alloc(l, *p);
563 /*
564 * Assumption:
565 * VMALLOC_START >= 0xc000000000000000UL
566 * MODULE_START >= 0xe000000000000000UL
567 */
568 UASM_i_SLL(p, ptr, bvaddr, 2);
569 uasm_il_bgez(p, r, ptr, label_vmalloc);
570
571 if (uasm_in_compat_space_p(MODULE_START) &&
572 !uasm_rel_lo(MODULE_START)) {
573 uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */
574 } else {
575 /* unlikely configuration */
576 uasm_i_nop(p); /* delay slot */
577 UASM_i_LA(p, ptr, MODULE_START);
578 }
579 uasm_i_dsubu(p, bvaddr, bvaddr, ptr);
580
581 if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) {
582 uasm_il_b(p, r, label_vmalloc_done);
583 uasm_i_lui(p, ptr, uasm_rel_hi(modd));
584 } else {
585 UASM_i_LA_mostly(p, ptr, modd);
586 uasm_il_b(p, r, label_vmalloc_done);
587 if (uasm_in_compat_space_p(modd))
588 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd));
589 else
590 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd));
591 }
592
593 uasm_l_vmalloc(l, *p); 559 uasm_l_vmalloc(l, *p);
594 if (uasm_in_compat_space_p(MODULE_START) &&
595 !uasm_rel_lo(MODULE_START) &&
596 MODULE_START << 32 == VMALLOC_START)
597 uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */
598 else
599 UASM_i_LA(p, ptr, VMALLOC_START);
600#else
601 uasm_l_vmalloc(l, *p);
602 UASM_i_LA(p, ptr, VMALLOC_START);
603#endif
604 uasm_i_dsubu(p, bvaddr, bvaddr, ptr);
605 560
606 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { 561 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
607 uasm_il_b(p, r, label_vmalloc_done); 562 uasm_il_b(p, r, label_vmalloc_done);
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 27c807b67fea..f1b14c8a4a1c 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -47,7 +47,7 @@ int *_prom_argv, *_prom_envp;
47 */ 47 */
48#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) 48#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
49 49
50int init_debug = 0; 50int init_debug;
51 51
52static int mips_revision_corid; 52static int mips_revision_corid;
53int mips_revision_sconid; 53int mips_revision_sconid;
diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c
index f48d60e84290..329420536241 100644
--- a/arch/mips/mti-malta/malta-reset.c
+++ b/arch/mips/mti-malta/malta-reset.c
@@ -22,6 +22,7 @@
22 * Reset the MIPS boards. 22 * Reset the MIPS boards.
23 * 23 *
24 */ 24 */
25#include <linux/init.h>
25#include <linux/pm.h> 26#include <linux/pm.h>
26 27
27#include <asm/io.h> 28#include <asm/io.h>
@@ -45,9 +46,13 @@ static void mips_machine_halt(void)
45} 46}
46 47
47 48
48void mips_reboot_setup(void) 49static int __init mips_reboot_setup(void)
49{ 50{
50 _machine_restart = mips_machine_restart; 51 _machine_restart = mips_machine_restart;
51 _machine_halt = mips_machine_halt; 52 _machine_halt = mips_machine_halt;
52 pm_power_off = mips_machine_halt; 53 pm_power_off = mips_machine_halt;
54
55 return 0;
53} 56}
57
58arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index dc78b8983eeb..b7f37d4982fa 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -218,7 +218,6 @@ void __init plat_mem_setup(void)
218#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 218#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
219 screen_info_setup(); 219 screen_info_setup();
220#endif 220#endif
221 mips_reboot_setup();
222 221
223 board_be_init = malta_be_init; 222 board_be_init = malta_be_init;
224 board_be_handler = malta_be_handler; 223 board_be_handler = malta_be_handler;
diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/nxp/pnx833x/stb22x/board.c
index 90cc604bdadf..644eb7c3210f 100644
--- a/arch/mips/nxp/pnx833x/stb22x/board.c
+++ b/arch/mips/nxp/pnx833x/stb22x/board.c
@@ -39,7 +39,7 @@
39#define PNX8335_DEBUG7 0x441c 39#define PNX8335_DEBUG7 0x441c
40 40
41int prom_argc; 41int prom_argc;
42char **prom_argv = 0, **prom_envp = 0; 42char **prom_argv, **prom_envp;
43 43
44extern void prom_init_cmdline(void); 44extern void prom_init_cmdline(void);
45extern char *prom_getenv(char *envname); 45extern char *prom_getenv(char *envname);
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/nxp/pnx8550/common/proc.c
index acf1fa889444..af094cd1d85b 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/nxp/pnx8550/common/proc.c
@@ -69,9 +69,9 @@ static int pnx8550_registers_read(char* page, char** start, off_t offset, int co
69 return len; 69 return len;
70} 70}
71 71
72static struct proc_dir_entry* pnx8550_dir = NULL; 72static struct proc_dir_entry* pnx8550_dir;
73static struct proc_dir_entry* pnx8550_timers = NULL; 73static struct proc_dir_entry* pnx8550_timers;
74static struct proc_dir_entry* pnx8550_registers = NULL; 74static struct proc_dir_entry* pnx8550_registers;
75 75
76static int pnx8550_proc_init( void ) 76static int pnx8550_proc_init( void )
77{ 77{
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index bf3be6fcf7ff..02cc65e52d11 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -15,3 +15,4 @@ oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o 15oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
16oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o 16oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
17oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o 17oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
18oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 3bf3354547f6..7832ad257a14 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -16,6 +16,7 @@
16 16
17extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak)); 17extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak));
18extern struct op_mips_model op_model_rm9000_ops __attribute__((weak)); 18extern struct op_mips_model op_model_rm9000_ops __attribute__((weak));
19extern struct op_mips_model op_model_loongson2_ops __attribute__((weak));
19 20
20static struct op_mips_model *model; 21static struct op_mips_model *model;
21 22
@@ -93,6 +94,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
93 case CPU_RM9000: 94 case CPU_RM9000:
94 lmodel = &op_model_rm9000_ops; 95 lmodel = &op_model_rm9000_ops;
95 break; 96 break;
97 case CPU_LOONGSON2:
98 lmodel = &op_model_loongson2_ops;
99 break;
96 }; 100 };
97 101
98 if (!lmodel) 102 if (!lmodel)
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
new file mode 100644
index 000000000000..655cb8dec340
--- /dev/null
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -0,0 +1,177 @@
1/*
2 * Loongson2 performance counter driver for oprofile
3 *
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
5 * Author: Yanhua <yanh@lemote.com>
6 * Author: Wu Zhangjin <wuzj@lemote.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 */
13#include <linux/init.h>
14#include <linux/oprofile.h>
15#include <linux/interrupt.h>
16
17#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
18#include "op_impl.h"
19
20/*
21 * a patch should be sent to oprofile with the loongson-specific support.
22 * otherwise, the oprofile tool will not recognize this and complain about
23 * "cpu_type 'unset' is not valid".
24 */
25#define LOONGSON2_CPU_TYPE "mips/godson2"
26
27#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5)
28#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
29
30#define LOONGSON2_PERFCNT_EXL (1UL << 0)
31#define LOONGSON2_PERFCNT_KERNEL (1UL << 1)
32#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2)
33#define LOONGSON2_PERFCNT_USER (1UL << 3)
34#define LOONGSON2_PERFCNT_INT_EN (1UL << 4)
35#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
36
37/* Loongson2 performance counter register */
38#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
39#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
40#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
41#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
42
43static struct loongson2_register_config {
44 unsigned int ctrl;
45 unsigned long long reset_counter1;
46 unsigned long long reset_counter2;
47 int cnt1_enalbed, cnt2_enalbed;
48} reg;
49
50DEFINE_SPINLOCK(sample_lock);
51
52static char *oprofid = "LoongsonPerf";
53static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
54/* Compute all of the registers in preparation for enabling profiling. */
55
56static void loongson2_reg_setup(struct op_counter_config *cfg)
57{
58 unsigned int ctrl = 0;
59
60 reg.reset_counter1 = 0;
61 reg.reset_counter2 = 0;
62 /* Compute the performance counter ctrl word. */
63 /* For now count kernel and user mode */
64 if (cfg[0].enabled) {
65 ctrl |= LOONGSON2_COUNTER1_EVENT(cfg[0].event);
66 reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
67 }
68
69 if (cfg[1].enabled) {
70 ctrl |= LOONGSON2_COUNTER2_EVENT(cfg[1].event);
71 reg.reset_counter2 = (0x80000000ULL - cfg[1].count);
72 }
73
74 if (cfg[0].enabled || cfg[1].enabled) {
75 ctrl |= LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_INT_EN;
76 if (cfg[0].kernel || cfg[1].kernel)
77 ctrl |= LOONGSON2_PERFCNT_KERNEL;
78 if (cfg[0].user || cfg[1].user)
79 ctrl |= LOONGSON2_PERFCNT_USER;
80 }
81
82 reg.ctrl = ctrl;
83
84 reg.cnt1_enalbed = cfg[0].enabled;
85 reg.cnt2_enalbed = cfg[1].enabled;
86
87}
88
89/* Program all of the registers in preparation for enabling profiling. */
90
91static void loongson2_cpu_setup(void *args)
92{
93 uint64_t perfcount;
94
95 perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1;
96 write_c0_perfcnt(perfcount);
97}
98
99static void loongson2_cpu_start(void *args)
100{
101 /* Start all counters on current CPU */
102 if (reg.cnt1_enalbed || reg.cnt2_enalbed)
103 write_c0_perfctrl(reg.ctrl);
104}
105
106static void loongson2_cpu_stop(void *args)
107{
108 /* Stop all counters on current CPU */
109 write_c0_perfctrl(0);
110 memset(&reg, 0, sizeof(reg));
111}
112
113static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
114{
115 uint64_t counter, counter1, counter2;
116 struct pt_regs *regs = get_irq_regs();
117 int enabled;
118 unsigned long flags;
119
120 /*
121 * LOONGSON2 defines two 32-bit performance counters.
122 * To avoid a race updating the registers we need to stop the counters
123 * while we're messing with
124 * them ...
125 */
126
127 /* Check whether the irq belongs to me */
128 enabled = reg.cnt1_enalbed | reg.cnt2_enalbed;
129 if (!enabled)
130 return IRQ_NONE;
131
132 counter = read_c0_perfcnt();
133 counter1 = counter & 0xffffffff;
134 counter2 = counter >> 32;
135
136 spin_lock_irqsave(&sample_lock, flags);
137
138 if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
139 if (reg.cnt1_enalbed)
140 oprofile_add_sample(regs, 0);
141 counter1 = reg.reset_counter1;
142 }
143 if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
144 if (reg.cnt2_enalbed)
145 oprofile_add_sample(regs, 1);
146 counter2 = reg.reset_counter2;
147 }
148
149 spin_unlock_irqrestore(&sample_lock, flags);
150
151 write_c0_perfcnt((counter2 << 32) | counter1);
152
153 return IRQ_HANDLED;
154}
155
156static int __init loongson2_init(void)
157{
158 return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
159 IRQF_SHARED, "Perfcounter", oprofid);
160}
161
162static void loongson2_exit(void)
163{
164 write_c0_perfctrl(0);
165 free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
166}
167
168struct op_mips_model op_model_loongson2_ops = {
169 .reg_setup = loongson2_reg_setup,
170 .cpu_setup = loongson2_cpu_setup,
171 .init = loongson2_init,
172 .exit = loongson2_exit,
173 .cpu_start = loongson2_cpu_start,
174 .cpu_stop = loongson2_cpu_stop,
175 .cpu_type = LOONGSON2_CPU_TYPE,
176 .num_counters = 2
177};
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 63d8a297c58d..91bfe73a7f60 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
16obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o 16obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
17obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o 17obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o 18obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
20 ops-bcm63xx.o
19 21
20# 22#
21# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
@@ -26,7 +28,7 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
26obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
27obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
28obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
29obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o 31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o
30obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
31obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
32obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-bcm63xx.c b/arch/mips/pci/fixup-bcm63xx.c
new file mode 100644
index 000000000000..340863009da9
--- /dev/null
+++ b/arch/mips/pci/fixup-bcm63xx.c
@@ -0,0 +1,21 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <bcm63xx_cpu.h>
12
13int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
14{
15 return bcm63xx_get_irq_number(IRQ_PCI);
16}
17
18int pcibios_plat_dev_init(struct pci_dev *dev)
19{
20 return 0;
21}
diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-fuloong2e.c
index e18ae4f574c1..0c4c7a81213f 100644
--- a/arch/mips/pci/fixup-lm2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * fixup-lm2e.c
3 *
4 * Copyright (C) 2004 ICT CAS 2 * Copyright (C) 2004 ICT CAS
5 * Author: Li xiaoyu, ICT CAS 3 * Author: Li xiaoyu, ICT CAS
6 * lixy@ict.ac.cn 4 * lixy@ict.ac.cn
@@ -12,22 +10,6 @@
12 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version. 12 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */ 13 */
32#include <linux/init.h> 14#include <linux/init.h>
33#include <linux/pci.h> 15#include <linux/pci.h>
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
new file mode 100644
index 000000000000..822ae179bc56
--- /dev/null
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -0,0 +1,467 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15
16#include "pci-bcm63xx.h"
17
18/*
19 * swizzle 32bits data to return only the needed part
20 */
21static int postprocess_read(u32 data, int where, unsigned int size)
22{
23 u32 ret;
24
25 ret = 0;
26 switch (size) {
27 case 1:
28 ret = (data >> ((where & 3) << 3)) & 0xff;
29 break;
30 case 2:
31 ret = (data >> ((where & 3) << 3)) & 0xffff;
32 break;
33 case 4:
34 ret = data;
35 break;
36 }
37 return ret;
38}
39
40static int preprocess_write(u32 orig_data, u32 val, int where,
41 unsigned int size)
42{
43 u32 ret;
44
45 ret = 0;
46 switch (size) {
47 case 1:
48 ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
49 (val << ((where & 3) << 3));
50 break;
51 case 2:
52 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
53 (val << ((where & 3) << 3));
54 break;
55 case 4:
56 ret = val;
57 break;
58 }
59 return ret;
60}
61
62/*
63 * setup hardware for a configuration cycle with given parameters
64 */
65static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
66 unsigned int devfn, int where)
67{
68 unsigned int slot, func, reg;
69 u32 val;
70
71 slot = PCI_SLOT(devfn);
72 func = PCI_FUNC(devfn);
73 reg = where >> 2;
74
75 /* sanity check */
76 if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
77 return 1;
78
79 if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
80 return 1;
81
82 if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
83 return 1;
84
85 /* ok, setup config access */
86 val = (reg << MPI_L2PCFG_REG_SHIFT);
87 val |= (func << MPI_L2PCFG_FUNC_SHIFT);
88 val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
89 val |= MPI_L2PCFG_CFG_USEREG_MASK;
90 val |= MPI_L2PCFG_CFG_SEL_MASK;
91 /* type 0 cycle for local bus, type 1 cycle for anything else */
92 if (type != 0) {
93 /* FIXME: how to specify bus ??? */
94 val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
95 }
96 bcm_mpi_writel(val, MPI_L2PCFG_REG);
97
98 return 0;
99}
100
101static int bcm63xx_do_cfg_read(int type, unsigned int busn,
102 unsigned int devfn, int where, int size,
103 u32 *val)
104{
105 u32 data;
106
107 /* two phase cycle, first we write address, then read data at
108 * another location, caller already has a spinlock so no need
109 * to add one here */
110 if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
111 return PCIBIOS_DEVICE_NOT_FOUND;
112 iob();
113 data = le32_to_cpu(__raw_readl(pci_iospace_start));
114 /* restore IO space normal behaviour */
115 bcm_mpi_writel(0, MPI_L2PCFG_REG);
116
117 *val = postprocess_read(data, where, size);
118
119 return PCIBIOS_SUCCESSFUL;
120}
121
122static int bcm63xx_do_cfg_write(int type, unsigned int busn,
123 unsigned int devfn, int where, int size,
124 u32 val)
125{
126 u32 data;
127
128 /* two phase cycle, first we write address, then write data to
129 * another location, caller already has a spinlock so no need
130 * to add one here */
131 if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
132 return PCIBIOS_DEVICE_NOT_FOUND;
133 iob();
134
135 data = le32_to_cpu(__raw_readl(pci_iospace_start));
136 data = preprocess_write(data, val, where, size);
137
138 __raw_writel(cpu_to_le32(data), pci_iospace_start);
139 wmb();
140 /* no way to know the access is done, we have to wait */
141 udelay(500);
142 /* restore IO space normal behaviour */
143 bcm_mpi_writel(0, MPI_L2PCFG_REG);
144
145 return PCIBIOS_SUCCESSFUL;
146}
147
148static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
149 int where, int size, u32 *val)
150{
151 int type;
152
153 type = bus->parent ? 1 : 0;
154
155 if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
156 return PCIBIOS_DEVICE_NOT_FOUND;
157
158 return bcm63xx_do_cfg_read(type, bus->number, devfn,
159 where, size, val);
160}
161
162static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
163 int where, int size, u32 val)
164{
165 int type;
166
167 type = bus->parent ? 1 : 0;
168
169 if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
170 return PCIBIOS_DEVICE_NOT_FOUND;
171
172 return bcm63xx_do_cfg_write(type, bus->number, devfn,
173 where, size, val);
174}
175
176struct pci_ops bcm63xx_pci_ops = {
177 .read = bcm63xx_pci_read,
178 .write = bcm63xx_pci_write
179};
180
181#ifdef CONFIG_CARDBUS
182/*
183 * emulate configuration read access on a cardbus bridge
184 */
185#define FAKE_CB_BRIDGE_SLOT 0x1e
186
187static int fake_cb_bridge_bus_number = -1;
188
189static struct {
190 u16 pci_command;
191 u8 cb_latency;
192 u8 subordinate_busn;
193 u8 cardbus_busn;
194 u8 pci_busn;
195 int bus_assigned;
196 u16 bridge_control;
197
198 u32 mem_base0;
199 u32 mem_limit0;
200 u32 mem_base1;
201 u32 mem_limit1;
202
203 u32 io_base0;
204 u32 io_limit0;
205 u32 io_base1;
206 u32 io_limit1;
207} fake_cb_bridge_regs;
208
209static int fake_cb_bridge_read(int where, int size, u32 *val)
210{
211 unsigned int reg;
212 u32 data;
213
214 data = 0;
215 reg = where >> 2;
216 switch (reg) {
217 case (PCI_VENDOR_ID >> 2):
218 case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
219 /* create dummy vendor/device id from our cpu id */
220 data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
221 break;
222
223 case (PCI_COMMAND >> 2):
224 data = (PCI_STATUS_DEVSEL_SLOW << 16);
225 data |= fake_cb_bridge_regs.pci_command;
226 break;
227
228 case (PCI_CLASS_REVISION >> 2):
229 data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
230 break;
231
232 case (PCI_CACHE_LINE_SIZE >> 2):
233 data = (PCI_HEADER_TYPE_CARDBUS << 16);
234 break;
235
236 case (PCI_INTERRUPT_LINE >> 2):
237 /* bridge control */
238 data = (fake_cb_bridge_regs.bridge_control << 16);
239 /* pin:intA line:0xff */
240 data |= (0x1 << 8) | 0xff;
241 break;
242
243 case (PCI_CB_PRIMARY_BUS >> 2):
244 data = (fake_cb_bridge_regs.cb_latency << 24);
245 data |= (fake_cb_bridge_regs.subordinate_busn << 16);
246 data |= (fake_cb_bridge_regs.cardbus_busn << 8);
247 data |= fake_cb_bridge_regs.pci_busn;
248 break;
249
250 case (PCI_CB_MEMORY_BASE_0 >> 2):
251 data = fake_cb_bridge_regs.mem_base0;
252 break;
253
254 case (PCI_CB_MEMORY_LIMIT_0 >> 2):
255 data = fake_cb_bridge_regs.mem_limit0;
256 break;
257
258 case (PCI_CB_MEMORY_BASE_1 >> 2):
259 data = fake_cb_bridge_regs.mem_base1;
260 break;
261
262 case (PCI_CB_MEMORY_LIMIT_1 >> 2):
263 data = fake_cb_bridge_regs.mem_limit1;
264 break;
265
266 case (PCI_CB_IO_BASE_0 >> 2):
267 /* | 1 for 32bits io support */
268 data = fake_cb_bridge_regs.io_base0 | 0x1;
269 break;
270
271 case (PCI_CB_IO_LIMIT_0 >> 2):
272 data = fake_cb_bridge_regs.io_limit0;
273 break;
274
275 case (PCI_CB_IO_BASE_1 >> 2):
276 /* | 1 for 32bits io support */
277 data = fake_cb_bridge_regs.io_base1 | 0x1;
278 break;
279
280 case (PCI_CB_IO_LIMIT_1 >> 2):
281 data = fake_cb_bridge_regs.io_limit1;
282 break;
283 }
284
285 *val = postprocess_read(data, where, size);
286 return PCIBIOS_SUCCESSFUL;
287}
288
289/*
290 * emulate configuration write access on a cardbus bridge
291 */
292static int fake_cb_bridge_write(int where, int size, u32 val)
293{
294 unsigned int reg;
295 u32 data, tmp;
296 int ret;
297
298 ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
299 if (ret != PCIBIOS_SUCCESSFUL)
300 return ret;
301
302 data = preprocess_write(data, val, where, size);
303
304 reg = where >> 2;
305 switch (reg) {
306 case (PCI_COMMAND >> 2):
307 fake_cb_bridge_regs.pci_command = (data & 0xffff);
308 break;
309
310 case (PCI_CB_PRIMARY_BUS >> 2):
311 fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
312 fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
313 fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
314 fake_cb_bridge_regs.pci_busn = data & 0xff;
315 if (fake_cb_bridge_regs.cardbus_busn)
316 fake_cb_bridge_regs.bus_assigned = 1;
317 break;
318
319 case (PCI_INTERRUPT_LINE >> 2):
320 tmp = (data >> 16) & 0xffff;
321 /* disable memory prefetch support */
322 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
323 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
324 fake_cb_bridge_regs.bridge_control = tmp;
325 break;
326
327 case (PCI_CB_MEMORY_BASE_0 >> 2):
328 fake_cb_bridge_regs.mem_base0 = data;
329 break;
330
331 case (PCI_CB_MEMORY_LIMIT_0 >> 2):
332 fake_cb_bridge_regs.mem_limit0 = data;
333 break;
334
335 case (PCI_CB_MEMORY_BASE_1 >> 2):
336 fake_cb_bridge_regs.mem_base1 = data;
337 break;
338
339 case (PCI_CB_MEMORY_LIMIT_1 >> 2):
340 fake_cb_bridge_regs.mem_limit1 = data;
341 break;
342
343 case (PCI_CB_IO_BASE_0 >> 2):
344 fake_cb_bridge_regs.io_base0 = data;
345 break;
346
347 case (PCI_CB_IO_LIMIT_0 >> 2):
348 fake_cb_bridge_regs.io_limit0 = data;
349 break;
350
351 case (PCI_CB_IO_BASE_1 >> 2):
352 fake_cb_bridge_regs.io_base1 = data;
353 break;
354
355 case (PCI_CB_IO_LIMIT_1 >> 2):
356 fake_cb_bridge_regs.io_limit1 = data;
357 break;
358 }
359
360 return PCIBIOS_SUCCESSFUL;
361}
362
363static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
364 int where, int size, u32 *val)
365{
366 /* snoop access to slot 0x1e on root bus, we fake a cardbus
367 * bridge at this location */
368 if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
369 fake_cb_bridge_bus_number = bus->number;
370 return fake_cb_bridge_read(where, size, val);
371 }
372
373 /* a configuration cycle for the device behind the cardbus
374 * bridge is actually done as a type 0 cycle on the primary
375 * bus. This means that only one device can be on the cardbus
376 * bus */
377 if (fake_cb_bridge_regs.bus_assigned &&
378 bus->number == fake_cb_bridge_regs.cardbus_busn &&
379 PCI_SLOT(devfn) == 0)
380 return bcm63xx_do_cfg_read(0, 0,
381 PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
382 where, size, val);
383
384 return PCIBIOS_DEVICE_NOT_FOUND;
385}
386
387static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
388 int where, int size, u32 val)
389{
390 if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
391 fake_cb_bridge_bus_number = bus->number;
392 return fake_cb_bridge_write(where, size, val);
393 }
394
395 if (fake_cb_bridge_regs.bus_assigned &&
396 bus->number == fake_cb_bridge_regs.cardbus_busn &&
397 PCI_SLOT(devfn) == 0)
398 return bcm63xx_do_cfg_write(0, 0,
399 PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
400 where, size, val);
401
402 return PCIBIOS_DEVICE_NOT_FOUND;
403}
404
405struct pci_ops bcm63xx_cb_ops = {
406 .read = bcm63xx_cb_read,
407 .write = bcm63xx_cb_write,
408};
409
410/*
411 * only one IO window, so it cannot be shared by PCI and cardbus, use
412 * fixup to choose and detect unhandled configuration
413 */
414static void bcm63xx_fixup(struct pci_dev *dev)
415{
416 static int io_window = -1;
417 int i, found, new_io_window;
418 u32 val;
419
420 /* look for any io resource */
421 found = 0;
422 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
423 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
424 found = 1;
425 break;
426 }
427 }
428
429 if (!found)
430 return;
431
432 /* skip our fake bus with only cardbus bridge on it */
433 if (dev->bus->number == fake_cb_bridge_bus_number)
434 return;
435
436 /* find on which bus the device is */
437 if (fake_cb_bridge_regs.bus_assigned &&
438 dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
439 PCI_SLOT(dev->devfn) == 0)
440 new_io_window = 1;
441 else
442 new_io_window = 0;
443
444 if (new_io_window == io_window)
445 return;
446
447 if (io_window != -1) {
448 printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
449 "need IO, which hardware cannot do\n");
450 return;
451 }
452
453 printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
454 (new_io_window == 0) ? "PCI" : "cardbus");
455
456 val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
457 if (io_window)
458 val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
459 else
460 val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
461 bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
462
463 io_window = new_io_window;
464}
465
466DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
467#endif
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index f742c51acf0d..54e55e7a2431 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,7 +29,7 @@
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32#ifdef CONFIG_LEMOTE_FULONG 32#ifdef CONFIG_LEMOTE_FULOONG2E
33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset)) 33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34#define ID_SEL_BEGIN 11 34#define ID_SEL_BEGIN 11
35#else 35#else
@@ -77,7 +77,7 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
77 addrp = CFG_SPACE_REG(addr & 0xffff); 77 addrp = CFG_SPACE_REG(addr & 0xffff);
78 if (access_type == PCI_ACCESS_WRITE) { 78 if (access_type == PCI_ACCESS_WRITE) {
79 writel(cpu_to_le32(*data), addrp); 79 writel(cpu_to_le32(*data), addrp);
80#ifndef CONFIG_LEMOTE_FULONG 80#ifndef CONFIG_LEMOTE_FULOONG2E
81 /* Wait till done */ 81 /* Wait till done */
82 while (BONITO_PCIMSTAT & 0xF); 82 while (BONITO_PCIMSTAT & 0xF);
83#endif 83#endif
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index a9060c771840..6f5e24c6ae67 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -57,7 +57,7 @@ static void *cfg_space;
57#define PCI_BUS_ENABLED 1 57#define PCI_BUS_ENABLED 1
58#define PCI_DEVICE_MODE 2 58#define PCI_DEVICE_MODE 2
59 59
60static int bcm1480_bus_status = 0; 60static int bcm1480_bus_status;
61 61
62#define PCI_BRIDGE_DEVICE 0 62#define PCI_BRIDGE_DEVICE 0
63 63
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index f54f45412b0b..50cc6e9e8240 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -56,7 +56,7 @@ static void *ht_cfg_space;
56#define PCI_BUS_ENABLED 1 56#define PCI_BUS_ENABLED 1
57#define PCI_DEVICE_MODE 2 57#define PCI_DEVICE_MODE 2
58 58
59static int bcm1480ht_bus_status = 0; 59static int bcm1480ht_bus_status;
60 60
61#define PCI_BRIDGE_DEVICE 0 61#define PCI_BRIDGE_DEVICE 0
62#define HT_BRIDGE_DEVICE 1 62#define HT_BRIDGE_DEVICE 1
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
new file mode 100644
index 000000000000..82e0fde1dba0
--- /dev/null
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -0,0 +1,224 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <asm/bootinfo.h>
14
15#include "pci-bcm63xx.h"
16
17/*
18 * Allow PCI to be disabled at runtime depending on board nvram
19 * configuration
20 */
21int bcm63xx_pci_enabled;
22
23static struct resource bcm_pci_mem_resource = {
24 .name = "bcm63xx PCI memory space",
25 .start = BCM_PCI_MEM_BASE_PA,
26 .end = BCM_PCI_MEM_END_PA,
27 .flags = IORESOURCE_MEM
28};
29
30static struct resource bcm_pci_io_resource = {
31 .name = "bcm63xx PCI IO space",
32 .start = BCM_PCI_IO_BASE_PA,
33#ifdef CONFIG_CARDBUS
34 .end = BCM_PCI_IO_HALF_PA,
35#else
36 .end = BCM_PCI_IO_END_PA,
37#endif
38 .flags = IORESOURCE_IO
39};
40
41struct pci_controller bcm63xx_controller = {
42 .pci_ops = &bcm63xx_pci_ops,
43 .io_resource = &bcm_pci_io_resource,
44 .mem_resource = &bcm_pci_mem_resource,
45};
46
47/*
48 * We handle cardbus via a fake Cardbus bridge, memory and io spaces
49 * have to be clearly separated from PCI one since we have different
50 * memory decoder.
51 */
52#ifdef CONFIG_CARDBUS
53static struct resource bcm_cb_mem_resource = {
54 .name = "bcm63xx Cardbus memory space",
55 .start = BCM_CB_MEM_BASE_PA,
56 .end = BCM_CB_MEM_END_PA,
57 .flags = IORESOURCE_MEM
58};
59
60static struct resource bcm_cb_io_resource = {
61 .name = "bcm63xx Cardbus IO space",
62 .start = BCM_PCI_IO_HALF_PA + 1,
63 .end = BCM_PCI_IO_END_PA,
64 .flags = IORESOURCE_IO
65};
66
67struct pci_controller bcm63xx_cb_controller = {
68 .pci_ops = &bcm63xx_cb_ops,
69 .io_resource = &bcm_cb_io_resource,
70 .mem_resource = &bcm_cb_mem_resource,
71};
72#endif
73
74static u32 bcm63xx_int_cfg_readl(u32 reg)
75{
76 u32 tmp;
77
78 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
79 tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
80 bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
81 iob();
82 return bcm_mpi_readl(MPI_PCICFGDATA_REG);
83}
84
85static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
86{
87 u32 tmp;
88
89 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
90 tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
91 bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
92 bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
93}
94
95void __iomem *pci_iospace_start;
96
97static int __init bcm63xx_pci_init(void)
98{
99 unsigned int mem_size;
100 u32 val;
101
102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
103 return -ENODEV;
104
105 if (!bcm63xx_pci_enabled)
106 return -ENODEV;
107
108 /*
109 * configuration access are done through IO space, remap 4
110 * first bytes to access it from CPU.
111 *
112 * this means that no io access from CPU should happen while
113 * we do a configuration cycle, but there's no way we can add
114 * a spinlock for each io access, so this is currently kind of
115 * broken on SMP.
116 */
117 pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
118 if (!pci_iospace_start)
119 return -ENOMEM;
120
121 /* setup local bus to PCI access (PCI memory) */
122 val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
123 bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
124 bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
125 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
126
127 /* set Cardbus IDSEL (type 0 cfg access on primary bus for
128 * this IDSEL will be done on Cardbus instead) */
129 val = bcm_pcmcia_readl(PCMCIA_C1_REG);
130 val &= ~PCMCIA_C1_CBIDSEL_MASK;
131 val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
132 bcm_pcmcia_writel(val, PCMCIA_C1_REG);
133
134#ifdef CONFIG_CARDBUS
135 /* setup local bus to PCI access (Cardbus memory) */
136 val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
137 bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
138 bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
139 val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
140 bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
141#else
142 /* disable second access windows */
143 bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
144#endif
145
146 /* setup local bus to PCI access (IO memory), we have only 1
147 * IO window for both PCI and cardbus, but it cannot handle
148 * both at the same time, assume standard PCI for now, if
149 * cardbus card has IO zone, PCI fixup will change window to
150 * cardbus */
151 val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
152 bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
153 bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
154 bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
155
156 /* enable PCI related GPIO pins */
157 bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
158
159 /* setup PCI to local bus access, used by PCI device to target
160 * local RAM while bus mastering */
161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
162 if (BCMCPU_IS_6358())
163 val = MPI_SP0_REMAP_ENABLE_MASK;
164 else
165 val = 0;
166 bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
167
168 bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
169 bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
170
171 mem_size = bcm63xx_get_memory_size();
172
173 /* 6348 before rev b0 exposes only 16 MB of RAM memory through
174 * PCI, throw a warning if we have more memory */
175 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
176 if (mem_size > (16 * 1024 * 1024))
177 printk(KERN_WARNING "bcm63xx: this CPU "
178 "revision cannot handle more than 16MB "
179 "of RAM for PCI bus mastering\n");
180 } else {
181 /* setup sp0 range to local RAM size */
182 bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
183 bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
184 }
185
186 /* change host bridge retry counter to infinite number of
187 * retry, needed for some broadcom wifi cards with Silicon
188 * Backplane bus where access to srom seems very slow */
189 val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
190 val &= ~REG_TIMER_RETRY_MASK;
191 bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
192
193 /* enable memory decoder and bus mastering */
194 val = bcm63xx_int_cfg_readl(PCI_COMMAND);
195 val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
196 bcm63xx_int_cfg_writel(val, PCI_COMMAND);
197
198 /* enable read prefetching & disable byte swapping for bus
199 * mastering transfers */
200 val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
201 val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
202 val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
203 val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
204 val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
205 bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
206
207 /* enable pci interrupt */
208 val = bcm_mpi_readl(MPI_LOCINT_REG);
209 val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
210 bcm_mpi_writel(val, MPI_LOCINT_REG);
211
212 register_pci_controller(&bcm63xx_controller);
213
214#ifdef CONFIG_CARDBUS
215 register_pci_controller(&bcm63xx_cb_controller);
216#endif
217
218 /* mark memory space used for IO mapping as reserved */
219 request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
220 "bcm63xx PCI IO space");
221 return 0;
222}
223
224arch_initcall(bcm63xx_pci_init);
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
new file mode 100644
index 000000000000..a6e594ef3d6a
--- /dev/null
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -0,0 +1,27 @@
1#ifndef PCI_BCM63XX_H_
2#define PCI_BCM63XX_H_
3
4#include <bcm63xx_cpu.h>
5#include <bcm63xx_io.h>
6#include <bcm63xx_regs.h>
7#include <bcm63xx_dev_pci.h>
8
9/*
10 * Cardbus shares the PCI bus, but has no IDSEL, so a special id is
11 * reserved for it. If you have a standard PCI device at this id, you
12 * need to change the following definition.
13 */
14#define CARDBUS_PCI_IDSEL 0x8
15
16/*
17 * defined in ops-bcm63xx.c
18 */
19extern struct pci_ops bcm63xx_pci_ops;
20extern struct pci_ops bcm63xx_cb_ops;
21
22/*
23 * defined in pci-bcm63xx.c
24 */
25extern void __iomem *pci_iospace_start;
26
27#endif /* ! PCI_BCM63XX_H_ */
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index bf639590b8b2..ada24e6f951f 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -58,7 +58,7 @@ static void *cfg_space;
58#define LDT_BUS_ENABLED 2 58#define LDT_BUS_ENABLED 2
59#define PCI_DEVICE_MODE 4 59#define PCI_DEVICE_MODE 4
60 60
61static int sb1250_bus_status = 0; 61static int sb1250_bus_status;
62 62
63#define PCI_BRIDGE_DEVICE 0 63#define PCI_BRIDGE_DEVICE 0
64#define LDT_BRIDGE_DEVICE 1 64#define LDT_BRIDGE_DEVICE 1
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index b0eb9e75c682..9a11c2226891 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -31,8 +31,8 @@ unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
31 31
32static struct pci_controller *hose_head, **hose_tail = &hose_head; 32static struct pci_controller *hose_head, **hose_tail = &hose_head;
33 33
34unsigned long PCIBIOS_MIN_IO = 0x0000; 34unsigned long PCIBIOS_MIN_IO;
35unsigned long PCIBIOS_MIN_MEM = 0; 35unsigned long PCIBIOS_MIN_MEM;
36 36
37static int pci_initialized; 37static int pci_initialized;
38 38
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 4b8174b382d7..0cf86fb32ec3 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -8,6 +8,7 @@
8 * Wu Zhangjin <wuzj@lemote.com> 8 * Wu Zhangjin <wuzj@lemote.com>
9 */ 9 */
10#include <asm/asm-offsets.h> 10#include <asm/asm-offsets.h>
11#include <asm/page.h>
11#include <asm/regdef.h> 12#include <asm/regdef.h>
12#include <asm/asm.h> 13#include <asm/asm.h>
13 14
@@ -34,7 +35,7 @@ LEAF(swsusp_arch_resume)
340: 350:
35 PTR_L t1, PBE_ADDRESS(t0) /* source */ 36 PTR_L t1, PBE_ADDRESS(t0) /* source */
36 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ 37 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
37 PTR_ADDIU t3, t1, _PAGE_SIZE 38 PTR_ADDIU t3, t1, PAGE_SIZE
381: 391:
39 REG_L t8, (t1) 40 REG_L t8, (t1)
40 REG_S t8, (t2) 41 REG_S t8, (t2)
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index ef1564e40c8d..416b18f9fa72 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -10,4 +10,4 @@ obj-$(CONFIG_SGI_IP22) += ip22-berr.o
10obj-$(CONFIG_SGI_IP28) += ip28-berr.o 10obj-$(CONFIG_SGI_IP28) += ip28-berr.o
11obj-$(CONFIG_EISA) += ip22-eisa.o 11obj-$(CONFIG_EISA) += ip22-eisa.o
12 12
13# EXTRA_CFLAGS += -Werror 13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 7b637a7c0e66..707cfa9c547d 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -341,6 +341,15 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
341} 341}
342#endif /* CONFIG_TOSHIBA_FPCIB0 */ 342#endif /* CONFIG_TOSHIBA_FPCIB0 */
343 343
344static void tc35815_fixup(struct pci_dev *dev)
345{
346 /* This device may have PM registers but not they are not suported. */
347 if (dev->pm_cap) {
348 dev_info(&dev->dev, "PM disabled\n");
349 dev->pm_cap = 0;
350 }
351}
352
344static void final_fixup(struct pci_dev *dev) 353static void final_fixup(struct pci_dev *dev)
345{ 354{
346 unsigned char bist; 355 unsigned char bist;
@@ -374,6 +383,10 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
374DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, 383DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
375 quirk_slc90e66_ide); 384 quirk_slc90e66_ide);
376#endif 385#endif
386DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
387 PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
389 PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
377DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); 390DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
378DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); 391DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
379 392
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index a205e2ba8e7b..c860810722c0 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -782,7 +782,7 @@ void __init txx9_iocled_init(unsigned long baseaddr,
782 return; 782 return;
783 iocled->mmioaddr = ioremap(baseaddr, 1); 783 iocled->mmioaddr = ioremap(baseaddr, 1);
784 if (!iocled->mmioaddr) 784 if (!iocled->mmioaddr)
785 return; 785 goto out_free;
786 iocled->chip.get = txx9_iocled_get; 786 iocled->chip.get = txx9_iocled_get;
787 iocled->chip.set = txx9_iocled_set; 787 iocled->chip.set = txx9_iocled_set;
788 iocled->chip.direction_input = txx9_iocled_dir_in; 788 iocled->chip.direction_input = txx9_iocled_dir_in;
@@ -791,13 +791,13 @@ void __init txx9_iocled_init(unsigned long baseaddr,
791 iocled->chip.base = basenum; 791 iocled->chip.base = basenum;
792 iocled->chip.ngpio = num; 792 iocled->chip.ngpio = num;
793 if (gpiochip_add(&iocled->chip)) 793 if (gpiochip_add(&iocled->chip))
794 return; 794 goto out_unmap;
795 if (basenum < 0) 795 if (basenum < 0)
796 basenum = iocled->chip.base; 796 basenum = iocled->chip.base;
797 797
798 pdev = platform_device_alloc("leds-gpio", basenum); 798 pdev = platform_device_alloc("leds-gpio", basenum);
799 if (!pdev) 799 if (!pdev)
800 return; 800 goto out_gpio;
801 iocled->pdata.num_leds = num; 801 iocled->pdata.num_leds = num;
802 iocled->pdata.leds = iocled->leds; 802 iocled->pdata.leds = iocled->leds;
803 for (i = 0; i < num; i++) { 803 for (i = 0; i < num; i++) {
@@ -812,7 +812,16 @@ void __init txx9_iocled_init(unsigned long baseaddr,
812 } 812 }
813 pdev->dev.platform_data = &iocled->pdata; 813 pdev->dev.platform_data = &iocled->pdata;
814 if (platform_device_add(pdev)) 814 if (platform_device_add(pdev))
815 platform_device_put(pdev); 815 goto out_pdev;
816 return;
817out_pdev:
818 platform_device_put(pdev);
819out_gpio:
820 gpio_remove(&iocled->chip);
821out_unmap:
822 iounmap(iocled->mmioaddr);
823out_free:
824 kfree(iocled);
816} 825}
817#else /* CONFIG_LEDS_GPIO */ 826#else /* CONFIG_LEDS_GPIO */
818void __init txx9_iocled_init(unsigned long baseaddr, 827void __init txx9_iocled_init(unsigned long baseaddr,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 03:48:00 -0500