1 files changed, 9 insertions, 6 deletions

diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 33fbae79af5e..f34ff8601942 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -36,14 +36,13 @@
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
 
+#include <asm/processor.h>
 #include <asm/time.h>
 #include <asm/mach-au1x00/au1000.h>
 
 /* 32kHz clock enabled and detected */
 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
 
-extern int allow_au1k_wait; /* default off for CP0 Counter */
-
 static cycle_t au1x_counter1_read(struct clocksource *cs)
 {
         return au_readl(SYS_RTCREAD);
@@ -153,13 +152,17 @@ void __init plat_time_init(void)
 
         printk(KERN_INFO "Alchemy clocksource installed\n");
 
-        /* can now use 'wait' */
-        allow_au1k_wait = 1;
         return;
 
 cntr_err:
-        /* counters unusable, use C0 counter */
+        /*
+         * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
+         * function is called.  Because the Alchemy counters are unusable
+         * the C0 timekeeping code is installed and use of the 'wait'
+         * instruction must be prohibited, which is done most easily by
+         * assigning NULL to cpu_wait.
+         */
+        cpu_wait = NULL;
         r4k_clockevent_init();
         init_r4k_clocksource();
-        allow_au1k_wait = 0;
 }