diff options
Diffstat (limited to 'arch/arm')
48 files changed, 10526 insertions, 510 deletions
diff --git a/arch/arm/configs/da830_omapl137_defconfig b/arch/arm/configs/da830_omapl137_defconfig new file mode 100644 index 000000000000..7c8e38f5c5ab --- /dev/null +++ b/arch/arm/configs/da830_omapl137_defconfig | |||
| @@ -0,0 +1,1254 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.30-rc2-davinci1 | ||
| 4 | # Wed May 13 15:33:29 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_LOCK_KERNEL=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | CONFIG_POSIX_MQUEUE=y | ||
| 43 | CONFIG_POSIX_MQUEUE_SYSCTL=y | ||
| 44 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 45 | # CONFIG_TASKSTATS is not set | ||
| 46 | # CONFIG_AUDIT is not set | ||
| 47 | |||
| 48 | # | ||
| 49 | # RCU Subsystem | ||
| 50 | # | ||
| 51 | CONFIG_CLASSIC_RCU=y | ||
| 52 | # CONFIG_TREE_RCU is not set | ||
| 53 | # CONFIG_PREEMPT_RCU is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 56 | CONFIG_IKCONFIG=y | ||
| 57 | CONFIG_IKCONFIG_PROC=y | ||
| 58 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 59 | CONFIG_GROUP_SCHED=y | ||
| 60 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 61 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 62 | CONFIG_USER_SCHED=y | ||
| 63 | # CONFIG_CGROUP_SCHED is not set | ||
| 64 | # CONFIG_CGROUPS is not set | ||
| 65 | CONFIG_SYSFS_DEPRECATED=y | ||
| 66 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 67 | # CONFIG_RELAY is not set | ||
| 68 | # CONFIG_NAMESPACES is not set | ||
| 69 | CONFIG_BLK_DEV_INITRD=y | ||
| 70 | CONFIG_INITRAMFS_SOURCE="" | ||
| 71 | CONFIG_RD_GZIP=y | ||
| 72 | # CONFIG_RD_BZIP2 is not set | ||
| 73 | # CONFIG_RD_LZMA is not set | ||
| 74 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 75 | CONFIG_SYSCTL=y | ||
| 76 | CONFIG_ANON_INODES=y | ||
| 77 | CONFIG_EMBEDDED=y | ||
| 78 | CONFIG_UID16=y | ||
| 79 | CONFIG_SYSCTL_SYSCALL=y | ||
| 80 | CONFIG_KALLSYMS=y | ||
| 81 | # CONFIG_KALLSYMS_ALL is not set | ||
| 82 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 83 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 84 | CONFIG_HOTPLUG=y | ||
| 85 | CONFIG_PRINTK=y | ||
| 86 | CONFIG_BUG=y | ||
| 87 | CONFIG_ELF_CORE=y | ||
| 88 | CONFIG_BASE_FULL=y | ||
| 89 | CONFIG_FUTEX=y | ||
| 90 | CONFIG_EPOLL=y | ||
| 91 | CONFIG_SIGNALFD=y | ||
| 92 | CONFIG_TIMERFD=y | ||
| 93 | CONFIG_EVENTFD=y | ||
| 94 | CONFIG_SHMEM=y | ||
| 95 | CONFIG_AIO=y | ||
| 96 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 97 | CONFIG_SLUB_DEBUG=y | ||
| 98 | CONFIG_COMPAT_BRK=y | ||
| 99 | # CONFIG_SLAB is not set | ||
| 100 | CONFIG_SLUB=y | ||
| 101 | # CONFIG_SLOB is not set | ||
| 102 | # CONFIG_PROFILING is not set | ||
| 103 | # CONFIG_MARKERS is not set | ||
| 104 | CONFIG_HAVE_OPROFILE=y | ||
| 105 | # CONFIG_KPROBES is not set | ||
| 106 | CONFIG_HAVE_KPROBES=y | ||
| 107 | CONFIG_HAVE_KRETPROBES=y | ||
| 108 | CONFIG_HAVE_CLK=y | ||
| 109 | # CONFIG_SLOW_WORK is not set | ||
| 110 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 111 | CONFIG_SLABINFO=y | ||
| 112 | CONFIG_RT_MUTEXES=y | ||
| 113 | CONFIG_BASE_SMALL=0 | ||
| 114 | CONFIG_MODULES=y | ||
| 115 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 116 | CONFIG_MODULE_UNLOAD=y | ||
| 117 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 118 | CONFIG_MODVERSIONS=y | ||
| 119 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 120 | CONFIG_BLOCK=y | ||
| 121 | # CONFIG_LBD is not set | ||
| 122 | # CONFIG_BLK_DEV_BSG is not set | ||
| 123 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 124 | |||
| 125 | # | ||
| 126 | # IO Schedulers | ||
| 127 | # | ||
| 128 | CONFIG_IOSCHED_NOOP=y | ||
| 129 | CONFIG_IOSCHED_AS=y | ||
| 130 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 131 | # CONFIG_IOSCHED_CFQ is not set | ||
| 132 | CONFIG_DEFAULT_AS=y | ||
| 133 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 134 | # CONFIG_DEFAULT_CFQ is not set | ||
| 135 | # CONFIG_DEFAULT_NOOP is not set | ||
| 136 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 137 | # CONFIG_FREEZER is not set | ||
| 138 | |||
| 139 | # | ||
| 140 | # System Type | ||
| 141 | # | ||
| 142 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 143 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 144 | # CONFIG_ARCH_REALVIEW is not set | ||
| 145 | # CONFIG_ARCH_VERSATILE is not set | ||
| 146 | # CONFIG_ARCH_AT91 is not set | ||
| 147 | # CONFIG_ARCH_CLPS711X is not set | ||
| 148 | # CONFIG_ARCH_EBSA110 is not set | ||
| 149 | # CONFIG_ARCH_EP93XX is not set | ||
| 150 | # CONFIG_ARCH_GEMINI is not set | ||
| 151 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 152 | # CONFIG_ARCH_NETX is not set | ||
| 153 | # CONFIG_ARCH_H720X is not set | ||
| 154 | # CONFIG_ARCH_IMX is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | ||
| 156 | # CONFIG_ARCH_IOP32X is not set | ||
| 157 | # CONFIG_ARCH_IOP33X is not set | ||
| 158 | # CONFIG_ARCH_IXP23XX is not set | ||
| 159 | # CONFIG_ARCH_IXP2000 is not set | ||
| 160 | # CONFIG_ARCH_IXP4XX is not set | ||
| 161 | # CONFIG_ARCH_L7200 is not set | ||
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 163 | # CONFIG_ARCH_KS8695 is not set | ||
| 164 | # CONFIG_ARCH_NS9XXX is not set | ||
| 165 | # CONFIG_ARCH_LOKI is not set | ||
| 166 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 167 | # CONFIG_ARCH_MXC is not set | ||
| 168 | # CONFIG_ARCH_ORION5X is not set | ||
| 169 | # CONFIG_ARCH_PNX4008 is not set | ||
| 170 | # CONFIG_ARCH_PXA is not set | ||
| 171 | # CONFIG_ARCH_MMP is not set | ||
| 172 | # CONFIG_ARCH_RPC is not set | ||
| 173 | # CONFIG_ARCH_SA1100 is not set | ||
| 174 | # CONFIG_ARCH_S3C2410 is not set | ||
| 175 | # CONFIG_ARCH_S3C64XX is not set | ||
| 176 | # CONFIG_ARCH_SHARK is not set | ||
| 177 | # CONFIG_ARCH_LH7A40X is not set | ||
| 178 | CONFIG_ARCH_DAVINCI=y | ||
| 179 | # CONFIG_ARCH_OMAP is not set | ||
| 180 | # CONFIG_ARCH_MSM is not set | ||
| 181 | # CONFIG_ARCH_W90X900 is not set | ||
| 182 | CONFIG_CP_INTC=y | ||
| 183 | |||
| 184 | # | ||
| 185 | # TI DaVinci Implementations | ||
| 186 | # | ||
| 187 | |||
| 188 | # | ||
| 189 | # DaVinci Core Type | ||
| 190 | # | ||
| 191 | # CONFIG_ARCH_DAVINCI_DM644x is not set | ||
| 192 | # CONFIG_ARCH_DAVINCI_DM646x is not set | ||
| 193 | # CONFIG_ARCH_DAVINCI_DM355 is not set | ||
| 194 | CONFIG_ARCH_DAVINCI_DA830=y | ||
| 195 | |||
| 196 | # | ||
| 197 | # DaVinci Board Type | ||
| 198 | # | ||
| 199 | CONFIG_MACH_DAVINCI_DA830_EVM=y | ||
| 200 | CONFIG_DAVINCI_MUX=y | ||
| 201 | # CONFIG_DAVINCI_MUX_DEBUG is not set | ||
| 202 | # CONFIG_DAVINCI_MUX_WARNINGS is not set | ||
| 203 | CONFIG_DAVINCI_RESET_CLOCKS=y | ||
| 204 | |||
| 205 | # | ||
| 206 | # Processor Type | ||
| 207 | # | ||
| 208 | CONFIG_CPU_32=y | ||
| 209 | CONFIG_CPU_ARM926T=y | ||
| 210 | CONFIG_CPU_32v5=y | ||
| 211 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 212 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 213 | CONFIG_CPU_CACHE_VIVT=y | ||
| 214 | CONFIG_CPU_COPY_V4WB=y | ||
| 215 | CONFIG_CPU_TLB_V4WBI=y | ||
| 216 | CONFIG_CPU_CP15=y | ||
| 217 | CONFIG_CPU_CP15_MMU=y | ||
| 218 | |||
| 219 | # | ||
| 220 | # Processor Features | ||
| 221 | # | ||
| 222 | CONFIG_ARM_THUMB=y | ||
| 223 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 224 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 225 | CONFIG_CPU_DCACHE_WRITETHROUGH=y | ||
| 226 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 227 | # CONFIG_OUTER_CACHE is not set | ||
| 228 | CONFIG_COMMON_CLKDEV=y | ||
| 229 | |||
| 230 | # | ||
| 231 | # Bus support | ||
| 232 | # | ||
| 233 | # CONFIG_PCI_SYSCALL is not set | ||
| 234 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 235 | # CONFIG_PCCARD is not set | ||
| 236 | |||
| 237 | # | ||
| 238 | # Kernel Features | ||
| 239 | # | ||
| 240 | CONFIG_TICK_ONESHOT=y | ||
| 241 | CONFIG_NO_HZ=y | ||
| 242 | CONFIG_HIGH_RES_TIMERS=y | ||
| 243 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 244 | CONFIG_VMSPLIT_3G=y | ||
| 245 | # CONFIG_VMSPLIT_2G is not set | ||
| 246 | # CONFIG_VMSPLIT_1G is not set | ||
| 247 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 248 | CONFIG_PREEMPT=y | ||
| 249 | CONFIG_HZ=100 | ||
| 250 | CONFIG_AEABI=y | ||
| 251 | # CONFIG_OABI_COMPAT is not set | ||
| 252 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 253 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 254 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 255 | # CONFIG_HIGHMEM is not set | ||
| 256 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 257 | CONFIG_FLATMEM_MANUAL=y | ||
| 258 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 259 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 260 | CONFIG_FLATMEM=y | ||
| 261 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 262 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 263 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 264 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 265 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 266 | CONFIG_BOUNCE=y | ||
| 267 | CONFIG_VIRT_TO_BUS=y | ||
| 268 | CONFIG_UNEVICTABLE_LRU=y | ||
| 269 | CONFIG_HAVE_MLOCK=y | ||
| 270 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 271 | CONFIG_LEDS=y | ||
| 272 | # CONFIG_LEDS_CPU is not set | ||
| 273 | CONFIG_ALIGNMENT_TRAP=y | ||
| 274 | |||
| 275 | # | ||
| 276 | # Boot options | ||
| 277 | # | ||
| 278 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 279 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 280 | CONFIG_CMDLINE="" | ||
| 281 | # CONFIG_XIP_KERNEL is not set | ||
| 282 | # CONFIG_KEXEC is not set | ||
| 283 | |||
| 284 | # | ||
| 285 | # CPU Power Management | ||
| 286 | # | ||
| 287 | # CONFIG_CPU_IDLE is not set | ||
| 288 | |||
| 289 | # | ||
| 290 | # Floating point emulation | ||
| 291 | # | ||
| 292 | |||
| 293 | # | ||
| 294 | # At least one emulation must be selected | ||
| 295 | # | ||
| 296 | # CONFIG_VFP is not set | ||
| 297 | |||
| 298 | # | ||
| 299 | # Userspace binary formats | ||
| 300 | # | ||
| 301 | CONFIG_BINFMT_ELF=y | ||
| 302 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 303 | CONFIG_HAVE_AOUT=y | ||
| 304 | # CONFIG_BINFMT_AOUT is not set | ||
| 305 | # CONFIG_BINFMT_MISC is not set | ||
| 306 | |||
| 307 | # | ||
| 308 | # Power management options | ||
| 309 | # | ||
| 310 | # CONFIG_PM is not set | ||
| 311 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 312 | CONFIG_NET=y | ||
| 313 | |||
| 314 | # | ||
| 315 | # Networking options | ||
| 316 | # | ||
| 317 | CONFIG_PACKET=y | ||
| 318 | # CONFIG_PACKET_MMAP is not set | ||
| 319 | CONFIG_UNIX=y | ||
| 320 | CONFIG_XFRM=y | ||
| 321 | # CONFIG_XFRM_USER is not set | ||
| 322 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 323 | # CONFIG_XFRM_MIGRATE is not set | ||
| 324 | # CONFIG_XFRM_STATISTICS is not set | ||
| 325 | # CONFIG_NET_KEY is not set | ||
| 326 | CONFIG_INET=y | ||
| 327 | # CONFIG_IP_MULTICAST is not set | ||
| 328 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 329 | CONFIG_IP_FIB_HASH=y | ||
| 330 | CONFIG_IP_PNP=y | ||
| 331 | CONFIG_IP_PNP_DHCP=y | ||
| 332 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 333 | # CONFIG_IP_PNP_RARP is not set | ||
| 334 | # CONFIG_NET_IPIP is not set | ||
| 335 | # CONFIG_NET_IPGRE is not set | ||
| 336 | # CONFIG_ARPD is not set | ||
| 337 | # CONFIG_SYN_COOKIES is not set | ||
| 338 | # CONFIG_INET_AH is not set | ||
| 339 | # CONFIG_INET_ESP is not set | ||
| 340 | # CONFIG_INET_IPCOMP is not set | ||
| 341 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 342 | CONFIG_INET_TUNNEL=m | ||
| 343 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 344 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 345 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 346 | # CONFIG_INET_LRO is not set | ||
| 347 | CONFIG_INET_DIAG=y | ||
| 348 | CONFIG_INET_TCP_DIAG=y | ||
| 349 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 350 | CONFIG_TCP_CONG_CUBIC=y | ||
| 351 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 352 | # CONFIG_TCP_MD5SIG is not set | ||
| 353 | CONFIG_IPV6=m | ||
| 354 | # CONFIG_IPV6_PRIVACY is not set | ||
| 355 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 356 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 357 | # CONFIG_INET6_AH is not set | ||
| 358 | # CONFIG_INET6_ESP is not set | ||
| 359 | # CONFIG_INET6_IPCOMP is not set | ||
| 360 | # CONFIG_IPV6_MIP6 is not set | ||
| 361 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 362 | # CONFIG_INET6_TUNNEL is not set | ||
| 363 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
| 364 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
| 365 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
| 366 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 367 | CONFIG_IPV6_SIT=m | ||
| 368 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 369 | # CONFIG_IPV6_TUNNEL is not set | ||
| 370 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 371 | # CONFIG_IPV6_MROUTE is not set | ||
| 372 | # CONFIG_NETWORK_SECMARK is not set | ||
| 373 | CONFIG_NETFILTER=y | ||
| 374 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 375 | CONFIG_NETFILTER_ADVANCED=y | ||
| 376 | |||
| 377 | # | ||
| 378 | # Core Netfilter Configuration | ||
| 379 | # | ||
| 380 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set | ||
| 381 | # CONFIG_NETFILTER_NETLINK_LOG is not set | ||
| 382 | # CONFIG_NF_CONNTRACK is not set | ||
| 383 | # CONFIG_NETFILTER_XTABLES is not set | ||
| 384 | # CONFIG_IP_VS is not set | ||
| 385 | |||
| 386 | # | ||
| 387 | # IP: Netfilter Configuration | ||
| 388 | # | ||
| 389 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 390 | # CONFIG_IP_NF_QUEUE is not set | ||
| 391 | # CONFIG_IP_NF_IPTABLES is not set | ||
| 392 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 393 | |||
| 394 | # | ||
| 395 | # IPv6: Netfilter Configuration | ||
| 396 | # | ||
| 397 | # CONFIG_IP6_NF_QUEUE is not set | ||
| 398 | # CONFIG_IP6_NF_IPTABLES is not set | ||
| 399 | # CONFIG_IP_DCCP is not set | ||
| 400 | # CONFIG_IP_SCTP is not set | ||
| 401 | # CONFIG_TIPC is not set | ||
| 402 | # CONFIG_ATM is not set | ||
| 403 | # CONFIG_BRIDGE is not set | ||
| 404 | # CONFIG_NET_DSA is not set | ||
| 405 | # CONFIG_VLAN_8021Q is not set | ||
| 406 | # CONFIG_DECNET is not set | ||
| 407 | # CONFIG_LLC2 is not set | ||
| 408 | # CONFIG_IPX is not set | ||
| 409 | # CONFIG_ATALK is not set | ||
| 410 | # CONFIG_X25 is not set | ||
| 411 | # CONFIG_LAPB is not set | ||
| 412 | # CONFIG_ECONET is not set | ||
| 413 | # CONFIG_WAN_ROUTER is not set | ||
| 414 | # CONFIG_PHONET is not set | ||
| 415 | # CONFIG_NET_SCHED is not set | ||
| 416 | # CONFIG_DCB is not set | ||
| 417 | |||
| 418 | # | ||
| 419 | # Network testing | ||
| 420 | # | ||
| 421 | # CONFIG_NET_PKTGEN is not set | ||
| 422 | # CONFIG_HAMRADIO is not set | ||
| 423 | # CONFIG_CAN is not set | ||
| 424 | # CONFIG_IRDA is not set | ||
| 425 | # CONFIG_BT is not set | ||
| 426 | # CONFIG_AF_RXRPC is not set | ||
| 427 | # CONFIG_WIRELESS is not set | ||
| 428 | # CONFIG_WIMAX is not set | ||
| 429 | # CONFIG_RFKILL is not set | ||
| 430 | # CONFIG_NET_9P is not set | ||
| 431 | |||
| 432 | # | ||
| 433 | # Device Drivers | ||
| 434 | # | ||
| 435 | |||
| 436 | # | ||
| 437 | # Generic Driver Options | ||
| 438 | # | ||
| 439 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 440 | CONFIG_STANDALONE=y | ||
| 441 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 442 | # CONFIG_FW_LOADER is not set | ||
| 443 | # CONFIG_DEBUG_DRIVER is not set | ||
| 444 | # CONFIG_DEBUG_DEVRES is not set | ||
| 445 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 446 | # CONFIG_CONNECTOR is not set | ||
| 447 | # CONFIG_MTD is not set | ||
| 448 | # CONFIG_PARPORT is not set | ||
| 449 | CONFIG_BLK_DEV=y | ||
| 450 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 451 | CONFIG_BLK_DEV_LOOP=m | ||
| 452 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 453 | # CONFIG_BLK_DEV_NBD is not set | ||
| 454 | CONFIG_BLK_DEV_RAM=y | ||
| 455 | CONFIG_BLK_DEV_RAM_COUNT=1 | ||
| 456 | CONFIG_BLK_DEV_RAM_SIZE=32768 | ||
| 457 | # CONFIG_BLK_DEV_XIP is not set | ||
| 458 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 459 | # CONFIG_ATA_OVER_ETH is not set | ||
| 460 | CONFIG_MISC_DEVICES=y | ||
| 461 | # CONFIG_ICS932S401 is not set | ||
| 462 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 463 | # CONFIG_ISL29003 is not set | ||
| 464 | # CONFIG_C2PORT is not set | ||
| 465 | |||
| 466 | # | ||
| 467 | # EEPROM support | ||
| 468 | # | ||
| 469 | CONFIG_EEPROM_AT24=y | ||
| 470 | # CONFIG_EEPROM_LEGACY is not set | ||
| 471 | # CONFIG_EEPROM_93CX6 is not set | ||
| 472 | CONFIG_HAVE_IDE=y | ||
| 473 | # CONFIG_IDE is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # SCSI device support | ||
| 477 | # | ||
| 478 | # CONFIG_RAID_ATTRS is not set | ||
| 479 | CONFIG_SCSI=m | ||
| 480 | CONFIG_SCSI_DMA=y | ||
| 481 | # CONFIG_SCSI_TGT is not set | ||
| 482 | # CONFIG_SCSI_NETLINK is not set | ||
| 483 | CONFIG_SCSI_PROC_FS=y | ||
| 484 | |||
| 485 | # | ||
| 486 | # SCSI support type (disk, tape, CD-ROM) | ||
| 487 | # | ||
| 488 | CONFIG_BLK_DEV_SD=m | ||
| 489 | # CONFIG_CHR_DEV_ST is not set | ||
| 490 | # CONFIG_CHR_DEV_OSST is not set | ||
| 491 | # CONFIG_BLK_DEV_SR is not set | ||
| 492 | # CONFIG_CHR_DEV_SG is not set | ||
| 493 | # CONFIG_CHR_DEV_SCH is not set | ||
| 494 | |||
| 495 | # | ||
| 496 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 497 | # | ||
| 498 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 499 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 500 | # CONFIG_SCSI_LOGGING is not set | ||
| 501 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 502 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 503 | |||
| 504 | # | ||
| 505 | # SCSI Transports | ||
| 506 | # | ||
| 507 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 508 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 509 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 510 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 511 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 512 | CONFIG_SCSI_LOWLEVEL=y | ||
| 513 | # CONFIG_ISCSI_TCP is not set | ||
| 514 | # CONFIG_LIBFC is not set | ||
| 515 | # CONFIG_LIBFCOE is not set | ||
| 516 | # CONFIG_SCSI_DEBUG is not set | ||
| 517 | # CONFIG_SCSI_DH is not set | ||
| 518 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 519 | # CONFIG_ATA is not set | ||
| 520 | # CONFIG_MD is not set | ||
| 521 | CONFIG_NETDEVICES=y | ||
| 522 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 523 | # CONFIG_DUMMY is not set | ||
| 524 | # CONFIG_BONDING is not set | ||
| 525 | # CONFIG_MACVLAN is not set | ||
| 526 | # CONFIG_EQUALIZER is not set | ||
| 527 | CONFIG_TUN=m | ||
| 528 | # CONFIG_VETH is not set | ||
| 529 | CONFIG_PHYLIB=y | ||
| 530 | |||
| 531 | # | ||
| 532 | # MII PHY device drivers | ||
| 533 | # | ||
| 534 | # CONFIG_MARVELL_PHY is not set | ||
| 535 | # CONFIG_DAVICOM_PHY is not set | ||
| 536 | # CONFIG_QSEMI_PHY is not set | ||
| 537 | CONFIG_LXT_PHY=y | ||
| 538 | # CONFIG_CICADA_PHY is not set | ||
| 539 | # CONFIG_VITESSE_PHY is not set | ||
| 540 | # CONFIG_SMSC_PHY is not set | ||
| 541 | # CONFIG_BROADCOM_PHY is not set | ||
| 542 | # CONFIG_ICPLUS_PHY is not set | ||
| 543 | # CONFIG_REALTEK_PHY is not set | ||
| 544 | # CONFIG_NATIONAL_PHY is not set | ||
| 545 | # CONFIG_STE10XP is not set | ||
| 546 | CONFIG_LSI_ET1011C_PHY=y | ||
| 547 | # CONFIG_FIXED_PHY is not set | ||
| 548 | # CONFIG_MDIO_BITBANG is not set | ||
| 549 | CONFIG_NET_ETHERNET=y | ||
| 550 | CONFIG_MII=y | ||
| 551 | # CONFIG_AX88796 is not set | ||
| 552 | # CONFIG_SMC91X is not set | ||
| 553 | CONFIG_TI_DAVINCI_EMAC=y | ||
| 554 | # CONFIG_DM9000 is not set | ||
| 555 | # CONFIG_ETHOC is not set | ||
| 556 | # CONFIG_SMC911X is not set | ||
| 557 | # CONFIG_SMSC911X is not set | ||
| 558 | # CONFIG_DNET is not set | ||
| 559 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 560 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 561 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 562 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 563 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 564 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 565 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 566 | # CONFIG_B44 is not set | ||
| 567 | # CONFIG_NETDEV_1000 is not set | ||
| 568 | # CONFIG_NETDEV_10000 is not set | ||
| 569 | |||
| 570 | # | ||
| 571 | # Wireless LAN | ||
| 572 | # | ||
| 573 | # CONFIG_WLAN_PRE80211 is not set | ||
| 574 | # CONFIG_WLAN_80211 is not set | ||
| 575 | |||
| 576 | # | ||
| 577 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 578 | # | ||
| 579 | # CONFIG_WAN is not set | ||
| 580 | # CONFIG_PPP is not set | ||
| 581 | # CONFIG_SLIP is not set | ||
| 582 | CONFIG_NETCONSOLE=y | ||
| 583 | # CONFIG_NETCONSOLE_DYNAMIC is not set | ||
| 584 | CONFIG_NETPOLL=y | ||
| 585 | CONFIG_NETPOLL_TRAP=y | ||
| 586 | CONFIG_NET_POLL_CONTROLLER=y | ||
| 587 | # CONFIG_ISDN is not set | ||
| 588 | |||
| 589 | # | ||
| 590 | # Input device support | ||
| 591 | # | ||
| 592 | CONFIG_INPUT=y | ||
| 593 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 594 | # CONFIG_INPUT_POLLDEV is not set | ||
| 595 | |||
| 596 | # | ||
| 597 | # Userland interfaces | ||
| 598 | # | ||
| 599 | CONFIG_INPUT_MOUSEDEV=m | ||
| 600 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 601 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 602 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 603 | # CONFIG_INPUT_JOYDEV is not set | ||
| 604 | CONFIG_INPUT_EVDEV=m | ||
| 605 | CONFIG_INPUT_EVBUG=m | ||
| 606 | |||
| 607 | # | ||
| 608 | # Input Device Drivers | ||
| 609 | # | ||
| 610 | CONFIG_INPUT_KEYBOARD=y | ||
| 611 | CONFIG_KEYBOARD_ATKBD=m | ||
| 612 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 613 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 614 | CONFIG_KEYBOARD_XTKBD=m | ||
| 615 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 616 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 617 | CONFIG_KEYBOARD_GPIO=y | ||
| 618 | # CONFIG_INPUT_MOUSE is not set | ||
| 619 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 620 | # CONFIG_INPUT_TABLET is not set | ||
| 621 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 622 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 623 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 624 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 625 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 626 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 627 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 628 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 629 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 630 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 631 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 632 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 633 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 634 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 635 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 636 | # CONFIG_INPUT_MISC is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Hardware I/O ports | ||
| 640 | # | ||
| 641 | CONFIG_SERIO=y | ||
| 642 | CONFIG_SERIO_SERPORT=y | ||
| 643 | CONFIG_SERIO_LIBPS2=y | ||
| 644 | # CONFIG_SERIO_RAW is not set | ||
| 645 | # CONFIG_GAMEPORT is not set | ||
| 646 | |||
| 647 | # | ||
| 648 | # Character devices | ||
| 649 | # | ||
| 650 | CONFIG_VT=y | ||
| 651 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 652 | # CONFIG_VT_CONSOLE is not set | ||
| 653 | CONFIG_HW_CONSOLE=y | ||
| 654 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 655 | CONFIG_DEVKMEM=y | ||
| 656 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 657 | |||
| 658 | # | ||
| 659 | # Serial drivers | ||
| 660 | # | ||
| 661 | CONFIG_SERIAL_8250=y | ||
| 662 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 663 | CONFIG_SERIAL_8250_NR_UARTS=3 | ||
| 664 | CONFIG_SERIAL_8250_RUNTIME_UARTS=3 | ||
| 665 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 666 | |||
| 667 | # | ||
| 668 | # Non-8250 serial port support | ||
| 669 | # | ||
| 670 | CONFIG_SERIAL_CORE=y | ||
| 671 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 672 | CONFIG_UNIX98_PTYS=y | ||
| 673 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 674 | CONFIG_LEGACY_PTYS=y | ||
| 675 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 676 | # CONFIG_IPMI_HANDLER is not set | ||
| 677 | CONFIG_HW_RANDOM=m | ||
| 678 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
| 679 | # CONFIG_R3964 is not set | ||
| 680 | # CONFIG_RAW_DRIVER is not set | ||
| 681 | # CONFIG_TCG_TPM is not set | ||
| 682 | CONFIG_I2C=y | ||
| 683 | CONFIG_I2C_BOARDINFO=y | ||
| 684 | CONFIG_I2C_CHARDEV=y | ||
| 685 | CONFIG_I2C_HELPER_AUTO=y | ||
| 686 | |||
| 687 | # | ||
| 688 | # I2C Hardware Bus support | ||
| 689 | # | ||
| 690 | |||
| 691 | # | ||
| 692 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 693 | # | ||
| 694 | CONFIG_I2C_DAVINCI=y | ||
| 695 | # CONFIG_I2C_GPIO is not set | ||
| 696 | # CONFIG_I2C_OCORES is not set | ||
| 697 | # CONFIG_I2C_SIMTEC is not set | ||
| 698 | |||
| 699 | # | ||
| 700 | # External I2C/SMBus adapter drivers | ||
| 701 | # | ||
| 702 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 703 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 704 | |||
| 705 | # | ||
| 706 | # Other I2C/SMBus bus drivers | ||
| 707 | # | ||
| 708 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 709 | # CONFIG_I2C_STUB is not set | ||
| 710 | |||
| 711 | # | ||
| 712 | # Miscellaneous I2C Chip support | ||
| 713 | # | ||
| 714 | # CONFIG_DS1682 is not set | ||
| 715 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 716 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 717 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 718 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 719 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 720 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 721 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 722 | # CONFIG_SPI is not set | ||
| 723 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 724 | CONFIG_GPIOLIB=y | ||
| 725 | # CONFIG_DEBUG_GPIO is not set | ||
| 726 | # CONFIG_GPIO_SYSFS is not set | ||
| 727 | |||
| 728 | # | ||
| 729 | # Memory mapped GPIO expanders: | ||
| 730 | # | ||
| 731 | |||
| 732 | # | ||
| 733 | # I2C GPIO expanders: | ||
| 734 | # | ||
| 735 | # CONFIG_GPIO_MAX732X is not set | ||
| 736 | # CONFIG_GPIO_PCA953X is not set | ||
| 737 | CONFIG_GPIO_PCF857X=m | ||
| 738 | |||
| 739 | # | ||
| 740 | # PCI GPIO expanders: | ||
| 741 | # | ||
| 742 | |||
| 743 | # | ||
| 744 | # SPI GPIO expanders: | ||
| 745 | # | ||
| 746 | # CONFIG_W1 is not set | ||
| 747 | # CONFIG_POWER_SUPPLY is not set | ||
| 748 | # CONFIG_HWMON is not set | ||
| 749 | # CONFIG_THERMAL is not set | ||
| 750 | # CONFIG_THERMAL_HWMON is not set | ||
| 751 | CONFIG_WATCHDOG=y | ||
| 752 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 753 | |||
| 754 | # | ||
| 755 | # Watchdog Device Drivers | ||
| 756 | # | ||
| 757 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 758 | # CONFIG_DAVINCI_WATCHDOG is not set | ||
| 759 | CONFIG_SSB_POSSIBLE=y | ||
| 760 | |||
| 761 | # | ||
| 762 | # Sonics Silicon Backplane | ||
| 763 | # | ||
| 764 | # CONFIG_SSB is not set | ||
| 765 | |||
| 766 | # | ||
| 767 | # Multifunction device drivers | ||
| 768 | # | ||
| 769 | # CONFIG_MFD_CORE is not set | ||
| 770 | # CONFIG_MFD_SM501 is not set | ||
| 771 | # CONFIG_MFD_ASIC3 is not set | ||
| 772 | # CONFIG_HTC_EGPIO is not set | ||
| 773 | # CONFIG_HTC_PASIC3 is not set | ||
| 774 | # CONFIG_TPS65010 is not set | ||
| 775 | # CONFIG_TWL4030_CORE is not set | ||
| 776 | # CONFIG_MFD_TMIO is not set | ||
| 777 | # CONFIG_MFD_T7L66XB is not set | ||
| 778 | # CONFIG_MFD_TC6387XB is not set | ||
| 779 | # CONFIG_MFD_TC6393XB is not set | ||
| 780 | # CONFIG_PMIC_DA903X is not set | ||
| 781 | # CONFIG_MFD_WM8400 is not set | ||
| 782 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 783 | # CONFIG_MFD_PCF50633 is not set | ||
| 784 | |||
| 785 | # | ||
| 786 | # Multimedia devices | ||
| 787 | # | ||
| 788 | |||
| 789 | # | ||
| 790 | # Multimedia core support | ||
| 791 | # | ||
| 792 | # CONFIG_VIDEO_DEV is not set | ||
| 793 | # CONFIG_DVB_CORE is not set | ||
| 794 | # CONFIG_VIDEO_MEDIA is not set | ||
| 795 | |||
| 796 | # | ||
| 797 | # Multimedia drivers | ||
| 798 | # | ||
| 799 | # CONFIG_DAB is not set | ||
| 800 | |||
| 801 | # | ||
| 802 | # Graphics support | ||
| 803 | # | ||
| 804 | # CONFIG_VGASTATE is not set | ||
| 805 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 806 | # CONFIG_FB is not set | ||
| 807 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 808 | |||
| 809 | # | ||
| 810 | # Display device support | ||
| 811 | # | ||
| 812 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 813 | |||
| 814 | # | ||
| 815 | # Console display driver support | ||
| 816 | # | ||
| 817 | # CONFIG_VGA_CONSOLE is not set | ||
| 818 | CONFIG_DUMMY_CONSOLE=y | ||
| 819 | CONFIG_SOUND=m | ||
| 820 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 821 | CONFIG_SND=m | ||
| 822 | CONFIG_SND_TIMER=m | ||
| 823 | CONFIG_SND_PCM=m | ||
| 824 | CONFIG_SND_JACK=y | ||
| 825 | # CONFIG_SND_SEQUENCER is not set | ||
| 826 | # CONFIG_SND_MIXER_OSS is not set | ||
| 827 | # CONFIG_SND_PCM_OSS is not set | ||
| 828 | # CONFIG_SND_HRTIMER is not set | ||
| 829 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 830 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 831 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 832 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 833 | # CONFIG_SND_DEBUG is not set | ||
| 834 | CONFIG_SND_DRIVERS=y | ||
| 835 | # CONFIG_SND_DUMMY is not set | ||
| 836 | # CONFIG_SND_MTPAV is not set | ||
| 837 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 838 | # CONFIG_SND_MPU401 is not set | ||
| 839 | CONFIG_SND_ARM=y | ||
| 840 | CONFIG_SND_SOC=m | ||
| 841 | CONFIG_SND_DAVINCI_SOC=m | ||
| 842 | CONFIG_SND_SOC_I2C_AND_SPI=m | ||
| 843 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 844 | # CONFIG_SOUND_PRIME is not set | ||
| 845 | # CONFIG_HID_SUPPORT is not set | ||
| 846 | # CONFIG_USB_SUPPORT is not set | ||
| 847 | # CONFIG_USB_MUSB_HOST is not set | ||
| 848 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 849 | # CONFIG_USB_MUSB_OTG is not set | ||
| 850 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 851 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 852 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 853 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 854 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 855 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 856 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 857 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 858 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 859 | # CONFIG_USB_GADGET_IMX is not set | ||
| 860 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 861 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 862 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 863 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 864 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 865 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 866 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 867 | # CONFIG_USB_ZERO is not set | ||
| 868 | # CONFIG_USB_ETH is not set | ||
| 869 | # CONFIG_USB_GADGETFS is not set | ||
| 870 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 871 | # CONFIG_USB_G_SERIAL is not set | ||
| 872 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 873 | # CONFIG_USB_G_PRINTER is not set | ||
| 874 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 875 | # CONFIG_MMC is not set | ||
| 876 | # CONFIG_MEMSTICK is not set | ||
| 877 | # CONFIG_ACCESSIBILITY is not set | ||
| 878 | # CONFIG_NEW_LEDS is not set | ||
| 879 | CONFIG_RTC_LIB=y | ||
| 880 | # CONFIG_RTC_CLASS is not set | ||
| 881 | # CONFIG_DMADEVICES is not set | ||
| 882 | # CONFIG_AUXDISPLAY is not set | ||
| 883 | # CONFIG_REGULATOR is not set | ||
| 884 | # CONFIG_UIO is not set | ||
| 885 | # CONFIG_STAGING is not set | ||
| 886 | |||
| 887 | # | ||
| 888 | # File systems | ||
| 889 | # | ||
| 890 | CONFIG_EXT2_FS=y | ||
| 891 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 892 | # CONFIG_EXT2_FS_XIP is not set | ||
| 893 | CONFIG_EXT3_FS=y | ||
| 894 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 895 | CONFIG_EXT3_FS_XATTR=y | ||
| 896 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 897 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 898 | # CONFIG_EXT4_FS is not set | ||
| 899 | CONFIG_JBD=y | ||
| 900 | # CONFIG_JBD_DEBUG is not set | ||
| 901 | CONFIG_FS_MBCACHE=y | ||
| 902 | # CONFIG_REISERFS_FS is not set | ||
| 903 | # CONFIG_JFS_FS is not set | ||
| 904 | # CONFIG_FS_POSIX_ACL is not set | ||
| 905 | CONFIG_FILE_LOCKING=y | ||
| 906 | CONFIG_XFS_FS=m | ||
| 907 | # CONFIG_XFS_QUOTA is not set | ||
| 908 | # CONFIG_XFS_POSIX_ACL is not set | ||
| 909 | # CONFIG_XFS_RT is not set | ||
| 910 | # CONFIG_XFS_DEBUG is not set | ||
| 911 | # CONFIG_OCFS2_FS is not set | ||
| 912 | # CONFIG_BTRFS_FS is not set | ||
| 913 | CONFIG_DNOTIFY=y | ||
| 914 | CONFIG_INOTIFY=y | ||
| 915 | CONFIG_INOTIFY_USER=y | ||
| 916 | # CONFIG_QUOTA is not set | ||
| 917 | # CONFIG_AUTOFS_FS is not set | ||
| 918 | CONFIG_AUTOFS4_FS=m | ||
| 919 | # CONFIG_FUSE_FS is not set | ||
| 920 | |||
| 921 | # | ||
| 922 | # Caches | ||
| 923 | # | ||
| 924 | # CONFIG_FSCACHE is not set | ||
| 925 | |||
| 926 | # | ||
| 927 | # CD-ROM/DVD Filesystems | ||
| 928 | # | ||
| 929 | # CONFIG_ISO9660_FS is not set | ||
| 930 | # CONFIG_UDF_FS is not set | ||
| 931 | |||
| 932 | # | ||
| 933 | # DOS/FAT/NT Filesystems | ||
| 934 | # | ||
| 935 | CONFIG_FAT_FS=y | ||
| 936 | CONFIG_MSDOS_FS=y | ||
| 937 | CONFIG_VFAT_FS=y | ||
| 938 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 939 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 940 | # CONFIG_NTFS_FS is not set | ||
| 941 | |||
| 942 | # | ||
| 943 | # Pseudo filesystems | ||
| 944 | # | ||
| 945 | CONFIG_PROC_FS=y | ||
| 946 | CONFIG_PROC_SYSCTL=y | ||
| 947 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 948 | CONFIG_SYSFS=y | ||
| 949 | CONFIG_TMPFS=y | ||
| 950 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 951 | # CONFIG_HUGETLB_PAGE is not set | ||
| 952 | # CONFIG_CONFIGFS_FS is not set | ||
| 953 | CONFIG_MISC_FILESYSTEMS=y | ||
| 954 | # CONFIG_ADFS_FS is not set | ||
| 955 | # CONFIG_AFFS_FS is not set | ||
| 956 | # CONFIG_HFS_FS is not set | ||
| 957 | # CONFIG_HFSPLUS_FS is not set | ||
| 958 | # CONFIG_BEFS_FS is not set | ||
| 959 | # CONFIG_BFS_FS is not set | ||
| 960 | # CONFIG_EFS_FS is not set | ||
| 961 | CONFIG_CRAMFS=y | ||
| 962 | # CONFIG_SQUASHFS is not set | ||
| 963 | # CONFIG_VXFS_FS is not set | ||
| 964 | CONFIG_MINIX_FS=m | ||
| 965 | # CONFIG_OMFS_FS is not set | ||
| 966 | # CONFIG_HPFS_FS is not set | ||
| 967 | # CONFIG_QNX4FS_FS is not set | ||
| 968 | # CONFIG_ROMFS_FS is not set | ||
| 969 | # CONFIG_SYSV_FS is not set | ||
| 970 | # CONFIG_UFS_FS is not set | ||
| 971 | # CONFIG_NILFS2_FS is not set | ||
| 972 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 973 | CONFIG_NFS_FS=y | ||
| 974 | CONFIG_NFS_V3=y | ||
| 975 | # CONFIG_NFS_V3_ACL is not set | ||
| 976 | # CONFIG_NFS_V4 is not set | ||
| 977 | CONFIG_ROOT_NFS=y | ||
| 978 | CONFIG_NFSD=m | ||
| 979 | CONFIG_NFSD_V3=y | ||
| 980 | # CONFIG_NFSD_V3_ACL is not set | ||
| 981 | # CONFIG_NFSD_V4 is not set | ||
| 982 | CONFIG_LOCKD=y | ||
| 983 | CONFIG_LOCKD_V4=y | ||
| 984 | CONFIG_EXPORTFS=m | ||
| 985 | CONFIG_NFS_COMMON=y | ||
| 986 | CONFIG_SUNRPC=y | ||
| 987 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 988 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 989 | CONFIG_SMB_FS=m | ||
| 990 | # CONFIG_SMB_NLS_DEFAULT is not set | ||
| 991 | # CONFIG_CIFS is not set | ||
| 992 | # CONFIG_NCP_FS is not set | ||
| 993 | # CONFIG_CODA_FS is not set | ||
| 994 | # CONFIG_AFS_FS is not set | ||
| 995 | |||
| 996 | # | ||
| 997 | # Partition Types | ||
| 998 | # | ||
| 999 | CONFIG_PARTITION_ADVANCED=y | ||
| 1000 | # CONFIG_ACORN_PARTITION is not set | ||
| 1001 | # CONFIG_OSF_PARTITION is not set | ||
| 1002 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1003 | # CONFIG_ATARI_PARTITION is not set | ||
| 1004 | # CONFIG_MAC_PARTITION is not set | ||
| 1005 | CONFIG_MSDOS_PARTITION=y | ||
| 1006 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1007 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1008 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1009 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1010 | # CONFIG_LDM_PARTITION is not set | ||
| 1011 | # CONFIG_SGI_PARTITION is not set | ||
| 1012 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1013 | # CONFIG_SUN_PARTITION is not set | ||
| 1014 | # CONFIG_KARMA_PARTITION is not set | ||
| 1015 | # CONFIG_EFI_PARTITION is not set | ||
| 1016 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1017 | CONFIG_NLS=y | ||
| 1018 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1019 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1020 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1021 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1022 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1023 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1024 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1025 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1026 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1027 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1028 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1029 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1030 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1031 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1032 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1033 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1034 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1035 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1036 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1037 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1038 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1039 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1040 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1041 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1042 | CONFIG_NLS_ASCII=m | ||
| 1043 | CONFIG_NLS_ISO8859_1=y | ||
| 1044 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1045 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1046 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1047 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1048 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1049 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1050 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1051 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1052 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1053 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1054 | # CONFIG_NLS_KOI8_R is not set | ||
| 1055 | # CONFIG_NLS_KOI8_U is not set | ||
| 1056 | CONFIG_NLS_UTF8=m | ||
| 1057 | # CONFIG_DLM is not set | ||
| 1058 | |||
| 1059 | # | ||
| 1060 | # Kernel hacking | ||
| 1061 | # | ||
| 1062 | # CONFIG_PRINTK_TIME is not set | ||
| 1063 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1064 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1065 | CONFIG_FRAME_WARN=1024 | ||
| 1066 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1067 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1068 | CONFIG_DEBUG_FS=y | ||
| 1069 | # CONFIG_HEADERS_CHECK is not set | ||
| 1070 | CONFIG_DEBUG_KERNEL=y | ||
| 1071 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1072 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1073 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1074 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1075 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1076 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1077 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1078 | CONFIG_SCHED_DEBUG=y | ||
| 1079 | # CONFIG_SCHEDSTATS is not set | ||
| 1080 | CONFIG_TIMER_STATS=y | ||
| 1081 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1082 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1083 | # CONFIG_SLUB_STATS is not set | ||
| 1084 | CONFIG_DEBUG_PREEMPT=y | ||
| 1085 | CONFIG_DEBUG_RT_MUTEXES=y | ||
| 1086 | CONFIG_DEBUG_PI_LIST=y | ||
| 1087 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1088 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1089 | CONFIG_DEBUG_MUTEXES=y | ||
| 1090 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1091 | # CONFIG_PROVE_LOCKING is not set | ||
| 1092 | # CONFIG_LOCK_STAT is not set | ||
| 1093 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1094 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1095 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1096 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1097 | # CONFIG_DEBUG_INFO is not set | ||
| 1098 | # CONFIG_DEBUG_VM is not set | ||
| 1099 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1100 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1101 | # CONFIG_DEBUG_LIST is not set | ||
| 1102 | # CONFIG_DEBUG_SG is not set | ||
| 1103 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1104 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1105 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1106 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1107 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1108 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1109 | # CONFIG_FAULT_INJECTION is not set | ||
| 1110 | # CONFIG_LATENCYTOP is not set | ||
| 1111 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1112 | # CONFIG_PAGE_POISONING is not set | ||
| 1113 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1114 | CONFIG_TRACING_SUPPORT=y | ||
| 1115 | |||
| 1116 | # | ||
| 1117 | # Tracers | ||
| 1118 | # | ||
| 1119 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1120 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1121 | # CONFIG_PREEMPT_TRACER is not set | ||
| 1122 | # CONFIG_SCHED_TRACER is not set | ||
| 1123 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1124 | # CONFIG_EVENT_TRACER is not set | ||
| 1125 | # CONFIG_BOOT_TRACER is not set | ||
| 1126 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1127 | # CONFIG_STACK_TRACER is not set | ||
| 1128 | # CONFIG_KMEMTRACE is not set | ||
| 1129 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1130 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1131 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 1132 | # CONFIG_SAMPLES is not set | ||
| 1133 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1134 | # CONFIG_KGDB is not set | ||
| 1135 | CONFIG_ARM_UNWIND=y | ||
| 1136 | CONFIG_DEBUG_USER=y | ||
| 1137 | CONFIG_DEBUG_ERRORS=y | ||
| 1138 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1139 | # CONFIG_DEBUG_LL is not set | ||
| 1140 | |||
| 1141 | # | ||
| 1142 | # Security options | ||
| 1143 | # | ||
| 1144 | # CONFIG_KEYS is not set | ||
| 1145 | # CONFIG_SECURITY is not set | ||
| 1146 | # CONFIG_SECURITYFS is not set | ||
| 1147 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1148 | CONFIG_CRYPTO=y | ||
| 1149 | |||
| 1150 | # | ||
| 1151 | # Crypto core or helper | ||
| 1152 | # | ||
| 1153 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1154 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1155 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 1156 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1157 | # CONFIG_CRYPTO_NULL is not set | ||
| 1158 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1159 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1160 | # CONFIG_CRYPTO_TEST is not set | ||
| 1161 | |||
| 1162 | # | ||
| 1163 | # Authenticated Encryption with Associated Data | ||
| 1164 | # | ||
| 1165 | # CONFIG_CRYPTO_CCM is not set | ||
| 1166 | # CONFIG_CRYPTO_GCM is not set | ||
| 1167 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1168 | |||
| 1169 | # | ||
| 1170 | # Block modes | ||
| 1171 | # | ||
| 1172 | # CONFIG_CRYPTO_CBC is not set | ||
| 1173 | # CONFIG_CRYPTO_CTR is not set | ||
| 1174 | # CONFIG_CRYPTO_CTS is not set | ||
| 1175 | # CONFIG_CRYPTO_ECB is not set | ||
| 1176 | # CONFIG_CRYPTO_LRW is not set | ||
| 1177 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1178 | # CONFIG_CRYPTO_XTS is not set | ||
| 1179 | |||
| 1180 | # | ||
| 1181 | # Hash modes | ||
| 1182 | # | ||
| 1183 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1184 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1185 | |||
| 1186 | # | ||
| 1187 | # Digest | ||
| 1188 | # | ||
| 1189 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1190 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1191 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1192 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1193 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1194 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1195 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1196 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1197 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1198 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1199 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1200 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1201 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1202 | |||
| 1203 | # | ||
| 1204 | # Ciphers | ||
| 1205 | # | ||
| 1206 | # CONFIG_CRYPTO_AES is not set | ||
| 1207 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1208 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1209 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1210 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1211 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1212 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1213 | # CONFIG_CRYPTO_DES is not set | ||
| 1214 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1215 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1216 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1217 | # CONFIG_CRYPTO_SEED is not set | ||
| 1218 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1219 | # CONFIG_CRYPTO_TEA is not set | ||
| 1220 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1221 | |||
| 1222 | # | ||
| 1223 | # Compression | ||
| 1224 | # | ||
| 1225 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1226 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1227 | # CONFIG_CRYPTO_LZO is not set | ||
| 1228 | |||
| 1229 | # | ||
| 1230 | # Random Number Generation | ||
| 1231 | # | ||
| 1232 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1233 | # CONFIG_CRYPTO_HW is not set | ||
| 1234 | # CONFIG_BINARY_PRINTF is not set | ||
| 1235 | |||
| 1236 | # | ||
| 1237 | # Library routines | ||
| 1238 | # | ||
| 1239 | CONFIG_BITREVERSE=y | ||
| 1240 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1241 | CONFIG_CRC_CCITT=m | ||
| 1242 | # CONFIG_CRC16 is not set | ||
| 1243 | CONFIG_CRC_T10DIF=m | ||
| 1244 | # CONFIG_CRC_ITU_T is not set | ||
| 1245 | CONFIG_CRC32=y | ||
| 1246 | # CONFIG_CRC7 is not set | ||
| 1247 | # CONFIG_LIBCRC32C is not set | ||
| 1248 | CONFIG_ZLIB_INFLATE=y | ||
| 1249 | CONFIG_DECOMPRESS_GZIP=y | ||
| 1250 | CONFIG_GENERIC_ALLOCATOR=y | ||
| 1251 | CONFIG_HAS_IOMEM=y | ||
| 1252 | CONFIG_HAS_IOPORT=y | ||
| 1253 | CONFIG_HAS_DMA=y | ||
| 1254 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/da850_omapl138_defconfig b/arch/arm/configs/da850_omapl138_defconfig new file mode 100644 index 000000000000..842a70b079bf --- /dev/null +++ b/arch/arm/configs/da850_omapl138_defconfig | |||
| @@ -0,0 +1,1229 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.30-davinci1 | ||
| 4 | # Mon Jun 29 07:54:15 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_LOCK_KERNEL=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | CONFIG_POSIX_MQUEUE=y | ||
| 43 | CONFIG_POSIX_MQUEUE_SYSCTL=y | ||
| 44 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 45 | # CONFIG_TASKSTATS is not set | ||
| 46 | # CONFIG_AUDIT is not set | ||
| 47 | |||
| 48 | # | ||
| 49 | # RCU Subsystem | ||
| 50 | # | ||
| 51 | CONFIG_CLASSIC_RCU=y | ||
| 52 | # CONFIG_TREE_RCU is not set | ||
| 53 | # CONFIG_PREEMPT_RCU is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 56 | CONFIG_IKCONFIG=y | ||
| 57 | CONFIG_IKCONFIG_PROC=y | ||
| 58 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 59 | CONFIG_GROUP_SCHED=y | ||
| 60 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 61 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 62 | CONFIG_USER_SCHED=y | ||
| 63 | # CONFIG_CGROUP_SCHED is not set | ||
| 64 | # CONFIG_CGROUPS is not set | ||
| 65 | CONFIG_SYSFS_DEPRECATED=y | ||
| 66 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 67 | # CONFIG_RELAY is not set | ||
| 68 | # CONFIG_NAMESPACES is not set | ||
| 69 | CONFIG_BLK_DEV_INITRD=y | ||
| 70 | CONFIG_INITRAMFS_SOURCE="" | ||
| 71 | CONFIG_RD_GZIP=y | ||
| 72 | # CONFIG_RD_BZIP2 is not set | ||
| 73 | # CONFIG_RD_LZMA is not set | ||
| 74 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 75 | CONFIG_SYSCTL=y | ||
| 76 | CONFIG_ANON_INODES=y | ||
| 77 | CONFIG_EMBEDDED=y | ||
| 78 | CONFIG_UID16=y | ||
| 79 | CONFIG_SYSCTL_SYSCALL=y | ||
| 80 | CONFIG_KALLSYMS=y | ||
| 81 | # CONFIG_KALLSYMS_ALL is not set | ||
| 82 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 83 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 84 | CONFIG_HOTPLUG=y | ||
| 85 | CONFIG_PRINTK=y | ||
| 86 | CONFIG_BUG=y | ||
| 87 | CONFIG_ELF_CORE=y | ||
| 88 | CONFIG_BASE_FULL=y | ||
| 89 | CONFIG_FUTEX=y | ||
| 90 | CONFIG_EPOLL=y | ||
| 91 | CONFIG_SIGNALFD=y | ||
| 92 | CONFIG_TIMERFD=y | ||
| 93 | CONFIG_EVENTFD=y | ||
| 94 | CONFIG_SHMEM=y | ||
| 95 | CONFIG_AIO=y | ||
| 96 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 97 | CONFIG_SLUB_DEBUG=y | ||
| 98 | CONFIG_COMPAT_BRK=y | ||
| 99 | # CONFIG_SLAB is not set | ||
| 100 | CONFIG_SLUB=y | ||
| 101 | # CONFIG_SLOB is not set | ||
| 102 | # CONFIG_PROFILING is not set | ||
| 103 | # CONFIG_MARKERS is not set | ||
| 104 | CONFIG_HAVE_OPROFILE=y | ||
| 105 | # CONFIG_KPROBES is not set | ||
| 106 | CONFIG_HAVE_KPROBES=y | ||
| 107 | CONFIG_HAVE_KRETPROBES=y | ||
| 108 | CONFIG_HAVE_CLK=y | ||
| 109 | # CONFIG_SLOW_WORK is not set | ||
| 110 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 111 | CONFIG_SLABINFO=y | ||
| 112 | CONFIG_RT_MUTEXES=y | ||
| 113 | CONFIG_BASE_SMALL=0 | ||
| 114 | CONFIG_MODULES=y | ||
| 115 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 116 | CONFIG_MODULE_UNLOAD=y | ||
| 117 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 118 | CONFIG_MODVERSIONS=y | ||
| 119 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 120 | CONFIG_BLOCK=y | ||
| 121 | # CONFIG_LBD is not set | ||
| 122 | # CONFIG_BLK_DEV_BSG is not set | ||
| 123 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 124 | |||
| 125 | # | ||
| 126 | # IO Schedulers | ||
| 127 | # | ||
| 128 | CONFIG_IOSCHED_NOOP=y | ||
| 129 | CONFIG_IOSCHED_AS=y | ||
| 130 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 131 | # CONFIG_IOSCHED_CFQ is not set | ||
| 132 | CONFIG_DEFAULT_AS=y | ||
| 133 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 134 | # CONFIG_DEFAULT_CFQ is not set | ||
| 135 | # CONFIG_DEFAULT_NOOP is not set | ||
| 136 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 137 | # CONFIG_FREEZER is not set | ||
| 138 | |||
| 139 | # | ||
| 140 | # System Type | ||
| 141 | # | ||
| 142 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 143 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 144 | # CONFIG_ARCH_REALVIEW is not set | ||
| 145 | # CONFIG_ARCH_VERSATILE is not set | ||
| 146 | # CONFIG_ARCH_AT91 is not set | ||
| 147 | # CONFIG_ARCH_CLPS711X is not set | ||
| 148 | # CONFIG_ARCH_EBSA110 is not set | ||
| 149 | # CONFIG_ARCH_EP93XX is not set | ||
| 150 | # CONFIG_ARCH_GEMINI is not set | ||
| 151 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 152 | # CONFIG_ARCH_NETX is not set | ||
| 153 | # CONFIG_ARCH_H720X is not set | ||
| 154 | # CONFIG_ARCH_IMX is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | ||
| 156 | # CONFIG_ARCH_IOP32X is not set | ||
| 157 | # CONFIG_ARCH_IOP33X is not set | ||
| 158 | # CONFIG_ARCH_IXP23XX is not set | ||
| 159 | # CONFIG_ARCH_IXP2000 is not set | ||
| 160 | # CONFIG_ARCH_IXP4XX is not set | ||
| 161 | # CONFIG_ARCH_L7200 is not set | ||
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 163 | # CONFIG_ARCH_KS8695 is not set | ||
| 164 | # CONFIG_ARCH_NS9XXX is not set | ||
| 165 | # CONFIG_ARCH_LOKI is not set | ||
| 166 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 167 | # CONFIG_ARCH_MXC is not set | ||
| 168 | # CONFIG_ARCH_ORION5X is not set | ||
| 169 | # CONFIG_ARCH_PNX4008 is not set | ||
| 170 | # CONFIG_ARCH_PXA is not set | ||
| 171 | # CONFIG_ARCH_MMP is not set | ||
| 172 | # CONFIG_ARCH_RPC is not set | ||
| 173 | # CONFIG_ARCH_SA1100 is not set | ||
| 174 | # CONFIG_ARCH_S3C2410 is not set | ||
| 175 | # CONFIG_ARCH_S3C64XX is not set | ||
| 176 | # CONFIG_ARCH_SHARK is not set | ||
| 177 | # CONFIG_ARCH_LH7A40X is not set | ||
| 178 | CONFIG_ARCH_DAVINCI=y | ||
| 179 | # CONFIG_ARCH_OMAP is not set | ||
| 180 | # CONFIG_ARCH_MSM is not set | ||
| 181 | # CONFIG_ARCH_W90X900 is not set | ||
| 182 | CONFIG_CP_INTC=y | ||
| 183 | |||
| 184 | # | ||
| 185 | # TI DaVinci Implementations | ||
| 186 | # | ||
| 187 | |||
| 188 | # | ||
| 189 | # DaVinci Core Type | ||
| 190 | # | ||
| 191 | # CONFIG_ARCH_DAVINCI_DM644x is not set | ||
| 192 | # CONFIG_ARCH_DAVINCI_DM355 is not set | ||
| 193 | # CONFIG_ARCH_DAVINCI_DM646x is not set | ||
| 194 | # CONFIG_ARCH_DAVINCI_DA830 is not set | ||
| 195 | CONFIG_ARCH_DAVINCI_DA850=y | ||
| 196 | CONFIG_ARCH_DAVINCI_DA8XX=y | ||
| 197 | # CONFIG_ARCH_DAVINCI_DM365 is not set | ||
| 198 | |||
| 199 | # | ||
| 200 | # DaVinci Board Type | ||
| 201 | # | ||
| 202 | CONFIG_MACH_DAVINCI_DA850_EVM=y | ||
| 203 | CONFIG_DAVINCI_MUX=y | ||
| 204 | # CONFIG_DAVINCI_MUX_DEBUG is not set | ||
| 205 | # CONFIG_DAVINCI_MUX_WARNINGS is not set | ||
| 206 | CONFIG_DAVINCI_RESET_CLOCKS=y | ||
| 207 | |||
| 208 | # | ||
| 209 | # Processor Type | ||
| 210 | # | ||
| 211 | CONFIG_CPU_32=y | ||
| 212 | CONFIG_CPU_ARM926T=y | ||
| 213 | CONFIG_CPU_32v5=y | ||
| 214 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 215 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 216 | CONFIG_CPU_CACHE_VIVT=y | ||
| 217 | CONFIG_CPU_COPY_V4WB=y | ||
| 218 | CONFIG_CPU_TLB_V4WBI=y | ||
| 219 | CONFIG_CPU_CP15=y | ||
| 220 | CONFIG_CPU_CP15_MMU=y | ||
| 221 | |||
| 222 | # | ||
| 223 | # Processor Features | ||
| 224 | # | ||
| 225 | CONFIG_ARM_THUMB=y | ||
| 226 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 227 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 228 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 229 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 230 | # CONFIG_OUTER_CACHE is not set | ||
| 231 | CONFIG_COMMON_CLKDEV=y | ||
| 232 | |||
| 233 | # | ||
| 234 | # Bus support | ||
| 235 | # | ||
| 236 | # CONFIG_PCI_SYSCALL is not set | ||
| 237 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 238 | # CONFIG_PCCARD is not set | ||
| 239 | |||
| 240 | # | ||
| 241 | # Kernel Features | ||
| 242 | # | ||
| 243 | CONFIG_TICK_ONESHOT=y | ||
| 244 | CONFIG_NO_HZ=y | ||
| 245 | CONFIG_HIGH_RES_TIMERS=y | ||
| 246 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 247 | CONFIG_VMSPLIT_3G=y | ||
| 248 | # CONFIG_VMSPLIT_2G is not set | ||
| 249 | # CONFIG_VMSPLIT_1G is not set | ||
| 250 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 251 | CONFIG_PREEMPT=y | ||
| 252 | CONFIG_HZ=100 | ||
| 253 | CONFIG_AEABI=y | ||
| 254 | # CONFIG_OABI_COMPAT is not set | ||
| 255 | # CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set | ||
| 256 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 257 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 258 | # CONFIG_HIGHMEM is not set | ||
| 259 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 260 | CONFIG_FLATMEM_MANUAL=y | ||
| 261 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 262 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 263 | CONFIG_FLATMEM=y | ||
| 264 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 265 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 266 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 267 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 268 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 269 | CONFIG_BOUNCE=y | ||
| 270 | CONFIG_VIRT_TO_BUS=y | ||
| 271 | CONFIG_UNEVICTABLE_LRU=y | ||
| 272 | CONFIG_HAVE_MLOCK=y | ||
| 273 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 274 | CONFIG_LEDS=y | ||
| 275 | # CONFIG_LEDS_CPU is not set | ||
| 276 | CONFIG_ALIGNMENT_TRAP=y | ||
| 277 | |||
| 278 | # | ||
| 279 | # Boot options | ||
| 280 | # | ||
| 281 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 282 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 283 | CONFIG_CMDLINE="" | ||
| 284 | # CONFIG_XIP_KERNEL is not set | ||
| 285 | # CONFIG_KEXEC is not set | ||
| 286 | |||
| 287 | # | ||
| 288 | # CPU Power Management | ||
| 289 | # | ||
| 290 | # CONFIG_CPU_IDLE is not set | ||
| 291 | |||
| 292 | # | ||
| 293 | # Floating point emulation | ||
| 294 | # | ||
| 295 | |||
| 296 | # | ||
| 297 | # At least one emulation must be selected | ||
| 298 | # | ||
| 299 | # CONFIG_VFP is not set | ||
| 300 | |||
| 301 | # | ||
| 302 | # Userspace binary formats | ||
| 303 | # | ||
| 304 | CONFIG_BINFMT_ELF=y | ||
| 305 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 306 | CONFIG_HAVE_AOUT=y | ||
| 307 | # CONFIG_BINFMT_AOUT is not set | ||
| 308 | # CONFIG_BINFMT_MISC is not set | ||
| 309 | |||
| 310 | # | ||
| 311 | # Power management options | ||
| 312 | # | ||
| 313 | # CONFIG_PM is not set | ||
| 314 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 315 | CONFIG_NET=y | ||
| 316 | |||
| 317 | # | ||
| 318 | # Networking options | ||
| 319 | # | ||
| 320 | CONFIG_PACKET=y | ||
| 321 | # CONFIG_PACKET_MMAP is not set | ||
| 322 | CONFIG_UNIX=y | ||
| 323 | CONFIG_XFRM=y | ||
| 324 | # CONFIG_XFRM_USER is not set | ||
| 325 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 326 | # CONFIG_XFRM_MIGRATE is not set | ||
| 327 | # CONFIG_XFRM_STATISTICS is not set | ||
| 328 | # CONFIG_NET_KEY is not set | ||
| 329 | CONFIG_INET=y | ||
| 330 | # CONFIG_IP_MULTICAST is not set | ||
| 331 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 332 | CONFIG_IP_FIB_HASH=y | ||
| 333 | CONFIG_IP_PNP=y | ||
| 334 | CONFIG_IP_PNP_DHCP=y | ||
| 335 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 336 | # CONFIG_IP_PNP_RARP is not set | ||
| 337 | # CONFIG_NET_IPIP is not set | ||
| 338 | # CONFIG_NET_IPGRE is not set | ||
| 339 | # CONFIG_ARPD is not set | ||
| 340 | # CONFIG_SYN_COOKIES is not set | ||
| 341 | # CONFIG_INET_AH is not set | ||
| 342 | # CONFIG_INET_ESP is not set | ||
| 343 | # CONFIG_INET_IPCOMP is not set | ||
| 344 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 345 | CONFIG_INET_TUNNEL=m | ||
| 346 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 347 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 348 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 349 | # CONFIG_INET_LRO is not set | ||
| 350 | CONFIG_INET_DIAG=y | ||
| 351 | CONFIG_INET_TCP_DIAG=y | ||
| 352 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 353 | CONFIG_TCP_CONG_CUBIC=y | ||
| 354 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 355 | # CONFIG_TCP_MD5SIG is not set | ||
| 356 | CONFIG_IPV6=m | ||
| 357 | # CONFIG_IPV6_PRIVACY is not set | ||
| 358 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 359 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 360 | # CONFIG_INET6_AH is not set | ||
| 361 | # CONFIG_INET6_ESP is not set | ||
| 362 | # CONFIG_INET6_IPCOMP is not set | ||
| 363 | # CONFIG_IPV6_MIP6 is not set | ||
| 364 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 365 | # CONFIG_INET6_TUNNEL is not set | ||
| 366 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
| 367 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
| 368 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
| 369 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 370 | CONFIG_IPV6_SIT=m | ||
| 371 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 372 | # CONFIG_IPV6_TUNNEL is not set | ||
| 373 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 374 | # CONFIG_IPV6_MROUTE is not set | ||
| 375 | # CONFIG_NETWORK_SECMARK is not set | ||
| 376 | CONFIG_NETFILTER=y | ||
| 377 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 378 | CONFIG_NETFILTER_ADVANCED=y | ||
| 379 | |||
| 380 | # | ||
| 381 | # Core Netfilter Configuration | ||
| 382 | # | ||
| 383 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set | ||
| 384 | # CONFIG_NETFILTER_NETLINK_LOG is not set | ||
| 385 | # CONFIG_NF_CONNTRACK is not set | ||
| 386 | # CONFIG_NETFILTER_XTABLES is not set | ||
| 387 | # CONFIG_IP_VS is not set | ||
| 388 | |||
| 389 | # | ||
| 390 | # IP: Netfilter Configuration | ||
| 391 | # | ||
| 392 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 393 | # CONFIG_IP_NF_QUEUE is not set | ||
| 394 | # CONFIG_IP_NF_IPTABLES is not set | ||
| 395 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 396 | |||
| 397 | # | ||
| 398 | # IPv6: Netfilter Configuration | ||
| 399 | # | ||
| 400 | # CONFIG_IP6_NF_QUEUE is not set | ||
| 401 | # CONFIG_IP6_NF_IPTABLES is not set | ||
| 402 | # CONFIG_IP_DCCP is not set | ||
| 403 | # CONFIG_IP_SCTP is not set | ||
| 404 | # CONFIG_TIPC is not set | ||
| 405 | # CONFIG_ATM is not set | ||
| 406 | # CONFIG_BRIDGE is not set | ||
| 407 | # CONFIG_NET_DSA is not set | ||
| 408 | # CONFIG_VLAN_8021Q is not set | ||
| 409 | # CONFIG_DECNET is not set | ||
| 410 | # CONFIG_LLC2 is not set | ||
| 411 | # CONFIG_IPX is not set | ||
| 412 | # CONFIG_ATALK is not set | ||
| 413 | # CONFIG_X25 is not set | ||
| 414 | # CONFIG_LAPB is not set | ||
| 415 | # CONFIG_ECONET is not set | ||
| 416 | # CONFIG_WAN_ROUTER is not set | ||
| 417 | # CONFIG_PHONET is not set | ||
| 418 | # CONFIG_NET_SCHED is not set | ||
| 419 | # CONFIG_DCB is not set | ||
| 420 | |||
| 421 | # | ||
| 422 | # Network testing | ||
| 423 | # | ||
| 424 | # CONFIG_NET_PKTGEN is not set | ||
| 425 | # CONFIG_HAMRADIO is not set | ||
| 426 | # CONFIG_CAN is not set | ||
| 427 | # CONFIG_IRDA is not set | ||
| 428 | # CONFIG_BT is not set | ||
| 429 | # CONFIG_AF_RXRPC is not set | ||
| 430 | # CONFIG_WIRELESS is not set | ||
| 431 | # CONFIG_WIMAX is not set | ||
| 432 | # CONFIG_RFKILL is not set | ||
| 433 | # CONFIG_NET_9P is not set | ||
| 434 | |||
| 435 | # | ||
| 436 | # Device Drivers | ||
| 437 | # | ||
| 438 | |||
| 439 | # | ||
| 440 | # Generic Driver Options | ||
| 441 | # | ||
| 442 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 443 | CONFIG_STANDALONE=y | ||
| 444 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 445 | # CONFIG_FW_LOADER is not set | ||
| 446 | # CONFIG_DEBUG_DRIVER is not set | ||
| 447 | # CONFIG_DEBUG_DEVRES is not set | ||
| 448 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 449 | # CONFIG_CONNECTOR is not set | ||
| 450 | # CONFIG_MTD is not set | ||
| 451 | # CONFIG_PARPORT is not set | ||
| 452 | CONFIG_BLK_DEV=y | ||
| 453 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 454 | CONFIG_BLK_DEV_LOOP=m | ||
| 455 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 456 | # CONFIG_BLK_DEV_NBD is not set | ||
| 457 | CONFIG_BLK_DEV_RAM=y | ||
| 458 | CONFIG_BLK_DEV_RAM_COUNT=1 | ||
| 459 | CONFIG_BLK_DEV_RAM_SIZE=32768 | ||
| 460 | # CONFIG_BLK_DEV_XIP is not set | ||
| 461 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 462 | # CONFIG_ATA_OVER_ETH is not set | ||
| 463 | CONFIG_MISC_DEVICES=y | ||
| 464 | # CONFIG_ICS932S401 is not set | ||
| 465 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 466 | # CONFIG_ISL29003 is not set | ||
| 467 | # CONFIG_C2PORT is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # EEPROM support | ||
| 471 | # | ||
| 472 | CONFIG_EEPROM_AT24=y | ||
| 473 | # CONFIG_EEPROM_LEGACY is not set | ||
| 474 | # CONFIG_EEPROM_93CX6 is not set | ||
| 475 | CONFIG_HAVE_IDE=y | ||
| 476 | # CONFIG_IDE is not set | ||
| 477 | |||
| 478 | # | ||
| 479 | # SCSI device support | ||
| 480 | # | ||
| 481 | # CONFIG_RAID_ATTRS is not set | ||
| 482 | CONFIG_SCSI=m | ||
| 483 | CONFIG_SCSI_DMA=y | ||
| 484 | # CONFIG_SCSI_TGT is not set | ||
| 485 | # CONFIG_SCSI_NETLINK is not set | ||
| 486 | CONFIG_SCSI_PROC_FS=y | ||
| 487 | |||
| 488 | # | ||
| 489 | # SCSI support type (disk, tape, CD-ROM) | ||
| 490 | # | ||
| 491 | CONFIG_BLK_DEV_SD=m | ||
| 492 | # CONFIG_CHR_DEV_ST is not set | ||
| 493 | # CONFIG_CHR_DEV_OSST is not set | ||
| 494 | # CONFIG_BLK_DEV_SR is not set | ||
| 495 | # CONFIG_CHR_DEV_SG is not set | ||
| 496 | # CONFIG_CHR_DEV_SCH is not set | ||
| 497 | |||
| 498 | # | ||
| 499 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 500 | # | ||
| 501 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 502 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 503 | # CONFIG_SCSI_LOGGING is not set | ||
| 504 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 505 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 506 | |||
| 507 | # | ||
| 508 | # SCSI Transports | ||
| 509 | # | ||
| 510 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 511 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 512 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 513 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 514 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 515 | CONFIG_SCSI_LOWLEVEL=y | ||
| 516 | # CONFIG_ISCSI_TCP is not set | ||
| 517 | # CONFIG_LIBFC is not set | ||
| 518 | # CONFIG_LIBFCOE is not set | ||
| 519 | # CONFIG_SCSI_DEBUG is not set | ||
| 520 | # CONFIG_SCSI_DH is not set | ||
| 521 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 522 | # CONFIG_ATA is not set | ||
| 523 | # CONFIG_MD is not set | ||
| 524 | CONFIG_NETDEVICES=y | ||
| 525 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 526 | # CONFIG_DUMMY is not set | ||
| 527 | # CONFIG_BONDING is not set | ||
| 528 | # CONFIG_MACVLAN is not set | ||
| 529 | # CONFIG_EQUALIZER is not set | ||
| 530 | CONFIG_TUN=m | ||
| 531 | # CONFIG_VETH is not set | ||
| 532 | CONFIG_PHYLIB=y | ||
| 533 | |||
| 534 | # | ||
| 535 | # MII PHY device drivers | ||
| 536 | # | ||
| 537 | # CONFIG_MARVELL_PHY is not set | ||
| 538 | # CONFIG_DAVICOM_PHY is not set | ||
| 539 | # CONFIG_QSEMI_PHY is not set | ||
| 540 | CONFIG_LXT_PHY=y | ||
| 541 | # CONFIG_CICADA_PHY is not set | ||
| 542 | # CONFIG_VITESSE_PHY is not set | ||
| 543 | # CONFIG_SMSC_PHY is not set | ||
| 544 | # CONFIG_BROADCOM_PHY is not set | ||
| 545 | # CONFIG_ICPLUS_PHY is not set | ||
| 546 | # CONFIG_REALTEK_PHY is not set | ||
| 547 | # CONFIG_NATIONAL_PHY is not set | ||
| 548 | # CONFIG_STE10XP is not set | ||
| 549 | CONFIG_LSI_ET1011C_PHY=y | ||
| 550 | # CONFIG_FIXED_PHY is not set | ||
| 551 | # CONFIG_MDIO_BITBANG is not set | ||
| 552 | CONFIG_NET_ETHERNET=y | ||
| 553 | CONFIG_MII=y | ||
| 554 | # CONFIG_AX88796 is not set | ||
| 555 | # CONFIG_SMC91X is not set | ||
| 556 | # CONFIG_TI_DAVINCI_EMAC is not set | ||
| 557 | # CONFIG_DM9000 is not set | ||
| 558 | # CONFIG_ETHOC is not set | ||
| 559 | # CONFIG_SMC911X is not set | ||
| 560 | # CONFIG_SMSC911X is not set | ||
| 561 | # CONFIG_DNET is not set | ||
| 562 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 563 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 564 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 565 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 566 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 567 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 568 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 569 | # CONFIG_B44 is not set | ||
| 570 | # CONFIG_NETDEV_1000 is not set | ||
| 571 | # CONFIG_NETDEV_10000 is not set | ||
| 572 | |||
| 573 | # | ||
| 574 | # Wireless LAN | ||
| 575 | # | ||
| 576 | # CONFIG_WLAN_PRE80211 is not set | ||
| 577 | # CONFIG_WLAN_80211 is not set | ||
| 578 | |||
| 579 | # | ||
| 580 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 581 | # | ||
| 582 | # CONFIG_WAN is not set | ||
| 583 | # CONFIG_PPP is not set | ||
| 584 | # CONFIG_SLIP is not set | ||
| 585 | CONFIG_NETCONSOLE=y | ||
| 586 | # CONFIG_NETCONSOLE_DYNAMIC is not set | ||
| 587 | CONFIG_NETPOLL=y | ||
| 588 | CONFIG_NETPOLL_TRAP=y | ||
| 589 | CONFIG_NET_POLL_CONTROLLER=y | ||
| 590 | # CONFIG_ISDN is not set | ||
| 591 | |||
| 592 | # | ||
| 593 | # Input device support | ||
| 594 | # | ||
| 595 | CONFIG_INPUT=y | ||
| 596 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 597 | # CONFIG_INPUT_POLLDEV is not set | ||
| 598 | |||
| 599 | # | ||
| 600 | # Userland interfaces | ||
| 601 | # | ||
| 602 | CONFIG_INPUT_MOUSEDEV=m | ||
| 603 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 604 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 605 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 606 | # CONFIG_INPUT_JOYDEV is not set | ||
| 607 | CONFIG_INPUT_EVDEV=m | ||
| 608 | CONFIG_INPUT_EVBUG=m | ||
| 609 | |||
| 610 | # | ||
| 611 | # Input Device Drivers | ||
| 612 | # | ||
| 613 | CONFIG_INPUT_KEYBOARD=y | ||
| 614 | CONFIG_KEYBOARD_ATKBD=m | ||
| 615 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 616 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 617 | CONFIG_KEYBOARD_XTKBD=m | ||
| 618 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 619 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 620 | CONFIG_KEYBOARD_GPIO=y | ||
| 621 | # CONFIG_INPUT_MOUSE is not set | ||
| 622 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 623 | # CONFIG_INPUT_TABLET is not set | ||
| 624 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 625 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 626 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 627 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 628 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 629 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 630 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 631 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 632 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 633 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 634 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 635 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 636 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 637 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 638 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 639 | # CONFIG_INPUT_MISC is not set | ||
| 640 | |||
| 641 | # | ||
| 642 | # Hardware I/O ports | ||
| 643 | # | ||
| 644 | CONFIG_SERIO=y | ||
| 645 | CONFIG_SERIO_SERPORT=y | ||
| 646 | CONFIG_SERIO_LIBPS2=y | ||
| 647 | # CONFIG_SERIO_RAW is not set | ||
| 648 | # CONFIG_GAMEPORT is not set | ||
| 649 | |||
| 650 | # | ||
| 651 | # Character devices | ||
| 652 | # | ||
| 653 | CONFIG_VT=y | ||
| 654 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 655 | # CONFIG_VT_CONSOLE is not set | ||
| 656 | CONFIG_HW_CONSOLE=y | ||
| 657 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 658 | CONFIG_DEVKMEM=y | ||
| 659 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 660 | |||
| 661 | # | ||
| 662 | # Serial drivers | ||
| 663 | # | ||
| 664 | CONFIG_SERIAL_8250=y | ||
| 665 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 666 | CONFIG_SERIAL_8250_NR_UARTS=3 | ||
| 667 | CONFIG_SERIAL_8250_RUNTIME_UARTS=3 | ||
| 668 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 669 | |||
| 670 | # | ||
| 671 | # Non-8250 serial port support | ||
| 672 | # | ||
| 673 | CONFIG_SERIAL_CORE=y | ||
| 674 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 675 | CONFIG_UNIX98_PTYS=y | ||
| 676 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 677 | CONFIG_LEGACY_PTYS=y | ||
| 678 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 679 | # CONFIG_IPMI_HANDLER is not set | ||
| 680 | CONFIG_HW_RANDOM=m | ||
| 681 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
| 682 | # CONFIG_R3964 is not set | ||
| 683 | # CONFIG_RAW_DRIVER is not set | ||
| 684 | # CONFIG_TCG_TPM is not set | ||
| 685 | CONFIG_I2C=y | ||
| 686 | CONFIG_I2C_BOARDINFO=y | ||
| 687 | CONFIG_I2C_CHARDEV=y | ||
| 688 | CONFIG_I2C_HELPER_AUTO=y | ||
| 689 | |||
| 690 | # | ||
| 691 | # I2C Hardware Bus support | ||
| 692 | # | ||
| 693 | |||
| 694 | # | ||
| 695 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 696 | # | ||
| 697 | CONFIG_I2C_DAVINCI=y | ||
| 698 | # CONFIG_I2C_GPIO is not set | ||
| 699 | # CONFIG_I2C_OCORES is not set | ||
| 700 | # CONFIG_I2C_SIMTEC is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # External I2C/SMBus adapter drivers | ||
| 704 | # | ||
| 705 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 706 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 707 | |||
| 708 | # | ||
| 709 | # Other I2C/SMBus bus drivers | ||
| 710 | # | ||
| 711 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 712 | # CONFIG_I2C_STUB is not set | ||
| 713 | |||
| 714 | # | ||
| 715 | # Miscellaneous I2C Chip support | ||
| 716 | # | ||
| 717 | # CONFIG_DS1682 is not set | ||
| 718 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 719 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 720 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 721 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 722 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 723 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 724 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 725 | # CONFIG_SPI is not set | ||
| 726 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 727 | CONFIG_GPIOLIB=y | ||
| 728 | # CONFIG_DEBUG_GPIO is not set | ||
| 729 | # CONFIG_GPIO_SYSFS is not set | ||
| 730 | |||
| 731 | # | ||
| 732 | # Memory mapped GPIO expanders: | ||
| 733 | # | ||
| 734 | |||
| 735 | # | ||
| 736 | # I2C GPIO expanders: | ||
| 737 | # | ||
| 738 | # CONFIG_GPIO_MAX732X is not set | ||
| 739 | # CONFIG_GPIO_PCA953X is not set | ||
| 740 | CONFIG_GPIO_PCF857X=m | ||
| 741 | |||
| 742 | # | ||
| 743 | # PCI GPIO expanders: | ||
| 744 | # | ||
| 745 | |||
| 746 | # | ||
| 747 | # SPI GPIO expanders: | ||
| 748 | # | ||
| 749 | # CONFIG_W1 is not set | ||
| 750 | # CONFIG_POWER_SUPPLY is not set | ||
| 751 | # CONFIG_HWMON is not set | ||
| 752 | # CONFIG_THERMAL is not set | ||
| 753 | # CONFIG_THERMAL_HWMON is not set | ||
| 754 | CONFIG_WATCHDOG=y | ||
| 755 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 756 | |||
| 757 | # | ||
| 758 | # Watchdog Device Drivers | ||
| 759 | # | ||
| 760 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 761 | # CONFIG_DAVINCI_WATCHDOG is not set | ||
| 762 | CONFIG_SSB_POSSIBLE=y | ||
| 763 | |||
| 764 | # | ||
| 765 | # Sonics Silicon Backplane | ||
| 766 | # | ||
| 767 | # CONFIG_SSB is not set | ||
| 768 | |||
| 769 | # | ||
| 770 | # Multifunction device drivers | ||
| 771 | # | ||
| 772 | # CONFIG_MFD_CORE is not set | ||
| 773 | # CONFIG_MFD_SM501 is not set | ||
| 774 | # CONFIG_MFD_ASIC3 is not set | ||
| 775 | # CONFIG_HTC_EGPIO is not set | ||
| 776 | # CONFIG_HTC_PASIC3 is not set | ||
| 777 | # CONFIG_TPS65010 is not set | ||
| 778 | # CONFIG_TWL4030_CORE is not set | ||
| 779 | # CONFIG_MFD_TMIO is not set | ||
| 780 | # CONFIG_MFD_T7L66XB is not set | ||
| 781 | # CONFIG_MFD_TC6387XB is not set | ||
| 782 | # CONFIG_MFD_TC6393XB is not set | ||
| 783 | # CONFIG_PMIC_DA903X is not set | ||
| 784 | # CONFIG_MFD_WM8400 is not set | ||
| 785 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 786 | # CONFIG_MFD_PCF50633 is not set | ||
| 787 | |||
| 788 | # | ||
| 789 | # Multimedia devices | ||
| 790 | # | ||
| 791 | |||
| 792 | # | ||
| 793 | # Multimedia core support | ||
| 794 | # | ||
| 795 | # CONFIG_VIDEO_DEV is not set | ||
| 796 | # CONFIG_DVB_CORE is not set | ||
| 797 | # CONFIG_VIDEO_MEDIA is not set | ||
| 798 | |||
| 799 | # | ||
| 800 | # Multimedia drivers | ||
| 801 | # | ||
| 802 | # CONFIG_DAB is not set | ||
| 803 | |||
| 804 | # | ||
| 805 | # Graphics support | ||
| 806 | # | ||
| 807 | # CONFIG_VGASTATE is not set | ||
| 808 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 809 | # CONFIG_FB is not set | ||
| 810 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 811 | |||
| 812 | # | ||
| 813 | # Display device support | ||
| 814 | # | ||
| 815 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 816 | |||
| 817 | # | ||
| 818 | # Console display driver support | ||
| 819 | # | ||
| 820 | # CONFIG_VGA_CONSOLE is not set | ||
| 821 | CONFIG_DUMMY_CONSOLE=y | ||
| 822 | CONFIG_SOUND=m | ||
| 823 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 824 | CONFIG_SND=m | ||
| 825 | CONFIG_SND_TIMER=m | ||
| 826 | CONFIG_SND_PCM=m | ||
| 827 | CONFIG_SND_JACK=y | ||
| 828 | # CONFIG_SND_SEQUENCER is not set | ||
| 829 | # CONFIG_SND_MIXER_OSS is not set | ||
| 830 | # CONFIG_SND_PCM_OSS is not set | ||
| 831 | # CONFIG_SND_HRTIMER is not set | ||
| 832 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 833 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 834 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 835 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 836 | # CONFIG_SND_DEBUG is not set | ||
| 837 | CONFIG_SND_DRIVERS=y | ||
| 838 | # CONFIG_SND_DUMMY is not set | ||
| 839 | # CONFIG_SND_MTPAV is not set | ||
| 840 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 841 | # CONFIG_SND_MPU401 is not set | ||
| 842 | CONFIG_SND_ARM=y | ||
| 843 | CONFIG_SND_SOC=m | ||
| 844 | CONFIG_SND_DAVINCI_SOC=m | ||
| 845 | CONFIG_SND_SOC_I2C_AND_SPI=m | ||
| 846 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 847 | # CONFIG_SOUND_PRIME is not set | ||
| 848 | # CONFIG_HID_SUPPORT is not set | ||
| 849 | # CONFIG_USB_SUPPORT is not set | ||
| 850 | # CONFIG_MMC is not set | ||
| 851 | # CONFIG_MEMSTICK is not set | ||
| 852 | # CONFIG_ACCESSIBILITY is not set | ||
| 853 | # CONFIG_NEW_LEDS is not set | ||
| 854 | CONFIG_RTC_LIB=y | ||
| 855 | # CONFIG_RTC_CLASS is not set | ||
| 856 | # CONFIG_DMADEVICES is not set | ||
| 857 | # CONFIG_AUXDISPLAY is not set | ||
| 858 | # CONFIG_REGULATOR is not set | ||
| 859 | # CONFIG_UIO is not set | ||
| 860 | # CONFIG_STAGING is not set | ||
| 861 | |||
| 862 | # | ||
| 863 | # File systems | ||
| 864 | # | ||
| 865 | CONFIG_EXT2_FS=y | ||
| 866 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 867 | # CONFIG_EXT2_FS_XIP is not set | ||
| 868 | CONFIG_EXT3_FS=y | ||
| 869 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 870 | CONFIG_EXT3_FS_XATTR=y | ||
| 871 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 872 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 873 | # CONFIG_EXT4_FS is not set | ||
| 874 | CONFIG_JBD=y | ||
| 875 | # CONFIG_JBD_DEBUG is not set | ||
| 876 | CONFIG_FS_MBCACHE=y | ||
| 877 | # CONFIG_REISERFS_FS is not set | ||
| 878 | # CONFIG_JFS_FS is not set | ||
| 879 | # CONFIG_FS_POSIX_ACL is not set | ||
| 880 | CONFIG_FILE_LOCKING=y | ||
| 881 | CONFIG_XFS_FS=m | ||
| 882 | # CONFIG_XFS_QUOTA is not set | ||
| 883 | # CONFIG_XFS_POSIX_ACL is not set | ||
| 884 | # CONFIG_XFS_RT is not set | ||
| 885 | # CONFIG_XFS_DEBUG is not set | ||
| 886 | # CONFIG_OCFS2_FS is not set | ||
| 887 | # CONFIG_BTRFS_FS is not set | ||
| 888 | CONFIG_DNOTIFY=y | ||
| 889 | CONFIG_INOTIFY=y | ||
| 890 | CONFIG_INOTIFY_USER=y | ||
| 891 | # CONFIG_QUOTA is not set | ||
| 892 | # CONFIG_AUTOFS_FS is not set | ||
| 893 | CONFIG_AUTOFS4_FS=m | ||
| 894 | # CONFIG_FUSE_FS is not set | ||
| 895 | |||
| 896 | # | ||
| 897 | # Caches | ||
| 898 | # | ||
| 899 | # CONFIG_FSCACHE is not set | ||
| 900 | |||
| 901 | # | ||
| 902 | # CD-ROM/DVD Filesystems | ||
| 903 | # | ||
| 904 | # CONFIG_ISO9660_FS is not set | ||
| 905 | # CONFIG_UDF_FS is not set | ||
| 906 | |||
| 907 | # | ||
| 908 | # DOS/FAT/NT Filesystems | ||
| 909 | # | ||
| 910 | CONFIG_FAT_FS=y | ||
| 911 | CONFIG_MSDOS_FS=y | ||
| 912 | CONFIG_VFAT_FS=y | ||
| 913 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 914 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 915 | # CONFIG_NTFS_FS is not set | ||
| 916 | |||
| 917 | # | ||
| 918 | # Pseudo filesystems | ||
| 919 | # | ||
| 920 | CONFIG_PROC_FS=y | ||
| 921 | CONFIG_PROC_SYSCTL=y | ||
| 922 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 923 | CONFIG_SYSFS=y | ||
| 924 | CONFIG_TMPFS=y | ||
| 925 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 926 | # CONFIG_HUGETLB_PAGE is not set | ||
| 927 | # CONFIG_CONFIGFS_FS is not set | ||
| 928 | CONFIG_MISC_FILESYSTEMS=y | ||
| 929 | # CONFIG_ADFS_FS is not set | ||
| 930 | # CONFIG_AFFS_FS is not set | ||
| 931 | # CONFIG_HFS_FS is not set | ||
| 932 | # CONFIG_HFSPLUS_FS is not set | ||
| 933 | # CONFIG_BEFS_FS is not set | ||
| 934 | # CONFIG_BFS_FS is not set | ||
| 935 | # CONFIG_EFS_FS is not set | ||
| 936 | CONFIG_CRAMFS=y | ||
| 937 | # CONFIG_SQUASHFS is not set | ||
| 938 | # CONFIG_VXFS_FS is not set | ||
| 939 | CONFIG_MINIX_FS=m | ||
| 940 | # CONFIG_OMFS_FS is not set | ||
| 941 | # CONFIG_HPFS_FS is not set | ||
| 942 | # CONFIG_QNX4FS_FS is not set | ||
| 943 | # CONFIG_ROMFS_FS is not set | ||
| 944 | # CONFIG_SYSV_FS is not set | ||
| 945 | # CONFIG_UFS_FS is not set | ||
| 946 | # CONFIG_NILFS2_FS is not set | ||
| 947 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 948 | CONFIG_NFS_FS=y | ||
| 949 | CONFIG_NFS_V3=y | ||
| 950 | # CONFIG_NFS_V3_ACL is not set | ||
| 951 | # CONFIG_NFS_V4 is not set | ||
| 952 | CONFIG_ROOT_NFS=y | ||
| 953 | CONFIG_NFSD=m | ||
| 954 | CONFIG_NFSD_V3=y | ||
| 955 | # CONFIG_NFSD_V3_ACL is not set | ||
| 956 | # CONFIG_NFSD_V4 is not set | ||
| 957 | CONFIG_LOCKD=y | ||
| 958 | CONFIG_LOCKD_V4=y | ||
| 959 | CONFIG_EXPORTFS=m | ||
| 960 | CONFIG_NFS_COMMON=y | ||
| 961 | CONFIG_SUNRPC=y | ||
| 962 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 963 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 964 | CONFIG_SMB_FS=m | ||
| 965 | # CONFIG_SMB_NLS_DEFAULT is not set | ||
| 966 | # CONFIG_CIFS is not set | ||
| 967 | # CONFIG_NCP_FS is not set | ||
| 968 | # CONFIG_CODA_FS is not set | ||
| 969 | # CONFIG_AFS_FS is not set | ||
| 970 | |||
| 971 | # | ||
| 972 | # Partition Types | ||
| 973 | # | ||
| 974 | CONFIG_PARTITION_ADVANCED=y | ||
| 975 | # CONFIG_ACORN_PARTITION is not set | ||
| 976 | # CONFIG_OSF_PARTITION is not set | ||
| 977 | # CONFIG_AMIGA_PARTITION is not set | ||
| 978 | # CONFIG_ATARI_PARTITION is not set | ||
| 979 | # CONFIG_MAC_PARTITION is not set | ||
| 980 | CONFIG_MSDOS_PARTITION=y | ||
| 981 | # CONFIG_BSD_DISKLABEL is not set | ||
| 982 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 983 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 984 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 985 | # CONFIG_LDM_PARTITION is not set | ||
| 986 | # CONFIG_SGI_PARTITION is not set | ||
| 987 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 988 | # CONFIG_SUN_PARTITION is not set | ||
| 989 | # CONFIG_KARMA_PARTITION is not set | ||
| 990 | # CONFIG_EFI_PARTITION is not set | ||
| 991 | # CONFIG_SYSV68_PARTITION is not set | ||
| 992 | CONFIG_NLS=y | ||
| 993 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 994 | CONFIG_NLS_CODEPAGE_437=y | ||
| 995 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 996 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 997 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 998 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 999 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1000 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1001 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1002 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1003 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1004 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1005 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1006 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1007 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1008 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1009 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1010 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1011 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1012 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1013 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1014 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1015 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1016 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1017 | CONFIG_NLS_ASCII=m | ||
| 1018 | CONFIG_NLS_ISO8859_1=y | ||
| 1019 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1020 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1021 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1022 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1023 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1024 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1025 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1026 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1027 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1028 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1029 | # CONFIG_NLS_KOI8_R is not set | ||
| 1030 | # CONFIG_NLS_KOI8_U is not set | ||
| 1031 | CONFIG_NLS_UTF8=m | ||
| 1032 | # CONFIG_DLM is not set | ||
| 1033 | |||
| 1034 | # | ||
| 1035 | # Kernel hacking | ||
| 1036 | # | ||
| 1037 | # CONFIG_PRINTK_TIME is not set | ||
| 1038 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1039 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1040 | CONFIG_FRAME_WARN=1024 | ||
| 1041 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1042 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1043 | CONFIG_DEBUG_FS=y | ||
| 1044 | # CONFIG_HEADERS_CHECK is not set | ||
| 1045 | CONFIG_DEBUG_KERNEL=y | ||
| 1046 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1047 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1048 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1049 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1050 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1051 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1052 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1053 | CONFIG_SCHED_DEBUG=y | ||
| 1054 | # CONFIG_SCHEDSTATS is not set | ||
| 1055 | CONFIG_TIMER_STATS=y | ||
| 1056 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1057 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1058 | # CONFIG_SLUB_STATS is not set | ||
| 1059 | CONFIG_DEBUG_PREEMPT=y | ||
| 1060 | CONFIG_DEBUG_RT_MUTEXES=y | ||
| 1061 | CONFIG_DEBUG_PI_LIST=y | ||
| 1062 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1063 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1064 | CONFIG_DEBUG_MUTEXES=y | ||
| 1065 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1066 | # CONFIG_PROVE_LOCKING is not set | ||
| 1067 | # CONFIG_LOCK_STAT is not set | ||
| 1068 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1069 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1070 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1071 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1072 | # CONFIG_DEBUG_INFO is not set | ||
| 1073 | # CONFIG_DEBUG_VM is not set | ||
| 1074 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1075 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1076 | # CONFIG_DEBUG_LIST is not set | ||
| 1077 | # CONFIG_DEBUG_SG is not set | ||
| 1078 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1079 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1080 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1081 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1082 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1083 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1084 | # CONFIG_FAULT_INJECTION is not set | ||
| 1085 | # CONFIG_LATENCYTOP is not set | ||
| 1086 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1087 | # CONFIG_PAGE_POISONING is not set | ||
| 1088 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1089 | CONFIG_TRACING_SUPPORT=y | ||
| 1090 | |||
| 1091 | # | ||
| 1092 | # Tracers | ||
| 1093 | # | ||
| 1094 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1095 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1096 | # CONFIG_PREEMPT_TRACER is not set | ||
| 1097 | # CONFIG_SCHED_TRACER is not set | ||
| 1098 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1099 | # CONFIG_EVENT_TRACER is not set | ||
| 1100 | # CONFIG_BOOT_TRACER is not set | ||
| 1101 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1102 | # CONFIG_STACK_TRACER is not set | ||
| 1103 | # CONFIG_KMEMTRACE is not set | ||
| 1104 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1105 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1106 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 1107 | # CONFIG_SAMPLES is not set | ||
| 1108 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1109 | # CONFIG_KGDB is not set | ||
| 1110 | CONFIG_ARM_UNWIND=y | ||
| 1111 | CONFIG_DEBUG_USER=y | ||
| 1112 | CONFIG_DEBUG_ERRORS=y | ||
| 1113 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1114 | # CONFIG_DEBUG_LL is not set | ||
| 1115 | |||
| 1116 | # | ||
| 1117 | # Security options | ||
| 1118 | # | ||
| 1119 | # CONFIG_KEYS is not set | ||
| 1120 | # CONFIG_SECURITY is not set | ||
| 1121 | # CONFIG_SECURITYFS is not set | ||
| 1122 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1123 | CONFIG_CRYPTO=y | ||
| 1124 | |||
| 1125 | # | ||
| 1126 | # Crypto core or helper | ||
| 1127 | # | ||
| 1128 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1129 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1130 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 1131 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1132 | # CONFIG_CRYPTO_NULL is not set | ||
| 1133 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1134 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1135 | # CONFIG_CRYPTO_TEST is not set | ||
| 1136 | |||
| 1137 | # | ||
| 1138 | # Authenticated Encryption with Associated Data | ||
| 1139 | # | ||
| 1140 | # CONFIG_CRYPTO_CCM is not set | ||
| 1141 | # CONFIG_CRYPTO_GCM is not set | ||
| 1142 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1143 | |||
| 1144 | # | ||
| 1145 | # Block modes | ||
| 1146 | # | ||
| 1147 | # CONFIG_CRYPTO_CBC is not set | ||
| 1148 | # CONFIG_CRYPTO_CTR is not set | ||
| 1149 | # CONFIG_CRYPTO_CTS is not set | ||
| 1150 | # CONFIG_CRYPTO_ECB is not set | ||
| 1151 | # CONFIG_CRYPTO_LRW is not set | ||
| 1152 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1153 | # CONFIG_CRYPTO_XTS is not set | ||
| 1154 | |||
| 1155 | # | ||
| 1156 | # Hash modes | ||
| 1157 | # | ||
| 1158 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1159 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1160 | |||
| 1161 | # | ||
| 1162 | # Digest | ||
| 1163 | # | ||
| 1164 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1165 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1166 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1167 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1168 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1169 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1170 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1171 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1172 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1173 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1174 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1175 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1176 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1177 | |||
| 1178 | # | ||
| 1179 | # Ciphers | ||
| 1180 | # | ||
| 1181 | # CONFIG_CRYPTO_AES is not set | ||
| 1182 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1183 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1184 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1185 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1186 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1187 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1188 | # CONFIG_CRYPTO_DES is not set | ||
| 1189 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1190 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1191 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1192 | # CONFIG_CRYPTO_SEED is not set | ||
| 1193 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1194 | # CONFIG_CRYPTO_TEA is not set | ||
| 1195 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1196 | |||
| 1197 | # | ||
| 1198 | # Compression | ||
| 1199 | # | ||
| 1200 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1201 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1202 | # CONFIG_CRYPTO_LZO is not set | ||
| 1203 | |||
| 1204 | # | ||
| 1205 | # Random Number Generation | ||
| 1206 | # | ||
| 1207 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1208 | # CONFIG_CRYPTO_HW is not set | ||
| 1209 | # CONFIG_BINARY_PRINTF is not set | ||
| 1210 | |||
| 1211 | # | ||
| 1212 | # Library routines | ||
| 1213 | # | ||
| 1214 | CONFIG_BITREVERSE=y | ||
| 1215 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1216 | CONFIG_CRC_CCITT=m | ||
| 1217 | # CONFIG_CRC16 is not set | ||
| 1218 | CONFIG_CRC_T10DIF=m | ||
| 1219 | # CONFIG_CRC_ITU_T is not set | ||
| 1220 | CONFIG_CRC32=y | ||
| 1221 | # CONFIG_CRC7 is not set | ||
| 1222 | # CONFIG_LIBCRC32C is not set | ||
| 1223 | CONFIG_ZLIB_INFLATE=y | ||
| 1224 | CONFIG_DECOMPRESS_GZIP=y | ||
| 1225 | CONFIG_GENERIC_ALLOCATOR=y | ||
| 1226 | CONFIG_HAS_IOMEM=y | ||
| 1227 | CONFIG_HAS_IOPORT=y | ||
| 1228 | CONFIG_HAS_DMA=y | ||
| 1229 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index ac18662f38cc..ddffe39d9f87 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.30-rc7 | 3 | # Linux kernel version: 2.6.31-rc3-davinci1 |
| 4 | # Tue May 26 07:24:28 2009 | 4 | # Fri Jul 17 08:26:52 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -9,7 +9,6 @@ CONFIG_GENERIC_GPIO=y | |||
| 9 | CONFIG_GENERIC_TIME=y | 9 | CONFIG_GENERIC_TIME=y |
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | 10 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 11 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | 12 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 13 | CONFIG_STACKTRACE_SUPPORT=y |
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y |
| @@ -18,14 +17,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | 20 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ZONE_DMA=y | 22 | CONFIG_ZONE_DMA=y |
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 23 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 26 | CONFIG_CONSTRUCTORS=y | ||
| 29 | 27 | ||
| 30 | # | 28 | # |
| 31 | # General setup | 29 | # General setup |
| @@ -62,8 +60,7 @@ CONFIG_FAIR_GROUP_SCHED=y | |||
| 62 | CONFIG_USER_SCHED=y | 60 | CONFIG_USER_SCHED=y |
| 63 | # CONFIG_CGROUP_SCHED is not set | 61 | # CONFIG_CGROUP_SCHED is not set |
| 64 | # CONFIG_CGROUPS is not set | 62 | # CONFIG_CGROUPS is not set |
| 65 | CONFIG_SYSFS_DEPRECATED=y | 63 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 66 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 67 | # CONFIG_RELAY is not set | 64 | # CONFIG_RELAY is not set |
| 68 | # CONFIG_NAMESPACES is not set | 65 | # CONFIG_NAMESPACES is not set |
| 69 | CONFIG_BLK_DEV_INITRD=y | 66 | CONFIG_BLK_DEV_INITRD=y |
| @@ -80,7 +77,6 @@ CONFIG_SYSCTL_SYSCALL=y | |||
| 80 | CONFIG_KALLSYMS=y | 77 | CONFIG_KALLSYMS=y |
| 81 | # CONFIG_KALLSYMS_ALL is not set | 78 | # CONFIG_KALLSYMS_ALL is not set |
| 82 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 79 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 83 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 84 | CONFIG_HOTPLUG=y | 80 | CONFIG_HOTPLUG=y |
| 85 | CONFIG_PRINTK=y | 81 | CONFIG_PRINTK=y |
| 86 | CONFIG_BUG=y | 82 | CONFIG_BUG=y |
| @@ -93,8 +89,13 @@ CONFIG_TIMERFD=y | |||
| 93 | CONFIG_EVENTFD=y | 89 | CONFIG_EVENTFD=y |
| 94 | CONFIG_SHMEM=y | 90 | CONFIG_SHMEM=y |
| 95 | CONFIG_AIO=y | 91 | CONFIG_AIO=y |
| 92 | |||
| 93 | # | ||
| 94 | # Performance Counters | ||
| 95 | # | ||
| 96 | CONFIG_VM_EVENT_COUNTERS=y | 96 | CONFIG_VM_EVENT_COUNTERS=y |
| 97 | CONFIG_SLUB_DEBUG=y | 97 | CONFIG_SLUB_DEBUG=y |
| 98 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 98 | CONFIG_COMPAT_BRK=y | 99 | CONFIG_COMPAT_BRK=y |
| 99 | # CONFIG_SLAB is not set | 100 | # CONFIG_SLAB is not set |
| 100 | CONFIG_SLUB=y | 101 | CONFIG_SLUB=y |
| @@ -106,6 +107,11 @@ CONFIG_HAVE_OPROFILE=y | |||
| 106 | CONFIG_HAVE_KPROBES=y | 107 | CONFIG_HAVE_KPROBES=y |
| 107 | CONFIG_HAVE_KRETPROBES=y | 108 | CONFIG_HAVE_KRETPROBES=y |
| 108 | CONFIG_HAVE_CLK=y | 109 | CONFIG_HAVE_CLK=y |
| 110 | |||
| 111 | # | ||
| 112 | # GCOV-based kernel profiling | ||
| 113 | # | ||
| 114 | # CONFIG_GCOV_KERNEL is not set | ||
| 109 | # CONFIG_SLOW_WORK is not set | 115 | # CONFIG_SLOW_WORK is not set |
| 110 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 116 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 111 | CONFIG_SLABINFO=y | 117 | CONFIG_SLABINFO=y |
| @@ -118,7 +124,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y | |||
| 118 | CONFIG_MODVERSIONS=y | 124 | CONFIG_MODVERSIONS=y |
| 119 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 125 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 120 | CONFIG_BLOCK=y | 126 | CONFIG_BLOCK=y |
| 121 | # CONFIG_LBD is not set | 127 | CONFIG_LBDAF=y |
| 122 | # CONFIG_BLK_DEV_BSG is not set | 128 | # CONFIG_BLK_DEV_BSG is not set |
| 123 | # CONFIG_BLK_DEV_INTEGRITY is not set | 129 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 124 | 130 | ||
| @@ -145,13 +151,14 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 145 | # CONFIG_ARCH_VERSATILE is not set | 151 | # CONFIG_ARCH_VERSATILE is not set |
| 146 | # CONFIG_ARCH_AT91 is not set | 152 | # CONFIG_ARCH_AT91 is not set |
| 147 | # CONFIG_ARCH_CLPS711X is not set | 153 | # CONFIG_ARCH_CLPS711X is not set |
| 154 | # CONFIG_ARCH_GEMINI is not set | ||
| 148 | # CONFIG_ARCH_EBSA110 is not set | 155 | # CONFIG_ARCH_EBSA110 is not set |
| 149 | # CONFIG_ARCH_EP93XX is not set | 156 | # CONFIG_ARCH_EP93XX is not set |
| 150 | # CONFIG_ARCH_GEMINI is not set | ||
| 151 | # CONFIG_ARCH_FOOTBRIDGE is not set | 157 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 152 | # CONFIG_ARCH_NETX is not set | 160 | # CONFIG_ARCH_NETX is not set |
| 153 | # CONFIG_ARCH_H720X is not set | 161 | # CONFIG_ARCH_H720X is not set |
| 154 | # CONFIG_ARCH_IMX is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | 162 | # CONFIG_ARCH_IOP13XX is not set |
| 156 | # CONFIG_ARCH_IOP32X is not set | 163 | # CONFIG_ARCH_IOP32X is not set |
| 157 | # CONFIG_ARCH_IOP33X is not set | 164 | # CONFIG_ARCH_IOP33X is not set |
| @@ -160,26 +167,27 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 160 | # CONFIG_ARCH_IXP4XX is not set | 167 | # CONFIG_ARCH_IXP4XX is not set |
| 161 | # CONFIG_ARCH_L7200 is not set | 168 | # CONFIG_ARCH_L7200 is not set |
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | 169 | # CONFIG_ARCH_KIRKWOOD is not set |
| 163 | # CONFIG_ARCH_KS8695 is not set | ||
| 164 | # CONFIG_ARCH_NS9XXX is not set | ||
| 165 | # CONFIG_ARCH_LOKI is not set | 170 | # CONFIG_ARCH_LOKI is not set |
| 166 | # CONFIG_ARCH_MV78XX0 is not set | 171 | # CONFIG_ARCH_MV78XX0 is not set |
| 167 | # CONFIG_ARCH_MXC is not set | ||
| 168 | # CONFIG_ARCH_ORION5X is not set | 172 | # CONFIG_ARCH_ORION5X is not set |
| 173 | # CONFIG_ARCH_MMP is not set | ||
| 174 | # CONFIG_ARCH_KS8695 is not set | ||
| 175 | # CONFIG_ARCH_NS9XXX is not set | ||
| 176 | # CONFIG_ARCH_W90X900 is not set | ||
| 169 | # CONFIG_ARCH_PNX4008 is not set | 177 | # CONFIG_ARCH_PNX4008 is not set |
| 170 | # CONFIG_ARCH_PXA is not set | 178 | # CONFIG_ARCH_PXA is not set |
| 171 | # CONFIG_ARCH_MMP is not set | 179 | # CONFIG_ARCH_MSM is not set |
| 172 | # CONFIG_ARCH_RPC is not set | 180 | # CONFIG_ARCH_RPC is not set |
| 173 | # CONFIG_ARCH_SA1100 is not set | 181 | # CONFIG_ARCH_SA1100 is not set |
| 174 | # CONFIG_ARCH_S3C2410 is not set | 182 | # CONFIG_ARCH_S3C2410 is not set |
| 175 | # CONFIG_ARCH_S3C64XX is not set | 183 | # CONFIG_ARCH_S3C64XX is not set |
| 176 | # CONFIG_ARCH_SHARK is not set | 184 | # CONFIG_ARCH_SHARK is not set |
| 177 | # CONFIG_ARCH_LH7A40X is not set | 185 | # CONFIG_ARCH_LH7A40X is not set |
| 186 | # CONFIG_ARCH_U300 is not set | ||
| 178 | CONFIG_ARCH_DAVINCI=y | 187 | CONFIG_ARCH_DAVINCI=y |
| 179 | # CONFIG_ARCH_OMAP is not set | 188 | # CONFIG_ARCH_OMAP is not set |
| 180 | # CONFIG_ARCH_MSM is not set | ||
| 181 | # CONFIG_ARCH_W90X900 is not set | ||
| 182 | CONFIG_AINTC=y | 189 | CONFIG_AINTC=y |
| 190 | CONFIG_ARCH_DAVINCI_DMx=y | ||
| 183 | 191 | ||
| 184 | # | 192 | # |
| 185 | # TI DaVinci Implementations | 193 | # TI DaVinci Implementations |
| @@ -191,6 +199,9 @@ CONFIG_AINTC=y | |||
| 191 | CONFIG_ARCH_DAVINCI_DM644x=y | 199 | CONFIG_ARCH_DAVINCI_DM644x=y |
| 192 | CONFIG_ARCH_DAVINCI_DM355=y | 200 | CONFIG_ARCH_DAVINCI_DM355=y |
| 193 | CONFIG_ARCH_DAVINCI_DM646x=y | 201 | CONFIG_ARCH_DAVINCI_DM646x=y |
| 202 | # CONFIG_ARCH_DAVINCI_DA830 is not set | ||
| 203 | # CONFIG_ARCH_DAVINCI_DA850 is not set | ||
| 204 | CONFIG_ARCH_DAVINCI_DM365=y | ||
| 194 | 205 | ||
| 195 | # | 206 | # |
| 196 | # DaVinci Board Type | 207 | # DaVinci Board Type |
| @@ -200,6 +211,7 @@ CONFIG_MACH_SFFSDR=y | |||
| 200 | CONFIG_MACH_DAVINCI_DM355_EVM=y | 211 | CONFIG_MACH_DAVINCI_DM355_EVM=y |
| 201 | CONFIG_MACH_DM355_LEOPARD=y | 212 | CONFIG_MACH_DM355_LEOPARD=y |
| 202 | CONFIG_MACH_DAVINCI_DM6467_EVM=y | 213 | CONFIG_MACH_DAVINCI_DM6467_EVM=y |
| 214 | CONFIG_MACH_DAVINCI_DM365_EVM=y | ||
| 203 | CONFIG_DAVINCI_MUX=y | 215 | CONFIG_DAVINCI_MUX=y |
| 204 | CONFIG_DAVINCI_MUX_DEBUG=y | 216 | CONFIG_DAVINCI_MUX_DEBUG=y |
| 205 | CONFIG_DAVINCI_MUX_WARNINGS=y | 217 | CONFIG_DAVINCI_MUX_WARNINGS=y |
| @@ -227,7 +239,6 @@ CONFIG_ARM_THUMB=y | |||
| 227 | # CONFIG_CPU_DCACHE_DISABLE is not set | 239 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 228 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 240 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 229 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | 241 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set |
| 230 | # CONFIG_OUTER_CACHE is not set | ||
| 231 | CONFIG_COMMON_CLKDEV=y | 242 | CONFIG_COMMON_CLKDEV=y |
| 232 | 243 | ||
| 233 | # | 244 | # |
| @@ -252,7 +263,6 @@ CONFIG_PREEMPT=y | |||
| 252 | CONFIG_HZ=100 | 263 | CONFIG_HZ=100 |
| 253 | CONFIG_AEABI=y | 264 | CONFIG_AEABI=y |
| 254 | # CONFIG_OABI_COMPAT is not set | 265 | # CONFIG_OABI_COMPAT is not set |
| 255 | # CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set | ||
| 256 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | 266 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
| 257 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | 267 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set |
| 258 | # CONFIG_HIGHMEM is not set | 268 | # CONFIG_HIGHMEM is not set |
| @@ -268,12 +278,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096 | |||
| 268 | CONFIG_ZONE_DMA_FLAG=1 | 278 | CONFIG_ZONE_DMA_FLAG=1 |
| 269 | CONFIG_BOUNCE=y | 279 | CONFIG_BOUNCE=y |
| 270 | CONFIG_VIRT_TO_BUS=y | 280 | CONFIG_VIRT_TO_BUS=y |
| 271 | CONFIG_UNEVICTABLE_LRU=y | ||
| 272 | CONFIG_HAVE_MLOCK=y | 281 | CONFIG_HAVE_MLOCK=y |
| 273 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | 282 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y |
| 283 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 274 | CONFIG_LEDS=y | 284 | CONFIG_LEDS=y |
| 275 | # CONFIG_LEDS_CPU is not set | 285 | # CONFIG_LEDS_CPU is not set |
| 276 | CONFIG_ALIGNMENT_TRAP=y | 286 | CONFIG_ALIGNMENT_TRAP=y |
| 287 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 277 | 288 | ||
| 278 | # | 289 | # |
| 279 | # Boot options | 290 | # Boot options |
| @@ -415,6 +426,7 @@ CONFIG_NETFILTER_ADVANCED=y | |||
| 415 | # CONFIG_ECONET is not set | 426 | # CONFIG_ECONET is not set |
| 416 | # CONFIG_WAN_ROUTER is not set | 427 | # CONFIG_WAN_ROUTER is not set |
| 417 | # CONFIG_PHONET is not set | 428 | # CONFIG_PHONET is not set |
| 429 | # CONFIG_IEEE802154 is not set | ||
| 418 | # CONFIG_NET_SCHED is not set | 430 | # CONFIG_NET_SCHED is not set |
| 419 | # CONFIG_DCB is not set | 431 | # CONFIG_DCB is not set |
| 420 | 432 | ||
| @@ -553,6 +565,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 | |||
| 553 | # CONFIG_BLK_DEV_XIP is not set | 565 | # CONFIG_BLK_DEV_XIP is not set |
| 554 | # CONFIG_CDROM_PKTCDVD is not set | 566 | # CONFIG_CDROM_PKTCDVD is not set |
| 555 | # CONFIG_ATA_OVER_ETH is not set | 567 | # CONFIG_ATA_OVER_ETH is not set |
| 568 | # CONFIG_MG_DISK is not set | ||
| 556 | CONFIG_MISC_DEVICES=y | 569 | CONFIG_MISC_DEVICES=y |
| 557 | # CONFIG_ICS932S401 is not set | 570 | # CONFIG_ICS932S401 is not set |
| 558 | # CONFIG_ENCLOSURE_SERVICES is not set | 571 | # CONFIG_ENCLOSURE_SERVICES is not set |
| @@ -564,6 +577,7 @@ CONFIG_MISC_DEVICES=y | |||
| 564 | # | 577 | # |
| 565 | CONFIG_EEPROM_AT24=y | 578 | CONFIG_EEPROM_AT24=y |
| 566 | # CONFIG_EEPROM_LEGACY is not set | 579 | # CONFIG_EEPROM_LEGACY is not set |
| 580 | # CONFIG_EEPROM_MAX6875 is not set | ||
| 567 | # CONFIG_EEPROM_93CX6 is not set | 581 | # CONFIG_EEPROM_93CX6 is not set |
| 568 | CONFIG_HAVE_IDE=y | 582 | CONFIG_HAVE_IDE=y |
| 569 | CONFIG_IDE=m | 583 | CONFIG_IDE=m |
| @@ -609,10 +623,6 @@ CONFIG_BLK_DEV_SD=m | |||
| 609 | # CONFIG_BLK_DEV_SR is not set | 623 | # CONFIG_BLK_DEV_SR is not set |
| 610 | # CONFIG_CHR_DEV_SG is not set | 624 | # CONFIG_CHR_DEV_SG is not set |
| 611 | # CONFIG_CHR_DEV_SCH is not set | 625 | # CONFIG_CHR_DEV_SCH is not set |
| 612 | |||
| 613 | # | ||
| 614 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 615 | # | ||
| 616 | # CONFIG_SCSI_MULTI_LUN is not set | 626 | # CONFIG_SCSI_MULTI_LUN is not set |
| 617 | # CONFIG_SCSI_CONSTANTS is not set | 627 | # CONFIG_SCSI_CONSTANTS is not set |
| 618 | # CONFIG_SCSI_LOGGING is not set | 628 | # CONFIG_SCSI_LOGGING is not set |
| @@ -637,7 +647,6 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 637 | # CONFIG_ATA is not set | 647 | # CONFIG_ATA is not set |
| 638 | # CONFIG_MD is not set | 648 | # CONFIG_MD is not set |
| 639 | CONFIG_NETDEVICES=y | 649 | CONFIG_NETDEVICES=y |
| 640 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 641 | # CONFIG_DUMMY is not set | 650 | # CONFIG_DUMMY is not set |
| 642 | # CONFIG_BONDING is not set | 651 | # CONFIG_BONDING is not set |
| 643 | # CONFIG_MACVLAN is not set | 652 | # CONFIG_MACVLAN is not set |
| @@ -684,6 +693,7 @@ CONFIG_DM9000_DEBUGLEVEL=4 | |||
| 684 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 693 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 685 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 694 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 686 | # CONFIG_B44 is not set | 695 | # CONFIG_B44 is not set |
| 696 | # CONFIG_KS8842 is not set | ||
| 687 | # CONFIG_NETDEV_1000 is not set | 697 | # CONFIG_NETDEV_1000 is not set |
| 688 | # CONFIG_NETDEV_10000 is not set | 698 | # CONFIG_NETDEV_10000 is not set |
| 689 | 699 | ||
| @@ -748,18 +758,21 @@ CONFIG_INPUT_EVBUG=m | |||
| 748 | # | 758 | # |
| 749 | CONFIG_INPUT_KEYBOARD=y | 759 | CONFIG_INPUT_KEYBOARD=y |
| 750 | CONFIG_KEYBOARD_ATKBD=m | 760 | CONFIG_KEYBOARD_ATKBD=m |
| 751 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 752 | # CONFIG_KEYBOARD_LKKBD is not set | 761 | # CONFIG_KEYBOARD_LKKBD is not set |
| 753 | CONFIG_KEYBOARD_XTKBD=m | 762 | CONFIG_KEYBOARD_GPIO=y |
| 763 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 764 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 754 | # CONFIG_KEYBOARD_NEWTON is not set | 765 | # CONFIG_KEYBOARD_NEWTON is not set |
| 755 | # CONFIG_KEYBOARD_STOWAWAY is not set | 766 | # CONFIG_KEYBOARD_STOWAWAY is not set |
| 756 | CONFIG_KEYBOARD_GPIO=y | 767 | # CONFIG_KEYBOARD_SUNKBD is not set |
| 768 | CONFIG_KEYBOARD_XTKBD=m | ||
| 757 | # CONFIG_INPUT_MOUSE is not set | 769 | # CONFIG_INPUT_MOUSE is not set |
| 758 | # CONFIG_INPUT_JOYSTICK is not set | 770 | # CONFIG_INPUT_JOYSTICK is not set |
| 759 | # CONFIG_INPUT_TABLET is not set | 771 | # CONFIG_INPUT_TABLET is not set |
| 760 | CONFIG_INPUT_TOUCHSCREEN=y | 772 | CONFIG_INPUT_TOUCHSCREEN=y |
| 761 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 773 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 762 | # CONFIG_TOUCHSCREEN_AD7879 is not set | 774 | # CONFIG_TOUCHSCREEN_AD7879 is not set |
| 775 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
| 763 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 776 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 764 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 777 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 765 | # CONFIG_TOUCHSCREEN_ELO is not set | 778 | # CONFIG_TOUCHSCREEN_ELO is not set |
| @@ -773,6 +786,7 @@ CONFIG_INPUT_TOUCHSCREEN=y | |||
| 773 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 786 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 774 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | 787 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set |
| 775 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | 788 | # CONFIG_TOUCHSCREEN_TSC2007 is not set |
| 789 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 776 | # CONFIG_INPUT_MISC is not set | 790 | # CONFIG_INPUT_MISC is not set |
| 777 | 791 | ||
| 778 | # | 792 | # |
| @@ -832,6 +846,7 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 832 | # I2C system bus drivers (mostly embedded / system-on-chip) | 846 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 833 | # | 847 | # |
| 834 | CONFIG_I2C_DAVINCI=y | 848 | CONFIG_I2C_DAVINCI=y |
| 849 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 835 | # CONFIG_I2C_GPIO is not set | 850 | # CONFIG_I2C_GPIO is not set |
| 836 | # CONFIG_I2C_OCORES is not set | 851 | # CONFIG_I2C_OCORES is not set |
| 837 | # CONFIG_I2C_SIMTEC is not set | 852 | # CONFIG_I2C_SIMTEC is not set |
| @@ -854,7 +869,6 @@ CONFIG_I2C_DAVINCI=y | |||
| 854 | # | 869 | # |
| 855 | # CONFIG_DS1682 is not set | 870 | # CONFIG_DS1682 is not set |
| 856 | # CONFIG_SENSORS_PCA9539 is not set | 871 | # CONFIG_SENSORS_PCA9539 is not set |
| 857 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 858 | # CONFIG_SENSORS_TSL2550 is not set | 872 | # CONFIG_SENSORS_TSL2550 is not set |
| 859 | # CONFIG_I2C_DEBUG_CORE is not set | 873 | # CONFIG_I2C_DEBUG_CORE is not set |
| 860 | # CONFIG_I2C_DEBUG_ALGO is not set | 874 | # CONFIG_I2C_DEBUG_ALGO is not set |
| @@ -935,6 +949,7 @@ CONFIG_HWMON=y | |||
| 935 | # CONFIG_SENSORS_SMSC47B397 is not set | 949 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 936 | # CONFIG_SENSORS_ADS7828 is not set | 950 | # CONFIG_SENSORS_ADS7828 is not set |
| 937 | # CONFIG_SENSORS_THMC50 is not set | 951 | # CONFIG_SENSORS_THMC50 is not set |
| 952 | # CONFIG_SENSORS_TMP401 is not set | ||
| 938 | # CONFIG_SENSORS_VT1211 is not set | 953 | # CONFIG_SENSORS_VT1211 is not set |
| 939 | # CONFIG_SENSORS_W83781D is not set | 954 | # CONFIG_SENSORS_W83781D is not set |
| 940 | # CONFIG_SENSORS_W83791D is not set | 955 | # CONFIG_SENSORS_W83791D is not set |
| @@ -986,52 +1001,8 @@ CONFIG_SSB_POSSIBLE=y | |||
| 986 | # CONFIG_MFD_WM8400 is not set | 1001 | # CONFIG_MFD_WM8400 is not set |
| 987 | # CONFIG_MFD_WM8350_I2C is not set | 1002 | # CONFIG_MFD_WM8350_I2C is not set |
| 988 | # CONFIG_MFD_PCF50633 is not set | 1003 | # CONFIG_MFD_PCF50633 is not set |
| 989 | 1004 | # CONFIG_AB3100_CORE is not set | |
| 990 | # | 1005 | # CONFIG_MEDIA_SUPPORT is not set |
| 991 | # Multimedia devices | ||
| 992 | # | ||
| 993 | |||
| 994 | # | ||
| 995 | # Multimedia core support | ||
| 996 | # | ||
| 997 | CONFIG_VIDEO_DEV=y | ||
| 998 | CONFIG_VIDEO_V4L2_COMMON=y | ||
| 999 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1000 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1001 | # CONFIG_DVB_CORE is not set | ||
| 1002 | CONFIG_VIDEO_MEDIA=y | ||
| 1003 | |||
| 1004 | # | ||
| 1005 | # Multimedia drivers | ||
| 1006 | # | ||
| 1007 | # CONFIG_MEDIA_ATTACH is not set | ||
| 1008 | CONFIG_MEDIA_TUNER=y | ||
| 1009 | # CONFIG_MEDIA_TUNER_CUSTOMISE is not set | ||
| 1010 | CONFIG_MEDIA_TUNER_SIMPLE=y | ||
| 1011 | CONFIG_MEDIA_TUNER_TDA8290=y | ||
| 1012 | CONFIG_MEDIA_TUNER_TDA9887=y | ||
| 1013 | CONFIG_MEDIA_TUNER_TEA5761=y | ||
| 1014 | CONFIG_MEDIA_TUNER_TEA5767=y | ||
| 1015 | CONFIG_MEDIA_TUNER_MT20XX=y | ||
| 1016 | CONFIG_MEDIA_TUNER_XC2028=y | ||
| 1017 | CONFIG_MEDIA_TUNER_XC5000=y | ||
| 1018 | CONFIG_MEDIA_TUNER_MC44S803=y | ||
| 1019 | CONFIG_VIDEO_V4L2=y | ||
| 1020 | CONFIG_VIDEO_V4L1=y | ||
| 1021 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1022 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1023 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1024 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1025 | # CONFIG_VIDEO_VIVI is not set | ||
| 1026 | # CONFIG_VIDEO_CPIA is not set | ||
| 1027 | # CONFIG_VIDEO_CPIA2 is not set | ||
| 1028 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1029 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1030 | # CONFIG_SOC_CAMERA is not set | ||
| 1031 | # CONFIG_V4L_USB_DRIVERS is not set | ||
| 1032 | # CONFIG_RADIO_ADAPTERS is not set | ||
| 1033 | CONFIG_DAB=y | ||
| 1034 | # CONFIG_USB_DABUSB is not set | ||
| 1035 | 1006 | ||
| 1036 | # | 1007 | # |
| 1037 | # Graphics support | 1008 | # Graphics support |
| @@ -1102,6 +1073,11 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 1102 | CONFIG_SND_VERBOSE_PROCFS=y | 1073 | CONFIG_SND_VERBOSE_PROCFS=y |
| 1103 | # CONFIG_SND_VERBOSE_PRINTK is not set | 1074 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 1104 | # CONFIG_SND_DEBUG is not set | 1075 | # CONFIG_SND_DEBUG is not set |
| 1076 | # CONFIG_SND_RAWMIDI_SEQ is not set | ||
| 1077 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
| 1078 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
| 1079 | # CONFIG_SND_SBAWE_SEQ is not set | ||
| 1080 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 1105 | CONFIG_SND_DRIVERS=y | 1081 | CONFIG_SND_DRIVERS=y |
| 1106 | # CONFIG_SND_DUMMY is not set | 1082 | # CONFIG_SND_DUMMY is not set |
| 1107 | # CONFIG_SND_MTPAV is not set | 1083 | # CONFIG_SND_MTPAV is not set |
| @@ -1112,9 +1088,16 @@ CONFIG_SND_USB=y | |||
| 1112 | # CONFIG_SND_USB_AUDIO is not set | 1088 | # CONFIG_SND_USB_AUDIO is not set |
| 1113 | # CONFIG_SND_USB_CAIAQ is not set | 1089 | # CONFIG_SND_USB_CAIAQ is not set |
| 1114 | CONFIG_SND_SOC=m | 1090 | CONFIG_SND_SOC=m |
| 1115 | # CONFIG_SND_DAVINCI_SOC is not set | 1091 | CONFIG_SND_DAVINCI_SOC=m |
| 1092 | CONFIG_SND_DAVINCI_SOC_I2S=m | ||
| 1093 | CONFIG_SND_DAVINCI_SOC_MCASP=m | ||
| 1094 | CONFIG_SND_DAVINCI_SOC_EVM=m | ||
| 1095 | CONFIG_SND_DM6467_SOC_EVM=m | ||
| 1096 | # CONFIG_SND_DAVINCI_SOC_SFFSDR is not set | ||
| 1116 | CONFIG_SND_SOC_I2C_AND_SPI=m | 1097 | CONFIG_SND_SOC_I2C_AND_SPI=m |
| 1117 | # CONFIG_SND_SOC_ALL_CODECS is not set | 1098 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 1099 | CONFIG_SND_SOC_SPDIF=m | ||
| 1100 | CONFIG_SND_SOC_TLV320AIC3X=m | ||
| 1118 | # CONFIG_SOUND_PRIME is not set | 1101 | # CONFIG_SOUND_PRIME is not set |
| 1119 | CONFIG_HID_SUPPORT=y | 1102 | CONFIG_HID_SUPPORT=y |
| 1120 | CONFIG_HID=m | 1103 | CONFIG_HID=m |
| @@ -1143,7 +1126,7 @@ CONFIG_HID_BELKIN=m | |||
| 1143 | CONFIG_HID_CHERRY=m | 1126 | CONFIG_HID_CHERRY=m |
| 1144 | CONFIG_HID_CHICONY=m | 1127 | CONFIG_HID_CHICONY=m |
| 1145 | CONFIG_HID_CYPRESS=m | 1128 | CONFIG_HID_CYPRESS=m |
| 1146 | # CONFIG_DRAGONRISE_FF is not set | 1129 | # CONFIG_HID_DRAGONRISE is not set |
| 1147 | CONFIG_HID_EZKEY=m | 1130 | CONFIG_HID_EZKEY=m |
| 1148 | # CONFIG_HID_KYE is not set | 1131 | # CONFIG_HID_KYE is not set |
| 1149 | CONFIG_HID_GYRATION=m | 1132 | CONFIG_HID_GYRATION=m |
| @@ -1160,10 +1143,11 @@ CONFIG_HID_PETALYNX=m | |||
| 1160 | CONFIG_HID_SAMSUNG=m | 1143 | CONFIG_HID_SAMSUNG=m |
| 1161 | CONFIG_HID_SONY=m | 1144 | CONFIG_HID_SONY=m |
| 1162 | CONFIG_HID_SUNPLUS=m | 1145 | CONFIG_HID_SUNPLUS=m |
| 1163 | # CONFIG_GREENASIA_FF is not set | 1146 | # CONFIG_HID_GREENASIA is not set |
| 1147 | # CONFIG_HID_SMARTJOYPLUS is not set | ||
| 1164 | # CONFIG_HID_TOPSEED is not set | 1148 | # CONFIG_HID_TOPSEED is not set |
| 1165 | # CONFIG_THRUSTMASTER_FF is not set | 1149 | # CONFIG_HID_THRUSTMASTER is not set |
| 1166 | # CONFIG_ZEROPLUS_FF is not set | 1150 | # CONFIG_HID_ZEROPLUS is not set |
| 1167 | CONFIG_USB_SUPPORT=y | 1151 | CONFIG_USB_SUPPORT=y |
| 1168 | CONFIG_USB_ARCH_HAS_HCD=y | 1152 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1169 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 1153 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| @@ -1266,6 +1250,7 @@ CONFIG_USB_STORAGE=m | |||
| 1266 | # CONFIG_USB_IDMOUSE is not set | 1250 | # CONFIG_USB_IDMOUSE is not set |
| 1267 | # CONFIG_USB_FTDI_ELAN is not set | 1251 | # CONFIG_USB_FTDI_ELAN is not set |
| 1268 | # CONFIG_USB_APPLEDISPLAY is not set | 1252 | # CONFIG_USB_APPLEDISPLAY is not set |
| 1253 | # CONFIG_USB_SISUSBVGA is not set | ||
| 1269 | # CONFIG_USB_LD is not set | 1254 | # CONFIG_USB_LD is not set |
| 1270 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1255 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1271 | # CONFIG_USB_IOWARRIOR is not set | 1256 | # CONFIG_USB_IOWARRIOR is not set |
| @@ -1285,17 +1270,20 @@ CONFIG_USB_GADGET_SELECTED=y | |||
| 1285 | # CONFIG_USB_GADGET_OMAP is not set | 1270 | # CONFIG_USB_GADGET_OMAP is not set |
| 1286 | # CONFIG_USB_GADGET_PXA25X is not set | 1271 | # CONFIG_USB_GADGET_PXA25X is not set |
| 1287 | # CONFIG_USB_GADGET_PXA27X is not set | 1272 | # CONFIG_USB_GADGET_PXA27X is not set |
| 1288 | # CONFIG_USB_GADGET_S3C2410 is not set | 1273 | # CONFIG_USB_GADGET_S3C_HSOTG is not set |
| 1289 | # CONFIG_USB_GADGET_IMX is not set | 1274 | # CONFIG_USB_GADGET_IMX is not set |
| 1275 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1290 | # CONFIG_USB_GADGET_M66592 is not set | 1276 | # CONFIG_USB_GADGET_M66592 is not set |
| 1291 | # CONFIG_USB_GADGET_AMD5536UDC is not set | 1277 | # CONFIG_USB_GADGET_AMD5536UDC is not set |
| 1292 | # CONFIG_USB_GADGET_FSL_QE is not set | 1278 | # CONFIG_USB_GADGET_FSL_QE is not set |
| 1293 | # CONFIG_USB_GADGET_CI13XXX is not set | 1279 | # CONFIG_USB_GADGET_CI13XXX is not set |
| 1294 | # CONFIG_USB_GADGET_NET2280 is not set | 1280 | # CONFIG_USB_GADGET_NET2280 is not set |
| 1295 | # CONFIG_USB_GADGET_GOKU is not set | 1281 | # CONFIG_USB_GADGET_GOKU is not set |
| 1282 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 1296 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 1283 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| 1297 | CONFIG_USB_GADGET_DUALSPEED=y | 1284 | CONFIG_USB_GADGET_DUALSPEED=y |
| 1298 | CONFIG_USB_ZERO=m | 1285 | CONFIG_USB_ZERO=m |
| 1286 | # CONFIG_USB_AUDIO is not set | ||
| 1299 | CONFIG_USB_ETH=m | 1287 | CONFIG_USB_ETH=m |
| 1300 | CONFIG_USB_ETH_RNDIS=y | 1288 | CONFIG_USB_ETH_RNDIS=y |
| 1301 | CONFIG_USB_GADGETFS=m | 1289 | CONFIG_USB_GADGETFS=m |
| @@ -1311,7 +1299,7 @@ CONFIG_USB_CDC_COMPOSITE=m | |||
| 1311 | # | 1299 | # |
| 1312 | CONFIG_USB_OTG_UTILS=y | 1300 | CONFIG_USB_OTG_UTILS=y |
| 1313 | # CONFIG_USB_GPIO_VBUS is not set | 1301 | # CONFIG_USB_GPIO_VBUS is not set |
| 1314 | # CONFIG_NOP_USB_XCEIV is not set | 1302 | CONFIG_NOP_USB_XCEIV=m |
| 1315 | CONFIG_MMC=m | 1303 | CONFIG_MMC=m |
| 1316 | # CONFIG_MMC_DEBUG is not set | 1304 | # CONFIG_MMC_DEBUG is not set |
| 1317 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1305 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| @@ -1328,7 +1316,6 @@ CONFIG_MMC_BLOCK=m | |||
| 1328 | # MMC/SD/SDIO Host Controller Drivers | 1316 | # MMC/SD/SDIO Host Controller Drivers |
| 1329 | # | 1317 | # |
| 1330 | # CONFIG_MMC_SDHCI is not set | 1318 | # CONFIG_MMC_SDHCI is not set |
| 1331 | # CONFIG_MMC_DAVINCI is not set | ||
| 1332 | # CONFIG_MEMSTICK is not set | 1319 | # CONFIG_MEMSTICK is not set |
| 1333 | # CONFIG_ACCESSIBILITY is not set | 1320 | # CONFIG_ACCESSIBILITY is not set |
| 1334 | CONFIG_NEW_LEDS=y | 1321 | CONFIG_NEW_LEDS=y |
| @@ -1340,7 +1327,7 @@ CONFIG_LEDS_CLASS=m | |||
| 1340 | # CONFIG_LEDS_PCA9532 is not set | 1327 | # CONFIG_LEDS_PCA9532 is not set |
| 1341 | CONFIG_LEDS_GPIO=m | 1328 | CONFIG_LEDS_GPIO=m |
| 1342 | CONFIG_LEDS_GPIO_PLATFORM=y | 1329 | CONFIG_LEDS_GPIO_PLATFORM=y |
| 1343 | # CONFIG_LEDS_LP5521 is not set | 1330 | # CONFIG_LEDS_LP3944 is not set |
| 1344 | # CONFIG_LEDS_PCA955X is not set | 1331 | # CONFIG_LEDS_PCA955X is not set |
| 1345 | # CONFIG_LEDS_BD2802 is not set | 1332 | # CONFIG_LEDS_BD2802 is not set |
| 1346 | 1333 | ||
| @@ -1386,6 +1373,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1386 | # CONFIG_RTC_DRV_S35390A is not set | 1373 | # CONFIG_RTC_DRV_S35390A is not set |
| 1387 | # CONFIG_RTC_DRV_FM3130 is not set | 1374 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1388 | # CONFIG_RTC_DRV_RX8581 is not set | 1375 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1376 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1389 | 1377 | ||
| 1390 | # | 1378 | # |
| 1391 | # SPI RTC drivers | 1379 | # SPI RTC drivers |
| @@ -1433,14 +1421,16 @@ CONFIG_FS_MBCACHE=y | |||
| 1433 | # CONFIG_REISERFS_FS is not set | 1421 | # CONFIG_REISERFS_FS is not set |
| 1434 | # CONFIG_JFS_FS is not set | 1422 | # CONFIG_JFS_FS is not set |
| 1435 | # CONFIG_FS_POSIX_ACL is not set | 1423 | # CONFIG_FS_POSIX_ACL is not set |
| 1436 | CONFIG_FILE_LOCKING=y | ||
| 1437 | CONFIG_XFS_FS=m | 1424 | CONFIG_XFS_FS=m |
| 1438 | # CONFIG_XFS_QUOTA is not set | 1425 | # CONFIG_XFS_QUOTA is not set |
| 1439 | # CONFIG_XFS_POSIX_ACL is not set | 1426 | # CONFIG_XFS_POSIX_ACL is not set |
| 1440 | # CONFIG_XFS_RT is not set | 1427 | # CONFIG_XFS_RT is not set |
| 1441 | # CONFIG_XFS_DEBUG is not set | 1428 | # CONFIG_XFS_DEBUG is not set |
| 1429 | # CONFIG_GFS2_FS is not set | ||
| 1442 | # CONFIG_OCFS2_FS is not set | 1430 | # CONFIG_OCFS2_FS is not set |
| 1443 | # CONFIG_BTRFS_FS is not set | 1431 | # CONFIG_BTRFS_FS is not set |
| 1432 | CONFIG_FILE_LOCKING=y | ||
| 1433 | CONFIG_FSNOTIFY=y | ||
| 1444 | CONFIG_DNOTIFY=y | 1434 | CONFIG_DNOTIFY=y |
| 1445 | CONFIG_INOTIFY=y | 1435 | CONFIG_INOTIFY=y |
| 1446 | CONFIG_INOTIFY_USER=y | 1436 | CONFIG_INOTIFY_USER=y |
| @@ -1623,6 +1613,7 @@ CONFIG_TIMER_STATS=y | |||
| 1623 | # CONFIG_DEBUG_OBJECTS is not set | 1613 | # CONFIG_DEBUG_OBJECTS is not set |
| 1624 | # CONFIG_SLUB_DEBUG_ON is not set | 1614 | # CONFIG_SLUB_DEBUG_ON is not set |
| 1625 | # CONFIG_SLUB_STATS is not set | 1615 | # CONFIG_SLUB_STATS is not set |
| 1616 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1626 | CONFIG_DEBUG_PREEMPT=y | 1617 | CONFIG_DEBUG_PREEMPT=y |
| 1627 | CONFIG_DEBUG_RT_MUTEXES=y | 1618 | CONFIG_DEBUG_RT_MUTEXES=y |
| 1628 | CONFIG_DEBUG_PI_LIST=y | 1619 | CONFIG_DEBUG_PI_LIST=y |
| @@ -1654,18 +1645,16 @@ CONFIG_DEBUG_BUGVERBOSE=y | |||
| 1654 | # CONFIG_PAGE_POISONING is not set | 1645 | # CONFIG_PAGE_POISONING is not set |
| 1655 | CONFIG_HAVE_FUNCTION_TRACER=y | 1646 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1656 | CONFIG_TRACING_SUPPORT=y | 1647 | CONFIG_TRACING_SUPPORT=y |
| 1657 | 1648 | CONFIG_FTRACE=y | |
| 1658 | # | ||
| 1659 | # Tracers | ||
| 1660 | # | ||
| 1661 | # CONFIG_FUNCTION_TRACER is not set | 1649 | # CONFIG_FUNCTION_TRACER is not set |
| 1662 | # CONFIG_IRQSOFF_TRACER is not set | 1650 | # CONFIG_IRQSOFF_TRACER is not set |
| 1663 | # CONFIG_PREEMPT_TRACER is not set | 1651 | # CONFIG_PREEMPT_TRACER is not set |
| 1664 | # CONFIG_SCHED_TRACER is not set | 1652 | # CONFIG_SCHED_TRACER is not set |
| 1665 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1653 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set |
| 1666 | # CONFIG_EVENT_TRACER is not set | ||
| 1667 | # CONFIG_BOOT_TRACER is not set | 1654 | # CONFIG_BOOT_TRACER is not set |
| 1668 | # CONFIG_TRACE_BRANCH_PROFILING is not set | 1655 | CONFIG_BRANCH_PROFILE_NONE=y |
| 1656 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 1657 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 1669 | # CONFIG_STACK_TRACER is not set | 1658 | # CONFIG_STACK_TRACER is not set |
| 1670 | # CONFIG_KMEMTRACE is not set | 1659 | # CONFIG_KMEMTRACE is not set |
| 1671 | # CONFIG_WORKQUEUE_TRACER is not set | 1660 | # CONFIG_WORKQUEUE_TRACER is not set |
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index be747f5c6cd8..40866c643f13 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig | |||
| @@ -6,6 +6,9 @@ config AINTC | |||
| 6 | config CP_INTC | 6 | config CP_INTC |
| 7 | bool | 7 | bool |
| 8 | 8 | ||
| 9 | config ARCH_DAVINCI_DMx | ||
| 10 | bool | ||
| 11 | |||
| 9 | menu "TI DaVinci Implementations" | 12 | menu "TI DaVinci Implementations" |
| 10 | 13 | ||
| 11 | comment "DaVinci Core Type" | 14 | comment "DaVinci Core Type" |
| @@ -13,20 +16,41 @@ comment "DaVinci Core Type" | |||
| 13 | config ARCH_DAVINCI_DM644x | 16 | config ARCH_DAVINCI_DM644x |
| 14 | bool "DaVinci 644x based system" | 17 | bool "DaVinci 644x based system" |
| 15 | select AINTC | 18 | select AINTC |
| 19 | select ARCH_DAVINCI_DMx | ||
| 16 | 20 | ||
| 17 | config ARCH_DAVINCI_DM355 | 21 | config ARCH_DAVINCI_DM355 |
| 18 | bool "DaVinci 355 based system" | 22 | bool "DaVinci 355 based system" |
| 19 | select AINTC | 23 | select AINTC |
| 24 | select ARCH_DAVINCI_DMx | ||
| 20 | 25 | ||
| 21 | config ARCH_DAVINCI_DM646x | 26 | config ARCH_DAVINCI_DM646x |
| 22 | bool "DaVinci 646x based system" | 27 | bool "DaVinci 646x based system" |
| 23 | select AINTC | 28 | select AINTC |
| 29 | select ARCH_DAVINCI_DMx | ||
| 30 | |||
| 31 | config ARCH_DAVINCI_DA830 | ||
| 32 | bool "DA830/OMAP-L137 based system" | ||
| 33 | select CP_INTC | ||
| 34 | select ARCH_DAVINCI_DA8XX | ||
| 35 | |||
| 36 | config ARCH_DAVINCI_DA850 | ||
| 37 | bool "DA850/OMAP-L138 based system" | ||
| 38 | select CP_INTC | ||
| 39 | select ARCH_DAVINCI_DA8XX | ||
| 40 | |||
| 41 | config ARCH_DAVINCI_DA8XX | ||
| 42 | bool | ||
| 43 | |||
| 44 | config ARCH_DAVINCI_DM365 | ||
| 45 | bool "DaVinci 365 based system" | ||
| 46 | select AINTC | ||
| 47 | select ARCH_DAVINCI_DMx | ||
| 24 | 48 | ||
| 25 | comment "DaVinci Board Type" | 49 | comment "DaVinci Board Type" |
| 26 | 50 | ||
| 27 | config MACH_DAVINCI_EVM | 51 | config MACH_DAVINCI_EVM |
| 28 | bool "TI DM644x EVM" | 52 | bool "TI DM644x EVM" |
| 29 | default y | 53 | default ARCH_DAVINCI_DM644x |
| 30 | depends on ARCH_DAVINCI_DM644x | 54 | depends on ARCH_DAVINCI_DM644x |
| 31 | help | 55 | help |
| 32 | Configure this option to specify the whether the board used | 56 | Configure this option to specify the whether the board used |
| @@ -41,6 +65,7 @@ config MACH_SFFSDR | |||
| 41 | 65 | ||
| 42 | config MACH_DAVINCI_DM355_EVM | 66 | config MACH_DAVINCI_DM355_EVM |
| 43 | bool "TI DM355 EVM" | 67 | bool "TI DM355 EVM" |
| 68 | default ARCH_DAVINCI_DM355 | ||
| 44 | depends on ARCH_DAVINCI_DM355 | 69 | depends on ARCH_DAVINCI_DM355 |
| 45 | help | 70 | help |
| 46 | Configure this option to specify the whether the board used | 71 | Configure this option to specify the whether the board used |
| @@ -55,11 +80,33 @@ config MACH_DM355_LEOPARD | |||
| 55 | 80 | ||
| 56 | config MACH_DAVINCI_DM6467_EVM | 81 | config MACH_DAVINCI_DM6467_EVM |
| 57 | bool "TI DM6467 EVM" | 82 | bool "TI DM6467 EVM" |
| 83 | default ARCH_DAVINCI_DM646x | ||
| 58 | depends on ARCH_DAVINCI_DM646x | 84 | depends on ARCH_DAVINCI_DM646x |
| 59 | help | 85 | help |
| 60 | Configure this option to specify the whether the board used | 86 | Configure this option to specify the whether the board used |
| 61 | for development is a DM6467 EVM | 87 | for development is a DM6467 EVM |
| 62 | 88 | ||
| 89 | config MACH_DAVINCI_DM365_EVM | ||
| 90 | bool "TI DM365 EVM" | ||
| 91 | default ARCH_DAVINCI_DM365 | ||
| 92 | depends on ARCH_DAVINCI_DM365 | ||
| 93 | help | ||
| 94 | Configure this option to specify whether the board used | ||
| 95 | for development is a DM365 EVM | ||
| 96 | |||
| 97 | config MACH_DAVINCI_DA830_EVM | ||
| 98 | bool "TI DA830/OMAP-L137 Reference Platform" | ||
| 99 | default ARCH_DAVINCI_DA830 | ||
| 100 | depends on ARCH_DAVINCI_DA830 | ||
| 101 | help | ||
| 102 | Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. | ||
| 103 | |||
| 104 | config MACH_DAVINCI_DA850_EVM | ||
| 105 | bool "TI DA850/OMAP-L138 Reference Platform" | ||
| 106 | default ARCH_DAVINCI_DA850 | ||
| 107 | depends on ARCH_DAVINCI_DA850 | ||
| 108 | help | ||
| 109 | Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. | ||
| 63 | 110 | ||
| 64 | config DAVINCI_MUX | 111 | config DAVINCI_MUX |
| 65 | bool "DAVINCI multiplexing support" | 112 | bool "DAVINCI multiplexing support" |
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 059ab78084ba..2e11e847313b 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile | |||
| @@ -5,14 +5,17 @@ | |||
| 5 | 5 | ||
| 6 | # Common objects | 6 | # Common objects |
| 7 | obj-y := time.o clock.o serial.o io.o psc.o \ | 7 | obj-y := time.o clock.o serial.o io.o psc.o \ |
| 8 | gpio.o devices.o dma.o usb.o common.o sram.o | 8 | gpio.o dma.o usb.o common.o sram.o |
| 9 | 9 | ||
| 10 | obj-$(CONFIG_DAVINCI_MUX) += mux.o | 10 | obj-$(CONFIG_DAVINCI_MUX) += mux.o |
| 11 | 11 | ||
| 12 | # Chip specific | 12 | # Chip specific |
| 13 | obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o | 13 | obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o |
| 14 | obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o | 14 | obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o |
| 15 | obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o | 15 | obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o |
| 16 | obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o | ||
| 17 | obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o | ||
| 18 | obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o | ||
| 16 | 19 | ||
| 17 | obj-$(CONFIG_AINTC) += irq.o | 20 | obj-$(CONFIG_AINTC) += irq.o |
| 18 | obj-$(CONFIG_CP_INTC) += cp_intc.o | 21 | obj-$(CONFIG_CP_INTC) += cp_intc.o |
| @@ -23,3 +26,6 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o | |||
| 23 | obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o | 26 | obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o |
| 24 | obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o | 27 | obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o |
| 25 | obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o | 28 | obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o |
| 29 | obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o | ||
| 30 | obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o | ||
| 31 | obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o | ||
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index e1dd366f836b..db97ef2c6477 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot | |||
| @@ -1,3 +1,13 @@ | |||
| 1 | ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) | ||
| 2 | ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) | ||
| 3 | $(error Cannot enable DaVinci and DA8XX platforms concurrently) | ||
| 4 | else | ||
| 5 | zreladdr-y := 0xc0008000 | ||
| 6 | params_phys-y := 0xc0000100 | ||
| 7 | initrd_phys-y := 0xc0800000 | ||
| 8 | endif | ||
| 9 | else | ||
| 1 | zreladdr-y := 0x80008000 | 10 | zreladdr-y := 0x80008000 |
| 2 | params_phys-y := 0x80000100 | 11 | params_phys-y := 0x80000100 |
| 3 | initrd_phys-y := 0x80800000 | 12 | initrd_phys-y := 0x80800000 |
| 13 | endif | ||
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c new file mode 100644 index 000000000000..bfbb63936f33 --- /dev/null +++ b/arch/arm/mach-davinci/board-da830-evm.c | |||
| @@ -0,0 +1,157 @@ | |||
| 1 | /* | ||
| 2 | * TI DA830/OMAP L137 EVM board | ||
| 3 | * | ||
| 4 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 5 | * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c | ||
| 6 | * | ||
| 7 | * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under | ||
| 8 | * the terms of the GNU General Public License version 2. This program | ||
| 9 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 10 | * or implied. | ||
| 11 | */ | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/console.h> | ||
| 16 | #include <linux/i2c.h> | ||
| 17 | #include <linux/i2c/at24.h> | ||
| 18 | |||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | |||
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/irqs.h> | ||
| 24 | #include <mach/cp_intc.h> | ||
| 25 | #include <mach/da8xx.h> | ||
| 26 | #include <mach/asp.h> | ||
| 27 | |||
| 28 | #define DA830_EVM_PHY_MASK 0x0 | ||
| 29 | #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ | ||
| 30 | |||
| 31 | static struct at24_platform_data da830_evm_i2c_eeprom_info = { | ||
| 32 | .byte_len = SZ_256K / 8, | ||
| 33 | .page_size = 64, | ||
| 34 | .flags = AT24_FLAG_ADDR16, | ||
| 35 | .setup = davinci_get_mac_addr, | ||
| 36 | .context = (void *)0x7f00, | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { | ||
| 40 | { | ||
| 41 | I2C_BOARD_INFO("24c256", 0x50), | ||
| 42 | .platform_data = &da830_evm_i2c_eeprom_info, | ||
| 43 | }, | ||
| 44 | { | ||
| 45 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | ||
| 46 | } | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { | ||
| 50 | .bus_freq = 100, /* kHz */ | ||
| 51 | .bus_delay = 0, /* usec */ | ||
| 52 | }; | ||
| 53 | |||
| 54 | static struct davinci_uart_config da830_evm_uart_config __initdata = { | ||
| 55 | .enabled_uarts = 0x7, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static u8 da830_iis_serializer_direction[] = { | ||
| 59 | RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 60 | INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 61 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 62 | }; | ||
| 63 | |||
| 64 | static struct snd_platform_data da830_evm_snd_data = { | ||
| 65 | .tx_dma_offset = 0x2000, | ||
| 66 | .rx_dma_offset = 0x2000, | ||
| 67 | .op_mode = DAVINCI_MCASP_IIS_MODE, | ||
| 68 | .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), | ||
| 69 | .tdm_slots = 2, | ||
| 70 | .serial_dir = da830_iis_serializer_direction, | ||
| 71 | .eventq_no = EVENTQ_0, | ||
| 72 | .version = MCASP_VERSION_2, | ||
| 73 | .txnumevt = 1, | ||
| 74 | .rxnumevt = 1, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static __init void da830_evm_init(void) | ||
| 78 | { | ||
| 79 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 80 | int ret; | ||
| 81 | |||
| 82 | ret = da8xx_register_edma(); | ||
| 83 | if (ret) | ||
| 84 | pr_warning("da830_evm_init: edma registration failed: %d\n", | ||
| 85 | ret); | ||
| 86 | |||
| 87 | ret = da8xx_pinmux_setup(da830_i2c0_pins); | ||
| 88 | if (ret) | ||
| 89 | pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", | ||
| 90 | ret); | ||
| 91 | |||
| 92 | ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); | ||
| 93 | if (ret) | ||
| 94 | pr_warning("da830_evm_init: i2c0 registration failed: %d\n", | ||
| 95 | ret); | ||
| 96 | |||
| 97 | soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; | ||
| 98 | soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; | ||
| 99 | soc_info->emac_pdata->rmii_en = 1; | ||
| 100 | |||
| 101 | ret = da8xx_pinmux_setup(da830_cpgmac_pins); | ||
| 102 | if (ret) | ||
| 103 | pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", | ||
| 104 | ret); | ||
| 105 | |||
| 106 | ret = da8xx_register_emac(); | ||
| 107 | if (ret) | ||
| 108 | pr_warning("da830_evm_init: emac registration failed: %d\n", | ||
| 109 | ret); | ||
| 110 | |||
| 111 | ret = da8xx_register_watchdog(); | ||
| 112 | if (ret) | ||
| 113 | pr_warning("da830_evm_init: watchdog registration failed: %d\n", | ||
| 114 | ret); | ||
| 115 | |||
| 116 | davinci_serial_init(&da830_evm_uart_config); | ||
| 117 | i2c_register_board_info(1, da830_evm_i2c_devices, | ||
| 118 | ARRAY_SIZE(da830_evm_i2c_devices)); | ||
| 119 | |||
| 120 | ret = da8xx_pinmux_setup(da830_mcasp1_pins); | ||
| 121 | if (ret) | ||
| 122 | pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", | ||
| 123 | ret); | ||
| 124 | |||
| 125 | da8xx_init_mcasp(1, &da830_evm_snd_data); | ||
| 126 | } | ||
| 127 | |||
| 128 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 129 | static int __init da830_evm_console_init(void) | ||
| 130 | { | ||
| 131 | return add_preferred_console("ttyS", 2, "115200"); | ||
| 132 | } | ||
| 133 | console_initcall(da830_evm_console_init); | ||
| 134 | #endif | ||
| 135 | |||
| 136 | static __init void da830_evm_irq_init(void) | ||
| 137 | { | ||
| 138 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 139 | |||
| 140 | cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, | ||
| 141 | soc_info->intc_irq_prios); | ||
| 142 | } | ||
| 143 | |||
| 144 | static void __init da830_evm_map_io(void) | ||
| 145 | { | ||
| 146 | da830_init(); | ||
| 147 | } | ||
| 148 | |||
| 149 | MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP L137 EVM") | ||
| 150 | .phys_io = IO_PHYS, | ||
| 151 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | ||
| 152 | .boot_params = (DA8XX_DDR_BASE + 0x100), | ||
| 153 | .map_io = da830_evm_map_io, | ||
| 154 | .init_irq = da830_evm_irq_init, | ||
| 155 | .timer = &davinci_timer, | ||
| 156 | .init_machine = da830_evm_init, | ||
| 157 | MACHINE_END | ||
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c new file mode 100644 index 000000000000..c759d72494e0 --- /dev/null +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
| @@ -0,0 +1,415 @@ | |||
| 1 | /* | ||
| 2 | * TI DA850/OMAP-L138 EVM board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Derived from: arch/arm/mach-davinci/board-da830-evm.c | ||
| 7 | * Original Copyrights follow: | ||
| 8 | * | ||
| 9 | * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under | ||
| 10 | * the terms of the GNU General Public License version 2. This program | ||
| 11 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 12 | * or implied. | ||
| 13 | */ | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/console.h> | ||
| 18 | #include <linux/i2c.h> | ||
| 19 | #include <linux/i2c/at24.h> | ||
| 20 | #include <linux/gpio.h> | ||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/mtd/mtd.h> | ||
| 23 | #include <linux/mtd/nand.h> | ||
| 24 | #include <linux/mtd/partitions.h> | ||
| 25 | #include <linux/mtd/physmap.h> | ||
| 26 | |||
| 27 | #include <asm/mach-types.h> | ||
| 28 | #include <asm/mach/arch.h> | ||
| 29 | |||
| 30 | #include <mach/common.h> | ||
| 31 | #include <mach/irqs.h> | ||
| 32 | #include <mach/cp_intc.h> | ||
| 33 | #include <mach/da8xx.h> | ||
| 34 | #include <mach/nand.h> | ||
| 35 | |||
| 36 | #define DA850_EVM_PHY_MASK 0x1 | ||
| 37 | #define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ | ||
| 38 | |||
| 39 | #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) | ||
| 40 | #define DA850_LCD_PWR_PIN GPIO_TO_PIN(8, 10) | ||
| 41 | |||
| 42 | #define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) | ||
| 43 | #define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) | ||
| 44 | |||
| 45 | static struct mtd_partition da850_evm_norflash_partition[] = { | ||
| 46 | { | ||
| 47 | .name = "NOR filesystem", | ||
| 48 | .offset = 0, | ||
| 49 | .size = MTDPART_SIZ_FULL, | ||
| 50 | .mask_flags = 0, | ||
| 51 | }, | ||
| 52 | }; | ||
| 53 | |||
| 54 | static struct physmap_flash_data da850_evm_norflash_data = { | ||
| 55 | .width = 2, | ||
| 56 | .parts = da850_evm_norflash_partition, | ||
| 57 | .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition), | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct resource da850_evm_norflash_resource[] = { | ||
| 61 | { | ||
| 62 | .start = DA8XX_AEMIF_CS2_BASE, | ||
| 63 | .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, | ||
| 64 | .flags = IORESOURCE_MEM, | ||
| 65 | }, | ||
| 66 | }; | ||
| 67 | |||
| 68 | static struct platform_device da850_evm_norflash_device = { | ||
| 69 | .name = "physmap-flash", | ||
| 70 | .id = 0, | ||
| 71 | .dev = { | ||
| 72 | .platform_data = &da850_evm_norflash_data, | ||
| 73 | }, | ||
| 74 | .num_resources = 1, | ||
| 75 | .resource = da850_evm_norflash_resource, | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash | ||
| 79 | * (128K blocks). It may be used instead of the (default) SPI flash | ||
| 80 | * to boot, using TI's tools to install the secondary boot loader | ||
| 81 | * (UBL) and U-Boot. | ||
| 82 | */ | ||
| 83 | struct mtd_partition da850_evm_nandflash_partition[] = { | ||
| 84 | { | ||
| 85 | .name = "u-boot env", | ||
| 86 | .offset = 0, | ||
| 87 | .size = SZ_128K, | ||
| 88 | .mask_flags = MTD_WRITEABLE, | ||
| 89 | }, | ||
| 90 | { | ||
| 91 | .name = "UBL", | ||
| 92 | .offset = MTDPART_OFS_APPEND, | ||
| 93 | .size = SZ_128K, | ||
| 94 | .mask_flags = MTD_WRITEABLE, | ||
| 95 | }, | ||
| 96 | { | ||
| 97 | .name = "u-boot", | ||
| 98 | .offset = MTDPART_OFS_APPEND, | ||
| 99 | .size = 4 * SZ_128K, | ||
| 100 | .mask_flags = MTD_WRITEABLE, | ||
| 101 | }, | ||
| 102 | { | ||
| 103 | .name = "kernel", | ||
| 104 | .offset = 0x200000, | ||
| 105 | .size = SZ_2M, | ||
| 106 | .mask_flags = 0, | ||
| 107 | }, | ||
| 108 | { | ||
| 109 | .name = "filesystem", | ||
| 110 | .offset = MTDPART_OFS_APPEND, | ||
| 111 | .size = MTDPART_SIZ_FULL, | ||
| 112 | .mask_flags = 0, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct davinci_nand_pdata da850_evm_nandflash_data = { | ||
| 117 | .parts = da850_evm_nandflash_partition, | ||
| 118 | .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), | ||
| 119 | .ecc_mode = NAND_ECC_HW, | ||
| 120 | .options = NAND_USE_FLASH_BBT, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static struct resource da850_evm_nandflash_resource[] = { | ||
| 124 | { | ||
| 125 | .start = DA8XX_AEMIF_CS3_BASE, | ||
| 126 | .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, | ||
| 127 | .flags = IORESOURCE_MEM, | ||
| 128 | }, | ||
| 129 | { | ||
| 130 | .start = DA8XX_AEMIF_CTL_BASE, | ||
| 131 | .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, | ||
| 132 | .flags = IORESOURCE_MEM, | ||
| 133 | }, | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct platform_device da850_evm_nandflash_device = { | ||
| 137 | .name = "davinci_nand", | ||
| 138 | .id = 1, | ||
| 139 | .dev = { | ||
| 140 | .platform_data = &da850_evm_nandflash_data, | ||
| 141 | }, | ||
| 142 | .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), | ||
| 143 | .resource = da850_evm_nandflash_resource, | ||
| 144 | }; | ||
| 145 | |||
| 146 | static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { | ||
| 147 | { | ||
| 148 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | ||
| 149 | } | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { | ||
| 153 | .bus_freq = 100, /* kHz */ | ||
| 154 | .bus_delay = 0, /* usec */ | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct davinci_uart_config da850_evm_uart_config __initdata = { | ||
| 158 | .enabled_uarts = 0x7, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct platform_device *da850_evm_devices[] __initdata = { | ||
| 162 | &da850_evm_nandflash_device, | ||
| 163 | &da850_evm_norflash_device, | ||
| 164 | }; | ||
| 165 | |||
| 166 | /* davinci da850 evm audio machine driver */ | ||
| 167 | static u8 da850_iis_serializer_direction[] = { | ||
| 168 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 169 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 170 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, | ||
| 171 | RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 172 | }; | ||
| 173 | |||
| 174 | static struct snd_platform_data da850_evm_snd_data = { | ||
| 175 | .tx_dma_offset = 0x2000, | ||
| 176 | .rx_dma_offset = 0x2000, | ||
| 177 | .op_mode = DAVINCI_MCASP_IIS_MODE, | ||
| 178 | .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), | ||
| 179 | .tdm_slots = 2, | ||
| 180 | .serial_dir = da850_iis_serializer_direction, | ||
| 181 | .eventq_no = EVENTQ_1, | ||
| 182 | .version = MCASP_VERSION_2, | ||
| 183 | .txnumevt = 1, | ||
| 184 | .rxnumevt = 1, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static int da850_evm_mmc_get_ro(int index) | ||
| 188 | { | ||
| 189 | return gpio_get_value(DA850_MMCSD_WP_PIN); | ||
| 190 | } | ||
| 191 | |||
| 192 | static int da850_evm_mmc_get_cd(int index) | ||
| 193 | { | ||
| 194 | return !gpio_get_value(DA850_MMCSD_CD_PIN); | ||
| 195 | } | ||
| 196 | |||
| 197 | static struct davinci_mmc_config da850_mmc_config = { | ||
| 198 | .get_ro = da850_evm_mmc_get_ro, | ||
| 199 | .get_cd = da850_evm_mmc_get_cd, | ||
| 200 | .wires = 4, | ||
| 201 | .version = MMC_CTLR_VERSION_2, | ||
| 202 | }; | ||
| 203 | |||
| 204 | static int da850_lcd_hw_init(void) | ||
| 205 | { | ||
| 206 | int status; | ||
| 207 | |||
| 208 | status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n"); | ||
| 209 | if (status < 0) | ||
| 210 | return status; | ||
| 211 | |||
| 212 | status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n"); | ||
| 213 | if (status < 0) { | ||
| 214 | gpio_free(DA850_LCD_BL_PIN); | ||
| 215 | return status; | ||
| 216 | } | ||
| 217 | |||
| 218 | gpio_direction_output(DA850_LCD_BL_PIN, 0); | ||
| 219 | gpio_direction_output(DA850_LCD_PWR_PIN, 0); | ||
| 220 | |||
| 221 | /* disable lcd backlight */ | ||
| 222 | gpio_set_value(DA850_LCD_BL_PIN, 0); | ||
| 223 | |||
| 224 | /* disable lcd power */ | ||
| 225 | gpio_set_value(DA850_LCD_PWR_PIN, 0); | ||
| 226 | |||
| 227 | /* enable lcd power */ | ||
| 228 | gpio_set_value(DA850_LCD_PWR_PIN, 1); | ||
| 229 | |||
| 230 | /* enable lcd backlight */ | ||
| 231 | gpio_set_value(DA850_LCD_BL_PIN, 1); | ||
| 232 | |||
| 233 | return 0; | ||
| 234 | } | ||
| 235 | |||
| 236 | #define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 | ||
| 237 | #define DA8XX_AEMIF_ASIZE_16BIT 0x1 | ||
| 238 | |||
| 239 | static void __init da850_evm_init_nor(void) | ||
| 240 | { | ||
| 241 | void __iomem *aemif_addr; | ||
| 242 | |||
| 243 | aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); | ||
| 244 | |||
| 245 | /* Configure data bus width of CS2 to 16 bit */ | ||
| 246 | writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | | ||
| 247 | DA8XX_AEMIF_ASIZE_16BIT, | ||
| 248 | aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); | ||
| 249 | |||
| 250 | iounmap(aemif_addr); | ||
| 251 | } | ||
| 252 | |||
| 253 | #if defined(CONFIG_MTD_PHYSMAP) || \ | ||
| 254 | defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 255 | #define HAS_NOR 1 | ||
| 256 | #else | ||
| 257 | #define HAS_NOR 0 | ||
| 258 | #endif | ||
| 259 | |||
| 260 | #if defined(CONFIG_MMC_DAVINCI) || \ | ||
| 261 | defined(CONFIG_MMC_DAVINCI_MODULE) | ||
| 262 | #define HAS_MMC 1 | ||
| 263 | #else | ||
| 264 | #define HAS_MMC 0 | ||
| 265 | #endif | ||
| 266 | |||
| 267 | static __init void da850_evm_init(void) | ||
| 268 | { | ||
| 269 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 270 | int ret; | ||
| 271 | |||
| 272 | ret = da8xx_pinmux_setup(da850_nand_pins); | ||
| 273 | if (ret) | ||
| 274 | pr_warning("da850_evm_init: nand mux setup failed: %d\n", | ||
| 275 | ret); | ||
| 276 | |||
| 277 | ret = da8xx_pinmux_setup(da850_nor_pins); | ||
| 278 | if (ret) | ||
| 279 | pr_warning("da850_evm_init: nor mux setup failed: %d\n", | ||
| 280 | ret); | ||
| 281 | |||
| 282 | da850_evm_init_nor(); | ||
| 283 | |||
| 284 | platform_add_devices(da850_evm_devices, | ||
| 285 | ARRAY_SIZE(da850_evm_devices)); | ||
| 286 | |||
| 287 | ret = da8xx_register_edma(); | ||
| 288 | if (ret) | ||
| 289 | pr_warning("da850_evm_init: edma registration failed: %d\n", | ||
| 290 | ret); | ||
| 291 | |||
| 292 | ret = da8xx_pinmux_setup(da850_i2c0_pins); | ||
| 293 | if (ret) | ||
| 294 | pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n", | ||
| 295 | ret); | ||
| 296 | |||
| 297 | ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); | ||
| 298 | if (ret) | ||
| 299 | pr_warning("da850_evm_init: i2c0 registration failed: %d\n", | ||
| 300 | ret); | ||
| 301 | |||
| 302 | soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; | ||
| 303 | soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; | ||
| 304 | soc_info->emac_pdata->rmii_en = 0; | ||
| 305 | |||
| 306 | ret = da8xx_pinmux_setup(da850_cpgmac_pins); | ||
| 307 | if (ret) | ||
| 308 | pr_warning("da850_evm_init: cpgmac mux setup failed: %d\n", | ||
| 309 | ret); | ||
| 310 | |||
| 311 | ret = da8xx_register_emac(); | ||
| 312 | if (ret) | ||
| 313 | pr_warning("da850_evm_init: emac registration failed: %d\n", | ||
| 314 | ret); | ||
| 315 | |||
| 316 | ret = da8xx_register_watchdog(); | ||
| 317 | if (ret) | ||
| 318 | pr_warning("da830_evm_init: watchdog registration failed: %d\n", | ||
| 319 | ret); | ||
| 320 | |||
| 321 | if (HAS_MMC) { | ||
| 322 | if (HAS_NOR) | ||
| 323 | pr_warning("WARNING: both NOR Flash and MMC/SD are " | ||
| 324 | "enabled, but they share AEMIF pins.\n" | ||
| 325 | "\tDisable one of them.\n"); | ||
| 326 | |||
| 327 | ret = da8xx_pinmux_setup(da850_mmcsd0_pins); | ||
| 328 | if (ret) | ||
| 329 | pr_warning("da850_evm_init: mmcsd0 mux setup failed:" | ||
| 330 | " %d\n", ret); | ||
| 331 | |||
| 332 | ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); | ||
| 333 | if (ret) | ||
| 334 | pr_warning("da850_evm_init: can not open GPIO %d\n", | ||
| 335 | DA850_MMCSD_CD_PIN); | ||
| 336 | gpio_direction_input(DA850_MMCSD_CD_PIN); | ||
| 337 | |||
| 338 | ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); | ||
| 339 | if (ret) | ||
| 340 | pr_warning("da850_evm_init: can not open GPIO %d\n", | ||
| 341 | DA850_MMCSD_WP_PIN); | ||
| 342 | gpio_direction_input(DA850_MMCSD_WP_PIN); | ||
| 343 | |||
| 344 | ret = da8xx_register_mmcsd0(&da850_mmc_config); | ||
| 345 | if (ret) | ||
| 346 | pr_warning("da850_evm_init: mmcsd0 registration failed:" | ||
| 347 | " %d\n", ret); | ||
| 348 | } | ||
| 349 | |||
| 350 | davinci_serial_init(&da850_evm_uart_config); | ||
| 351 | |||
| 352 | i2c_register_board_info(1, da850_evm_i2c_devices, | ||
| 353 | ARRAY_SIZE(da850_evm_i2c_devices)); | ||
| 354 | |||
| 355 | /* | ||
| 356 | * shut down uart 0 and 1; they are not used on the board and | ||
| 357 | * accessing them causes endless "too much work in irq53" messages | ||
| 358 | * with arago fs | ||
| 359 | */ | ||
| 360 | __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); | ||
| 361 | __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); | ||
| 362 | |||
| 363 | ret = da8xx_pinmux_setup(da850_mcasp_pins); | ||
| 364 | if (ret) | ||
| 365 | pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", | ||
| 366 | ret); | ||
| 367 | |||
| 368 | da8xx_init_mcasp(0, &da850_evm_snd_data); | ||
| 369 | |||
| 370 | ret = da8xx_pinmux_setup(da850_lcdcntl_pins); | ||
| 371 | if (ret) | ||
| 372 | pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", | ||
| 373 | ret); | ||
| 374 | |||
| 375 | ret = da850_lcd_hw_init(); | ||
| 376 | if (ret) | ||
| 377 | pr_warning("da850_evm_init: lcd initialization failed: %d\n", | ||
| 378 | ret); | ||
| 379 | |||
| 380 | ret = da8xx_register_lcdc(); | ||
| 381 | if (ret) | ||
| 382 | pr_warning("da850_evm_init: lcdc registration failed: %d\n", | ||
| 383 | ret); | ||
| 384 | } | ||
| 385 | |||
| 386 | #ifdef CONFIG_SERIAL_8250_CONSOLE | ||
| 387 | static int __init da850_evm_console_init(void) | ||
| 388 | { | ||
| 389 | return add_preferred_console("ttyS", 2, "115200"); | ||
| 390 | } | ||
| 391 | console_initcall(da850_evm_console_init); | ||
| 392 | #endif | ||
| 393 | |||
| 394 | static __init void da850_evm_irq_init(void) | ||
| 395 | { | ||
| 396 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 397 | |||
| 398 | cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ, | ||
| 399 | soc_info->intc_irq_prios); | ||
| 400 | } | ||
| 401 | |||
| 402 | static void __init da850_evm_map_io(void) | ||
| 403 | { | ||
| 404 | da850_init(); | ||
| 405 | } | ||
| 406 | |||
| 407 | MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") | ||
| 408 | .phys_io = IO_PHYS, | ||
| 409 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | ||
| 410 | .boot_params = (DA8XX_DDR_BASE + 0x100), | ||
| 411 | .map_io = da850_evm_map_io, | ||
| 412 | .init_irq = da850_evm_irq_init, | ||
| 413 | .timer = &davinci_timer, | ||
| 414 | .init_machine = da850_evm_init, | ||
| 415 | MACHINE_END | ||
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index d6ab64ccd496..77e806798822 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c | |||
| @@ -20,6 +20,8 @@ | |||
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | #include <linux/gpio.h> | 21 | #include <linux/gpio.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/videodev2.h> | ||
| 24 | #include <media/tvp514x.h> | ||
| 23 | #include <linux/spi/spi.h> | 25 | #include <linux/spi/spi.h> |
| 24 | #include <linux/spi/eeprom.h> | 26 | #include <linux/spi/eeprom.h> |
| 25 | 27 | ||
| @@ -117,6 +119,8 @@ static struct davinci_i2c_platform_data i2c_pdata = { | |||
| 117 | .bus_delay = 0 /* usec */, | 119 | .bus_delay = 0 /* usec */, |
| 118 | }; | 120 | }; |
| 119 | 121 | ||
| 122 | static struct snd_platform_data dm355_evm_snd_data; | ||
| 123 | |||
| 120 | static int dm355evm_mmc_gpios = -EINVAL; | 124 | static int dm355evm_mmc_gpios = -EINVAL; |
| 121 | 125 | ||
| 122 | static void dm355evm_mmcsd_gpios(unsigned gpio) | 126 | static void dm355evm_mmcsd_gpios(unsigned gpio) |
| @@ -134,11 +138,11 @@ static void dm355evm_mmcsd_gpios(unsigned gpio) | |||
| 134 | } | 138 | } |
| 135 | 139 | ||
| 136 | static struct i2c_board_info dm355evm_i2c_info[] = { | 140 | static struct i2c_board_info dm355evm_i2c_info[] = { |
| 137 | { I2C_BOARD_INFO("dm355evm_msp", 0x25), | 141 | { I2C_BOARD_INFO("dm355evm_msp", 0x25), |
| 138 | .platform_data = dm355evm_mmcsd_gpios, | 142 | .platform_data = dm355evm_mmcsd_gpios, |
| 139 | /* plus irq */ }, | 143 | }, |
| 140 | /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ | 144 | /* { plus irq }, */ |
| 141 | /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ | 145 | { I2C_BOARD_INFO("tlv320aic33", 0x1b), }, |
| 142 | }; | 146 | }; |
| 143 | 147 | ||
| 144 | static void __init evm_init_i2c(void) | 148 | static void __init evm_init_i2c(void) |
| @@ -177,6 +181,72 @@ static struct platform_device dm355evm_dm9000 = { | |||
| 177 | .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), | 181 | .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), |
| 178 | }; | 182 | }; |
| 179 | 183 | ||
| 184 | static struct tvp514x_platform_data tvp5146_pdata = { | ||
| 185 | .clk_polarity = 0, | ||
| 186 | .hs_polarity = 1, | ||
| 187 | .vs_polarity = 1 | ||
| 188 | }; | ||
| 189 | |||
| 190 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) | ||
| 191 | /* Inputs available at the TVP5146 */ | ||
| 192 | static struct v4l2_input tvp5146_inputs[] = { | ||
| 193 | { | ||
| 194 | .index = 0, | ||
| 195 | .name = "Composite", | ||
| 196 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
| 197 | .std = TVP514X_STD_ALL, | ||
| 198 | }, | ||
| 199 | { | ||
| 200 | .index = 1, | ||
| 201 | .name = "S-Video", | ||
| 202 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
| 203 | .std = TVP514X_STD_ALL, | ||
| 204 | }, | ||
| 205 | }; | ||
| 206 | |||
| 207 | /* | ||
| 208 | * this is the route info for connecting each input to decoder | ||
| 209 | * ouput that goes to vpfe. There is a one to one correspondence | ||
| 210 | * with tvp5146_inputs | ||
| 211 | */ | ||
| 212 | static struct vpfe_route tvp5146_routes[] = { | ||
| 213 | { | ||
| 214 | .input = INPUT_CVBS_VI2B, | ||
| 215 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | ||
| 216 | }, | ||
| 217 | { | ||
| 218 | .input = INPUT_SVIDEO_VI2C_VI1C, | ||
| 219 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | ||
| 220 | }, | ||
| 221 | }; | ||
| 222 | |||
| 223 | static struct vpfe_subdev_info vpfe_sub_devs[] = { | ||
| 224 | { | ||
| 225 | .name = "tvp5146", | ||
| 226 | .grp_id = 0, | ||
| 227 | .num_inputs = ARRAY_SIZE(tvp5146_inputs), | ||
| 228 | .inputs = tvp5146_inputs, | ||
| 229 | .routes = tvp5146_routes, | ||
| 230 | .can_route = 1, | ||
| 231 | .ccdc_if_params = { | ||
| 232 | .if_type = VPFE_BT656, | ||
| 233 | .hdpol = VPFE_PINPOL_POSITIVE, | ||
| 234 | .vdpol = VPFE_PINPOL_POSITIVE, | ||
| 235 | }, | ||
| 236 | .board_info = { | ||
| 237 | I2C_BOARD_INFO("tvp5146", 0x5d), | ||
| 238 | .platform_data = &tvp5146_pdata, | ||
| 239 | }, | ||
| 240 | } | ||
| 241 | }; | ||
| 242 | |||
| 243 | static struct vpfe_config vpfe_cfg = { | ||
| 244 | .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), | ||
| 245 | .sub_devs = vpfe_sub_devs, | ||
| 246 | .card_name = "DM355 EVM", | ||
| 247 | .ccdc = "DM355 CCDC", | ||
| 248 | }; | ||
| 249 | |||
| 180 | static struct platform_device *davinci_evm_devices[] __initdata = { | 250 | static struct platform_device *davinci_evm_devices[] __initdata = { |
| 181 | &dm355evm_dm9000, | 251 | &dm355evm_dm9000, |
| 182 | &davinci_nand_device, | 252 | &davinci_nand_device, |
| @@ -188,6 +258,8 @@ static struct davinci_uart_config uart_config __initdata = { | |||
| 188 | 258 | ||
| 189 | static void __init dm355_evm_map_io(void) | 259 | static void __init dm355_evm_map_io(void) |
| 190 | { | 260 | { |
| 261 | /* setup input configuration for VPFE input devices */ | ||
| 262 | dm355_set_vpfe_config(&vpfe_cfg); | ||
| 191 | dm355_init(); | 263 | dm355_init(); |
| 192 | } | 264 | } |
| 193 | 265 | ||
| @@ -279,6 +351,9 @@ static __init void dm355_evm_init(void) | |||
| 279 | 351 | ||
| 280 | dm355_init_spi0(BIT(0), dm355_evm_spi_info, | 352 | dm355_init_spi0(BIT(0), dm355_evm_spi_info, |
| 281 | ARRAY_SIZE(dm355_evm_spi_info)); | 353 | ARRAY_SIZE(dm355_evm_spi_info)); |
| 354 | |||
| 355 | /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ | ||
| 356 | dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); | ||
| 282 | } | 357 | } |
| 283 | 358 | ||
| 284 | static __init void dm355_evm_irq_init(void) | 359 | static __init void dm355_evm_irq_init(void) |
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c new file mode 100644 index 000000000000..a1d5e7dac741 --- /dev/null +++ b/arch/arm/mach-davinci/board-dm365-evm.c | |||
| @@ -0,0 +1,492 @@ | |||
| 1 | /* | ||
| 2 | * TI DaVinci DM365 EVM board support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments Incorporated | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/dma-mapping.h> | ||
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/i2c/at24.h> | ||
| 23 | #include <linux/leds.h> | ||
| 24 | #include <linux/mtd/mtd.h> | ||
| 25 | #include <linux/mtd/partitions.h> | ||
| 26 | #include <linux/mtd/nand.h> | ||
| 27 | #include <asm/setup.h> | ||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/map.h> | ||
| 31 | #include <mach/mux.h> | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <mach/dm365.h> | ||
| 34 | #include <mach/psc.h> | ||
| 35 | #include <mach/common.h> | ||
| 36 | #include <mach/i2c.h> | ||
| 37 | #include <mach/serial.h> | ||
| 38 | #include <mach/common.h> | ||
| 39 | #include <mach/mmc.h> | ||
| 40 | #include <mach/nand.h> | ||
| 41 | |||
| 42 | |||
| 43 | static inline int have_imager(void) | ||
| 44 | { | ||
| 45 | /* REVISIT when it's supported, trigger via Kconfig */ | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | static inline int have_tvp7002(void) | ||
| 50 | { | ||
| 51 | /* REVISIT when it's supported, trigger via Kconfig */ | ||
| 52 | return 0; | ||
| 53 | } | ||
| 54 | |||
| 55 | |||
| 56 | #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 | ||
| 57 | #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | ||
| 58 | #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 | ||
| 59 | |||
| 60 | #define DM365_EVM_PHY_MASK (0x2) | ||
| 61 | #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ | ||
| 62 | |||
| 63 | /* | ||
| 64 | * A MAX-II CPLD is used for various board control functions. | ||
| 65 | */ | ||
| 66 | #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) | ||
| 67 | |||
| 68 | #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ | ||
| 69 | #define CPLD_TEST CPLD_OFFSET(0,1) | ||
| 70 | #define CPLD_LEDS CPLD_OFFSET(0,2) | ||
| 71 | #define CPLD_MUX CPLD_OFFSET(0,3) | ||
| 72 | #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ | ||
| 73 | #define CPLD_POWER CPLD_OFFSET(1,1) | ||
| 74 | #define CPLD_VIDEO CPLD_OFFSET(1,2) | ||
| 75 | #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ | ||
| 76 | |||
| 77 | #define CPLD_DILC_OUT CPLD_OFFSET(2,0) | ||
| 78 | #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ | ||
| 79 | |||
| 80 | #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) | ||
| 81 | #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) | ||
| 82 | #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) | ||
| 83 | #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) | ||
| 84 | #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) | ||
| 85 | #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) | ||
| 86 | #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) | ||
| 87 | #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) | ||
| 88 | #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) | ||
| 89 | |||
| 90 | #define CPLD_RESETS CPLD_OFFSET(4,3) | ||
| 91 | |||
| 92 | #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) | ||
| 93 | #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) | ||
| 94 | #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) | ||
| 95 | #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) | ||
| 96 | #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) | ||
| 97 | #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) | ||
| 98 | |||
| 99 | static void __iomem *cpld; | ||
| 100 | |||
| 101 | |||
| 102 | /* NOTE: this is geared for the standard config, with a socketed | ||
| 103 | * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you | ||
| 104 | * swap chips with a different block size, partitioning will | ||
| 105 | * need to be changed. This NAND chip MT29F16G08FAA is the default | ||
| 106 | * NAND shipped with the Spectrum Digital DM365 EVM | ||
| 107 | */ | ||
| 108 | #define NAND_BLOCK_SIZE SZ_128K | ||
| 109 | |||
| 110 | static struct mtd_partition davinci_nand_partitions[] = { | ||
| 111 | { | ||
| 112 | /* UBL (a few copies) plus U-Boot */ | ||
| 113 | .name = "bootloader", | ||
| 114 | .offset = 0, | ||
| 115 | .size = 28 * NAND_BLOCK_SIZE, | ||
| 116 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 117 | }, { | ||
| 118 | /* U-Boot environment */ | ||
| 119 | .name = "params", | ||
| 120 | .offset = MTDPART_OFS_APPEND, | ||
| 121 | .size = 2 * NAND_BLOCK_SIZE, | ||
| 122 | .mask_flags = 0, | ||
| 123 | }, { | ||
| 124 | .name = "kernel", | ||
| 125 | .offset = MTDPART_OFS_APPEND, | ||
| 126 | .size = SZ_4M, | ||
| 127 | .mask_flags = 0, | ||
| 128 | }, { | ||
| 129 | .name = "filesystem1", | ||
| 130 | .offset = MTDPART_OFS_APPEND, | ||
| 131 | .size = SZ_512M, | ||
| 132 | .mask_flags = 0, | ||
| 133 | }, { | ||
| 134 | .name = "filesystem2", | ||
| 135 | .offset = MTDPART_OFS_APPEND, | ||
| 136 | .size = MTDPART_SIZ_FULL, | ||
| 137 | .mask_flags = 0, | ||
| 138 | } | ||
| 139 | /* two blocks with bad block table (and mirror) at the end */ | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct davinci_nand_pdata davinci_nand_data = { | ||
| 143 | .mask_chipsel = BIT(14), | ||
| 144 | .parts = davinci_nand_partitions, | ||
| 145 | .nr_parts = ARRAY_SIZE(davinci_nand_partitions), | ||
| 146 | .ecc_mode = NAND_ECC_HW, | ||
| 147 | .options = NAND_USE_FLASH_BBT, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct resource davinci_nand_resources[] = { | ||
| 151 | { | ||
| 152 | .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, | ||
| 153 | .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, | ||
| 154 | .flags = IORESOURCE_MEM, | ||
| 155 | }, { | ||
| 156 | .start = DM365_ASYNC_EMIF_CONTROL_BASE, | ||
| 157 | .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, | ||
| 158 | .flags = IORESOURCE_MEM, | ||
| 159 | }, | ||
| 160 | }; | ||
| 161 | |||
| 162 | static struct platform_device davinci_nand_device = { | ||
| 163 | .name = "davinci_nand", | ||
| 164 | .id = 0, | ||
| 165 | .num_resources = ARRAY_SIZE(davinci_nand_resources), | ||
| 166 | .resource = davinci_nand_resources, | ||
| 167 | .dev = { | ||
| 168 | .platform_data = &davinci_nand_data, | ||
| 169 | }, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static struct at24_platform_data eeprom_info = { | ||
| 173 | .byte_len = (256*1024) / 8, | ||
| 174 | .page_size = 64, | ||
| 175 | .flags = AT24_FLAG_ADDR16, | ||
| 176 | .setup = davinci_get_mac_addr, | ||
| 177 | .context = (void *)0x7f00, | ||
| 178 | }; | ||
| 179 | |||
| 180 | static struct i2c_board_info i2c_info[] = { | ||
| 181 | { | ||
| 182 | I2C_BOARD_INFO("24c256", 0x50), | ||
| 183 | .platform_data = &eeprom_info, | ||
| 184 | }, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static struct davinci_i2c_platform_data i2c_pdata = { | ||
| 188 | .bus_freq = 400 /* kHz */, | ||
| 189 | .bus_delay = 0 /* usec */, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static int cpld_mmc_get_cd(int module) | ||
| 193 | { | ||
| 194 | if (!cpld) | ||
| 195 | return -ENXIO; | ||
| 196 | |||
| 197 | /* low == card present */ | ||
| 198 | return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); | ||
| 199 | } | ||
| 200 | |||
| 201 | static int cpld_mmc_get_ro(int module) | ||
| 202 | { | ||
| 203 | if (!cpld) | ||
| 204 | return -ENXIO; | ||
| 205 | |||
| 206 | /* high == card's write protect switch active */ | ||
| 207 | return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); | ||
| 208 | } | ||
| 209 | |||
| 210 | static struct davinci_mmc_config dm365evm_mmc_config = { | ||
| 211 | .get_cd = cpld_mmc_get_cd, | ||
| 212 | .get_ro = cpld_mmc_get_ro, | ||
| 213 | .wires = 4, | ||
| 214 | .max_freq = 50000000, | ||
| 215 | .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, | ||
| 216 | .version = MMC_CTLR_VERSION_2, | ||
| 217 | }; | ||
| 218 | |||
| 219 | static void dm365evm_emac_configure(void) | ||
| 220 | { | ||
| 221 | /* | ||
| 222 | * EMAC pins are multiplexed with GPIO and UART | ||
| 223 | * Further details are available at the DM365 ARM | ||
| 224 | * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 | ||
| 225 | */ | ||
| 226 | davinci_cfg_reg(DM365_EMAC_TX_EN); | ||
| 227 | davinci_cfg_reg(DM365_EMAC_TX_CLK); | ||
| 228 | davinci_cfg_reg(DM365_EMAC_COL); | ||
| 229 | davinci_cfg_reg(DM365_EMAC_TXD3); | ||
| 230 | davinci_cfg_reg(DM365_EMAC_TXD2); | ||
| 231 | davinci_cfg_reg(DM365_EMAC_TXD1); | ||
| 232 | davinci_cfg_reg(DM365_EMAC_TXD0); | ||
| 233 | davinci_cfg_reg(DM365_EMAC_RXD3); | ||
| 234 | davinci_cfg_reg(DM365_EMAC_RXD2); | ||
| 235 | davinci_cfg_reg(DM365_EMAC_RXD1); | ||
| 236 | davinci_cfg_reg(DM365_EMAC_RXD0); | ||
| 237 | davinci_cfg_reg(DM365_EMAC_RX_CLK); | ||
| 238 | davinci_cfg_reg(DM365_EMAC_RX_DV); | ||
| 239 | davinci_cfg_reg(DM365_EMAC_RX_ER); | ||
| 240 | davinci_cfg_reg(DM365_EMAC_CRS); | ||
| 241 | davinci_cfg_reg(DM365_EMAC_MDIO); | ||
| 242 | davinci_cfg_reg(DM365_EMAC_MDCLK); | ||
| 243 | |||
| 244 | /* | ||
| 245 | * EMAC interrupts are multiplexed with GPIO interrupts | ||
| 246 | * Details are available at the DM365 ARM | ||
| 247 | * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 | ||
| 248 | */ | ||
| 249 | davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); | ||
| 250 | davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); | ||
| 251 | davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); | ||
| 252 | davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); | ||
| 253 | } | ||
| 254 | |||
| 255 | static void dm365evm_mmc_configure(void) | ||
| 256 | { | ||
| 257 | /* | ||
| 258 | * MMC/SD pins are multiplexed with GPIO and EMIF | ||
| 259 | * Further details are available at the DM365 ARM | ||
| 260 | * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 | ||
| 261 | */ | ||
| 262 | davinci_cfg_reg(DM365_SD1_CLK); | ||
| 263 | davinci_cfg_reg(DM365_SD1_CMD); | ||
| 264 | davinci_cfg_reg(DM365_SD1_DATA3); | ||
| 265 | davinci_cfg_reg(DM365_SD1_DATA2); | ||
| 266 | davinci_cfg_reg(DM365_SD1_DATA1); | ||
| 267 | davinci_cfg_reg(DM365_SD1_DATA0); | ||
| 268 | } | ||
| 269 | |||
| 270 | static void __init evm_init_i2c(void) | ||
| 271 | { | ||
| 272 | davinci_init_i2c(&i2c_pdata); | ||
| 273 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); | ||
| 274 | } | ||
| 275 | |||
| 276 | static struct platform_device *dm365_evm_nand_devices[] __initdata = { | ||
| 277 | &davinci_nand_device, | ||
| 278 | }; | ||
| 279 | |||
| 280 | static inline int have_leds(void) | ||
| 281 | { | ||
| 282 | #ifdef CONFIG_LEDS_CLASS | ||
| 283 | return 1; | ||
| 284 | #else | ||
| 285 | return 0; | ||
| 286 | #endif | ||
| 287 | } | ||
| 288 | |||
| 289 | struct cpld_led { | ||
| 290 | struct led_classdev cdev; | ||
| 291 | u8 mask; | ||
| 292 | }; | ||
| 293 | |||
| 294 | static const struct { | ||
| 295 | const char *name; | ||
| 296 | const char *trigger; | ||
| 297 | } cpld_leds[] = { | ||
| 298 | { "dm365evm::ds2", }, | ||
| 299 | { "dm365evm::ds3", }, | ||
| 300 | { "dm365evm::ds4", }, | ||
| 301 | { "dm365evm::ds5", }, | ||
| 302 | { "dm365evm::ds6", "nand-disk", }, | ||
| 303 | { "dm365evm::ds7", "mmc1", }, | ||
| 304 | { "dm365evm::ds8", "mmc0", }, | ||
| 305 | { "dm365evm::ds9", "heartbeat", }, | ||
| 306 | }; | ||
| 307 | |||
| 308 | static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) | ||
| 309 | { | ||
| 310 | struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); | ||
| 311 | u8 reg = __raw_readb(cpld + CPLD_LEDS); | ||
| 312 | |||
| 313 | if (b != LED_OFF) | ||
| 314 | reg &= ~led->mask; | ||
| 315 | else | ||
| 316 | reg |= led->mask; | ||
| 317 | __raw_writeb(reg, cpld + CPLD_LEDS); | ||
| 318 | } | ||
| 319 | |||
| 320 | static enum led_brightness cpld_led_get(struct led_classdev *cdev) | ||
| 321 | { | ||
| 322 | struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); | ||
| 323 | u8 reg = __raw_readb(cpld + CPLD_LEDS); | ||
| 324 | |||
| 325 | return (reg & led->mask) ? LED_OFF : LED_FULL; | ||
| 326 | } | ||
| 327 | |||
| 328 | static int __init cpld_leds_init(void) | ||
| 329 | { | ||
| 330 | int i; | ||
| 331 | |||
| 332 | if (!have_leds() || !cpld) | ||
| 333 | return 0; | ||
| 334 | |||
| 335 | /* setup LEDs */ | ||
| 336 | __raw_writeb(0xff, cpld + CPLD_LEDS); | ||
| 337 | for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { | ||
| 338 | struct cpld_led *led; | ||
| 339 | |||
| 340 | led = kzalloc(sizeof(*led), GFP_KERNEL); | ||
| 341 | if (!led) | ||
| 342 | break; | ||
| 343 | |||
| 344 | led->cdev.name = cpld_leds[i].name; | ||
| 345 | led->cdev.brightness_set = cpld_led_set; | ||
| 346 | led->cdev.brightness_get = cpld_led_get; | ||
| 347 | led->cdev.default_trigger = cpld_leds[i].trigger; | ||
| 348 | led->mask = BIT(i); | ||
| 349 | |||
| 350 | if (led_classdev_register(NULL, &led->cdev) < 0) { | ||
| 351 | kfree(led); | ||
| 352 | break; | ||
| 353 | } | ||
| 354 | } | ||
| 355 | |||
| 356 | return 0; | ||
| 357 | } | ||
| 358 | /* run after subsys_initcall() for LEDs */ | ||
| 359 | fs_initcall(cpld_leds_init); | ||
| 360 | |||
| 361 | |||
| 362 | static void __init evm_init_cpld(void) | ||
| 363 | { | ||
| 364 | u8 mux, resets; | ||
| 365 | const char *label; | ||
| 366 | struct clk *aemif_clk; | ||
| 367 | |||
| 368 | /* Make sure we can configure the CPLD through CS1. Then | ||
| 369 | * leave it on for later access to MMC and LED registers. | ||
| 370 | */ | ||
| 371 | aemif_clk = clk_get(NULL, "aemif"); | ||
| 372 | if (IS_ERR(aemif_clk)) | ||
| 373 | return; | ||
| 374 | clk_enable(aemif_clk); | ||
| 375 | |||
| 376 | if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, | ||
| 377 | "cpld") == NULL) | ||
| 378 | goto fail; | ||
| 379 | cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); | ||
| 380 | if (!cpld) { | ||
| 381 | release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, | ||
| 382 | SECTION_SIZE); | ||
| 383 | fail: | ||
| 384 | pr_err("ERROR: can't map CPLD\n"); | ||
| 385 | clk_disable(aemif_clk); | ||
| 386 | return; | ||
| 387 | } | ||
| 388 | |||
| 389 | /* External muxing for some signals */ | ||
| 390 | mux = 0; | ||
| 391 | |||
| 392 | /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). | ||
| 393 | * NOTE: SW4 bus width setting must match! | ||
| 394 | */ | ||
| 395 | if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { | ||
| 396 | /* external keypad mux */ | ||
| 397 | mux |= BIT(7); | ||
| 398 | |||
| 399 | platform_add_devices(dm365_evm_nand_devices, | ||
| 400 | ARRAY_SIZE(dm365_evm_nand_devices)); | ||
| 401 | } else { | ||
| 402 | /* no OneNAND support yet */ | ||
| 403 | } | ||
| 404 | |||
| 405 | /* Leave external chips in reset when unused. */ | ||
| 406 | resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); | ||
| 407 | |||
| 408 | /* Static video input config with SN74CBT16214 1-of-3 mux: | ||
| 409 | * - port b1 == tvp7002 (mux lowbits == 1 or 6) | ||
| 410 | * - port b2 == imager (mux lowbits == 2 or 7) | ||
| 411 | * - port b3 == tvp5146 (mux lowbits == 5) | ||
| 412 | * | ||
| 413 | * Runtime switching could work too, with limitations. | ||
| 414 | */ | ||
| 415 | if (have_imager()) { | ||
| 416 | label = "HD imager"; | ||
| 417 | mux |= 1; | ||
| 418 | |||
| 419 | /* externally mux MMC1/ENET/AIC33 to imager */ | ||
| 420 | mux |= BIT(6) | BIT(5) | BIT(3); | ||
| 421 | } else { | ||
| 422 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 423 | |||
| 424 | /* we can use MMC1 ... */ | ||
| 425 | dm365evm_mmc_configure(); | ||
| 426 | davinci_setup_mmc(1, &dm365evm_mmc_config); | ||
| 427 | |||
| 428 | /* ... and ENET ... */ | ||
| 429 | dm365evm_emac_configure(); | ||
| 430 | soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; | ||
| 431 | soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; | ||
| 432 | resets &= ~BIT(3); | ||
| 433 | |||
| 434 | /* ... and AIC33 */ | ||
| 435 | resets &= ~BIT(1); | ||
| 436 | |||
| 437 | if (have_tvp7002()) { | ||
| 438 | mux |= 2; | ||
| 439 | resets &= ~BIT(2); | ||
| 440 | label = "tvp7002 HD"; | ||
| 441 | } else { | ||
| 442 | /* default to tvp5146 */ | ||
| 443 | mux |= 5; | ||
| 444 | resets &= ~BIT(0); | ||
| 445 | label = "tvp5146 SD"; | ||
| 446 | } | ||
| 447 | } | ||
| 448 | __raw_writeb(mux, cpld + CPLD_MUX); | ||
| 449 | __raw_writeb(resets, cpld + CPLD_RESETS); | ||
| 450 | pr_info("EVM: %s video input\n", label); | ||
| 451 | |||
| 452 | /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ | ||
| 453 | } | ||
| 454 | |||
| 455 | static struct davinci_uart_config uart_config __initdata = { | ||
| 456 | .enabled_uarts = (1 << 0), | ||
| 457 | }; | ||
| 458 | |||
| 459 | static void __init dm365_evm_map_io(void) | ||
| 460 | { | ||
| 461 | dm365_init(); | ||
| 462 | } | ||
| 463 | |||
| 464 | static __init void dm365_evm_init(void) | ||
| 465 | { | ||
| 466 | evm_init_i2c(); | ||
| 467 | davinci_serial_init(&uart_config); | ||
| 468 | |||
| 469 | dm365evm_emac_configure(); | ||
| 470 | dm365evm_mmc_configure(); | ||
| 471 | |||
| 472 | davinci_setup_mmc(0, &dm365evm_mmc_config); | ||
| 473 | |||
| 474 | /* maybe setup mmc1/etc ... _after_ mmc0 */ | ||
| 475 | evm_init_cpld(); | ||
| 476 | } | ||
| 477 | |||
| 478 | static __init void dm365_evm_irq_init(void) | ||
| 479 | { | ||
| 480 | davinci_irq_init(); | ||
| 481 | } | ||
| 482 | |||
| 483 | MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") | ||
| 484 | .phys_io = IO_PHYS, | ||
| 485 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | ||
| 486 | .boot_params = (0x80000100), | ||
| 487 | .map_io = dm365_evm_map_io, | ||
| 488 | .init_irq = dm365_evm_irq_init, | ||
| 489 | .timer = &davinci_timer, | ||
| 490 | .init_machine = dm365_evm_init, | ||
| 491 | MACHINE_END | ||
| 492 | |||
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 56c8cd01de9a..1213a0087ad4 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c | |||
| @@ -28,6 +28,9 @@ | |||
| 28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| 29 | #include <linux/phy.h> | 29 | #include <linux/phy.h> |
| 30 | #include <linux/clk.h> | 30 | #include <linux/clk.h> |
| 31 | #include <linux/videodev2.h> | ||
| 32 | |||
| 33 | #include <media/tvp514x.h> | ||
| 31 | 34 | ||
| 32 | #include <asm/setup.h> | 35 | #include <asm/setup.h> |
| 33 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| @@ -194,6 +197,72 @@ static struct platform_device davinci_fb_device = { | |||
| 194 | .num_resources = 0, | 197 | .num_resources = 0, |
| 195 | }; | 198 | }; |
| 196 | 199 | ||
| 200 | static struct tvp514x_platform_data tvp5146_pdata = { | ||
| 201 | .clk_polarity = 0, | ||
| 202 | .hs_polarity = 1, | ||
| 203 | .vs_polarity = 1 | ||
| 204 | }; | ||
| 205 | |||
| 206 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) | ||
| 207 | /* Inputs available at the TVP5146 */ | ||
| 208 | static struct v4l2_input tvp5146_inputs[] = { | ||
| 209 | { | ||
| 210 | .index = 0, | ||
| 211 | .name = "Composite", | ||
| 212 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
| 213 | .std = TVP514X_STD_ALL, | ||
| 214 | }, | ||
| 215 | { | ||
| 216 | .index = 1, | ||
| 217 | .name = "S-Video", | ||
| 218 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
| 219 | .std = TVP514X_STD_ALL, | ||
| 220 | }, | ||
| 221 | }; | ||
| 222 | |||
| 223 | /* | ||
| 224 | * this is the route info for connecting each input to decoder | ||
| 225 | * ouput that goes to vpfe. There is a one to one correspondence | ||
| 226 | * with tvp5146_inputs | ||
| 227 | */ | ||
| 228 | static struct vpfe_route tvp5146_routes[] = { | ||
| 229 | { | ||
| 230 | .input = INPUT_CVBS_VI2B, | ||
| 231 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | ||
| 232 | }, | ||
| 233 | { | ||
| 234 | .input = INPUT_SVIDEO_VI2C_VI1C, | ||
| 235 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | ||
| 236 | }, | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct vpfe_subdev_info vpfe_sub_devs[] = { | ||
| 240 | { | ||
| 241 | .name = "tvp5146", | ||
| 242 | .grp_id = 0, | ||
| 243 | .num_inputs = ARRAY_SIZE(tvp5146_inputs), | ||
| 244 | .inputs = tvp5146_inputs, | ||
| 245 | .routes = tvp5146_routes, | ||
| 246 | .can_route = 1, | ||
| 247 | .ccdc_if_params = { | ||
| 248 | .if_type = VPFE_BT656, | ||
| 249 | .hdpol = VPFE_PINPOL_POSITIVE, | ||
| 250 | .vdpol = VPFE_PINPOL_POSITIVE, | ||
| 251 | }, | ||
| 252 | .board_info = { | ||
| 253 | I2C_BOARD_INFO("tvp5146", 0x5d), | ||
| 254 | .platform_data = &tvp5146_pdata, | ||
| 255 | }, | ||
| 256 | }, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static struct vpfe_config vpfe_cfg = { | ||
| 260 | .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), | ||
| 261 | .sub_devs = vpfe_sub_devs, | ||
| 262 | .card_name = "DM6446 EVM", | ||
| 263 | .ccdc = "DM6446 CCDC", | ||
| 264 | }; | ||
| 265 | |||
| 197 | static struct platform_device rtc_dev = { | 266 | static struct platform_device rtc_dev = { |
| 198 | .name = "rtc_davinci_evm", | 267 | .name = "rtc_davinci_evm", |
| 199 | .id = -1, | 268 | .id = -1, |
| @@ -225,6 +294,8 @@ static struct platform_device ide_dev = { | |||
| 225 | }, | 294 | }, |
| 226 | }; | 295 | }; |
| 227 | 296 | ||
| 297 | static struct snd_platform_data dm644x_evm_snd_data; | ||
| 298 | |||
| 228 | /*----------------------------------------------------------------------*/ | 299 | /*----------------------------------------------------------------------*/ |
| 229 | 300 | ||
| 230 | /* | 301 | /* |
| @@ -557,10 +628,9 @@ static struct i2c_board_info __initdata i2c_info[] = { | |||
| 557 | I2C_BOARD_INFO("24c256", 0x50), | 628 | I2C_BOARD_INFO("24c256", 0x50), |
| 558 | .platform_data = &eeprom_info, | 629 | .platform_data = &eeprom_info, |
| 559 | }, | 630 | }, |
| 560 | /* ALSO: | 631 | { |
| 561 | * - tvl320aic33 audio codec (0x1b) | 632 | I2C_BOARD_INFO("tlv320aic33", 0x1b), |
| 562 | * - tvp5146 video decoder (0x5d) | 633 | }, |
| 563 | */ | ||
| 564 | }; | 634 | }; |
| 565 | 635 | ||
| 566 | /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), | 636 | /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), |
| @@ -590,6 +660,8 @@ static struct davinci_uart_config uart_config __initdata = { | |||
| 590 | static void __init | 660 | static void __init |
| 591 | davinci_evm_map_io(void) | 661 | davinci_evm_map_io(void) |
| 592 | { | 662 | { |
| 663 | /* setup input configuration for VPFE input devices */ | ||
| 664 | dm644x_set_vpfe_config(&vpfe_cfg); | ||
| 593 | dm644x_init(); | 665 | dm644x_init(); |
| 594 | } | 666 | } |
| 595 | 667 | ||
| @@ -666,6 +738,7 @@ static __init void davinci_evm_init(void) | |||
| 666 | davinci_setup_mmc(0, &dm6446evm_mmc_config); | 738 | davinci_setup_mmc(0, &dm6446evm_mmc_config); |
| 667 | 739 | ||
| 668 | davinci_serial_init(&uart_config); | 740 | davinci_serial_init(&uart_config); |
| 741 | dm644x_init_asp(&dm644x_evm_snd_data); | ||
| 669 | 742 | ||
| 670 | soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; | 743 | soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; |
| 671 | soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; | 744 | soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; |
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 8657e72debc1..24e0e13b1492 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c | |||
| @@ -34,6 +34,8 @@ | |||
| 34 | #include <linux/i2c/pcf857x.h> | 34 | #include <linux/i2c/pcf857x.h> |
| 35 | #include <linux/etherdevice.h> | 35 | #include <linux/etherdevice.h> |
| 36 | 36 | ||
| 37 | #include <media/tvp514x.h> | ||
| 38 | |||
| 37 | #include <asm/setup.h> | 39 | #include <asm/setup.h> |
| 38 | #include <asm/mach-types.h> | 40 | #include <asm/mach-types.h> |
| 39 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
| @@ -48,13 +50,89 @@ | |||
| 48 | #include <mach/mmc.h> | 50 | #include <mach/mmc.h> |
| 49 | #include <mach/emac.h> | 51 | #include <mach/emac.h> |
| 50 | 52 | ||
| 53 | #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ | ||
| 54 | defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) | ||
| 55 | #define HAS_ATA 1 | ||
| 56 | #else | ||
| 57 | #define HAS_ATA 0 | ||
| 58 | #endif | ||
| 59 | |||
| 60 | /* CPLD Register 0 bits to control ATA */ | ||
| 61 | #define DM646X_EVM_ATA_RST BIT(0) | ||
| 62 | #define DM646X_EVM_ATA_PWD BIT(1) | ||
| 63 | |||
| 51 | #define DM646X_EVM_PHY_MASK (0x2) | 64 | #define DM646X_EVM_PHY_MASK (0x2) |
| 52 | #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ | 65 | #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ |
| 53 | 66 | ||
| 67 | #define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38) | ||
| 68 | #define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c) | ||
| 69 | #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) | ||
| 70 | #define VCH2CLK_SYSCLK8 (BIT(9)) | ||
| 71 | #define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) | ||
| 72 | #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12)) | ||
| 73 | #define VCH3CLK_SYSCLK8 (BIT(13)) | ||
| 74 | #define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) | ||
| 75 | |||
| 76 | #define VIDCH2CLK (BIT(10)) | ||
| 77 | #define VIDCH3CLK (BIT(11)) | ||
| 78 | #define VIDCH1CLK (BIT(4)) | ||
| 79 | #define TVP7002_INPUT (BIT(4)) | ||
| 80 | #define TVP5147_INPUT (~BIT(4)) | ||
| 81 | #define VPIF_INPUT_ONE_CHANNEL (BIT(5)) | ||
| 82 | #define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) | ||
| 83 | #define TVP5147_CH0 "tvp514x-0" | ||
| 84 | #define TVP5147_CH1 "tvp514x-1" | ||
| 85 | |||
| 86 | static void __iomem *vpif_vidclkctl_reg; | ||
| 87 | static void __iomem *vpif_vsclkdis_reg; | ||
| 88 | /* spin lock for updating above registers */ | ||
| 89 | static spinlock_t vpif_reg_lock; | ||
| 90 | |||
| 54 | static struct davinci_uart_config uart_config __initdata = { | 91 | static struct davinci_uart_config uart_config __initdata = { |
| 55 | .enabled_uarts = (1 << 0), | 92 | .enabled_uarts = (1 << 0), |
| 56 | }; | 93 | }; |
| 57 | 94 | ||
| 95 | /* CPLD Register 0 Client: used for I/O Control */ | ||
| 96 | static int cpld_reg0_probe(struct i2c_client *client, | ||
| 97 | const struct i2c_device_id *id) | ||
| 98 | { | ||
| 99 | if (HAS_ATA) { | ||
| 100 | u8 data; | ||
| 101 | struct i2c_msg msg[2] = { | ||
| 102 | { | ||
| 103 | .addr = client->addr, | ||
| 104 | .flags = I2C_M_RD, | ||
| 105 | .len = 1, | ||
| 106 | .buf = &data, | ||
| 107 | }, | ||
| 108 | { | ||
| 109 | .addr = client->addr, | ||
| 110 | .flags = 0, | ||
| 111 | .len = 1, | ||
| 112 | .buf = &data, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */ | ||
| 117 | i2c_transfer(client->adapter, msg, 1); | ||
| 118 | data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD); | ||
| 119 | i2c_transfer(client->adapter, msg + 1, 1); | ||
| 120 | } | ||
| 121 | |||
| 122 | return 0; | ||
| 123 | } | ||
| 124 | |||
| 125 | static const struct i2c_device_id cpld_reg_ids[] = { | ||
| 126 | { "cpld_reg0", 0, }, | ||
| 127 | { }, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static struct i2c_driver dm6467evm_cpld_driver = { | ||
| 131 | .driver.name = "cpld_reg0", | ||
| 132 | .id_table = cpld_reg_ids, | ||
| 133 | .probe = cpld_reg0_probe, | ||
| 134 | }; | ||
| 135 | |||
| 58 | /* LEDS */ | 136 | /* LEDS */ |
| 59 | 137 | ||
| 60 | static struct gpio_led evm_leds[] = { | 138 | static struct gpio_led evm_leds[] = { |
| @@ -206,6 +284,69 @@ static struct at24_platform_data eeprom_info = { | |||
| 206 | .context = (void *)0x7f00, | 284 | .context = (void *)0x7f00, |
| 207 | }; | 285 | }; |
| 208 | 286 | ||
| 287 | static u8 dm646x_iis_serializer_direction[] = { | ||
| 288 | TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, | ||
| 289 | }; | ||
| 290 | |||
| 291 | static u8 dm646x_dit_serializer_direction[] = { | ||
| 292 | TX_MODE, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static struct snd_platform_data dm646x_evm_snd_data[] = { | ||
| 296 | { | ||
| 297 | .tx_dma_offset = 0x400, | ||
| 298 | .rx_dma_offset = 0x400, | ||
| 299 | .op_mode = DAVINCI_MCASP_IIS_MODE, | ||
| 300 | .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), | ||
| 301 | .tdm_slots = 2, | ||
| 302 | .serial_dir = dm646x_iis_serializer_direction, | ||
| 303 | .eventq_no = EVENTQ_0, | ||
| 304 | }, | ||
| 305 | { | ||
| 306 | .tx_dma_offset = 0x400, | ||
| 307 | .rx_dma_offset = 0, | ||
| 308 | .op_mode = DAVINCI_MCASP_DIT_MODE, | ||
| 309 | .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), | ||
| 310 | .tdm_slots = 32, | ||
| 311 | .serial_dir = dm646x_dit_serializer_direction, | ||
| 312 | .eventq_no = EVENTQ_0, | ||
| 313 | }, | ||
| 314 | }; | ||
| 315 | |||
| 316 | static struct i2c_client *cpld_client; | ||
| 317 | |||
| 318 | static int cpld_video_probe(struct i2c_client *client, | ||
| 319 | const struct i2c_device_id *id) | ||
| 320 | { | ||
| 321 | cpld_client = client; | ||
| 322 | return 0; | ||
| 323 | } | ||
| 324 | |||
| 325 | static int __devexit cpld_video_remove(struct i2c_client *client) | ||
| 326 | { | ||
| 327 | cpld_client = NULL; | ||
| 328 | return 0; | ||
| 329 | } | ||
| 330 | |||
| 331 | static const struct i2c_device_id cpld_video_id[] = { | ||
| 332 | { "cpld_video", 0 }, | ||
| 333 | { } | ||
| 334 | }; | ||
| 335 | |||
| 336 | static struct i2c_driver cpld_video_driver = { | ||
| 337 | .driver = { | ||
| 338 | .name = "cpld_video", | ||
| 339 | }, | ||
| 340 | .probe = cpld_video_probe, | ||
| 341 | .remove = cpld_video_remove, | ||
| 342 | .id_table = cpld_video_id, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static void evm_init_cpld(void) | ||
| 346 | { | ||
| 347 | i2c_add_driver(&cpld_video_driver); | ||
| 348 | } | ||
| 349 | |||
| 209 | static struct i2c_board_info __initdata i2c_info[] = { | 350 | static struct i2c_board_info __initdata i2c_info[] = { |
| 210 | { | 351 | { |
| 211 | I2C_BOARD_INFO("24c256", 0x50), | 352 | I2C_BOARD_INFO("24c256", 0x50), |
| @@ -215,6 +356,15 @@ static struct i2c_board_info __initdata i2c_info[] = { | |||
| 215 | I2C_BOARD_INFO("pcf8574a", 0x38), | 356 | I2C_BOARD_INFO("pcf8574a", 0x38), |
| 216 | .platform_data = &pcf_data, | 357 | .platform_data = &pcf_data, |
| 217 | }, | 358 | }, |
| 359 | { | ||
| 360 | I2C_BOARD_INFO("cpld_reg0", 0x3a), | ||
| 361 | }, | ||
| 362 | { | ||
| 363 | I2C_BOARD_INFO("tlv320aic33", 0x18), | ||
| 364 | }, | ||
| 365 | { | ||
| 366 | I2C_BOARD_INFO("cpld_video", 0x3b), | ||
| 367 | }, | ||
| 218 | }; | 368 | }; |
| 219 | 369 | ||
| 220 | static struct davinci_i2c_platform_data i2c_pdata = { | 370 | static struct davinci_i2c_platform_data i2c_pdata = { |
| @@ -222,10 +372,265 @@ static struct davinci_i2c_platform_data i2c_pdata = { | |||
| 222 | .bus_delay = 0 /* usec */, | 372 | .bus_delay = 0 /* usec */, |
| 223 | }; | 373 | }; |
| 224 | 374 | ||
| 375 | static int set_vpif_clock(int mux_mode, int hd) | ||
| 376 | { | ||
| 377 | unsigned long flags; | ||
| 378 | unsigned int value; | ||
| 379 | int val = 0; | ||
| 380 | int err = 0; | ||
| 381 | |||
| 382 | if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client) | ||
| 383 | return -ENXIO; | ||
| 384 | |||
| 385 | /* disable the clock */ | ||
| 386 | spin_lock_irqsave(&vpif_reg_lock, flags); | ||
| 387 | value = __raw_readl(vpif_vsclkdis_reg); | ||
| 388 | value |= (VIDCH3CLK | VIDCH2CLK); | ||
| 389 | __raw_writel(value, vpif_vsclkdis_reg); | ||
| 390 | spin_unlock_irqrestore(&vpif_reg_lock, flags); | ||
| 391 | |||
| 392 | val = i2c_smbus_read_byte(cpld_client); | ||
| 393 | if (val < 0) | ||
| 394 | return val; | ||
| 395 | |||
| 396 | if (mux_mode == 1) | ||
| 397 | val &= ~0x40; | ||
| 398 | else | ||
| 399 | val |= 0x40; | ||
| 400 | |||
| 401 | err = i2c_smbus_write_byte(cpld_client, val); | ||
| 402 | if (err) | ||
| 403 | return err; | ||
| 404 | |||
| 405 | value = __raw_readl(vpif_vidclkctl_reg); | ||
| 406 | value &= ~(VCH2CLK_MASK); | ||
| 407 | value &= ~(VCH3CLK_MASK); | ||
| 408 | |||
| 409 | if (hd >= 1) | ||
| 410 | value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8); | ||
| 411 | else | ||
| 412 | value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); | ||
| 413 | |||
| 414 | __raw_writel(value, vpif_vidclkctl_reg); | ||
| 415 | |||
| 416 | spin_lock_irqsave(&vpif_reg_lock, flags); | ||
| 417 | value = __raw_readl(vpif_vsclkdis_reg); | ||
| 418 | /* enable the clock */ | ||
| 419 | value &= ~(VIDCH3CLK | VIDCH2CLK); | ||
| 420 | __raw_writel(value, vpif_vsclkdis_reg); | ||
| 421 | spin_unlock_irqrestore(&vpif_reg_lock, flags); | ||
| 422 | |||
| 423 | return 0; | ||
| 424 | } | ||
| 425 | |||
| 426 | static struct vpif_subdev_info dm646x_vpif_subdev[] = { | ||
| 427 | { | ||
| 428 | .name = "adv7343", | ||
| 429 | .board_info = { | ||
| 430 | I2C_BOARD_INFO("adv7343", 0x2a), | ||
| 431 | }, | ||
| 432 | }, | ||
| 433 | { | ||
| 434 | .name = "ths7303", | ||
| 435 | .board_info = { | ||
| 436 | I2C_BOARD_INFO("ths7303", 0x2c), | ||
| 437 | }, | ||
| 438 | }, | ||
| 439 | }; | ||
| 440 | |||
| 441 | static const char *output[] = { | ||
| 442 | "Composite", | ||
| 443 | "Component", | ||
| 444 | "S-Video", | ||
| 445 | }; | ||
| 446 | |||
| 447 | static struct vpif_display_config dm646x_vpif_display_config = { | ||
| 448 | .set_clock = set_vpif_clock, | ||
| 449 | .subdevinfo = dm646x_vpif_subdev, | ||
| 450 | .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), | ||
| 451 | .output = output, | ||
| 452 | .output_count = ARRAY_SIZE(output), | ||
| 453 | .card_name = "DM646x EVM", | ||
| 454 | }; | ||
| 455 | |||
| 456 | /** | ||
| 457 | * setup_vpif_input_path() | ||
| 458 | * @channel: channel id (0 - CH0, 1 - CH1) | ||
| 459 | * @sub_dev_name: ptr sub device name | ||
| 460 | * | ||
| 461 | * This will set vpif input to capture data from tvp514x or | ||
| 462 | * tvp7002. | ||
| 463 | */ | ||
| 464 | static int setup_vpif_input_path(int channel, const char *sub_dev_name) | ||
| 465 | { | ||
| 466 | int err = 0; | ||
| 467 | int val; | ||
| 468 | |||
| 469 | /* for channel 1, we don't do anything */ | ||
| 470 | if (channel != 0) | ||
| 471 | return 0; | ||
| 472 | |||
| 473 | if (!cpld_client) | ||
| 474 | return -ENXIO; | ||
| 475 | |||
| 476 | val = i2c_smbus_read_byte(cpld_client); | ||
| 477 | if (val < 0) | ||
| 478 | return val; | ||
| 479 | |||
| 480 | if (!strcmp(sub_dev_name, TVP5147_CH0) || | ||
| 481 | !strcmp(sub_dev_name, TVP5147_CH1)) | ||
| 482 | val &= TVP5147_INPUT; | ||
| 483 | else | ||
| 484 | val |= TVP7002_INPUT; | ||
| 485 | |||
| 486 | err = i2c_smbus_write_byte(cpld_client, val); | ||
| 487 | if (err) | ||
| 488 | return err; | ||
| 489 | return 0; | ||
| 490 | } | ||
| 491 | |||
| 492 | /** | ||
| 493 | * setup_vpif_input_channel_mode() | ||
| 494 | * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel | ||
| 495 | * | ||
| 496 | * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147) | ||
| 497 | */ | ||
| 498 | static int setup_vpif_input_channel_mode(int mux_mode) | ||
| 499 | { | ||
| 500 | unsigned long flags; | ||
| 501 | int err = 0; | ||
| 502 | int val; | ||
| 503 | u32 value; | ||
| 504 | |||
| 505 | if (!vpif_vsclkdis_reg || !cpld_client) | ||
| 506 | return -ENXIO; | ||
| 507 | |||
| 508 | val = i2c_smbus_read_byte(cpld_client); | ||
| 509 | if (val < 0) | ||
| 510 | return val; | ||
| 511 | |||
| 512 | spin_lock_irqsave(&vpif_reg_lock, flags); | ||
| 513 | value = __raw_readl(vpif_vsclkdis_reg); | ||
| 514 | if (mux_mode) { | ||
| 515 | val &= VPIF_INPUT_TWO_CHANNEL; | ||
| 516 | value |= VIDCH1CLK; | ||
| 517 | } else { | ||
| 518 | val |= VPIF_INPUT_ONE_CHANNEL; | ||
| 519 | value &= ~VIDCH1CLK; | ||
| 520 | } | ||
| 521 | __raw_writel(value, vpif_vsclkdis_reg); | ||
| 522 | spin_unlock_irqrestore(&vpif_reg_lock, flags); | ||
| 523 | |||
| 524 | err = i2c_smbus_write_byte(cpld_client, val); | ||
| 525 | if (err) | ||
| 526 | return err; | ||
| 527 | |||
| 528 | return 0; | ||
| 529 | } | ||
| 530 | |||
| 531 | static struct tvp514x_platform_data tvp5146_pdata = { | ||
| 532 | .clk_polarity = 0, | ||
| 533 | .hs_polarity = 1, | ||
| 534 | .vs_polarity = 1 | ||
| 535 | }; | ||
| 536 | |||
| 537 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) | ||
| 538 | |||
| 539 | static struct vpif_subdev_info vpif_capture_sdev_info[] = { | ||
| 540 | { | ||
| 541 | .name = TVP5147_CH0, | ||
| 542 | .board_info = { | ||
| 543 | I2C_BOARD_INFO("tvp5146", 0x5d), | ||
| 544 | .platform_data = &tvp5146_pdata, | ||
| 545 | }, | ||
| 546 | .input = INPUT_CVBS_VI2B, | ||
| 547 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | ||
| 548 | .can_route = 1, | ||
| 549 | .vpif_if = { | ||
| 550 | .if_type = VPIF_IF_BT656, | ||
| 551 | .hd_pol = 1, | ||
| 552 | .vd_pol = 1, | ||
| 553 | .fid_pol = 0, | ||
| 554 | }, | ||
| 555 | }, | ||
| 556 | { | ||
| 557 | .name = TVP5147_CH1, | ||
| 558 | .board_info = { | ||
| 559 | I2C_BOARD_INFO("tvp5146", 0x5c), | ||
| 560 | .platform_data = &tvp5146_pdata, | ||
| 561 | }, | ||
| 562 | .input = INPUT_SVIDEO_VI2C_VI1C, | ||
| 563 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | ||
| 564 | .can_route = 1, | ||
| 565 | .vpif_if = { | ||
| 566 | .if_type = VPIF_IF_BT656, | ||
| 567 | .hd_pol = 1, | ||
| 568 | .vd_pol = 1, | ||
| 569 | .fid_pol = 0, | ||
| 570 | }, | ||
| 571 | }, | ||
| 572 | }; | ||
| 573 | |||
| 574 | static const struct vpif_input dm6467_ch0_inputs[] = { | ||
| 575 | { | ||
| 576 | .input = { | ||
| 577 | .index = 0, | ||
| 578 | .name = "Composite", | ||
| 579 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
| 580 | .std = TVP514X_STD_ALL, | ||
| 581 | }, | ||
| 582 | .subdev_name = TVP5147_CH0, | ||
| 583 | }, | ||
| 584 | }; | ||
| 585 | |||
| 586 | static const struct vpif_input dm6467_ch1_inputs[] = { | ||
| 587 | { | ||
| 588 | .input = { | ||
| 589 | .index = 0, | ||
| 590 | .name = "S-Video", | ||
| 591 | .type = V4L2_INPUT_TYPE_CAMERA, | ||
| 592 | .std = TVP514X_STD_ALL, | ||
| 593 | }, | ||
| 594 | .subdev_name = TVP5147_CH1, | ||
| 595 | }, | ||
| 596 | }; | ||
| 597 | |||
| 598 | static struct vpif_capture_config dm646x_vpif_capture_cfg = { | ||
| 599 | .setup_input_path = setup_vpif_input_path, | ||
| 600 | .setup_input_channel_mode = setup_vpif_input_channel_mode, | ||
| 601 | .subdev_info = vpif_capture_sdev_info, | ||
| 602 | .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info), | ||
| 603 | .chan_config[0] = { | ||
| 604 | .inputs = dm6467_ch0_inputs, | ||
| 605 | .input_count = ARRAY_SIZE(dm6467_ch0_inputs), | ||
| 606 | }, | ||
| 607 | .chan_config[1] = { | ||
| 608 | .inputs = dm6467_ch1_inputs, | ||
| 609 | .input_count = ARRAY_SIZE(dm6467_ch1_inputs), | ||
| 610 | }, | ||
| 611 | }; | ||
| 612 | |||
| 613 | static void __init evm_init_video(void) | ||
| 614 | { | ||
| 615 | vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4); | ||
| 616 | vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4); | ||
| 617 | if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) { | ||
| 618 | pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n"); | ||
| 619 | return; | ||
| 620 | } | ||
| 621 | spin_lock_init(&vpif_reg_lock); | ||
| 622 | |||
| 623 | dm646x_setup_vpif(&dm646x_vpif_display_config, | ||
| 624 | &dm646x_vpif_capture_cfg); | ||
| 625 | } | ||
| 626 | |||
| 225 | static void __init evm_init_i2c(void) | 627 | static void __init evm_init_i2c(void) |
| 226 | { | 628 | { |
| 227 | davinci_init_i2c(&i2c_pdata); | 629 | davinci_init_i2c(&i2c_pdata); |
| 630 | i2c_add_driver(&dm6467evm_cpld_driver); | ||
| 228 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); | 631 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); |
| 632 | evm_init_cpld(); | ||
| 633 | evm_init_video(); | ||
| 229 | } | 634 | } |
| 230 | 635 | ||
| 231 | static void __init davinci_map_io(void) | 636 | static void __init davinci_map_io(void) |
| @@ -239,6 +644,11 @@ static __init void evm_init(void) | |||
| 239 | 644 | ||
| 240 | evm_init_i2c(); | 645 | evm_init_i2c(); |
| 241 | davinci_serial_init(&uart_config); | 646 | davinci_serial_init(&uart_config); |
| 647 | dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); | ||
| 648 | dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); | ||
| 649 | |||
| 650 | if (HAS_ATA) | ||
| 651 | dm646x_init_ide(); | ||
| 242 | 652 | ||
| 243 | soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; | 653 | soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; |
| 244 | soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; | 654 | soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; |
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 39bf321d70a2..83d54d50b5ea 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c | |||
| @@ -227,7 +227,10 @@ static void __init clk_pll_init(struct clk *clk) | |||
| 227 | if (ctrl & PLLCTL_PLLEN) { | 227 | if (ctrl & PLLCTL_PLLEN) { |
| 228 | bypass = 0; | 228 | bypass = 0; |
| 229 | mult = __raw_readl(pll->base + PLLM); | 229 | mult = __raw_readl(pll->base + PLLM); |
| 230 | mult = (mult & PLLM_PLLM_MASK) + 1; | 230 | if (cpu_is_davinci_dm365()) |
| 231 | mult = 2 * (mult & PLLM_PLLM_MASK); | ||
| 232 | else | ||
| 233 | mult = (mult & PLLM_PLLM_MASK) + 1; | ||
| 231 | } else | 234 | } else |
| 232 | bypass = 1; | 235 | bypass = 1; |
| 233 | 236 | ||
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c new file mode 100644 index 000000000000..19b2748357fc --- /dev/null +++ b/arch/arm/mach-davinci/da830.c | |||
| @@ -0,0 +1,1205 @@ | |||
| 1 | /* | ||
| 2 | * TI DA830/OMAP L137 chip specific setup | ||
| 3 | * | ||
| 4 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 5 | * | ||
| 6 | * 2009 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/clk.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | |||
| 16 | #include <asm/mach/map.h> | ||
| 17 | |||
| 18 | #include <mach/clock.h> | ||
| 19 | #include <mach/psc.h> | ||
| 20 | #include <mach/mux.h> | ||
| 21 | #include <mach/irqs.h> | ||
| 22 | #include <mach/cputype.h> | ||
| 23 | #include <mach/common.h> | ||
| 24 | #include <mach/time.h> | ||
| 25 | #include <mach/da8xx.h> | ||
| 26 | #include <mach/asp.h> | ||
| 27 | |||
| 28 | #include "clock.h" | ||
| 29 | #include "mux.h" | ||
| 30 | |||
| 31 | /* Offsets of the 8 compare registers on the da830 */ | ||
| 32 | #define DA830_CMP12_0 0x60 | ||
| 33 | #define DA830_CMP12_1 0x64 | ||
| 34 | #define DA830_CMP12_2 0x68 | ||
| 35 | #define DA830_CMP12_3 0x6c | ||
| 36 | #define DA830_CMP12_4 0x70 | ||
| 37 | #define DA830_CMP12_5 0x74 | ||
| 38 | #define DA830_CMP12_6 0x78 | ||
| 39 | #define DA830_CMP12_7 0x7c | ||
| 40 | |||
| 41 | #define DA830_REF_FREQ 24000000 | ||
| 42 | |||
| 43 | static struct pll_data pll0_data = { | ||
| 44 | .num = 1, | ||
| 45 | .phys_base = DA8XX_PLL0_BASE, | ||
| 46 | .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct clk ref_clk = { | ||
| 50 | .name = "ref_clk", | ||
| 51 | .rate = DA830_REF_FREQ, | ||
| 52 | }; | ||
| 53 | |||
| 54 | static struct clk pll0_clk = { | ||
| 55 | .name = "pll0", | ||
| 56 | .parent = &ref_clk, | ||
| 57 | .pll_data = &pll0_data, | ||
| 58 | .flags = CLK_PLL, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct clk pll0_aux_clk = { | ||
| 62 | .name = "pll0_aux_clk", | ||
| 63 | .parent = &pll0_clk, | ||
| 64 | .flags = CLK_PLL | PRE_PLL, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct clk pll0_sysclk2 = { | ||
| 68 | .name = "pll0_sysclk2", | ||
| 69 | .parent = &pll0_clk, | ||
| 70 | .flags = CLK_PLL, | ||
| 71 | .div_reg = PLLDIV2, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct clk pll0_sysclk3 = { | ||
| 75 | .name = "pll0_sysclk3", | ||
| 76 | .parent = &pll0_clk, | ||
| 77 | .flags = CLK_PLL, | ||
| 78 | .div_reg = PLLDIV3, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static struct clk pll0_sysclk4 = { | ||
| 82 | .name = "pll0_sysclk4", | ||
| 83 | .parent = &pll0_clk, | ||
| 84 | .flags = CLK_PLL, | ||
| 85 | .div_reg = PLLDIV4, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct clk pll0_sysclk5 = { | ||
| 89 | .name = "pll0_sysclk5", | ||
| 90 | .parent = &pll0_clk, | ||
| 91 | .flags = CLK_PLL, | ||
| 92 | .div_reg = PLLDIV5, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct clk pll0_sysclk6 = { | ||
| 96 | .name = "pll0_sysclk6", | ||
| 97 | .parent = &pll0_clk, | ||
| 98 | .flags = CLK_PLL, | ||
| 99 | .div_reg = PLLDIV6, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct clk pll0_sysclk7 = { | ||
| 103 | .name = "pll0_sysclk7", | ||
| 104 | .parent = &pll0_clk, | ||
| 105 | .flags = CLK_PLL, | ||
| 106 | .div_reg = PLLDIV7, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct clk i2c0_clk = { | ||
| 110 | .name = "i2c0", | ||
| 111 | .parent = &pll0_aux_clk, | ||
| 112 | }; | ||
| 113 | |||
| 114 | static struct clk timerp64_0_clk = { | ||
| 115 | .name = "timer0", | ||
| 116 | .parent = &pll0_aux_clk, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct clk timerp64_1_clk = { | ||
| 120 | .name = "timer1", | ||
| 121 | .parent = &pll0_aux_clk, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct clk arm_rom_clk = { | ||
| 125 | .name = "arm_rom", | ||
| 126 | .parent = &pll0_sysclk2, | ||
| 127 | .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, | ||
| 128 | .flags = ALWAYS_ENABLED, | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct clk scr0_ss_clk = { | ||
| 132 | .name = "scr0_ss", | ||
| 133 | .parent = &pll0_sysclk2, | ||
| 134 | .lpsc = DA8XX_LPSC0_SCR0_SS, | ||
| 135 | .flags = ALWAYS_ENABLED, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct clk scr1_ss_clk = { | ||
| 139 | .name = "scr1_ss", | ||
| 140 | .parent = &pll0_sysclk2, | ||
| 141 | .lpsc = DA8XX_LPSC0_SCR1_SS, | ||
| 142 | .flags = ALWAYS_ENABLED, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct clk scr2_ss_clk = { | ||
| 146 | .name = "scr2_ss", | ||
| 147 | .parent = &pll0_sysclk2, | ||
| 148 | .lpsc = DA8XX_LPSC0_SCR2_SS, | ||
| 149 | .flags = ALWAYS_ENABLED, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct clk dmax_clk = { | ||
| 153 | .name = "dmax", | ||
| 154 | .parent = &pll0_sysclk2, | ||
| 155 | .lpsc = DA8XX_LPSC0_DMAX, | ||
| 156 | .flags = ALWAYS_ENABLED, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static struct clk tpcc_clk = { | ||
| 160 | .name = "tpcc", | ||
| 161 | .parent = &pll0_sysclk2, | ||
| 162 | .lpsc = DA8XX_LPSC0_TPCC, | ||
| 163 | .flags = ALWAYS_ENABLED | CLK_PSC, | ||
| 164 | }; | ||
| 165 | |||
| 166 | static struct clk tptc0_clk = { | ||
| 167 | .name = "tptc0", | ||
| 168 | .parent = &pll0_sysclk2, | ||
| 169 | .lpsc = DA8XX_LPSC0_TPTC0, | ||
| 170 | .flags = ALWAYS_ENABLED, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct clk tptc1_clk = { | ||
| 174 | .name = "tptc1", | ||
| 175 | .parent = &pll0_sysclk2, | ||
| 176 | .lpsc = DA8XX_LPSC0_TPTC1, | ||
| 177 | .flags = ALWAYS_ENABLED, | ||
| 178 | }; | ||
| 179 | |||
| 180 | static struct clk mmcsd_clk = { | ||
| 181 | .name = "mmcsd", | ||
| 182 | .parent = &pll0_sysclk2, | ||
| 183 | .lpsc = DA8XX_LPSC0_MMC_SD, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static struct clk uart0_clk = { | ||
| 187 | .name = "uart0", | ||
| 188 | .parent = &pll0_sysclk2, | ||
| 189 | .lpsc = DA8XX_LPSC0_UART0, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct clk uart1_clk = { | ||
| 193 | .name = "uart1", | ||
| 194 | .parent = &pll0_sysclk2, | ||
| 195 | .lpsc = DA8XX_LPSC1_UART1, | ||
| 196 | .psc_ctlr = 1, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct clk uart2_clk = { | ||
| 200 | .name = "uart2", | ||
| 201 | .parent = &pll0_sysclk2, | ||
| 202 | .lpsc = DA8XX_LPSC1_UART2, | ||
| 203 | .psc_ctlr = 1, | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct clk spi0_clk = { | ||
| 207 | .name = "spi0", | ||
| 208 | .parent = &pll0_sysclk2, | ||
| 209 | .lpsc = DA8XX_LPSC0_SPI0, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct clk spi1_clk = { | ||
| 213 | .name = "spi1", | ||
| 214 | .parent = &pll0_sysclk2, | ||
| 215 | .lpsc = DA8XX_LPSC1_SPI1, | ||
| 216 | .psc_ctlr = 1, | ||
| 217 | }; | ||
| 218 | |||
| 219 | static struct clk ecap0_clk = { | ||
| 220 | .name = "ecap0", | ||
| 221 | .parent = &pll0_sysclk2, | ||
| 222 | .lpsc = DA8XX_LPSC1_ECAP, | ||
| 223 | .psc_ctlr = 1, | ||
| 224 | }; | ||
| 225 | |||
| 226 | static struct clk ecap1_clk = { | ||
| 227 | .name = "ecap1", | ||
| 228 | .parent = &pll0_sysclk2, | ||
| 229 | .lpsc = DA8XX_LPSC1_ECAP, | ||
| 230 | .psc_ctlr = 1, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct clk ecap2_clk = { | ||
| 234 | .name = "ecap2", | ||
| 235 | .parent = &pll0_sysclk2, | ||
| 236 | .lpsc = DA8XX_LPSC1_ECAP, | ||
| 237 | .psc_ctlr = 1, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static struct clk pwm0_clk = { | ||
| 241 | .name = "pwm0", | ||
| 242 | .parent = &pll0_sysclk2, | ||
| 243 | .lpsc = DA8XX_LPSC1_PWM, | ||
| 244 | .psc_ctlr = 1, | ||
| 245 | }; | ||
| 246 | |||
| 247 | static struct clk pwm1_clk = { | ||
| 248 | .name = "pwm1", | ||
| 249 | .parent = &pll0_sysclk2, | ||
| 250 | .lpsc = DA8XX_LPSC1_PWM, | ||
| 251 | .psc_ctlr = 1, | ||
| 252 | }; | ||
| 253 | |||
| 254 | static struct clk pwm2_clk = { | ||
| 255 | .name = "pwm2", | ||
| 256 | .parent = &pll0_sysclk2, | ||
| 257 | .lpsc = DA8XX_LPSC1_PWM, | ||
| 258 | .psc_ctlr = 1, | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct clk eqep0_clk = { | ||
| 262 | .name = "eqep0", | ||
| 263 | .parent = &pll0_sysclk2, | ||
| 264 | .lpsc = DA830_LPSC1_EQEP, | ||
| 265 | .psc_ctlr = 1, | ||
| 266 | }; | ||
| 267 | |||
| 268 | static struct clk eqep1_clk = { | ||
| 269 | .name = "eqep1", | ||
| 270 | .parent = &pll0_sysclk2, | ||
| 271 | .lpsc = DA830_LPSC1_EQEP, | ||
| 272 | .psc_ctlr = 1, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct clk lcdc_clk = { | ||
| 276 | .name = "lcdc", | ||
| 277 | .parent = &pll0_sysclk2, | ||
| 278 | .lpsc = DA8XX_LPSC1_LCDC, | ||
| 279 | .psc_ctlr = 1, | ||
| 280 | }; | ||
| 281 | |||
| 282 | static struct clk mcasp0_clk = { | ||
| 283 | .name = "mcasp0", | ||
| 284 | .parent = &pll0_sysclk2, | ||
| 285 | .lpsc = DA8XX_LPSC1_McASP0, | ||
| 286 | .psc_ctlr = 1, | ||
| 287 | }; | ||
| 288 | |||
| 289 | static struct clk mcasp1_clk = { | ||
| 290 | .name = "mcasp1", | ||
| 291 | .parent = &pll0_sysclk2, | ||
| 292 | .lpsc = DA830_LPSC1_McASP1, | ||
| 293 | .psc_ctlr = 1, | ||
| 294 | }; | ||
| 295 | |||
| 296 | static struct clk mcasp2_clk = { | ||
| 297 | .name = "mcasp2", | ||
| 298 | .parent = &pll0_sysclk2, | ||
| 299 | .lpsc = DA830_LPSC1_McASP2, | ||
| 300 | .psc_ctlr = 1, | ||
| 301 | }; | ||
| 302 | |||
| 303 | static struct clk usb20_clk = { | ||
| 304 | .name = "usb20", | ||
| 305 | .parent = &pll0_sysclk2, | ||
| 306 | .lpsc = DA8XX_LPSC1_USB20, | ||
| 307 | .psc_ctlr = 1, | ||
| 308 | }; | ||
| 309 | |||
| 310 | static struct clk aemif_clk = { | ||
| 311 | .name = "aemif", | ||
| 312 | .parent = &pll0_sysclk3, | ||
| 313 | .lpsc = DA8XX_LPSC0_EMIF25, | ||
| 314 | .flags = ALWAYS_ENABLED, | ||
| 315 | }; | ||
| 316 | |||
| 317 | static struct clk aintc_clk = { | ||
| 318 | .name = "aintc", | ||
| 319 | .parent = &pll0_sysclk4, | ||
| 320 | .lpsc = DA8XX_LPSC0_AINTC, | ||
| 321 | .flags = ALWAYS_ENABLED, | ||
| 322 | }; | ||
| 323 | |||
| 324 | static struct clk secu_mgr_clk = { | ||
| 325 | .name = "secu_mgr", | ||
| 326 | .parent = &pll0_sysclk4, | ||
| 327 | .lpsc = DA8XX_LPSC0_SECU_MGR, | ||
| 328 | .flags = ALWAYS_ENABLED, | ||
| 329 | }; | ||
| 330 | |||
| 331 | static struct clk emac_clk = { | ||
| 332 | .name = "emac", | ||
| 333 | .parent = &pll0_sysclk4, | ||
| 334 | .lpsc = DA8XX_LPSC1_CPGMAC, | ||
| 335 | .psc_ctlr = 1, | ||
| 336 | }; | ||
| 337 | |||
| 338 | static struct clk gpio_clk = { | ||
| 339 | .name = "gpio", | ||
| 340 | .parent = &pll0_sysclk4, | ||
| 341 | .lpsc = DA8XX_LPSC1_GPIO, | ||
| 342 | .psc_ctlr = 1, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static struct clk i2c1_clk = { | ||
| 346 | .name = "i2c1", | ||
| 347 | .parent = &pll0_sysclk4, | ||
| 348 | .lpsc = DA8XX_LPSC1_I2C, | ||
| 349 | .psc_ctlr = 1, | ||
| 350 | }; | ||
| 351 | |||
| 352 | static struct clk usb11_clk = { | ||
| 353 | .name = "usb11", | ||
| 354 | .parent = &pll0_sysclk4, | ||
| 355 | .lpsc = DA8XX_LPSC1_USB11, | ||
| 356 | .psc_ctlr = 1, | ||
| 357 | }; | ||
| 358 | |||
| 359 | static struct clk emif3_clk = { | ||
| 360 | .name = "emif3", | ||
| 361 | .parent = &pll0_sysclk5, | ||
| 362 | .lpsc = DA8XX_LPSC1_EMIF3C, | ||
| 363 | .flags = ALWAYS_ENABLED, | ||
| 364 | .psc_ctlr = 1, | ||
| 365 | }; | ||
| 366 | |||
| 367 | static struct clk arm_clk = { | ||
| 368 | .name = "arm", | ||
| 369 | .parent = &pll0_sysclk6, | ||
| 370 | .lpsc = DA8XX_LPSC0_ARM, | ||
| 371 | .flags = ALWAYS_ENABLED, | ||
| 372 | }; | ||
| 373 | |||
| 374 | static struct clk rmii_clk = { | ||
| 375 | .name = "rmii", | ||
| 376 | .parent = &pll0_sysclk7, | ||
| 377 | }; | ||
| 378 | |||
| 379 | static struct davinci_clk da830_clks[] = { | ||
| 380 | CLK(NULL, "ref", &ref_clk), | ||
| 381 | CLK(NULL, "pll0", &pll0_clk), | ||
| 382 | CLK(NULL, "pll0_aux", &pll0_aux_clk), | ||
| 383 | CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), | ||
| 384 | CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), | ||
| 385 | CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), | ||
| 386 | CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), | ||
| 387 | CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), | ||
| 388 | CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), | ||
| 389 | CLK("i2c_davinci.1", NULL, &i2c0_clk), | ||
| 390 | CLK(NULL, "timer0", &timerp64_0_clk), | ||
| 391 | CLK("watchdog", NULL, &timerp64_1_clk), | ||
| 392 | CLK(NULL, "arm_rom", &arm_rom_clk), | ||
| 393 | CLK(NULL, "scr0_ss", &scr0_ss_clk), | ||
| 394 | CLK(NULL, "scr1_ss", &scr1_ss_clk), | ||
| 395 | CLK(NULL, "scr2_ss", &scr2_ss_clk), | ||
| 396 | CLK(NULL, "dmax", &dmax_clk), | ||
| 397 | CLK(NULL, "tpcc", &tpcc_clk), | ||
| 398 | CLK(NULL, "tptc0", &tptc0_clk), | ||
| 399 | CLK(NULL, "tptc1", &tptc1_clk), | ||
| 400 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), | ||
| 401 | CLK(NULL, "uart0", &uart0_clk), | ||
| 402 | CLK(NULL, "uart1", &uart1_clk), | ||
| 403 | CLK(NULL, "uart2", &uart2_clk), | ||
| 404 | CLK("dm_spi.0", NULL, &spi0_clk), | ||
| 405 | CLK("dm_spi.1", NULL, &spi1_clk), | ||
| 406 | CLK(NULL, "ecap0", &ecap0_clk), | ||
| 407 | CLK(NULL, "ecap1", &ecap1_clk), | ||
| 408 | CLK(NULL, "ecap2", &ecap2_clk), | ||
| 409 | CLK(NULL, "pwm0", &pwm0_clk), | ||
| 410 | CLK(NULL, "pwm1", &pwm1_clk), | ||
| 411 | CLK(NULL, "pwm2", &pwm2_clk), | ||
| 412 | CLK("eqep.0", NULL, &eqep0_clk), | ||
| 413 | CLK("eqep.1", NULL, &eqep1_clk), | ||
| 414 | CLK("da830_lcdc", NULL, &lcdc_clk), | ||
| 415 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), | ||
| 416 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), | ||
| 417 | CLK("davinci-mcasp.2", NULL, &mcasp2_clk), | ||
| 418 | CLK("musb_hdrc", NULL, &usb20_clk), | ||
| 419 | CLK(NULL, "aemif", &aemif_clk), | ||
| 420 | CLK(NULL, "aintc", &aintc_clk), | ||
| 421 | CLK(NULL, "secu_mgr", &secu_mgr_clk), | ||
| 422 | CLK("davinci_emac.1", NULL, &emac_clk), | ||
| 423 | CLK(NULL, "gpio", &gpio_clk), | ||
| 424 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | ||
| 425 | CLK(NULL, "usb11", &usb11_clk), | ||
| 426 | CLK(NULL, "emif3", &emif3_clk), | ||
| 427 | CLK(NULL, "arm", &arm_clk), | ||
| 428 | CLK(NULL, "rmii", &rmii_clk), | ||
| 429 | CLK(NULL, NULL, NULL), | ||
| 430 | }; | ||
| 431 | |||
| 432 | /* | ||
| 433 | * Device specific mux setup | ||
| 434 | * | ||
| 435 | * soc description mux mode mode mux dbg | ||
| 436 | * reg offset mask mode | ||
| 437 | */ | ||
| 438 | static const struct mux_config da830_pins[] = { | ||
| 439 | #ifdef CONFIG_DAVINCI_MUX | ||
| 440 | MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) | ||
| 441 | MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) | ||
| 442 | MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) | ||
| 443 | MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) | ||
| 444 | MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) | ||
| 445 | MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) | ||
| 446 | MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) | ||
| 447 | MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) | ||
| 448 | MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) | ||
| 449 | MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) | ||
| 450 | MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) | ||
| 451 | MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) | ||
| 452 | MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) | ||
| 453 | MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) | ||
| 454 | MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) | ||
| 455 | MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) | ||
| 456 | MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) | ||
| 457 | MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) | ||
| 458 | MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) | ||
| 459 | MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) | ||
| 460 | MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) | ||
| 461 | MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) | ||
| 462 | MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) | ||
| 463 | MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) | ||
| 464 | MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) | ||
| 465 | MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) | ||
| 466 | MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) | ||
| 467 | MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) | ||
| 468 | MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) | ||
| 469 | MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) | ||
| 470 | MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) | ||
| 471 | MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) | ||
| 472 | MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) | ||
| 473 | MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) | ||
| 474 | MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) | ||
| 475 | MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) | ||
| 476 | MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) | ||
| 477 | MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) | ||
| 478 | MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) | ||
| 479 | MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) | ||
| 480 | MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) | ||
| 481 | MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) | ||
| 482 | MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) | ||
| 483 | MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) | ||
| 484 | MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) | ||
| 485 | MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) | ||
| 486 | MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) | ||
| 487 | MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) | ||
| 488 | MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) | ||
| 489 | MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) | ||
| 490 | MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) | ||
| 491 | MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) | ||
| 492 | MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) | ||
| 493 | MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) | ||
| 494 | MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) | ||
| 495 | MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) | ||
| 496 | MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) | ||
| 497 | MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) | ||
| 498 | MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) | ||
| 499 | MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) | ||
| 500 | MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) | ||
| 501 | MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) | ||
| 502 | MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) | ||
| 503 | MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) | ||
| 504 | MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) | ||
| 505 | MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) | ||
| 506 | MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) | ||
| 507 | MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) | ||
| 508 | MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) | ||
| 509 | MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) | ||
| 510 | MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) | ||
| 511 | MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) | ||
| 512 | MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) | ||
| 513 | MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) | ||
| 514 | MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) | ||
| 515 | MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) | ||
| 516 | MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) | ||
| 517 | MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) | ||
| 518 | MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) | ||
| 519 | MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) | ||
| 520 | MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) | ||
| 521 | MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) | ||
| 522 | MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) | ||
| 523 | MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) | ||
| 524 | MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) | ||
| 525 | MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) | ||
| 526 | MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) | ||
| 527 | MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) | ||
| 528 | MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) | ||
| 529 | MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) | ||
| 530 | MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) | ||
| 531 | MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) | ||
| 532 | MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) | ||
| 533 | MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) | ||
| 534 | MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) | ||
| 535 | MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) | ||
| 536 | MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) | ||
| 537 | MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) | ||
| 538 | MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) | ||
| 539 | MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) | ||
| 540 | MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) | ||
| 541 | MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) | ||
| 542 | MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) | ||
| 543 | MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) | ||
| 544 | MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) | ||
| 545 | MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) | ||
| 546 | MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) | ||
| 547 | MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) | ||
| 548 | MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) | ||
| 549 | MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) | ||
| 550 | MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) | ||
| 551 | MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) | ||
| 552 | MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) | ||
| 553 | MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) | ||
| 554 | MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) | ||
| 555 | MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) | ||
| 556 | MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) | ||
| 557 | MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) | ||
| 558 | MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) | ||
| 559 | MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) | ||
| 560 | MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) | ||
| 561 | MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) | ||
| 562 | MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) | ||
| 563 | MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) | ||
| 564 | MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) | ||
| 565 | MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) | ||
| 566 | MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) | ||
| 567 | MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) | ||
| 568 | MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) | ||
| 569 | MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) | ||
| 570 | MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) | ||
| 571 | MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) | ||
| 572 | MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) | ||
| 573 | MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) | ||
| 574 | MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) | ||
| 575 | MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) | ||
| 576 | MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) | ||
| 577 | MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) | ||
| 578 | MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) | ||
| 579 | MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) | ||
| 580 | MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) | ||
| 581 | MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) | ||
| 582 | MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) | ||
| 583 | MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) | ||
| 584 | MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) | ||
| 585 | MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) | ||
| 586 | MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) | ||
| 587 | MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) | ||
| 588 | MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) | ||
| 589 | MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) | ||
| 590 | MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) | ||
| 591 | MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) | ||
| 592 | MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) | ||
| 593 | MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) | ||
| 594 | MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) | ||
| 595 | MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) | ||
| 596 | MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) | ||
| 597 | MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) | ||
| 598 | MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) | ||
| 599 | MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) | ||
| 600 | MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) | ||
| 601 | MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) | ||
| 602 | MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) | ||
| 603 | MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) | ||
| 604 | MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) | ||
| 605 | MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) | ||
| 606 | MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) | ||
| 607 | MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) | ||
| 608 | MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) | ||
| 609 | MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) | ||
| 610 | MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) | ||
| 611 | MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) | ||
| 612 | MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) | ||
| 613 | MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) | ||
| 614 | MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) | ||
| 615 | MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) | ||
| 616 | MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) | ||
| 617 | MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) | ||
| 618 | MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) | ||
| 619 | MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) | ||
| 620 | MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) | ||
| 621 | MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) | ||
| 622 | MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) | ||
| 623 | MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) | ||
| 624 | MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) | ||
| 625 | MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) | ||
| 626 | MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) | ||
| 627 | MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) | ||
| 628 | MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) | ||
| 629 | MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) | ||
| 630 | MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) | ||
| 631 | MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) | ||
| 632 | MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) | ||
| 633 | MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) | ||
| 634 | MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) | ||
| 635 | MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) | ||
| 636 | MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) | ||
| 637 | MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) | ||
| 638 | MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) | ||
| 639 | MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) | ||
| 640 | MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) | ||
| 641 | MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) | ||
| 642 | MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) | ||
| 643 | MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) | ||
| 644 | MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) | ||
| 645 | MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) | ||
| 646 | MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) | ||
| 647 | MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) | ||
| 648 | MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) | ||
| 649 | MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) | ||
| 650 | MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) | ||
| 651 | MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) | ||
| 652 | MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) | ||
| 653 | MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) | ||
| 654 | MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) | ||
| 655 | MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) | ||
| 656 | MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) | ||
| 657 | MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) | ||
| 658 | MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) | ||
| 659 | MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) | ||
| 660 | MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) | ||
| 661 | MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) | ||
| 662 | MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) | ||
| 663 | MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) | ||
| 664 | MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) | ||
| 665 | MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) | ||
| 666 | MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) | ||
| 667 | MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) | ||
| 668 | MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) | ||
| 669 | MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) | ||
| 670 | MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) | ||
| 671 | MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) | ||
| 672 | MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) | ||
| 673 | MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) | ||
| 674 | MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) | ||
| 675 | MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) | ||
| 676 | MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) | ||
| 677 | MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) | ||
| 678 | MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) | ||
| 679 | MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) | ||
| 680 | MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) | ||
| 681 | MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) | ||
| 682 | MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) | ||
| 683 | MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) | ||
| 684 | MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) | ||
| 685 | MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) | ||
| 686 | MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) | ||
| 687 | MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) | ||
| 688 | MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) | ||
| 689 | MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) | ||
| 690 | MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) | ||
| 691 | MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) | ||
| 692 | MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) | ||
| 693 | MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) | ||
| 694 | MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) | ||
| 695 | MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) | ||
| 696 | MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) | ||
| 697 | MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) | ||
| 698 | MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) | ||
| 699 | MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) | ||
| 700 | MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) | ||
| 701 | MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) | ||
| 702 | MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) | ||
| 703 | MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) | ||
| 704 | MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) | ||
| 705 | MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) | ||
| 706 | MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) | ||
| 707 | MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) | ||
| 708 | MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) | ||
| 709 | MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) | ||
| 710 | MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) | ||
| 711 | MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) | ||
| 712 | MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) | ||
| 713 | MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) | ||
| 714 | MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) | ||
| 715 | MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) | ||
| 716 | MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) | ||
| 717 | MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) | ||
| 718 | MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) | ||
| 719 | MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) | ||
| 720 | MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) | ||
| 721 | MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) | ||
| 722 | MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) | ||
| 723 | MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) | ||
| 724 | MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) | ||
| 725 | MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) | ||
| 726 | MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) | ||
| 727 | MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) | ||
| 728 | MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) | ||
| 729 | MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) | ||
| 730 | MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) | ||
| 731 | MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) | ||
| 732 | MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) | ||
| 733 | MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) | ||
| 734 | MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) | ||
| 735 | MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) | ||
| 736 | MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) | ||
| 737 | MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) | ||
| 738 | MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) | ||
| 739 | MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) | ||
| 740 | MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) | ||
| 741 | MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) | ||
| 742 | MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) | ||
| 743 | MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) | ||
| 744 | MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) | ||
| 745 | MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) | ||
| 746 | MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) | ||
| 747 | MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) | ||
| 748 | MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) | ||
| 749 | MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) | ||
| 750 | MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) | ||
| 751 | MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) | ||
| 752 | MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) | ||
| 753 | MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) | ||
| 754 | MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) | ||
| 755 | MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) | ||
| 756 | MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) | ||
| 757 | MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) | ||
| 758 | MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) | ||
| 759 | MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) | ||
| 760 | MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) | ||
| 761 | MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) | ||
| 762 | MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) | ||
| 763 | MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) | ||
| 764 | MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) | ||
| 765 | MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) | ||
| 766 | MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) | ||
| 767 | MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) | ||
| 768 | MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) | ||
| 769 | MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) | ||
| 770 | MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) | ||
| 771 | MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) | ||
| 772 | MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) | ||
| 773 | MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) | ||
| 774 | MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) | ||
| 775 | MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) | ||
| 776 | MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) | ||
| 777 | MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) | ||
| 778 | MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) | ||
| 779 | MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) | ||
| 780 | MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) | ||
| 781 | MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) | ||
| 782 | MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) | ||
| 783 | MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) | ||
| 784 | MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) | ||
| 785 | MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) | ||
| 786 | MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) | ||
| 787 | MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) | ||
| 788 | MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) | ||
| 789 | MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) | ||
| 790 | MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) | ||
| 791 | MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) | ||
| 792 | MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) | ||
| 793 | MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) | ||
| 794 | MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) | ||
| 795 | MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) | ||
| 796 | MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) | ||
| 797 | MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) | ||
| 798 | MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) | ||
| 799 | MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) | ||
| 800 | MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) | ||
| 801 | MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) | ||
| 802 | MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) | ||
| 803 | MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) | ||
| 804 | MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) | ||
| 805 | MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) | ||
| 806 | MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) | ||
| 807 | MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) | ||
| 808 | MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) | ||
| 809 | MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) | ||
| 810 | MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) | ||
| 811 | MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) | ||
| 812 | MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) | ||
| 813 | MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) | ||
| 814 | MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) | ||
| 815 | MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) | ||
| 816 | MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) | ||
| 817 | MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) | ||
| 818 | MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) | ||
| 819 | MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) | ||
| 820 | MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) | ||
| 821 | MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) | ||
| 822 | MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) | ||
| 823 | MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) | ||
| 824 | MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) | ||
| 825 | MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) | ||
| 826 | MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) | ||
| 827 | MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) | ||
| 828 | MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) | ||
| 829 | MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) | ||
| 830 | MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) | ||
| 831 | MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) | ||
| 832 | MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) | ||
| 833 | MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) | ||
| 834 | MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) | ||
| 835 | MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) | ||
| 836 | MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) | ||
| 837 | MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) | ||
| 838 | MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) | ||
| 839 | MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) | ||
| 840 | MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) | ||
| 841 | #endif | ||
| 842 | }; | ||
| 843 | |||
| 844 | const short da830_emif25_pins[] __initdata = { | ||
| 845 | DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, | ||
| 846 | DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, | ||
| 847 | DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, | ||
| 848 | DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, | ||
| 849 | DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, | ||
| 850 | DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, | ||
| 851 | DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, | ||
| 852 | DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, | ||
| 853 | DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, | ||
| 854 | DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, | ||
| 855 | DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, | ||
| 856 | -1 | ||
| 857 | }; | ||
| 858 | |||
| 859 | const short da830_spi0_pins[] __initdata = { | ||
| 860 | DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, | ||
| 861 | DA830_NSPI0_SCS_0, | ||
| 862 | -1 | ||
| 863 | }; | ||
| 864 | |||
| 865 | const short da830_spi1_pins[] __initdata = { | ||
| 866 | DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, | ||
| 867 | DA830_NSPI1_SCS_0, | ||
| 868 | -1 | ||
| 869 | }; | ||
| 870 | |||
| 871 | const short da830_mmc_sd_pins[] __initdata = { | ||
| 872 | DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, | ||
| 873 | DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, | ||
| 874 | DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, | ||
| 875 | DA830_MMCSD_CMD, | ||
| 876 | -1 | ||
| 877 | }; | ||
| 878 | |||
| 879 | const short da830_uart0_pins[] __initdata = { | ||
| 880 | DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, | ||
| 881 | -1 | ||
| 882 | }; | ||
| 883 | |||
| 884 | const short da830_uart1_pins[] __initdata = { | ||
| 885 | DA830_UART1_RXD, DA830_UART1_TXD, | ||
| 886 | -1 | ||
| 887 | }; | ||
| 888 | |||
| 889 | const short da830_uart2_pins[] __initdata = { | ||
| 890 | DA830_UART2_RXD, DA830_UART2_TXD, | ||
| 891 | -1 | ||
| 892 | }; | ||
| 893 | |||
| 894 | const short da830_usb20_pins[] __initdata = { | ||
| 895 | DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, | ||
| 896 | -1 | ||
| 897 | }; | ||
| 898 | |||
| 899 | const short da830_usb11_pins[] __initdata = { | ||
| 900 | DA830_USB_REFCLKIN, | ||
| 901 | -1 | ||
| 902 | }; | ||
| 903 | |||
| 904 | const short da830_uhpi_pins[] __initdata = { | ||
| 905 | DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, | ||
| 906 | DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, | ||
| 907 | DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, | ||
| 908 | DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, | ||
| 909 | DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, | ||
| 910 | DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, | ||
| 911 | DA830_NUHPI_HINT, DA830_NUHPI_HRDY, | ||
| 912 | -1 | ||
| 913 | }; | ||
| 914 | |||
| 915 | const short da830_cpgmac_pins[] __initdata = { | ||
| 916 | DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, | ||
| 917 | DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, | ||
| 918 | DA830_MDIO_D, | ||
| 919 | -1 | ||
| 920 | }; | ||
| 921 | |||
| 922 | const short da830_emif3c_pins[] __initdata = { | ||
| 923 | DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, | ||
| 924 | DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, | ||
| 925 | DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, | ||
| 926 | DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, | ||
| 927 | DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, | ||
| 928 | DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, | ||
| 929 | DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, | ||
| 930 | DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, | ||
| 931 | DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, | ||
| 932 | DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, | ||
| 933 | DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, | ||
| 934 | DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, | ||
| 935 | DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, | ||
| 936 | DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, | ||
| 937 | DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, | ||
| 938 | -1 | ||
| 939 | }; | ||
| 940 | |||
| 941 | const short da830_mcasp0_pins[] __initdata = { | ||
| 942 | DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, | ||
| 943 | DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, | ||
| 944 | DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, | ||
| 945 | DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, | ||
| 946 | DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, | ||
| 947 | DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, | ||
| 948 | -1 | ||
| 949 | }; | ||
| 950 | |||
| 951 | const short da830_mcasp1_pins[] __initdata = { | ||
| 952 | DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, | ||
| 953 | DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, | ||
| 954 | DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, | ||
| 955 | DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, | ||
| 956 | DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, | ||
| 957 | -1 | ||
| 958 | }; | ||
| 959 | |||
| 960 | const short da830_mcasp2_pins[] __initdata = { | ||
| 961 | DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, | ||
| 962 | DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, | ||
| 963 | DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, | ||
| 964 | -1 | ||
| 965 | }; | ||
| 966 | |||
| 967 | const short da830_i2c0_pins[] __initdata = { | ||
| 968 | DA830_I2C0_SDA, DA830_I2C0_SCL, | ||
| 969 | -1 | ||
| 970 | }; | ||
| 971 | |||
| 972 | const short da830_i2c1_pins[] __initdata = { | ||
| 973 | DA830_I2C1_SCL, DA830_I2C1_SDA, | ||
| 974 | -1 | ||
| 975 | }; | ||
| 976 | |||
| 977 | const short da830_lcdcntl_pins[] __initdata = { | ||
| 978 | DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, | ||
| 979 | DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, | ||
| 980 | DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, | ||
| 981 | DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, | ||
| 982 | DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, | ||
| 983 | DA830_LCD_MCLK, | ||
| 984 | -1 | ||
| 985 | }; | ||
| 986 | |||
| 987 | const short da830_pwm_pins[] __initdata = { | ||
| 988 | DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, | ||
| 989 | DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, | ||
| 990 | DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, | ||
| 991 | -1 | ||
| 992 | }; | ||
| 993 | |||
| 994 | const short da830_ecap0_pins[] __initdata = { | ||
| 995 | DA830_ECAP0_APWM0, | ||
| 996 | -1 | ||
| 997 | }; | ||
| 998 | |||
| 999 | const short da830_ecap1_pins[] __initdata = { | ||
| 1000 | DA830_ECAP1_APWM1, | ||
| 1001 | -1 | ||
| 1002 | }; | ||
| 1003 | |||
| 1004 | const short da830_ecap2_pins[] __initdata = { | ||
| 1005 | DA830_ECAP2_APWM2, | ||
| 1006 | -1 | ||
| 1007 | }; | ||
| 1008 | |||
| 1009 | const short da830_eqep0_pins[] __initdata = { | ||
| 1010 | DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, | ||
| 1011 | -1 | ||
| 1012 | }; | ||
| 1013 | |||
| 1014 | const short da830_eqep1_pins[] __initdata = { | ||
| 1015 | DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, | ||
| 1016 | -1 | ||
| 1017 | }; | ||
| 1018 | |||
| 1019 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ | ||
| 1020 | static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { | ||
| 1021 | [IRQ_DA8XX_COMMTX] = 7, | ||
| 1022 | [IRQ_DA8XX_COMMRX] = 7, | ||
| 1023 | [IRQ_DA8XX_NINT] = 7, | ||
| 1024 | [IRQ_DA8XX_EVTOUT0] = 7, | ||
| 1025 | [IRQ_DA8XX_EVTOUT1] = 7, | ||
| 1026 | [IRQ_DA8XX_EVTOUT2] = 7, | ||
| 1027 | [IRQ_DA8XX_EVTOUT3] = 7, | ||
| 1028 | [IRQ_DA8XX_EVTOUT4] = 7, | ||
| 1029 | [IRQ_DA8XX_EVTOUT5] = 7, | ||
| 1030 | [IRQ_DA8XX_EVTOUT6] = 7, | ||
| 1031 | [IRQ_DA8XX_EVTOUT6] = 7, | ||
| 1032 | [IRQ_DA8XX_EVTOUT7] = 7, | ||
| 1033 | [IRQ_DA8XX_CCINT0] = 7, | ||
| 1034 | [IRQ_DA8XX_CCERRINT] = 7, | ||
| 1035 | [IRQ_DA8XX_TCERRINT0] = 7, | ||
| 1036 | [IRQ_DA8XX_AEMIFINT] = 7, | ||
| 1037 | [IRQ_DA8XX_I2CINT0] = 7, | ||
| 1038 | [IRQ_DA8XX_MMCSDINT0] = 7, | ||
| 1039 | [IRQ_DA8XX_MMCSDINT1] = 7, | ||
| 1040 | [IRQ_DA8XX_ALLINT0] = 7, | ||
| 1041 | [IRQ_DA8XX_RTC] = 7, | ||
| 1042 | [IRQ_DA8XX_SPINT0] = 7, | ||
| 1043 | [IRQ_DA8XX_TINT12_0] = 7, | ||
| 1044 | [IRQ_DA8XX_TINT34_0] = 7, | ||
| 1045 | [IRQ_DA8XX_TINT12_1] = 7, | ||
| 1046 | [IRQ_DA8XX_TINT34_1] = 7, | ||
| 1047 | [IRQ_DA8XX_UARTINT0] = 7, | ||
| 1048 | [IRQ_DA8XX_KEYMGRINT] = 7, | ||
| 1049 | [IRQ_DA8XX_SECINT] = 7, | ||
| 1050 | [IRQ_DA8XX_SECKEYERR] = 7, | ||
| 1051 | [IRQ_DA830_MPUERR] = 7, | ||
| 1052 | [IRQ_DA830_IOPUERR] = 7, | ||
| 1053 | [IRQ_DA830_BOOTCFGERR] = 7, | ||
| 1054 | [IRQ_DA8XX_CHIPINT0] = 7, | ||
| 1055 | [IRQ_DA8XX_CHIPINT1] = 7, | ||
| 1056 | [IRQ_DA8XX_CHIPINT2] = 7, | ||
| 1057 | [IRQ_DA8XX_CHIPINT3] = 7, | ||
| 1058 | [IRQ_DA8XX_TCERRINT1] = 7, | ||
| 1059 | [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, | ||
| 1060 | [IRQ_DA8XX_C0_RX_PULSE] = 7, | ||
| 1061 | [IRQ_DA8XX_C0_TX_PULSE] = 7, | ||
| 1062 | [IRQ_DA8XX_C0_MISC_PULSE] = 7, | ||
| 1063 | [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, | ||
| 1064 | [IRQ_DA8XX_C1_RX_PULSE] = 7, | ||
| 1065 | [IRQ_DA8XX_C1_TX_PULSE] = 7, | ||
| 1066 | [IRQ_DA8XX_C1_MISC_PULSE] = 7, | ||
| 1067 | [IRQ_DA8XX_MEMERR] = 7, | ||
| 1068 | [IRQ_DA8XX_GPIO0] = 7, | ||
| 1069 | [IRQ_DA8XX_GPIO1] = 7, | ||
| 1070 | [IRQ_DA8XX_GPIO2] = 7, | ||
| 1071 | [IRQ_DA8XX_GPIO3] = 7, | ||
| 1072 | [IRQ_DA8XX_GPIO4] = 7, | ||
| 1073 | [IRQ_DA8XX_GPIO5] = 7, | ||
| 1074 | [IRQ_DA8XX_GPIO6] = 7, | ||
| 1075 | [IRQ_DA8XX_GPIO7] = 7, | ||
| 1076 | [IRQ_DA8XX_GPIO8] = 7, | ||
| 1077 | [IRQ_DA8XX_I2CINT1] = 7, | ||
| 1078 | [IRQ_DA8XX_LCDINT] = 7, | ||
| 1079 | [IRQ_DA8XX_UARTINT1] = 7, | ||
| 1080 | [IRQ_DA8XX_MCASPINT] = 7, | ||
| 1081 | [IRQ_DA8XX_ALLINT1] = 7, | ||
| 1082 | [IRQ_DA8XX_SPINT1] = 7, | ||
| 1083 | [IRQ_DA8XX_UHPI_INT1] = 7, | ||
| 1084 | [IRQ_DA8XX_USB_INT] = 7, | ||
| 1085 | [IRQ_DA8XX_IRQN] = 7, | ||
| 1086 | [IRQ_DA8XX_RWAKEUP] = 7, | ||
| 1087 | [IRQ_DA8XX_UARTINT2] = 7, | ||
| 1088 | [IRQ_DA8XX_DFTSSINT] = 7, | ||
| 1089 | [IRQ_DA8XX_EHRPWM0] = 7, | ||
| 1090 | [IRQ_DA8XX_EHRPWM0TZ] = 7, | ||
| 1091 | [IRQ_DA8XX_EHRPWM1] = 7, | ||
| 1092 | [IRQ_DA8XX_EHRPWM1TZ] = 7, | ||
| 1093 | [IRQ_DA830_EHRPWM2] = 7, | ||
| 1094 | [IRQ_DA830_EHRPWM2TZ] = 7, | ||
| 1095 | [IRQ_DA8XX_ECAP0] = 7, | ||
| 1096 | [IRQ_DA8XX_ECAP1] = 7, | ||
| 1097 | [IRQ_DA8XX_ECAP2] = 7, | ||
| 1098 | [IRQ_DA830_EQEP0] = 7, | ||
| 1099 | [IRQ_DA830_EQEP1] = 7, | ||
| 1100 | [IRQ_DA830_T12CMPINT0_0] = 7, | ||
| 1101 | [IRQ_DA830_T12CMPINT1_0] = 7, | ||
| 1102 | [IRQ_DA830_T12CMPINT2_0] = 7, | ||
| 1103 | [IRQ_DA830_T12CMPINT3_0] = 7, | ||
| 1104 | [IRQ_DA830_T12CMPINT4_0] = 7, | ||
| 1105 | [IRQ_DA830_T12CMPINT5_0] = 7, | ||
| 1106 | [IRQ_DA830_T12CMPINT6_0] = 7, | ||
| 1107 | [IRQ_DA830_T12CMPINT7_0] = 7, | ||
| 1108 | [IRQ_DA830_T12CMPINT0_1] = 7, | ||
| 1109 | [IRQ_DA830_T12CMPINT1_1] = 7, | ||
| 1110 | [IRQ_DA830_T12CMPINT2_1] = 7, | ||
| 1111 | [IRQ_DA830_T12CMPINT3_1] = 7, | ||
| 1112 | [IRQ_DA830_T12CMPINT4_1] = 7, | ||
| 1113 | [IRQ_DA830_T12CMPINT5_1] = 7, | ||
| 1114 | [IRQ_DA830_T12CMPINT6_1] = 7, | ||
| 1115 | [IRQ_DA830_T12CMPINT7_1] = 7, | ||
| 1116 | [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, | ||
| 1117 | }; | ||
| 1118 | |||
| 1119 | static struct map_desc da830_io_desc[] = { | ||
| 1120 | { | ||
| 1121 | .virtual = IO_VIRT, | ||
| 1122 | .pfn = __phys_to_pfn(IO_PHYS), | ||
| 1123 | .length = IO_SIZE, | ||
| 1124 | .type = MT_DEVICE | ||
| 1125 | }, | ||
| 1126 | { | ||
| 1127 | .virtual = DA8XX_CP_INTC_VIRT, | ||
| 1128 | .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), | ||
| 1129 | .length = DA8XX_CP_INTC_SIZE, | ||
| 1130 | .type = MT_DEVICE | ||
| 1131 | }, | ||
| 1132 | }; | ||
| 1133 | |||
| 1134 | static void __iomem *da830_psc_bases[] = { | ||
| 1135 | IO_ADDRESS(DA8XX_PSC0_BASE), | ||
| 1136 | IO_ADDRESS(DA8XX_PSC1_BASE), | ||
| 1137 | }; | ||
| 1138 | |||
| 1139 | /* Contents of JTAG ID register used to identify exact cpu type */ | ||
| 1140 | static struct davinci_id da830_ids[] = { | ||
| 1141 | { | ||
| 1142 | .variant = 0x0, | ||
| 1143 | .part_no = 0xb7df, | ||
| 1144 | .manufacturer = 0x017, /* 0x02f >> 1 */ | ||
| 1145 | .cpu_id = DAVINCI_CPU_ID_DA830, | ||
| 1146 | .name = "da830/omap l137", | ||
| 1147 | }, | ||
| 1148 | }; | ||
| 1149 | |||
| 1150 | static struct davinci_timer_instance da830_timer_instance[2] = { | ||
| 1151 | { | ||
| 1152 | .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), | ||
| 1153 | .bottom_irq = IRQ_DA8XX_TINT12_0, | ||
| 1154 | .top_irq = IRQ_DA8XX_TINT34_0, | ||
| 1155 | .cmp_off = DA830_CMP12_0, | ||
| 1156 | .cmp_irq = IRQ_DA830_T12CMPINT0_0, | ||
| 1157 | }, | ||
| 1158 | { | ||
| 1159 | .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), | ||
| 1160 | .bottom_irq = IRQ_DA8XX_TINT12_1, | ||
| 1161 | .top_irq = IRQ_DA8XX_TINT34_1, | ||
| 1162 | .cmp_off = DA830_CMP12_0, | ||
| 1163 | .cmp_irq = IRQ_DA830_T12CMPINT0_1, | ||
| 1164 | }, | ||
| 1165 | }; | ||
| 1166 | |||
| 1167 | /* | ||
| 1168 | * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource | ||
| 1169 | * T0_TOP: Timer 0, top : Used by DSP | ||
| 1170 | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer | ||
| 1171 | */ | ||
| 1172 | static struct davinci_timer_info da830_timer_info = { | ||
| 1173 | .timers = da830_timer_instance, | ||
| 1174 | .clockevent_id = T0_BOT, | ||
| 1175 | .clocksource_id = T0_BOT, | ||
| 1176 | }; | ||
| 1177 | |||
| 1178 | static struct davinci_soc_info davinci_soc_info_da830 = { | ||
| 1179 | .io_desc = da830_io_desc, | ||
| 1180 | .io_desc_num = ARRAY_SIZE(da830_io_desc), | ||
| 1181 | .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), | ||
| 1182 | .ids = da830_ids, | ||
| 1183 | .ids_num = ARRAY_SIZE(da830_ids), | ||
| 1184 | .cpu_clks = da830_clks, | ||
| 1185 | .psc_bases = da830_psc_bases, | ||
| 1186 | .psc_bases_num = ARRAY_SIZE(da830_psc_bases), | ||
| 1187 | .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), | ||
| 1188 | .pinmux_pins = da830_pins, | ||
| 1189 | .pinmux_pins_num = ARRAY_SIZE(da830_pins), | ||
| 1190 | .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, | ||
| 1191 | .intc_type = DAVINCI_INTC_TYPE_CP_INTC, | ||
| 1192 | .intc_irq_prios = da830_default_priorities, | ||
| 1193 | .intc_irq_num = DA830_N_CP_INTC_IRQ, | ||
| 1194 | .timer_info = &da830_timer_info, | ||
| 1195 | .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), | ||
| 1196 | .gpio_num = 128, | ||
| 1197 | .gpio_irq = IRQ_DA8XX_GPIO0, | ||
| 1198 | .serial_dev = &da8xx_serial_device, | ||
| 1199 | .emac_pdata = &da8xx_emac_pdata, | ||
| 1200 | }; | ||
| 1201 | |||
| 1202 | void __init da830_init(void) | ||
| 1203 | { | ||
| 1204 | davinci_common_init(&davinci_soc_info_da830); | ||
| 1205 | } | ||
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c new file mode 100644 index 000000000000..192d719a47df --- /dev/null +++ b/arch/arm/mach-davinci/da850.c | |||
| @@ -0,0 +1,820 @@ | |||
| 1 | /* | ||
| 2 | * TI DA850/OMAP-L138 chip specific setup | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Derived from: arch/arm/mach-davinci/da830.c | ||
| 7 | * Original Copyrights follow: | ||
| 8 | * | ||
| 9 | * 2009 (c) MontaVista Software, Inc. This file is licensed under | ||
| 10 | * the terms of the GNU General Public License version 2. This program | ||
| 11 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 12 | * or implied. | ||
| 13 | */ | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | |||
| 19 | #include <asm/mach/map.h> | ||
| 20 | |||
| 21 | #include <mach/clock.h> | ||
| 22 | #include <mach/psc.h> | ||
| 23 | #include <mach/mux.h> | ||
| 24 | #include <mach/irqs.h> | ||
| 25 | #include <mach/cputype.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/time.h> | ||
| 28 | #include <mach/da8xx.h> | ||
| 29 | |||
| 30 | #include "clock.h" | ||
| 31 | #include "mux.h" | ||
| 32 | |||
| 33 | #define DA850_PLL1_BASE 0x01e1a000 | ||
| 34 | #define DA850_TIMER64P2_BASE 0x01f0c000 | ||
| 35 | #define DA850_TIMER64P3_BASE 0x01f0d000 | ||
| 36 | |||
| 37 | #define DA850_REF_FREQ 24000000 | ||
| 38 | |||
| 39 | static struct pll_data pll0_data = { | ||
| 40 | .num = 1, | ||
| 41 | .phys_base = DA8XX_PLL0_BASE, | ||
| 42 | .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct clk ref_clk = { | ||
| 46 | .name = "ref_clk", | ||
| 47 | .rate = DA850_REF_FREQ, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct clk pll0_clk = { | ||
| 51 | .name = "pll0", | ||
| 52 | .parent = &ref_clk, | ||
| 53 | .pll_data = &pll0_data, | ||
| 54 | .flags = CLK_PLL, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static struct clk pll0_aux_clk = { | ||
| 58 | .name = "pll0_aux_clk", | ||
| 59 | .parent = &pll0_clk, | ||
| 60 | .flags = CLK_PLL | PRE_PLL, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct clk pll0_sysclk2 = { | ||
| 64 | .name = "pll0_sysclk2", | ||
| 65 | .parent = &pll0_clk, | ||
| 66 | .flags = CLK_PLL, | ||
| 67 | .div_reg = PLLDIV2, | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct clk pll0_sysclk3 = { | ||
| 71 | .name = "pll0_sysclk3", | ||
| 72 | .parent = &pll0_clk, | ||
| 73 | .flags = CLK_PLL, | ||
| 74 | .div_reg = PLLDIV3, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct clk pll0_sysclk4 = { | ||
| 78 | .name = "pll0_sysclk4", | ||
| 79 | .parent = &pll0_clk, | ||
| 80 | .flags = CLK_PLL, | ||
| 81 | .div_reg = PLLDIV4, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct clk pll0_sysclk5 = { | ||
| 85 | .name = "pll0_sysclk5", | ||
| 86 | .parent = &pll0_clk, | ||
| 87 | .flags = CLK_PLL, | ||
| 88 | .div_reg = PLLDIV5, | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct clk pll0_sysclk6 = { | ||
| 92 | .name = "pll0_sysclk6", | ||
| 93 | .parent = &pll0_clk, | ||
| 94 | .flags = CLK_PLL, | ||
| 95 | .div_reg = PLLDIV6, | ||
| 96 | }; | ||
| 97 | |||
| 98 | static struct clk pll0_sysclk7 = { | ||
| 99 | .name = "pll0_sysclk7", | ||
| 100 | .parent = &pll0_clk, | ||
| 101 | .flags = CLK_PLL, | ||
| 102 | .div_reg = PLLDIV7, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct pll_data pll1_data = { | ||
| 106 | .num = 2, | ||
| 107 | .phys_base = DA850_PLL1_BASE, | ||
| 108 | .flags = PLL_HAS_POSTDIV, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct clk pll1_clk = { | ||
| 112 | .name = "pll1", | ||
| 113 | .parent = &ref_clk, | ||
| 114 | .pll_data = &pll1_data, | ||
| 115 | .flags = CLK_PLL, | ||
| 116 | }; | ||
| 117 | |||
| 118 | static struct clk pll1_aux_clk = { | ||
| 119 | .name = "pll1_aux_clk", | ||
| 120 | .parent = &pll1_clk, | ||
| 121 | .flags = CLK_PLL | PRE_PLL, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct clk pll1_sysclk2 = { | ||
| 125 | .name = "pll1_sysclk2", | ||
| 126 | .parent = &pll1_clk, | ||
| 127 | .flags = CLK_PLL, | ||
| 128 | .div_reg = PLLDIV2, | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct clk pll1_sysclk3 = { | ||
| 132 | .name = "pll1_sysclk3", | ||
| 133 | .parent = &pll1_clk, | ||
| 134 | .flags = CLK_PLL, | ||
| 135 | .div_reg = PLLDIV3, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct clk pll1_sysclk4 = { | ||
| 139 | .name = "pll1_sysclk4", | ||
| 140 | .parent = &pll1_clk, | ||
| 141 | .flags = CLK_PLL, | ||
| 142 | .div_reg = PLLDIV4, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct clk pll1_sysclk5 = { | ||
| 146 | .name = "pll1_sysclk5", | ||
| 147 | .parent = &pll1_clk, | ||
| 148 | .flags = CLK_PLL, | ||
| 149 | .div_reg = PLLDIV5, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct clk pll1_sysclk6 = { | ||
| 153 | .name = "pll0_sysclk6", | ||
| 154 | .parent = &pll0_clk, | ||
| 155 | .flags = CLK_PLL, | ||
| 156 | .div_reg = PLLDIV6, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static struct clk pll1_sysclk7 = { | ||
| 160 | .name = "pll1_sysclk7", | ||
| 161 | .parent = &pll1_clk, | ||
| 162 | .flags = CLK_PLL, | ||
| 163 | .div_reg = PLLDIV7, | ||
| 164 | }; | ||
| 165 | |||
| 166 | static struct clk i2c0_clk = { | ||
| 167 | .name = "i2c0", | ||
| 168 | .parent = &pll0_aux_clk, | ||
| 169 | }; | ||
| 170 | |||
| 171 | static struct clk timerp64_0_clk = { | ||
| 172 | .name = "timer0", | ||
| 173 | .parent = &pll0_aux_clk, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct clk timerp64_1_clk = { | ||
| 177 | .name = "timer1", | ||
| 178 | .parent = &pll0_aux_clk, | ||
| 179 | }; | ||
| 180 | |||
| 181 | static struct clk arm_rom_clk = { | ||
| 182 | .name = "arm_rom", | ||
| 183 | .parent = &pll0_sysclk2, | ||
| 184 | .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, | ||
| 185 | .flags = ALWAYS_ENABLED, | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct clk tpcc0_clk = { | ||
| 189 | .name = "tpcc0", | ||
| 190 | .parent = &pll0_sysclk2, | ||
| 191 | .lpsc = DA8XX_LPSC0_TPCC, | ||
| 192 | .flags = ALWAYS_ENABLED | CLK_PSC, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static struct clk tptc0_clk = { | ||
| 196 | .name = "tptc0", | ||
| 197 | .parent = &pll0_sysclk2, | ||
| 198 | .lpsc = DA8XX_LPSC0_TPTC0, | ||
| 199 | .flags = ALWAYS_ENABLED, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct clk tptc1_clk = { | ||
| 203 | .name = "tptc1", | ||
| 204 | .parent = &pll0_sysclk2, | ||
| 205 | .lpsc = DA8XX_LPSC0_TPTC1, | ||
| 206 | .flags = ALWAYS_ENABLED, | ||
| 207 | }; | ||
| 208 | |||
| 209 | static struct clk tpcc1_clk = { | ||
| 210 | .name = "tpcc1", | ||
| 211 | .parent = &pll0_sysclk2, | ||
| 212 | .lpsc = DA850_LPSC1_TPCC1, | ||
| 213 | .flags = CLK_PSC | ALWAYS_ENABLED, | ||
| 214 | .psc_ctlr = 1, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct clk tptc2_clk = { | ||
| 218 | .name = "tptc2", | ||
| 219 | .parent = &pll0_sysclk2, | ||
| 220 | .lpsc = DA850_LPSC1_TPTC2, | ||
| 221 | .flags = ALWAYS_ENABLED, | ||
| 222 | .psc_ctlr = 1, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct clk uart0_clk = { | ||
| 226 | .name = "uart0", | ||
| 227 | .parent = &pll0_sysclk2, | ||
| 228 | .lpsc = DA8XX_LPSC0_UART0, | ||
| 229 | }; | ||
| 230 | |||
| 231 | static struct clk uart1_clk = { | ||
| 232 | .name = "uart1", | ||
| 233 | .parent = &pll0_sysclk2, | ||
| 234 | .lpsc = DA8XX_LPSC1_UART1, | ||
| 235 | .psc_ctlr = 1, | ||
| 236 | }; | ||
| 237 | |||
| 238 | static struct clk uart2_clk = { | ||
| 239 | .name = "uart2", | ||
| 240 | .parent = &pll0_sysclk2, | ||
| 241 | .lpsc = DA8XX_LPSC1_UART2, | ||
| 242 | .psc_ctlr = 1, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static struct clk aintc_clk = { | ||
| 246 | .name = "aintc", | ||
| 247 | .parent = &pll0_sysclk4, | ||
| 248 | .lpsc = DA8XX_LPSC0_AINTC, | ||
| 249 | .flags = ALWAYS_ENABLED, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static struct clk gpio_clk = { | ||
| 253 | .name = "gpio", | ||
| 254 | .parent = &pll0_sysclk4, | ||
| 255 | .lpsc = DA8XX_LPSC1_GPIO, | ||
| 256 | .psc_ctlr = 1, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static struct clk i2c1_clk = { | ||
| 260 | .name = "i2c1", | ||
| 261 | .parent = &pll0_sysclk4, | ||
| 262 | .lpsc = DA8XX_LPSC1_I2C, | ||
| 263 | .psc_ctlr = 1, | ||
| 264 | }; | ||
| 265 | |||
| 266 | static struct clk emif3_clk = { | ||
| 267 | .name = "emif3", | ||
| 268 | .parent = &pll0_sysclk5, | ||
| 269 | .lpsc = DA8XX_LPSC1_EMIF3C, | ||
| 270 | .flags = ALWAYS_ENABLED, | ||
| 271 | .psc_ctlr = 1, | ||
| 272 | }; | ||
| 273 | |||
| 274 | static struct clk arm_clk = { | ||
| 275 | .name = "arm", | ||
| 276 | .parent = &pll0_sysclk6, | ||
| 277 | .lpsc = DA8XX_LPSC0_ARM, | ||
| 278 | .flags = ALWAYS_ENABLED, | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct clk rmii_clk = { | ||
| 282 | .name = "rmii", | ||
| 283 | .parent = &pll0_sysclk7, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct clk emac_clk = { | ||
| 287 | .name = "emac", | ||
| 288 | .parent = &pll0_sysclk4, | ||
| 289 | .lpsc = DA8XX_LPSC1_CPGMAC, | ||
| 290 | .psc_ctlr = 1, | ||
| 291 | }; | ||
| 292 | |||
| 293 | static struct clk mcasp_clk = { | ||
| 294 | .name = "mcasp", | ||
| 295 | .parent = &pll0_sysclk2, | ||
| 296 | .lpsc = DA8XX_LPSC1_McASP0, | ||
| 297 | .psc_ctlr = 1, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct clk lcdc_clk = { | ||
| 301 | .name = "lcdc", | ||
| 302 | .parent = &pll0_sysclk2, | ||
| 303 | .lpsc = DA8XX_LPSC1_LCDC, | ||
| 304 | .psc_ctlr = 1, | ||
| 305 | }; | ||
| 306 | |||
| 307 | static struct clk mmcsd_clk = { | ||
| 308 | .name = "mmcsd", | ||
| 309 | .parent = &pll0_sysclk2, | ||
| 310 | .lpsc = DA8XX_LPSC0_MMC_SD, | ||
| 311 | }; | ||
| 312 | |||
| 313 | static struct clk aemif_clk = { | ||
| 314 | .name = "aemif", | ||
| 315 | .parent = &pll0_sysclk3, | ||
| 316 | .lpsc = DA8XX_LPSC0_EMIF25, | ||
| 317 | .flags = ALWAYS_ENABLED, | ||
| 318 | }; | ||
| 319 | |||
| 320 | static struct davinci_clk da850_clks[] = { | ||
| 321 | CLK(NULL, "ref", &ref_clk), | ||
| 322 | CLK(NULL, "pll0", &pll0_clk), | ||
| 323 | CLK(NULL, "pll0_aux", &pll0_aux_clk), | ||
| 324 | CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), | ||
| 325 | CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), | ||
| 326 | CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), | ||
| 327 | CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), | ||
| 328 | CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), | ||
| 329 | CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), | ||
| 330 | CLK(NULL, "pll1", &pll1_clk), | ||
| 331 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | ||
| 332 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | ||
| 333 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | ||
| 334 | CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), | ||
| 335 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | ||
| 336 | CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), | ||
| 337 | CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), | ||
| 338 | CLK("i2c_davinci.1", NULL, &i2c0_clk), | ||
| 339 | CLK(NULL, "timer0", &timerp64_0_clk), | ||
| 340 | CLK("watchdog", NULL, &timerp64_1_clk), | ||
| 341 | CLK(NULL, "arm_rom", &arm_rom_clk), | ||
| 342 | CLK(NULL, "tpcc0", &tpcc0_clk), | ||
| 343 | CLK(NULL, "tptc0", &tptc0_clk), | ||
| 344 | CLK(NULL, "tptc1", &tptc1_clk), | ||
| 345 | CLK(NULL, "tpcc1", &tpcc1_clk), | ||
| 346 | CLK(NULL, "tptc2", &tptc2_clk), | ||
| 347 | CLK(NULL, "uart0", &uart0_clk), | ||
| 348 | CLK(NULL, "uart1", &uart1_clk), | ||
| 349 | CLK(NULL, "uart2", &uart2_clk), | ||
| 350 | CLK(NULL, "aintc", &aintc_clk), | ||
| 351 | CLK(NULL, "gpio", &gpio_clk), | ||
| 352 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | ||
| 353 | CLK(NULL, "emif3", &emif3_clk), | ||
| 354 | CLK(NULL, "arm", &arm_clk), | ||
| 355 | CLK(NULL, "rmii", &rmii_clk), | ||
| 356 | CLK("davinci_emac.1", NULL, &emac_clk), | ||
| 357 | CLK("davinci-mcasp.0", NULL, &mcasp_clk), | ||
| 358 | CLK("da8xx_lcdc.0", NULL, &lcdc_clk), | ||
| 359 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), | ||
| 360 | CLK(NULL, "aemif", &aemif_clk), | ||
| 361 | CLK(NULL, NULL, NULL), | ||
| 362 | }; | ||
| 363 | |||
| 364 | /* | ||
| 365 | * Device specific mux setup | ||
| 366 | * | ||
| 367 | * soc description mux mode mode mux dbg | ||
| 368 | * reg offset mask mode | ||
| 369 | */ | ||
| 370 | static const struct mux_config da850_pins[] = { | ||
| 371 | #ifdef CONFIG_DAVINCI_MUX | ||
| 372 | /* UART0 function */ | ||
| 373 | MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) | ||
| 374 | MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) | ||
| 375 | MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) | ||
| 376 | MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) | ||
| 377 | /* UART1 function */ | ||
| 378 | MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) | ||
| 379 | MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) | ||
| 380 | /* UART2 function */ | ||
| 381 | MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) | ||
| 382 | MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) | ||
| 383 | /* I2C1 function */ | ||
| 384 | MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) | ||
| 385 | MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) | ||
| 386 | /* I2C0 function */ | ||
| 387 | MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) | ||
| 388 | MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) | ||
| 389 | /* EMAC function */ | ||
| 390 | MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) | ||
| 391 | MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) | ||
| 392 | MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) | ||
| 393 | MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) | ||
| 394 | MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) | ||
| 395 | MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) | ||
| 396 | MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) | ||
| 397 | MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) | ||
| 398 | MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) | ||
| 399 | MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) | ||
| 400 | MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) | ||
| 401 | MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) | ||
| 402 | MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) | ||
| 403 | MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) | ||
| 404 | MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) | ||
| 405 | MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) | ||
| 406 | MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) | ||
| 407 | /* McASP function */ | ||
| 408 | MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) | ||
| 409 | MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) | ||
| 410 | MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) | ||
| 411 | MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) | ||
| 412 | MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) | ||
| 413 | MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) | ||
| 414 | MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) | ||
| 415 | MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) | ||
| 416 | MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) | ||
| 417 | MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) | ||
| 418 | MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) | ||
| 419 | MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) | ||
| 420 | MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) | ||
| 421 | MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) | ||
| 422 | MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) | ||
| 423 | MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) | ||
| 424 | MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) | ||
| 425 | MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) | ||
| 426 | MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) | ||
| 427 | MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) | ||
| 428 | MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) | ||
| 429 | MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) | ||
| 430 | MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) | ||
| 431 | /* LCD function */ | ||
| 432 | MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) | ||
| 433 | MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) | ||
| 434 | MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) | ||
| 435 | MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) | ||
| 436 | MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) | ||
| 437 | MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) | ||
| 438 | MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) | ||
| 439 | MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) | ||
| 440 | MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) | ||
| 441 | MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) | ||
| 442 | MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) | ||
| 443 | MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) | ||
| 444 | MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) | ||
| 445 | MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) | ||
| 446 | MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) | ||
| 447 | MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) | ||
| 448 | MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) | ||
| 449 | MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) | ||
| 450 | MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) | ||
| 451 | MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) | ||
| 452 | /* MMC/SD0 function */ | ||
| 453 | MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) | ||
| 454 | MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) | ||
| 455 | MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) | ||
| 456 | MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) | ||
| 457 | MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) | ||
| 458 | MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) | ||
| 459 | /* EMIF2.5/EMIFA function */ | ||
| 460 | MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) | ||
| 461 | MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) | ||
| 462 | MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) | ||
| 463 | MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) | ||
| 464 | MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) | ||
| 465 | MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) | ||
| 466 | MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) | ||
| 467 | MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) | ||
| 468 | MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) | ||
| 469 | MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) | ||
| 470 | MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) | ||
| 471 | MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) | ||
| 472 | MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) | ||
| 473 | MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) | ||
| 474 | MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) | ||
| 475 | MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) | ||
| 476 | MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) | ||
| 477 | MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) | ||
| 478 | MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) | ||
| 479 | MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) | ||
| 480 | MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) | ||
| 481 | MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) | ||
| 482 | MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) | ||
| 483 | MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) | ||
| 484 | MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) | ||
| 485 | MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) | ||
| 486 | MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) | ||
| 487 | MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) | ||
| 488 | MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) | ||
| 489 | MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) | ||
| 490 | MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) | ||
| 491 | MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) | ||
| 492 | MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) | ||
| 493 | MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) | ||
| 494 | MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) | ||
| 495 | MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) | ||
| 496 | MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) | ||
| 497 | MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) | ||
| 498 | MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) | ||
| 499 | MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) | ||
| 500 | MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) | ||
| 501 | MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) | ||
| 502 | MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) | ||
| 503 | MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) | ||
| 504 | MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) | ||
| 505 | MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) | ||
| 506 | MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) | ||
| 507 | MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) | ||
| 508 | /* GPIO function */ | ||
| 509 | MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) | ||
| 510 | MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false) | ||
| 511 | MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) | ||
| 512 | MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) | ||
| 513 | #endif | ||
| 514 | }; | ||
| 515 | |||
| 516 | const short da850_uart0_pins[] __initdata = { | ||
| 517 | DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD, | ||
| 518 | -1 | ||
| 519 | }; | ||
| 520 | |||
| 521 | const short da850_uart1_pins[] __initdata = { | ||
| 522 | DA850_UART1_RXD, DA850_UART1_TXD, | ||
| 523 | -1 | ||
| 524 | }; | ||
| 525 | |||
| 526 | const short da850_uart2_pins[] __initdata = { | ||
| 527 | DA850_UART2_RXD, DA850_UART2_TXD, | ||
| 528 | -1 | ||
| 529 | }; | ||
| 530 | |||
| 531 | const short da850_i2c0_pins[] __initdata = { | ||
| 532 | DA850_I2C0_SDA, DA850_I2C0_SCL, | ||
| 533 | -1 | ||
| 534 | }; | ||
| 535 | |||
| 536 | const short da850_i2c1_pins[] __initdata = { | ||
| 537 | DA850_I2C1_SCL, DA850_I2C1_SDA, | ||
| 538 | -1 | ||
| 539 | }; | ||
| 540 | |||
| 541 | const short da850_cpgmac_pins[] __initdata = { | ||
| 542 | DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, | ||
| 543 | DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, | ||
| 544 | DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, | ||
| 545 | DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, | ||
| 546 | DA850_MDIO_D, | ||
| 547 | -1 | ||
| 548 | }; | ||
| 549 | |||
| 550 | const short da850_mcasp_pins[] __initdata = { | ||
| 551 | DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, | ||
| 552 | DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, | ||
| 553 | DA850_AXR_11, DA850_AXR_12, | ||
| 554 | -1 | ||
| 555 | }; | ||
| 556 | |||
| 557 | const short da850_lcdcntl_pins[] __initdata = { | ||
| 558 | DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4, | ||
| 559 | DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8, | ||
| 560 | DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12, | ||
| 561 | DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK, | ||
| 562 | DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15, | ||
| 563 | DA850_GPIO8_10, | ||
| 564 | -1 | ||
| 565 | }; | ||
| 566 | |||
| 567 | const short da850_mmcsd0_pins[] __initdata = { | ||
| 568 | DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, | ||
| 569 | DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, | ||
| 570 | DA850_GPIO4_0, DA850_GPIO4_1, | ||
| 571 | -1 | ||
| 572 | }; | ||
| 573 | |||
| 574 | const short da850_nand_pins[] __initdata = { | ||
| 575 | DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4, | ||
| 576 | DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0, | ||
| 577 | DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, | ||
| 578 | DA850_NEMA_WE, DA850_NEMA_OE, | ||
| 579 | -1 | ||
| 580 | }; | ||
| 581 | |||
| 582 | const short da850_nor_pins[] __initdata = { | ||
| 583 | DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, | ||
| 584 | DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, | ||
| 585 | DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, | ||
| 586 | DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, | ||
| 587 | DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, | ||
| 588 | DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, | ||
| 589 | DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, | ||
| 590 | DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, | ||
| 591 | DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, | ||
| 592 | DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, | ||
| 593 | DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, | ||
| 594 | DA850_EMA_A_22, DA850_EMA_A_23, | ||
| 595 | -1 | ||
| 596 | }; | ||
| 597 | |||
| 598 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ | ||
| 599 | static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { | ||
| 600 | [IRQ_DA8XX_COMMTX] = 7, | ||
| 601 | [IRQ_DA8XX_COMMRX] = 7, | ||
| 602 | [IRQ_DA8XX_NINT] = 7, | ||
| 603 | [IRQ_DA8XX_EVTOUT0] = 7, | ||
| 604 | [IRQ_DA8XX_EVTOUT1] = 7, | ||
| 605 | [IRQ_DA8XX_EVTOUT2] = 7, | ||
| 606 | [IRQ_DA8XX_EVTOUT3] = 7, | ||
| 607 | [IRQ_DA8XX_EVTOUT4] = 7, | ||
| 608 | [IRQ_DA8XX_EVTOUT5] = 7, | ||
| 609 | [IRQ_DA8XX_EVTOUT6] = 7, | ||
| 610 | [IRQ_DA8XX_EVTOUT6] = 7, | ||
| 611 | [IRQ_DA8XX_EVTOUT7] = 7, | ||
| 612 | [IRQ_DA8XX_CCINT0] = 7, | ||
| 613 | [IRQ_DA8XX_CCERRINT] = 7, | ||
| 614 | [IRQ_DA8XX_TCERRINT0] = 7, | ||
| 615 | [IRQ_DA8XX_AEMIFINT] = 7, | ||
| 616 | [IRQ_DA8XX_I2CINT0] = 7, | ||
| 617 | [IRQ_DA8XX_MMCSDINT0] = 7, | ||
| 618 | [IRQ_DA8XX_MMCSDINT1] = 7, | ||
| 619 | [IRQ_DA8XX_ALLINT0] = 7, | ||
| 620 | [IRQ_DA8XX_RTC] = 7, | ||
| 621 | [IRQ_DA8XX_SPINT0] = 7, | ||
| 622 | [IRQ_DA8XX_TINT12_0] = 7, | ||
| 623 | [IRQ_DA8XX_TINT34_0] = 7, | ||
| 624 | [IRQ_DA8XX_TINT12_1] = 7, | ||
| 625 | [IRQ_DA8XX_TINT34_1] = 7, | ||
| 626 | [IRQ_DA8XX_UARTINT0] = 7, | ||
| 627 | [IRQ_DA8XX_KEYMGRINT] = 7, | ||
| 628 | [IRQ_DA8XX_SECINT] = 7, | ||
| 629 | [IRQ_DA8XX_SECKEYERR] = 7, | ||
| 630 | [IRQ_DA850_MPUADDRERR0] = 7, | ||
| 631 | [IRQ_DA850_MPUPROTERR0] = 7, | ||
| 632 | [IRQ_DA850_IOPUADDRERR0] = 7, | ||
| 633 | [IRQ_DA850_IOPUPROTERR0] = 7, | ||
| 634 | [IRQ_DA850_IOPUADDRERR1] = 7, | ||
| 635 | [IRQ_DA850_IOPUPROTERR1] = 7, | ||
| 636 | [IRQ_DA850_IOPUADDRERR2] = 7, | ||
| 637 | [IRQ_DA850_IOPUPROTERR2] = 7, | ||
| 638 | [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7, | ||
| 639 | [IRQ_DA850_BOOTCFG_PROT_ERR] = 7, | ||
| 640 | [IRQ_DA850_MPUADDRERR1] = 7, | ||
| 641 | [IRQ_DA850_MPUPROTERR1] = 7, | ||
| 642 | [IRQ_DA850_IOPUADDRERR3] = 7, | ||
| 643 | [IRQ_DA850_IOPUPROTERR3] = 7, | ||
| 644 | [IRQ_DA850_IOPUADDRERR4] = 7, | ||
| 645 | [IRQ_DA850_IOPUPROTERR4] = 7, | ||
| 646 | [IRQ_DA850_IOPUADDRERR5] = 7, | ||
| 647 | [IRQ_DA850_IOPUPROTERR5] = 7, | ||
| 648 | [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7, | ||
| 649 | [IRQ_DA8XX_CHIPINT0] = 7, | ||
| 650 | [IRQ_DA8XX_CHIPINT1] = 7, | ||
| 651 | [IRQ_DA8XX_CHIPINT2] = 7, | ||
| 652 | [IRQ_DA8XX_CHIPINT3] = 7, | ||
| 653 | [IRQ_DA8XX_TCERRINT1] = 7, | ||
| 654 | [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, | ||
| 655 | [IRQ_DA8XX_C0_RX_PULSE] = 7, | ||
| 656 | [IRQ_DA8XX_C0_TX_PULSE] = 7, | ||
| 657 | [IRQ_DA8XX_C0_MISC_PULSE] = 7, | ||
| 658 | [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, | ||
| 659 | [IRQ_DA8XX_C1_RX_PULSE] = 7, | ||
| 660 | [IRQ_DA8XX_C1_TX_PULSE] = 7, | ||
| 661 | [IRQ_DA8XX_C1_MISC_PULSE] = 7, | ||
| 662 | [IRQ_DA8XX_MEMERR] = 7, | ||
| 663 | [IRQ_DA8XX_GPIO0] = 7, | ||
| 664 | [IRQ_DA8XX_GPIO1] = 7, | ||
| 665 | [IRQ_DA8XX_GPIO2] = 7, | ||
| 666 | [IRQ_DA8XX_GPIO3] = 7, | ||
| 667 | [IRQ_DA8XX_GPIO4] = 7, | ||
| 668 | [IRQ_DA8XX_GPIO5] = 7, | ||
| 669 | [IRQ_DA8XX_GPIO6] = 7, | ||
| 670 | [IRQ_DA8XX_GPIO7] = 7, | ||
| 671 | [IRQ_DA8XX_GPIO8] = 7, | ||
| 672 | [IRQ_DA8XX_I2CINT1] = 7, | ||
| 673 | [IRQ_DA8XX_LCDINT] = 7, | ||
| 674 | [IRQ_DA8XX_UARTINT1] = 7, | ||
| 675 | [IRQ_DA8XX_MCASPINT] = 7, | ||
| 676 | [IRQ_DA8XX_ALLINT1] = 7, | ||
| 677 | [IRQ_DA8XX_SPINT1] = 7, | ||
| 678 | [IRQ_DA8XX_UHPI_INT1] = 7, | ||
| 679 | [IRQ_DA8XX_USB_INT] = 7, | ||
| 680 | [IRQ_DA8XX_IRQN] = 7, | ||
| 681 | [IRQ_DA8XX_RWAKEUP] = 7, | ||
| 682 | [IRQ_DA8XX_UARTINT2] = 7, | ||
| 683 | [IRQ_DA8XX_DFTSSINT] = 7, | ||
| 684 | [IRQ_DA8XX_EHRPWM0] = 7, | ||
| 685 | [IRQ_DA8XX_EHRPWM0TZ] = 7, | ||
| 686 | [IRQ_DA8XX_EHRPWM1] = 7, | ||
| 687 | [IRQ_DA8XX_EHRPWM1TZ] = 7, | ||
| 688 | [IRQ_DA850_SATAINT] = 7, | ||
| 689 | [IRQ_DA850_TINT12_2] = 7, | ||
| 690 | [IRQ_DA850_TINT34_2] = 7, | ||
| 691 | [IRQ_DA850_TINTALL_2] = 7, | ||
| 692 | [IRQ_DA8XX_ECAP0] = 7, | ||
| 693 | [IRQ_DA8XX_ECAP1] = 7, | ||
| 694 | [IRQ_DA8XX_ECAP2] = 7, | ||
| 695 | [IRQ_DA850_MMCSDINT0_1] = 7, | ||
| 696 | [IRQ_DA850_MMCSDINT1_1] = 7, | ||
| 697 | [IRQ_DA850_T12CMPINT0_2] = 7, | ||
| 698 | [IRQ_DA850_T12CMPINT1_2] = 7, | ||
| 699 | [IRQ_DA850_T12CMPINT2_2] = 7, | ||
| 700 | [IRQ_DA850_T12CMPINT3_2] = 7, | ||
| 701 | [IRQ_DA850_T12CMPINT4_2] = 7, | ||
| 702 | [IRQ_DA850_T12CMPINT5_2] = 7, | ||
| 703 | [IRQ_DA850_T12CMPINT6_2] = 7, | ||
| 704 | [IRQ_DA850_T12CMPINT7_2] = 7, | ||
| 705 | [IRQ_DA850_T12CMPINT0_3] = 7, | ||
| 706 | [IRQ_DA850_T12CMPINT1_3] = 7, | ||
| 707 | [IRQ_DA850_T12CMPINT2_3] = 7, | ||
| 708 | [IRQ_DA850_T12CMPINT3_3] = 7, | ||
| 709 | [IRQ_DA850_T12CMPINT4_3] = 7, | ||
| 710 | [IRQ_DA850_T12CMPINT5_3] = 7, | ||
| 711 | [IRQ_DA850_T12CMPINT6_3] = 7, | ||
| 712 | [IRQ_DA850_T12CMPINT7_3] = 7, | ||
| 713 | [IRQ_DA850_RPIINT] = 7, | ||
| 714 | [IRQ_DA850_VPIFINT] = 7, | ||
| 715 | [IRQ_DA850_CCINT1] = 7, | ||
| 716 | [IRQ_DA850_CCERRINT1] = 7, | ||
| 717 | [IRQ_DA850_TCERRINT2] = 7, | ||
| 718 | [IRQ_DA850_TINT12_3] = 7, | ||
| 719 | [IRQ_DA850_TINT34_3] = 7, | ||
| 720 | [IRQ_DA850_TINTALL_3] = 7, | ||
| 721 | [IRQ_DA850_MCBSP0RINT] = 7, | ||
| 722 | [IRQ_DA850_MCBSP0XINT] = 7, | ||
| 723 | [IRQ_DA850_MCBSP1RINT] = 7, | ||
| 724 | [IRQ_DA850_MCBSP1XINT] = 7, | ||
| 725 | [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, | ||
| 726 | }; | ||
| 727 | |||
| 728 | static struct map_desc da850_io_desc[] = { | ||
| 729 | { | ||
| 730 | .virtual = IO_VIRT, | ||
| 731 | .pfn = __phys_to_pfn(IO_PHYS), | ||
| 732 | .length = IO_SIZE, | ||
| 733 | .type = MT_DEVICE | ||
| 734 | }, | ||
| 735 | { | ||
| 736 | .virtual = DA8XX_CP_INTC_VIRT, | ||
| 737 | .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), | ||
| 738 | .length = DA8XX_CP_INTC_SIZE, | ||
| 739 | .type = MT_DEVICE | ||
| 740 | }, | ||
| 741 | }; | ||
| 742 | |||
| 743 | static void __iomem *da850_psc_bases[] = { | ||
| 744 | IO_ADDRESS(DA8XX_PSC0_BASE), | ||
| 745 | IO_ADDRESS(DA8XX_PSC1_BASE), | ||
| 746 | }; | ||
| 747 | |||
| 748 | /* Contents of JTAG ID register used to identify exact cpu type */ | ||
| 749 | static struct davinci_id da850_ids[] = { | ||
| 750 | { | ||
| 751 | .variant = 0x0, | ||
| 752 | .part_no = 0xb7d1, | ||
| 753 | .manufacturer = 0x017, /* 0x02f >> 1 */ | ||
| 754 | .cpu_id = DAVINCI_CPU_ID_DA850, | ||
| 755 | .name = "da850/omap-l138", | ||
| 756 | }, | ||
| 757 | }; | ||
| 758 | |||
| 759 | static struct davinci_timer_instance da850_timer_instance[4] = { | ||
| 760 | { | ||
| 761 | .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), | ||
| 762 | .bottom_irq = IRQ_DA8XX_TINT12_0, | ||
| 763 | .top_irq = IRQ_DA8XX_TINT34_0, | ||
| 764 | }, | ||
| 765 | { | ||
| 766 | .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), | ||
| 767 | .bottom_irq = IRQ_DA8XX_TINT12_1, | ||
| 768 | .top_irq = IRQ_DA8XX_TINT34_1, | ||
| 769 | }, | ||
| 770 | { | ||
| 771 | .base = IO_ADDRESS(DA850_TIMER64P2_BASE), | ||
| 772 | .bottom_irq = IRQ_DA850_TINT12_2, | ||
| 773 | .top_irq = IRQ_DA850_TINT34_2, | ||
| 774 | }, | ||
| 775 | { | ||
| 776 | .base = IO_ADDRESS(DA850_TIMER64P3_BASE), | ||
| 777 | .bottom_irq = IRQ_DA850_TINT12_3, | ||
| 778 | .top_irq = IRQ_DA850_TINT34_3, | ||
| 779 | }, | ||
| 780 | }; | ||
| 781 | |||
| 782 | /* | ||
| 783 | * T0_BOT: Timer 0, bottom : Used for clock_event | ||
| 784 | * T0_TOP: Timer 0, top : Used for clocksource | ||
| 785 | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer | ||
| 786 | */ | ||
| 787 | static struct davinci_timer_info da850_timer_info = { | ||
| 788 | .timers = da850_timer_instance, | ||
| 789 | .clockevent_id = T0_BOT, | ||
| 790 | .clocksource_id = T0_TOP, | ||
| 791 | }; | ||
| 792 | |||
| 793 | static struct davinci_soc_info davinci_soc_info_da850 = { | ||
| 794 | .io_desc = da850_io_desc, | ||
| 795 | .io_desc_num = ARRAY_SIZE(da850_io_desc), | ||
| 796 | .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), | ||
| 797 | .ids = da850_ids, | ||
| 798 | .ids_num = ARRAY_SIZE(da850_ids), | ||
| 799 | .cpu_clks = da850_clks, | ||
| 800 | .psc_bases = da850_psc_bases, | ||
| 801 | .psc_bases_num = ARRAY_SIZE(da850_psc_bases), | ||
| 802 | .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), | ||
| 803 | .pinmux_pins = da850_pins, | ||
| 804 | .pinmux_pins_num = ARRAY_SIZE(da850_pins), | ||
| 805 | .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, | ||
| 806 | .intc_type = DAVINCI_INTC_TYPE_CP_INTC, | ||
| 807 | .intc_irq_prios = da850_default_priorities, | ||
| 808 | .intc_irq_num = DA850_N_CP_INTC_IRQ, | ||
| 809 | .timer_info = &da850_timer_info, | ||
| 810 | .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), | ||
| 811 | .gpio_num = 144, | ||
| 812 | .gpio_irq = IRQ_DA8XX_GPIO0, | ||
| 813 | .serial_dev = &da8xx_serial_device, | ||
| 814 | .emac_pdata = &da8xx_emac_pdata, | ||
| 815 | }; | ||
| 816 | |||
| 817 | void __init da850_init(void) | ||
| 818 | { | ||
| 819 | davinci_common_init(&davinci_soc_info_da850); | ||
| 820 | } | ||
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c new file mode 100644 index 000000000000..58ad5b66fd60 --- /dev/null +++ b/arch/arm/mach-davinci/devices-da8xx.c | |||
| @@ -0,0 +1,450 @@ | |||
| 1 | /* | ||
| 2 | * DA8XX/OMAP L1XX platform device data | ||
| 3 | * | ||
| 4 | * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * Derived from code that was: | ||
| 6 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | */ | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/dma-mapping.h> | ||
| 18 | #include <linux/serial_8250.h> | ||
| 19 | |||
| 20 | #include <mach/cputype.h> | ||
| 21 | #include <mach/common.h> | ||
| 22 | #include <mach/time.h> | ||
| 23 | #include <mach/da8xx.h> | ||
| 24 | #include <video/da8xx-fb.h> | ||
| 25 | |||
| 26 | #include "clock.h" | ||
| 27 | |||
| 28 | #define DA8XX_TPCC_BASE 0x01c00000 | ||
| 29 | #define DA8XX_TPTC0_BASE 0x01c08000 | ||
| 30 | #define DA8XX_TPTC1_BASE 0x01c08400 | ||
| 31 | #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ | ||
| 32 | #define DA8XX_I2C0_BASE 0x01c22000 | ||
| 33 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 | ||
| 34 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 | ||
| 35 | #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 | ||
| 36 | #define DA8XX_EMAC_MDIO_BASE 0x01e24000 | ||
| 37 | #define DA8XX_GPIO_BASE 0x01e26000 | ||
| 38 | #define DA8XX_I2C1_BASE 0x01e28000 | ||
| 39 | |||
| 40 | #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 | ||
| 41 | #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 | ||
| 42 | #define DA8XX_EMAC_RAM_OFFSET 0x0000 | ||
| 43 | #define DA8XX_MDIO_REG_OFFSET 0x4000 | ||
| 44 | #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K | ||
| 45 | |||
| 46 | static struct plat_serial8250_port da8xx_serial_pdata[] = { | ||
| 47 | { | ||
| 48 | .mapbase = DA8XX_UART0_BASE, | ||
| 49 | .irq = IRQ_DA8XX_UARTINT0, | ||
| 50 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | ||
| 51 | UPF_IOREMAP, | ||
| 52 | .iotype = UPIO_MEM, | ||
| 53 | .regshift = 2, | ||
| 54 | }, | ||
| 55 | { | ||
| 56 | .mapbase = DA8XX_UART1_BASE, | ||
| 57 | .irq = IRQ_DA8XX_UARTINT1, | ||
| 58 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | ||
| 59 | UPF_IOREMAP, | ||
| 60 | .iotype = UPIO_MEM, | ||
| 61 | .regshift = 2, | ||
| 62 | }, | ||
| 63 | { | ||
| 64 | .mapbase = DA8XX_UART2_BASE, | ||
| 65 | .irq = IRQ_DA8XX_UARTINT2, | ||
| 66 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | ||
| 67 | UPF_IOREMAP, | ||
| 68 | .iotype = UPIO_MEM, | ||
| 69 | .regshift = 2, | ||
| 70 | }, | ||
| 71 | { | ||
| 72 | .flags = 0, | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | struct platform_device da8xx_serial_device = { | ||
| 77 | .name = "serial8250", | ||
| 78 | .id = PLAT8250_DEV_PLATFORM, | ||
| 79 | .dev = { | ||
| 80 | .platform_data = da8xx_serial_pdata, | ||
| 81 | }, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static const s8 da8xx_dma_chan_no_event[] = { | ||
| 85 | 20, 21, | ||
| 86 | -1 | ||
| 87 | }; | ||
| 88 | |||
| 89 | static const s8 da8xx_queue_tc_mapping[][2] = { | ||
| 90 | /* {event queue no, TC no} */ | ||
| 91 | {0, 0}, | ||
| 92 | {1, 1}, | ||
| 93 | {-1, -1} | ||
| 94 | }; | ||
| 95 | |||
| 96 | static const s8 da8xx_queue_priority_mapping[][2] = { | ||
| 97 | /* {event queue no, Priority} */ | ||
| 98 | {0, 3}, | ||
| 99 | {1, 7}, | ||
| 100 | {-1, -1} | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct edma_soc_info da8xx_edma_info[] = { | ||
| 104 | { | ||
| 105 | .n_channel = 32, | ||
| 106 | .n_region = 4, | ||
| 107 | .n_slot = 128, | ||
| 108 | .n_tc = 2, | ||
| 109 | .n_cc = 1, | ||
| 110 | .noevent = da8xx_dma_chan_no_event, | ||
| 111 | .queue_tc_mapping = da8xx_queue_tc_mapping, | ||
| 112 | .queue_priority_mapping = da8xx_queue_priority_mapping, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct resource da8xx_edma_resources[] = { | ||
| 117 | { | ||
| 118 | .name = "edma_cc0", | ||
| 119 | .start = DA8XX_TPCC_BASE, | ||
| 120 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | ||
| 121 | .flags = IORESOURCE_MEM, | ||
| 122 | }, | ||
| 123 | { | ||
| 124 | .name = "edma_tc0", | ||
| 125 | .start = DA8XX_TPTC0_BASE, | ||
| 126 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | ||
| 127 | .flags = IORESOURCE_MEM, | ||
| 128 | }, | ||
| 129 | { | ||
| 130 | .name = "edma_tc1", | ||
| 131 | .start = DA8XX_TPTC1_BASE, | ||
| 132 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | ||
| 133 | .flags = IORESOURCE_MEM, | ||
| 134 | }, | ||
| 135 | { | ||
| 136 | .name = "edma0", | ||
| 137 | .start = IRQ_DA8XX_CCINT0, | ||
| 138 | .flags = IORESOURCE_IRQ, | ||
| 139 | }, | ||
| 140 | { | ||
| 141 | .name = "edma0_err", | ||
| 142 | .start = IRQ_DA8XX_CCERRINT, | ||
| 143 | .flags = IORESOURCE_IRQ, | ||
| 144 | }, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct platform_device da8xx_edma_device = { | ||
| 148 | .name = "edma", | ||
| 149 | .id = -1, | ||
| 150 | .dev = { | ||
| 151 | .platform_data = da8xx_edma_info, | ||
| 152 | }, | ||
| 153 | .num_resources = ARRAY_SIZE(da8xx_edma_resources), | ||
| 154 | .resource = da8xx_edma_resources, | ||
| 155 | }; | ||
| 156 | |||
| 157 | int __init da8xx_register_edma(void) | ||
| 158 | { | ||
| 159 | return platform_device_register(&da8xx_edma_device); | ||
| 160 | } | ||
| 161 | |||
| 162 | static struct resource da8xx_i2c_resources0[] = { | ||
| 163 | { | ||
| 164 | .start = DA8XX_I2C0_BASE, | ||
| 165 | .end = DA8XX_I2C0_BASE + SZ_4K - 1, | ||
| 166 | .flags = IORESOURCE_MEM, | ||
| 167 | }, | ||
| 168 | { | ||
| 169 | .start = IRQ_DA8XX_I2CINT0, | ||
| 170 | .end = IRQ_DA8XX_I2CINT0, | ||
| 171 | .flags = IORESOURCE_IRQ, | ||
| 172 | }, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static struct platform_device da8xx_i2c_device0 = { | ||
| 176 | .name = "i2c_davinci", | ||
| 177 | .id = 1, | ||
| 178 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), | ||
| 179 | .resource = da8xx_i2c_resources0, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct resource da8xx_i2c_resources1[] = { | ||
| 183 | { | ||
| 184 | .start = DA8XX_I2C1_BASE, | ||
| 185 | .end = DA8XX_I2C1_BASE + SZ_4K - 1, | ||
| 186 | .flags = IORESOURCE_MEM, | ||
| 187 | }, | ||
| 188 | { | ||
| 189 | .start = IRQ_DA8XX_I2CINT1, | ||
| 190 | .end = IRQ_DA8XX_I2CINT1, | ||
| 191 | .flags = IORESOURCE_IRQ, | ||
| 192 | }, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static struct platform_device da8xx_i2c_device1 = { | ||
| 196 | .name = "i2c_davinci", | ||
| 197 | .id = 2, | ||
| 198 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), | ||
| 199 | .resource = da8xx_i2c_resources1, | ||
| 200 | }; | ||
| 201 | |||
| 202 | int __init da8xx_register_i2c(int instance, | ||
| 203 | struct davinci_i2c_platform_data *pdata) | ||
| 204 | { | ||
| 205 | struct platform_device *pdev; | ||
| 206 | |||
| 207 | if (instance == 0) | ||
| 208 | pdev = &da8xx_i2c_device0; | ||
| 209 | else if (instance == 1) | ||
| 210 | pdev = &da8xx_i2c_device1; | ||
| 211 | else | ||
| 212 | return -EINVAL; | ||
| 213 | |||
| 214 | pdev->dev.platform_data = pdata; | ||
| 215 | return platform_device_register(pdev); | ||
| 216 | } | ||
| 217 | |||
| 218 | static struct resource da8xx_watchdog_resources[] = { | ||
| 219 | { | ||
| 220 | .start = DA8XX_WDOG_BASE, | ||
| 221 | .end = DA8XX_WDOG_BASE + SZ_4K - 1, | ||
| 222 | .flags = IORESOURCE_MEM, | ||
| 223 | }, | ||
| 224 | }; | ||
| 225 | |||
| 226 | struct platform_device davinci_wdt_device = { | ||
| 227 | .name = "watchdog", | ||
| 228 | .id = -1, | ||
| 229 | .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), | ||
| 230 | .resource = da8xx_watchdog_resources, | ||
| 231 | }; | ||
| 232 | |||
| 233 | int __init da8xx_register_watchdog(void) | ||
| 234 | { | ||
| 235 | return platform_device_register(&davinci_wdt_device); | ||
| 236 | } | ||
| 237 | |||
| 238 | static struct resource da8xx_emac_resources[] = { | ||
| 239 | { | ||
| 240 | .start = DA8XX_EMAC_CPPI_PORT_BASE, | ||
| 241 | .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, | ||
| 242 | .flags = IORESOURCE_MEM, | ||
| 243 | }, | ||
| 244 | { | ||
| 245 | .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, | ||
| 246 | .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, | ||
| 247 | .flags = IORESOURCE_IRQ, | ||
| 248 | }, | ||
| 249 | { | ||
| 250 | .start = IRQ_DA8XX_C0_RX_PULSE, | ||
| 251 | .end = IRQ_DA8XX_C0_RX_PULSE, | ||
| 252 | .flags = IORESOURCE_IRQ, | ||
| 253 | }, | ||
| 254 | { | ||
| 255 | .start = IRQ_DA8XX_C0_TX_PULSE, | ||
| 256 | .end = IRQ_DA8XX_C0_TX_PULSE, | ||
| 257 | .flags = IORESOURCE_IRQ, | ||
| 258 | }, | ||
| 259 | { | ||
| 260 | .start = IRQ_DA8XX_C0_MISC_PULSE, | ||
| 261 | .end = IRQ_DA8XX_C0_MISC_PULSE, | ||
| 262 | .flags = IORESOURCE_IRQ, | ||
| 263 | }, | ||
| 264 | }; | ||
| 265 | |||
| 266 | struct emac_platform_data da8xx_emac_pdata = { | ||
| 267 | .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, | ||
| 268 | .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, | ||
| 269 | .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, | ||
| 270 | .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, | ||
| 271 | .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, | ||
| 272 | .version = EMAC_VERSION_2, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct platform_device da8xx_emac_device = { | ||
| 276 | .name = "davinci_emac", | ||
| 277 | .id = 1, | ||
| 278 | .dev = { | ||
| 279 | .platform_data = &da8xx_emac_pdata, | ||
| 280 | }, | ||
| 281 | .num_resources = ARRAY_SIZE(da8xx_emac_resources), | ||
| 282 | .resource = da8xx_emac_resources, | ||
| 283 | }; | ||
| 284 | |||
| 285 | static struct resource da830_mcasp1_resources[] = { | ||
| 286 | { | ||
| 287 | .name = "mcasp1", | ||
| 288 | .start = DAVINCI_DA830_MCASP1_REG_BASE, | ||
| 289 | .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, | ||
| 290 | .flags = IORESOURCE_MEM, | ||
| 291 | }, | ||
| 292 | /* TX event */ | ||
| 293 | { | ||
| 294 | .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, | ||
| 295 | .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, | ||
| 296 | .flags = IORESOURCE_DMA, | ||
| 297 | }, | ||
| 298 | /* RX event */ | ||
| 299 | { | ||
| 300 | .start = DAVINCI_DA830_DMA_MCASP1_AREVT, | ||
| 301 | .end = DAVINCI_DA830_DMA_MCASP1_AREVT, | ||
| 302 | .flags = IORESOURCE_DMA, | ||
| 303 | }, | ||
| 304 | }; | ||
| 305 | |||
| 306 | static struct platform_device da830_mcasp1_device = { | ||
| 307 | .name = "davinci-mcasp", | ||
| 308 | .id = 1, | ||
| 309 | .num_resources = ARRAY_SIZE(da830_mcasp1_resources), | ||
| 310 | .resource = da830_mcasp1_resources, | ||
| 311 | }; | ||
| 312 | |||
| 313 | static struct resource da850_mcasp_resources[] = { | ||
| 314 | { | ||
| 315 | .name = "mcasp", | ||
| 316 | .start = DAVINCI_DA8XX_MCASP0_REG_BASE, | ||
| 317 | .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, | ||
| 318 | .flags = IORESOURCE_MEM, | ||
| 319 | }, | ||
| 320 | /* TX event */ | ||
| 321 | { | ||
| 322 | .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | ||
| 323 | .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | ||
| 324 | .flags = IORESOURCE_DMA, | ||
| 325 | }, | ||
| 326 | /* RX event */ | ||
| 327 | { | ||
| 328 | .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | ||
| 329 | .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | ||
| 330 | .flags = IORESOURCE_DMA, | ||
| 331 | }, | ||
| 332 | }; | ||
| 333 | |||
| 334 | static struct platform_device da850_mcasp_device = { | ||
| 335 | .name = "davinci-mcasp", | ||
| 336 | .id = 0, | ||
| 337 | .num_resources = ARRAY_SIZE(da850_mcasp_resources), | ||
| 338 | .resource = da850_mcasp_resources, | ||
| 339 | }; | ||
| 340 | |||
| 341 | int __init da8xx_register_emac(void) | ||
| 342 | { | ||
| 343 | return platform_device_register(&da8xx_emac_device); | ||
| 344 | } | ||
| 345 | |||
| 346 | void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata) | ||
| 347 | { | ||
| 348 | /* DA830/OMAP-L137 has 3 instances of McASP */ | ||
| 349 | if (cpu_is_davinci_da830() && id == 1) { | ||
| 350 | da830_mcasp1_device.dev.platform_data = pdata; | ||
| 351 | platform_device_register(&da830_mcasp1_device); | ||
| 352 | } else if (cpu_is_davinci_da850()) { | ||
| 353 | da850_mcasp_device.dev.platform_data = pdata; | ||
| 354 | platform_device_register(&da850_mcasp_device); | ||
| 355 | } | ||
| 356 | } | ||
| 357 | |||
| 358 | static const struct display_panel disp_panel = { | ||
| 359 | QVGA, | ||
| 360 | 16, | ||
| 361 | 16, | ||
| 362 | COLOR_ACTIVE, | ||
| 363 | }; | ||
| 364 | |||
| 365 | static struct lcd_ctrl_config lcd_cfg = { | ||
| 366 | &disp_panel, | ||
| 367 | .ac_bias = 255, | ||
| 368 | .ac_bias_intrpt = 0, | ||
| 369 | .dma_burst_sz = 16, | ||
| 370 | .bpp = 16, | ||
| 371 | .fdd = 255, | ||
| 372 | .tft_alt_mode = 0, | ||
| 373 | .stn_565_mode = 0, | ||
| 374 | .mono_8bit_mode = 0, | ||
| 375 | .invert_line_clock = 1, | ||
| 376 | .invert_frm_clock = 1, | ||
| 377 | .sync_edge = 0, | ||
| 378 | .sync_ctrl = 1, | ||
| 379 | .raster_order = 0, | ||
| 380 | }; | ||
| 381 | |||
| 382 | static struct da8xx_lcdc_platform_data da850_evm_lcdc_pdata = { | ||
| 383 | .manu_name = "sharp", | ||
| 384 | .controller_data = &lcd_cfg, | ||
| 385 | .type = "Sharp_LK043T1DG01", | ||
| 386 | }; | ||
| 387 | |||
| 388 | static struct resource da8xx_lcdc_resources[] = { | ||
| 389 | [0] = { /* registers */ | ||
| 390 | .start = DA8XX_LCD_CNTRL_BASE, | ||
| 391 | .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, | ||
| 392 | .flags = IORESOURCE_MEM, | ||
| 393 | }, | ||
| 394 | [1] = { /* interrupt */ | ||
| 395 | .start = IRQ_DA8XX_LCDINT, | ||
| 396 | .end = IRQ_DA8XX_LCDINT, | ||
| 397 | .flags = IORESOURCE_IRQ, | ||
| 398 | }, | ||
| 399 | }; | ||
| 400 | |||
| 401 | static struct platform_device da850_lcdc_device = { | ||
| 402 | .name = "da8xx_lcdc", | ||
| 403 | .id = 0, | ||
| 404 | .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), | ||
| 405 | .resource = da8xx_lcdc_resources, | ||
| 406 | .dev = { | ||
| 407 | .platform_data = &da850_evm_lcdc_pdata, | ||
| 408 | } | ||
| 409 | }; | ||
| 410 | |||
| 411 | int __init da8xx_register_lcdc(void) | ||
| 412 | { | ||
| 413 | return platform_device_register(&da850_lcdc_device); | ||
| 414 | } | ||
| 415 | |||
| 416 | static struct resource da8xx_mmcsd0_resources[] = { | ||
| 417 | { /* registers */ | ||
| 418 | .start = DA8XX_MMCSD0_BASE, | ||
| 419 | .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, | ||
| 420 | .flags = IORESOURCE_MEM, | ||
| 421 | }, | ||
| 422 | { /* interrupt */ | ||
| 423 | .start = IRQ_DA8XX_MMCSDINT0, | ||
| 424 | .end = IRQ_DA8XX_MMCSDINT0, | ||
| 425 | .flags = IORESOURCE_IRQ, | ||
| 426 | }, | ||
| 427 | { /* DMA RX */ | ||
| 428 | .start = EDMA_CTLR_CHAN(0, 16), | ||
| 429 | .end = EDMA_CTLR_CHAN(0, 16), | ||
| 430 | .flags = IORESOURCE_DMA, | ||
| 431 | }, | ||
| 432 | { /* DMA TX */ | ||
| 433 | .start = EDMA_CTLR_CHAN(0, 17), | ||
| 434 | .end = EDMA_CTLR_CHAN(0, 17), | ||
| 435 | .flags = IORESOURCE_DMA, | ||
| 436 | }, | ||
| 437 | }; | ||
| 438 | |||
| 439 | static struct platform_device da8xx_mmcsd0_device = { | ||
| 440 | .name = "davinci_mmc", | ||
| 441 | .id = 0, | ||
| 442 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), | ||
| 443 | .resource = da8xx_mmcsd0_resources, | ||
| 444 | }; | ||
| 445 | |||
| 446 | int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) | ||
| 447 | { | ||
| 448 | da8xx_mmcsd0_device.dev.platform_data = config; | ||
| 449 | return platform_device_register(&da8xx_mmcsd0_device); | ||
| 450 | } | ||
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index de16f347566a..a55b650db71e 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c | |||
| @@ -31,6 +31,8 @@ | |||
| 31 | #define DAVINCI_MMCSD0_BASE 0x01E10000 | 31 | #define DAVINCI_MMCSD0_BASE 0x01E10000 |
| 32 | #define DM355_MMCSD0_BASE 0x01E11000 | 32 | #define DM355_MMCSD0_BASE 0x01E11000 |
| 33 | #define DM355_MMCSD1_BASE 0x01E00000 | 33 | #define DM355_MMCSD1_BASE 0x01E00000 |
| 34 | #define DM365_MMCSD0_BASE 0x01D11000 | ||
| 35 | #define DM365_MMCSD1_BASE 0x01D00000 | ||
| 34 | 36 | ||
| 35 | static struct resource i2c_resources[] = { | 37 | static struct resource i2c_resources[] = { |
| 36 | { | 38 | { |
| @@ -82,10 +84,10 @@ static struct resource mmcsd0_resources[] = { | |||
| 82 | }, | 84 | }, |
| 83 | /* DMA channels: RX, then TX */ | 85 | /* DMA channels: RX, then TX */ |
| 84 | { | 86 | { |
| 85 | .start = DAVINCI_DMA_MMCRXEVT, | 87 | .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT), |
| 86 | .flags = IORESOURCE_DMA, | 88 | .flags = IORESOURCE_DMA, |
| 87 | }, { | 89 | }, { |
| 88 | .start = DAVINCI_DMA_MMCTXEVT, | 90 | .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT), |
| 89 | .flags = IORESOURCE_DMA, | 91 | .flags = IORESOURCE_DMA, |
| 90 | }, | 92 | }, |
| 91 | }; | 93 | }; |
| @@ -119,10 +121,10 @@ static struct resource mmcsd1_resources[] = { | |||
| 119 | }, | 121 | }, |
| 120 | /* DMA channels: RX, then TX */ | 122 | /* DMA channels: RX, then TX */ |
| 121 | { | 123 | { |
| 122 | .start = 30, /* rx */ | 124 | .start = EDMA_CTLR_CHAN(0, 30), /* rx */ |
| 123 | .flags = IORESOURCE_DMA, | 125 | .flags = IORESOURCE_DMA, |
| 124 | }, { | 126 | }, { |
| 125 | .start = 31, /* tx */ | 127 | .start = EDMA_CTLR_CHAN(0, 31), /* tx */ |
| 126 | .flags = IORESOURCE_DMA, | 128 | .flags = IORESOURCE_DMA, |
| 127 | }, | 129 | }, |
| 128 | }; | 130 | }; |
| @@ -154,19 +156,31 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |||
| 154 | */ | 156 | */ |
| 155 | switch (module) { | 157 | switch (module) { |
| 156 | case 1: | 158 | case 1: |
| 157 | if (!cpu_is_davinci_dm355()) | 159 | if (cpu_is_davinci_dm355()) { |
| 160 | /* REVISIT we may not need all these pins if e.g. this | ||
| 161 | * is a hard-wired SDIO device... | ||
| 162 | */ | ||
| 163 | davinci_cfg_reg(DM355_SD1_CMD); | ||
| 164 | davinci_cfg_reg(DM355_SD1_CLK); | ||
| 165 | davinci_cfg_reg(DM355_SD1_DATA0); | ||
| 166 | davinci_cfg_reg(DM355_SD1_DATA1); | ||
| 167 | davinci_cfg_reg(DM355_SD1_DATA2); | ||
| 168 | davinci_cfg_reg(DM355_SD1_DATA3); | ||
| 169 | } else if (cpu_is_davinci_dm365()) { | ||
| 170 | void __iomem *pupdctl1 = | ||
| 171 | IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); | ||
| 172 | |||
| 173 | /* Configure pull down control */ | ||
| 174 | __raw_writel((__raw_readl(pupdctl1) & ~0x400), | ||
| 175 | pupdctl1); | ||
| 176 | |||
| 177 | mmcsd1_resources[0].start = DM365_MMCSD1_BASE; | ||
| 178 | mmcsd1_resources[0].end = DM365_MMCSD1_BASE + | ||
| 179 | SZ_4K - 1; | ||
| 180 | mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1; | ||
| 181 | } else | ||
| 158 | break; | 182 | break; |
| 159 | 183 | ||
| 160 | /* REVISIT we may not need all these pins if e.g. this | ||
| 161 | * is a hard-wired SDIO device... | ||
| 162 | */ | ||
| 163 | davinci_cfg_reg(DM355_SD1_CMD); | ||
| 164 | davinci_cfg_reg(DM355_SD1_CLK); | ||
| 165 | davinci_cfg_reg(DM355_SD1_DATA0); | ||
| 166 | davinci_cfg_reg(DM355_SD1_DATA1); | ||
| 167 | davinci_cfg_reg(DM355_SD1_DATA2); | ||
| 168 | davinci_cfg_reg(DM355_SD1_DATA3); | ||
| 169 | |||
| 170 | pdev = &davinci_mmcsd1_device; | 184 | pdev = &davinci_mmcsd1_device; |
| 171 | break; | 185 | break; |
| 172 | case 0: | 186 | case 0: |
| @@ -180,9 +194,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |||
| 180 | 194 | ||
| 181 | /* enable RX EDMA */ | 195 | /* enable RX EDMA */ |
| 182 | davinci_cfg_reg(DM355_EVT26_MMC0_RX); | 196 | davinci_cfg_reg(DM355_EVT26_MMC0_RX); |
| 183 | } | 197 | } else if (cpu_is_davinci_dm365()) { |
| 184 | 198 | mmcsd0_resources[0].start = DM365_MMCSD0_BASE; | |
| 185 | else if (cpu_is_davinci_dm644x()) { | 199 | mmcsd0_resources[0].end = DM365_MMCSD0_BASE + |
| 200 | SZ_4K - 1; | ||
| 201 | mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; | ||
| 202 | } else if (cpu_is_davinci_dm644x()) { | ||
| 186 | /* REVISIT: should this be in board-init code? */ | 203 | /* REVISIT: should this be in board-init code? */ |
| 187 | void __iomem *base = | 204 | void __iomem *base = |
| 188 | IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); | 205 | IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); |
| @@ -216,6 +233,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |||
| 216 | 233 | ||
| 217 | static struct resource wdt_resources[] = { | 234 | static struct resource wdt_resources[] = { |
| 218 | { | 235 | { |
| 236 | .start = DAVINCI_WDOG_BASE, | ||
| 237 | .end = DAVINCI_WDOG_BASE + SZ_1K - 1, | ||
| 219 | .flags = IORESOURCE_MEM, | 238 | .flags = IORESOURCE_MEM, |
| 220 | }, | 239 | }, |
| 221 | }; | 240 | }; |
| @@ -229,11 +248,6 @@ struct platform_device davinci_wdt_device = { | |||
| 229 | 248 | ||
| 230 | static void davinci_init_wdt(void) | 249 | static void davinci_init_wdt(void) |
| 231 | { | 250 | { |
| 232 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 233 | |||
| 234 | wdt_resources[0].start = (resource_size_t)soc_info->wdt_base; | ||
| 235 | wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1; | ||
| 236 | |||
| 237 | platform_device_register(&davinci_wdt_device); | 251 | platform_device_register(&davinci_wdt_device); |
| 238 | } | 252 | } |
| 239 | 253 | ||
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index baaaf328de2e..059670018aff 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <mach/time.h> | 30 | #include <mach/time.h> |
| 31 | #include <mach/serial.h> | 31 | #include <mach/serial.h> |
| 32 | #include <mach/common.h> | 32 | #include <mach/common.h> |
| 33 | #include <mach/asp.h> | ||
| 33 | 34 | ||
| 34 | #include "clock.h" | 35 | #include "clock.h" |
| 35 | #include "mux.h" | 36 | #include "mux.h" |
| @@ -360,8 +361,8 @@ static struct davinci_clk dm355_clks[] = { | |||
| 360 | CLK(NULL, "uart1", &uart1_clk), | 361 | CLK(NULL, "uart1", &uart1_clk), |
| 361 | CLK(NULL, "uart2", &uart2_clk), | 362 | CLK(NULL, "uart2", &uart2_clk), |
| 362 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 363 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 363 | CLK("soc-audio.0", NULL, &asp0_clk), | 364 | CLK("davinci-asp.0", NULL, &asp0_clk), |
| 364 | CLK("soc-audio.1", NULL, &asp1_clk), | 365 | CLK("davinci-asp.1", NULL, &asp1_clk), |
| 365 | CLK("davinci_mmc.0", NULL, &mmcsd0_clk), | 366 | CLK("davinci_mmc.0", NULL, &mmcsd0_clk), |
| 366 | CLK("davinci_mmc.1", NULL, &mmcsd1_clk), | 367 | CLK("davinci_mmc.1", NULL, &mmcsd1_clk), |
| 367 | CLK(NULL, "spi0", &spi0_clk), | 368 | CLK(NULL, "spi0", &spi0_clk), |
| @@ -481,6 +482,20 @@ INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) | |||
| 481 | EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) | 482 | EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) |
| 482 | EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) | 483 | EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) |
| 483 | EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) | 484 | EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) |
| 485 | |||
| 486 | MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) | ||
| 487 | MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) | ||
| 488 | MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) | ||
| 489 | MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) | ||
| 490 | MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) | ||
| 491 | |||
| 492 | MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) | ||
| 493 | MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) | ||
| 494 | MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) | ||
| 495 | MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) | ||
| 496 | MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) | ||
| 497 | MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false) | ||
| 498 | MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false) | ||
| 484 | #endif | 499 | #endif |
| 485 | }; | 500 | }; |
| 486 | 501 | ||
| @@ -558,17 +573,38 @@ static const s8 dma_chan_dm355_no_event[] = { | |||
| 558 | -1 | 573 | -1 |
| 559 | }; | 574 | }; |
| 560 | 575 | ||
| 561 | static struct edma_soc_info dm355_edma_info = { | 576 | static const s8 |
| 562 | .n_channel = 64, | 577 | queue_tc_mapping[][2] = { |
| 563 | .n_region = 4, | 578 | /* {event queue no, TC no} */ |
| 564 | .n_slot = 128, | 579 | {0, 0}, |
| 565 | .n_tc = 2, | 580 | {1, 1}, |
| 566 | .noevent = dma_chan_dm355_no_event, | 581 | {-1, -1}, |
| 582 | }; | ||
| 583 | |||
| 584 | static const s8 | ||
| 585 | queue_priority_mapping[][2] = { | ||
| 586 | /* {event queue no, Priority} */ | ||
| 587 | {0, 3}, | ||
| 588 | {1, 7}, | ||
| 589 | {-1, -1}, | ||
| 590 | }; | ||
| 591 | |||
| 592 | static struct edma_soc_info dm355_edma_info[] = { | ||
| 593 | { | ||
| 594 | .n_channel = 64, | ||
| 595 | .n_region = 4, | ||
| 596 | .n_slot = 128, | ||
| 597 | .n_tc = 2, | ||
| 598 | .n_cc = 1, | ||
| 599 | .noevent = dma_chan_dm355_no_event, | ||
| 600 | .queue_tc_mapping = queue_tc_mapping, | ||
| 601 | .queue_priority_mapping = queue_priority_mapping, | ||
| 602 | }, | ||
| 567 | }; | 603 | }; |
| 568 | 604 | ||
| 569 | static struct resource edma_resources[] = { | 605 | static struct resource edma_resources[] = { |
| 570 | { | 606 | { |
| 571 | .name = "edma_cc", | 607 | .name = "edma_cc0", |
| 572 | .start = 0x01c00000, | 608 | .start = 0x01c00000, |
| 573 | .end = 0x01c00000 + SZ_64K - 1, | 609 | .end = 0x01c00000 + SZ_64K - 1, |
| 574 | .flags = IORESOURCE_MEM, | 610 | .flags = IORESOURCE_MEM, |
| @@ -586,10 +622,12 @@ static struct resource edma_resources[] = { | |||
| 586 | .flags = IORESOURCE_MEM, | 622 | .flags = IORESOURCE_MEM, |
| 587 | }, | 623 | }, |
| 588 | { | 624 | { |
| 625 | .name = "edma0", | ||
| 589 | .start = IRQ_CCINT0, | 626 | .start = IRQ_CCINT0, |
| 590 | .flags = IORESOURCE_IRQ, | 627 | .flags = IORESOURCE_IRQ, |
| 591 | }, | 628 | }, |
| 592 | { | 629 | { |
| 630 | .name = "edma0_err", | ||
| 593 | .start = IRQ_CCERRINT, | 631 | .start = IRQ_CCERRINT, |
| 594 | .flags = IORESOURCE_IRQ, | 632 | .flags = IORESOURCE_IRQ, |
| 595 | }, | 633 | }, |
| @@ -598,12 +636,98 @@ static struct resource edma_resources[] = { | |||
| 598 | 636 | ||
| 599 | static struct platform_device dm355_edma_device = { | 637 | static struct platform_device dm355_edma_device = { |
| 600 | .name = "edma", | 638 | .name = "edma", |
| 601 | .id = -1, | 639 | .id = 0, |
| 602 | .dev.platform_data = &dm355_edma_info, | 640 | .dev.platform_data = dm355_edma_info, |
| 603 | .num_resources = ARRAY_SIZE(edma_resources), | 641 | .num_resources = ARRAY_SIZE(edma_resources), |
| 604 | .resource = edma_resources, | 642 | .resource = edma_resources, |
| 605 | }; | 643 | }; |
| 606 | 644 | ||
| 645 | static struct resource dm355_asp1_resources[] = { | ||
| 646 | { | ||
| 647 | .start = DAVINCI_ASP1_BASE, | ||
| 648 | .end = DAVINCI_ASP1_BASE + SZ_8K - 1, | ||
| 649 | .flags = IORESOURCE_MEM, | ||
| 650 | }, | ||
| 651 | { | ||
| 652 | .start = DAVINCI_DMA_ASP1_TX, | ||
| 653 | .end = DAVINCI_DMA_ASP1_TX, | ||
| 654 | .flags = IORESOURCE_DMA, | ||
| 655 | }, | ||
| 656 | { | ||
| 657 | .start = DAVINCI_DMA_ASP1_RX, | ||
| 658 | .end = DAVINCI_DMA_ASP1_RX, | ||
| 659 | .flags = IORESOURCE_DMA, | ||
| 660 | }, | ||
| 661 | }; | ||
| 662 | |||
| 663 | static struct platform_device dm355_asp1_device = { | ||
| 664 | .name = "davinci-asp", | ||
| 665 | .id = 1, | ||
| 666 | .num_resources = ARRAY_SIZE(dm355_asp1_resources), | ||
| 667 | .resource = dm355_asp1_resources, | ||
| 668 | }; | ||
| 669 | |||
| 670 | static struct resource dm355_vpss_resources[] = { | ||
| 671 | { | ||
| 672 | /* VPSS BL Base address */ | ||
| 673 | .name = "vpss", | ||
| 674 | .start = 0x01c70800, | ||
| 675 | .end = 0x01c70800 + 0xff, | ||
| 676 | .flags = IORESOURCE_MEM, | ||
| 677 | }, | ||
| 678 | { | ||
| 679 | /* VPSS CLK Base address */ | ||
| 680 | .name = "vpss", | ||
| 681 | .start = 0x01c70000, | ||
| 682 | .end = 0x01c70000 + 0xf, | ||
| 683 | .flags = IORESOURCE_MEM, | ||
| 684 | }, | ||
| 685 | }; | ||
| 686 | |||
| 687 | static struct platform_device dm355_vpss_device = { | ||
| 688 | .name = "vpss", | ||
| 689 | .id = -1, | ||
| 690 | .dev.platform_data = "dm355_vpss", | ||
| 691 | .num_resources = ARRAY_SIZE(dm355_vpss_resources), | ||
| 692 | .resource = dm355_vpss_resources, | ||
| 693 | }; | ||
| 694 | |||
| 695 | static struct resource vpfe_resources[] = { | ||
| 696 | { | ||
| 697 | .start = IRQ_VDINT0, | ||
| 698 | .end = IRQ_VDINT0, | ||
| 699 | .flags = IORESOURCE_IRQ, | ||
| 700 | }, | ||
| 701 | { | ||
| 702 | .start = IRQ_VDINT1, | ||
| 703 | .end = IRQ_VDINT1, | ||
| 704 | .flags = IORESOURCE_IRQ, | ||
| 705 | }, | ||
| 706 | /* CCDC Base address */ | ||
| 707 | { | ||
| 708 | .flags = IORESOURCE_MEM, | ||
| 709 | .start = 0x01c70600, | ||
| 710 | .end = 0x01c70600 + 0x1ff, | ||
| 711 | }, | ||
| 712 | }; | ||
| 713 | |||
| 714 | static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); | ||
| 715 | static struct platform_device vpfe_capture_dev = { | ||
| 716 | .name = CAPTURE_DRV_NAME, | ||
| 717 | .id = -1, | ||
| 718 | .num_resources = ARRAY_SIZE(vpfe_resources), | ||
| 719 | .resource = vpfe_resources, | ||
| 720 | .dev = { | ||
| 721 | .dma_mask = &vpfe_capture_dma_mask, | ||
| 722 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 723 | }, | ||
| 724 | }; | ||
| 725 | |||
| 726 | void dm355_set_vpfe_config(struct vpfe_config *cfg) | ||
| 727 | { | ||
| 728 | vpfe_capture_dev.dev.platform_data = cfg; | ||
| 729 | } | ||
| 730 | |||
| 607 | /*----------------------------------------------------------------------*/ | 731 | /*----------------------------------------------------------------------*/ |
| 608 | 732 | ||
| 609 | static struct map_desc dm355_io_desc[] = { | 733 | static struct map_desc dm355_io_desc[] = { |
| @@ -704,7 +828,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { | |||
| 704 | .intc_irq_prios = dm355_default_priorities, | 828 | .intc_irq_prios = dm355_default_priorities, |
| 705 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | 829 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, |
| 706 | .timer_info = &dm355_timer_info, | 830 | .timer_info = &dm355_timer_info, |
| 707 | .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), | ||
| 708 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), | 831 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), |
| 709 | .gpio_num = 104, | 832 | .gpio_num = 104, |
| 710 | .gpio_irq = IRQ_DM355_GPIOBNK0, | 833 | .gpio_irq = IRQ_DM355_GPIOBNK0, |
| @@ -713,6 +836,19 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { | |||
| 713 | .sram_len = SZ_32K, | 836 | .sram_len = SZ_32K, |
| 714 | }; | 837 | }; |
| 715 | 838 | ||
| 839 | void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) | ||
| 840 | { | ||
| 841 | /* we don't use ASP1 IRQs, or we'd need to mux them ... */ | ||
| 842 | if (evt_enable & ASP1_TX_EVT_EN) | ||
| 843 | davinci_cfg_reg(DM355_EVT8_ASP1_TX); | ||
| 844 | |||
| 845 | if (evt_enable & ASP1_RX_EVT_EN) | ||
| 846 | davinci_cfg_reg(DM355_EVT9_ASP1_RX); | ||
| 847 | |||
| 848 | dm355_asp1_device.dev.platform_data = pdata; | ||
| 849 | platform_device_register(&dm355_asp1_device); | ||
| 850 | } | ||
| 851 | |||
| 716 | void __init dm355_init(void) | 852 | void __init dm355_init(void) |
| 717 | { | 853 | { |
| 718 | davinci_common_init(&davinci_soc_info_dm355); | 854 | davinci_common_init(&davinci_soc_info_dm355); |
| @@ -725,6 +861,20 @@ static int __init dm355_init_devices(void) | |||
| 725 | 861 | ||
| 726 | davinci_cfg_reg(DM355_INT_EDMA_CC); | 862 | davinci_cfg_reg(DM355_INT_EDMA_CC); |
| 727 | platform_device_register(&dm355_edma_device); | 863 | platform_device_register(&dm355_edma_device); |
| 864 | platform_device_register(&dm355_vpss_device); | ||
| 865 | /* | ||
| 866 | * setup Mux configuration for vpfe input and register | ||
| 867 | * vpfe capture platform device | ||
| 868 | */ | ||
| 869 | davinci_cfg_reg(DM355_VIN_PCLK); | ||
| 870 | davinci_cfg_reg(DM355_VIN_CAM_WEN); | ||
| 871 | davinci_cfg_reg(DM355_VIN_CAM_VD); | ||
| 872 | davinci_cfg_reg(DM355_VIN_CAM_HD); | ||
| 873 | davinci_cfg_reg(DM355_VIN_YIN_EN); | ||
| 874 | davinci_cfg_reg(DM355_VIN_CINL_EN); | ||
| 875 | davinci_cfg_reg(DM355_VIN_CINH_EN); | ||
| 876 | platform_device_register(&vpfe_capture_dev); | ||
| 877 | |||
| 728 | return 0; | 878 | return 0; |
| 729 | } | 879 | } |
| 730 | postcore_initcall(dm355_init_devices); | 880 | postcore_initcall(dm355_init_devices); |
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c new file mode 100644 index 000000000000..e81517434703 --- /dev/null +++ b/arch/arm/mach-davinci/dm365.c | |||
| @@ -0,0 +1,926 @@ | |||
| 1 | /* | ||
| 2 | * TI DaVinci DM365 chip specific setup | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Texas Instruments | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/clk.h> | ||
| 18 | #include <linux/serial_8250.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/dma-mapping.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | |||
| 23 | #include <asm/mach/map.h> | ||
| 24 | |||
| 25 | #include <mach/dm365.h> | ||
| 26 | #include <mach/clock.h> | ||
| 27 | #include <mach/cputype.h> | ||
| 28 | #include <mach/edma.h> | ||
| 29 | #include <mach/psc.h> | ||
| 30 | #include <mach/mux.h> | ||
| 31 | #include <mach/irqs.h> | ||
| 32 | #include <mach/time.h> | ||
| 33 | #include <mach/serial.h> | ||
| 34 | #include <mach/common.h> | ||
| 35 | |||
| 36 | #include "clock.h" | ||
| 37 | #include "mux.h" | ||
| 38 | |||
| 39 | #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ | ||
| 40 | |||
| 41 | static struct pll_data pll1_data = { | ||
| 42 | .num = 1, | ||
| 43 | .phys_base = DAVINCI_PLL1_BASE, | ||
| 44 | .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct pll_data pll2_data = { | ||
| 48 | .num = 2, | ||
| 49 | .phys_base = DAVINCI_PLL2_BASE, | ||
| 50 | .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, | ||
| 51 | }; | ||
| 52 | |||
| 53 | static struct clk ref_clk = { | ||
| 54 | .name = "ref_clk", | ||
| 55 | .rate = DM365_REF_FREQ, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct clk pll1_clk = { | ||
| 59 | .name = "pll1", | ||
| 60 | .parent = &ref_clk, | ||
| 61 | .flags = CLK_PLL, | ||
| 62 | .pll_data = &pll1_data, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct clk pll1_aux_clk = { | ||
| 66 | .name = "pll1_aux_clk", | ||
| 67 | .parent = &pll1_clk, | ||
| 68 | .flags = CLK_PLL | PRE_PLL, | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct clk pll1_sysclkbp = { | ||
| 72 | .name = "pll1_sysclkbp", | ||
| 73 | .parent = &pll1_clk, | ||
| 74 | .flags = CLK_PLL | PRE_PLL, | ||
| 75 | .div_reg = BPDIV | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct clk clkout0_clk = { | ||
| 79 | .name = "clkout0", | ||
| 80 | .parent = &pll1_clk, | ||
| 81 | .flags = CLK_PLL | PRE_PLL, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct clk pll1_sysclk1 = { | ||
| 85 | .name = "pll1_sysclk1", | ||
| 86 | .parent = &pll1_clk, | ||
| 87 | .flags = CLK_PLL, | ||
| 88 | .div_reg = PLLDIV1, | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct clk pll1_sysclk2 = { | ||
| 92 | .name = "pll1_sysclk2", | ||
| 93 | .parent = &pll1_clk, | ||
| 94 | .flags = CLK_PLL, | ||
| 95 | .div_reg = PLLDIV2, | ||
| 96 | }; | ||
| 97 | |||
| 98 | static struct clk pll1_sysclk3 = { | ||
| 99 | .name = "pll1_sysclk3", | ||
| 100 | .parent = &pll1_clk, | ||
| 101 | .flags = CLK_PLL, | ||
| 102 | .div_reg = PLLDIV3, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct clk pll1_sysclk4 = { | ||
| 106 | .name = "pll1_sysclk4", | ||
| 107 | .parent = &pll1_clk, | ||
| 108 | .flags = CLK_PLL, | ||
| 109 | .div_reg = PLLDIV4, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct clk pll1_sysclk5 = { | ||
| 113 | .name = "pll1_sysclk5", | ||
| 114 | .parent = &pll1_clk, | ||
| 115 | .flags = CLK_PLL, | ||
| 116 | .div_reg = PLLDIV5, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct clk pll1_sysclk6 = { | ||
| 120 | .name = "pll1_sysclk6", | ||
| 121 | .parent = &pll1_clk, | ||
| 122 | .flags = CLK_PLL, | ||
| 123 | .div_reg = PLLDIV6, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct clk pll1_sysclk7 = { | ||
| 127 | .name = "pll1_sysclk7", | ||
| 128 | .parent = &pll1_clk, | ||
| 129 | .flags = CLK_PLL, | ||
| 130 | .div_reg = PLLDIV7, | ||
| 131 | }; | ||
| 132 | |||
| 133 | static struct clk pll1_sysclk8 = { | ||
| 134 | .name = "pll1_sysclk8", | ||
| 135 | .parent = &pll1_clk, | ||
| 136 | .flags = CLK_PLL, | ||
| 137 | .div_reg = PLLDIV8, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static struct clk pll1_sysclk9 = { | ||
| 141 | .name = "pll1_sysclk9", | ||
| 142 | .parent = &pll1_clk, | ||
| 143 | .flags = CLK_PLL, | ||
| 144 | .div_reg = PLLDIV9, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct clk pll2_clk = { | ||
| 148 | .name = "pll2", | ||
| 149 | .parent = &ref_clk, | ||
| 150 | .flags = CLK_PLL, | ||
| 151 | .pll_data = &pll2_data, | ||
| 152 | }; | ||
| 153 | |||
| 154 | static struct clk pll2_aux_clk = { | ||
| 155 | .name = "pll2_aux_clk", | ||
| 156 | .parent = &pll2_clk, | ||
| 157 | .flags = CLK_PLL | PRE_PLL, | ||
| 158 | }; | ||
| 159 | |||
| 160 | static struct clk clkout1_clk = { | ||
| 161 | .name = "clkout1", | ||
| 162 | .parent = &pll2_clk, | ||
| 163 | .flags = CLK_PLL | PRE_PLL, | ||
| 164 | }; | ||
| 165 | |||
| 166 | static struct clk pll2_sysclk1 = { | ||
| 167 | .name = "pll2_sysclk1", | ||
| 168 | .parent = &pll2_clk, | ||
| 169 | .flags = CLK_PLL, | ||
| 170 | .div_reg = PLLDIV1, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct clk pll2_sysclk2 = { | ||
| 174 | .name = "pll2_sysclk2", | ||
| 175 | .parent = &pll2_clk, | ||
| 176 | .flags = CLK_PLL, | ||
| 177 | .div_reg = PLLDIV2, | ||
| 178 | }; | ||
| 179 | |||
| 180 | static struct clk pll2_sysclk3 = { | ||
| 181 | .name = "pll2_sysclk3", | ||
| 182 | .parent = &pll2_clk, | ||
| 183 | .flags = CLK_PLL, | ||
| 184 | .div_reg = PLLDIV3, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static struct clk pll2_sysclk4 = { | ||
| 188 | .name = "pll2_sysclk4", | ||
| 189 | .parent = &pll2_clk, | ||
| 190 | .flags = CLK_PLL, | ||
| 191 | .div_reg = PLLDIV4, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct clk pll2_sysclk5 = { | ||
| 195 | .name = "pll2_sysclk5", | ||
| 196 | .parent = &pll2_clk, | ||
| 197 | .flags = CLK_PLL, | ||
| 198 | .div_reg = PLLDIV5, | ||
| 199 | }; | ||
| 200 | |||
| 201 | static struct clk pll2_sysclk6 = { | ||
| 202 | .name = "pll2_sysclk6", | ||
| 203 | .parent = &pll2_clk, | ||
| 204 | .flags = CLK_PLL, | ||
| 205 | .div_reg = PLLDIV6, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static struct clk pll2_sysclk7 = { | ||
| 209 | .name = "pll2_sysclk7", | ||
| 210 | .parent = &pll2_clk, | ||
| 211 | .flags = CLK_PLL, | ||
| 212 | .div_reg = PLLDIV7, | ||
| 213 | }; | ||
| 214 | |||
| 215 | static struct clk pll2_sysclk8 = { | ||
| 216 | .name = "pll2_sysclk8", | ||
| 217 | .parent = &pll2_clk, | ||
| 218 | .flags = CLK_PLL, | ||
| 219 | .div_reg = PLLDIV8, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static struct clk pll2_sysclk9 = { | ||
| 223 | .name = "pll2_sysclk9", | ||
| 224 | .parent = &pll2_clk, | ||
| 225 | .flags = CLK_PLL, | ||
| 226 | .div_reg = PLLDIV9, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static struct clk vpss_dac_clk = { | ||
| 230 | .name = "vpss_dac", | ||
| 231 | .parent = &pll1_sysclk3, | ||
| 232 | .lpsc = DM365_LPSC_DAC_CLK, | ||
| 233 | }; | ||
| 234 | |||
| 235 | static struct clk vpss_master_clk = { | ||
| 236 | .name = "vpss_master", | ||
| 237 | .parent = &pll1_sysclk5, | ||
| 238 | .lpsc = DM365_LPSC_VPSSMSTR, | ||
| 239 | .flags = CLK_PSC, | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct clk arm_clk = { | ||
| 243 | .name = "arm_clk", | ||
| 244 | .parent = &pll2_sysclk2, | ||
| 245 | .lpsc = DAVINCI_LPSC_ARM, | ||
| 246 | .flags = ALWAYS_ENABLED, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct clk uart0_clk = { | ||
| 250 | .name = "uart0", | ||
| 251 | .parent = &pll1_aux_clk, | ||
| 252 | .lpsc = DAVINCI_LPSC_UART0, | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct clk uart1_clk = { | ||
| 256 | .name = "uart1", | ||
| 257 | .parent = &pll1_sysclk4, | ||
| 258 | .lpsc = DAVINCI_LPSC_UART1, | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct clk i2c_clk = { | ||
| 262 | .name = "i2c", | ||
| 263 | .parent = &pll1_aux_clk, | ||
| 264 | .lpsc = DAVINCI_LPSC_I2C, | ||
| 265 | }; | ||
| 266 | |||
| 267 | static struct clk mmcsd0_clk = { | ||
| 268 | .name = "mmcsd0", | ||
| 269 | .parent = &pll1_sysclk8, | ||
| 270 | .lpsc = DAVINCI_LPSC_MMC_SD, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static struct clk mmcsd1_clk = { | ||
| 274 | .name = "mmcsd1", | ||
| 275 | .parent = &pll1_sysclk4, | ||
| 276 | .lpsc = DM365_LPSC_MMC_SD1, | ||
| 277 | }; | ||
| 278 | |||
| 279 | static struct clk spi0_clk = { | ||
| 280 | .name = "spi0", | ||
| 281 | .parent = &pll1_sysclk4, | ||
| 282 | .lpsc = DAVINCI_LPSC_SPI, | ||
| 283 | }; | ||
| 284 | |||
| 285 | static struct clk spi1_clk = { | ||
| 286 | .name = "spi1", | ||
| 287 | .parent = &pll1_sysclk4, | ||
| 288 | .lpsc = DM365_LPSC_SPI1, | ||
| 289 | }; | ||
| 290 | |||
| 291 | static struct clk spi2_clk = { | ||
| 292 | .name = "spi2", | ||
| 293 | .parent = &pll1_sysclk4, | ||
| 294 | .lpsc = DM365_LPSC_SPI2, | ||
| 295 | }; | ||
| 296 | |||
| 297 | static struct clk spi3_clk = { | ||
| 298 | .name = "spi3", | ||
| 299 | .parent = &pll1_sysclk4, | ||
| 300 | .lpsc = DM365_LPSC_SPI3, | ||
| 301 | }; | ||
| 302 | |||
| 303 | static struct clk spi4_clk = { | ||
| 304 | .name = "spi4", | ||
| 305 | .parent = &pll1_aux_clk, | ||
| 306 | .lpsc = DM365_LPSC_SPI4, | ||
| 307 | }; | ||
| 308 | |||
| 309 | static struct clk gpio_clk = { | ||
| 310 | .name = "gpio", | ||
| 311 | .parent = &pll1_sysclk4, | ||
| 312 | .lpsc = DAVINCI_LPSC_GPIO, | ||
| 313 | }; | ||
| 314 | |||
| 315 | static struct clk aemif_clk = { | ||
| 316 | .name = "aemif", | ||
| 317 | .parent = &pll1_sysclk4, | ||
| 318 | .lpsc = DAVINCI_LPSC_AEMIF, | ||
| 319 | }; | ||
| 320 | |||
| 321 | static struct clk pwm0_clk = { | ||
| 322 | .name = "pwm0", | ||
| 323 | .parent = &pll1_aux_clk, | ||
| 324 | .lpsc = DAVINCI_LPSC_PWM0, | ||
| 325 | }; | ||
| 326 | |||
| 327 | static struct clk pwm1_clk = { | ||
| 328 | .name = "pwm1", | ||
| 329 | .parent = &pll1_aux_clk, | ||
| 330 | .lpsc = DAVINCI_LPSC_PWM1, | ||
| 331 | }; | ||
| 332 | |||
| 333 | static struct clk pwm2_clk = { | ||
| 334 | .name = "pwm2", | ||
| 335 | .parent = &pll1_aux_clk, | ||
| 336 | .lpsc = DAVINCI_LPSC_PWM2, | ||
| 337 | }; | ||
| 338 | |||
| 339 | static struct clk pwm3_clk = { | ||
| 340 | .name = "pwm3", | ||
| 341 | .parent = &ref_clk, | ||
| 342 | .lpsc = DM365_LPSC_PWM3, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static struct clk timer0_clk = { | ||
| 346 | .name = "timer0", | ||
| 347 | .parent = &pll1_aux_clk, | ||
| 348 | .lpsc = DAVINCI_LPSC_TIMER0, | ||
| 349 | }; | ||
| 350 | |||
| 351 | static struct clk timer1_clk = { | ||
| 352 | .name = "timer1", | ||
| 353 | .parent = &pll1_aux_clk, | ||
| 354 | .lpsc = DAVINCI_LPSC_TIMER1, | ||
| 355 | }; | ||
| 356 | |||
| 357 | static struct clk timer2_clk = { | ||
| 358 | .name = "timer2", | ||
| 359 | .parent = &pll1_aux_clk, | ||
| 360 | .lpsc = DAVINCI_LPSC_TIMER2, | ||
| 361 | .usecount = 1, | ||
| 362 | }; | ||
| 363 | |||
| 364 | static struct clk timer3_clk = { | ||
| 365 | .name = "timer3", | ||
| 366 | .parent = &pll1_aux_clk, | ||
| 367 | .lpsc = DM365_LPSC_TIMER3, | ||
| 368 | }; | ||
| 369 | |||
| 370 | static struct clk usb_clk = { | ||
| 371 | .name = "usb", | ||
| 372 | .parent = &pll2_sysclk1, | ||
| 373 | .lpsc = DAVINCI_LPSC_USB, | ||
| 374 | }; | ||
| 375 | |||
| 376 | static struct clk emac_clk = { | ||
| 377 | .name = "emac", | ||
| 378 | .parent = &pll1_sysclk4, | ||
| 379 | .lpsc = DM365_LPSC_EMAC, | ||
| 380 | }; | ||
| 381 | |||
| 382 | static struct clk voicecodec_clk = { | ||
| 383 | .name = "voice_codec", | ||
| 384 | .parent = &pll2_sysclk4, | ||
| 385 | .lpsc = DM365_LPSC_VOICE_CODEC, | ||
| 386 | }; | ||
| 387 | |||
| 388 | static struct clk asp0_clk = { | ||
| 389 | .name = "asp0", | ||
| 390 | .parent = &pll1_sysclk4, | ||
| 391 | .lpsc = DM365_LPSC_McBSP1, | ||
| 392 | }; | ||
| 393 | |||
| 394 | static struct clk rto_clk = { | ||
| 395 | .name = "rto", | ||
| 396 | .parent = &pll1_sysclk4, | ||
| 397 | .lpsc = DM365_LPSC_RTO, | ||
| 398 | }; | ||
| 399 | |||
| 400 | static struct clk mjcp_clk = { | ||
| 401 | .name = "mjcp", | ||
| 402 | .parent = &pll1_sysclk3, | ||
| 403 | .lpsc = DM365_LPSC_MJCP, | ||
| 404 | }; | ||
| 405 | |||
| 406 | static struct davinci_clk dm365_clks[] = { | ||
| 407 | CLK(NULL, "ref", &ref_clk), | ||
| 408 | CLK(NULL, "pll1", &pll1_clk), | ||
| 409 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | ||
| 410 | CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), | ||
| 411 | CLK(NULL, "clkout0", &clkout0_clk), | ||
| 412 | CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), | ||
| 413 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | ||
| 414 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | ||
| 415 | CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), | ||
| 416 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | ||
| 417 | CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), | ||
| 418 | CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), | ||
| 419 | CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), | ||
| 420 | CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), | ||
| 421 | CLK(NULL, "pll2", &pll2_clk), | ||
| 422 | CLK(NULL, "pll2_aux", &pll2_aux_clk), | ||
| 423 | CLK(NULL, "clkout1", &clkout1_clk), | ||
| 424 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | ||
| 425 | CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), | ||
| 426 | CLK(NULL, "pll2_sysclk3", &pll2_sysclk3), | ||
| 427 | CLK(NULL, "pll2_sysclk4", &pll2_sysclk4), | ||
| 428 | CLK(NULL, "pll2_sysclk5", &pll2_sysclk5), | ||
| 429 | CLK(NULL, "pll2_sysclk6", &pll2_sysclk6), | ||
| 430 | CLK(NULL, "pll2_sysclk7", &pll2_sysclk7), | ||
| 431 | CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), | ||
| 432 | CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), | ||
| 433 | CLK(NULL, "vpss_dac", &vpss_dac_clk), | ||
| 434 | CLK(NULL, "vpss_master", &vpss_master_clk), | ||
| 435 | CLK(NULL, "arm", &arm_clk), | ||
| 436 | CLK(NULL, "uart0", &uart0_clk), | ||
| 437 | CLK(NULL, "uart1", &uart1_clk), | ||
| 438 | CLK("i2c_davinci.1", NULL, &i2c_clk), | ||
| 439 | CLK("davinci_mmc.0", NULL, &mmcsd0_clk), | ||
| 440 | CLK("davinci_mmc.1", NULL, &mmcsd1_clk), | ||
| 441 | CLK("spi_davinci.0", NULL, &spi0_clk), | ||
| 442 | CLK("spi_davinci.1", NULL, &spi1_clk), | ||
| 443 | CLK("spi_davinci.2", NULL, &spi2_clk), | ||
| 444 | CLK("spi_davinci.3", NULL, &spi3_clk), | ||
| 445 | CLK("spi_davinci.4", NULL, &spi4_clk), | ||
| 446 | CLK(NULL, "gpio", &gpio_clk), | ||
| 447 | CLK(NULL, "aemif", &aemif_clk), | ||
| 448 | CLK(NULL, "pwm0", &pwm0_clk), | ||
| 449 | CLK(NULL, "pwm1", &pwm1_clk), | ||
| 450 | CLK(NULL, "pwm2", &pwm2_clk), | ||
| 451 | CLK(NULL, "pwm3", &pwm3_clk), | ||
| 452 | CLK(NULL, "timer0", &timer0_clk), | ||
| 453 | CLK(NULL, "timer1", &timer1_clk), | ||
| 454 | CLK("watchdog", NULL, &timer2_clk), | ||
| 455 | CLK(NULL, "timer3", &timer3_clk), | ||
| 456 | CLK(NULL, "usb", &usb_clk), | ||
| 457 | CLK("davinci_emac.1", NULL, &emac_clk), | ||
| 458 | CLK("voice_codec", NULL, &voicecodec_clk), | ||
| 459 | CLK("soc-audio.0", NULL, &asp0_clk), | ||
| 460 | CLK(NULL, "rto", &rto_clk), | ||
| 461 | CLK(NULL, "mjcp", &mjcp_clk), | ||
| 462 | CLK(NULL, NULL, NULL), | ||
| 463 | }; | ||
| 464 | |||
| 465 | /*----------------------------------------------------------------------*/ | ||
| 466 | |||
| 467 | #define PINMUX0 0x00 | ||
| 468 | #define PINMUX1 0x04 | ||
| 469 | #define PINMUX2 0x08 | ||
| 470 | #define PINMUX3 0x0c | ||
| 471 | #define PINMUX4 0x10 | ||
| 472 | #define INTMUX 0x18 | ||
| 473 | #define EVTMUX 0x1c | ||
| 474 | |||
| 475 | |||
| 476 | static const struct mux_config dm365_pins[] = { | ||
| 477 | #ifdef CONFIG_DAVINCI_MUX | ||
| 478 | MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) | ||
| 479 | |||
| 480 | MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) | ||
| 481 | MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) | ||
| 482 | MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) | ||
| 483 | MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) | ||
| 484 | MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) | ||
| 485 | MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) | ||
| 486 | |||
| 487 | MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) | ||
| 488 | MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) | ||
| 489 | |||
| 490 | MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false) | ||
| 491 | MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) | ||
| 492 | MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) | ||
| 493 | MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) | ||
| 494 | MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) | ||
| 495 | |||
| 496 | MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) | ||
| 497 | MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) | ||
| 498 | MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) | ||
| 499 | MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) | ||
| 500 | MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) | ||
| 501 | MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) | ||
| 502 | |||
| 503 | MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) | ||
| 504 | MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) | ||
| 505 | MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) | ||
| 506 | MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) | ||
| 507 | MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) | ||
| 508 | |||
| 509 | MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) | ||
| 510 | MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) | ||
| 511 | MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) | ||
| 512 | MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) | ||
| 513 | MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) | ||
| 514 | MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) | ||
| 515 | |||
| 516 | MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) | ||
| 517 | MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) | ||
| 518 | MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) | ||
| 519 | MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) | ||
| 520 | MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) | ||
| 521 | MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) | ||
| 522 | MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) | ||
| 523 | MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) | ||
| 524 | MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) | ||
| 525 | MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) | ||
| 526 | MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) | ||
| 527 | MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) | ||
| 528 | MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) | ||
| 529 | MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) | ||
| 530 | MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) | ||
| 531 | MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) | ||
| 532 | MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) | ||
| 533 | |||
| 534 | MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false) | ||
| 535 | |||
| 536 | MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) | ||
| 537 | MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) | ||
| 538 | MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) | ||
| 539 | MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) | ||
| 540 | MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) | ||
| 541 | MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) | ||
| 542 | MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) | ||
| 543 | MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) | ||
| 544 | MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) | ||
| 545 | MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) | ||
| 546 | MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) | ||
| 547 | MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) | ||
| 548 | |||
| 549 | MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) | ||
| 550 | MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) | ||
| 551 | MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) | ||
| 552 | MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) | ||
| 553 | MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) | ||
| 554 | |||
| 555 | MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) | ||
| 556 | MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) | ||
| 557 | MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) | ||
| 558 | MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) | ||
| 559 | MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) | ||
| 560 | |||
| 561 | MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) | ||
| 562 | MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) | ||
| 563 | MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) | ||
| 564 | MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) | ||
| 565 | MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) | ||
| 566 | |||
| 567 | MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) | ||
| 568 | MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) | ||
| 569 | MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) | ||
| 570 | MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) | ||
| 571 | MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) | ||
| 572 | |||
| 573 | MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) | ||
| 574 | MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) | ||
| 575 | MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) | ||
| 576 | |||
| 577 | MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) | ||
| 578 | MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) | ||
| 579 | MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) | ||
| 580 | MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) | ||
| 581 | MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) | ||
| 582 | MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) | ||
| 583 | MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) | ||
| 584 | MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) | ||
| 585 | MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) | ||
| 586 | MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) | ||
| 587 | |||
| 588 | INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) | ||
| 589 | INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) | ||
| 590 | INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) | ||
| 591 | INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) | ||
| 592 | INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) | ||
| 593 | INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) | ||
| 594 | INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) | ||
| 595 | INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) | ||
| 596 | INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) | ||
| 597 | INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) | ||
| 598 | INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) | ||
| 599 | INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) | ||
| 600 | INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) | ||
| 601 | INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) | ||
| 602 | INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) | ||
| 603 | INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) | ||
| 604 | INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) | ||
| 605 | INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) | ||
| 606 | #endif | ||
| 607 | }; | ||
| 608 | |||
| 609 | static struct emac_platform_data dm365_emac_pdata = { | ||
| 610 | .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, | ||
| 611 | .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, | ||
| 612 | .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, | ||
| 613 | .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET, | ||
| 614 | .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, | ||
| 615 | .version = EMAC_VERSION_2, | ||
| 616 | }; | ||
| 617 | |||
| 618 | static struct resource dm365_emac_resources[] = { | ||
| 619 | { | ||
| 620 | .start = DM365_EMAC_BASE, | ||
| 621 | .end = DM365_EMAC_BASE + 0x47ff, | ||
| 622 | .flags = IORESOURCE_MEM, | ||
| 623 | }, | ||
| 624 | { | ||
| 625 | .start = IRQ_DM365_EMAC_RXTHRESH, | ||
| 626 | .end = IRQ_DM365_EMAC_RXTHRESH, | ||
| 627 | .flags = IORESOURCE_IRQ, | ||
| 628 | }, | ||
| 629 | { | ||
| 630 | .start = IRQ_DM365_EMAC_RXPULSE, | ||
| 631 | .end = IRQ_DM365_EMAC_RXPULSE, | ||
| 632 | .flags = IORESOURCE_IRQ, | ||
| 633 | }, | ||
| 634 | { | ||
| 635 | .start = IRQ_DM365_EMAC_TXPULSE, | ||
| 636 | .end = IRQ_DM365_EMAC_TXPULSE, | ||
| 637 | .flags = IORESOURCE_IRQ, | ||
| 638 | }, | ||
| 639 | { | ||
| 640 | .start = IRQ_DM365_EMAC_MISCPULSE, | ||
| 641 | .end = IRQ_DM365_EMAC_MISCPULSE, | ||
| 642 | .flags = IORESOURCE_IRQ, | ||
| 643 | }, | ||
| 644 | }; | ||
| 645 | |||
| 646 | static struct platform_device dm365_emac_device = { | ||
| 647 | .name = "davinci_emac", | ||
| 648 | .id = 1, | ||
| 649 | .dev = { | ||
| 650 | .platform_data = &dm365_emac_pdata, | ||
| 651 | }, | ||
| 652 | .num_resources = ARRAY_SIZE(dm365_emac_resources), | ||
| 653 | .resource = dm365_emac_resources, | ||
| 654 | }; | ||
| 655 | |||
| 656 | static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { | ||
| 657 | [IRQ_VDINT0] = 2, | ||
| 658 | [IRQ_VDINT1] = 6, | ||
| 659 | [IRQ_VDINT2] = 6, | ||
| 660 | [IRQ_HISTINT] = 6, | ||
| 661 | [IRQ_H3AINT] = 6, | ||
| 662 | [IRQ_PRVUINT] = 6, | ||
| 663 | [IRQ_RSZINT] = 6, | ||
| 664 | [IRQ_DM365_INSFINT] = 7, | ||
| 665 | [IRQ_VENCINT] = 6, | ||
| 666 | [IRQ_ASQINT] = 6, | ||
| 667 | [IRQ_IMXINT] = 6, | ||
| 668 | [IRQ_DM365_IMCOPINT] = 4, | ||
| 669 | [IRQ_USBINT] = 4, | ||
| 670 | [IRQ_DM365_RTOINT] = 7, | ||
| 671 | [IRQ_DM365_TINT5] = 7, | ||
| 672 | [IRQ_DM365_TINT6] = 5, | ||
| 673 | [IRQ_CCINT0] = 5, | ||
| 674 | [IRQ_CCERRINT] = 5, | ||
| 675 | [IRQ_TCERRINT0] = 5, | ||
| 676 | [IRQ_TCERRINT] = 7, | ||
| 677 | [IRQ_PSCIN] = 4, | ||
| 678 | [IRQ_DM365_SPINT2_1] = 7, | ||
| 679 | [IRQ_DM365_TINT7] = 7, | ||
| 680 | [IRQ_DM365_SDIOINT0] = 7, | ||
| 681 | [IRQ_MBXINT] = 7, | ||
| 682 | [IRQ_MBRINT] = 7, | ||
| 683 | [IRQ_MMCINT] = 7, | ||
| 684 | [IRQ_DM365_MMCINT1] = 7, | ||
| 685 | [IRQ_DM365_PWMINT3] = 7, | ||
| 686 | [IRQ_DDRINT] = 4, | ||
| 687 | [IRQ_AEMIFINT] = 2, | ||
| 688 | [IRQ_DM365_SDIOINT1] = 2, | ||
| 689 | [IRQ_TINT0_TINT12] = 7, | ||
| 690 | [IRQ_TINT0_TINT34] = 7, | ||
| 691 | [IRQ_TINT1_TINT12] = 7, | ||
| 692 | [IRQ_TINT1_TINT34] = 7, | ||
| 693 | [IRQ_PWMINT0] = 7, | ||
| 694 | [IRQ_PWMINT1] = 3, | ||
| 695 | [IRQ_PWMINT2] = 3, | ||
| 696 | [IRQ_I2C] = 3, | ||
| 697 | [IRQ_UARTINT0] = 3, | ||
| 698 | [IRQ_UARTINT1] = 3, | ||
| 699 | [IRQ_DM365_SPIINT0_0] = 3, | ||
| 700 | [IRQ_DM365_SPIINT3_0] = 3, | ||
| 701 | [IRQ_DM365_GPIO0] = 3, | ||
| 702 | [IRQ_DM365_GPIO1] = 7, | ||
| 703 | [IRQ_DM365_GPIO2] = 4, | ||
| 704 | [IRQ_DM365_GPIO3] = 4, | ||
| 705 | [IRQ_DM365_GPIO4] = 7, | ||
| 706 | [IRQ_DM365_GPIO5] = 7, | ||
| 707 | [IRQ_DM365_GPIO6] = 7, | ||
| 708 | [IRQ_DM365_GPIO7] = 7, | ||
| 709 | [IRQ_DM365_EMAC_RXTHRESH] = 7, | ||
| 710 | [IRQ_DM365_EMAC_RXPULSE] = 7, | ||
| 711 | [IRQ_DM365_EMAC_TXPULSE] = 7, | ||
| 712 | [IRQ_DM365_EMAC_MISCPULSE] = 7, | ||
| 713 | [IRQ_DM365_GPIO12] = 7, | ||
| 714 | [IRQ_DM365_GPIO13] = 7, | ||
| 715 | [IRQ_DM365_GPIO14] = 7, | ||
| 716 | [IRQ_DM365_GPIO15] = 7, | ||
| 717 | [IRQ_DM365_KEYINT] = 7, | ||
| 718 | [IRQ_DM365_TCERRINT2] = 7, | ||
| 719 | [IRQ_DM365_TCERRINT3] = 7, | ||
| 720 | [IRQ_DM365_EMUINT] = 7, | ||
| 721 | }; | ||
| 722 | |||
| 723 | /* Four Transfer Controllers on DM365 */ | ||
| 724 | static const s8 | ||
| 725 | dm365_queue_tc_mapping[][2] = { | ||
| 726 | /* {event queue no, TC no} */ | ||
| 727 | {0, 0}, | ||
| 728 | {1, 1}, | ||
| 729 | {2, 2}, | ||
| 730 | {3, 3}, | ||
| 731 | {-1, -1}, | ||
| 732 | }; | ||
| 733 | |||
| 734 | static const s8 | ||
| 735 | dm365_queue_priority_mapping[][2] = { | ||
| 736 | /* {event queue no, Priority} */ | ||
| 737 | {0, 7}, | ||
| 738 | {1, 7}, | ||
| 739 | {2, 7}, | ||
| 740 | {3, 0}, | ||
| 741 | {-1, -1}, | ||
| 742 | }; | ||
| 743 | |||
| 744 | static struct edma_soc_info dm365_edma_info[] = { | ||
| 745 | { | ||
| 746 | .n_channel = 64, | ||
| 747 | .n_region = 4, | ||
| 748 | .n_slot = 256, | ||
| 749 | .n_tc = 4, | ||
| 750 | .n_cc = 1, | ||
| 751 | .queue_tc_mapping = dm365_queue_tc_mapping, | ||
| 752 | .queue_priority_mapping = dm365_queue_priority_mapping, | ||
| 753 | .default_queue = EVENTQ_2, | ||
| 754 | }, | ||
| 755 | }; | ||
| 756 | |||
| 757 | static struct resource edma_resources[] = { | ||
| 758 | { | ||
| 759 | .name = "edma_cc0", | ||
| 760 | .start = 0x01c00000, | ||
| 761 | .end = 0x01c00000 + SZ_64K - 1, | ||
| 762 | .flags = IORESOURCE_MEM, | ||
| 763 | }, | ||
| 764 | { | ||
| 765 | .name = "edma_tc0", | ||
| 766 | .start = 0x01c10000, | ||
| 767 | .end = 0x01c10000 + SZ_1K - 1, | ||
| 768 | .flags = IORESOURCE_MEM, | ||
| 769 | }, | ||
| 770 | { | ||
| 771 | .name = "edma_tc1", | ||
| 772 | .start = 0x01c10400, | ||
| 773 | .end = 0x01c10400 + SZ_1K - 1, | ||
| 774 | .flags = IORESOURCE_MEM, | ||
| 775 | }, | ||
| 776 | { | ||
| 777 | .name = "edma_tc2", | ||
| 778 | .start = 0x01c10800, | ||
| 779 | .end = 0x01c10800 + SZ_1K - 1, | ||
| 780 | .flags = IORESOURCE_MEM, | ||
| 781 | }, | ||
| 782 | { | ||
| 783 | .name = "edma_tc3", | ||
| 784 | .start = 0x01c10c00, | ||
| 785 | .end = 0x01c10c00 + SZ_1K - 1, | ||
| 786 | .flags = IORESOURCE_MEM, | ||
| 787 | }, | ||
| 788 | { | ||
| 789 | .name = "edma0", | ||
| 790 | .start = IRQ_CCINT0, | ||
| 791 | .flags = IORESOURCE_IRQ, | ||
| 792 | }, | ||
| 793 | { | ||
| 794 | .name = "edma0_err", | ||
| 795 | .start = IRQ_CCERRINT, | ||
| 796 | .flags = IORESOURCE_IRQ, | ||
| 797 | }, | ||
| 798 | /* not using TC*_ERR */ | ||
| 799 | }; | ||
| 800 | |||
| 801 | static struct platform_device dm365_edma_device = { | ||
| 802 | .name = "edma", | ||
| 803 | .id = 0, | ||
| 804 | .dev.platform_data = dm365_edma_info, | ||
| 805 | .num_resources = ARRAY_SIZE(edma_resources), | ||
| 806 | .resource = edma_resources, | ||
| 807 | }; | ||
| 808 | |||
| 809 | static struct map_desc dm365_io_desc[] = { | ||
| 810 | { | ||
| 811 | .virtual = IO_VIRT, | ||
| 812 | .pfn = __phys_to_pfn(IO_PHYS), | ||
| 813 | .length = IO_SIZE, | ||
| 814 | .type = MT_DEVICE | ||
| 815 | }, | ||
| 816 | { | ||
| 817 | .virtual = SRAM_VIRT, | ||
| 818 | .pfn = __phys_to_pfn(0x00010000), | ||
| 819 | .length = SZ_32K, | ||
| 820 | /* MT_MEMORY_NONCACHED requires supersection alignment */ | ||
| 821 | .type = MT_DEVICE, | ||
| 822 | }, | ||
| 823 | }; | ||
| 824 | |||
| 825 | /* Contents of JTAG ID register used to identify exact cpu type */ | ||
| 826 | static struct davinci_id dm365_ids[] = { | ||
| 827 | { | ||
| 828 | .variant = 0x0, | ||
| 829 | .part_no = 0xb83e, | ||
| 830 | .manufacturer = 0x017, | ||
| 831 | .cpu_id = DAVINCI_CPU_ID_DM365, | ||
| 832 | .name = "dm365_rev1.1", | ||
| 833 | }, | ||
| 834 | { | ||
| 835 | .variant = 0x8, | ||
| 836 | .part_no = 0xb83e, | ||
| 837 | .manufacturer = 0x017, | ||
| 838 | .cpu_id = DAVINCI_CPU_ID_DM365, | ||
| 839 | .name = "dm365_rev1.2", | ||
| 840 | }, | ||
| 841 | }; | ||
| 842 | |||
| 843 | static void __iomem *dm365_psc_bases[] = { | ||
| 844 | IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), | ||
| 845 | }; | ||
| 846 | |||
| 847 | struct davinci_timer_info dm365_timer_info = { | ||
| 848 | .timers = davinci_timer_instance, | ||
| 849 | .clockevent_id = T0_BOT, | ||
| 850 | .clocksource_id = T0_TOP, | ||
| 851 | }; | ||
| 852 | |||
| 853 | static struct plat_serial8250_port dm365_serial_platform_data[] = { | ||
| 854 | { | ||
| 855 | .mapbase = DAVINCI_UART0_BASE, | ||
| 856 | .irq = IRQ_UARTINT0, | ||
| 857 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | ||
| 858 | UPF_IOREMAP, | ||
| 859 | .iotype = UPIO_MEM, | ||
| 860 | .regshift = 2, | ||
| 861 | }, | ||
| 862 | { | ||
| 863 | .mapbase = DAVINCI_UART1_BASE, | ||
| 864 | .irq = IRQ_UARTINT1, | ||
| 865 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | ||
| 866 | UPF_IOREMAP, | ||
| 867 | .iotype = UPIO_MEM, | ||
| 868 | .regshift = 2, | ||
| 869 | }, | ||
| 870 | { | ||
| 871 | .flags = 0 | ||
| 872 | }, | ||
| 873 | }; | ||
| 874 | |||
| 875 | static struct platform_device dm365_serial_device = { | ||
| 876 | .name = "serial8250", | ||
| 877 | .id = PLAT8250_DEV_PLATFORM, | ||
| 878 | .dev = { | ||
| 879 | .platform_data = dm365_serial_platform_data, | ||
| 880 | }, | ||
| 881 | }; | ||
| 882 | |||
| 883 | static struct davinci_soc_info davinci_soc_info_dm365 = { | ||
| 884 | .io_desc = dm365_io_desc, | ||
| 885 | .io_desc_num = ARRAY_SIZE(dm365_io_desc), | ||
| 886 | .jtag_id_base = IO_ADDRESS(0x01c40028), | ||
| 887 | .ids = dm365_ids, | ||
| 888 | .ids_num = ARRAY_SIZE(dm365_ids), | ||
| 889 | .cpu_clks = dm365_clks, | ||
| 890 | .psc_bases = dm365_psc_bases, | ||
| 891 | .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), | ||
| 892 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), | ||
| 893 | .pinmux_pins = dm365_pins, | ||
| 894 | .pinmux_pins_num = ARRAY_SIZE(dm365_pins), | ||
| 895 | .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), | ||
| 896 | .intc_type = DAVINCI_INTC_TYPE_AINTC, | ||
| 897 | .intc_irq_prios = dm365_default_priorities, | ||
| 898 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | ||
| 899 | .timer_info = &dm365_timer_info, | ||
| 900 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), | ||
| 901 | .gpio_num = 104, | ||
| 902 | .gpio_irq = IRQ_DM365_GPIO0, | ||
| 903 | .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ | ||
| 904 | .serial_dev = &dm365_serial_device, | ||
| 905 | .emac_pdata = &dm365_emac_pdata, | ||
| 906 | .sram_dma = 0x00010000, | ||
| 907 | .sram_len = SZ_32K, | ||
| 908 | }; | ||
| 909 | |||
| 910 | void __init dm365_init(void) | ||
| 911 | { | ||
| 912 | davinci_common_init(&davinci_soc_info_dm365); | ||
| 913 | } | ||
| 914 | |||
| 915 | static int __init dm365_init_devices(void) | ||
| 916 | { | ||
| 917 | if (!cpu_is_davinci_dm365()) | ||
| 918 | return 0; | ||
| 919 | |||
| 920 | davinci_cfg_reg(DM365_INT_EDMA_CC); | ||
| 921 | platform_device_register(&dm365_edma_device); | ||
| 922 | platform_device_register(&dm365_emac_device); | ||
| 923 | |||
| 924 | return 0; | ||
| 925 | } | ||
| 926 | postcore_initcall(dm365_init_devices); | ||
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index fb5449b3c97b..d6e0fa5a8d8a 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <mach/time.h> | 27 | #include <mach/time.h> |
| 28 | #include <mach/serial.h> | 28 | #include <mach/serial.h> |
| 29 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 30 | #include <mach/asp.h> | ||
| 30 | 31 | ||
| 31 | #include "clock.h" | 32 | #include "clock.h" |
| 32 | #include "mux.h" | 33 | #include "mux.h" |
| @@ -303,7 +304,7 @@ struct davinci_clk dm644x_clks[] = { | |||
| 303 | CLK("davinci_emac.1", NULL, &emac_clk), | 304 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 304 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 305 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 305 | CLK("palm_bk3710", NULL, &ide_clk), | 306 | CLK("palm_bk3710", NULL, &ide_clk), |
| 306 | CLK("soc-audio.0", NULL, &asp_clk), | 307 | CLK("davinci-asp", NULL, &asp_clk), |
| 307 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), | 308 | CLK("davinci_mmc.0", NULL, &mmcsd_clk), |
| 308 | CLK(NULL, "spi", &spi_clk), | 309 | CLK(NULL, "spi", &spi_clk), |
| 309 | CLK(NULL, "gpio", &gpio_clk), | 310 | CLK(NULL, "gpio", &gpio_clk), |
| @@ -484,17 +485,38 @@ static const s8 dma_chan_dm644x_no_event[] = { | |||
| 484 | -1 | 485 | -1 |
| 485 | }; | 486 | }; |
| 486 | 487 | ||
| 487 | static struct edma_soc_info dm644x_edma_info = { | 488 | static const s8 |
| 488 | .n_channel = 64, | 489 | queue_tc_mapping[][2] = { |
| 489 | .n_region = 4, | 490 | /* {event queue no, TC no} */ |
| 490 | .n_slot = 128, | 491 | {0, 0}, |
| 491 | .n_tc = 2, | 492 | {1, 1}, |
| 492 | .noevent = dma_chan_dm644x_no_event, | 493 | {-1, -1}, |
| 494 | }; | ||
| 495 | |||
| 496 | static const s8 | ||
| 497 | queue_priority_mapping[][2] = { | ||
| 498 | /* {event queue no, Priority} */ | ||
| 499 | {0, 3}, | ||
| 500 | {1, 7}, | ||
| 501 | {-1, -1}, | ||
| 502 | }; | ||
| 503 | |||
| 504 | static struct edma_soc_info dm644x_edma_info[] = { | ||
| 505 | { | ||
| 506 | .n_channel = 64, | ||
| 507 | .n_region = 4, | ||
| 508 | .n_slot = 128, | ||
| 509 | .n_tc = 2, | ||
| 510 | .n_cc = 1, | ||
| 511 | .noevent = dma_chan_dm644x_no_event, | ||
| 512 | .queue_tc_mapping = queue_tc_mapping, | ||
| 513 | .queue_priority_mapping = queue_priority_mapping, | ||
| 514 | }, | ||
| 493 | }; | 515 | }; |
| 494 | 516 | ||
| 495 | static struct resource edma_resources[] = { | 517 | static struct resource edma_resources[] = { |
| 496 | { | 518 | { |
| 497 | .name = "edma_cc", | 519 | .name = "edma_cc0", |
| 498 | .start = 0x01c00000, | 520 | .start = 0x01c00000, |
| 499 | .end = 0x01c00000 + SZ_64K - 1, | 521 | .end = 0x01c00000 + SZ_64K - 1, |
| 500 | .flags = IORESOURCE_MEM, | 522 | .flags = IORESOURCE_MEM, |
| @@ -512,10 +534,12 @@ static struct resource edma_resources[] = { | |||
| 512 | .flags = IORESOURCE_MEM, | 534 | .flags = IORESOURCE_MEM, |
| 513 | }, | 535 | }, |
| 514 | { | 536 | { |
| 537 | .name = "edma0", | ||
| 515 | .start = IRQ_CCINT0, | 538 | .start = IRQ_CCINT0, |
| 516 | .flags = IORESOURCE_IRQ, | 539 | .flags = IORESOURCE_IRQ, |
| 517 | }, | 540 | }, |
| 518 | { | 541 | { |
| 542 | .name = "edma0_err", | ||
| 519 | .start = IRQ_CCERRINT, | 543 | .start = IRQ_CCERRINT, |
| 520 | .flags = IORESOURCE_IRQ, | 544 | .flags = IORESOURCE_IRQ, |
| 521 | }, | 545 | }, |
| @@ -524,12 +548,91 @@ static struct resource edma_resources[] = { | |||
| 524 | 548 | ||
| 525 | static struct platform_device dm644x_edma_device = { | 549 | static struct platform_device dm644x_edma_device = { |
| 526 | .name = "edma", | 550 | .name = "edma", |
| 527 | .id = -1, | 551 | .id = 0, |
| 528 | .dev.platform_data = &dm644x_edma_info, | 552 | .dev.platform_data = dm644x_edma_info, |
| 529 | .num_resources = ARRAY_SIZE(edma_resources), | 553 | .num_resources = ARRAY_SIZE(edma_resources), |
| 530 | .resource = edma_resources, | 554 | .resource = edma_resources, |
| 531 | }; | 555 | }; |
| 532 | 556 | ||
| 557 | /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ | ||
| 558 | static struct resource dm644x_asp_resources[] = { | ||
| 559 | { | ||
| 560 | .start = DAVINCI_ASP0_BASE, | ||
| 561 | .end = DAVINCI_ASP0_BASE + SZ_8K - 1, | ||
| 562 | .flags = IORESOURCE_MEM, | ||
| 563 | }, | ||
| 564 | { | ||
| 565 | .start = DAVINCI_DMA_ASP0_TX, | ||
| 566 | .end = DAVINCI_DMA_ASP0_TX, | ||
| 567 | .flags = IORESOURCE_DMA, | ||
| 568 | }, | ||
| 569 | { | ||
| 570 | .start = DAVINCI_DMA_ASP0_RX, | ||
| 571 | .end = DAVINCI_DMA_ASP0_RX, | ||
| 572 | .flags = IORESOURCE_DMA, | ||
| 573 | }, | ||
| 574 | }; | ||
| 575 | |||
| 576 | static struct platform_device dm644x_asp_device = { | ||
| 577 | .name = "davinci-asp", | ||
| 578 | .id = -1, | ||
| 579 | .num_resources = ARRAY_SIZE(dm644x_asp_resources), | ||
| 580 | .resource = dm644x_asp_resources, | ||
| 581 | }; | ||
| 582 | |||
| 583 | static struct resource dm644x_vpss_resources[] = { | ||
| 584 | { | ||
| 585 | /* VPSS Base address */ | ||
| 586 | .name = "vpss", | ||
| 587 | .start = 0x01c73400, | ||
| 588 | .end = 0x01c73400 + 0xff, | ||
| 589 | .flags = IORESOURCE_MEM, | ||
| 590 | }, | ||
| 591 | }; | ||
| 592 | |||
| 593 | static struct platform_device dm644x_vpss_device = { | ||
| 594 | .name = "vpss", | ||
| 595 | .id = -1, | ||
| 596 | .dev.platform_data = "dm644x_vpss", | ||
| 597 | .num_resources = ARRAY_SIZE(dm644x_vpss_resources), | ||
| 598 | .resource = dm644x_vpss_resources, | ||
| 599 | }; | ||
| 600 | |||
| 601 | static struct resource vpfe_resources[] = { | ||
| 602 | { | ||
| 603 | .start = IRQ_VDINT0, | ||
| 604 | .end = IRQ_VDINT0, | ||
| 605 | .flags = IORESOURCE_IRQ, | ||
| 606 | }, | ||
| 607 | { | ||
| 608 | .start = IRQ_VDINT1, | ||
| 609 | .end = IRQ_VDINT1, | ||
| 610 | .flags = IORESOURCE_IRQ, | ||
| 611 | }, | ||
| 612 | { | ||
| 613 | .start = 0x01c70400, | ||
| 614 | .end = 0x01c70400 + 0xff, | ||
| 615 | .flags = IORESOURCE_MEM, | ||
| 616 | }, | ||
| 617 | }; | ||
| 618 | |||
| 619 | static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); | ||
| 620 | static struct platform_device vpfe_capture_dev = { | ||
| 621 | .name = CAPTURE_DRV_NAME, | ||
| 622 | .id = -1, | ||
| 623 | .num_resources = ARRAY_SIZE(vpfe_resources), | ||
| 624 | .resource = vpfe_resources, | ||
| 625 | .dev = { | ||
| 626 | .dma_mask = &vpfe_capture_dma_mask, | ||
| 627 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 628 | }, | ||
| 629 | }; | ||
| 630 | |||
| 631 | void dm644x_set_vpfe_config(struct vpfe_config *cfg) | ||
| 632 | { | ||
| 633 | vpfe_capture_dev.dev.platform_data = cfg; | ||
| 634 | } | ||
| 635 | |||
| 533 | /*----------------------------------------------------------------------*/ | 636 | /*----------------------------------------------------------------------*/ |
| 534 | 637 | ||
| 535 | static struct map_desc dm644x_io_desc[] = { | 638 | static struct map_desc dm644x_io_desc[] = { |
| @@ -557,6 +660,13 @@ static struct davinci_id dm644x_ids[] = { | |||
| 557 | .cpu_id = DAVINCI_CPU_ID_DM6446, | 660 | .cpu_id = DAVINCI_CPU_ID_DM6446, |
| 558 | .name = "dm6446", | 661 | .name = "dm6446", |
| 559 | }, | 662 | }, |
| 663 | { | ||
| 664 | .variant = 0x1, | ||
| 665 | .part_no = 0xb700, | ||
| 666 | .manufacturer = 0x017, | ||
| 667 | .cpu_id = DAVINCI_CPU_ID_DM6446, | ||
| 668 | .name = "dm6446a", | ||
| 669 | }, | ||
| 560 | }; | 670 | }; |
| 561 | 671 | ||
| 562 | static void __iomem *dm644x_psc_bases[] = { | 672 | static void __iomem *dm644x_psc_bases[] = { |
| @@ -630,7 +740,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { | |||
| 630 | .intc_irq_prios = dm644x_default_priorities, | 740 | .intc_irq_prios = dm644x_default_priorities, |
| 631 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | 741 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, |
| 632 | .timer_info = &dm644x_timer_info, | 742 | .timer_info = &dm644x_timer_info, |
| 633 | .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), | ||
| 634 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), | 743 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), |
| 635 | .gpio_num = 71, | 744 | .gpio_num = 71, |
| 636 | .gpio_irq = IRQ_GPIOBNK0, | 745 | .gpio_irq = IRQ_GPIOBNK0, |
| @@ -640,6 +749,13 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { | |||
| 640 | .sram_len = SZ_16K, | 749 | .sram_len = SZ_16K, |
| 641 | }; | 750 | }; |
| 642 | 751 | ||
| 752 | void __init dm644x_init_asp(struct snd_platform_data *pdata) | ||
| 753 | { | ||
| 754 | davinci_cfg_reg(DM644X_MCBSP); | ||
| 755 | dm644x_asp_device.dev.platform_data = pdata; | ||
| 756 | platform_device_register(&dm644x_asp_device); | ||
| 757 | } | ||
| 758 | |||
| 643 | void __init dm644x_init(void) | 759 | void __init dm644x_init(void) |
| 644 | { | 760 | { |
| 645 | davinci_common_init(&davinci_soc_info_dm644x); | 761 | davinci_common_init(&davinci_soc_info_dm644x); |
| @@ -652,6 +768,9 @@ static int __init dm644x_init_devices(void) | |||
| 652 | 768 | ||
| 653 | platform_device_register(&dm644x_edma_device); | 769 | platform_device_register(&dm644x_edma_device); |
| 654 | platform_device_register(&dm644x_emac_device); | 770 | platform_device_register(&dm644x_emac_device); |
| 771 | platform_device_register(&dm644x_vpss_device); | ||
| 772 | platform_device_register(&vpfe_capture_dev); | ||
| 773 | |||
| 655 | return 0; | 774 | return 0; |
| 656 | } | 775 | } |
| 657 | postcore_initcall(dm644x_init_devices); | 776 | postcore_initcall(dm644x_init_devices); |
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 334f0711e0f5..0976049c7b3b 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c | |||
| @@ -27,10 +27,20 @@ | |||
| 27 | #include <mach/time.h> | 27 | #include <mach/time.h> |
| 28 | #include <mach/serial.h> | 28 | #include <mach/serial.h> |
| 29 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 30 | #include <mach/asp.h> | ||
| 30 | 31 | ||
| 31 | #include "clock.h" | 32 | #include "clock.h" |
| 32 | #include "mux.h" | 33 | #include "mux.h" |
| 33 | 34 | ||
| 35 | #define DAVINCI_VPIF_BASE (0x01C12000) | ||
| 36 | #define VDD3P3V_PWDN_OFFSET (0x48) | ||
| 37 | #define VSCLKDIS_OFFSET (0x6C) | ||
| 38 | |||
| 39 | #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ | ||
| 40 | BIT_MASK(0)) | ||
| 41 | #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ | ||
| 42 | BIT_MASK(8)) | ||
| 43 | |||
| 34 | /* | 44 | /* |
| 35 | * Device specific clocks | 45 | * Device specific clocks |
| 36 | */ | 46 | */ |
| @@ -162,6 +172,41 @@ static struct clk arm_clk = { | |||
| 162 | .flags = ALWAYS_ENABLED, | 172 | .flags = ALWAYS_ENABLED, |
| 163 | }; | 173 | }; |
| 164 | 174 | ||
| 175 | static struct clk edma_cc_clk = { | ||
| 176 | .name = "edma_cc", | ||
| 177 | .parent = &pll1_sysclk2, | ||
| 178 | .lpsc = DM646X_LPSC_TPCC, | ||
| 179 | .flags = ALWAYS_ENABLED, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct clk edma_tc0_clk = { | ||
| 183 | .name = "edma_tc0", | ||
| 184 | .parent = &pll1_sysclk2, | ||
| 185 | .lpsc = DM646X_LPSC_TPTC0, | ||
| 186 | .flags = ALWAYS_ENABLED, | ||
| 187 | }; | ||
| 188 | |||
| 189 | static struct clk edma_tc1_clk = { | ||
| 190 | .name = "edma_tc1", | ||
| 191 | .parent = &pll1_sysclk2, | ||
| 192 | .lpsc = DM646X_LPSC_TPTC1, | ||
| 193 | .flags = ALWAYS_ENABLED, | ||
| 194 | }; | ||
| 195 | |||
| 196 | static struct clk edma_tc2_clk = { | ||
| 197 | .name = "edma_tc2", | ||
| 198 | .parent = &pll1_sysclk2, | ||
| 199 | .lpsc = DM646X_LPSC_TPTC2, | ||
| 200 | .flags = ALWAYS_ENABLED, | ||
| 201 | }; | ||
| 202 | |||
| 203 | static struct clk edma_tc3_clk = { | ||
| 204 | .name = "edma_tc3", | ||
| 205 | .parent = &pll1_sysclk2, | ||
| 206 | .lpsc = DM646X_LPSC_TPTC3, | ||
| 207 | .flags = ALWAYS_ENABLED, | ||
| 208 | }; | ||
| 209 | |||
| 165 | static struct clk uart0_clk = { | 210 | static struct clk uart0_clk = { |
| 166 | .name = "uart0", | 211 | .name = "uart0", |
| 167 | .parent = &aux_clkin, | 212 | .parent = &aux_clkin, |
| @@ -192,6 +237,18 @@ static struct clk gpio_clk = { | |||
| 192 | .lpsc = DM646X_LPSC_GPIO, | 237 | .lpsc = DM646X_LPSC_GPIO, |
| 193 | }; | 238 | }; |
| 194 | 239 | ||
| 240 | static struct clk mcasp0_clk = { | ||
| 241 | .name = "mcasp0", | ||
| 242 | .parent = &pll1_sysclk3, | ||
| 243 | .lpsc = DM646X_LPSC_McASP0, | ||
| 244 | }; | ||
| 245 | |||
| 246 | static struct clk mcasp1_clk = { | ||
| 247 | .name = "mcasp1", | ||
| 248 | .parent = &pll1_sysclk3, | ||
| 249 | .lpsc = DM646X_LPSC_McASP1, | ||
| 250 | }; | ||
| 251 | |||
| 195 | static struct clk aemif_clk = { | 252 | static struct clk aemif_clk = { |
| 196 | .name = "aemif", | 253 | .name = "aemif", |
| 197 | .parent = &pll1_sysclk3, | 254 | .parent = &pll1_sysclk3, |
| @@ -237,6 +294,13 @@ static struct clk timer2_clk = { | |||
| 237 | .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ | 294 | .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ |
| 238 | }; | 295 | }; |
| 239 | 296 | ||
| 297 | |||
| 298 | static struct clk ide_clk = { | ||
| 299 | .name = "ide", | ||
| 300 | .parent = &pll1_sysclk4, | ||
| 301 | .lpsc = DAVINCI_LPSC_ATA, | ||
| 302 | }; | ||
| 303 | |||
| 240 | static struct clk vpif0_clk = { | 304 | static struct clk vpif0_clk = { |
| 241 | .name = "vpif0", | 305 | .name = "vpif0", |
| 242 | .parent = &ref_clk, | 306 | .parent = &ref_clk, |
| @@ -269,11 +333,18 @@ struct davinci_clk dm646x_clks[] = { | |||
| 269 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | 333 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), |
| 270 | CLK(NULL, "dsp", &dsp_clk), | 334 | CLK(NULL, "dsp", &dsp_clk), |
| 271 | CLK(NULL, "arm", &arm_clk), | 335 | CLK(NULL, "arm", &arm_clk), |
| 336 | CLK(NULL, "edma_cc", &edma_cc_clk), | ||
| 337 | CLK(NULL, "edma_tc0", &edma_tc0_clk), | ||
| 338 | CLK(NULL, "edma_tc1", &edma_tc1_clk), | ||
| 339 | CLK(NULL, "edma_tc2", &edma_tc2_clk), | ||
| 340 | CLK(NULL, "edma_tc3", &edma_tc3_clk), | ||
| 272 | CLK(NULL, "uart0", &uart0_clk), | 341 | CLK(NULL, "uart0", &uart0_clk), |
| 273 | CLK(NULL, "uart1", &uart1_clk), | 342 | CLK(NULL, "uart1", &uart1_clk), |
| 274 | CLK(NULL, "uart2", &uart2_clk), | 343 | CLK(NULL, "uart2", &uart2_clk), |
| 275 | CLK("i2c_davinci.1", NULL, &i2c_clk), | 344 | CLK("i2c_davinci.1", NULL, &i2c_clk), |
| 276 | CLK(NULL, "gpio", &gpio_clk), | 345 | CLK(NULL, "gpio", &gpio_clk), |
| 346 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), | ||
| 347 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), | ||
| 277 | CLK(NULL, "aemif", &aemif_clk), | 348 | CLK(NULL, "aemif", &aemif_clk), |
| 278 | CLK("davinci_emac.1", NULL, &emac_clk), | 349 | CLK("davinci_emac.1", NULL, &emac_clk), |
| 279 | CLK(NULL, "pwm0", &pwm0_clk), | 350 | CLK(NULL, "pwm0", &pwm0_clk), |
| @@ -281,6 +352,7 @@ struct davinci_clk dm646x_clks[] = { | |||
| 281 | CLK(NULL, "timer0", &timer0_clk), | 352 | CLK(NULL, "timer0", &timer0_clk), |
| 282 | CLK(NULL, "timer1", &timer1_clk), | 353 | CLK(NULL, "timer1", &timer1_clk), |
| 283 | CLK("watchdog", NULL, &timer2_clk), | 354 | CLK("watchdog", NULL, &timer2_clk), |
| 355 | CLK("palm_bk3710", NULL, &ide_clk), | ||
| 284 | CLK(NULL, "vpif0", &vpif0_clk), | 356 | CLK(NULL, "vpif0", &vpif0_clk), |
| 285 | CLK(NULL, "vpif1", &vpif1_clk), | 357 | CLK(NULL, "vpif1", &vpif1_clk), |
| 286 | CLK(NULL, NULL, NULL), | 358 | CLK(NULL, NULL, NULL), |
| @@ -344,7 +416,7 @@ static struct platform_device dm646x_emac_device = { | |||
| 344 | */ | 416 | */ |
| 345 | static const struct mux_config dm646x_pins[] = { | 417 | static const struct mux_config dm646x_pins[] = { |
| 346 | #ifdef CONFIG_DAVINCI_MUX | 418 | #ifdef CONFIG_DAVINCI_MUX |
| 347 | MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) | 419 | MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) |
| 348 | 420 | ||
| 349 | MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) | 421 | MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) |
| 350 | 422 | ||
| @@ -451,17 +523,43 @@ static const s8 dma_chan_dm646x_no_event[] = { | |||
| 451 | -1 | 523 | -1 |
| 452 | }; | 524 | }; |
| 453 | 525 | ||
| 454 | static struct edma_soc_info dm646x_edma_info = { | 526 | /* Four Transfer Controllers on DM646x */ |
| 455 | .n_channel = 64, | 527 | static const s8 |
| 456 | .n_region = 6, /* 0-1, 4-7 */ | 528 | dm646x_queue_tc_mapping[][2] = { |
| 457 | .n_slot = 512, | 529 | /* {event queue no, TC no} */ |
| 458 | .n_tc = 4, | 530 | {0, 0}, |
| 459 | .noevent = dma_chan_dm646x_no_event, | 531 | {1, 1}, |
| 532 | {2, 2}, | ||
| 533 | {3, 3}, | ||
| 534 | {-1, -1}, | ||
| 535 | }; | ||
| 536 | |||
| 537 | static const s8 | ||
| 538 | dm646x_queue_priority_mapping[][2] = { | ||
| 539 | /* {event queue no, Priority} */ | ||
| 540 | {0, 4}, | ||
| 541 | {1, 0}, | ||
| 542 | {2, 5}, | ||
| 543 | {3, 1}, | ||
| 544 | {-1, -1}, | ||
| 545 | }; | ||
| 546 | |||
| 547 | static struct edma_soc_info dm646x_edma_info[] = { | ||
| 548 | { | ||
| 549 | .n_channel = 64, | ||
| 550 | .n_region = 6, /* 0-1, 4-7 */ | ||
| 551 | .n_slot = 512, | ||
| 552 | .n_tc = 4, | ||
| 553 | .n_cc = 1, | ||
| 554 | .noevent = dma_chan_dm646x_no_event, | ||
| 555 | .queue_tc_mapping = dm646x_queue_tc_mapping, | ||
| 556 | .queue_priority_mapping = dm646x_queue_priority_mapping, | ||
| 557 | }, | ||
| 460 | }; | 558 | }; |
| 461 | 559 | ||
| 462 | static struct resource edma_resources[] = { | 560 | static struct resource edma_resources[] = { |
| 463 | { | 561 | { |
| 464 | .name = "edma_cc", | 562 | .name = "edma_cc0", |
| 465 | .start = 0x01c00000, | 563 | .start = 0x01c00000, |
| 466 | .end = 0x01c00000 + SZ_64K - 1, | 564 | .end = 0x01c00000 + SZ_64K - 1, |
| 467 | .flags = IORESOURCE_MEM, | 565 | .flags = IORESOURCE_MEM, |
| @@ -491,10 +589,12 @@ static struct resource edma_resources[] = { | |||
| 491 | .flags = IORESOURCE_MEM, | 589 | .flags = IORESOURCE_MEM, |
| 492 | }, | 590 | }, |
| 493 | { | 591 | { |
| 592 | .name = "edma0", | ||
| 494 | .start = IRQ_CCINT0, | 593 | .start = IRQ_CCINT0, |
| 495 | .flags = IORESOURCE_IRQ, | 594 | .flags = IORESOURCE_IRQ, |
| 496 | }, | 595 | }, |
| 497 | { | 596 | { |
| 597 | .name = "edma0_err", | ||
| 498 | .start = IRQ_CCERRINT, | 598 | .start = IRQ_CCERRINT, |
| 499 | .flags = IORESOURCE_IRQ, | 599 | .flags = IORESOURCE_IRQ, |
| 500 | }, | 600 | }, |
| @@ -503,12 +603,167 @@ static struct resource edma_resources[] = { | |||
| 503 | 603 | ||
| 504 | static struct platform_device dm646x_edma_device = { | 604 | static struct platform_device dm646x_edma_device = { |
| 505 | .name = "edma", | 605 | .name = "edma", |
| 506 | .id = -1, | 606 | .id = 0, |
| 507 | .dev.platform_data = &dm646x_edma_info, | 607 | .dev.platform_data = dm646x_edma_info, |
| 508 | .num_resources = ARRAY_SIZE(edma_resources), | 608 | .num_resources = ARRAY_SIZE(edma_resources), |
| 509 | .resource = edma_resources, | 609 | .resource = edma_resources, |
| 510 | }; | 610 | }; |
| 511 | 611 | ||
| 612 | static struct resource ide_resources[] = { | ||
| 613 | { | ||
| 614 | .start = DM646X_ATA_REG_BASE, | ||
| 615 | .end = DM646X_ATA_REG_BASE + 0x7ff, | ||
| 616 | .flags = IORESOURCE_MEM, | ||
| 617 | }, | ||
| 618 | { | ||
| 619 | .start = IRQ_DM646X_IDE, | ||
| 620 | .end = IRQ_DM646X_IDE, | ||
| 621 | .flags = IORESOURCE_IRQ, | ||
| 622 | }, | ||
| 623 | }; | ||
| 624 | |||
| 625 | static u64 ide_dma_mask = DMA_BIT_MASK(32); | ||
| 626 | |||
| 627 | static struct platform_device ide_dev = { | ||
| 628 | .name = "palm_bk3710", | ||
| 629 | .id = -1, | ||
| 630 | .resource = ide_resources, | ||
| 631 | .num_resources = ARRAY_SIZE(ide_resources), | ||
| 632 | .dev = { | ||
| 633 | .dma_mask = &ide_dma_mask, | ||
| 634 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 635 | }, | ||
| 636 | }; | ||
| 637 | |||
| 638 | static struct resource dm646x_mcasp0_resources[] = { | ||
| 639 | { | ||
| 640 | .name = "mcasp0", | ||
| 641 | .start = DAVINCI_DM646X_MCASP0_REG_BASE, | ||
| 642 | .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, | ||
| 643 | .flags = IORESOURCE_MEM, | ||
| 644 | }, | ||
| 645 | /* first TX, then RX */ | ||
| 646 | { | ||
| 647 | .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, | ||
| 648 | .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, | ||
| 649 | .flags = IORESOURCE_DMA, | ||
| 650 | }, | ||
| 651 | { | ||
| 652 | .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, | ||
| 653 | .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, | ||
| 654 | .flags = IORESOURCE_DMA, | ||
| 655 | }, | ||
| 656 | }; | ||
| 657 | |||
| 658 | static struct resource dm646x_mcasp1_resources[] = { | ||
| 659 | { | ||
| 660 | .name = "mcasp1", | ||
| 661 | .start = DAVINCI_DM646X_MCASP1_REG_BASE, | ||
| 662 | .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, | ||
| 663 | .flags = IORESOURCE_MEM, | ||
| 664 | }, | ||
| 665 | /* DIT mode, only TX event */ | ||
| 666 | { | ||
| 667 | .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, | ||
| 668 | .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, | ||
| 669 | .flags = IORESOURCE_DMA, | ||
| 670 | }, | ||
| 671 | /* DIT mode, dummy entry */ | ||
| 672 | { | ||
| 673 | .start = -1, | ||
| 674 | .end = -1, | ||
| 675 | .flags = IORESOURCE_DMA, | ||
| 676 | }, | ||
| 677 | }; | ||
| 678 | |||
| 679 | static struct platform_device dm646x_mcasp0_device = { | ||
| 680 | .name = "davinci-mcasp", | ||
| 681 | .id = 0, | ||
| 682 | .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), | ||
| 683 | .resource = dm646x_mcasp0_resources, | ||
| 684 | }; | ||
| 685 | |||
| 686 | static struct platform_device dm646x_mcasp1_device = { | ||
| 687 | .name = "davinci-mcasp", | ||
| 688 | .id = 1, | ||
| 689 | .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), | ||
| 690 | .resource = dm646x_mcasp1_resources, | ||
| 691 | }; | ||
| 692 | |||
| 693 | static struct platform_device dm646x_dit_device = { | ||
| 694 | .name = "spdif-dit", | ||
| 695 | .id = -1, | ||
| 696 | }; | ||
| 697 | |||
| 698 | static u64 vpif_dma_mask = DMA_BIT_MASK(32); | ||
| 699 | |||
| 700 | static struct resource vpif_resource[] = { | ||
| 701 | { | ||
| 702 | .start = DAVINCI_VPIF_BASE, | ||
| 703 | .end = DAVINCI_VPIF_BASE + 0x03ff, | ||
| 704 | .flags = IORESOURCE_MEM, | ||
| 705 | } | ||
| 706 | }; | ||
| 707 | |||
| 708 | static struct platform_device vpif_dev = { | ||
| 709 | .name = "vpif", | ||
| 710 | .id = -1, | ||
| 711 | .dev = { | ||
| 712 | .dma_mask = &vpif_dma_mask, | ||
| 713 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 714 | }, | ||
| 715 | .resource = vpif_resource, | ||
| 716 | .num_resources = ARRAY_SIZE(vpif_resource), | ||
| 717 | }; | ||
| 718 | |||
| 719 | static struct resource vpif_display_resource[] = { | ||
| 720 | { | ||
| 721 | .start = IRQ_DM646X_VP_VERTINT2, | ||
| 722 | .end = IRQ_DM646X_VP_VERTINT2, | ||
| 723 | .flags = IORESOURCE_IRQ, | ||
| 724 | }, | ||
| 725 | { | ||
| 726 | .start = IRQ_DM646X_VP_VERTINT3, | ||
| 727 | .end = IRQ_DM646X_VP_VERTINT3, | ||
| 728 | .flags = IORESOURCE_IRQ, | ||
| 729 | }, | ||
| 730 | }; | ||
| 731 | |||
| 732 | static struct platform_device vpif_display_dev = { | ||
| 733 | .name = "vpif_display", | ||
| 734 | .id = -1, | ||
| 735 | .dev = { | ||
| 736 | .dma_mask = &vpif_dma_mask, | ||
| 737 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 738 | }, | ||
| 739 | .resource = vpif_display_resource, | ||
| 740 | .num_resources = ARRAY_SIZE(vpif_display_resource), | ||
| 741 | }; | ||
| 742 | |||
| 743 | static struct resource vpif_capture_resource[] = { | ||
| 744 | { | ||
| 745 | .start = IRQ_DM646X_VP_VERTINT0, | ||
| 746 | .end = IRQ_DM646X_VP_VERTINT0, | ||
| 747 | .flags = IORESOURCE_IRQ, | ||
| 748 | }, | ||
| 749 | { | ||
| 750 | .start = IRQ_DM646X_VP_VERTINT1, | ||
| 751 | .end = IRQ_DM646X_VP_VERTINT1, | ||
| 752 | .flags = IORESOURCE_IRQ, | ||
| 753 | }, | ||
| 754 | }; | ||
| 755 | |||
| 756 | static struct platform_device vpif_capture_dev = { | ||
| 757 | .name = "vpif_capture", | ||
| 758 | .id = -1, | ||
| 759 | .dev = { | ||
| 760 | .dma_mask = &vpif_dma_mask, | ||
| 761 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 762 | }, | ||
| 763 | .resource = vpif_capture_resource, | ||
| 764 | .num_resources = ARRAY_SIZE(vpif_capture_resource), | ||
| 765 | }; | ||
| 766 | |||
| 512 | /*----------------------------------------------------------------------*/ | 767 | /*----------------------------------------------------------------------*/ |
| 513 | 768 | ||
| 514 | static struct map_desc dm646x_io_desc[] = { | 769 | static struct map_desc dm646x_io_desc[] = { |
| @@ -609,7 +864,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { | |||
| 609 | .intc_irq_prios = dm646x_default_priorities, | 864 | .intc_irq_prios = dm646x_default_priorities, |
| 610 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | 865 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, |
| 611 | .timer_info = &dm646x_timer_info, | 866 | .timer_info = &dm646x_timer_info, |
| 612 | .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), | ||
| 613 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), | 867 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), |
| 614 | .gpio_num = 43, /* Only 33 usable */ | 868 | .gpio_num = 43, /* Only 33 usable */ |
| 615 | .gpio_irq = IRQ_DM646X_GPIOBNK0, | 869 | .gpio_irq = IRQ_DM646X_GPIOBNK0, |
| @@ -619,6 +873,51 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { | |||
| 619 | .sram_len = SZ_32K, | 873 | .sram_len = SZ_32K, |
| 620 | }; | 874 | }; |
| 621 | 875 | ||
| 876 | void __init dm646x_init_ide() | ||
| 877 | { | ||
| 878 | davinci_cfg_reg(DM646X_ATAEN); | ||
| 879 | platform_device_register(&ide_dev); | ||
| 880 | } | ||
| 881 | |||
| 882 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) | ||
| 883 | { | ||
| 884 | dm646x_mcasp0_device.dev.platform_data = pdata; | ||
| 885 | platform_device_register(&dm646x_mcasp0_device); | ||
| 886 | } | ||
| 887 | |||
| 888 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) | ||
| 889 | { | ||
| 890 | dm646x_mcasp1_device.dev.platform_data = pdata; | ||
| 891 | platform_device_register(&dm646x_mcasp1_device); | ||
| 892 | platform_device_register(&dm646x_dit_device); | ||
| 893 | } | ||
| 894 | |||
| 895 | void dm646x_setup_vpif(struct vpif_display_config *display_config, | ||
| 896 | struct vpif_capture_config *capture_config) | ||
| 897 | { | ||
| 898 | unsigned int value; | ||
| 899 | void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); | ||
| 900 | |||
| 901 | value = __raw_readl(base + VSCLKDIS_OFFSET); | ||
| 902 | value &= ~VSCLKDIS_MASK; | ||
| 903 | __raw_writel(value, base + VSCLKDIS_OFFSET); | ||
| 904 | |||
| 905 | value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); | ||
| 906 | value &= ~VDD3P3V_VID_MASK; | ||
| 907 | __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); | ||
| 908 | |||
| 909 | davinci_cfg_reg(DM646X_STSOMUX_DISABLE); | ||
| 910 | davinci_cfg_reg(DM646X_STSIMUX_DISABLE); | ||
| 911 | davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); | ||
| 912 | davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); | ||
| 913 | |||
| 914 | vpif_display_dev.dev.platform_data = display_config; | ||
| 915 | vpif_capture_dev.dev.platform_data = capture_config; | ||
| 916 | platform_device_register(&vpif_dev); | ||
| 917 | platform_device_register(&vpif_display_dev); | ||
| 918 | platform_device_register(&vpif_capture_dev); | ||
| 919 | } | ||
| 920 | |||
| 622 | void __init dm646x_init(void) | 921 | void __init dm646x_init(void) |
| 623 | { | 922 | { |
| 624 | davinci_common_init(&davinci_soc_info_dm646x); | 923 | davinci_common_init(&davinci_soc_info_dm646x); |
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 15e9eb158bb7..f2e57d272958 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c | |||
| @@ -100,132 +100,158 @@ | |||
| 100 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ | 100 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ |
| 101 | #define EDMA_PARM 0x4000 /* 128 param entries */ | 101 | #define EDMA_PARM 0x4000 /* 128 param entries */ |
| 102 | 102 | ||
| 103 | #define DAVINCI_DMA_3PCC_BASE 0x01C00000 | ||
| 104 | |||
| 105 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) | 103 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
| 106 | 104 | ||
| 105 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ | ||
| 106 | #define CHMAP_EXIST BIT(24) | ||
| 107 | |||
| 107 | #define EDMA_MAX_DMACH 64 | 108 | #define EDMA_MAX_DMACH 64 |
| 108 | #define EDMA_MAX_PARAMENTRY 512 | 109 | #define EDMA_MAX_PARAMENTRY 512 |
| 109 | #define EDMA_MAX_EVQUE 2 /* FIXME too small */ | 110 | #define EDMA_MAX_CC 2 |
| 110 | 111 | ||
| 111 | 112 | ||
| 112 | /*****************************************************************************/ | 113 | /*****************************************************************************/ |
| 113 | 114 | ||
| 114 | static void __iomem *edmacc_regs_base; | 115 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
| 115 | 116 | ||
| 116 | static inline unsigned int edma_read(int offset) | 117 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
| 117 | { | 118 | { |
| 118 | return (unsigned int)__raw_readl(edmacc_regs_base + offset); | 119 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
| 119 | } | 120 | } |
| 120 | 121 | ||
| 121 | static inline void edma_write(int offset, int val) | 122 | static inline void edma_write(unsigned ctlr, int offset, int val) |
| 122 | { | 123 | { |
| 123 | __raw_writel(val, edmacc_regs_base + offset); | 124 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
| 124 | } | 125 | } |
| 125 | static inline void edma_modify(int offset, unsigned and, unsigned or) | 126 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
| 127 | unsigned or) | ||
| 126 | { | 128 | { |
| 127 | unsigned val = edma_read(offset); | 129 | unsigned val = edma_read(ctlr, offset); |
| 128 | val &= and; | 130 | val &= and; |
| 129 | val |= or; | 131 | val |= or; |
| 130 | edma_write(offset, val); | 132 | edma_write(ctlr, offset, val); |
| 131 | } | 133 | } |
| 132 | static inline void edma_and(int offset, unsigned and) | 134 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
| 133 | { | 135 | { |
| 134 | unsigned val = edma_read(offset); | 136 | unsigned val = edma_read(ctlr, offset); |
| 135 | val &= and; | 137 | val &= and; |
| 136 | edma_write(offset, val); | 138 | edma_write(ctlr, offset, val); |
| 137 | } | 139 | } |
| 138 | static inline void edma_or(int offset, unsigned or) | 140 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
| 139 | { | 141 | { |
| 140 | unsigned val = edma_read(offset); | 142 | unsigned val = edma_read(ctlr, offset); |
| 141 | val |= or; | 143 | val |= or; |
| 142 | edma_write(offset, val); | 144 | edma_write(ctlr, offset, val); |
| 143 | } | 145 | } |
| 144 | static inline unsigned int edma_read_array(int offset, int i) | 146 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
| 145 | { | 147 | { |
| 146 | return edma_read(offset + (i << 2)); | 148 | return edma_read(ctlr, offset + (i << 2)); |
| 147 | } | 149 | } |
| 148 | static inline void edma_write_array(int offset, int i, unsigned val) | 150 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
| 151 | unsigned val) | ||
| 149 | { | 152 | { |
| 150 | edma_write(offset + (i << 2), val); | 153 | edma_write(ctlr, offset + (i << 2), val); |
| 151 | } | 154 | } |
| 152 | static inline void edma_modify_array(int offset, int i, | 155 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
| 153 | unsigned and, unsigned or) | 156 | unsigned and, unsigned or) |
| 154 | { | 157 | { |
| 155 | edma_modify(offset + (i << 2), and, or); | 158 | edma_modify(ctlr, offset + (i << 2), and, or); |
| 156 | } | 159 | } |
| 157 | static inline void edma_or_array(int offset, int i, unsigned or) | 160 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
| 158 | { | 161 | { |
| 159 | edma_or(offset + (i << 2), or); | 162 | edma_or(ctlr, offset + (i << 2), or); |
| 160 | } | 163 | } |
| 161 | static inline void edma_or_array2(int offset, int i, int j, unsigned or) | 164 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
| 165 | unsigned or) | ||
| 162 | { | 166 | { |
| 163 | edma_or(offset + ((i*2 + j) << 2), or); | 167 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
| 164 | } | 168 | } |
| 165 | static inline void edma_write_array2(int offset, int i, int j, unsigned val) | 169 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
| 170 | unsigned val) | ||
| 166 | { | 171 | { |
| 167 | edma_write(offset + ((i*2 + j) << 2), val); | 172 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
| 168 | } | 173 | } |
| 169 | static inline unsigned int edma_shadow0_read(int offset) | 174 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
| 170 | { | 175 | { |
| 171 | return edma_read(EDMA_SHADOW0 + offset); | 176 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
| 172 | } | 177 | } |
| 173 | static inline unsigned int edma_shadow0_read_array(int offset, int i) | 178 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
| 179 | int i) | ||
| 174 | { | 180 | { |
| 175 | return edma_read(EDMA_SHADOW0 + offset + (i << 2)); | 181 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
| 176 | } | 182 | } |
| 177 | static inline void edma_shadow0_write(int offset, unsigned val) | 183 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
| 178 | { | 184 | { |
| 179 | edma_write(EDMA_SHADOW0 + offset, val); | 185 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
| 180 | } | 186 | } |
| 181 | static inline void edma_shadow0_write_array(int offset, int i, unsigned val) | 187 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
| 188 | unsigned val) | ||
| 182 | { | 189 | { |
| 183 | edma_write(EDMA_SHADOW0 + offset + (i << 2), val); | 190 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
| 184 | } | 191 | } |
| 185 | static inline unsigned int edma_parm_read(int offset, int param_no) | 192 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
| 193 | int param_no) | ||
| 186 | { | 194 | { |
| 187 | return edma_read(EDMA_PARM + offset + (param_no << 5)); | 195 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
| 188 | } | 196 | } |
| 189 | static inline void edma_parm_write(int offset, int param_no, unsigned val) | 197 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
| 198 | unsigned val) | ||
| 190 | { | 199 | { |
| 191 | edma_write(EDMA_PARM + offset + (param_no << 5), val); | 200 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
| 192 | } | 201 | } |
| 193 | static inline void edma_parm_modify(int offset, int param_no, | 202 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
| 194 | unsigned and, unsigned or) | 203 | unsigned and, unsigned or) |
| 195 | { | 204 | { |
| 196 | edma_modify(EDMA_PARM + offset + (param_no << 5), and, or); | 205 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
| 197 | } | 206 | } |
| 198 | static inline void edma_parm_and(int offset, int param_no, unsigned and) | 207 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
| 208 | unsigned and) | ||
| 199 | { | 209 | { |
| 200 | edma_and(EDMA_PARM + offset + (param_no << 5), and); | 210 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
| 201 | } | 211 | } |
| 202 | static inline void edma_parm_or(int offset, int param_no, unsigned or) | 212 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
| 213 | unsigned or) | ||
| 203 | { | 214 | { |
| 204 | edma_or(EDMA_PARM + offset + (param_no << 5), or); | 215 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
| 205 | } | 216 | } |
| 206 | 217 | ||
| 207 | /*****************************************************************************/ | 218 | /*****************************************************************************/ |
| 208 | 219 | ||
| 209 | /* actual number of DMA channels and slots on this silicon */ | 220 | /* actual number of DMA channels and slots on this silicon */ |
| 210 | static unsigned num_channels; | 221 | struct edma { |
| 211 | static unsigned num_slots; | 222 | /* how many dma resources of each type */ |
| 223 | unsigned num_channels; | ||
| 224 | unsigned num_region; | ||
| 225 | unsigned num_slots; | ||
| 226 | unsigned num_tc; | ||
| 227 | unsigned num_cc; | ||
| 228 | enum dma_event_q default_queue; | ||
| 229 | |||
| 230 | /* list of channels with no even trigger; terminated by "-1" */ | ||
| 231 | const s8 *noevent; | ||
| 232 | |||
| 233 | /* The edma_inuse bit for each PaRAM slot is clear unless the | ||
| 234 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | ||
| 235 | */ | ||
| 236 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | ||
| 212 | 237 | ||
| 213 | static struct dma_interrupt_data { | 238 | /* The edma_noevent bit for each channel is clear unless |
| 214 | void (*callback)(unsigned channel, unsigned short ch_status, | 239 | * it doesn't trigger DMA events on this platform. It uses a |
| 215 | void *data); | 240 | * bit of SOC-specific initialization code. |
| 216 | void *data; | 241 | */ |
| 217 | } intr_data[EDMA_MAX_DMACH]; | 242 | DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); |
| 218 | 243 | ||
| 219 | /* The edma_inuse bit for each PaRAM slot is clear unless the | 244 | unsigned irq_res_start; |
| 220 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | 245 | unsigned irq_res_end; |
| 221 | */ | ||
| 222 | static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | ||
| 223 | 246 | ||
| 224 | /* The edma_noevent bit for each channel is clear unless | 247 | struct dma_interrupt_data { |
| 225 | * it doesn't trigger DMA events on this platform. It uses a | 248 | void (*callback)(unsigned channel, unsigned short ch_status, |
| 226 | * bit of SOC-specific initialization code. | 249 | void *data); |
| 227 | */ | 250 | void *data; |
| 228 | static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); | 251 | } intr_data[EDMA_MAX_DMACH]; |
| 252 | }; | ||
| 253 | |||
| 254 | static struct edma *edma_info[EDMA_MAX_CC]; | ||
| 229 | 255 | ||
| 230 | /* dummy param set used to (re)initialize parameter RAM slots */ | 256 | /* dummy param set used to (re)initialize parameter RAM slots */ |
| 231 | static const struct edmacc_param dummy_paramset = { | 257 | static const struct edmacc_param dummy_paramset = { |
| @@ -233,47 +259,52 @@ static const struct edmacc_param dummy_paramset = { | |||
| 233 | .ccnt = 1, | 259 | .ccnt = 1, |
| 234 | }; | 260 | }; |
| 235 | 261 | ||
| 236 | static const int __initconst | ||
| 237 | queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { | ||
| 238 | /* {event queue no, TC no} */ | ||
| 239 | {0, 0}, | ||
| 240 | {1, 1}, | ||
| 241 | {-1, -1} | ||
| 242 | }; | ||
| 243 | |||
| 244 | static const int __initconst | ||
| 245 | queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { | ||
| 246 | /* {event queue no, Priority} */ | ||
| 247 | {0, 3}, | ||
| 248 | {1, 7}, | ||
| 249 | {-1, -1} | ||
| 250 | }; | ||
| 251 | |||
| 252 | /*****************************************************************************/ | 262 | /*****************************************************************************/ |
| 253 | 263 | ||
| 254 | static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no) | 264 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
| 265 | enum dma_event_q queue_no) | ||
| 255 | { | 266 | { |
| 256 | int bit = (ch_no & 0x7) * 4; | 267 | int bit = (ch_no & 0x7) * 4; |
| 257 | 268 | ||
| 258 | /* default to low priority queue */ | 269 | /* default to low priority queue */ |
| 259 | if (queue_no == EVENTQ_DEFAULT) | 270 | if (queue_no == EVENTQ_DEFAULT) |
| 260 | queue_no = EVENTQ_1; | 271 | queue_no = edma_info[ctlr]->default_queue; |
| 261 | 272 | ||
| 262 | queue_no &= 7; | 273 | queue_no &= 7; |
| 263 | edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3), | 274 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
| 264 | ~(0x7 << bit), queue_no << bit); | 275 | ~(0x7 << bit), queue_no << bit); |
| 265 | } | 276 | } |
| 266 | 277 | ||
| 267 | static void __init map_queue_tc(int queue_no, int tc_no) | 278 | static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) |
| 268 | { | 279 | { |
| 269 | int bit = queue_no * 4; | 280 | int bit = queue_no * 4; |
| 270 | edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); | 281 | edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); |
| 271 | } | 282 | } |
| 272 | 283 | ||
| 273 | static void __init assign_priority_to_queue(int queue_no, int priority) | 284 | static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, |
| 285 | int priority) | ||
| 274 | { | 286 | { |
| 275 | int bit = queue_no * 4; | 287 | int bit = queue_no * 4; |
| 276 | edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); | 288 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
| 289 | ((priority & 0x7) << bit)); | ||
| 290 | } | ||
| 291 | |||
| 292 | /** | ||
| 293 | * map_dmach_param - Maps channel number to param entry number | ||
| 294 | * | ||
| 295 | * This maps the dma channel number to param entry numberter. In | ||
| 296 | * other words using the DMA channel mapping registers a param entry | ||
| 297 | * can be mapped to any channel | ||
| 298 | * | ||
| 299 | * Callers are responsible for ensuring the channel mapping logic is | ||
| 300 | * included in that particular EDMA variant (Eg : dm646x) | ||
| 301 | * | ||
| 302 | */ | ||
| 303 | static void __init map_dmach_param(unsigned ctlr) | ||
| 304 | { | ||
| 305 | int i; | ||
| 306 | for (i = 0; i < EDMA_MAX_DMACH; i++) | ||
| 307 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); | ||
| 277 | } | 308 | } |
| 278 | 309 | ||
| 279 | static inline void | 310 | static inline void |
| @@ -281,22 +312,39 @@ setup_dma_interrupt(unsigned lch, | |||
| 281 | void (*callback)(unsigned channel, u16 ch_status, void *data), | 312 | void (*callback)(unsigned channel, u16 ch_status, void *data), |
| 282 | void *data) | 313 | void *data) |
| 283 | { | 314 | { |
| 315 | unsigned ctlr; | ||
| 316 | |||
| 317 | ctlr = EDMA_CTLR(lch); | ||
| 318 | lch = EDMA_CHAN_SLOT(lch); | ||
| 319 | |||
| 284 | if (!callback) { | 320 | if (!callback) { |
| 285 | edma_shadow0_write_array(SH_IECR, lch >> 5, | 321 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
| 286 | (1 << (lch & 0x1f))); | 322 | (1 << (lch & 0x1f))); |
| 287 | } | 323 | } |
| 288 | 324 | ||
| 289 | intr_data[lch].callback = callback; | 325 | edma_info[ctlr]->intr_data[lch].callback = callback; |
| 290 | intr_data[lch].data = data; | 326 | edma_info[ctlr]->intr_data[lch].data = data; |
| 291 | 327 | ||
| 292 | if (callback) { | 328 | if (callback) { |
| 293 | edma_shadow0_write_array(SH_ICR, lch >> 5, | 329 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
| 294 | (1 << (lch & 0x1f))); | 330 | (1 << (lch & 0x1f))); |
| 295 | edma_shadow0_write_array(SH_IESR, lch >> 5, | 331 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
| 296 | (1 << (lch & 0x1f))); | 332 | (1 << (lch & 0x1f))); |
| 297 | } | 333 | } |
| 298 | } | 334 | } |
| 299 | 335 | ||
| 336 | static int irq2ctlr(int irq) | ||
| 337 | { | ||
| 338 | if (irq >= edma_info[0]->irq_res_start && | ||
| 339 | irq <= edma_info[0]->irq_res_end) | ||
| 340 | return 0; | ||
| 341 | else if (irq >= edma_info[1]->irq_res_start && | ||
| 342 | irq <= edma_info[1]->irq_res_end) | ||
| 343 | return 1; | ||
| 344 | |||
| 345 | return -1; | ||
| 346 | } | ||
| 347 | |||
| 300 | /****************************************************************************** | 348 | /****************************************************************************** |
| 301 | * | 349 | * |
| 302 | * DMA interrupt handler | 350 | * DMA interrupt handler |
| @@ -305,32 +353,39 @@ setup_dma_interrupt(unsigned lch, | |||
| 305 | static irqreturn_t dma_irq_handler(int irq, void *data) | 353 | static irqreturn_t dma_irq_handler(int irq, void *data) |
| 306 | { | 354 | { |
| 307 | int i; | 355 | int i; |
| 356 | unsigned ctlr; | ||
| 308 | unsigned int cnt = 0; | 357 | unsigned int cnt = 0; |
| 309 | 358 | ||
| 359 | ctlr = irq2ctlr(irq); | ||
| 360 | |||
| 310 | dev_dbg(data, "dma_irq_handler\n"); | 361 | dev_dbg(data, "dma_irq_handler\n"); |
| 311 | 362 | ||
| 312 | if ((edma_shadow0_read_array(SH_IPR, 0) == 0) | 363 | if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) |
| 313 | && (edma_shadow0_read_array(SH_IPR, 1) == 0)) | 364 | && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) |
| 314 | return IRQ_NONE; | 365 | return IRQ_NONE; |
| 315 | 366 | ||
| 316 | while (1) { | 367 | while (1) { |
| 317 | int j; | 368 | int j; |
| 318 | if (edma_shadow0_read_array(SH_IPR, 0)) | 369 | if (edma_shadow0_read_array(ctlr, SH_IPR, 0)) |
| 319 | j = 0; | 370 | j = 0; |
| 320 | else if (edma_shadow0_read_array(SH_IPR, 1)) | 371 | else if (edma_shadow0_read_array(ctlr, SH_IPR, 1)) |
| 321 | j = 1; | 372 | j = 1; |
| 322 | else | 373 | else |
| 323 | break; | 374 | break; |
| 324 | dev_dbg(data, "IPR%d %08x\n", j, | 375 | dev_dbg(data, "IPR%d %08x\n", j, |
| 325 | edma_shadow0_read_array(SH_IPR, j)); | 376 | edma_shadow0_read_array(ctlr, SH_IPR, j)); |
| 326 | for (i = 0; i < 32; i++) { | 377 | for (i = 0; i < 32; i++) { |
| 327 | int k = (j << 5) + i; | 378 | int k = (j << 5) + i; |
| 328 | if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) { | 379 | if (edma_shadow0_read_array(ctlr, SH_IPR, j) & |
| 380 | (1 << i)) { | ||
| 329 | /* Clear the corresponding IPR bits */ | 381 | /* Clear the corresponding IPR bits */ |
| 330 | edma_shadow0_write_array(SH_ICR, j, (1 << i)); | 382 | edma_shadow0_write_array(ctlr, SH_ICR, j, |
| 331 | if (intr_data[k].callback) { | 383 | (1 << i)); |
| 332 | intr_data[k].callback(k, DMA_COMPLETE, | 384 | if (edma_info[ctlr]->intr_data[k].callback) { |
| 333 | intr_data[k].data); | 385 | edma_info[ctlr]->intr_data[k].callback( |
| 386 | k, DMA_COMPLETE, | ||
| 387 | edma_info[ctlr]->intr_data[k]. | ||
| 388 | data); | ||
| 334 | } | 389 | } |
| 335 | } | 390 | } |
| 336 | } | 391 | } |
| @@ -338,7 +393,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) | |||
| 338 | if (cnt > 10) | 393 | if (cnt > 10) |
| 339 | break; | 394 | break; |
| 340 | } | 395 | } |
| 341 | edma_shadow0_write(SH_IEVAL, 1); | 396 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
| 342 | return IRQ_HANDLED; | 397 | return IRQ_HANDLED; |
| 343 | } | 398 | } |
| 344 | 399 | ||
| @@ -350,78 +405,87 @@ static irqreturn_t dma_irq_handler(int irq, void *data) | |||
| 350 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | 405 | static irqreturn_t dma_ccerr_handler(int irq, void *data) |
| 351 | { | 406 | { |
| 352 | int i; | 407 | int i; |
| 408 | unsigned ctlr; | ||
| 353 | unsigned int cnt = 0; | 409 | unsigned int cnt = 0; |
| 354 | 410 | ||
| 411 | ctlr = irq2ctlr(irq); | ||
| 412 | |||
| 355 | dev_dbg(data, "dma_ccerr_handler\n"); | 413 | dev_dbg(data, "dma_ccerr_handler\n"); |
| 356 | 414 | ||
| 357 | if ((edma_read_array(EDMA_EMR, 0) == 0) && | 415 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
| 358 | (edma_read_array(EDMA_EMR, 1) == 0) && | 416 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && |
| 359 | (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0)) | 417 | (edma_read(ctlr, EDMA_QEMR) == 0) && |
| 418 | (edma_read(ctlr, EDMA_CCERR) == 0)) | ||
| 360 | return IRQ_NONE; | 419 | return IRQ_NONE; |
| 361 | 420 | ||
| 362 | while (1) { | 421 | while (1) { |
| 363 | int j = -1; | 422 | int j = -1; |
| 364 | if (edma_read_array(EDMA_EMR, 0)) | 423 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
| 365 | j = 0; | 424 | j = 0; |
| 366 | else if (edma_read_array(EDMA_EMR, 1)) | 425 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
| 367 | j = 1; | 426 | j = 1; |
| 368 | if (j >= 0) { | 427 | if (j >= 0) { |
| 369 | dev_dbg(data, "EMR%d %08x\n", j, | 428 | dev_dbg(data, "EMR%d %08x\n", j, |
| 370 | edma_read_array(EDMA_EMR, j)); | 429 | edma_read_array(ctlr, EDMA_EMR, j)); |
| 371 | for (i = 0; i < 32; i++) { | 430 | for (i = 0; i < 32; i++) { |
| 372 | int k = (j << 5) + i; | 431 | int k = (j << 5) + i; |
| 373 | if (edma_read_array(EDMA_EMR, j) & (1 << i)) { | 432 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
| 433 | (1 << i)) { | ||
| 374 | /* Clear the corresponding EMR bits */ | 434 | /* Clear the corresponding EMR bits */ |
| 375 | edma_write_array(EDMA_EMCR, j, 1 << i); | 435 | edma_write_array(ctlr, EDMA_EMCR, j, |
| 436 | 1 << i); | ||
| 376 | /* Clear any SER */ | 437 | /* Clear any SER */ |
| 377 | edma_shadow0_write_array(SH_SECR, j, | 438 | edma_shadow0_write_array(ctlr, SH_SECR, |
| 378 | (1 << i)); | 439 | j, (1 << i)); |
| 379 | if (intr_data[k].callback) { | 440 | if (edma_info[ctlr]->intr_data[k]. |
| 380 | intr_data[k].callback(k, | 441 | callback) { |
| 381 | DMA_CC_ERROR, | 442 | edma_info[ctlr]->intr_data[k]. |
| 382 | intr_data | 443 | callback(k, |
| 383 | [k].data); | 444 | DMA_CC_ERROR, |
| 445 | edma_info[ctlr]->intr_data | ||
| 446 | [k].data); | ||
| 384 | } | 447 | } |
| 385 | } | 448 | } |
| 386 | } | 449 | } |
| 387 | } else if (edma_read(EDMA_QEMR)) { | 450 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
| 388 | dev_dbg(data, "QEMR %02x\n", | 451 | dev_dbg(data, "QEMR %02x\n", |
| 389 | edma_read(EDMA_QEMR)); | 452 | edma_read(ctlr, EDMA_QEMR)); |
| 390 | for (i = 0; i < 8; i++) { | 453 | for (i = 0; i < 8; i++) { |
| 391 | if (edma_read(EDMA_QEMR) & (1 << i)) { | 454 | if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { |
| 392 | /* Clear the corresponding IPR bits */ | 455 | /* Clear the corresponding IPR bits */ |
| 393 | edma_write(EDMA_QEMCR, 1 << i); | 456 | edma_write(ctlr, EDMA_QEMCR, 1 << i); |
| 394 | edma_shadow0_write(SH_QSECR, (1 << i)); | 457 | edma_shadow0_write(ctlr, SH_QSECR, |
| 458 | (1 << i)); | ||
| 395 | 459 | ||
| 396 | /* NOTE: not reported!! */ | 460 | /* NOTE: not reported!! */ |
| 397 | } | 461 | } |
| 398 | } | 462 | } |
| 399 | } else if (edma_read(EDMA_CCERR)) { | 463 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
| 400 | dev_dbg(data, "CCERR %08x\n", | 464 | dev_dbg(data, "CCERR %08x\n", |
| 401 | edma_read(EDMA_CCERR)); | 465 | edma_read(ctlr, EDMA_CCERR)); |
| 402 | /* FIXME: CCERR.BIT(16) ignored! much better | 466 | /* FIXME: CCERR.BIT(16) ignored! much better |
| 403 | * to just write CCERRCLR with CCERR value... | 467 | * to just write CCERRCLR with CCERR value... |
| 404 | */ | 468 | */ |
| 405 | for (i = 0; i < 8; i++) { | 469 | for (i = 0; i < 8; i++) { |
| 406 | if (edma_read(EDMA_CCERR) & (1 << i)) { | 470 | if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { |
| 407 | /* Clear the corresponding IPR bits */ | 471 | /* Clear the corresponding IPR bits */ |
| 408 | edma_write(EDMA_CCERRCLR, 1 << i); | 472 | edma_write(ctlr, EDMA_CCERRCLR, 1 << i); |
| 409 | 473 | ||
| 410 | /* NOTE: not reported!! */ | 474 | /* NOTE: not reported!! */ |
| 411 | } | 475 | } |
| 412 | } | 476 | } |
| 413 | } | 477 | } |
| 414 | if ((edma_read_array(EDMA_EMR, 0) == 0) | 478 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) |
| 415 | && (edma_read_array(EDMA_EMR, 1) == 0) | 479 | && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) |
| 416 | && (edma_read(EDMA_QEMR) == 0) | 480 | && (edma_read(ctlr, EDMA_QEMR) == 0) |
| 417 | && (edma_read(EDMA_CCERR) == 0)) { | 481 | && (edma_read(ctlr, EDMA_CCERR) == 0)) { |
| 418 | break; | 482 | break; |
| 419 | } | 483 | } |
| 420 | cnt++; | 484 | cnt++; |
| 421 | if (cnt > 10) | 485 | if (cnt > 10) |
| 422 | break; | 486 | break; |
| 423 | } | 487 | } |
| 424 | edma_write(EDMA_EEVAL, 1); | 488 | edma_write(ctlr, EDMA_EEVAL, 1); |
| 425 | return IRQ_HANDLED; | 489 | return IRQ_HANDLED; |
| 426 | } | 490 | } |
| 427 | 491 | ||
| @@ -445,6 +509,45 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data) | |||
| 445 | return IRQ_HANDLED; | 509 | return IRQ_HANDLED; |
| 446 | } | 510 | } |
| 447 | 511 | ||
| 512 | static int reserve_contiguous_params(int ctlr, unsigned int id, | ||
| 513 | unsigned int num_params, | ||
| 514 | unsigned int start_param) | ||
| 515 | { | ||
| 516 | int i, j; | ||
| 517 | unsigned int count = num_params; | ||
| 518 | |||
| 519 | for (i = start_param; i < edma_info[ctlr]->num_slots; ++i) { | ||
| 520 | j = EDMA_CHAN_SLOT(i); | ||
| 521 | if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) | ||
| 522 | count--; | ||
| 523 | if (count == 0) | ||
| 524 | break; | ||
| 525 | else if (id == EDMA_CONT_PARAMS_FIXED_EXACT) | ||
| 526 | break; | ||
| 527 | else | ||
| 528 | count = num_params; | ||
| 529 | } | ||
| 530 | |||
| 531 | /* | ||
| 532 | * We have to clear any bits that we set | ||
| 533 | * if we run out parameter RAMs, i.e we do find a set | ||
| 534 | * of contiguous parameter RAMs but do not find the exact number | ||
| 535 | * requested as we may reach the total number of parameter RAMs | ||
| 536 | */ | ||
| 537 | if (count) { | ||
| 538 | for (j = i - num_params + count + 1; j <= i ; ++j) | ||
| 539 | clear_bit(j, edma_info[ctlr]->edma_inuse); | ||
| 540 | |||
| 541 | return -EBUSY; | ||
| 542 | } | ||
| 543 | |||
| 544 | for (j = i - num_params + 1; j <= i; ++j) | ||
| 545 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), | ||
| 546 | &dummy_paramset, PARM_SIZE); | ||
| 547 | |||
| 548 | return EDMA_CTLR_CHAN(ctlr, i - num_params + 1); | ||
| 549 | } | ||
| 550 | |||
| 448 | /*-----------------------------------------------------------------------*/ | 551 | /*-----------------------------------------------------------------------*/ |
| 449 | 552 | ||
| 450 | /* Resource alloc/free: dma channels, parameter RAM slots */ | 553 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
| @@ -484,35 +587,53 @@ int edma_alloc_channel(int channel, | |||
| 484 | void *data, | 587 | void *data, |
| 485 | enum dma_event_q eventq_no) | 588 | enum dma_event_q eventq_no) |
| 486 | { | 589 | { |
| 590 | unsigned i, done, ctlr = 0; | ||
| 591 | |||
| 592 | if (channel >= 0) { | ||
| 593 | ctlr = EDMA_CTLR(channel); | ||
| 594 | channel = EDMA_CHAN_SLOT(channel); | ||
| 595 | } | ||
| 596 | |||
| 487 | if (channel < 0) { | 597 | if (channel < 0) { |
| 488 | channel = 0; | 598 | for (i = 0; i < EDMA_MAX_CC; i++) { |
| 489 | for (;;) { | 599 | channel = 0; |
| 490 | channel = find_next_bit(edma_noevent, | 600 | for (;;) { |
| 491 | num_channels, channel); | 601 | channel = find_next_bit(edma_info[i]-> |
| 492 | if (channel == num_channels) | 602 | edma_noevent, |
| 493 | return -ENOMEM; | 603 | edma_info[i]->num_channels, |
| 494 | if (!test_and_set_bit(channel, edma_inuse)) | 604 | channel); |
| 605 | if (channel == edma_info[i]->num_channels) | ||
| 606 | return -ENOMEM; | ||
| 607 | if (!test_and_set_bit(channel, | ||
| 608 | edma_info[i]->edma_inuse)) { | ||
| 609 | done = 1; | ||
| 610 | ctlr = i; | ||
| 611 | break; | ||
| 612 | } | ||
| 613 | channel++; | ||
| 614 | } | ||
| 615 | if (done) | ||
| 495 | break; | 616 | break; |
| 496 | channel++; | ||
| 497 | } | 617 | } |
| 498 | } else if (channel >= num_channels) { | 618 | } else if (channel >= edma_info[ctlr]->num_channels) { |
| 499 | return -EINVAL; | 619 | return -EINVAL; |
| 500 | } else if (test_and_set_bit(channel, edma_inuse)) { | 620 | } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { |
| 501 | return -EBUSY; | 621 | return -EBUSY; |
| 502 | } | 622 | } |
| 503 | 623 | ||
| 504 | /* ensure access through shadow region 0 */ | 624 | /* ensure access through shadow region 0 */ |
| 505 | edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); | 625 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); |
| 506 | 626 | ||
| 507 | /* ensure no events are pending */ | 627 | /* ensure no events are pending */ |
| 508 | edma_stop(channel); | 628 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
| 509 | memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), | 629 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
| 510 | &dummy_paramset, PARM_SIZE); | 630 | &dummy_paramset, PARM_SIZE); |
| 511 | 631 | ||
| 512 | if (callback) | 632 | if (callback) |
| 513 | setup_dma_interrupt(channel, callback, data); | 633 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
| 634 | callback, data); | ||
| 514 | 635 | ||
| 515 | map_dmach_queue(channel, eventq_no); | 636 | map_dmach_queue(ctlr, channel, eventq_no); |
| 516 | 637 | ||
| 517 | return channel; | 638 | return channel; |
| 518 | } | 639 | } |
| @@ -532,15 +653,20 @@ EXPORT_SYMBOL(edma_alloc_channel); | |||
| 532 | */ | 653 | */ |
| 533 | void edma_free_channel(unsigned channel) | 654 | void edma_free_channel(unsigned channel) |
| 534 | { | 655 | { |
| 535 | if (channel >= num_channels) | 656 | unsigned ctlr; |
| 657 | |||
| 658 | ctlr = EDMA_CTLR(channel); | ||
| 659 | channel = EDMA_CHAN_SLOT(channel); | ||
| 660 | |||
| 661 | if (channel >= edma_info[ctlr]->num_channels) | ||
| 536 | return; | 662 | return; |
| 537 | 663 | ||
| 538 | setup_dma_interrupt(channel, NULL, NULL); | 664 | setup_dma_interrupt(channel, NULL, NULL); |
| 539 | /* REVISIT should probably take out of shadow region 0 */ | 665 | /* REVISIT should probably take out of shadow region 0 */ |
| 540 | 666 | ||
| 541 | memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), | 667 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
| 542 | &dummy_paramset, PARM_SIZE); | 668 | &dummy_paramset, PARM_SIZE); |
| 543 | clear_bit(channel, edma_inuse); | 669 | clear_bit(channel, edma_info[ctlr]->edma_inuse); |
| 544 | } | 670 | } |
| 545 | EXPORT_SYMBOL(edma_free_channel); | 671 | EXPORT_SYMBOL(edma_free_channel); |
| 546 | 672 | ||
| @@ -558,28 +684,33 @@ EXPORT_SYMBOL(edma_free_channel); | |||
| 558 | * | 684 | * |
| 559 | * Returns the number of the slot, else negative errno. | 685 | * Returns the number of the slot, else negative errno. |
| 560 | */ | 686 | */ |
| 561 | int edma_alloc_slot(int slot) | 687 | int edma_alloc_slot(unsigned ctlr, int slot) |
| 562 | { | 688 | { |
| 689 | if (slot >= 0) | ||
| 690 | slot = EDMA_CHAN_SLOT(slot); | ||
| 691 | |||
| 563 | if (slot < 0) { | 692 | if (slot < 0) { |
| 564 | slot = num_channels; | 693 | slot = edma_info[ctlr]->num_channels; |
| 565 | for (;;) { | 694 | for (;;) { |
| 566 | slot = find_next_zero_bit(edma_inuse, | 695 | slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, |
| 567 | num_slots, slot); | 696 | edma_info[ctlr]->num_slots, slot); |
| 568 | if (slot == num_slots) | 697 | if (slot == edma_info[ctlr]->num_slots) |
| 569 | return -ENOMEM; | 698 | return -ENOMEM; |
| 570 | if (!test_and_set_bit(slot, edma_inuse)) | 699 | if (!test_and_set_bit(slot, |
| 700 | edma_info[ctlr]->edma_inuse)) | ||
| 571 | break; | 701 | break; |
| 572 | } | 702 | } |
| 573 | } else if (slot < num_channels || slot >= num_slots) { | 703 | } else if (slot < edma_info[ctlr]->num_channels || |
| 704 | slot >= edma_info[ctlr]->num_slots) { | ||
| 574 | return -EINVAL; | 705 | return -EINVAL; |
| 575 | } else if (test_and_set_bit(slot, edma_inuse)) { | 706 | } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { |
| 576 | return -EBUSY; | 707 | return -EBUSY; |
| 577 | } | 708 | } |
| 578 | 709 | ||
| 579 | memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), | 710 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
| 580 | &dummy_paramset, PARM_SIZE); | 711 | &dummy_paramset, PARM_SIZE); |
| 581 | 712 | ||
| 582 | return slot; | 713 | return EDMA_CTLR_CHAN(ctlr, slot); |
| 583 | } | 714 | } |
| 584 | EXPORT_SYMBOL(edma_alloc_slot); | 715 | EXPORT_SYMBOL(edma_alloc_slot); |
| 585 | 716 | ||
| @@ -593,15 +724,119 @@ EXPORT_SYMBOL(edma_alloc_slot); | |||
| 593 | */ | 724 | */ |
| 594 | void edma_free_slot(unsigned slot) | 725 | void edma_free_slot(unsigned slot) |
| 595 | { | 726 | { |
| 596 | if (slot < num_channels || slot >= num_slots) | 727 | unsigned ctlr; |
| 728 | |||
| 729 | ctlr = EDMA_CTLR(slot); | ||
| 730 | slot = EDMA_CHAN_SLOT(slot); | ||
| 731 | |||
| 732 | if (slot < edma_info[ctlr]->num_channels || | ||
| 733 | slot >= edma_info[ctlr]->num_slots) | ||
| 597 | return; | 734 | return; |
| 598 | 735 | ||
| 599 | memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), | 736 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
| 600 | &dummy_paramset, PARM_SIZE); | 737 | &dummy_paramset, PARM_SIZE); |
| 601 | clear_bit(slot, edma_inuse); | 738 | clear_bit(slot, edma_info[ctlr]->edma_inuse); |
| 602 | } | 739 | } |
| 603 | EXPORT_SYMBOL(edma_free_slot); | 740 | EXPORT_SYMBOL(edma_free_slot); |
| 604 | 741 | ||
| 742 | |||
| 743 | /** | ||
| 744 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots | ||
| 745 | * The API will return the starting point of a set of | ||
| 746 | * contiguous PARAM's that have been requested | ||
| 747 | * | ||
| 748 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT | ||
| 749 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | ||
| 750 | * @count: number of contiguous Paramter RAM's | ||
| 751 | * @param - the start value of Parameter RAM that should be passed if id | ||
| 752 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | ||
| 753 | * | ||
| 754 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of | ||
| 755 | * contiguous Parameter RAMs from parameter RAM 64 in the case of DaVinci SOCs | ||
| 756 | * and 32 in the case of Primus | ||
| 757 | * | ||
| 758 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a | ||
| 759 | * set of contiguous parameter RAMs from the "param" that is passed as an | ||
| 760 | * argument to the API. | ||
| 761 | * | ||
| 762 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries | ||
| 763 | * starts looking for a set of contiguous parameter RAMs from the "param" | ||
| 764 | * that is passed as an argument to the API. On failure the API will try to | ||
| 765 | * find a set of contiguous Parameter RAMs in the remaining Parameter RAMs | ||
| 766 | */ | ||
| 767 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | ||
| 768 | { | ||
| 769 | /* | ||
| 770 | * The start slot requested should be greater than | ||
| 771 | * the number of channels and lesser than the total number | ||
| 772 | * of slots | ||
| 773 | */ | ||
| 774 | if (slot < edma_info[ctlr]->num_channels || | ||
| 775 | slot >= edma_info[ctlr]->num_slots) | ||
| 776 | return -EINVAL; | ||
| 777 | |||
| 778 | /* | ||
| 779 | * The number of parameter RAMs requested cannot be less than 1 | ||
| 780 | * and cannot be more than the number of slots minus the number of | ||
| 781 | * channels | ||
| 782 | */ | ||
| 783 | if (count < 1 || count > | ||
| 784 | (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) | ||
| 785 | return -EINVAL; | ||
| 786 | |||
| 787 | switch (id) { | ||
| 788 | case EDMA_CONT_PARAMS_ANY: | ||
| 789 | return reserve_contiguous_params(ctlr, id, count, | ||
| 790 | edma_info[ctlr]->num_channels); | ||
| 791 | case EDMA_CONT_PARAMS_FIXED_EXACT: | ||
| 792 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | ||
| 793 | return reserve_contiguous_params(ctlr, id, count, slot); | ||
| 794 | default: | ||
| 795 | return -EINVAL; | ||
| 796 | } | ||
| 797 | |||
| 798 | } | ||
| 799 | EXPORT_SYMBOL(edma_alloc_cont_slots); | ||
| 800 | |||
| 801 | /** | ||
| 802 | * edma_free_cont_slots - deallocate DMA parameter RAMs | ||
| 803 | * @slot: first parameter RAM of a set of parameter RAMs to be freed | ||
| 804 | * @count: the number of contiguous parameter RAMs to be freed | ||
| 805 | * | ||
| 806 | * This deallocates the parameter RAM slots allocated by | ||
| 807 | * edma_alloc_cont_slots. | ||
| 808 | * Callers/applications need to keep track of sets of contiguous | ||
| 809 | * parameter RAMs that have been allocated using the edma_alloc_cont_slots | ||
| 810 | * API. | ||
| 811 | * Callers are responsible for ensuring the slots are inactive, and will | ||
| 812 | * not be activated. | ||
| 813 | */ | ||
| 814 | int edma_free_cont_slots(unsigned slot, int count) | ||
| 815 | { | ||
| 816 | unsigned ctlr; | ||
| 817 | int i; | ||
| 818 | |||
| 819 | ctlr = EDMA_CTLR(slot); | ||
| 820 | slot = EDMA_CHAN_SLOT(slot); | ||
| 821 | |||
| 822 | if (slot < edma_info[ctlr]->num_channels || | ||
| 823 | slot >= edma_info[ctlr]->num_slots || | ||
| 824 | count < 1) | ||
| 825 | return -EINVAL; | ||
| 826 | |||
| 827 | for (i = slot; i < slot + count; ++i) { | ||
| 828 | ctlr = EDMA_CTLR(i); | ||
| 829 | slot = EDMA_CHAN_SLOT(i); | ||
| 830 | |||
| 831 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), | ||
| 832 | &dummy_paramset, PARM_SIZE); | ||
| 833 | clear_bit(slot, edma_info[ctlr]->edma_inuse); | ||
| 834 | } | ||
| 835 | |||
| 836 | return 0; | ||
| 837 | } | ||
| 838 | EXPORT_SYMBOL(edma_free_cont_slots); | ||
| 839 | |||
| 605 | /*-----------------------------------------------------------------------*/ | 840 | /*-----------------------------------------------------------------------*/ |
| 606 | 841 | ||
| 607 | /* Parameter RAM operations (i) -- read/write partial slots */ | 842 | /* Parameter RAM operations (i) -- read/write partial slots */ |
| @@ -620,8 +855,13 @@ EXPORT_SYMBOL(edma_free_slot); | |||
| 620 | void edma_set_src(unsigned slot, dma_addr_t src_port, | 855 | void edma_set_src(unsigned slot, dma_addr_t src_port, |
| 621 | enum address_mode mode, enum fifo_width width) | 856 | enum address_mode mode, enum fifo_width width) |
| 622 | { | 857 | { |
| 623 | if (slot < num_slots) { | 858 | unsigned ctlr; |
| 624 | unsigned int i = edma_parm_read(PARM_OPT, slot); | 859 | |
| 860 | ctlr = EDMA_CTLR(slot); | ||
| 861 | slot = EDMA_CHAN_SLOT(slot); | ||
| 862 | |||
| 863 | if (slot < edma_info[ctlr]->num_slots) { | ||
| 864 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); | ||
| 625 | 865 | ||
| 626 | if (mode) { | 866 | if (mode) { |
| 627 | /* set SAM and program FWID */ | 867 | /* set SAM and program FWID */ |
| @@ -630,11 +870,11 @@ void edma_set_src(unsigned slot, dma_addr_t src_port, | |||
| 630 | /* clear SAM */ | 870 | /* clear SAM */ |
| 631 | i &= ~SAM; | 871 | i &= ~SAM; |
| 632 | } | 872 | } |
| 633 | edma_parm_write(PARM_OPT, slot, i); | 873 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
| 634 | 874 | ||
| 635 | /* set the source port address | 875 | /* set the source port address |
| 636 | in source register of param structure */ | 876 | in source register of param structure */ |
| 637 | edma_parm_write(PARM_SRC, slot, src_port); | 877 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
| 638 | } | 878 | } |
| 639 | } | 879 | } |
| 640 | EXPORT_SYMBOL(edma_set_src); | 880 | EXPORT_SYMBOL(edma_set_src); |
| @@ -653,8 +893,13 @@ EXPORT_SYMBOL(edma_set_src); | |||
| 653 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | 893 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, |
| 654 | enum address_mode mode, enum fifo_width width) | 894 | enum address_mode mode, enum fifo_width width) |
| 655 | { | 895 | { |
| 656 | if (slot < num_slots) { | 896 | unsigned ctlr; |
| 657 | unsigned int i = edma_parm_read(PARM_OPT, slot); | 897 | |
| 898 | ctlr = EDMA_CTLR(slot); | ||
| 899 | slot = EDMA_CHAN_SLOT(slot); | ||
| 900 | |||
| 901 | if (slot < edma_info[ctlr]->num_slots) { | ||
| 902 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); | ||
| 658 | 903 | ||
| 659 | if (mode) { | 904 | if (mode) { |
| 660 | /* set DAM and program FWID */ | 905 | /* set DAM and program FWID */ |
| @@ -663,10 +908,10 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |||
| 663 | /* clear DAM */ | 908 | /* clear DAM */ |
| 664 | i &= ~DAM; | 909 | i &= ~DAM; |
| 665 | } | 910 | } |
| 666 | edma_parm_write(PARM_OPT, slot, i); | 911 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
| 667 | /* set the destination port address | 912 | /* set the destination port address |
| 668 | in dest register of param structure */ | 913 | in dest register of param structure */ |
| 669 | edma_parm_write(PARM_DST, slot, dest_port); | 914 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
| 670 | } | 915 | } |
| 671 | } | 916 | } |
| 672 | EXPORT_SYMBOL(edma_set_dest); | 917 | EXPORT_SYMBOL(edma_set_dest); |
| @@ -683,8 +928,12 @@ EXPORT_SYMBOL(edma_set_dest); | |||
| 683 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) | 928 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) |
| 684 | { | 929 | { |
| 685 | struct edmacc_param temp; | 930 | struct edmacc_param temp; |
| 931 | unsigned ctlr; | ||
| 932 | |||
| 933 | ctlr = EDMA_CTLR(slot); | ||
| 934 | slot = EDMA_CHAN_SLOT(slot); | ||
| 686 | 935 | ||
| 687 | edma_read_slot(slot, &temp); | 936 | edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); |
| 688 | if (src != NULL) | 937 | if (src != NULL) |
| 689 | *src = temp.src; | 938 | *src = temp.src; |
| 690 | if (dst != NULL) | 939 | if (dst != NULL) |
| @@ -704,10 +953,15 @@ EXPORT_SYMBOL(edma_get_position); | |||
| 704 | */ | 953 | */ |
| 705 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | 954 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) |
| 706 | { | 955 | { |
| 707 | if (slot < num_slots) { | 956 | unsigned ctlr; |
| 708 | edma_parm_modify(PARM_SRC_DST_BIDX, slot, | 957 | |
| 958 | ctlr = EDMA_CTLR(slot); | ||
| 959 | slot = EDMA_CHAN_SLOT(slot); | ||
| 960 | |||
| 961 | if (slot < edma_info[ctlr]->num_slots) { | ||
| 962 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, | ||
| 709 | 0xffff0000, src_bidx); | 963 | 0xffff0000, src_bidx); |
| 710 | edma_parm_modify(PARM_SRC_DST_CIDX, slot, | 964 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
| 711 | 0xffff0000, src_cidx); | 965 | 0xffff0000, src_cidx); |
| 712 | } | 966 | } |
| 713 | } | 967 | } |
| @@ -725,10 +979,15 @@ EXPORT_SYMBOL(edma_set_src_index); | |||
| 725 | */ | 979 | */ |
| 726 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | 980 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) |
| 727 | { | 981 | { |
| 728 | if (slot < num_slots) { | 982 | unsigned ctlr; |
| 729 | edma_parm_modify(PARM_SRC_DST_BIDX, slot, | 983 | |
| 984 | ctlr = EDMA_CTLR(slot); | ||
| 985 | slot = EDMA_CHAN_SLOT(slot); | ||
| 986 | |||
| 987 | if (slot < edma_info[ctlr]->num_slots) { | ||
| 988 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, | ||
| 730 | 0x0000ffff, dest_bidx << 16); | 989 | 0x0000ffff, dest_bidx << 16); |
| 731 | edma_parm_modify(PARM_SRC_DST_CIDX, slot, | 990 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
| 732 | 0x0000ffff, dest_cidx << 16); | 991 | 0x0000ffff, dest_cidx << 16); |
| 733 | } | 992 | } |
| 734 | } | 993 | } |
| @@ -767,16 +1026,21 @@ void edma_set_transfer_params(unsigned slot, | |||
| 767 | u16 acnt, u16 bcnt, u16 ccnt, | 1026 | u16 acnt, u16 bcnt, u16 ccnt, |
| 768 | u16 bcnt_rld, enum sync_dimension sync_mode) | 1027 | u16 bcnt_rld, enum sync_dimension sync_mode) |
| 769 | { | 1028 | { |
| 770 | if (slot < num_slots) { | 1029 | unsigned ctlr; |
| 771 | edma_parm_modify(PARM_LINK_BCNTRLD, slot, | 1030 | |
| 1031 | ctlr = EDMA_CTLR(slot); | ||
| 1032 | slot = EDMA_CHAN_SLOT(slot); | ||
| 1033 | |||
| 1034 | if (slot < edma_info[ctlr]->num_slots) { | ||
| 1035 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, | ||
| 772 | 0x0000ffff, bcnt_rld << 16); | 1036 | 0x0000ffff, bcnt_rld << 16); |
| 773 | if (sync_mode == ASYNC) | 1037 | if (sync_mode == ASYNC) |
| 774 | edma_parm_and(PARM_OPT, slot, ~SYNCDIM); | 1038 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
| 775 | else | 1039 | else |
| 776 | edma_parm_or(PARM_OPT, slot, SYNCDIM); | 1040 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
| 777 | /* Set the acount, bcount, ccount registers */ | 1041 | /* Set the acount, bcount, ccount registers */ |
| 778 | edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt); | 1042 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
| 779 | edma_parm_write(PARM_CCNT, slot, ccnt); | 1043 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); |
| 780 | } | 1044 | } |
| 781 | } | 1045 | } |
| 782 | EXPORT_SYMBOL(edma_set_transfer_params); | 1046 | EXPORT_SYMBOL(edma_set_transfer_params); |
| @@ -790,11 +1054,19 @@ EXPORT_SYMBOL(edma_set_transfer_params); | |||
| 790 | */ | 1054 | */ |
| 791 | void edma_link(unsigned from, unsigned to) | 1055 | void edma_link(unsigned from, unsigned to) |
| 792 | { | 1056 | { |
| 793 | if (from >= num_slots) | 1057 | unsigned ctlr_from, ctlr_to; |
| 1058 | |||
| 1059 | ctlr_from = EDMA_CTLR(from); | ||
| 1060 | from = EDMA_CHAN_SLOT(from); | ||
| 1061 | ctlr_to = EDMA_CTLR(to); | ||
| 1062 | to = EDMA_CHAN_SLOT(to); | ||
| 1063 | |||
| 1064 | if (from >= edma_info[ctlr_from]->num_slots) | ||
| 794 | return; | 1065 | return; |
| 795 | if (to >= num_slots) | 1066 | if (to >= edma_info[ctlr_to]->num_slots) |
| 796 | return; | 1067 | return; |
| 797 | edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); | 1068 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
| 1069 | PARM_OFFSET(to)); | ||
| 798 | } | 1070 | } |
| 799 | EXPORT_SYMBOL(edma_link); | 1071 | EXPORT_SYMBOL(edma_link); |
| 800 | 1072 | ||
| @@ -807,9 +1079,14 @@ EXPORT_SYMBOL(edma_link); | |||
| 807 | */ | 1079 | */ |
| 808 | void edma_unlink(unsigned from) | 1080 | void edma_unlink(unsigned from) |
| 809 | { | 1081 | { |
| 810 | if (from >= num_slots) | 1082 | unsigned ctlr; |
| 1083 | |||
| 1084 | ctlr = EDMA_CTLR(from); | ||
| 1085 | from = EDMA_CHAN_SLOT(from); | ||
| 1086 | |||
| 1087 | if (from >= edma_info[ctlr]->num_slots) | ||
| 811 | return; | 1088 | return; |
| 812 | edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff); | 1089 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
| 813 | } | 1090 | } |
| 814 | EXPORT_SYMBOL(edma_unlink); | 1091 | EXPORT_SYMBOL(edma_unlink); |
| 815 | 1092 | ||
| @@ -829,9 +1106,15 @@ EXPORT_SYMBOL(edma_unlink); | |||
| 829 | */ | 1106 | */ |
| 830 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) | 1107 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) |
| 831 | { | 1108 | { |
| 832 | if (slot >= num_slots) | 1109 | unsigned ctlr; |
| 1110 | |||
| 1111 | ctlr = EDMA_CTLR(slot); | ||
| 1112 | slot = EDMA_CHAN_SLOT(slot); | ||
| 1113 | |||
| 1114 | if (slot >= edma_info[ctlr]->num_slots) | ||
| 833 | return; | 1115 | return; |
| 834 | memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE); | 1116 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
| 1117 | PARM_SIZE); | ||
| 835 | } | 1118 | } |
| 836 | EXPORT_SYMBOL(edma_write_slot); | 1119 | EXPORT_SYMBOL(edma_write_slot); |
| 837 | 1120 | ||
| @@ -845,9 +1128,15 @@ EXPORT_SYMBOL(edma_write_slot); | |||
| 845 | */ | 1128 | */ |
| 846 | void edma_read_slot(unsigned slot, struct edmacc_param *param) | 1129 | void edma_read_slot(unsigned slot, struct edmacc_param *param) |
| 847 | { | 1130 | { |
| 848 | if (slot >= num_slots) | 1131 | unsigned ctlr; |
| 1132 | |||
| 1133 | ctlr = EDMA_CTLR(slot); | ||
| 1134 | slot = EDMA_CHAN_SLOT(slot); | ||
| 1135 | |||
| 1136 | if (slot >= edma_info[ctlr]->num_slots) | ||
| 849 | return; | 1137 | return; |
| 850 | memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE); | 1138 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
| 1139 | PARM_SIZE); | ||
| 851 | } | 1140 | } |
| 852 | EXPORT_SYMBOL(edma_read_slot); | 1141 | EXPORT_SYMBOL(edma_read_slot); |
| 853 | 1142 | ||
| @@ -864,10 +1153,15 @@ EXPORT_SYMBOL(edma_read_slot); | |||
| 864 | */ | 1153 | */ |
| 865 | void edma_pause(unsigned channel) | 1154 | void edma_pause(unsigned channel) |
| 866 | { | 1155 | { |
| 867 | if (channel < num_channels) { | 1156 | unsigned ctlr; |
| 1157 | |||
| 1158 | ctlr = EDMA_CTLR(channel); | ||
| 1159 | channel = EDMA_CHAN_SLOT(channel); | ||
| 1160 | |||
| 1161 | if (channel < edma_info[ctlr]->num_channels) { | ||
| 868 | unsigned int mask = (1 << (channel & 0x1f)); | 1162 | unsigned int mask = (1 << (channel & 0x1f)); |
| 869 | 1163 | ||
| 870 | edma_shadow0_write_array(SH_EECR, channel >> 5, mask); | 1164 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
| 871 | } | 1165 | } |
| 872 | } | 1166 | } |
| 873 | EXPORT_SYMBOL(edma_pause); | 1167 | EXPORT_SYMBOL(edma_pause); |
| @@ -880,10 +1174,15 @@ EXPORT_SYMBOL(edma_pause); | |||
| 880 | */ | 1174 | */ |
| 881 | void edma_resume(unsigned channel) | 1175 | void edma_resume(unsigned channel) |
| 882 | { | 1176 | { |
| 883 | if (channel < num_channels) { | 1177 | unsigned ctlr; |
| 1178 | |||
| 1179 | ctlr = EDMA_CTLR(channel); | ||
| 1180 | channel = EDMA_CHAN_SLOT(channel); | ||
| 1181 | |||
| 1182 | if (channel < edma_info[ctlr]->num_channels) { | ||
| 884 | unsigned int mask = (1 << (channel & 0x1f)); | 1183 | unsigned int mask = (1 << (channel & 0x1f)); |
| 885 | 1184 | ||
| 886 | edma_shadow0_write_array(SH_EESR, channel >> 5, mask); | 1185 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
| 887 | } | 1186 | } |
| 888 | } | 1187 | } |
| 889 | EXPORT_SYMBOL(edma_resume); | 1188 | EXPORT_SYMBOL(edma_resume); |
| @@ -901,28 +1200,33 @@ EXPORT_SYMBOL(edma_resume); | |||
| 901 | */ | 1200 | */ |
| 902 | int edma_start(unsigned channel) | 1201 | int edma_start(unsigned channel) |
| 903 | { | 1202 | { |
| 904 | if (channel < num_channels) { | 1203 | unsigned ctlr; |
| 1204 | |||
| 1205 | ctlr = EDMA_CTLR(channel); | ||
| 1206 | channel = EDMA_CHAN_SLOT(channel); | ||
| 1207 | |||
| 1208 | if (channel < edma_info[ctlr]->num_channels) { | ||
| 905 | int j = channel >> 5; | 1209 | int j = channel >> 5; |
| 906 | unsigned int mask = (1 << (channel & 0x1f)); | 1210 | unsigned int mask = (1 << (channel & 0x1f)); |
| 907 | 1211 | ||
| 908 | /* EDMA channels without event association */ | 1212 | /* EDMA channels without event association */ |
| 909 | if (test_bit(channel, edma_noevent)) { | 1213 | if (test_bit(channel, edma_info[ctlr]->edma_noevent)) { |
| 910 | pr_debug("EDMA: ESR%d %08x\n", j, | 1214 | pr_debug("EDMA: ESR%d %08x\n", j, |
| 911 | edma_shadow0_read_array(SH_ESR, j)); | 1215 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
| 912 | edma_shadow0_write_array(SH_ESR, j, mask); | 1216 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); |
| 913 | return 0; | 1217 | return 0; |
| 914 | } | 1218 | } |
| 915 | 1219 | ||
| 916 | /* EDMA channel with event association */ | 1220 | /* EDMA channel with event association */ |
| 917 | pr_debug("EDMA: ER%d %08x\n", j, | 1221 | pr_debug("EDMA: ER%d %08x\n", j, |
| 918 | edma_shadow0_read_array(SH_ER, j)); | 1222 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
| 919 | /* Clear any pending error */ | 1223 | /* Clear any pending error */ |
| 920 | edma_write_array(EDMA_EMCR, j, mask); | 1224 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
| 921 | /* Clear any SER */ | 1225 | /* Clear any SER */ |
| 922 | edma_shadow0_write_array(SH_SECR, j, mask); | 1226 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
| 923 | edma_shadow0_write_array(SH_EESR, j, mask); | 1227 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); |
| 924 | pr_debug("EDMA: EER%d %08x\n", j, | 1228 | pr_debug("EDMA: EER%d %08x\n", j, |
| 925 | edma_shadow0_read_array(SH_EER, j)); | 1229 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
| 926 | return 0; | 1230 | return 0; |
| 927 | } | 1231 | } |
| 928 | 1232 | ||
| @@ -941,17 +1245,22 @@ EXPORT_SYMBOL(edma_start); | |||
| 941 | */ | 1245 | */ |
| 942 | void edma_stop(unsigned channel) | 1246 | void edma_stop(unsigned channel) |
| 943 | { | 1247 | { |
| 944 | if (channel < num_channels) { | 1248 | unsigned ctlr; |
| 1249 | |||
| 1250 | ctlr = EDMA_CTLR(channel); | ||
| 1251 | channel = EDMA_CHAN_SLOT(channel); | ||
| 1252 | |||
| 1253 | if (channel < edma_info[ctlr]->num_channels) { | ||
| 945 | int j = channel >> 5; | 1254 | int j = channel >> 5; |
| 946 | unsigned int mask = (1 << (channel & 0x1f)); | 1255 | unsigned int mask = (1 << (channel & 0x1f)); |
| 947 | 1256 | ||
| 948 | edma_shadow0_write_array(SH_EECR, j, mask); | 1257 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
| 949 | edma_shadow0_write_array(SH_ECR, j, mask); | 1258 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); |
| 950 | edma_shadow0_write_array(SH_SECR, j, mask); | 1259 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
| 951 | edma_write_array(EDMA_EMCR, j, mask); | 1260 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
| 952 | 1261 | ||
| 953 | pr_debug("EDMA: EER%d %08x\n", j, | 1262 | pr_debug("EDMA: EER%d %08x\n", j, |
| 954 | edma_shadow0_read_array(SH_EER, j)); | 1263 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
| 955 | 1264 | ||
| 956 | /* REVISIT: consider guarding against inappropriate event | 1265 | /* REVISIT: consider guarding against inappropriate event |
| 957 | * chaining by overwriting with dummy_paramset. | 1266 | * chaining by overwriting with dummy_paramset. |
| @@ -975,18 +1284,23 @@ EXPORT_SYMBOL(edma_stop); | |||
| 975 | 1284 | ||
| 976 | void edma_clean_channel(unsigned channel) | 1285 | void edma_clean_channel(unsigned channel) |
| 977 | { | 1286 | { |
| 978 | if (channel < num_channels) { | 1287 | unsigned ctlr; |
| 1288 | |||
| 1289 | ctlr = EDMA_CTLR(channel); | ||
| 1290 | channel = EDMA_CHAN_SLOT(channel); | ||
| 1291 | |||
| 1292 | if (channel < edma_info[ctlr]->num_channels) { | ||
| 979 | int j = (channel >> 5); | 1293 | int j = (channel >> 5); |
| 980 | unsigned int mask = 1 << (channel & 0x1f); | 1294 | unsigned int mask = 1 << (channel & 0x1f); |
| 981 | 1295 | ||
| 982 | pr_debug("EDMA: EMR%d %08x\n", j, | 1296 | pr_debug("EDMA: EMR%d %08x\n", j, |
| 983 | edma_read_array(EDMA_EMR, j)); | 1297 | edma_read_array(ctlr, EDMA_EMR, j)); |
| 984 | edma_shadow0_write_array(SH_ECR, j, mask); | 1298 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); |
| 985 | /* Clear the corresponding EMR bits */ | 1299 | /* Clear the corresponding EMR bits */ |
| 986 | edma_write_array(EDMA_EMCR, j, mask); | 1300 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
| 987 | /* Clear any SER */ | 1301 | /* Clear any SER */ |
| 988 | edma_shadow0_write_array(SH_SECR, j, mask); | 1302 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
| 989 | edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3); | 1303 | edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); |
| 990 | } | 1304 | } |
| 991 | } | 1305 | } |
| 992 | EXPORT_SYMBOL(edma_clean_channel); | 1306 | EXPORT_SYMBOL(edma_clean_channel); |
| @@ -998,12 +1312,17 @@ EXPORT_SYMBOL(edma_clean_channel); | |||
| 998 | */ | 1312 | */ |
| 999 | void edma_clear_event(unsigned channel) | 1313 | void edma_clear_event(unsigned channel) |
| 1000 | { | 1314 | { |
| 1001 | if (channel >= num_channels) | 1315 | unsigned ctlr; |
| 1316 | |||
| 1317 | ctlr = EDMA_CTLR(channel); | ||
| 1318 | channel = EDMA_CHAN_SLOT(channel); | ||
| 1319 | |||
| 1320 | if (channel >= edma_info[ctlr]->num_channels) | ||
| 1002 | return; | 1321 | return; |
| 1003 | if (channel < 32) | 1322 | if (channel < 32) |
| 1004 | edma_write(EDMA_ECR, 1 << channel); | 1323 | edma_write(ctlr, EDMA_ECR, 1 << channel); |
| 1005 | else | 1324 | else |
| 1006 | edma_write(EDMA_ECRH, 1 << (channel - 32)); | 1325 | edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); |
| 1007 | } | 1326 | } |
| 1008 | EXPORT_SYMBOL(edma_clear_event); | 1327 | EXPORT_SYMBOL(edma_clear_event); |
| 1009 | 1328 | ||
| @@ -1012,62 +1331,133 @@ EXPORT_SYMBOL(edma_clear_event); | |||
| 1012 | static int __init edma_probe(struct platform_device *pdev) | 1331 | static int __init edma_probe(struct platform_device *pdev) |
| 1013 | { | 1332 | { |
| 1014 | struct edma_soc_info *info = pdev->dev.platform_data; | 1333 | struct edma_soc_info *info = pdev->dev.platform_data; |
| 1015 | int i; | 1334 | const s8 (*queue_priority_mapping)[2]; |
| 1016 | int status; | 1335 | const s8 (*queue_tc_mapping)[2]; |
| 1336 | int i, j, found = 0; | ||
| 1337 | int status = -1; | ||
| 1017 | const s8 *noevent; | 1338 | const s8 *noevent; |
| 1018 | int irq = 0, err_irq = 0; | 1339 | int irq[EDMA_MAX_CC] = {0, 0}; |
| 1019 | struct resource *r; | 1340 | int err_irq[EDMA_MAX_CC] = {0, 0}; |
| 1020 | resource_size_t len; | 1341 | struct resource *r[EDMA_MAX_CC] = {NULL}; |
| 1342 | resource_size_t len[EDMA_MAX_CC]; | ||
| 1343 | char res_name[10]; | ||
| 1344 | char irq_name[10]; | ||
| 1021 | 1345 | ||
| 1022 | if (!info) | 1346 | if (!info) |
| 1023 | return -ENODEV; | 1347 | return -ENODEV; |
| 1024 | 1348 | ||
| 1025 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc"); | 1349 | for (j = 0; j < EDMA_MAX_CC; j++) { |
| 1026 | if (!r) | 1350 | sprintf(res_name, "edma_cc%d", j); |
| 1027 | return -ENODEV; | 1351 | r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1352 | res_name); | ||
| 1353 | if (!r[j]) { | ||
| 1354 | if (found) | ||
| 1355 | break; | ||
| 1356 | else | ||
| 1357 | return -ENODEV; | ||
| 1358 | } else | ||
| 1359 | found = 1; | ||
| 1360 | |||
| 1361 | len[j] = resource_size(r[j]); | ||
| 1362 | |||
| 1363 | r[j] = request_mem_region(r[j]->start, len[j], | ||
| 1364 | dev_name(&pdev->dev)); | ||
| 1365 | if (!r[j]) { | ||
| 1366 | status = -EBUSY; | ||
| 1367 | goto fail1; | ||
| 1368 | } | ||
| 1028 | 1369 | ||
| 1029 | len = r->end - r->start + 1; | 1370 | edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); |
| 1371 | if (!edmacc_regs_base[j]) { | ||
| 1372 | status = -EBUSY; | ||
| 1373 | goto fail1; | ||
| 1374 | } | ||
| 1030 | 1375 | ||
| 1031 | r = request_mem_region(r->start, len, r->name); | 1376 | edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); |
| 1032 | if (!r) | 1377 | if (!edma_info[j]) { |
| 1033 | return -EBUSY; | 1378 | status = -ENOMEM; |
| 1379 | goto fail1; | ||
| 1380 | } | ||
| 1381 | memset(edma_info[j], 0, sizeof(struct edma)); | ||
| 1382 | |||
| 1383 | edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, | ||
| 1384 | EDMA_MAX_DMACH); | ||
| 1385 | edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, | ||
| 1386 | EDMA_MAX_PARAMENTRY); | ||
| 1387 | edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, | ||
| 1388 | EDMA_MAX_CC); | ||
| 1389 | |||
| 1390 | edma_info[j]->default_queue = info[j].default_queue; | ||
| 1391 | if (!edma_info[j]->default_queue) | ||
| 1392 | edma_info[j]->default_queue = EVENTQ_1; | ||
| 1393 | |||
| 1394 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", | ||
| 1395 | edmacc_regs_base[j]); | ||
| 1396 | |||
| 1397 | for (i = 0; i < edma_info[j]->num_slots; i++) | ||
| 1398 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), | ||
| 1399 | &dummy_paramset, PARM_SIZE); | ||
| 1400 | |||
| 1401 | noevent = info[j].noevent; | ||
| 1402 | if (noevent) { | ||
| 1403 | while (*noevent != -1) | ||
| 1404 | set_bit(*noevent++, edma_info[j]->edma_noevent); | ||
| 1405 | } | ||
| 1034 | 1406 | ||
| 1035 | edmacc_regs_base = ioremap(r->start, len); | 1407 | sprintf(irq_name, "edma%d", j); |
| 1036 | if (!edmacc_regs_base) { | 1408 | irq[j] = platform_get_irq_byname(pdev, irq_name); |
| 1037 | status = -EBUSY; | 1409 | edma_info[j]->irq_res_start = irq[j]; |
| 1038 | goto fail1; | 1410 | status = request_irq(irq[j], dma_irq_handler, 0, "edma", |
| 1039 | } | 1411 | &pdev->dev); |
| 1412 | if (status < 0) { | ||
| 1413 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | ||
| 1414 | irq[j], status); | ||
| 1415 | goto fail; | ||
| 1416 | } | ||
| 1040 | 1417 | ||
| 1041 | num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH); | 1418 | sprintf(irq_name, "edma%d_err", j); |
| 1042 | num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY); | 1419 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); |
| 1420 | edma_info[j]->irq_res_end = err_irq[j]; | ||
| 1421 | status = request_irq(err_irq[j], dma_ccerr_handler, 0, | ||
| 1422 | "edma_error", &pdev->dev); | ||
| 1423 | if (status < 0) { | ||
| 1424 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | ||
| 1425 | err_irq[j], status); | ||
| 1426 | goto fail; | ||
| 1427 | } | ||
| 1043 | 1428 | ||
| 1044 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base); | 1429 | /* Everything lives on transfer controller 1 until otherwise |
| 1430 | * specified. This way, long transfers on the low priority queue | ||
| 1431 | * started by the codec engine will not cause audio defects. | ||
| 1432 | */ | ||
| 1433 | for (i = 0; i < edma_info[j]->num_channels; i++) | ||
| 1434 | map_dmach_queue(j, i, EVENTQ_1); | ||
| 1045 | 1435 | ||
| 1046 | for (i = 0; i < num_slots; i++) | 1436 | queue_tc_mapping = info[j].queue_tc_mapping; |
| 1047 | memcpy_toio(edmacc_regs_base + PARM_OFFSET(i), | 1437 | queue_priority_mapping = info[j].queue_priority_mapping; |
| 1048 | &dummy_paramset, PARM_SIZE); | ||
| 1049 | 1438 | ||
| 1050 | noevent = info->noevent; | 1439 | /* Event queue to TC mapping */ |
| 1051 | if (noevent) { | 1440 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) |
| 1052 | while (*noevent != -1) | 1441 | map_queue_tc(j, queue_tc_mapping[i][0], |
| 1053 | set_bit(*noevent++, edma_noevent); | 1442 | queue_tc_mapping[i][1]); |
| 1054 | } | ||
| 1055 | 1443 | ||
| 1056 | irq = platform_get_irq(pdev, 0); | 1444 | /* Event queue priority mapping */ |
| 1057 | status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev); | 1445 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) |
| 1058 | if (status < 0) { | 1446 | assign_priority_to_queue(j, |
| 1059 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | 1447 | queue_priority_mapping[i][0], |
| 1060 | irq, status); | 1448 | queue_priority_mapping[i][1]); |
| 1061 | goto fail; | 1449 | |
| 1062 | } | 1450 | /* Map the channel to param entry if channel mapping logic |
| 1451 | * exist | ||
| 1452 | */ | ||
| 1453 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | ||
| 1454 | map_dmach_param(j); | ||
| 1063 | 1455 | ||
| 1064 | err_irq = platform_get_irq(pdev, 1); | 1456 | for (i = 0; i < info[j].n_region; i++) { |
| 1065 | status = request_irq(err_irq, dma_ccerr_handler, 0, | 1457 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); |
| 1066 | "edma_error", &pdev->dev); | 1458 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); |
| 1067 | if (status < 0) { | 1459 | edma_write_array(j, EDMA_QRAE, i, 0x0); |
| 1068 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | 1460 | } |
| 1069 | err_irq, status); | ||
| 1070 | goto fail; | ||
| 1071 | } | 1461 | } |
| 1072 | 1462 | ||
| 1073 | if (tc_errs_handled) { | 1463 | if (tc_errs_handled) { |
| @@ -1087,38 +1477,23 @@ static int __init edma_probe(struct platform_device *pdev) | |||
| 1087 | } | 1477 | } |
| 1088 | } | 1478 | } |
| 1089 | 1479 | ||
| 1090 | /* Everything lives on transfer controller 1 until otherwise specified. | ||
| 1091 | * This way, long transfers on the low priority queue | ||
| 1092 | * started by the codec engine will not cause audio defects. | ||
| 1093 | */ | ||
| 1094 | for (i = 0; i < num_channels; i++) | ||
| 1095 | map_dmach_queue(i, EVENTQ_1); | ||
| 1096 | |||
| 1097 | /* Event queue to TC mapping */ | ||
| 1098 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) | ||
| 1099 | map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]); | ||
| 1100 | |||
| 1101 | /* Event queue priority mapping */ | ||
| 1102 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | ||
| 1103 | assign_priority_to_queue(queue_priority_mapping[i][0], | ||
| 1104 | queue_priority_mapping[i][1]); | ||
| 1105 | |||
| 1106 | for (i = 0; i < info->n_region; i++) { | ||
| 1107 | edma_write_array2(EDMA_DRAE, i, 0, 0x0); | ||
| 1108 | edma_write_array2(EDMA_DRAE, i, 1, 0x0); | ||
| 1109 | edma_write_array(EDMA_QRAE, i, 0x0); | ||
| 1110 | } | ||
| 1111 | |||
| 1112 | return 0; | 1480 | return 0; |
| 1113 | 1481 | ||
| 1114 | fail: | 1482 | fail: |
| 1115 | if (err_irq) | 1483 | for (i = 0; i < EDMA_MAX_CC; i++) { |
| 1116 | free_irq(err_irq, NULL); | 1484 | if (err_irq[i]) |
| 1117 | if (irq) | 1485 | free_irq(err_irq[i], &pdev->dev); |
| 1118 | free_irq(irq, NULL); | 1486 | if (irq[i]) |
| 1119 | iounmap(edmacc_regs_base); | 1487 | free_irq(irq[i], &pdev->dev); |
| 1488 | } | ||
| 1120 | fail1: | 1489 | fail1: |
| 1121 | release_mem_region(r->start, len); | 1490 | for (i = 0; i < EDMA_MAX_CC; i++) { |
| 1491 | if (r[i]) | ||
| 1492 | release_mem_region(r[i]->start, len[i]); | ||
| 1493 | if (edmacc_regs_base[i]) | ||
| 1494 | iounmap(edmacc_regs_base[i]); | ||
| 1495 | kfree(edma_info[i]); | ||
| 1496 | } | ||
| 1122 | return status; | 1497 | return status; |
| 1123 | } | 1498 | } |
| 1124 | 1499 | ||
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 1b6532159c58..f6ea9db11f41 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
| @@ -34,6 +34,7 @@ static DEFINE_SPINLOCK(gpio_lock); | |||
| 34 | struct davinci_gpio { | 34 | struct davinci_gpio { |
| 35 | struct gpio_chip chip; | 35 | struct gpio_chip chip; |
| 36 | struct gpio_controller *__iomem regs; | 36 | struct gpio_controller *__iomem regs; |
| 37 | int irq_base; | ||
| 37 | }; | 38 | }; |
| 38 | 39 | ||
| 39 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; | 40 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
| @@ -161,8 +162,7 @@ pure_initcall(davinci_gpio_setup); | |||
| 161 | * used as output pins ... which is convenient for testing. | 162 | * used as output pins ... which is convenient for testing. |
| 162 | * | 163 | * |
| 163 | * NOTE: The first few GPIOs also have direct INTC hookups in addition | 164 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
| 164 | * to their GPIOBNK0 irq, with a bit less overhead but less flexibility | 165 | * to their GPIOBNK0 irq, with a bit less overhead. |
| 165 | * on triggering (e.g. no edge options). We don't try to use those. | ||
| 166 | * | 166 | * |
| 167 | * All those INTC hookups (direct, plus several IRQ banks) can also | 167 | * All those INTC hookups (direct, plus several IRQ banks) can also |
| 168 | * serve as EDMA event triggers. | 168 | * serve as EDMA event triggers. |
| @@ -171,7 +171,7 @@ pure_initcall(davinci_gpio_setup); | |||
| 171 | static void gpio_irq_disable(unsigned irq) | 171 | static void gpio_irq_disable(unsigned irq) |
| 172 | { | 172 | { |
| 173 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 173 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 174 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | 174 | u32 mask = (u32) get_irq_data(irq); |
| 175 | 175 | ||
| 176 | __raw_writel(mask, &g->clr_falling); | 176 | __raw_writel(mask, &g->clr_falling); |
| 177 | __raw_writel(mask, &g->clr_rising); | 177 | __raw_writel(mask, &g->clr_rising); |
| @@ -180,7 +180,7 @@ static void gpio_irq_disable(unsigned irq) | |||
| 180 | static void gpio_irq_enable(unsigned irq) | 180 | static void gpio_irq_enable(unsigned irq) |
| 181 | { | 181 | { |
| 182 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 182 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 183 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | 183 | u32 mask = (u32) get_irq_data(irq); |
| 184 | unsigned status = irq_desc[irq].status; | 184 | unsigned status = irq_desc[irq].status; |
| 185 | 185 | ||
| 186 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | 186 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| @@ -196,7 +196,7 @@ static void gpio_irq_enable(unsigned irq) | |||
| 196 | static int gpio_irq_type(unsigned irq, unsigned trigger) | 196 | static int gpio_irq_type(unsigned irq, unsigned trigger) |
| 197 | { | 197 | { |
| 198 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 198 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); |
| 199 | u32 mask = __gpio_mask(irq_to_gpio(irq)); | 199 | u32 mask = (u32) get_irq_data(irq); |
| 200 | 200 | ||
| 201 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 201 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 202 | return -EINVAL; | 202 | return -EINVAL; |
| @@ -260,6 +260,45 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 260 | /* now it may re-trigger */ | 260 | /* now it may re-trigger */ |
| 261 | } | 261 | } |
| 262 | 262 | ||
| 263 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) | ||
| 264 | { | ||
| 265 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); | ||
| 266 | |||
| 267 | if (d->irq_base >= 0) | ||
| 268 | return d->irq_base + offset; | ||
| 269 | else | ||
| 270 | return -ENODEV; | ||
| 271 | } | ||
| 272 | |||
| 273 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | ||
| 274 | { | ||
| 275 | struct davinci_soc_info *soc_info = &davinci_soc_info; | ||
| 276 | |||
| 277 | /* NOTE: we assume for now that only irqs in the first gpio_chip | ||
| 278 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). | ||
| 279 | */ | ||
| 280 | if (offset < soc_info->gpio_unbanked) | ||
| 281 | return soc_info->gpio_irq + offset; | ||
| 282 | else | ||
| 283 | return -ENODEV; | ||
| 284 | } | ||
| 285 | |||
| 286 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) | ||
| 287 | { | ||
| 288 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | ||
| 289 | u32 mask = (u32) get_irq_data(irq); | ||
| 290 | |||
| 291 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | ||
| 292 | return -EINVAL; | ||
| 293 | |||
| 294 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | ||
| 295 | ? &g->set_falling : &g->clr_falling); | ||
| 296 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | ||
| 297 | ? &g->set_rising : &g->clr_rising); | ||
| 298 | |||
| 299 | return 0; | ||
| 300 | } | ||
| 301 | |||
| 263 | /* | 302 | /* |
| 264 | * NOTE: for suspend/resume, probably best to make a platform_device with | 303 | * NOTE: for suspend/resume, probably best to make a platform_device with |
| 265 | * suspend_late/resume_resume calls hooking into results of the set_wake() | 304 | * suspend_late/resume_resume calls hooking into results of the set_wake() |
| @@ -275,6 +314,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
| 275 | u32 binten = 0; | 314 | u32 binten = 0; |
| 276 | unsigned ngpio, bank_irq; | 315 | unsigned ngpio, bank_irq; |
| 277 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 316 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 317 | struct gpio_controller *__iomem g; | ||
| 278 | 318 | ||
| 279 | ngpio = soc_info->gpio_num; | 319 | ngpio = soc_info->gpio_num; |
| 280 | 320 | ||
| @@ -292,12 +332,63 @@ static int __init davinci_gpio_irq_setup(void) | |||
| 292 | } | 332 | } |
| 293 | clk_enable(clk); | 333 | clk_enable(clk); |
| 294 | 334 | ||
| 335 | /* Arrange gpio_to_irq() support, handling either direct IRQs or | ||
| 336 | * banked IRQs. Having GPIOs in the first GPIO bank use direct | ||
| 337 | * IRQs, while the others use banked IRQs, would need some setup | ||
| 338 | * tweaks to recognize hardware which can do that. | ||
| 339 | */ | ||
| 340 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | ||
| 341 | chips[bank].chip.to_irq = gpio_to_irq_banked; | ||
| 342 | chips[bank].irq_base = soc_info->gpio_unbanked | ||
| 343 | ? -EINVAL | ||
| 344 | : (soc_info->intc_irq_num + gpio); | ||
| 345 | } | ||
| 346 | |||
| 347 | /* | ||
| 348 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | ||
| 349 | * controller only handling trigger modes. We currently assume no | ||
| 350 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | ||
| 351 | */ | ||
| 352 | if (soc_info->gpio_unbanked) { | ||
| 353 | static struct irq_chip gpio_irqchip_unbanked; | ||
| 354 | |||
| 355 | /* pass "bank 0" GPIO IRQs to AINTC */ | ||
| 356 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | ||
| 357 | binten = BIT(0); | ||
| 358 | |||
| 359 | /* AINTC handles mask/unmask; GPIO handles triggering */ | ||
| 360 | irq = bank_irq; | ||
| 361 | gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); | ||
| 362 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | ||
| 363 | gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; | ||
| 364 | |||
| 365 | /* default trigger: both edges */ | ||
| 366 | g = gpio2controller(0); | ||
| 367 | __raw_writel(~0, &g->set_falling); | ||
| 368 | __raw_writel(~0, &g->set_rising); | ||
| 369 | |||
| 370 | /* set the direct IRQs up to use that irqchip */ | ||
| 371 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | ||
| 372 | set_irq_chip(irq, &gpio_irqchip_unbanked); | ||
| 373 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | ||
| 374 | set_irq_chip_data(irq, g); | ||
| 375 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; | ||
| 376 | } | ||
| 377 | |||
| 378 | goto done; | ||
| 379 | } | ||
| 380 | |||
| 381 | /* | ||
| 382 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | ||
| 383 | * then chain through our own handler. | ||
| 384 | */ | ||
| 295 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; | 385 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
| 296 | gpio < ngpio; | 386 | gpio < ngpio; |
| 297 | bank++, bank_irq++) { | 387 | bank++, bank_irq++) { |
| 298 | struct gpio_controller *__iomem g = gpio2controller(gpio); | ||
| 299 | unsigned i; | 388 | unsigned i; |
| 300 | 389 | ||
| 390 | /* disabled by default, enabled only as needed */ | ||
| 391 | g = gpio2controller(gpio); | ||
| 301 | __raw_writel(~0, &g->clr_falling); | 392 | __raw_writel(~0, &g->clr_falling); |
| 302 | __raw_writel(~0, &g->clr_rising); | 393 | __raw_writel(~0, &g->clr_rising); |
| 303 | 394 | ||
| @@ -309,6 +400,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
| 309 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { | 400 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
| 310 | set_irq_chip(irq, &gpio_irqchip); | 401 | set_irq_chip(irq, &gpio_irqchip); |
| 311 | set_irq_chip_data(irq, g); | 402 | set_irq_chip_data(irq, g); |
| 403 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | ||
| 312 | set_irq_handler(irq, handle_simple_irq); | 404 | set_irq_handler(irq, handle_simple_irq); |
| 313 | set_irq_flags(irq, IRQF_VALID); | 405 | set_irq_flags(irq, IRQF_VALID); |
| 314 | } | 406 | } |
| @@ -316,6 +408,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
| 316 | binten |= BIT(bank); | 408 | binten |= BIT(bank); |
| 317 | } | 409 | } |
| 318 | 410 | ||
| 411 | done: | ||
| 319 | /* BINTEN -- per-bank interrupt enable. genirq would also let these | 412 | /* BINTEN -- per-bank interrupt enable. genirq would also let these |
| 320 | * bits be set/cleared dynamically. | 413 | * bits be set/cleared dynamically. |
| 321 | */ | 414 | */ |
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index e0abc437d796..18e4ce34ece6 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h | |||
| @@ -5,21 +5,73 @@ | |||
| 5 | #define __ASM_ARCH_DAVINCI_ASP_H | 5 | #define __ASM_ARCH_DAVINCI_ASP_H |
| 6 | 6 | ||
| 7 | #include <mach/irqs.h> | 7 | #include <mach/irqs.h> |
| 8 | #include <mach/edma.h> | ||
| 8 | 9 | ||
| 9 | /* Bases of register banks */ | 10 | /* Bases of dm644x and dm355 register banks */ |
| 10 | #define DAVINCI_ASP0_BASE 0x01E02000 | 11 | #define DAVINCI_ASP0_BASE 0x01E02000 |
| 11 | #define DAVINCI_ASP1_BASE 0x01E04000 | 12 | #define DAVINCI_ASP1_BASE 0x01E04000 |
| 12 | 13 | ||
| 13 | /* EDMA channels */ | 14 | /* Bases of dm646x register banks */ |
| 15 | #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 | ||
| 16 | #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 | ||
| 17 | |||
| 18 | /* Bases of da850/da830 McASP0 register banks */ | ||
| 19 | #define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 | ||
| 20 | |||
| 21 | /* Bases of da830 McASP1 register banks */ | ||
| 22 | #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 | ||
| 23 | |||
| 24 | /* EDMA channels of dm644x and dm355 */ | ||
| 14 | #define DAVINCI_DMA_ASP0_TX 2 | 25 | #define DAVINCI_DMA_ASP0_TX 2 |
| 15 | #define DAVINCI_DMA_ASP0_RX 3 | 26 | #define DAVINCI_DMA_ASP0_RX 3 |
| 16 | #define DAVINCI_DMA_ASP1_TX 8 | 27 | #define DAVINCI_DMA_ASP1_TX 8 |
| 17 | #define DAVINCI_DMA_ASP1_RX 9 | 28 | #define DAVINCI_DMA_ASP1_RX 9 |
| 18 | 29 | ||
| 30 | /* EDMA channels of dm646x */ | ||
| 31 | #define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 | ||
| 32 | #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 | ||
| 33 | #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 | ||
| 34 | |||
| 35 | /* EDMA channels of da850/da830 McASP0 */ | ||
| 36 | #define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 | ||
| 37 | #define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 | ||
| 38 | |||
| 39 | /* EDMA channels of da830 McASP1 */ | ||
| 40 | #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 | ||
| 41 | #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 | ||
| 42 | |||
| 19 | /* Interrupts */ | 43 | /* Interrupts */ |
| 20 | #define DAVINCI_ASP0_RX_INT IRQ_MBRINT | 44 | #define DAVINCI_ASP0_RX_INT IRQ_MBRINT |
| 21 | #define DAVINCI_ASP0_TX_INT IRQ_MBXINT | 45 | #define DAVINCI_ASP0_TX_INT IRQ_MBXINT |
| 22 | #define DAVINCI_ASP1_RX_INT IRQ_MBRINT | 46 | #define DAVINCI_ASP1_RX_INT IRQ_MBRINT |
| 23 | #define DAVINCI_ASP1_TX_INT IRQ_MBXINT | 47 | #define DAVINCI_ASP1_TX_INT IRQ_MBXINT |
| 24 | 48 | ||
| 49 | struct snd_platform_data { | ||
| 50 | u32 tx_dma_offset; | ||
| 51 | u32 rx_dma_offset; | ||
| 52 | enum dma_event_q eventq_no; /* event queue number */ | ||
| 53 | unsigned int codec_fmt; | ||
| 54 | |||
| 55 | /* McASP specific fields */ | ||
| 56 | int tdm_slots; | ||
| 57 | u8 op_mode; | ||
| 58 | u8 num_serializer; | ||
| 59 | u8 *serial_dir; | ||
| 60 | u8 version; | ||
| 61 | u8 txnumevt; | ||
| 62 | u8 rxnumevt; | ||
| 63 | }; | ||
| 64 | |||
| 65 | enum { | ||
| 66 | MCASP_VERSION_1 = 0, /* DM646x */ | ||
| 67 | MCASP_VERSION_2, /* DA8xx/OMAPL1x */ | ||
| 68 | }; | ||
| 69 | |||
| 70 | #define INACTIVE_MODE 0 | ||
| 71 | #define TX_MODE 1 | ||
| 72 | #define RX_MODE 2 | ||
| 73 | |||
| 74 | #define DAVINCI_MCASP_IIS_MODE 0 | ||
| 75 | #define DAVINCI_MCASP_DIT_MODE 1 | ||
| 76 | |||
| 25 | #endif /* __ASM_ARCH_DAVINCI_ASP_H */ | 77 | #endif /* __ASM_ARCH_DAVINCI_ASP_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index a1f03b606d8f..1fd3917cae4e 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h | |||
| @@ -60,10 +60,10 @@ struct davinci_soc_info { | |||
| 60 | u8 *intc_irq_prios; | 60 | u8 *intc_irq_prios; |
| 61 | unsigned long intc_irq_num; | 61 | unsigned long intc_irq_num; |
| 62 | struct davinci_timer_info *timer_info; | 62 | struct davinci_timer_info *timer_info; |
| 63 | void __iomem *wdt_base; | ||
| 64 | void __iomem *gpio_base; | 63 | void __iomem *gpio_base; |
| 65 | unsigned gpio_num; | 64 | unsigned gpio_num; |
| 66 | unsigned gpio_irq; | 65 | unsigned gpio_irq; |
| 66 | unsigned gpio_unbanked; | ||
| 67 | struct platform_device *serial_dev; | 67 | struct platform_device *serial_dev; |
| 68 | struct emac_platform_data *emac_pdata; | 68 | struct emac_platform_data *emac_pdata; |
| 69 | dma_addr_t sram_dma; | 69 | dma_addr_t sram_dma; |
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index d12a5ed2959a..189b1ff13642 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h | |||
| @@ -30,6 +30,9 @@ struct davinci_id { | |||
| 30 | #define DAVINCI_CPU_ID_DM6446 0x64460000 | 30 | #define DAVINCI_CPU_ID_DM6446 0x64460000 |
| 31 | #define DAVINCI_CPU_ID_DM6467 0x64670000 | 31 | #define DAVINCI_CPU_ID_DM6467 0x64670000 |
| 32 | #define DAVINCI_CPU_ID_DM355 0x03550000 | 32 | #define DAVINCI_CPU_ID_DM355 0x03550000 |
| 33 | #define DAVINCI_CPU_ID_DM365 0x03650000 | ||
| 34 | #define DAVINCI_CPU_ID_DA830 0x08300000 | ||
| 35 | #define DAVINCI_CPU_ID_DA850 0x08500000 | ||
| 33 | 36 | ||
| 34 | #define IS_DAVINCI_CPU(type, id) \ | 37 | #define IS_DAVINCI_CPU(type, id) \ |
| 35 | static inline int is_davinci_ ##type(void) \ | 38 | static inline int is_davinci_ ##type(void) \ |
| @@ -40,6 +43,9 @@ static inline int is_davinci_ ##type(void) \ | |||
| 40 | IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) | 43 | IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) |
| 41 | IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) | 44 | IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) |
| 42 | IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) | 45 | IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) |
| 46 | IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) | ||
| 47 | IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) | ||
| 48 | IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) | ||
| 43 | 49 | ||
| 44 | #ifdef CONFIG_ARCH_DAVINCI_DM644x | 50 | #ifdef CONFIG_ARCH_DAVINCI_DM644x |
| 45 | #define cpu_is_davinci_dm644x() is_davinci_dm644x() | 51 | #define cpu_is_davinci_dm644x() is_davinci_dm644x() |
| @@ -59,4 +65,22 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) | |||
| 59 | #define cpu_is_davinci_dm355() 0 | 65 | #define cpu_is_davinci_dm355() 0 |
| 60 | #endif | 66 | #endif |
| 61 | 67 | ||
| 68 | #ifdef CONFIG_ARCH_DAVINCI_DM365 | ||
| 69 | #define cpu_is_davinci_dm365() is_davinci_dm365() | ||
| 70 | #else | ||
| 71 | #define cpu_is_davinci_dm365() 0 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifdef CONFIG_ARCH_DAVINCI_DA830 | ||
| 75 | #define cpu_is_davinci_da830() is_davinci_da830() | ||
| 76 | #else | ||
| 77 | #define cpu_is_davinci_da830() 0 | ||
| 78 | #endif | ||
| 79 | |||
| 80 | #ifdef CONFIG_ARCH_DAVINCI_DA850 | ||
| 81 | #define cpu_is_davinci_da850() is_davinci_da850() | ||
| 82 | #else | ||
| 83 | #define cpu_is_davinci_da850() 0 | ||
| 84 | #endif | ||
| 85 | |||
| 62 | #endif | 86 | #endif |
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 000000000000..d4095d0572c6 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/da8xx.h | |||
| @@ -0,0 +1,121 @@ | |||
| 1 | /* | ||
| 2 | * Chip specific defines for DA8XX/OMAP L1XX SoC | ||
| 3 | * | ||
| 4 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_DAVINCI_DA8XX_H | ||
| 12 | #define __ASM_ARCH_DAVINCI_DA8XX_H | ||
| 13 | |||
| 14 | #include <mach/serial.h> | ||
| 15 | #include <mach/edma.h> | ||
| 16 | #include <mach/i2c.h> | ||
| 17 | #include <mach/emac.h> | ||
| 18 | #include <mach/asp.h> | ||
| 19 | #include <mach/mmc.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * The cp_intc interrupt controller for the da8xx isn't in the same | ||
| 23 | * chunk of physical memory space as the other registers (like it is | ||
| 24 | * on the davincis) so it needs to be mapped separately. It will be | ||
| 25 | * mapped early on when the I/O space is mapped and we'll put it just | ||
| 26 | * before the I/O space in the processor's virtual memory space. | ||
| 27 | */ | ||
| 28 | #define DA8XX_CP_INTC_BASE 0xfffee000 | ||
| 29 | #define DA8XX_CP_INTC_SIZE SZ_8K | ||
| 30 | #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) | ||
| 31 | |||
| 32 | #define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) | ||
| 33 | |||
| 34 | #define DA8XX_PSC0_BASE 0x01c10000 | ||
| 35 | #define DA8XX_PLL0_BASE 0x01c11000 | ||
| 36 | #define DA8XX_JTAG_ID_REG 0x01c14018 | ||
| 37 | #define DA8XX_TIMER64P0_BASE 0x01c20000 | ||
| 38 | #define DA8XX_TIMER64P1_BASE 0x01c21000 | ||
| 39 | #define DA8XX_GPIO_BASE 0x01e26000 | ||
| 40 | #define DA8XX_PSC1_BASE 0x01e27000 | ||
| 41 | #define DA8XX_LCD_CNTRL_BASE 0x01e13000 | ||
| 42 | #define DA8XX_MMCSD0_BASE 0x01c40000 | ||
| 43 | #define DA8XX_AEMIF_CS2_BASE 0x60000000 | ||
| 44 | #define DA8XX_AEMIF_CS3_BASE 0x62000000 | ||
| 45 | #define DA8XX_AEMIF_CTL_BASE 0x68000000 | ||
| 46 | |||
| 47 | #define PINMUX0 0x00 | ||
| 48 | #define PINMUX1 0x04 | ||
| 49 | #define PINMUX2 0x08 | ||
| 50 | #define PINMUX3 0x0c | ||
| 51 | #define PINMUX4 0x10 | ||
| 52 | #define PINMUX5 0x14 | ||
| 53 | #define PINMUX6 0x18 | ||
| 54 | #define PINMUX7 0x1c | ||
| 55 | #define PINMUX8 0x20 | ||
| 56 | #define PINMUX9 0x24 | ||
| 57 | #define PINMUX10 0x28 | ||
| 58 | #define PINMUX11 0x2c | ||
| 59 | #define PINMUX12 0x30 | ||
| 60 | #define PINMUX13 0x34 | ||
| 61 | #define PINMUX14 0x38 | ||
| 62 | #define PINMUX15 0x3c | ||
| 63 | #define PINMUX16 0x40 | ||
| 64 | #define PINMUX17 0x44 | ||
| 65 | #define PINMUX18 0x48 | ||
| 66 | #define PINMUX19 0x4c | ||
| 67 | |||
| 68 | void __init da830_init(void); | ||
| 69 | void __init da850_init(void); | ||
| 70 | |||
| 71 | int da8xx_register_edma(void); | ||
| 72 | int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); | ||
| 73 | int da8xx_register_watchdog(void); | ||
| 74 | int da8xx_register_emac(void); | ||
| 75 | int da8xx_register_lcdc(void); | ||
| 76 | int da8xx_register_mmcsd0(struct davinci_mmc_config *config); | ||
| 77 | void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); | ||
| 78 | |||
| 79 | extern struct platform_device da8xx_serial_device; | ||
| 80 | extern struct emac_platform_data da8xx_emac_pdata; | ||
| 81 | |||
| 82 | extern const short da830_emif25_pins[]; | ||
| 83 | extern const short da830_spi0_pins[]; | ||
| 84 | extern const short da830_spi1_pins[]; | ||
| 85 | extern const short da830_mmc_sd_pins[]; | ||
| 86 | extern const short da830_uart0_pins[]; | ||
| 87 | extern const short da830_uart1_pins[]; | ||
| 88 | extern const short da830_uart2_pins[]; | ||
| 89 | extern const short da830_usb20_pins[]; | ||
| 90 | extern const short da830_usb11_pins[]; | ||
| 91 | extern const short da830_uhpi_pins[]; | ||
| 92 | extern const short da830_cpgmac_pins[]; | ||
| 93 | extern const short da830_emif3c_pins[]; | ||
| 94 | extern const short da830_mcasp0_pins[]; | ||
| 95 | extern const short da830_mcasp1_pins[]; | ||
| 96 | extern const short da830_mcasp2_pins[]; | ||
| 97 | extern const short da830_i2c0_pins[]; | ||
| 98 | extern const short da830_i2c1_pins[]; | ||
| 99 | extern const short da830_lcdcntl_pins[]; | ||
| 100 | extern const short da830_pwm_pins[]; | ||
| 101 | extern const short da830_ecap0_pins[]; | ||
| 102 | extern const short da830_ecap1_pins[]; | ||
| 103 | extern const short da830_ecap2_pins[]; | ||
| 104 | extern const short da830_eqep0_pins[]; | ||
| 105 | extern const short da830_eqep1_pins[]; | ||
| 106 | |||
| 107 | extern const short da850_uart0_pins[]; | ||
| 108 | extern const short da850_uart1_pins[]; | ||
| 109 | extern const short da850_uart2_pins[]; | ||
| 110 | extern const short da850_i2c0_pins[]; | ||
| 111 | extern const short da850_i2c1_pins[]; | ||
| 112 | extern const short da850_cpgmac_pins[]; | ||
| 113 | extern const short da850_mcasp_pins[]; | ||
| 114 | extern const short da850_lcdcntl_pins[]; | ||
| 115 | extern const short da850_mmcsd0_pins[]; | ||
| 116 | extern const short da850_nand_pins[]; | ||
| 117 | extern const short da850_nor_pins[]; | ||
| 118 | |||
| 119 | int da8xx_pinmux_setup(const short pins[]); | ||
| 120 | |||
| 121 | #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index de3fc2182b47..17ab5236da66 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S | |||
| @@ -24,7 +24,15 @@ | |||
| 24 | tst \rx, #1 @ MMU enabled? | 24 | tst \rx, #1 @ MMU enabled? |
| 25 | moveq \rx, #0x01000000 @ physical base address | 25 | moveq \rx, #0x01000000 @ physical base address |
| 26 | movne \rx, #0xfe000000 @ virtual base | 26 | movne \rx, #0xfe000000 @ virtual base |
| 27 | #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) | ||
| 28 | #error Cannot enable DaVinci and DA8XX platforms concurrently | ||
| 29 | #elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ | ||
| 30 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | ||
| 31 | orr \rx, \rx, #0x00d00000 @ physical base address | ||
| 32 | orr \rx, \rx, #0x0000d000 @ of UART 2 | ||
| 33 | #else | ||
| 27 | orr \rx, \rx, #0x00c20000 @ UART 0 | 34 | orr \rx, \rx, #0x00c20000 @ UART 0 |
| 35 | #endif | ||
| 28 | .endm | 36 | .endm |
| 29 | 37 | ||
| 30 | .macro senduart,rd,rx | 38 | .macro senduart,rd,rx |
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h index 54903b72438e..85536d8e8336 100644 --- a/arch/arm/mach-davinci/include/mach/dm355.h +++ b/arch/arm/mach-davinci/include/mach/dm355.h | |||
| @@ -12,11 +12,18 @@ | |||
| 12 | #define __ASM_ARCH_DM355_H | 12 | #define __ASM_ARCH_DM355_H |
| 13 | 13 | ||
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | #include <mach/asp.h> | ||
| 16 | #include <media/davinci/vpfe_capture.h> | ||
| 17 | |||
| 18 | #define ASP1_TX_EVT_EN 1 | ||
| 19 | #define ASP1_RX_EVT_EN 2 | ||
| 15 | 20 | ||
| 16 | struct spi_board_info; | 21 | struct spi_board_info; |
| 17 | 22 | ||
| 18 | void __init dm355_init(void); | 23 | void __init dm355_init(void); |
| 19 | void dm355_init_spi0(unsigned chipselect_mask, | 24 | void dm355_init_spi0(unsigned chipselect_mask, |
| 20 | struct spi_board_info *info, unsigned len); | 25 | struct spi_board_info *info, unsigned len); |
| 26 | void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); | ||
| 27 | void dm355_set_vpfe_config(struct vpfe_config *cfg); | ||
| 21 | 28 | ||
| 22 | #endif /* __ASM_ARCH_DM355_H */ | 29 | #endif /* __ASM_ARCH_DM355_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h new file mode 100644 index 000000000000..09db4343bb4c --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm365.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Texas Instruments Incorporated | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License as | ||
| 6 | * published by the Free Software Foundation version 2. | ||
| 7 | * | ||
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 9 | * kind, whether express or implied; without even the implied warranty | ||
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARCH_DM365_H | ||
| 14 | #define __ASM_ARCH_DM665_H | ||
| 15 | |||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | #include <mach/emac.h> | ||
| 19 | |||
| 20 | #define DM365_EMAC_BASE (0x01D07000) | ||
| 21 | #define DM365_EMAC_CNTRL_OFFSET (0x0000) | ||
| 22 | #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) | ||
| 23 | #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) | ||
| 24 | #define DM365_EMAC_MDIO_OFFSET (0x4000) | ||
| 25 | #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) | ||
| 26 | |||
| 27 | void __init dm365_init(void); | ||
| 28 | |||
| 29 | #endif /* __ASM_ARCH_DM365_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 15d42b92a8c9..0efb73852c2c 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
| 26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 27 | #include <mach/emac.h> | 27 | #include <mach/emac.h> |
| 28 | #include <mach/asp.h> | ||
| 29 | #include <media/davinci/vpfe_capture.h> | ||
| 28 | 30 | ||
| 29 | #define DM644X_EMAC_BASE (0x01C80000) | 31 | #define DM644X_EMAC_BASE (0x01C80000) |
| 30 | #define DM644X_EMAC_CNTRL_OFFSET (0x0000) | 32 | #define DM644X_EMAC_CNTRL_OFFSET (0x0000) |
| @@ -34,5 +36,7 @@ | |||
| 34 | #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) | 36 | #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) |
| 35 | 37 | ||
| 36 | void __init dm644x_init(void); | 38 | void __init dm644x_init(void); |
| 39 | void __init dm644x_init_asp(struct snd_platform_data *pdata); | ||
| 40 | void dm644x_set_vpfe_config(struct vpfe_config *cfg); | ||
| 37 | 41 | ||
| 38 | #endif /* __ASM_ARCH_DM644X_H */ | 42 | #endif /* __ASM_ARCH_DM644X_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 1fc764c8646e..8cec746ae9d2 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h | |||
| @@ -13,6 +13,9 @@ | |||
| 13 | 13 | ||
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | #include <mach/emac.h> | 15 | #include <mach/emac.h> |
| 16 | #include <mach/asp.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | #include <linux/videodev2.h> | ||
| 16 | 19 | ||
| 17 | #define DM646X_EMAC_BASE (0x01C80000) | 20 | #define DM646X_EMAC_BASE (0x01C80000) |
| 18 | #define DM646X_EMAC_CNTRL_OFFSET (0x0000) | 21 | #define DM646X_EMAC_CNTRL_OFFSET (0x0000) |
| @@ -21,6 +24,68 @@ | |||
| 21 | #define DM646X_EMAC_MDIO_OFFSET (0x4000) | 24 | #define DM646X_EMAC_MDIO_OFFSET (0x4000) |
| 22 | #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) | 25 | #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) |
| 23 | 26 | ||
| 27 | #define DM646X_ATA_REG_BASE (0x01C66000) | ||
| 28 | |||
| 24 | void __init dm646x_init(void); | 29 | void __init dm646x_init(void); |
| 30 | void __init dm646x_init_ide(void); | ||
| 31 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); | ||
| 32 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); | ||
| 33 | |||
| 34 | void dm646x_video_init(void); | ||
| 35 | |||
| 36 | enum vpif_if_type { | ||
| 37 | VPIF_IF_BT656, | ||
| 38 | VPIF_IF_BT1120, | ||
| 39 | VPIF_IF_RAW_BAYER | ||
| 40 | }; | ||
| 41 | |||
| 42 | struct vpif_interface { | ||
| 43 | enum vpif_if_type if_type; | ||
| 44 | unsigned hd_pol:1; | ||
| 45 | unsigned vd_pol:1; | ||
| 46 | unsigned fid_pol:1; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct vpif_subdev_info { | ||
| 50 | const char *name; | ||
| 51 | struct i2c_board_info board_info; | ||
| 52 | u32 input; | ||
| 53 | u32 output; | ||
| 54 | unsigned can_route:1; | ||
| 55 | struct vpif_interface vpif_if; | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct vpif_display_config { | ||
| 59 | int (*set_clock)(int, int); | ||
| 60 | struct vpif_subdev_info *subdevinfo; | ||
| 61 | int subdev_count; | ||
| 62 | const char **output; | ||
| 63 | int output_count; | ||
| 64 | const char *card_name; | ||
| 65 | }; | ||
| 66 | |||
| 67 | struct vpif_input { | ||
| 68 | struct v4l2_input input; | ||
| 69 | const char *subdev_name; | ||
| 70 | }; | ||
| 71 | |||
| 72 | #define VPIF_CAPTURE_MAX_CHANNELS 2 | ||
| 73 | |||
| 74 | struct vpif_capture_chan_config { | ||
| 75 | const struct vpif_input *inputs; | ||
| 76 | int input_count; | ||
| 77 | }; | ||
| 78 | |||
| 79 | struct vpif_capture_config { | ||
| 80 | int (*setup_input_channel_mode)(int); | ||
| 81 | int (*setup_input_path)(int, const char *); | ||
| 82 | struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; | ||
| 83 | struct vpif_subdev_info *subdev_info; | ||
| 84 | int subdev_count; | ||
| 85 | const char *card_name; | ||
| 86 | }; | ||
| 87 | |||
| 88 | void dm646x_setup_vpif(struct vpif_display_config *, | ||
| 89 | struct vpif_capture_config *); | ||
| 25 | 90 | ||
| 26 | #endif /* __ASM_ARCH_DM646X_H */ | 91 | #endif /* __ASM_ARCH_DM646X_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 24a379239d7f..eb8bfd7925e7 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h | |||
| @@ -139,6 +139,54 @@ struct edmacc_param { | |||
| 139 | #define DAVINCI_DMA_PWM1 53 | 139 | #define DAVINCI_DMA_PWM1 53 |
| 140 | #define DAVINCI_DMA_PWM2 54 | 140 | #define DAVINCI_DMA_PWM2 54 |
| 141 | 141 | ||
| 142 | /* DA830 specific EDMA3 information */ | ||
| 143 | #define EDMA_DA830_NUM_DMACH 32 | ||
| 144 | #define EDMA_DA830_NUM_TCC 32 | ||
| 145 | #define EDMA_DA830_NUM_PARAMENTRY 128 | ||
| 146 | #define EDMA_DA830_NUM_EVQUE 2 | ||
| 147 | #define EDMA_DA830_NUM_TC 2 | ||
| 148 | #define EDMA_DA830_CHMAP_EXIST 0 | ||
| 149 | #define EDMA_DA830_NUM_REGIONS 4 | ||
| 150 | #define DA830_DMACH2EVENT_MAP0 0x000FC03Fu | ||
| 151 | #define DA830_DMACH2EVENT_MAP1 0x00000000u | ||
| 152 | #define DA830_EDMA_ARM_OWN 0x30FFCCFFu | ||
| 153 | |||
| 154 | /* DA830 specific EDMA3 Events Information */ | ||
| 155 | enum DA830_edma_ch { | ||
| 156 | DA830_DMACH_MCASP0_RX, | ||
| 157 | DA830_DMACH_MCASP0_TX, | ||
| 158 | DA830_DMACH_MCASP1_RX, | ||
| 159 | DA830_DMACH_MCASP1_TX, | ||
| 160 | DA830_DMACH_MCASP2_RX, | ||
| 161 | DA830_DMACH_MCASP2_TX, | ||
| 162 | DA830_DMACH_GPIO_BNK0INT, | ||
| 163 | DA830_DMACH_GPIO_BNK1INT, | ||
| 164 | DA830_DMACH_UART0_RX, | ||
| 165 | DA830_DMACH_UART0_TX, | ||
| 166 | DA830_DMACH_TMR64P0_EVTOUT12, | ||
| 167 | DA830_DMACH_TMR64P0_EVTOUT34, | ||
| 168 | DA830_DMACH_UART1_RX, | ||
| 169 | DA830_DMACH_UART1_TX, | ||
| 170 | DA830_DMACH_SPI0_RX, | ||
| 171 | DA830_DMACH_SPI0_TX, | ||
| 172 | DA830_DMACH_MMCSD_RX, | ||
| 173 | DA830_DMACH_MMCSD_TX, | ||
| 174 | DA830_DMACH_SPI1_RX, | ||
| 175 | DA830_DMACH_SPI1_TX, | ||
| 176 | DA830_DMACH_DMAX_EVTOUT6, | ||
| 177 | DA830_DMACH_DMAX_EVTOUT7, | ||
| 178 | DA830_DMACH_GPIO_BNK2INT, | ||
| 179 | DA830_DMACH_GPIO_BNK3INT, | ||
| 180 | DA830_DMACH_I2C0_RX, | ||
| 181 | DA830_DMACH_I2C0_TX, | ||
| 182 | DA830_DMACH_I2C1_RX, | ||
| 183 | DA830_DMACH_I2C1_TX, | ||
| 184 | DA830_DMACH_GPIO_BNK4INT, | ||
| 185 | DA830_DMACH_GPIO_BNK5INT, | ||
| 186 | DA830_DMACH_UART2_RX, | ||
| 187 | DA830_DMACH_UART2_TX | ||
| 188 | }; | ||
| 189 | |||
| 142 | /*ch_status paramater of callback function possible values*/ | 190 | /*ch_status paramater of callback function possible values*/ |
| 143 | #define DMA_COMPLETE 1 | 191 | #define DMA_COMPLETE 1 |
| 144 | #define DMA_CC_ERROR 2 | 192 | #define DMA_CC_ERROR 2 |
| @@ -162,6 +210,8 @@ enum fifo_width { | |||
| 162 | enum dma_event_q { | 210 | enum dma_event_q { |
| 163 | EVENTQ_0 = 0, | 211 | EVENTQ_0 = 0, |
| 164 | EVENTQ_1 = 1, | 212 | EVENTQ_1 = 1, |
| 213 | EVENTQ_2 = 2, | ||
| 214 | EVENTQ_3 = 3, | ||
| 165 | EVENTQ_DEFAULT = -1 | 215 | EVENTQ_DEFAULT = -1 |
| 166 | }; | 216 | }; |
| 167 | 217 | ||
| @@ -170,8 +220,15 @@ enum sync_dimension { | |||
| 170 | ABSYNC = 1 | 220 | ABSYNC = 1 |
| 171 | }; | 221 | }; |
| 172 | 222 | ||
| 223 | #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) | ||
| 224 | #define EDMA_CTLR(i) ((i) >> 16) | ||
| 225 | #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) | ||
| 226 | |||
| 173 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ | 227 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ |
| 174 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ | 228 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ |
| 229 | #define EDMA_CONT_PARAMS_ANY 1001 | ||
| 230 | #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 | ||
| 231 | #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 | ||
| 175 | 232 | ||
| 176 | /* alloc/free DMA channels and their dedicated parameter RAM slots */ | 233 | /* alloc/free DMA channels and their dedicated parameter RAM slots */ |
| 177 | int edma_alloc_channel(int channel, | 234 | int edma_alloc_channel(int channel, |
| @@ -180,9 +237,13 @@ int edma_alloc_channel(int channel, | |||
| 180 | void edma_free_channel(unsigned channel); | 237 | void edma_free_channel(unsigned channel); |
| 181 | 238 | ||
| 182 | /* alloc/free parameter RAM slots */ | 239 | /* alloc/free parameter RAM slots */ |
| 183 | int edma_alloc_slot(int slot); | 240 | int edma_alloc_slot(unsigned ctlr, int slot); |
| 184 | void edma_free_slot(unsigned slot); | 241 | void edma_free_slot(unsigned slot); |
| 185 | 242 | ||
| 243 | /* alloc/free a set of contiguous parameter RAM slots */ | ||
| 244 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); | ||
| 245 | int edma_free_cont_slots(unsigned slot, int count); | ||
| 246 | |||
| 186 | /* calls that operate on part of a parameter RAM slot */ | 247 | /* calls that operate on part of a parameter RAM slot */ |
| 187 | void edma_set_src(unsigned slot, dma_addr_t src_port, | 248 | void edma_set_src(unsigned slot, dma_addr_t src_port, |
| 188 | enum address_mode mode, enum fifo_width); | 249 | enum address_mode mode, enum fifo_width); |
| @@ -216,9 +277,13 @@ struct edma_soc_info { | |||
| 216 | unsigned n_region; | 277 | unsigned n_region; |
| 217 | unsigned n_slot; | 278 | unsigned n_slot; |
| 218 | unsigned n_tc; | 279 | unsigned n_tc; |
| 280 | unsigned n_cc; | ||
| 281 | enum dma_event_q default_queue; | ||
| 219 | 282 | ||
| 220 | /* list of channels with no even trigger; terminated by "-1" */ | 283 | /* list of channels with no even trigger; terminated by "-1" */ |
| 221 | const s8 *noevent; | 284 | const s8 *noevent; |
| 285 | const s8 (*queue_tc_mapping)[2]; | ||
| 286 | const s8 (*queue_priority_mapping)[2]; | ||
| 222 | }; | 287 | }; |
| 223 | 288 | ||
| 224 | #endif | 289 | #endif |
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index ae0745568316..f3b8ef878158 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h | |||
| @@ -42,6 +42,9 @@ | |||
| 42 | */ | 42 | */ |
| 43 | #define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ | 43 | #define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ |
| 44 | 44 | ||
| 45 | /* Convert GPIO signal to GPIO pin number */ | ||
| 46 | #define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) | ||
| 47 | |||
| 45 | struct gpio_controller { | 48 | struct gpio_controller { |
| 46 | u32 dir; | 49 | u32 dir; |
| 47 | u32 out_data; | 50 | u32 out_data; |
| @@ -78,6 +81,8 @@ __gpio_to_controller(unsigned gpio) | |||
| 78 | ptr = base + 0x60; | 81 | ptr = base + 0x60; |
| 79 | else if (gpio < 32 * 4) | 82 | else if (gpio < 32 * 4) |
| 80 | ptr = base + 0x88; | 83 | ptr = base + 0x88; |
| 84 | else if (gpio < 32 * 5) | ||
| 85 | ptr = base + 0xb0; | ||
| 81 | else | 86 | else |
| 82 | ptr = NULL; | 87 | ptr = NULL; |
| 83 | return ptr; | 88 | return ptr; |
| @@ -142,15 +147,13 @@ static inline int gpio_cansleep(unsigned gpio) | |||
| 142 | 147 | ||
| 143 | static inline int gpio_to_irq(unsigned gpio) | 148 | static inline int gpio_to_irq(unsigned gpio) |
| 144 | { | 149 | { |
| 145 | if (gpio >= DAVINCI_N_GPIO) | 150 | return __gpio_to_irq(gpio); |
| 146 | return -EINVAL; | ||
| 147 | return davinci_soc_info.intc_irq_num + gpio; | ||
| 148 | } | 151 | } |
| 149 | 152 | ||
| 150 | static inline int irq_to_gpio(unsigned irq) | 153 | static inline int irq_to_gpio(unsigned irq) |
| 151 | { | 154 | { |
| 152 | /* caller guarantees gpio_to_irq() succeeded */ | 155 | /* don't support the reverse mapping */ |
| 153 | return irq - davinci_soc_info.intc_irq_num; | 156 | return -ENOSYS; |
| 154 | } | 157 | } |
| 155 | 158 | ||
| 156 | #endif /* __DAVINCI_GPIO_H */ | 159 | #endif /* __DAVINCI_GPIO_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index 48c77934d519..41c89386e39b 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h | |||
| @@ -24,4 +24,21 @@ | |||
| 24 | /* System control register offsets */ | 24 | /* System control register offsets */ |
| 25 | #define DM64XX_VDD3P3V_PWDN 0x48 | 25 | #define DM64XX_VDD3P3V_PWDN 0x48 |
| 26 | 26 | ||
| 27 | /* | ||
| 28 | * I/O mapping | ||
| 29 | */ | ||
| 30 | #define IO_PHYS 0x01c00000 | ||
| 31 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ | ||
| 32 | #define IO_SIZE 0x00400000 | ||
| 33 | #define IO_VIRT (IO_PHYS + IO_OFFSET) | ||
| 34 | #define io_v2p(va) ((va) - IO_OFFSET) | ||
| 35 | #define __IO_ADDRESS(x) ((x) + IO_OFFSET) | ||
| 36 | #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) | ||
| 37 | |||
| 38 | #ifdef __ASSEMBLER__ | ||
| 39 | #define IOMEM(x) x | ||
| 40 | #else | ||
| 41 | #define IOMEM(x) ((void __force __iomem *)(x)) | ||
| 42 | #endif | ||
| 43 | |||
| 27 | #endif /* __ASM_ARCH_HARDWARE_H */ | 44 | #endif /* __ASM_ARCH_HARDWARE_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index 2479785405af..62b0a90309ad 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h | |||
| @@ -14,18 +14,6 @@ | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | 14 | #define IO_SPACE_LIMIT 0xffffffff |
| 15 | 15 | ||
| 16 | /* | 16 | /* |
| 17 | * ---------------------------------------------------------------------------- | ||
| 18 | * I/O mapping | ||
| 19 | * ---------------------------------------------------------------------------- | ||
| 20 | */ | ||
| 21 | #define IO_PHYS 0x01c00000 | ||
| 22 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ | ||
| 23 | #define IO_SIZE 0x00400000 | ||
| 24 | #define IO_VIRT (IO_PHYS + IO_OFFSET) | ||
| 25 | #define io_v2p(va) ((va) - IO_OFFSET) | ||
| 26 | #define __IO_ADDRESS(x) ((x) + IO_OFFSET) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * We don't actually have real ISA nor PCI buses, but there is so many | 17 | * We don't actually have real ISA nor PCI buses, but there is so many |
| 30 | * drivers out there that might just work if we fake them... | 18 | * drivers out there that might just work if we fake them... |
| 31 | */ | 19 | */ |
| @@ -33,19 +21,12 @@ | |||
| 33 | #define __mem_pci(a) (a) | 21 | #define __mem_pci(a) (a) |
| 34 | #define __mem_isa(a) (a) | 22 | #define __mem_isa(a) (a) |
| 35 | 23 | ||
| 36 | #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) | 24 | #ifndef __ASSEMBLER__ |
| 37 | |||
| 38 | #ifdef __ASSEMBLER__ | ||
| 39 | #define IOMEM(x) x | ||
| 40 | #else | ||
| 41 | #define IOMEM(x) ((void __force __iomem *)(x)) | ||
| 42 | |||
| 43 | #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) | 25 | #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) |
| 44 | #define __arch_iounmap(v) davinci_iounmap(v) | 26 | #define __arch_iounmap(v) davinci_iounmap(v) |
| 45 | 27 | ||
| 46 | void __iomem *davinci_ioremap(unsigned long phys, size_t size, | 28 | void __iomem *davinci_ioremap(unsigned long phys, size_t size, |
| 47 | unsigned int type); | 29 | unsigned int type); |
| 48 | void davinci_iounmap(volatile void __iomem *addr); | 30 | void davinci_iounmap(volatile void __iomem *addr); |
| 49 | 31 | #endif | |
| 50 | #endif /* __ASSEMBLER__ */ | ||
| 51 | #endif /* __ASM_ARCH_IO_H */ | 32 | #endif /* __ASM_ARCH_IO_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index bc5d6aaa69a3..3c918a772619 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h | |||
| @@ -99,9 +99,6 @@ | |||
| 99 | #define IRQ_EMUINT 63 | 99 | #define IRQ_EMUINT 63 |
| 100 | 100 | ||
| 101 | #define DAVINCI_N_AINTC_IRQ 64 | 101 | #define DAVINCI_N_AINTC_IRQ 64 |
| 102 | #define DAVINCI_N_GPIO 104 | ||
| 103 | |||
| 104 | #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) | ||
| 105 | 102 | ||
| 106 | #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 | 103 | #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 |
| 107 | 104 | ||
| @@ -206,4 +203,206 @@ | |||
| 206 | #define IRQ_DM355_GPIOBNK5 59 | 203 | #define IRQ_DM355_GPIOBNK5 59 |
| 207 | #define IRQ_DM355_GPIOBNK6 60 | 204 | #define IRQ_DM355_GPIOBNK6 60 |
| 208 | 205 | ||
| 206 | /* DaVinci DM365-specific Interrupts */ | ||
| 207 | #define IRQ_DM365_INSFINT 7 | ||
| 208 | #define IRQ_DM365_IMXINT1 8 | ||
| 209 | #define IRQ_DM365_IMXINT0 10 | ||
| 210 | #define IRQ_DM365_KLD_ARMINT 10 | ||
| 211 | #define IRQ_DM365_IMCOPINT 11 | ||
| 212 | #define IRQ_DM365_RTOINT 13 | ||
| 213 | #define IRQ_DM365_TINT5 14 | ||
| 214 | #define IRQ_DM365_TINT6 15 | ||
| 215 | #define IRQ_DM365_SPINT2_1 21 | ||
| 216 | #define IRQ_DM365_TINT7 22 | ||
| 217 | #define IRQ_DM365_SDIOINT0 23 | ||
| 218 | #define IRQ_DM365_MMCINT1 27 | ||
| 219 | #define IRQ_DM365_PWMINT3 28 | ||
| 220 | #define IRQ_DM365_SDIOINT1 31 | ||
| 221 | #define IRQ_DM365_SPIINT0_0 42 | ||
| 222 | #define IRQ_DM365_SPIINT3_0 43 | ||
| 223 | #define IRQ_DM365_GPIO0 44 | ||
| 224 | #define IRQ_DM365_GPIO1 45 | ||
| 225 | #define IRQ_DM365_GPIO2 46 | ||
| 226 | #define IRQ_DM365_GPIO3 47 | ||
| 227 | #define IRQ_DM365_GPIO4 48 | ||
| 228 | #define IRQ_DM365_GPIO5 49 | ||
| 229 | #define IRQ_DM365_GPIO6 50 | ||
| 230 | #define IRQ_DM365_GPIO7 51 | ||
| 231 | #define IRQ_DM365_EMAC_RXTHRESH 52 | ||
| 232 | #define IRQ_DM365_EMAC_RXPULSE 53 | ||
| 233 | #define IRQ_DM365_EMAC_TXPULSE 54 | ||
| 234 | #define IRQ_DM365_EMAC_MISCPULSE 55 | ||
| 235 | #define IRQ_DM365_GPIO12 56 | ||
| 236 | #define IRQ_DM365_GPIO13 57 | ||
| 237 | #define IRQ_DM365_GPIO14 58 | ||
| 238 | #define IRQ_DM365_GPIO15 59 | ||
| 239 | #define IRQ_DM365_ADCINT 59 | ||
| 240 | #define IRQ_DM365_KEYINT 60 | ||
| 241 | #define IRQ_DM365_TCERRINT2 61 | ||
| 242 | #define IRQ_DM365_TCERRINT3 62 | ||
| 243 | #define IRQ_DM365_EMUINT 63 | ||
| 244 | |||
| 245 | /* DA8XX interrupts */ | ||
| 246 | #define IRQ_DA8XX_COMMTX 0 | ||
| 247 | #define IRQ_DA8XX_COMMRX 1 | ||
| 248 | #define IRQ_DA8XX_NINT 2 | ||
| 249 | #define IRQ_DA8XX_EVTOUT0 3 | ||
| 250 | #define IRQ_DA8XX_EVTOUT1 4 | ||
| 251 | #define IRQ_DA8XX_EVTOUT2 5 | ||
| 252 | #define IRQ_DA8XX_EVTOUT3 6 | ||
| 253 | #define IRQ_DA8XX_EVTOUT4 7 | ||
| 254 | #define IRQ_DA8XX_EVTOUT5 8 | ||
| 255 | #define IRQ_DA8XX_EVTOUT6 9 | ||
| 256 | #define IRQ_DA8XX_EVTOUT7 10 | ||
| 257 | #define IRQ_DA8XX_CCINT0 11 | ||
| 258 | #define IRQ_DA8XX_CCERRINT 12 | ||
| 259 | #define IRQ_DA8XX_TCERRINT0 13 | ||
| 260 | #define IRQ_DA8XX_AEMIFINT 14 | ||
| 261 | #define IRQ_DA8XX_I2CINT0 15 | ||
| 262 | #define IRQ_DA8XX_MMCSDINT0 16 | ||
| 263 | #define IRQ_DA8XX_MMCSDINT1 17 | ||
| 264 | #define IRQ_DA8XX_ALLINT0 18 | ||
| 265 | #define IRQ_DA8XX_RTC 19 | ||
| 266 | #define IRQ_DA8XX_SPINT0 20 | ||
| 267 | #define IRQ_DA8XX_TINT12_0 21 | ||
| 268 | #define IRQ_DA8XX_TINT34_0 22 | ||
| 269 | #define IRQ_DA8XX_TINT12_1 23 | ||
| 270 | #define IRQ_DA8XX_TINT34_1 24 | ||
| 271 | #define IRQ_DA8XX_UARTINT0 25 | ||
| 272 | #define IRQ_DA8XX_KEYMGRINT 26 | ||
| 273 | #define IRQ_DA8XX_SECINT 26 | ||
| 274 | #define IRQ_DA8XX_SECKEYERR 26 | ||
| 275 | #define IRQ_DA8XX_CHIPINT0 28 | ||
| 276 | #define IRQ_DA8XX_CHIPINT1 29 | ||
| 277 | #define IRQ_DA8XX_CHIPINT2 30 | ||
| 278 | #define IRQ_DA8XX_CHIPINT3 31 | ||
| 279 | #define IRQ_DA8XX_TCERRINT1 32 | ||
| 280 | #define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 | ||
| 281 | #define IRQ_DA8XX_C0_RX_PULSE 34 | ||
| 282 | #define IRQ_DA8XX_C0_TX_PULSE 35 | ||
| 283 | #define IRQ_DA8XX_C0_MISC_PULSE 36 | ||
| 284 | #define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 | ||
| 285 | #define IRQ_DA8XX_C1_RX_PULSE 38 | ||
| 286 | #define IRQ_DA8XX_C1_TX_PULSE 39 | ||
| 287 | #define IRQ_DA8XX_C1_MISC_PULSE 40 | ||
| 288 | #define IRQ_DA8XX_MEMERR 41 | ||
| 289 | #define IRQ_DA8XX_GPIO0 42 | ||
| 290 | #define IRQ_DA8XX_GPIO1 43 | ||
| 291 | #define IRQ_DA8XX_GPIO2 44 | ||
| 292 | #define IRQ_DA8XX_GPIO3 45 | ||
| 293 | #define IRQ_DA8XX_GPIO4 46 | ||
| 294 | #define IRQ_DA8XX_GPIO5 47 | ||
| 295 | #define IRQ_DA8XX_GPIO6 48 | ||
| 296 | #define IRQ_DA8XX_GPIO7 49 | ||
| 297 | #define IRQ_DA8XX_GPIO8 50 | ||
| 298 | #define IRQ_DA8XX_I2CINT1 51 | ||
| 299 | #define IRQ_DA8XX_LCDINT 52 | ||
| 300 | #define IRQ_DA8XX_UARTINT1 53 | ||
| 301 | #define IRQ_DA8XX_MCASPINT 54 | ||
| 302 | #define IRQ_DA8XX_ALLINT1 55 | ||
| 303 | #define IRQ_DA8XX_SPINT1 56 | ||
| 304 | #define IRQ_DA8XX_UHPI_INT1 57 | ||
| 305 | #define IRQ_DA8XX_USB_INT 58 | ||
| 306 | #define IRQ_DA8XX_IRQN 59 | ||
| 307 | #define IRQ_DA8XX_RWAKEUP 60 | ||
| 308 | #define IRQ_DA8XX_UARTINT2 61 | ||
| 309 | #define IRQ_DA8XX_DFTSSINT 62 | ||
| 310 | #define IRQ_DA8XX_EHRPWM0 63 | ||
| 311 | #define IRQ_DA8XX_EHRPWM0TZ 64 | ||
| 312 | #define IRQ_DA8XX_EHRPWM1 65 | ||
| 313 | #define IRQ_DA8XX_EHRPWM1TZ 66 | ||
| 314 | #define IRQ_DA8XX_ECAP0 69 | ||
| 315 | #define IRQ_DA8XX_ECAP1 70 | ||
| 316 | #define IRQ_DA8XX_ECAP2 71 | ||
| 317 | #define IRQ_DA8XX_ARMCLKSTOPREQ 90 | ||
| 318 | |||
| 319 | /* DA830 specific interrupts */ | ||
| 320 | #define IRQ_DA830_MPUERR 27 | ||
| 321 | #define IRQ_DA830_IOPUERR 27 | ||
| 322 | #define IRQ_DA830_BOOTCFGERR 27 | ||
| 323 | #define IRQ_DA830_EHRPWM2 67 | ||
| 324 | #define IRQ_DA830_EHRPWM2TZ 68 | ||
| 325 | #define IRQ_DA830_EQEP0 72 | ||
| 326 | #define IRQ_DA830_EQEP1 73 | ||
| 327 | #define IRQ_DA830_T12CMPINT0_0 74 | ||
| 328 | #define IRQ_DA830_T12CMPINT1_0 75 | ||
| 329 | #define IRQ_DA830_T12CMPINT2_0 76 | ||
| 330 | #define IRQ_DA830_T12CMPINT3_0 77 | ||
| 331 | #define IRQ_DA830_T12CMPINT4_0 78 | ||
| 332 | #define IRQ_DA830_T12CMPINT5_0 79 | ||
| 333 | #define IRQ_DA830_T12CMPINT6_0 80 | ||
| 334 | #define IRQ_DA830_T12CMPINT7_0 81 | ||
| 335 | #define IRQ_DA830_T12CMPINT0_1 82 | ||
| 336 | #define IRQ_DA830_T12CMPINT1_1 83 | ||
| 337 | #define IRQ_DA830_T12CMPINT2_1 84 | ||
| 338 | #define IRQ_DA830_T12CMPINT3_1 85 | ||
| 339 | #define IRQ_DA830_T12CMPINT4_1 86 | ||
| 340 | #define IRQ_DA830_T12CMPINT5_1 87 | ||
| 341 | #define IRQ_DA830_T12CMPINT6_1 88 | ||
| 342 | #define IRQ_DA830_T12CMPINT7_1 89 | ||
| 343 | |||
| 344 | #define DA830_N_CP_INTC_IRQ 96 | ||
| 345 | |||
| 346 | /* DA850 speicific interrupts */ | ||
| 347 | #define IRQ_DA850_MPUADDRERR0 27 | ||
| 348 | #define IRQ_DA850_MPUPROTERR0 27 | ||
| 349 | #define IRQ_DA850_IOPUADDRERR0 27 | ||
| 350 | #define IRQ_DA850_IOPUPROTERR0 27 | ||
| 351 | #define IRQ_DA850_IOPUADDRERR1 27 | ||
| 352 | #define IRQ_DA850_IOPUPROTERR1 27 | ||
| 353 | #define IRQ_DA850_IOPUADDRERR2 27 | ||
| 354 | #define IRQ_DA850_IOPUPROTERR2 27 | ||
| 355 | #define IRQ_DA850_BOOTCFG_ADDR_ERR 27 | ||
| 356 | #define IRQ_DA850_BOOTCFG_PROT_ERR 27 | ||
| 357 | #define IRQ_DA850_MPUADDRERR1 27 | ||
| 358 | #define IRQ_DA850_MPUPROTERR1 27 | ||
| 359 | #define IRQ_DA850_IOPUADDRERR3 27 | ||
| 360 | #define IRQ_DA850_IOPUPROTERR3 27 | ||
| 361 | #define IRQ_DA850_IOPUADDRERR4 27 | ||
| 362 | #define IRQ_DA850_IOPUPROTERR4 27 | ||
| 363 | #define IRQ_DA850_IOPUADDRERR5 27 | ||
| 364 | #define IRQ_DA850_IOPUPROTERR5 27 | ||
| 365 | #define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 | ||
| 366 | #define IRQ_DA850_SATAINT 67 | ||
| 367 | #define IRQ_DA850_TINT12_2 68 | ||
| 368 | #define IRQ_DA850_TINT34_2 68 | ||
| 369 | #define IRQ_DA850_TINTALL_2 68 | ||
| 370 | #define IRQ_DA850_MMCSDINT0_1 72 | ||
| 371 | #define IRQ_DA850_MMCSDINT1_1 73 | ||
| 372 | #define IRQ_DA850_T12CMPINT0_2 74 | ||
| 373 | #define IRQ_DA850_T12CMPINT1_2 75 | ||
| 374 | #define IRQ_DA850_T12CMPINT2_2 76 | ||
| 375 | #define IRQ_DA850_T12CMPINT3_2 77 | ||
| 376 | #define IRQ_DA850_T12CMPINT4_2 78 | ||
| 377 | #define IRQ_DA850_T12CMPINT5_2 79 | ||
| 378 | #define IRQ_DA850_T12CMPINT6_2 80 | ||
| 379 | #define IRQ_DA850_T12CMPINT7_2 81 | ||
| 380 | #define IRQ_DA850_T12CMPINT0_3 82 | ||
| 381 | #define IRQ_DA850_T12CMPINT1_3 83 | ||
| 382 | #define IRQ_DA850_T12CMPINT2_3 84 | ||
| 383 | #define IRQ_DA850_T12CMPINT3_3 85 | ||
| 384 | #define IRQ_DA850_T12CMPINT4_3 86 | ||
| 385 | #define IRQ_DA850_T12CMPINT5_3 87 | ||
| 386 | #define IRQ_DA850_T12CMPINT6_3 88 | ||
| 387 | #define IRQ_DA850_T12CMPINT7_3 89 | ||
| 388 | #define IRQ_DA850_RPIINT 91 | ||
| 389 | #define IRQ_DA850_VPIFINT 92 | ||
| 390 | #define IRQ_DA850_CCINT1 93 | ||
| 391 | #define IRQ_DA850_CCERRINT1 94 | ||
| 392 | #define IRQ_DA850_TCERRINT2 95 | ||
| 393 | #define IRQ_DA850_TINT12_3 96 | ||
| 394 | #define IRQ_DA850_TINT34_3 96 | ||
| 395 | #define IRQ_DA850_TINTALL_3 96 | ||
| 396 | #define IRQ_DA850_MCBSP0RINT 97 | ||
| 397 | #define IRQ_DA850_MCBSP0XINT 98 | ||
| 398 | #define IRQ_DA850_MCBSP1RINT 99 | ||
| 399 | #define IRQ_DA850_MCBSP1XINT 100 | ||
| 400 | |||
| 401 | #define DA850_N_CP_INTC_IRQ 101 | ||
| 402 | |||
| 403 | /* da850 currently has the most gpio pins (144) */ | ||
| 404 | #define DAVINCI_N_GPIO 144 | ||
| 405 | /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ | ||
| 406 | #define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) | ||
| 407 | |||
| 209 | #endif /* __ASM_ARCH_IRQS_H */ | 408 | #endif /* __ASM_ARCH_IRQS_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index c712c7cdf38f..80309aed534a 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h | |||
| @@ -20,9 +20,16 @@ | |||
| 20 | /************************************************************************** | 20 | /************************************************************************** |
| 21 | * Definitions | 21 | * Definitions |
| 22 | **************************************************************************/ | 22 | **************************************************************************/ |
| 23 | #define DAVINCI_DDR_BASE 0x80000000 | 23 | #define DAVINCI_DDR_BASE 0x80000000 |
| 24 | #define DA8XX_DDR_BASE 0xc0000000 | ||
| 24 | 25 | ||
| 26 | #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) | ||
| 27 | #error Cannot enable DaVinci and DA8XX platforms concurrently | ||
| 28 | #elif defined(CONFIG_ARCH_DAVINCI_DA8XX) | ||
| 29 | #define PHYS_OFFSET DA8XX_DDR_BASE | ||
| 30 | #else | ||
| 25 | #define PHYS_OFFSET DAVINCI_DDR_BASE | 31 | #define PHYS_OFFSET DAVINCI_DDR_BASE |
| 32 | #endif | ||
| 26 | 33 | ||
| 27 | /* | 34 | /* |
| 28 | * Increase size of DMA-consistent memory region | 35 | * Increase size of DMA-consistent memory region |
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 27378458542f..bb84893a4e83 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h | |||
| @@ -154,6 +154,737 @@ enum davinci_dm355_index { | |||
| 154 | DM355_EVT8_ASP1_TX, | 154 | DM355_EVT8_ASP1_TX, |
| 155 | DM355_EVT9_ASP1_RX, | 155 | DM355_EVT9_ASP1_RX, |
| 156 | DM355_EVT26_MMC0_RX, | 156 | DM355_EVT26_MMC0_RX, |
| 157 | |||
| 158 | /* Video Out */ | ||
| 159 | DM355_VOUT_FIELD, | ||
| 160 | DM355_VOUT_FIELD_G70, | ||
| 161 | DM355_VOUT_HVSYNC, | ||
| 162 | DM355_VOUT_COUTL_EN, | ||
| 163 | DM355_VOUT_COUTH_EN, | ||
| 164 | |||
| 165 | /* Video In Pin Mux */ | ||
| 166 | DM355_VIN_PCLK, | ||
| 167 | DM355_VIN_CAM_WEN, | ||
| 168 | DM355_VIN_CAM_VD, | ||
| 169 | DM355_VIN_CAM_HD, | ||
| 170 | DM355_VIN_YIN_EN, | ||
| 171 | DM355_VIN_CINL_EN, | ||
| 172 | DM355_VIN_CINH_EN, | ||
| 173 | }; | ||
| 174 | |||
| 175 | enum davinci_dm365_index { | ||
| 176 | /* MMC/SD 0 */ | ||
| 177 | DM365_MMCSD0, | ||
| 178 | |||
| 179 | /* MMC/SD 1 */ | ||
| 180 | DM365_SD1_CLK, | ||
| 181 | DM365_SD1_CMD, | ||
| 182 | DM365_SD1_DATA3, | ||
| 183 | DM365_SD1_DATA2, | ||
| 184 | DM365_SD1_DATA1, | ||
| 185 | DM365_SD1_DATA0, | ||
| 186 | |||
| 187 | /* I2C */ | ||
| 188 | DM365_I2C_SDA, | ||
| 189 | DM365_I2C_SCL, | ||
| 190 | |||
| 191 | /* AEMIF */ | ||
| 192 | DM365_AEMIF_AR, | ||
| 193 | DM365_AEMIF_A3, | ||
| 194 | DM365_AEMIF_A7, | ||
| 195 | DM365_AEMIF_D15_8, | ||
| 196 | DM365_AEMIF_CE0, | ||
| 197 | |||
| 198 | /* ASP0 function */ | ||
| 199 | DM365_MCBSP0_BDX, | ||
| 200 | DM365_MCBSP0_X, | ||
| 201 | DM365_MCBSP0_BFSX, | ||
| 202 | DM365_MCBSP0_BDR, | ||
| 203 | DM365_MCBSP0_R, | ||
| 204 | DM365_MCBSP0_BFSR, | ||
| 205 | |||
| 206 | /* SPI0 */ | ||
| 207 | DM365_SPI0_SCLK, | ||
| 208 | DM365_SPI0_SDI, | ||
| 209 | DM365_SPI0_SDO, | ||
| 210 | DM365_SPI0_SDENA0, | ||
| 211 | DM365_SPI0_SDENA1, | ||
| 212 | |||
| 213 | /* UART */ | ||
| 214 | DM365_UART0_RXD, | ||
| 215 | DM365_UART0_TXD, | ||
| 216 | DM365_UART1_RXD, | ||
| 217 | DM365_UART1_TXD, | ||
| 218 | DM365_UART1_RTS, | ||
| 219 | DM365_UART1_CTS, | ||
| 220 | |||
| 221 | /* EMAC */ | ||
| 222 | DM365_EMAC_TX_EN, | ||
| 223 | DM365_EMAC_TX_CLK, | ||
| 224 | DM365_EMAC_COL, | ||
| 225 | DM365_EMAC_TXD3, | ||
| 226 | DM365_EMAC_TXD2, | ||
| 227 | DM365_EMAC_TXD1, | ||
| 228 | DM365_EMAC_TXD0, | ||
| 229 | DM365_EMAC_RXD3, | ||
| 230 | DM365_EMAC_RXD2, | ||
| 231 | DM365_EMAC_RXD1, | ||
| 232 | DM365_EMAC_RXD0, | ||
| 233 | DM365_EMAC_RX_CLK, | ||
| 234 | DM365_EMAC_RX_DV, | ||
| 235 | DM365_EMAC_RX_ER, | ||
| 236 | DM365_EMAC_CRS, | ||
| 237 | DM365_EMAC_MDIO, | ||
| 238 | DM365_EMAC_MDCLK, | ||
| 239 | |||
| 240 | /* Keypad */ | ||
| 241 | DM365_KEYPAD, | ||
| 242 | |||
| 243 | /* PWM */ | ||
| 244 | DM365_PWM0, | ||
| 245 | DM365_PWM0_G23, | ||
| 246 | DM365_PWM1, | ||
| 247 | DM365_PWM1_G25, | ||
| 248 | DM365_PWM2_G87, | ||
| 249 | DM365_PWM2_G88, | ||
| 250 | DM365_PWM2_G89, | ||
| 251 | DM365_PWM2_G90, | ||
| 252 | DM365_PWM3_G80, | ||
| 253 | DM365_PWM3_G81, | ||
| 254 | DM365_PWM3_G85, | ||
| 255 | DM365_PWM3_G86, | ||
| 256 | |||
| 257 | /* SPI1 */ | ||
| 258 | DM365_SPI1_SCLK, | ||
| 259 | DM365_SPI1_SDO, | ||
| 260 | DM365_SPI1_SDI, | ||
| 261 | DM365_SPI1_SDENA0, | ||
| 262 | DM365_SPI1_SDENA1, | ||
| 263 | |||
| 264 | /* SPI2 */ | ||
| 265 | DM365_SPI2_SCLK, | ||
| 266 | DM365_SPI2_SDO, | ||
| 267 | DM365_SPI2_SDI, | ||
| 268 | DM365_SPI2_SDENA0, | ||
| 269 | DM365_SPI2_SDENA1, | ||
| 270 | |||
| 271 | /* SPI3 */ | ||
| 272 | DM365_SPI3_SCLK, | ||
| 273 | DM365_SPI3_SDO, | ||
| 274 | DM365_SPI3_SDI, | ||
| 275 | DM365_SPI3_SDENA0, | ||
| 276 | DM365_SPI3_SDENA1, | ||
| 277 | |||
| 278 | /* SPI4 */ | ||
| 279 | DM365_SPI4_SCLK, | ||
| 280 | DM365_SPI4_SDO, | ||
| 281 | DM365_SPI4_SDI, | ||
| 282 | DM365_SPI4_SDENA0, | ||
| 283 | DM365_SPI4_SDENA1, | ||
| 284 | |||
| 285 | /* GPIO */ | ||
| 286 | DM365_GPIO20, | ||
| 287 | DM365_GPIO33, | ||
| 288 | DM365_GPIO40, | ||
| 289 | |||
| 290 | /* Video */ | ||
| 291 | DM365_VOUT_FIELD, | ||
| 292 | DM365_VOUT_FIELD_G81, | ||
| 293 | DM365_VOUT_HVSYNC, | ||
| 294 | DM365_VOUT_COUTL_EN, | ||
| 295 | DM365_VOUT_COUTH_EN, | ||
| 296 | DM365_VIN_CAM_WEN, | ||
| 297 | DM365_VIN_CAM_VD, | ||
| 298 | DM365_VIN_CAM_HD, | ||
| 299 | DM365_VIN_YIN4_7_EN, | ||
| 300 | DM365_VIN_YIN0_3_EN, | ||
| 301 | |||
| 302 | /* IRQ muxing */ | ||
| 303 | DM365_INT_EDMA_CC, | ||
| 304 | DM365_INT_EDMA_TC0_ERR, | ||
| 305 | DM365_INT_EDMA_TC1_ERR, | ||
| 306 | DM365_INT_EDMA_TC2_ERR, | ||
| 307 | DM365_INT_EDMA_TC3_ERR, | ||
| 308 | DM365_INT_PRTCSS, | ||
| 309 | DM365_INT_EMAC_RXTHRESH, | ||
| 310 | DM365_INT_EMAC_RXPULSE, | ||
| 311 | DM365_INT_EMAC_TXPULSE, | ||
| 312 | DM365_INT_EMAC_MISCPULSE, | ||
| 313 | DM365_INT_IMX0_ENABLE, | ||
| 314 | DM365_INT_IMX0_DISABLE, | ||
| 315 | DM365_INT_HDVICP_ENABLE, | ||
| 316 | DM365_INT_HDVICP_DISABLE, | ||
| 317 | DM365_INT_IMX1_ENABLE, | ||
| 318 | DM365_INT_IMX1_DISABLE, | ||
| 319 | DM365_INT_NSF_ENABLE, | ||
| 320 | DM365_INT_NSF_DISABLE, | ||
| 321 | |||
| 322 | /* EDMA event muxing */ | ||
| 323 | DM365_EVT2_ASP_TX, | ||
| 324 | DM365_EVT3_ASP_RX, | ||
| 325 | DM365_EVT26_MMC0_RX, | ||
| 326 | }; | ||
| 327 | |||
| 328 | enum da830_index { | ||
| 329 | DA830_GPIO7_14, | ||
| 330 | DA830_RTCK, | ||
| 331 | DA830_GPIO7_15, | ||
| 332 | DA830_EMU_0, | ||
| 333 | DA830_EMB_SDCKE, | ||
| 334 | DA830_EMB_CLK_GLUE, | ||
| 335 | DA830_EMB_CLK, | ||
| 336 | DA830_NEMB_CS_0, | ||
| 337 | DA830_NEMB_CAS, | ||
| 338 | DA830_NEMB_RAS, | ||
| 339 | DA830_NEMB_WE, | ||
| 340 | DA830_EMB_BA_1, | ||
| 341 | DA830_EMB_BA_0, | ||
| 342 | DA830_EMB_A_0, | ||
| 343 | DA830_EMB_A_1, | ||
| 344 | DA830_EMB_A_2, | ||
| 345 | DA830_EMB_A_3, | ||
| 346 | DA830_EMB_A_4, | ||
| 347 | DA830_EMB_A_5, | ||
| 348 | DA830_GPIO7_0, | ||
| 349 | DA830_GPIO7_1, | ||
| 350 | DA830_GPIO7_2, | ||
| 351 | DA830_GPIO7_3, | ||
| 352 | DA830_GPIO7_4, | ||
| 353 | DA830_GPIO7_5, | ||
| 354 | DA830_GPIO7_6, | ||
| 355 | DA830_GPIO7_7, | ||
| 356 | DA830_EMB_A_6, | ||
| 357 | DA830_EMB_A_7, | ||
| 358 | DA830_EMB_A_8, | ||
| 359 | DA830_EMB_A_9, | ||
| 360 | DA830_EMB_A_10, | ||
| 361 | DA830_EMB_A_11, | ||
| 362 | DA830_EMB_A_12, | ||
| 363 | DA830_EMB_D_31, | ||
| 364 | DA830_GPIO7_8, | ||
| 365 | DA830_GPIO7_9, | ||
| 366 | DA830_GPIO7_10, | ||
| 367 | DA830_GPIO7_11, | ||
| 368 | DA830_GPIO7_12, | ||
| 369 | DA830_GPIO7_13, | ||
| 370 | DA830_GPIO3_13, | ||
| 371 | DA830_EMB_D_30, | ||
| 372 | DA830_EMB_D_29, | ||
| 373 | DA830_EMB_D_28, | ||
| 374 | DA830_EMB_D_27, | ||
| 375 | DA830_EMB_D_26, | ||
| 376 | DA830_EMB_D_25, | ||
| 377 | DA830_EMB_D_24, | ||
| 378 | DA830_EMB_D_23, | ||
| 379 | DA830_EMB_D_22, | ||
| 380 | DA830_EMB_D_21, | ||
| 381 | DA830_EMB_D_20, | ||
| 382 | DA830_EMB_D_19, | ||
| 383 | DA830_EMB_D_18, | ||
| 384 | DA830_EMB_D_17, | ||
| 385 | DA830_EMB_D_16, | ||
| 386 | DA830_NEMB_WE_DQM_3, | ||
| 387 | DA830_NEMB_WE_DQM_2, | ||
| 388 | DA830_EMB_D_0, | ||
| 389 | DA830_EMB_D_1, | ||
| 390 | DA830_EMB_D_2, | ||
| 391 | DA830_EMB_D_3, | ||
| 392 | DA830_EMB_D_4, | ||
| 393 | DA830_EMB_D_5, | ||
| 394 | DA830_EMB_D_6, | ||
| 395 | DA830_GPIO6_0, | ||
| 396 | DA830_GPIO6_1, | ||
| 397 | DA830_GPIO6_2, | ||
| 398 | DA830_GPIO6_3, | ||
| 399 | DA830_GPIO6_4, | ||
| 400 | DA830_GPIO6_5, | ||
| 401 | DA830_GPIO6_6, | ||
| 402 | DA830_EMB_D_7, | ||
| 403 | DA830_EMB_D_8, | ||
| 404 | DA830_EMB_D_9, | ||
| 405 | DA830_EMB_D_10, | ||
| 406 | DA830_EMB_D_11, | ||
| 407 | DA830_EMB_D_12, | ||
| 408 | DA830_EMB_D_13, | ||
| 409 | DA830_EMB_D_14, | ||
| 410 | DA830_GPIO6_7, | ||
| 411 | DA830_GPIO6_8, | ||
| 412 | DA830_GPIO6_9, | ||
| 413 | DA830_GPIO6_10, | ||
| 414 | DA830_GPIO6_11, | ||
| 415 | DA830_GPIO6_12, | ||
| 416 | DA830_GPIO6_13, | ||
| 417 | DA830_GPIO6_14, | ||
| 418 | DA830_EMB_D_15, | ||
| 419 | DA830_NEMB_WE_DQM_1, | ||
| 420 | DA830_NEMB_WE_DQM_0, | ||
| 421 | DA830_SPI0_SOMI_0, | ||
| 422 | DA830_SPI0_SIMO_0, | ||
| 423 | DA830_SPI0_CLK, | ||
| 424 | DA830_NSPI0_ENA, | ||
| 425 | DA830_NSPI0_SCS_0, | ||
| 426 | DA830_EQEP0I, | ||
| 427 | DA830_EQEP0S, | ||
| 428 | DA830_EQEP1I, | ||
| 429 | DA830_NUART0_CTS, | ||
| 430 | DA830_NUART0_RTS, | ||
| 431 | DA830_EQEP0A, | ||
| 432 | DA830_EQEP0B, | ||
| 433 | DA830_GPIO6_15, | ||
| 434 | DA830_GPIO5_14, | ||
| 435 | DA830_GPIO5_15, | ||
| 436 | DA830_GPIO5_0, | ||
| 437 | DA830_GPIO5_1, | ||
| 438 | DA830_GPIO5_2, | ||
| 439 | DA830_GPIO5_3, | ||
| 440 | DA830_GPIO5_4, | ||
| 441 | DA830_SPI1_SOMI_0, | ||
| 442 | DA830_SPI1_SIMO_0, | ||
| 443 | DA830_SPI1_CLK, | ||
| 444 | DA830_UART0_RXD, | ||
| 445 | DA830_UART0_TXD, | ||
| 446 | DA830_AXR1_10, | ||
| 447 | DA830_AXR1_11, | ||
| 448 | DA830_NSPI1_ENA, | ||
| 449 | DA830_I2C1_SCL, | ||
| 450 | DA830_I2C1_SDA, | ||
| 451 | DA830_EQEP1S, | ||
| 452 | DA830_I2C0_SDA, | ||
| 453 | DA830_I2C0_SCL, | ||
| 454 | DA830_UART2_RXD, | ||
| 455 | DA830_TM64P0_IN12, | ||
| 456 | DA830_TM64P0_OUT12, | ||
| 457 | DA830_GPIO5_5, | ||
| 458 | DA830_GPIO5_6, | ||
| 459 | DA830_GPIO5_7, | ||
| 460 | DA830_GPIO5_8, | ||
| 461 | DA830_GPIO5_9, | ||
| 462 | DA830_GPIO5_10, | ||
| 463 | DA830_GPIO5_11, | ||
| 464 | DA830_GPIO5_12, | ||
| 465 | DA830_NSPI1_SCS_0, | ||
| 466 | DA830_USB0_DRVVBUS, | ||
| 467 | DA830_AHCLKX0, | ||
| 468 | DA830_ACLKX0, | ||
| 469 | DA830_AFSX0, | ||
| 470 | DA830_AHCLKR0, | ||
| 471 | DA830_ACLKR0, | ||
| 472 | DA830_AFSR0, | ||
| 473 | DA830_UART2_TXD, | ||
| 474 | DA830_AHCLKX2, | ||
| 475 | DA830_ECAP0_APWM0, | ||
| 476 | DA830_RMII_MHZ_50_CLK, | ||
| 477 | DA830_ECAP1_APWM1, | ||
| 478 | DA830_USB_REFCLKIN, | ||
| 479 | DA830_GPIO5_13, | ||
| 480 | DA830_GPIO4_15, | ||
| 481 | DA830_GPIO2_11, | ||
| 482 | DA830_GPIO2_12, | ||
| 483 | DA830_GPIO2_13, | ||
| 484 | DA830_GPIO2_14, | ||
| 485 | DA830_GPIO2_15, | ||
| 486 | DA830_GPIO3_12, | ||
| 487 | DA830_AMUTE0, | ||
| 488 | DA830_AXR0_0, | ||
| 489 | DA830_AXR0_1, | ||
| 490 | DA830_AXR0_2, | ||
| 491 | DA830_AXR0_3, | ||
| 492 | DA830_AXR0_4, | ||
| 493 | DA830_AXR0_5, | ||
| 494 | DA830_AXR0_6, | ||
| 495 | DA830_RMII_TXD_0, | ||
| 496 | DA830_RMII_TXD_1, | ||
| 497 | DA830_RMII_TXEN, | ||
| 498 | DA830_RMII_CRS_DV, | ||
| 499 | DA830_RMII_RXD_0, | ||
| 500 | DA830_RMII_RXD_1, | ||
| 501 | DA830_RMII_RXER, | ||
| 502 | DA830_AFSR2, | ||
| 503 | DA830_ACLKX2, | ||
| 504 | DA830_AXR2_3, | ||
| 505 | DA830_AXR2_2, | ||
| 506 | DA830_AXR2_1, | ||
| 507 | DA830_AFSX2, | ||
| 508 | DA830_ACLKR2, | ||
| 509 | DA830_NRESETOUT, | ||
| 510 | DA830_GPIO3_0, | ||
| 511 | DA830_GPIO3_1, | ||
| 512 | DA830_GPIO3_2, | ||
| 513 | DA830_GPIO3_3, | ||
| 514 | DA830_GPIO3_4, | ||
| 515 | DA830_GPIO3_5, | ||
| 516 | DA830_GPIO3_6, | ||
| 517 | DA830_AXR0_7, | ||
| 518 | DA830_AXR0_8, | ||
| 519 | DA830_UART1_RXD, | ||
| 520 | DA830_UART1_TXD, | ||
| 521 | DA830_AXR0_11, | ||
| 522 | DA830_AHCLKX1, | ||
| 523 | DA830_ACLKX1, | ||
| 524 | DA830_AFSX1, | ||
| 525 | DA830_MDIO_CLK, | ||
| 526 | DA830_MDIO_D, | ||
| 527 | DA830_AXR0_9, | ||
| 528 | DA830_AXR0_10, | ||
| 529 | DA830_EPWM0B, | ||
| 530 | DA830_EPWM0A, | ||
| 531 | DA830_EPWMSYNCI, | ||
| 532 | DA830_AXR2_0, | ||
| 533 | DA830_EPWMSYNC0, | ||
| 534 | DA830_GPIO3_7, | ||
| 535 | DA830_GPIO3_8, | ||
| 536 | DA830_GPIO3_9, | ||
| 537 | DA830_GPIO3_10, | ||
| 538 | DA830_GPIO3_11, | ||
| 539 | DA830_GPIO3_14, | ||
| 540 | DA830_GPIO3_15, | ||
| 541 | DA830_GPIO4_10, | ||
| 542 | DA830_AHCLKR1, | ||
| 543 | DA830_ACLKR1, | ||
| 544 | DA830_AFSR1, | ||
| 545 | DA830_AMUTE1, | ||
| 546 | DA830_AXR1_0, | ||
| 547 | DA830_AXR1_1, | ||
| 548 | DA830_AXR1_2, | ||
| 549 | DA830_AXR1_3, | ||
| 550 | DA830_ECAP2_APWM2, | ||
| 551 | DA830_EHRPWMGLUETZ, | ||
| 552 | DA830_EQEP1A, | ||
| 553 | DA830_GPIO4_11, | ||
| 554 | DA830_GPIO4_12, | ||
| 555 | DA830_GPIO4_13, | ||
| 556 | DA830_GPIO4_14, | ||
| 557 | DA830_GPIO4_0, | ||
| 558 | DA830_GPIO4_1, | ||
| 559 | DA830_GPIO4_2, | ||
| 560 | DA830_GPIO4_3, | ||
| 561 | DA830_AXR1_4, | ||
| 562 | DA830_AXR1_5, | ||
| 563 | DA830_AXR1_6, | ||
| 564 | DA830_AXR1_7, | ||
| 565 | DA830_AXR1_8, | ||
| 566 | DA830_AXR1_9, | ||
| 567 | DA830_EMA_D_0, | ||
| 568 | DA830_EMA_D_1, | ||
| 569 | DA830_EQEP1B, | ||
| 570 | DA830_EPWM2B, | ||
| 571 | DA830_EPWM2A, | ||
| 572 | DA830_EPWM1B, | ||
| 573 | DA830_EPWM1A, | ||
| 574 | DA830_MMCSD_DAT_0, | ||
| 575 | DA830_MMCSD_DAT_1, | ||
| 576 | DA830_UHPI_HD_0, | ||
| 577 | DA830_UHPI_HD_1, | ||
| 578 | DA830_GPIO4_4, | ||
| 579 | DA830_GPIO4_5, | ||
| 580 | DA830_GPIO4_6, | ||
| 581 | DA830_GPIO4_7, | ||
| 582 | DA830_GPIO4_8, | ||
| 583 | DA830_GPIO4_9, | ||
| 584 | DA830_GPIO0_0, | ||
| 585 | DA830_GPIO0_1, | ||
| 586 | DA830_EMA_D_2, | ||
| 587 | DA830_EMA_D_3, | ||
| 588 | DA830_EMA_D_4, | ||
| 589 | DA830_EMA_D_5, | ||
| 590 | DA830_EMA_D_6, | ||
| 591 | DA830_EMA_D_7, | ||
| 592 | DA830_EMA_D_8, | ||
| 593 | DA830_EMA_D_9, | ||
| 594 | DA830_MMCSD_DAT_2, | ||
| 595 | DA830_MMCSD_DAT_3, | ||
| 596 | DA830_MMCSD_DAT_4, | ||
| 597 | DA830_MMCSD_DAT_5, | ||
| 598 | DA830_MMCSD_DAT_6, | ||
| 599 | DA830_MMCSD_DAT_7, | ||
| 600 | DA830_UHPI_HD_8, | ||
| 601 | DA830_UHPI_HD_9, | ||
| 602 | DA830_UHPI_HD_2, | ||
| 603 | DA830_UHPI_HD_3, | ||
| 604 | DA830_UHPI_HD_4, | ||
| 605 | DA830_UHPI_HD_5, | ||
| 606 | DA830_UHPI_HD_6, | ||
| 607 | DA830_UHPI_HD_7, | ||
| 608 | DA830_LCD_D_8, | ||
| 609 | DA830_LCD_D_9, | ||
| 610 | DA830_GPIO0_2, | ||
| 611 | DA830_GPIO0_3, | ||
| 612 | DA830_GPIO0_4, | ||
| 613 | DA830_GPIO0_5, | ||
| 614 | DA830_GPIO0_6, | ||
| 615 | DA830_GPIO0_7, | ||
| 616 | DA830_GPIO0_8, | ||
| 617 | DA830_GPIO0_9, | ||
| 618 | DA830_EMA_D_10, | ||
| 619 | DA830_EMA_D_11, | ||
| 620 | DA830_EMA_D_12, | ||
| 621 | DA830_EMA_D_13, | ||
| 622 | DA830_EMA_D_14, | ||
| 623 | DA830_EMA_D_15, | ||
| 624 | DA830_EMA_A_0, | ||
| 625 | DA830_EMA_A_1, | ||
| 626 | DA830_UHPI_HD_10, | ||
| 627 | DA830_UHPI_HD_11, | ||
| 628 | DA830_UHPI_HD_12, | ||
| 629 | DA830_UHPI_HD_13, | ||
| 630 | DA830_UHPI_HD_14, | ||
| 631 | DA830_UHPI_HD_15, | ||
| 632 | DA830_LCD_D_7, | ||
| 633 | DA830_MMCSD_CLK, | ||
| 634 | DA830_LCD_D_10, | ||
| 635 | DA830_LCD_D_11, | ||
| 636 | DA830_LCD_D_12, | ||
| 637 | DA830_LCD_D_13, | ||
| 638 | DA830_LCD_D_14, | ||
| 639 | DA830_LCD_D_15, | ||
| 640 | DA830_UHPI_HCNTL0, | ||
| 641 | DA830_GPIO0_10, | ||
| 642 | DA830_GPIO0_11, | ||
| 643 | DA830_GPIO0_12, | ||
| 644 | DA830_GPIO0_13, | ||
| 645 | DA830_GPIO0_14, | ||
| 646 | DA830_GPIO0_15, | ||
| 647 | DA830_GPIO1_0, | ||
| 648 | DA830_GPIO1_1, | ||
| 649 | DA830_EMA_A_2, | ||
| 650 | DA830_EMA_A_3, | ||
| 651 | DA830_EMA_A_4, | ||
| 652 | DA830_EMA_A_5, | ||
| 653 | DA830_EMA_A_6, | ||
| 654 | DA830_EMA_A_7, | ||
| 655 | DA830_EMA_A_8, | ||
| 656 | DA830_EMA_A_9, | ||
| 657 | DA830_MMCSD_CMD, | ||
| 658 | DA830_LCD_D_6, | ||
| 659 | DA830_LCD_D_3, | ||
| 660 | DA830_LCD_D_2, | ||
| 661 | DA830_LCD_D_1, | ||
| 662 | DA830_LCD_D_0, | ||
| 663 | DA830_LCD_PCLK, | ||
| 664 | DA830_LCD_HSYNC, | ||
| 665 | DA830_UHPI_HCNTL1, | ||
| 666 | DA830_GPIO1_2, | ||
| 667 | DA830_GPIO1_3, | ||
| 668 | DA830_GPIO1_4, | ||
| 669 | DA830_GPIO1_5, | ||
| 670 | DA830_GPIO1_6, | ||
| 671 | DA830_GPIO1_7, | ||
| 672 | DA830_GPIO1_8, | ||
| 673 | DA830_GPIO1_9, | ||
| 674 | DA830_EMA_A_10, | ||
| 675 | DA830_EMA_A_11, | ||
| 676 | DA830_EMA_A_12, | ||
| 677 | DA830_EMA_BA_1, | ||
| 678 | DA830_EMA_BA_0, | ||
| 679 | DA830_EMA_CLK, | ||
| 680 | DA830_EMA_SDCKE, | ||
| 681 | DA830_NEMA_CAS, | ||
| 682 | DA830_LCD_VSYNC, | ||
| 683 | DA830_NLCD_AC_ENB_CS, | ||
| 684 | DA830_LCD_MCLK, | ||
| 685 | DA830_LCD_D_5, | ||
| 686 | DA830_LCD_D_4, | ||
| 687 | DA830_OBSCLK, | ||
| 688 | DA830_NEMA_CS_4, | ||
| 689 | DA830_UHPI_HHWIL, | ||
| 690 | DA830_AHCLKR2, | ||
| 691 | DA830_GPIO1_10, | ||
| 692 | DA830_GPIO1_11, | ||
| 693 | DA830_GPIO1_12, | ||
| 694 | DA830_GPIO1_13, | ||
| 695 | DA830_GPIO1_14, | ||
| 696 | DA830_GPIO1_15, | ||
| 697 | DA830_GPIO2_0, | ||
| 698 | DA830_GPIO2_1, | ||
| 699 | DA830_NEMA_RAS, | ||
| 700 | DA830_NEMA_WE, | ||
| 701 | DA830_NEMA_CS_0, | ||
| 702 | DA830_NEMA_CS_2, | ||
| 703 | DA830_NEMA_CS_3, | ||
| 704 | DA830_NEMA_OE, | ||
| 705 | DA830_NEMA_WE_DQM_1, | ||
| 706 | DA830_NEMA_WE_DQM_0, | ||
| 707 | DA830_NEMA_CS_5, | ||
| 708 | DA830_UHPI_HRNW, | ||
| 709 | DA830_NUHPI_HAS, | ||
| 710 | DA830_NUHPI_HCS, | ||
| 711 | DA830_NUHPI_HDS1, | ||
| 712 | DA830_NUHPI_HDS2, | ||
| 713 | DA830_NUHPI_HINT, | ||
| 714 | DA830_AXR0_12, | ||
| 715 | DA830_AMUTE2, | ||
| 716 | DA830_AXR0_13, | ||
| 717 | DA830_AXR0_14, | ||
| 718 | DA830_AXR0_15, | ||
| 719 | DA830_GPIO2_2, | ||
| 720 | DA830_GPIO2_3, | ||
| 721 | DA830_GPIO2_4, | ||
| 722 | DA830_GPIO2_5, | ||
| 723 | DA830_GPIO2_6, | ||
| 724 | DA830_GPIO2_7, | ||
| 725 | DA830_GPIO2_8, | ||
| 726 | DA830_GPIO2_9, | ||
| 727 | DA830_EMA_WAIT_0, | ||
| 728 | DA830_NUHPI_HRDY, | ||
| 729 | DA830_GPIO2_10, | ||
| 730 | }; | ||
| 731 | |||
| 732 | enum davinci_da850_index { | ||
| 733 | /* UART0 function */ | ||
| 734 | DA850_NUART0_CTS, | ||
| 735 | DA850_NUART0_RTS, | ||
| 736 | DA850_UART0_RXD, | ||
| 737 | DA850_UART0_TXD, | ||
| 738 | |||
| 739 | /* UART1 function */ | ||
| 740 | DA850_NUART1_CTS, | ||
| 741 | DA850_NUART1_RTS, | ||
| 742 | DA850_UART1_RXD, | ||
| 743 | DA850_UART1_TXD, | ||
| 744 | |||
| 745 | /* UART2 function */ | ||
| 746 | DA850_NUART2_CTS, | ||
| 747 | DA850_NUART2_RTS, | ||
| 748 | DA850_UART2_RXD, | ||
| 749 | DA850_UART2_TXD, | ||
| 750 | |||
| 751 | /* I2C1 function */ | ||
| 752 | DA850_I2C1_SCL, | ||
| 753 | DA850_I2C1_SDA, | ||
| 754 | |||
| 755 | /* I2C0 function */ | ||
| 756 | DA850_I2C0_SDA, | ||
| 757 | DA850_I2C0_SCL, | ||
| 758 | |||
| 759 | /* EMAC function */ | ||
| 760 | DA850_MII_TXEN, | ||
| 761 | DA850_MII_TXCLK, | ||
| 762 | DA850_MII_COL, | ||
| 763 | DA850_MII_TXD_3, | ||
| 764 | DA850_MII_TXD_2, | ||
| 765 | DA850_MII_TXD_1, | ||
| 766 | DA850_MII_TXD_0, | ||
| 767 | DA850_MII_RXER, | ||
| 768 | DA850_MII_CRS, | ||
| 769 | DA850_MII_RXCLK, | ||
| 770 | DA850_MII_RXDV, | ||
| 771 | DA850_MII_RXD_3, | ||
| 772 | DA850_MII_RXD_2, | ||
| 773 | DA850_MII_RXD_1, | ||
| 774 | DA850_MII_RXD_0, | ||
| 775 | DA850_MDIO_CLK, | ||
| 776 | DA850_MDIO_D, | ||
| 777 | |||
| 778 | /* McASP function */ | ||
| 779 | DA850_ACLKR, | ||
| 780 | DA850_ACLKX, | ||
| 781 | DA850_AFSR, | ||
| 782 | DA850_AFSX, | ||
| 783 | DA850_AHCLKR, | ||
| 784 | DA850_AHCLKX, | ||
| 785 | DA850_AMUTE, | ||
| 786 | DA850_AXR_15, | ||
| 787 | DA850_AXR_14, | ||
| 788 | DA850_AXR_13, | ||
| 789 | DA850_AXR_12, | ||
| 790 | DA850_AXR_11, | ||
| 791 | DA850_AXR_10, | ||
| 792 | DA850_AXR_9, | ||
| 793 | DA850_AXR_8, | ||
| 794 | DA850_AXR_7, | ||
| 795 | DA850_AXR_6, | ||
| 796 | DA850_AXR_5, | ||
| 797 | DA850_AXR_4, | ||
| 798 | DA850_AXR_3, | ||
| 799 | DA850_AXR_2, | ||
| 800 | DA850_AXR_1, | ||
| 801 | DA850_AXR_0, | ||
| 802 | |||
| 803 | /* LCD function */ | ||
| 804 | DA850_LCD_D_7, | ||
| 805 | DA850_LCD_D_6, | ||
| 806 | DA850_LCD_D_5, | ||
| 807 | DA850_LCD_D_4, | ||
| 808 | DA850_LCD_D_3, | ||
| 809 | DA850_LCD_D_2, | ||
| 810 | DA850_LCD_D_1, | ||
| 811 | DA850_LCD_D_0, | ||
| 812 | DA850_LCD_D_15, | ||
| 813 | DA850_LCD_D_14, | ||
| 814 | DA850_LCD_D_13, | ||
| 815 | DA850_LCD_D_12, | ||
| 816 | DA850_LCD_D_11, | ||
| 817 | DA850_LCD_D_10, | ||
| 818 | DA850_LCD_D_9, | ||
| 819 | DA850_LCD_D_8, | ||
| 820 | DA850_LCD_PCLK, | ||
| 821 | DA850_LCD_HSYNC, | ||
| 822 | DA850_LCD_VSYNC, | ||
| 823 | DA850_NLCD_AC_ENB_CS, | ||
| 824 | |||
| 825 | /* MMC/SD0 function */ | ||
| 826 | DA850_MMCSD0_DAT_0, | ||
| 827 | DA850_MMCSD0_DAT_1, | ||
| 828 | DA850_MMCSD0_DAT_2, | ||
| 829 | DA850_MMCSD0_DAT_3, | ||
| 830 | DA850_MMCSD0_CLK, | ||
| 831 | DA850_MMCSD0_CMD, | ||
| 832 | |||
| 833 | /* EMIF2.5/EMIFA function */ | ||
| 834 | DA850_EMA_D_7, | ||
| 835 | DA850_EMA_D_6, | ||
| 836 | DA850_EMA_D_5, | ||
| 837 | DA850_EMA_D_4, | ||
| 838 | DA850_EMA_D_3, | ||
| 839 | DA850_EMA_D_2, | ||
| 840 | DA850_EMA_D_1, | ||
| 841 | DA850_EMA_D_0, | ||
| 842 | DA850_EMA_A_1, | ||
| 843 | DA850_EMA_A_2, | ||
| 844 | DA850_NEMA_CS_3, | ||
| 845 | DA850_NEMA_CS_4, | ||
| 846 | DA850_NEMA_WE, | ||
| 847 | DA850_NEMA_OE, | ||
| 848 | DA850_EMA_D_15, | ||
| 849 | DA850_EMA_D_14, | ||
| 850 | DA850_EMA_D_13, | ||
| 851 | DA850_EMA_D_12, | ||
| 852 | DA850_EMA_D_11, | ||
| 853 | DA850_EMA_D_10, | ||
| 854 | DA850_EMA_D_9, | ||
| 855 | DA850_EMA_D_8, | ||
| 856 | DA850_EMA_A_0, | ||
| 857 | DA850_EMA_A_3, | ||
| 858 | DA850_EMA_A_4, | ||
| 859 | DA850_EMA_A_5, | ||
| 860 | DA850_EMA_A_6, | ||
| 861 | DA850_EMA_A_7, | ||
| 862 | DA850_EMA_A_8, | ||
| 863 | DA850_EMA_A_9, | ||
| 864 | DA850_EMA_A_10, | ||
| 865 | DA850_EMA_A_11, | ||
| 866 | DA850_EMA_A_12, | ||
| 867 | DA850_EMA_A_13, | ||
| 868 | DA850_EMA_A_14, | ||
| 869 | DA850_EMA_A_15, | ||
| 870 | DA850_EMA_A_16, | ||
| 871 | DA850_EMA_A_17, | ||
| 872 | DA850_EMA_A_18, | ||
| 873 | DA850_EMA_A_19, | ||
| 874 | DA850_EMA_A_20, | ||
| 875 | DA850_EMA_A_21, | ||
| 876 | DA850_EMA_A_22, | ||
| 877 | DA850_EMA_A_23, | ||
| 878 | DA850_EMA_BA_1, | ||
| 879 | DA850_EMA_CLK, | ||
| 880 | DA850_EMA_WAIT_1, | ||
| 881 | DA850_NEMA_CS_2, | ||
| 882 | |||
| 883 | /* GPIO function */ | ||
| 884 | DA850_GPIO2_15, | ||
| 885 | DA850_GPIO8_10, | ||
| 886 | DA850_GPIO4_0, | ||
| 887 | DA850_GPIO4_1, | ||
| 157 | }; | 888 | }; |
| 158 | 889 | ||
| 159 | #ifdef CONFIG_DAVINCI_MUX | 890 | #ifdef CONFIG_DAVINCI_MUX |
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index ab8a2586d1cc..171173c1dbad 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h | |||
| @@ -81,6 +81,24 @@ | |||
| 81 | #define DM355_LPSC_RTO 12 | 81 | #define DM355_LPSC_RTO 12 |
| 82 | #define DM355_LPSC_VPSS_DAC 41 | 82 | #define DM355_LPSC_VPSS_DAC 41 |
| 83 | 83 | ||
| 84 | /* DM365 */ | ||
| 85 | #define DM365_LPSC_TIMER3 5 | ||
| 86 | #define DM365_LPSC_SPI1 6 | ||
| 87 | #define DM365_LPSC_MMC_SD1 7 | ||
| 88 | #define DM365_LPSC_McBSP1 8 | ||
| 89 | #define DM365_LPSC_PWM3 10 | ||
| 90 | #define DM365_LPSC_SPI2 11 | ||
| 91 | #define DM365_LPSC_RTO 12 | ||
| 92 | #define DM365_LPSC_TIMER4 17 | ||
| 93 | #define DM365_LPSC_SPI0 22 | ||
| 94 | #define DM365_LPSC_SPI3 38 | ||
| 95 | #define DM365_LPSC_SPI4 39 | ||
| 96 | #define DM365_LPSC_EMAC 40 | ||
| 97 | #define DM365_LPSC_VOICE_CODEC 44 | ||
| 98 | #define DM365_LPSC_DAC_CLK 46 | ||
| 99 | #define DM365_LPSC_VPSSMSTR 47 | ||
| 100 | #define DM365_LPSC_MJCP 50 | ||
| 101 | |||
| 84 | /* | 102 | /* |
| 85 | * LPSC Assignments | 103 | * LPSC Assignments |
| 86 | */ | 104 | */ |
| @@ -118,6 +136,50 @@ | |||
| 118 | #define DM646X_LPSC_TIMER1 35 | 136 | #define DM646X_LPSC_TIMER1 35 |
| 119 | #define DM646X_LPSC_ARM_INTC 45 | 137 | #define DM646X_LPSC_ARM_INTC 45 |
| 120 | 138 | ||
| 139 | /* PSC0 defines */ | ||
| 140 | #define DA8XX_LPSC0_TPCC 0 | ||
| 141 | #define DA8XX_LPSC0_TPTC0 1 | ||
| 142 | #define DA8XX_LPSC0_TPTC1 2 | ||
| 143 | #define DA8XX_LPSC0_EMIF25 3 | ||
| 144 | #define DA8XX_LPSC0_SPI0 4 | ||
| 145 | #define DA8XX_LPSC0_MMC_SD 5 | ||
| 146 | #define DA8XX_LPSC0_AINTC 6 | ||
| 147 | #define DA8XX_LPSC0_ARM_RAM_ROM 7 | ||
| 148 | #define DA8XX_LPSC0_SECU_MGR 8 | ||
| 149 | #define DA8XX_LPSC0_UART0 9 | ||
| 150 | #define DA8XX_LPSC0_SCR0_SS 10 | ||
| 151 | #define DA8XX_LPSC0_SCR1_SS 11 | ||
| 152 | #define DA8XX_LPSC0_SCR2_SS 12 | ||
| 153 | #define DA8XX_LPSC0_DMAX 13 | ||
| 154 | #define DA8XX_LPSC0_ARM 14 | ||
| 155 | #define DA8XX_LPSC0_GEM 15 | ||
| 156 | |||
| 157 | /* PSC1 defines */ | ||
| 158 | #define DA850_LPSC1_TPCC1 0 | ||
| 159 | #define DA8XX_LPSC1_USB20 1 | ||
| 160 | #define DA8XX_LPSC1_USB11 2 | ||
| 161 | #define DA8XX_LPSC1_GPIO 3 | ||
| 162 | #define DA8XX_LPSC1_UHPI 4 | ||
| 163 | #define DA8XX_LPSC1_CPGMAC 5 | ||
| 164 | #define DA8XX_LPSC1_EMIF3C 6 | ||
| 165 | #define DA8XX_LPSC1_McASP0 7 | ||
| 166 | #define DA830_LPSC1_McASP1 8 | ||
| 167 | #define DA850_LPSC1_SATA 8 | ||
| 168 | #define DA830_LPSC1_McASP2 9 | ||
| 169 | #define DA8XX_LPSC1_SPI1 10 | ||
| 170 | #define DA8XX_LPSC1_I2C 11 | ||
| 171 | #define DA8XX_LPSC1_UART1 12 | ||
| 172 | #define DA8XX_LPSC1_UART2 13 | ||
| 173 | #define DA8XX_LPSC1_LCDC 16 | ||
| 174 | #define DA8XX_LPSC1_PWM 17 | ||
| 175 | #define DA8XX_LPSC1_ECAP 20 | ||
| 176 | #define DA830_LPSC1_EQEP 21 | ||
| 177 | #define DA850_LPSC1_TPTC2 21 | ||
| 178 | #define DA8XX_LPSC1_SCR_P0_SS 24 | ||
| 179 | #define DA8XX_LPSC1_SCR_P1_SS 25 | ||
| 180 | #define DA8XX_LPSC1_CR_P3_SS 26 | ||
| 181 | #define DA8XX_LPSC1_L3_CBA_RAM 31 | ||
| 182 | |||
| 121 | extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); | 183 | extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); |
| 122 | extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, | 184 | extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, |
| 123 | unsigned int id, char enable); | 185 | unsigned int id, char enable); |
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 794fa5cf93c1..a584697a9e70 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h | |||
| @@ -11,13 +11,17 @@ | |||
| 11 | #ifndef __ASM_ARCH_SERIAL_H | 11 | #ifndef __ASM_ARCH_SERIAL_H |
| 12 | #define __ASM_ARCH_SERIAL_H | 12 | #define __ASM_ARCH_SERIAL_H |
| 13 | 13 | ||
| 14 | #include <mach/io.h> | 14 | #include <mach/hardware.h> |
| 15 | 15 | ||
| 16 | #define DAVINCI_MAX_NR_UARTS 3 | 16 | #define DAVINCI_MAX_NR_UARTS 3 |
| 17 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) | 17 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) |
| 18 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) | 18 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) |
| 19 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) | 19 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) |
| 20 | 20 | ||
| 21 | #define DA8XX_UART0_BASE (IO_PHYS + 0x042000) | ||
| 22 | #define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) | ||
| 23 | #define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) | ||
| 24 | |||
| 21 | /* DaVinci UART register offsets */ | 25 | /* DaVinci UART register offsets */ |
| 22 | #define UART_DAVINCI_PWREMU 0x0c | 26 | #define UART_DAVINCI_PWREMU 0x0c |
| 23 | #define UART_DM646X_SCR 0x10 | 27 | #define UART_DM646X_SCR 0x10 |
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index b7e7036674fa..8e4f10fe1263 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h | |||
| @@ -16,12 +16,12 @@ | |||
| 16 | 16 | ||
| 17 | extern void davinci_watchdog_reset(void); | 17 | extern void davinci_watchdog_reset(void); |
| 18 | 18 | ||
| 19 | static void arch_idle(void) | 19 | static inline void arch_idle(void) |
| 20 | { | 20 | { |
| 21 | cpu_do_idle(); | 21 | cpu_do_idle(); |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static void arch_reset(char mode, const char *cmd) | 24 | static inline void arch_reset(char mode, const char *cmd) |
| 25 | { | 25 | { |
| 26 | davinci_watchdog_reset(); | 26 | davinci_watchdog_reset(); |
| 27 | } | 27 | } |
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 1e27475f9a23..33796b4db17f 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h | |||
| @@ -21,8 +21,11 @@ static u32 *uart; | |||
| 21 | 21 | ||
| 22 | static u32 *get_uart_base(void) | 22 | static u32 *get_uart_base(void) |
| 23 | { | 23 | { |
| 24 | /* Add logic here for new platforms, using __macine_arch_type */ | 24 | if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM || |
| 25 | return (u32 *)DAVINCI_UART0_BASE; | 25 | __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) |
| 26 | return (u32 *)DA8XX_UART2_BASE; | ||
| 27 | else | ||
| 28 | return (u32 *)DAVINCI_UART0_BASE; | ||
| 26 | } | 29 | } |
| 27 | 30 | ||
| 28 | /* PORT_16C550A, in polled non-fifo mode */ | 31 | /* PORT_16C550A, in polled non-fifo mode */ |
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h index ad51625b6609..d49646a8e206 100644 --- a/arch/arm/mach-davinci/include/mach/vmalloc.h +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | 8 | * is licensed "as is" without any warranty of any kind, whether express |
| 9 | * or implied. | 9 | * or implied. |
| 10 | */ | 10 | */ |
| 11 | #include <mach/io.h> | 11 | #include <mach/hardware.h> |
| 12 | 12 | ||
| 13 | /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ | 13 | /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ |
| 14 | #define VMALLOC_END (IO_VIRT - (2<<20)) | 14 | #define VMALLOC_END (IO_VIRT - (2<<20)) |
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index d310f579aa85..898905e48946 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c | |||
| @@ -91,3 +91,17 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) | |||
| 91 | return 0; | 91 | return 0; |
| 92 | } | 92 | } |
| 93 | EXPORT_SYMBOL(davinci_cfg_reg); | 93 | EXPORT_SYMBOL(davinci_cfg_reg); |
| 94 | |||
| 95 | int da8xx_pinmux_setup(const short pins[]) | ||
| 96 | { | ||
| 97 | int i, error = -EINVAL; | ||
| 98 | |||
| 99 | if (pins) | ||
| 100 | for (i = 0; pins[i] >= 0; i++) { | ||
| 101 | error = davinci_cfg_reg(pins[i]); | ||
| 102 | if (error) | ||
| 103 | break; | ||
| 104 | } | ||
| 105 | |||
| 106 | return error; | ||
| 107 | } | ||
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c index db54b2a66b4d..4f1fc9b318b3 100644 --- a/arch/arm/mach-davinci/sram.c +++ b/arch/arm/mach-davinci/sram.c | |||
| @@ -60,7 +60,7 @@ static int __init sram_init(void) | |||
| 60 | int status = 0; | 60 | int status = 0; |
| 61 | 61 | ||
| 62 | if (len) { | 62 | if (len) { |
| 63 | len = min(len, SRAM_SIZE); | 63 | len = min_t(unsigned, len, SRAM_SIZE); |
| 64 | sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); | 64 | sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); |
| 65 | if (!sram_pool) | 65 | if (!sram_pool) |
| 66 | status = -ENOMEM; | 66 | status = -ENOMEM; |
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 0884ca57bfb0..0d1b6d407b46 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c | |||
| @@ -406,11 +406,11 @@ struct sys_timer davinci_timer = { | |||
| 406 | void davinci_watchdog_reset(void) | 406 | void davinci_watchdog_reset(void) |
| 407 | { | 407 | { |
| 408 | u32 tgcr, wdtcr; | 408 | u32 tgcr, wdtcr; |
| 409 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 409 | struct platform_device *pdev = &davinci_wdt_device; |
| 410 | void __iomem *base = soc_info->wdt_base; | 410 | void __iomem *base = IO_ADDRESS(pdev->resource[0].start); |
| 411 | struct clk *wd_clk; | 411 | struct clk *wd_clk; |
| 412 | 412 | ||
| 413 | wd_clk = clk_get(&davinci_wdt_device.dev, NULL); | 413 | wd_clk = clk_get(&pdev->dev, NULL); |
| 414 | if (WARN_ON(IS_ERR(wd_clk))) | 414 | if (WARN_ON(IS_ERR(wd_clk))) |
| 415 | return; | 415 | return; |
| 416 | clk_enable(wd_clk); | 416 | clk_enable(wd_clk); |
| @@ -420,11 +420,11 @@ void davinci_watchdog_reset(void) | |||
| 420 | 420 | ||
| 421 | /* reset timer, set mode to 64-bit watchdog, and unreset */ | 421 | /* reset timer, set mode to 64-bit watchdog, and unreset */ |
| 422 | tgcr = 0; | 422 | tgcr = 0; |
| 423 | __raw_writel(tgcr, base + TCR); | 423 | __raw_writel(tgcr, base + TGCR); |
| 424 | tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; | 424 | tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; |
| 425 | tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | | 425 | tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | |
| 426 | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); | 426 | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); |
| 427 | __raw_writel(tgcr, base + TCR); | 427 | __raw_writel(tgcr, base + TGCR); |
| 428 | 428 | ||
| 429 | /* clear counter and period regs */ | 429 | /* clear counter and period regs */ |
| 430 | __raw_writel(0, base + TIM12); | 430 | __raw_writel(0, base + TIM12); |
| @@ -432,12 +432,8 @@ void davinci_watchdog_reset(void) | |||
| 432 | __raw_writel(0, base + PRD12); | 432 | __raw_writel(0, base + PRD12); |
| 433 | __raw_writel(0, base + PRD34); | 433 | __raw_writel(0, base + PRD34); |
| 434 | 434 | ||
| 435 | /* enable */ | ||
| 436 | wdtcr = __raw_readl(base + WDTCR); | ||
| 437 | wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; | ||
| 438 | __raw_writel(wdtcr, base + WDTCR); | ||
| 439 | |||
| 440 | /* put watchdog in pre-active state */ | 435 | /* put watchdog in pre-active state */ |
| 436 | wdtcr = __raw_readl(base + WDTCR); | ||
| 441 | wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | | 437 | wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | |
| 442 | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); | 438 | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); |
| 443 | __raw_writel(wdtcr, base + WDTCR); | 439 | __raw_writel(wdtcr, base + WDTCR); |
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index abedb6337182..06f55931620c 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <mach/common.h> | 13 | #include <mach/common.h> |
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | #include <mach/irqs.h> | 15 | #include <mach/irqs.h> |
| 16 | #include <mach/cputype.h> | ||
| 16 | 17 | ||
| 17 | #define DAVINCI_USB_OTG_BASE 0x01C64000 | 18 | #define DAVINCI_USB_OTG_BASE 0x01C64000 |
| 18 | 19 | ||
| @@ -64,6 +65,10 @@ static struct resource usb_resources[] = { | |||
| 64 | .start = IRQ_USBINT, | 65 | .start = IRQ_USBINT, |
| 65 | .flags = IORESOURCE_IRQ, | 66 | .flags = IORESOURCE_IRQ, |
| 66 | }, | 67 | }, |
| 68 | { | ||
| 69 | /* placeholder for the dedicated CPPI IRQ */ | ||
| 70 | .flags = IORESOURCE_IRQ, | ||
| 71 | }, | ||
| 67 | }; | 72 | }; |
| 68 | 73 | ||
| 69 | static u64 usb_dmamask = DMA_BIT_MASK(32); | 74 | static u64 usb_dmamask = DMA_BIT_MASK(32); |
| @@ -84,6 +89,14 @@ void __init setup_usb(unsigned mA, unsigned potpgt_msec) | |||
| 84 | { | 89 | { |
| 85 | usb_data.power = mA / 2; | 90 | usb_data.power = mA / 2; |
| 86 | usb_data.potpgt = potpgt_msec / 2; | 91 | usb_data.potpgt = potpgt_msec / 2; |
| 92 | |||
| 93 | if (cpu_is_davinci_dm646x()) { | ||
| 94 | /* Override the defaults as DM6467 uses different IRQs. */ | ||
| 95 | usb_dev.resource[1].start = IRQ_DM646X_USBINT; | ||
| 96 | usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT; | ||
| 97 | } else /* other devices don't have dedicated CPPI IRQ */ | ||
| 98 | usb_dev.num_resources = 2; | ||
| 99 | |||
| 87 | platform_device_register(&usb_dev); | 100 | platform_device_register(&usb_dev); |
| 88 | } | 101 | } |
| 89 | 102 | ||