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-rw-r--r--arch/arm/mach-davinci/dm355.c174
1 files changed, 162 insertions, 12 deletions
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index baaaf328de2e..059670018aff 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -30,6 +30,7 @@
30#include <mach/time.h> 30#include <mach/time.h>
31#include <mach/serial.h> 31#include <mach/serial.h>
32#include <mach/common.h> 32#include <mach/common.h>
33#include <mach/asp.h>
33 34
34#include "clock.h" 35#include "clock.h"
35#include "mux.h" 36#include "mux.h"
@@ -360,8 +361,8 @@ static struct davinci_clk dm355_clks[] = {
360 CLK(NULL, "uart1", &uart1_clk), 361 CLK(NULL, "uart1", &uart1_clk),
361 CLK(NULL, "uart2", &uart2_clk), 362 CLK(NULL, "uart2", &uart2_clk),
362 CLK("i2c_davinci.1", NULL, &i2c_clk), 363 CLK("i2c_davinci.1", NULL, &i2c_clk),
363 CLK("soc-audio.0", NULL, &asp0_clk), 364 CLK("davinci-asp.0", NULL, &asp0_clk),
364 CLK("soc-audio.1", NULL, &asp1_clk), 365 CLK("davinci-asp.1", NULL, &asp1_clk),
365 CLK("davinci_mmc.0", NULL, &mmcsd0_clk), 366 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
366 CLK("davinci_mmc.1", NULL, &mmcsd1_clk), 367 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
367 CLK(NULL, "spi0", &spi0_clk), 368 CLK(NULL, "spi0", &spi0_clk),
@@ -481,6 +482,20 @@ INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
481EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) 482EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
482EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) 483EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
483EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) 484EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
485
486MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
487MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
488MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
489MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
490MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
491
492MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
493MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
494MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
495MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
496MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
497MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
498MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
484#endif 499#endif
485}; 500};
486 501
@@ -558,17 +573,38 @@ static const s8 dma_chan_dm355_no_event[] = {
558 -1 573 -1
559}; 574};
560 575
561static struct edma_soc_info dm355_edma_info = { 576static const s8
562 .n_channel = 64, 577queue_tc_mapping[][2] = {
563 .n_region = 4, 578 /* {event queue no, TC no} */
564 .n_slot = 128, 579 {0, 0},
565 .n_tc = 2, 580 {1, 1},
566 .noevent = dma_chan_dm355_no_event, 581 {-1, -1},
582};
583
584static const s8
585queue_priority_mapping[][2] = {
586 /* {event queue no, Priority} */
587 {0, 3},
588 {1, 7},
589 {-1, -1},
590};
591
592static struct edma_soc_info dm355_edma_info[] = {
593 {
594 .n_channel = 64,
595 .n_region = 4,
596 .n_slot = 128,
597 .n_tc = 2,
598 .n_cc = 1,
599 .noevent = dma_chan_dm355_no_event,
600 .queue_tc_mapping = queue_tc_mapping,
601 .queue_priority_mapping = queue_priority_mapping,
602 },
567}; 603};
568 604
569static struct resource edma_resources[] = { 605static struct resource edma_resources[] = {
570 { 606 {
571 .name = "edma_cc", 607 .name = "edma_cc0",
572 .start = 0x01c00000, 608 .start = 0x01c00000,
573 .end = 0x01c00000 + SZ_64K - 1, 609 .end = 0x01c00000 + SZ_64K - 1,
574 .flags = IORESOURCE_MEM, 610 .flags = IORESOURCE_MEM,
@@ -586,10 +622,12 @@ static struct resource edma_resources[] = {
586 .flags = IORESOURCE_MEM, 622 .flags = IORESOURCE_MEM,
587 }, 623 },
588 { 624 {
625 .name = "edma0",
589 .start = IRQ_CCINT0, 626 .start = IRQ_CCINT0,
590 .flags = IORESOURCE_IRQ, 627 .flags = IORESOURCE_IRQ,
591 }, 628 },
592 { 629 {
630 .name = "edma0_err",
593 .start = IRQ_CCERRINT, 631 .start = IRQ_CCERRINT,
594 .flags = IORESOURCE_IRQ, 632 .flags = IORESOURCE_IRQ,
595 }, 633 },
@@ -598,12 +636,98 @@ static struct resource edma_resources[] = {
598 636
599static struct platform_device dm355_edma_device = { 637static struct platform_device dm355_edma_device = {
600 .name = "edma", 638 .name = "edma",
601 .id = -1, 639 .id = 0,
602 .dev.platform_data = &dm355_edma_info, 640 .dev.platform_data = dm355_edma_info,
603 .num_resources = ARRAY_SIZE(edma_resources), 641 .num_resources = ARRAY_SIZE(edma_resources),
604 .resource = edma_resources, 642 .resource = edma_resources,
605}; 643};
606 644
645static struct resource dm355_asp1_resources[] = {
646 {
647 .start = DAVINCI_ASP1_BASE,
648 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
649 .flags = IORESOURCE_MEM,
650 },
651 {
652 .start = DAVINCI_DMA_ASP1_TX,
653 .end = DAVINCI_DMA_ASP1_TX,
654 .flags = IORESOURCE_DMA,
655 },
656 {
657 .start = DAVINCI_DMA_ASP1_RX,
658 .end = DAVINCI_DMA_ASP1_RX,
659 .flags = IORESOURCE_DMA,
660 },
661};
662
663static struct platform_device dm355_asp1_device = {
664 .name = "davinci-asp",
665 .id = 1,
666 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
667 .resource = dm355_asp1_resources,
668};
669
670static struct resource dm355_vpss_resources[] = {
671 {
672 /* VPSS BL Base address */
673 .name = "vpss",
674 .start = 0x01c70800,
675 .end = 0x01c70800 + 0xff,
676 .flags = IORESOURCE_MEM,
677 },
678 {
679 /* VPSS CLK Base address */
680 .name = "vpss",
681 .start = 0x01c70000,
682 .end = 0x01c70000 + 0xf,
683 .flags = IORESOURCE_MEM,
684 },
685};
686
687static struct platform_device dm355_vpss_device = {
688 .name = "vpss",
689 .id = -1,
690 .dev.platform_data = "dm355_vpss",
691 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
692 .resource = dm355_vpss_resources,
693};
694
695static struct resource vpfe_resources[] = {
696 {
697 .start = IRQ_VDINT0,
698 .end = IRQ_VDINT0,
699 .flags = IORESOURCE_IRQ,
700 },
701 {
702 .start = IRQ_VDINT1,
703 .end = IRQ_VDINT1,
704 .flags = IORESOURCE_IRQ,
705 },
706 /* CCDC Base address */
707 {
708 .flags = IORESOURCE_MEM,
709 .start = 0x01c70600,
710 .end = 0x01c70600 + 0x1ff,
711 },
712};
713
714static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
715static struct platform_device vpfe_capture_dev = {
716 .name = CAPTURE_DRV_NAME,
717 .id = -1,
718 .num_resources = ARRAY_SIZE(vpfe_resources),
719 .resource = vpfe_resources,
720 .dev = {
721 .dma_mask = &vpfe_capture_dma_mask,
722 .coherent_dma_mask = DMA_BIT_MASK(32),
723 },
724};
725
726void dm355_set_vpfe_config(struct vpfe_config *cfg)
727{
728 vpfe_capture_dev.dev.platform_data = cfg;
729}
730
607/*----------------------------------------------------------------------*/ 731/*----------------------------------------------------------------------*/
608 732
609static struct map_desc dm355_io_desc[] = { 733static struct map_desc dm355_io_desc[] = {
@@ -704,7 +828,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
704 .intc_irq_prios = dm355_default_priorities, 828 .intc_irq_prios = dm355_default_priorities,
705 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 829 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
706 .timer_info = &dm355_timer_info, 830 .timer_info = &dm355_timer_info,
707 .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
708 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), 831 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
709 .gpio_num = 104, 832 .gpio_num = 104,
710 .gpio_irq = IRQ_DM355_GPIOBNK0, 833 .gpio_irq = IRQ_DM355_GPIOBNK0,
@@ -713,6 +836,19 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
713 .sram_len = SZ_32K, 836 .sram_len = SZ_32K,
714}; 837};
715 838
839void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
840{
841 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
842 if (evt_enable & ASP1_TX_EVT_EN)
843 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
844
845 if (evt_enable & ASP1_RX_EVT_EN)
846 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
847
848 dm355_asp1_device.dev.platform_data = pdata;
849 platform_device_register(&dm355_asp1_device);
850}
851
716void __init dm355_init(void) 852void __init dm355_init(void)
717{ 853{
718 davinci_common_init(&davinci_soc_info_dm355); 854 davinci_common_init(&davinci_soc_info_dm355);
@@ -725,6 +861,20 @@ static int __init dm355_init_devices(void)
725 861
726 davinci_cfg_reg(DM355_INT_EDMA_CC); 862 davinci_cfg_reg(DM355_INT_EDMA_CC);
727 platform_device_register(&dm355_edma_device); 863 platform_device_register(&dm355_edma_device);
864 platform_device_register(&dm355_vpss_device);
865 /*
866 * setup Mux configuration for vpfe input and register
867 * vpfe capture platform device
868 */
869 davinci_cfg_reg(DM355_VIN_PCLK);
870 davinci_cfg_reg(DM355_VIN_CAM_WEN);
871 davinci_cfg_reg(DM355_VIN_CAM_VD);
872 davinci_cfg_reg(DM355_VIN_CAM_HD);
873 davinci_cfg_reg(DM355_VIN_YIN_EN);
874 davinci_cfg_reg(DM355_VIN_CINL_EN);
875 davinci_cfg_reg(DM355_VIN_CINH_EN);
876 platform_device_register(&vpfe_capture_dev);
877
728 return 0; 878 return 0;
729} 879}
730postcore_initcall(dm355_init_devices); 880postcore_initcall(dm355_init_devices);