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-rw-r--r--arch/arm/mach-s3c64xx/include/mach/debug-macro.S39
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/dma.h127
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/entry-macro.S18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h48
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h60
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h53
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h49
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h44
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h71
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h42
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h74
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h40
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h36
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h54
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h70
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h69
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h46
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio.h96
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/hardware.h16
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/irqs.h214
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h107
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/memory.h18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pll.h74
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pm-core.h98
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pwm-clock.h56
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-clock.h156
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-fb.h41
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h25
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-gpio.h187
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-irq.h20
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-modem.h31
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-srom.h59
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-sys.h28
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h116
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/s3c6400.h36
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/s3c6410.h29
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/spi-clocks.h18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/system.h30
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/tick.h29
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/uncompress.h28
40 files changed, 2452 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b18ac5266dfc
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
1/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16#include <plat/regs-serial.h>
17
18 /* note, for the boot process to work we have to keep the UART
19 * virtual address aligned to an 1MiB boundary for the L1
20 * mapping the head code makes. We keep the UART virtual address
21 * aligned and add in the offset when we load the value here.
22 */
23
24 .macro addruart, rx
25 mrc p15, 0, \rx, c1, c0
26 tst \rx, #1
27 ldreq \rx, = S3C_PA_UART
28 ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
29#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
31#endif
32 .endm
33
34/* include the reset of the code which will do the work, we're only
35 * compiling for a single cpu processor type so the default of s3c2440
36 * will be fine with us.
37 */
38
39#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
new file mode 100644
index 000000000000..0a5d9268a23e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -0,0 +1,127 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - DMA support
9 */
10
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H __FILE__
13
14#define S3C_DMA_CHANNELS (16)
15
16/* see mach-s3c2410/dma.h for notes on dma channel numbers */
17
18/* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
21 */
22enum dma_ch {
23 /* DMA0/SDMA0 */
24 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2,
26 DMACH_UART1,
27 DMACH_UART1_SRC2,
28 DMACH_UART2,
29 DMACH_UART2_SRC2,
30 DMACH_UART3,
31 DMACH_UART3_SRC2,
32 DMACH_PCM0_TX,
33 DMACH_PCM0_RX,
34 DMACH_I2S0_OUT,
35 DMACH_I2S0_IN,
36 DMACH_SPI0_TX,
37 DMACH_SPI0_RX,
38 DMACH_HSI_I2SV40_TX,
39 DMACH_HSI_I2SV40_RX,
40
41 /* DMA1/SDMA1 */
42 DMACH_PCM1_TX = 16,
43 DMACH_PCM1_RX,
44 DMACH_I2S1_OUT,
45 DMACH_I2S1_IN,
46 DMACH_SPI1_TX,
47 DMACH_SPI1_RX,
48 DMACH_AC97_PCMOUT,
49 DMACH_AC97_PCMIN,
50 DMACH_AC97_MICIN,
51 DMACH_PWM,
52 DMACH_IRDA,
53 DMACH_EXTERNAL,
54 DMACH_RES1,
55 DMACH_RES2,
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
59};
60
61static __inline__ bool s3c_dma_has_circular(void)
62{
63 return true;
64}
65
66#define S3C2410_DMAF_CIRCULAR (1 << 0)
67
68#include <plat/dma.h>
69
70#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
71
72struct s3c64xx_dma_buff;
73
74/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
75 * @next: Pointer to next buffer in queue or ring.
76 * @pw: Client provided identifier
77 * @lli: Pointer to hardware descriptor this buffer is associated with.
78 * @lli_dma: Hardare address of the descriptor.
79 */
80struct s3c64xx_dma_buff {
81 struct s3c64xx_dma_buff *next;
82
83 void *pw;
84 struct pl080s_lli *lli;
85 dma_addr_t lli_dma;
86};
87
88struct s3c64xx_dmac;
89
90struct s3c2410_dma_chan {
91 unsigned char number; /* number of this dma channel */
92 unsigned char in_use; /* channel allocated */
93 unsigned char bit; /* bit for enable/disable/etc */
94 unsigned char hw_width;
95 unsigned char peripheral;
96
97 unsigned int flags;
98 enum s3c2410_dmasrc source;
99
100
101 dma_addr_t dev_addr;
102
103 struct s3c2410_dma_client *client;
104 struct s3c64xx_dmac *dmac; /* pointer to controller */
105
106 void __iomem *regs;
107
108 /* cdriver callbacks */
109 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
110 s3c2410_dma_opfn_t op_fn; /* channel op callback */
111
112 /* buffer list and information */
113 struct s3c64xx_dma_buff *curr; /* current dma buffer */
114 struct s3c64xx_dma_buff *next; /* next buffer to load */
115 struct s3c64xx_dma_buff *end; /* end of queue */
116
117 /* note, when channel is running in circular mode, curr is the
118 * first buffer enqueued, end is the last and curr is where the
119 * last buffer-done event is set-at. The buffers are not freed
120 * and the last buffer hardware descriptor points back to the
121 * first.
122 */
123};
124
125#include <plat/dma-core.h>
126
127#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..dd362604dcce
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * Low-level IRQ helper macros for the Samsung S3C64XX series
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13*/
14
15#include <mach/map.h>
16#include <mach/irqs.h>
17
18#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
new file mode 100644
index 000000000000..34212e1a7e81
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
@@ -0,0 +1,48 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank A register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
16#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
17#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
18#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
19#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
20
21#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
26#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
27
28#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
29#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
30
31#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
32#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
33
34#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
35#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
36
37#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
38#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
39
40#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
41#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
42
43#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
44#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
45
46#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
47#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)
48
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
new file mode 100644
index 000000000000..7232c037e642
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
@@ -0,0 +1,60 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank B register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
16#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
17#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
18#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
19#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
20
21#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
26#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
27#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
28#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
29#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
30
31#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
32#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
33#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
34#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
35#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
36
37#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
38#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
39#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
40#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
41#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
42#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
43
44#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
45#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
46#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
47#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
48#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
49
50#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
51#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
52#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
53#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
54
55#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
56#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
57
58#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
59#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)
60
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
new file mode 100644
index 000000000000..db189ab1639a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
@@ -0,0 +1,53 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank C register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
16#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
17#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
18#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
19#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
20
21#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
26#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
27
28#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
29#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
30
31#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
32#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
33
34#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
35#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
36
37#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
38#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
39#define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16)
40#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
41
42#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
43#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
44#define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20)
45#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
46
47#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
48#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
49
50#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
51#define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28)
52#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
53
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
new file mode 100644
index 000000000000..1a01cee7aca3
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
@@ -0,0 +1,49 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank D register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
16#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
17#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
18#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
19#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
20
21#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
26#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
27#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
28#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
29
30#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
31#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
32#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
33#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
34
35#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
36#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
37#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
38#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
39
40#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
41#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
42#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
43#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
44
45#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
46#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
47#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
48#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)
49
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
new file mode 100644
index 000000000000..f057adb627dd
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
@@ -0,0 +1,44 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank E register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
16#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
17#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
18#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
19#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
20
21#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
26#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
27#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
28
29#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
30#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
31#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
32
33#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
34#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
35#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
36
37#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
38#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
39#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
40
41#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
42#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
43#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)
44
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
new file mode 100644
index 000000000000..62ab8f5e7835
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
@@ -0,0 +1,71 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank F register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
16#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
17#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
18#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
19#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
20
21#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
26#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
27
28#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
29#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
30
31#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
32#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
33
34#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
35#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
36
37#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
38#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
39
40#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
41#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
42
43#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
44#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
45
46#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
47#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
48
49#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
50#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
51
52#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
53#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
54
55#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
56#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
57
58#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
59#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
60
61#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
62#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
63
64#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
65#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
66
67#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
68#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
69
70#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
71
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
new file mode 100644
index 000000000000..b94954af1598
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank G register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
16#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
17#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
18#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
19#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
20
21#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
26#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
27
28#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
29#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
30
31#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
32#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
33
34#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
35#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
36
37#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
38#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
39
40#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
41#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
42
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
new file mode 100644
index 000000000000..5d75aaad865e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
@@ -0,0 +1,74 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank H register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
16#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
17#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
18#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
19#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
20#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
21
22#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
23#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
24#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
25
26#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
27#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
28#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
29
30#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
31#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
32#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
33
34#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
35#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
36#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
37
38#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
39#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
40#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
41
42#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
43#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
44#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
45
46#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
47#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
48#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
49
50#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
51#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
52#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
53#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
54#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
55#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
56
57#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
58#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
59#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
60#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
61#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
62#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
63
64#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
65#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
66#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
67#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
68#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
69
70#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
71#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
72#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
73#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
74#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
new file mode 100644
index 000000000000..4ceaa6098bc7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
@@ -0,0 +1,40 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank I register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
16#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
17#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
18#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
19#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
20
21#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPI0_VD0 (0x02 << 0)
26#define S3C64XX_GPI1_VD1 (0x02 << 2)
27#define S3C64XX_GPI2_VD2 (0x02 << 4)
28#define S3C64XX_GPI3_VD3 (0x02 << 6)
29#define S3C64XX_GPI4_VD4 (0x02 << 8)
30#define S3C64XX_GPI5_VD5 (0x02 << 10)
31#define S3C64XX_GPI6_VD6 (0x02 << 12)
32#define S3C64XX_GPI7_VD7 (0x02 << 14)
33#define S3C64XX_GPI8_VD8 (0x02 << 16)
34#define S3C64XX_GPI9_VD9 (0x02 << 18)
35#define S3C64XX_GPI10_VD10 (0x02 << 20)
36#define S3C64XX_GPI11_VD11 (0x02 << 22)
37#define S3C64XX_GPI12_VD12 (0x02 << 24)
38#define S3C64XX_GPI13_VD13 (0x02 << 26)
39#define S3C64XX_GPI14_VD14 (0x02 << 28)
40#define S3C64XX_GPI15_VD15 (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
new file mode 100644
index 000000000000..6f25cd079a40
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank J register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
16#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
17#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
18#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
19#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
20
21#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPJ0_VD16 (0x02 << 0)
26#define S3C64XX_GPJ1_VD17 (0x02 << 2)
27#define S3C64XX_GPJ2_VD18 (0x02 << 4)
28#define S3C64XX_GPJ3_VD19 (0x02 << 6)
29#define S3C64XX_GPJ4_VD20 (0x02 << 8)
30#define S3C64XX_GPJ5_VD21 (0x02 << 10)
31#define S3C64XX_GPJ6_VD22 (0x02 << 12)
32#define S3C64XX_GPJ7_VD23 (0x02 << 14)
33#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
34#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
35#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
36#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
new file mode 100644
index 000000000000..d0aeda1cd9de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
@@ -0,0 +1,54 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank N register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
16#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
17#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
18
19#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
20#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
21#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
22
23#define S3C64XX_GPN0_EINT0 (0x02 << 0)
24#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
25
26#define S3C64XX_GPN1_EINT1 (0x02 << 2)
27#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
28
29#define S3C64XX_GPN2_EINT2 (0x02 << 4)
30#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
31
32#define S3C64XX_GPN3_EINT3 (0x02 << 6)
33#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
34
35#define S3C64XX_GPN4_EINT4 (0x02 << 8)
36#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
37
38#define S3C64XX_GPN5_EINT5 (0x02 << 10)
39#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
40
41#define S3C64XX_GPN6_EINT6 (0x02 << 12)
42#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
43
44#define S3C64XX_GPN7_EINT7 (0x02 << 14)
45#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
46
47#define S3C64XX_GPN8_EINT8 (0x02 << 16)
48#define S3C64XX_GPN9_EINT9 (0x02 << 18)
49#define S3C64XX_GPN10_EINT10 (0x02 << 20)
50#define S3C64XX_GPN11_EINT11 (0x02 << 22)
51#define S3C64XX_GPN12_EINT12 (0x02 << 24)
52#define S3C64XX_GPN13_EINT13 (0x02 << 26)
53#define S3C64XX_GPN14_EINT14 (0x02 << 28)
54#define S3C64XX_GPN15_EINT15 (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
new file mode 100644
index 000000000000..21868fa102d0
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank O register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
16#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
17#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
18#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
19#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
20
21#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
26#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
27
28#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
29#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
30
31#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
32#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
33
34#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
35#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
36
37#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
38
39#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
40
41#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
42#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
43
44#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
45#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
46
47#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
48#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
49
50#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
51#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
52
53#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
54#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
55
56#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
57#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
58
59#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
60#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
61
62#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
63#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
64
65#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
66#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
67
68#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
69#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)
70
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
new file mode 100644
index 000000000000..46bcfb63b8de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
@@ -0,0 +1,69 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank P register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
16#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
17#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
18#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
19#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
20
21#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
26#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
27
28#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
29#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
30
31#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
32#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
33
34#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
35#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
36
37#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
38#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
39
40#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
41#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
42
43#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
44#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
45
46#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
47#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
48
49#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
50#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
51
52#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
53#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
54
55#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
56#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
57
58#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
59#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
60
61#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
62#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
63
64#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
65#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
66
67#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
68#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
69
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
new file mode 100644
index 000000000000..1712223487b0
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank Q register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
16#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
17#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
18#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
19#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
20
21#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
26#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
27
28#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
29#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
30
31#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
32
33#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
34
35#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
36
37#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
38
39#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
40
41#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
42#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
43
44#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
45#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)
46
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
new file mode 100644
index 000000000000..e8e35e8fe731
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -0,0 +1,96 @@
1/* arch/arm/mach-s3c6400/include/mach/gpio.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C6400 - GPIO lib support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define gpio_get_value __gpio_get_value
16#define gpio_set_value __gpio_set_value
17#define gpio_cansleep __gpio_cansleep
18#define gpio_to_irq __gpio_to_irq
19
20/* GPIO bank sizes */
21#define S3C64XX_GPIO_A_NR (8)
22#define S3C64XX_GPIO_B_NR (7)
23#define S3C64XX_GPIO_C_NR (8)
24#define S3C64XX_GPIO_D_NR (5)
25#define S3C64XX_GPIO_E_NR (5)
26#define S3C64XX_GPIO_F_NR (16)
27#define S3C64XX_GPIO_G_NR (7)
28#define S3C64XX_GPIO_H_NR (10)
29#define S3C64XX_GPIO_I_NR (16)
30#define S3C64XX_GPIO_J_NR (12)
31#define S3C64XX_GPIO_K_NR (16)
32#define S3C64XX_GPIO_L_NR (15)
33#define S3C64XX_GPIO_M_NR (6)
34#define S3C64XX_GPIO_N_NR (16)
35#define S3C64XX_GPIO_O_NR (16)
36#define S3C64XX_GPIO_P_NR (15)
37#define S3C64XX_GPIO_Q_NR (9)
38
39/* GPIO bank numbes */
40
41/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
42 * space for debugging purposes so that any accidental
43 * change from one gpio bank to another can be caught.
44*/
45
46#define S3C64XX_GPIO_NEXT(__gpio) \
47 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
48
49enum s3c_gpio_number {
50 S3C64XX_GPIO_A_START = 0,
51 S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
52 S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
53 S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
54 S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
55 S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
56 S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
57 S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
58 S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
59 S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
60 S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
61 S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
62 S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
63 S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
64 S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
65 S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
66 S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
67};
68
69/* S3C64XX GPIO number definitions. */
70
71#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
72#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
73#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
74#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
75#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
76#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
77#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
78#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
79#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
80#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
81#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
82#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
83#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
84#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
85#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
86#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
87#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
88
89/* the end of the S3C64XX specific gpios */
90#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
91#define S3C_GPIO_END S3C64XX_GPIO_END
92
93/* define the number of gpios we need to the one after the GPQ() range */
94#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
95
96#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s3c64xx/include/mach/hardware.h b/arch/arm/mach-s3c64xx/include/mach/hardware.h
new file mode 100644
index 000000000000..862d033e57a4
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/hardware.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - Hardware support
9 */
10
11#ifndef __ASM_ARCH_HARDWARE_H
12#define __ASM_ARCH_HARDWARE_H __FILE__
13
14/* currently nothing here, placeholder */
15
16#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
new file mode 100644
index 000000000000..44bb3e491b5c
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -0,0 +1,214 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - IRQ support
9 */
10
11#ifndef __ASM_MACH_S3C64XX_IRQS_H
12#define __ASM_MACH_S3C64XX_IRQS_H __FILE__
13
14/* we keep the first set of CPU IRQs out of the range of
15 * the ISA space, so that the PC104 has them to itself
16 * and we don't end up having to do horrible things to the
17 * standard ISA drivers....
18 *
19 * note, since we're using the VICs, our start must be a
20 * mulitple of 32 to allow the common code to work
21 */
22
23#define S3C_IRQ_OFFSET (32)
24
25#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
26
27#define IRQ_VIC0_BASE S3C_IRQ(0)
28#define IRQ_VIC1_BASE S3C_IRQ(32)
29
30/* UART interrupts, each UART has 4 intterupts per channel so
31 * use the space between the ISA and S3C main interrupts. Note, these
32 * are not in the same order as the S3C24XX series! */
33
34#define IRQ_S3CUART_BASE0 (16)
35#define IRQ_S3CUART_BASE1 (20)
36#define IRQ_S3CUART_BASE2 (24)
37#define IRQ_S3CUART_BASE3 (28)
38
39#define UART_IRQ_RXD (0)
40#define UART_IRQ_ERR (1)
41#define UART_IRQ_TXD (2)
42#define UART_IRQ_MODEM (3)
43
44#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
45#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
46#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
47
48#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
49#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
50#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
51
52#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
53#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
54#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
55
56#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
57#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
58#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
59
60/* VIC based IRQs */
61
62#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
63#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
64
65/* VIC0 */
66
67#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
68#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
69#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
70#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
71#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
72#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
73#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
74#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
75#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
76#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
77#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
78#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
79#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
80#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
81#define IRQ_2D S3C64XX_IRQ_VIC0(11)
82#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
83#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
84#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
85#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
86#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
87#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
88#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
89#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
90#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
91#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
92#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
93#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
94#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
95#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
96#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
97#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
98#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
99#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
100#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
101#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
102
103/* VIC1 */
104
105#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
106#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
107#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
108#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
109#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
110#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
111#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
112#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
113#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
114#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
115#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
116#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
117#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
118#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
119#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
120#define IRQ_USBH S3C64XX_IRQ_VIC1(15)
121#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
122#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
123#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
124#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
125#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
126#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
127#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
128#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
129#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
130#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
131#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
132#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
133#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
134#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
135#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
136#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
137#define IRQ_TC IRQ_PENDN
138#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
139
140#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
141
142#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
143#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
144#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
145#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
146#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
147
148/* compatibility for device defines */
149
150#define IRQ_IIC1 IRQ_S3C6410_IIC1
151
152/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
153 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
154 * which we place after the pair of VICs. */
155
156#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
157
158#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
159#define IRQ_EINT(x) S3C_EINT(x)
160#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
161
162/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
163 * that they are sourced from the GPIO pins but with a different scheme for
164 * priority and source indication.
165 *
166 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
167 * interrupts, but for historical reasons they are kept apart from these
168 * next interrupts.
169 *
170 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
171 * machine specific support files.
172 */
173
174#define IRQ_EINT_GROUP1_NR (15)
175#define IRQ_EINT_GROUP2_NR (8)
176#define IRQ_EINT_GROUP3_NR (5)
177#define IRQ_EINT_GROUP4_NR (14)
178#define IRQ_EINT_GROUP5_NR (7)
179#define IRQ_EINT_GROUP6_NR (10)
180#define IRQ_EINT_GROUP7_NR (16)
181#define IRQ_EINT_GROUP8_NR (15)
182#define IRQ_EINT_GROUP9_NR (9)
183
184#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
185#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
186#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
187#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
188#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
189#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
190#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
191#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
192#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
193#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
194
195#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no))
196
197/* Define a group of interrupts for board-specific use (eg, for MFD
198 * interrupt controllers). */
199#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
200
201#ifdef CONFIG_SMDK6410_WM1190_EV1
202#define IRQ_BOARD_NR 64
203#else
204#define IRQ_BOARD_NR 16
205#endif
206
207#define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR)
208
209/* Set the default NR_IRQS */
210
211#define NR_IRQS (IRQ_BOARD_END + 1)
212
213#endif /* __ASM_MACH_S3C64XX_IRQS_H */
214
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
new file mode 100644
index 000000000000..801c1c0f3a95
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -0,0 +1,107 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/map.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - Memory map definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_MAP_H
16#define __ASM_ARCH_MAP_H __FILE__
17
18#include <plat/map-base.h>
19
20/*
21 * Post-mux Chip Select Regions Xm0CSn_
22 * These may be used by SROM, NAND or CF depending on settings
23 */
24
25#define S3C64XX_PA_XM0CSN0 (0x10000000)
26#define S3C64XX_PA_XM0CSN1 (0x18000000)
27#define S3C64XX_PA_XM0CSN2 (0x20000000)
28#define S3C64XX_PA_XM0CSN3 (0x28000000)
29#define S3C64XX_PA_XM0CSN4 (0x30000000)
30#define S3C64XX_PA_XM0CSN5 (0x38000000)
31
32/* HSMMC units */
33#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
34#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
36#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
37
38#define S3C_PA_UART (0x7F005000)
39#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
40#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
41#define S3C_PA_UART2 (S3C_PA_UART + 0x800)
42#define S3C_PA_UART3 (S3C_PA_UART + 0xC00)
43#define S3C_UART_OFFSET (0x400)
44
45/* See notes on UART VA mapping in debug-macro.S */
46#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
47
48#define S3C_VA_UART0 S3C_VA_UARTx(0)
49#define S3C_VA_UART1 S3C_VA_UARTx(1)
50#define S3C_VA_UART2 S3C_VA_UARTx(2)
51#define S3C_VA_UART3 S3C_VA_UARTx(3)
52
53#define S3C64XX_PA_SROM (0x70000000)
54
55#define S3C64XX_PA_NAND (0x70200000)
56#define S3C64XX_PA_FB (0x77100000)
57#define S3C64XX_PA_USB_HSOTG (0x7C000000)
58#define S3C64XX_PA_WATCHDOG (0x7E004000)
59#define S3C64XX_PA_RTC (0x7E005000)
60#define S3C64XX_PA_ADC (0x7E00B000)
61#define S3C64XX_PA_SYSCON (0x7E00F000)
62#define S3C64XX_PA_AC97 (0x7F001000)
63#define S3C64XX_PA_IIS0 (0x7F002000)
64#define S3C64XX_PA_IIS1 (0x7F003000)
65#define S3C64XX_PA_TIMER (0x7F006000)
66#define S3C64XX_PA_IIC0 (0x7F004000)
67#define S3C64XX_PA_SPI0 (0x7F00B000)
68#define S3C64XX_PA_SPI1 (0x7F00C000)
69#define S3C64XX_PA_PCM0 (0x7F009000)
70#define S3C64XX_PA_PCM1 (0x7F00A000)
71#define S3C64XX_PA_IISV4 (0x7F00D000)
72#define S3C64XX_PA_IIC1 (0x7F00F000)
73
74#define S3C64XX_PA_GPIO (0x7F008000)
75#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
76#define S3C64XX_SZ_GPIO SZ_4K
77
78#define S3C64XX_PA_SDRAM (0x50000000)
79#define S3C64XX_PA_VIC0 (0x71200000)
80#define S3C64XX_PA_VIC1 (0x71300000)
81
82#define S3C64XX_PA_MODEM (0x74108000)
83#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
84
85#define S3C64XX_PA_USBHOST (0x74300000)
86
87#define S3C64XX_PA_USB_HSPHY (0x7C100000)
88#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
89
90/* place VICs close together */
91#define VA_VIC0 (S3C_VA_IRQ + 0x00)
92#define VA_VIC1 (S3C_VA_IRQ + 0x10000)
93
94/* compatibiltiy defines. */
95#define S3C_PA_TIMER S3C64XX_PA_TIMER
96#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
97#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
98#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
99#define S3C_PA_IIC S3C64XX_PA_IIC0
100#define S3C_PA_IIC1 S3C64XX_PA_IIC1
101#define S3C_PA_NAND S3C64XX_PA_NAND
102#define S3C_PA_FB S3C64XX_PA_FB
103#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
104#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
105#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
106
107#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
new file mode 100644
index 000000000000..a3ac84a65480
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/memory.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c6400/include/mach/memory.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PHYS_OFFSET UL(0x50000000)
17
18#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
new file mode 100644
index 000000000000..90bbd72fdc4e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pll.h
@@ -0,0 +1,74 @@
1/* arch/arm/plat-s3c64xx/include/plat/pll.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX PLL code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
16#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
17#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
18#define S3C6400_PLL_MDIV_SHIFT (16)
19#define S3C6400_PLL_PDIV_SHIFT (8)
20#define S3C6400_PLL_SDIV_SHIFT (0)
21
22#include <asm/div64.h>
23
24static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
25 u32 pllcon)
26{
27 u32 mdiv, pdiv, sdiv;
28 u64 fvco = baseclk;
29
30 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
31 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
32 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
33
34 fvco *= mdiv;
35 do_div(fvco, (pdiv << sdiv));
36
37 return (unsigned long)fvco;
38}
39
40#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
41#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
42#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
43#define S3C6400_EPLL_MDIV_SHIFT (16)
44#define S3C6400_EPLL_PDIV_SHIFT (8)
45#define S3C6400_EPLL_SDIV_SHIFT (0)
46#define S3C6400_EPLL_KDIV_MASK (0xffff)
47
48static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
49{
50 unsigned long result;
51 u32 epll0 = __raw_readl(S3C_EPLL_CON0);
52 u32 epll1 = __raw_readl(S3C_EPLL_CON1);
53 u32 mdiv, pdiv, sdiv, kdiv;
54 u64 tmp;
55
56 mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
57 pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
58 sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
59 kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
60
61 /* We need to multiple baseclk by mdiv (the integer part) and kdiv
62 * which is in 2^16ths, so shift mdiv up (does not overflow) and
63 * add kdiv before multiplying. The use of tmp is to avoid any
64 * overflows before shifting bac down into result when multipling
65 * by the mdiv and kdiv pair.
66 */
67
68 tmp = baseclk;
69 tmp *= (mdiv << 16) + kdiv;
70 do_div(tmp, (pdiv << sdiv));
71 result = tmp >> 16;
72
73 return result;
74}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
new file mode 100644
index 000000000000..1e9f20f0bb7b
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -0,0 +1,98 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <mach/regs-gpio.h>
16
17static inline void s3c_pm_debug_init_uart(void)
18{
19 u32 tmp = __raw_readl(S3C_PCLK_GATE);
20
21 /* As a note, since the S3C64XX UARTs generally have multiple
22 * clock sources, we simply enable PCLK at the moment and hope
23 * that the resume settings for the UART are suitable for the
24 * use with PCLK.
25 */
26
27 tmp |= S3C_CLKCON_PCLK_UART0;
28 tmp |= S3C_CLKCON_PCLK_UART1;
29 tmp |= S3C_CLKCON_PCLK_UART2;
30 tmp |= S3C_CLKCON_PCLK_UART3;
31
32 __raw_writel(tmp, S3C_PCLK_GATE);
33 udelay(10);
34}
35
36static inline void s3c_pm_arch_prepare_irqs(void)
37{
38 /* VIC should have already been taken care of */
39
40 /* clear any pending EINT0 interrupts */
41 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
42}
43
44static inline void s3c_pm_arch_stop_clocks(void)
45{
46}
47
48static inline void s3c_pm_arch_show_resume_irqs(void)
49{
50}
51
52/* make these defines, we currently do not have any need to change
53 * the IRQ wake controls depending on the CPU we are running on */
54
55#define s3c_irqwake_eintallow ((1 << 28) - 1)
56#define s3c_irqwake_intallow (0)
57
58static inline void s3c_pm_arch_update_uart(void __iomem *regs,
59 struct pm_uart_save *save)
60{
61 u32 ucon = __raw_readl(regs + S3C2410_UCON);
62 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
63 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
64 u32 new_ucon;
65 u32 delta;
66
67 /* S3C64XX UART blocks only support level interrupts, so ensure that
68 * when we restore unused UART blocks we force the level interrupt
69 * settigs. */
70 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
71
72 /* We have a constraint on changing the clock type of the UART
73 * between UCLKx and PCLK, so ensure that when we restore UCON
74 * that the CLK field is correctly modified if the bootloader
75 * has changed anything.
76 */
77 if (ucon_clk != save_clk) {
78 new_ucon = save->ucon;
79 delta = ucon_clk ^ save_clk;
80
81 /* change from UCLKx => wrong PCLK,
82 * either UCLK can be tested for by a bit-test
83 * with UCLK0 */
84 if (ucon_clk & S3C6400_UCON_UCLK0 &&
85 !(save_clk & S3C6400_UCON_UCLK0) &&
86 delta & S3C6400_UCON_PCLK2) {
87 new_ucon &= ~S3C6400_UCON_UCLK0;
88 } else if (delta == S3C6400_UCON_PCLK2) {
89 /* as an precaution, don't change from
90 * PCLK2 => PCLK or vice-versa */
91 new_ucon ^= S3C6400_UCON_PCLK2;
92 }
93
94 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
95 ucon, new_ucon, save->ucon);
96 save->ucon = new_ucon;
97 }
98}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..b25bedee0d52
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64xx - pwm clock and timer support
9 */
10
11/**
12 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
13 * @tcfg: The timer TCFG1 register bits shifted down to 0.
14 *
15 * Return true if the given configuration from TCFG1 is a TCLK instead
16 * any of the TDIV clocks.
17 */
18static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
19{
20 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
21}
22
23/**
24 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
25 * @tcfg1: The tcfg1 setting, shifted down.
26 *
27 * Get the divisor value for the given tcfg1 setting. We assume the
28 * caller has already checked to see if this is not a TCLK source.
29 */
30static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
31{
32 return 1 << tcfg1;
33}
34
35/**
36 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
37 *
38 * Return true if we have a /1 in the tdiv setting.
39 */
40static inline unsigned int pwm_tdiv_has_div1(void)
41{
42 return 1;
43}
44
45/**
46 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
47 * @div: The divisor to calculate the bit information for.
48 *
49 * Turn a divisor into the necessary bit field for TCFG1.
50 */
51static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
52{
53 return ilog2(div);
54}
55
56#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
new file mode 100644
index 000000000000..3ef62741e5d1
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -0,0 +1,156 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX clock register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_REGS_CLOCK_H
16#define __PLAT_REGS_CLOCK_H __FILE__
17
18#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S3C_APLL_LOCK S3C_CLKREG(0x00)
21#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
22#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
23#define S3C_APLL_CON S3C_CLKREG(0x0C)
24#define S3C_MPLL_CON S3C_CLKREG(0x10)
25#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
26#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
27#define S3C_CLK_SRC S3C_CLKREG(0x1C)
28#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
29#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
30#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
31#define S3C_CLK_OUT S3C_CLKREG(0x2C)
32#define S3C_HCLK_GATE S3C_CLKREG(0x30)
33#define S3C_PCLK_GATE S3C_CLKREG(0x34)
34#define S3C_SCLK_GATE S3C_CLKREG(0x38)
35#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
36
37/* CLKDIV0 */
38#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
39#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
40#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
41#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
42#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
43#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
44#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
45#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
46
47#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
48#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
49#define S3C6400_CLKDIV0_ARM_SHIFT (0)
50
51/* HCLK GATE Registers */
52#define S3C_CLKCON_HCLK_3DSE (1<<31)
53#define S3C_CLKCON_HCLK_UHOST (1<<29)
54#define S3C_CLKCON_HCLK_SECUR (1<<28)
55#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
56#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
57#define S3C_CLKCON_HCLK_IROM (1<<25)
58#define S3C_CLKCON_HCLK_DDR1 (1<<24)
59#define S3C_CLKCON_HCLK_DDR0 (1<<23)
60#define S3C_CLKCON_HCLK_MEM1 (1<<22)
61#define S3C_CLKCON_HCLK_MEM0 (1<<21)
62#define S3C_CLKCON_HCLK_USB (1<<20)
63#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
64#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
65#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
66#define S3C_CLKCON_HCLK_MDP (1<<16)
67#define S3C_CLKCON_HCLK_DHOST (1<<15)
68#define S3C_CLKCON_HCLK_IHOST (1<<14)
69#define S3C_CLKCON_HCLK_DMA1 (1<<13)
70#define S3C_CLKCON_HCLK_DMA0 (1<<12)
71#define S3C_CLKCON_HCLK_JPEG (1<<11)
72#define S3C_CLKCON_HCLK_CAMIF (1<<10)
73#define S3C_CLKCON_HCLK_SCALER (1<<9)
74#define S3C_CLKCON_HCLK_2D (1<<8)
75#define S3C_CLKCON_HCLK_TV (1<<7)
76#define S3C_CLKCON_HCLK_POST0 (1<<5)
77#define S3C_CLKCON_HCLK_ROT (1<<4)
78#define S3C_CLKCON_HCLK_LCD (1<<3)
79#define S3C_CLKCON_HCLK_TZIC (1<<2)
80#define S3C_CLKCON_HCLK_INTC (1<<1)
81#define S3C_CLKCON_HCLK_MFC (1<<0)
82
83/* PCLK GATE Registers */
84#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
85#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
86#define S3C_CLKCON_PCLK_SKEY (1<<24)
87#define S3C_CLKCON_PCLK_CHIPID (1<<23)
88#define S3C_CLKCON_PCLK_SPI1 (1<<22)
89#define S3C_CLKCON_PCLK_SPI0 (1<<21)
90#define S3C_CLKCON_PCLK_HSIRX (1<<20)
91#define S3C_CLKCON_PCLK_HSITX (1<<19)
92#define S3C_CLKCON_PCLK_GPIO (1<<18)
93#define S3C_CLKCON_PCLK_IIC (1<<17)
94#define S3C_CLKCON_PCLK_IIS1 (1<<16)
95#define S3C_CLKCON_PCLK_IIS0 (1<<15)
96#define S3C_CLKCON_PCLK_AC97 (1<<14)
97#define S3C_CLKCON_PCLK_TZPC (1<<13)
98#define S3C_CLKCON_PCLK_TSADC (1<<12)
99#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
100#define S3C_CLKCON_PCLK_IRDA (1<<10)
101#define S3C_CLKCON_PCLK_PCM1 (1<<9)
102#define S3C_CLKCON_PCLK_PCM0 (1<<8)
103#define S3C_CLKCON_PCLK_PWM (1<<7)
104#define S3C_CLKCON_PCLK_RTC (1<<6)
105#define S3C_CLKCON_PCLK_WDT (1<<5)
106#define S3C_CLKCON_PCLK_UART3 (1<<4)
107#define S3C_CLKCON_PCLK_UART2 (1<<3)
108#define S3C_CLKCON_PCLK_UART1 (1<<2)
109#define S3C_CLKCON_PCLK_UART0 (1<<1)
110#define S3C_CLKCON_PCLK_MFC (1<<0)
111
112/* SCLK GATE Registers */
113#define S3C_CLKCON_SCLK_UHOST (1<<30)
114#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
115#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
116#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
117#define S3C_CLKCON_SCLK_MMC2 (1<<26)
118#define S3C_CLKCON_SCLK_MMC1 (1<<25)
119#define S3C_CLKCON_SCLK_MMC0 (1<<24)
120#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
121#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
122#define S3C_CLKCON_SCLK_SPI1 (1<<21)
123#define S3C_CLKCON_SCLK_SPI0 (1<<20)
124#define S3C_CLKCON_SCLK_DAC27 (1<<19)
125#define S3C_CLKCON_SCLK_TV27 (1<<18)
126#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
127#define S3C_CLKCON_SCLK_SCALER (1<<16)
128#define S3C_CLKCON_SCLK_LCD27 (1<<15)
129#define S3C_CLKCON_SCLK_LCD (1<<14)
130#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
131#define S3C6410_CLKCON_FIMC (1<<13)
132#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
133#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
134#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
135#define S3C_CLKCON_SCLK_POST0 (1<<10)
136#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
137#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
138#define S3C_CLKCON_SCLK_SECUR (1<<7)
139#define S3C_CLKCON_SCLK_IRDA (1<<6)
140#define S3C_CLKCON_SCLK_UART (1<<5)
141#define S3C_CLKCON_SCLK_ONENAND (1<<4)
142#define S3C_CLKCON_SCLK_MFC (1<<3)
143#define S3C_CLKCON_SCLK_CAM (1<<2)
144#define S3C_CLKCON_SCLK_JPEG (1<<1)
145
146/* CLKSRC */
147
148#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
149#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
150#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
151#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
152#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
153#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
154#define S3C6400_CLKSRC_MFC (1 << 4)
155
156#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
new file mode 100644
index 000000000000..f56611526c63
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2009 Samsung Electronics Co.
5 *
6 * Pawel Osciak <p.osciak@samsung.com>
7 * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
8 *
9 * Framebuffer register definitions for Samsung S3C64xx.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARCH_MACH_REGS_FB_H
17#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
18
19#include <plat/regs-fb-v4.h>
20
21/* Palette registers */
22#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
23#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
24#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
25#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
26#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
27
28static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
29{
30 switch (window) {
31 case 0: return WIN0_PAL(reg);
32 case 1: return WIN1_PAL(reg);
33 case 2: return WIN2_PAL(reg);
34 case 3: return WIN3_PAL(reg);
35 case 4: return WIN4_PAL(reg);
36 }
37
38 BUG();
39}
40
41#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
new file mode 100644
index 000000000000..82342f6fd27d
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO memory port register definitions
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
12#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
13
14#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
16
17#define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18#define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19#define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
20
21#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
23
24#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
25
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..81f7f6e6832e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
@@ -0,0 +1,187 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO register definitions
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
12#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
13
14/* Base addresses for each of the banks */
15
16#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg))
17
18#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
19#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
20#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
21#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
22#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
23#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
24#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
25#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
26#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
27#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
28#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800)
29#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810)
30#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820)
31#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830)
32#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140)
33#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160)
34#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180)
35
36/* SPCON */
37
38#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0)
39
40#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30)
41#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30)
42#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30)
43#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30)
44#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30)
45#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30)
46
47#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28)
48#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28)
49#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28)
50#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28)
51#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28)
52#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28)
53
54#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26)
55#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26)
56#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26)
57#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26)
58#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26)
59#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26)
60
61#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24)
62#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24)
63#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24)
64#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24)
65#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24)
66#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24)
67
68#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22)
69#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22)
70#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22)
71#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22)
72#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22)
73#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22)
74
75#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21)
76
77#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18)
78#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18)
79#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18)
80#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18)
81#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18)
82#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18)
83
84#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16)
85#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16)
86#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16)
87#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16)
88#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16)
89
90#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14)
91#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14)
92#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14)
93#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14)
94#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14)
95
96#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12)
97#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12)
98#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12)
99#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12)
100#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12)
101
102#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8)
103#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8)
104#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8)
105#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8)
106#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8)
107
108#define S3C64XX_SPCON_USBH_DMPD (1 << 7)
109#define S3C64XX_SPCON_USBH_DPPD (1 << 6)
110#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5)
111#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4)
112#define S3C64XX_SPCON_USBH_SUSPND (1 << 3)
113
114#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0)
115#define S3C64XX_SPCON_LCD_SEL_SHIFT (0)
116#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0)
117#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0)
118#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0)
119
120
121/* External interrupt registers */
122
123#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200)
124#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204)
125#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208)
126#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C)
127#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210)
128
129#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220)
130#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224)
131#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228)
132#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C)
133#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230)
134
135#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240)
136#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244)
137#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248)
138#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C)
139#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250)
140
141#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260)
142#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264)
143#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268)
144#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C)
145#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270)
146
147#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280)
148#define S3C64XX_PRIORITY_ARB(x) (1 << (x))
149
150#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284)
151#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288)
152
153#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
154#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
155#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
156#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
157#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
158#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
159
160#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
161#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
162
163/* GPIO sleep configuration */
164
165#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880)
166
167#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14)
168#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5)
169
170#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12)
171#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12)
172#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12)
173#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12)
174
175#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0)
176#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0)
177#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0)
178#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0)
179
180
181#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930)
182
183#define S3C64XX_SLPEN_USE_xSLP (1 << 0)
184#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1)
185
186#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
187
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
new file mode 100644
index 000000000000..bcce68a0bb75
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - IRQ register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_REGS_IRQ_H
16#define __ASM_ARCH_REGS_IRQ_H __FILE__
17
18#include <asm/hardware/vic.h>
19
20#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
new file mode 100644
index 000000000000..49f7759dedfa
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-modem.h
@@ -0,0 +1,31 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - modem block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_MODEM_H
16#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
17
18#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x))
19
20#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0)
21#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4)
22#define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8)
23#define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC)
24#define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10)
25#define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14)
26#define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18)
27
28#define MIFPCON_INT2M_LEVEL (1 << 4)
29#define MIFPCON_LCD_BYPASS (1 << 3)
30
31#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
new file mode 100644
index 000000000000..756731b36297
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-srom.h
@@ -0,0 +1,59 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
2 *
3 * Copyright 2009 Andy Green <andy@warmcat.com>
4 *
5 * S3C64XX SROM definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __PLAT_REGS_SROM_H
13#define __PLAT_REGS_SROM_H __FILE__
14
15#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
16
17#define S3C64XX_SROM_BW S3C64XX_SROMREG(0)
18#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4)
19#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8)
20#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc)
21#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10)
22#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14)
23#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18)
24
25/*
26 * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
27 */
28
29#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
30#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
31#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
32#define S3C64XX_SROM_BW__CS_MASK 0xf
33
34#define S3C64XX_SROM_BW__NCS0__SHIFT 0
35#define S3C64XX_SROM_BW__NCS1__SHIFT 4
36#define S3C64XX_SROM_BW__NCS2__SHIFT 8
37#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc
38#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10
39
40/*
41 * applies to same to BCS0 - BCS4
42 */
43
44#define S3C64XX_SROM_BCX__PMC__SHIFT 0
45#define S3C64XX_SROM_BCX__PMC__MASK 3
46#define S3C64XX_SROM_BCX__TACP__SHIFT 4
47#define S3C64XX_SROM_BCX__TACP__MASK 0xf
48#define S3C64XX_SROM_BCX__TCAH__SHIFT 8
49#define S3C64XX_SROM_BCX__TCAH__MASK 0xf
50#define S3C64XX_SROM_BCX__TCOH__SHIFT 12
51#define S3C64XX_SROM_BCX__TCOH__MASK 0xf
52#define S3C64XX_SROM_BCX__TACC__SHIFT 16
53#define S3C64XX_SROM_BCX__TACC__MASK 0x1f
54#define S3C64XX_SROM_BCX__TCOS__SHIFT 24
55#define S3C64XX_SROM_BCX__TCOS__MASK 0xf
56#define S3C64XX_SROM_BCX__TACS__SHIFT 28
57#define S3C64XX_SROM_BCX__TACS__MASK 0xf
58
59#endif /* _PLAT_REGS_SROM_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
new file mode 100644
index 000000000000..69b78d9f83b8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
@@ -0,0 +1,28 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX system register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_REGS_SYS_H
16#define __PLAT_REGS_SYS_H __FILE__
17
18#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
19
20#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
23
24#define S3C64XX_OTHERS S3C_SYSREG(0x900)
25
26#define S3C64XX_OTHERS_USBMASK (1 << 16)
27
28#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
new file mode 100644
index 000000000000..270d96ac9705
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h
@@ -0,0 +1,116 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - syscon power and sleep control registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
16#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
17
18#define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
19
20#define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17)
21#define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16)
22#define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15)
23#define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14)
24#define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13)
25#define S3C64XX_PWRCFG_TS_DISABLE (1 << 12)
26#define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11)
27#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10)
28#define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9)
29#define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8)
30#define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7)
31
32#define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
33#define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5)
34#define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
35#define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
36#define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
37#define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
38
39#define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
40#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3)
41#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
42#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
43#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
44
45#define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2)
46#define S3C64XX_PWRCFG_OSC27_EN (1 << 0)
47
48#define S3C64XX_EINT_MASK S3C_SYSREG(0x808)
49
50#define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810)
51
52#define S3C64XX_NORMALCFG_IROM_ON (1 << 30)
53#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16)
54#define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15)
55#define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14)
56#define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13)
57#define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12)
58#define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10)
59#define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9)
60
61#define S3C64XX_STOP_CFG S3C_SYSREG(0x814)
62
63#define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29)
64#define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20)
65#define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17)
66#define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8)
67#define S3C64XX_STOPCFG_OSC_EN (1 << 0)
68
69#define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818)
70
71#define S3C64XX_SLEEPCFG_OSC_EN (1 << 0)
72
73#define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c)
74
75#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6)
76#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5)
77#define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4)
78#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3)
79#define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2)
80#define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1)
81#define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0)
82
83#define S3C64XX_OSC_STABLE S3C_SYSREG(0x824)
84#define S3C64XX_PWR_STABLE S3C_SYSREG(0x828)
85
86#define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908)
87
88#define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11)
89#define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10)
90#define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9)
91#define S3C64XX_WAKEUPSTAT_HSI (1 << 8)
92#define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6)
93#define S3C64XX_WAKEUPSTAT_MSM (1 << 5)
94#define S3C64XX_WAKEUPSTAT_KEY (1 << 4)
95#define S3C64XX_WAKEUPSTAT_TS (1 << 3)
96#define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2)
97#define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1)
98#define S3C64XX_WAKEUPSTAT_EINT (1 << 0)
99
100#define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c)
101
102#define S3C64XX_BLKPWRSTAT_G (1 << 7)
103#define S3C64XX_BLKPWRSTAT_ETM (1 << 6)
104#define S3C64XX_BLKPWRSTAT_S (1 << 5)
105#define S3C64XX_BLKPWRSTAT_F (1 << 4)
106#define S3C64XX_BLKPWRSTAT_P (1 << 3)
107#define S3C64XX_BLKPWRSTAT_I (1 << 2)
108#define S3C64XX_BLKPWRSTAT_V (1 << 1)
109#define S3C64XX_BLKPWRSTAT_TOP (1 << 0)
110
111#define S3C64XX_INFORM0 S3C_SYSREG(0xA00)
112#define S3C64XX_INFORM1 S3C_SYSREG(0xA04)
113#define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
114#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
115
116#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
new file mode 100644
index 000000000000..f86958d05352
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
@@ -0,0 +1,36 @@
1/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6400 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S3C6400 related SoCs */
16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_setup_clocks(void);
19
20extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
21
22#ifdef CONFIG_CPU_S3C6400
23
24extern int s3c6400_init(void);
25extern void s3c6400_init_irq(void);
26extern void s3c6400_map_io(void);
27extern void s3c6400_init_clocks(int xtal);
28
29#define s3c6400_init_uarts s3c6400_common_init_uarts
30
31#else
32#define s3c6400_init_clocks NULL
33#define s3c6400_init_uarts NULL
34#define s3c6400_map_io NULL
35#define s3c6400_init NULL
36#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
new file mode 100644
index 000000000000..24f1141ffcb7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
@@ -0,0 +1,29 @@
1/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6410 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifdef CONFIG_CPU_S3C6410
16
17extern int s3c6410_init(void);
18extern void s3c6410_init_irq(void);
19extern void s3c6410_map_io(void);
20extern void s3c6410_init_clocks(int xtal);
21
22#define s3c6410_init_uarts s3c6400_common_init_uarts
23
24#else
25#define s3c6410_init_clocks NULL
26#define s3c6410_init_uarts NULL
27#define s3c6410_map_io NULL
28#define s3c6410_init NULL
29#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..9d0c43b4b687
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_CLKS_H
12#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
13
14#define S3C64XX_SPI_SRCCLK_PCLK 0
15#define S3C64XX_SPI_SRCCLK_SPIBUS 1
16#define S3C64XX_SPI_SRCCLK_48M 2
17
18#endif /* __S3C64XX_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
new file mode 100644
index 000000000000..2e58cb7a7147
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
@@ -0,0 +1,30 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/system.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - system implementation
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__
13
14#include <plat/watchdog-reset.h>
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20
21static void arch_reset(char mode, const char *cmd)
22{
23 if (mode != 's')
24 arch_wdt_reset();
25
26 /* if all else fails, or mode was for soft, jump to 0 */
27 cpu_reset(0);
28}
29
30#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h
new file mode 100644
index 000000000000..ebe18a9469b8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/tick.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - Timer tick support definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_TICK_H
16#define __ASM_ARCH_TICK_H __FILE__
17
18/* note, the timer interrutps turn up in 2 places, the vic and then
19 * the timer block. We take the VIC as the base at the moment.
20 */
21static inline u32 s3c24xx_ostimer_pending(void)
22{
23 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
24 return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
25}
26
27#define TICK_MAX (0xffffffff)
28
29#endif /* __ASM_ARCH_6400_TICK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c6a82a20bf2a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -0,0 +1,28 @@
1/* arch/arm/mach-s3c6400/include/mach/uncompress.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C6400 - uncompress code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_UNCOMPRESS_H
16#define __ASM_ARCH_UNCOMPRESS_H
17
18#include <mach/map.h>
19#include <plat/uncompress.h>
20
21static void arch_detect_cpu(void)
22{
23 /* we do not need to do any cpu detection here at the moment. */
24 fifo_mask = S3C2440_UFSTAT_TXMASK;
25 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
26}
27
28#endif /* __ASM_ARCH_UNCOMPRESS_H */
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