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Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h')
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h69
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
new file mode 100644
index 000000000000..46bcfb63b8de
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
@@ -0,0 +1,69 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank P register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
16#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
17#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
18#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
19#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
20
21#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
26#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
27
28#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
29#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
30
31#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
32#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
33
34#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
35#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
36
37#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
38#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
39
40#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
41#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
42
43#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
44#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
45
46#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
47#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
48
49#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
50#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
51
52#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
53#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
54
55#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
56#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
57
58#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
59#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
60
61#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
62#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
63
64#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
65#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
66
67#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
68#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
69