diff options
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h')
-rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h new file mode 100644 index 000000000000..62ab8f5e7835 --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h | |||
@@ -0,0 +1,71 @@ | |||
1 | /* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank F register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00) | ||
16 | #define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04) | ||
17 | #define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08) | ||
18 | #define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c) | ||
19 | #define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0) | ||
26 | #define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2) | ||
29 | #define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4) | ||
32 | #define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4) | ||
33 | |||
34 | #define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6) | ||
35 | #define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6) | ||
36 | |||
37 | #define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8) | ||
38 | #define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8) | ||
39 | |||
40 | #define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10) | ||
41 | #define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10) | ||
42 | |||
43 | #define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12) | ||
44 | #define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12) | ||
45 | |||
46 | #define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14) | ||
47 | #define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14) | ||
48 | |||
49 | #define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16) | ||
50 | #define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16) | ||
51 | |||
52 | #define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18) | ||
53 | #define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18) | ||
54 | |||
55 | #define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20) | ||
56 | #define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20) | ||
57 | |||
58 | #define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22) | ||
59 | #define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22) | ||
60 | |||
61 | #define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24) | ||
62 | #define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24) | ||
63 | |||
64 | #define S3C64XX_GPF13_PWM_ECLK (0x02 << 26) | ||
65 | #define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26) | ||
66 | |||
67 | #define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28) | ||
68 | #define S3C64XX_GPF14_CLKOUT0 (0x03 << 28) | ||
69 | |||
70 | #define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30) | ||
71 | |||