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-rw-r--r--arch/arm/mach-davinci/include/mach/asp.h56
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h24
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h121
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-davinci/include/mach/dm355.h7
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h29
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h65
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h67
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h13
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h17
-rw-r--r--arch/arm/mach-davinci/include/mach/io.h23
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h205
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h9
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h731
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h62
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h6
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-davinci/include/mach/vmalloc.h2
21 files changed, 1422 insertions, 40 deletions
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index e0abc437d796..18e4ce34ece6 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -5,21 +5,73 @@
5#define __ASM_ARCH_DAVINCI_ASP_H 5#define __ASM_ARCH_DAVINCI_ASP_H
6 6
7#include <mach/irqs.h> 7#include <mach/irqs.h>
8#include <mach/edma.h>
8 9
9/* Bases of register banks */ 10/* Bases of dm644x and dm355 register banks */
10#define DAVINCI_ASP0_BASE 0x01E02000 11#define DAVINCI_ASP0_BASE 0x01E02000
11#define DAVINCI_ASP1_BASE 0x01E04000 12#define DAVINCI_ASP1_BASE 0x01E04000
12 13
13/* EDMA channels */ 14/* Bases of dm646x register banks */
15#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
16#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
17
18/* Bases of da850/da830 McASP0 register banks */
19#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
20
21/* Bases of da830 McASP1 register banks */
22#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
23
24/* EDMA channels of dm644x and dm355 */
14#define DAVINCI_DMA_ASP0_TX 2 25#define DAVINCI_DMA_ASP0_TX 2
15#define DAVINCI_DMA_ASP0_RX 3 26#define DAVINCI_DMA_ASP0_RX 3
16#define DAVINCI_DMA_ASP1_TX 8 27#define DAVINCI_DMA_ASP1_TX 8
17#define DAVINCI_DMA_ASP1_RX 9 28#define DAVINCI_DMA_ASP1_RX 9
18 29
30/* EDMA channels of dm646x */
31#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
32#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
33#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
34
35/* EDMA channels of da850/da830 McASP0 */
36#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
37#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
38
39/* EDMA channels of da830 McASP1 */
40#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
41#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
42
19/* Interrupts */ 43/* Interrupts */
20#define DAVINCI_ASP0_RX_INT IRQ_MBRINT 44#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
21#define DAVINCI_ASP0_TX_INT IRQ_MBXINT 45#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
22#define DAVINCI_ASP1_RX_INT IRQ_MBRINT 46#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
23#define DAVINCI_ASP1_TX_INT IRQ_MBXINT 47#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
24 48
49struct snd_platform_data {
50 u32 tx_dma_offset;
51 u32 rx_dma_offset;
52 enum dma_event_q eventq_no; /* event queue number */
53 unsigned int codec_fmt;
54
55 /* McASP specific fields */
56 int tdm_slots;
57 u8 op_mode;
58 u8 num_serializer;
59 u8 *serial_dir;
60 u8 version;
61 u8 txnumevt;
62 u8 rxnumevt;
63};
64
65enum {
66 MCASP_VERSION_1 = 0, /* DM646x */
67 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
68};
69
70#define INACTIVE_MODE 0
71#define TX_MODE 1
72#define RX_MODE 2
73
74#define DAVINCI_MCASP_IIS_MODE 0
75#define DAVINCI_MCASP_DIT_MODE 1
76
25#endif /* __ASM_ARCH_DAVINCI_ASP_H */ 77#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a1f03b606d8f..1fd3917cae4e 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -60,10 +60,10 @@ struct davinci_soc_info {
60 u8 *intc_irq_prios; 60 u8 *intc_irq_prios;
61 unsigned long intc_irq_num; 61 unsigned long intc_irq_num;
62 struct davinci_timer_info *timer_info; 62 struct davinci_timer_info *timer_info;
63 void __iomem *wdt_base;
64 void __iomem *gpio_base; 63 void __iomem *gpio_base;
65 unsigned gpio_num; 64 unsigned gpio_num;
66 unsigned gpio_irq; 65 unsigned gpio_irq;
66 unsigned gpio_unbanked;
67 struct platform_device *serial_dev; 67 struct platform_device *serial_dev;
68 struct emac_platform_data *emac_pdata; 68 struct emac_platform_data *emac_pdata;
69 dma_addr_t sram_dma; 69 dma_addr_t sram_dma;
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index d12a5ed2959a..189b1ff13642 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -30,6 +30,9 @@ struct davinci_id {
30#define DAVINCI_CPU_ID_DM6446 0x64460000 30#define DAVINCI_CPU_ID_DM6446 0x64460000
31#define DAVINCI_CPU_ID_DM6467 0x64670000 31#define DAVINCI_CPU_ID_DM6467 0x64670000
32#define DAVINCI_CPU_ID_DM355 0x03550000 32#define DAVINCI_CPU_ID_DM355 0x03550000
33#define DAVINCI_CPU_ID_DM365 0x03650000
34#define DAVINCI_CPU_ID_DA830 0x08300000
35#define DAVINCI_CPU_ID_DA850 0x08500000
33 36
34#define IS_DAVINCI_CPU(type, id) \ 37#define IS_DAVINCI_CPU(type, id) \
35static inline int is_davinci_ ##type(void) \ 38static inline int is_davinci_ ##type(void) \
@@ -40,6 +43,9 @@ static inline int is_davinci_ ##type(void) \
40IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) 43IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
41IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) 44IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
42IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) 45IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
46IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
47IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
48IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
43 49
44#ifdef CONFIG_ARCH_DAVINCI_DM644x 50#ifdef CONFIG_ARCH_DAVINCI_DM644x
45#define cpu_is_davinci_dm644x() is_davinci_dm644x() 51#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -59,4 +65,22 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
59#define cpu_is_davinci_dm355() 0 65#define cpu_is_davinci_dm355() 0
60#endif 66#endif
61 67
68#ifdef CONFIG_ARCH_DAVINCI_DM365
69#define cpu_is_davinci_dm365() is_davinci_dm365()
70#else
71#define cpu_is_davinci_dm365() 0
72#endif
73
74#ifdef CONFIG_ARCH_DAVINCI_DA830
75#define cpu_is_davinci_da830() is_davinci_da830()
76#else
77#define cpu_is_davinci_da830() 0
78#endif
79
80#ifdef CONFIG_ARCH_DAVINCI_DA850
81#define cpu_is_davinci_da850() is_davinci_da850()
82#else
83#define cpu_is_davinci_da850() 0
84#endif
85
62#endif 86#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
new file mode 100644
index 000000000000..d4095d0572c6
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -0,0 +1,121 @@
1/*
2 * Chip specific defines for DA8XX/OMAP L1XX SoC
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
12#define __ASM_ARCH_DAVINCI_DA8XX_H
13
14#include <mach/serial.h>
15#include <mach/edma.h>
16#include <mach/i2c.h>
17#include <mach/emac.h>
18#include <mach/asp.h>
19#include <mach/mmc.h>
20
21/*
22 * The cp_intc interrupt controller for the da8xx isn't in the same
23 * chunk of physical memory space as the other registers (like it is
24 * on the davincis) so it needs to be mapped separately. It will be
25 * mapped early on when the I/O space is mapped and we'll put it just
26 * before the I/O space in the processor's virtual memory space.
27 */
28#define DA8XX_CP_INTC_BASE 0xfffee000
29#define DA8XX_CP_INTC_SIZE SZ_8K
30#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
31
32#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000)
33
34#define DA8XX_PSC0_BASE 0x01c10000
35#define DA8XX_PLL0_BASE 0x01c11000
36#define DA8XX_JTAG_ID_REG 0x01c14018
37#define DA8XX_TIMER64P0_BASE 0x01c20000
38#define DA8XX_TIMER64P1_BASE 0x01c21000
39#define DA8XX_GPIO_BASE 0x01e26000
40#define DA8XX_PSC1_BASE 0x01e27000
41#define DA8XX_LCD_CNTRL_BASE 0x01e13000
42#define DA8XX_MMCSD0_BASE 0x01c40000
43#define DA8XX_AEMIF_CS2_BASE 0x60000000
44#define DA8XX_AEMIF_CS3_BASE 0x62000000
45#define DA8XX_AEMIF_CTL_BASE 0x68000000
46
47#define PINMUX0 0x00
48#define PINMUX1 0x04
49#define PINMUX2 0x08
50#define PINMUX3 0x0c
51#define PINMUX4 0x10
52#define PINMUX5 0x14
53#define PINMUX6 0x18
54#define PINMUX7 0x1c
55#define PINMUX8 0x20
56#define PINMUX9 0x24
57#define PINMUX10 0x28
58#define PINMUX11 0x2c
59#define PINMUX12 0x30
60#define PINMUX13 0x34
61#define PINMUX14 0x38
62#define PINMUX15 0x3c
63#define PINMUX16 0x40
64#define PINMUX17 0x44
65#define PINMUX18 0x48
66#define PINMUX19 0x4c
67
68void __init da830_init(void);
69void __init da850_init(void);
70
71int da8xx_register_edma(void);
72int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
73int da8xx_register_watchdog(void);
74int da8xx_register_emac(void);
75int da8xx_register_lcdc(void);
76int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
77void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata);
78
79extern struct platform_device da8xx_serial_device;
80extern struct emac_platform_data da8xx_emac_pdata;
81
82extern const short da830_emif25_pins[];
83extern const short da830_spi0_pins[];
84extern const short da830_spi1_pins[];
85extern const short da830_mmc_sd_pins[];
86extern const short da830_uart0_pins[];
87extern const short da830_uart1_pins[];
88extern const short da830_uart2_pins[];
89extern const short da830_usb20_pins[];
90extern const short da830_usb11_pins[];
91extern const short da830_uhpi_pins[];
92extern const short da830_cpgmac_pins[];
93extern const short da830_emif3c_pins[];
94extern const short da830_mcasp0_pins[];
95extern const short da830_mcasp1_pins[];
96extern const short da830_mcasp2_pins[];
97extern const short da830_i2c0_pins[];
98extern const short da830_i2c1_pins[];
99extern const short da830_lcdcntl_pins[];
100extern const short da830_pwm_pins[];
101extern const short da830_ecap0_pins[];
102extern const short da830_ecap1_pins[];
103extern const short da830_ecap2_pins[];
104extern const short da830_eqep0_pins[];
105extern const short da830_eqep1_pins[];
106
107extern const short da850_uart0_pins[];
108extern const short da850_uart1_pins[];
109extern const short da850_uart2_pins[];
110extern const short da850_i2c0_pins[];
111extern const short da850_i2c1_pins[];
112extern const short da850_cpgmac_pins[];
113extern const short da850_mcasp_pins[];
114extern const short da850_lcdcntl_pins[];
115extern const short da850_mmcsd0_pins[];
116extern const short da850_nand_pins[];
117extern const short da850_nor_pins[];
118
119int da8xx_pinmux_setup(const short pins[]);
120
121#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index de3fc2182b47..17ab5236da66 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -24,7 +24,15 @@
24 tst \rx, #1 @ MMU enabled? 24 tst \rx, #1 @ MMU enabled?
25 moveq \rx, #0x01000000 @ physical base address 25 moveq \rx, #0x01000000 @ physical base address
26 movne \rx, #0xfe000000 @ virtual base 26 movne \rx, #0xfe000000 @ virtual base
27#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
28#error Cannot enable DaVinci and DA8XX platforms concurrently
29#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
30 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
31 orr \rx, \rx, #0x00d00000 @ physical base address
32 orr \rx, \rx, #0x0000d000 @ of UART 2
33#else
27 orr \rx, \rx, #0x00c20000 @ UART 0 34 orr \rx, \rx, #0x00c20000 @ UART 0
35#endif
28 .endm 36 .endm
29 37
30 .macro senduart,rd,rx 38 .macro senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
index 54903b72438e..85536d8e8336 100644
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -12,11 +12,18 @@
12#define __ASM_ARCH_DM355_H 12#define __ASM_ARCH_DM355_H
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/asp.h>
16#include <media/davinci/vpfe_capture.h>
17
18#define ASP1_TX_EVT_EN 1
19#define ASP1_RX_EVT_EN 2
15 20
16struct spi_board_info; 21struct spi_board_info;
17 22
18void __init dm355_init(void); 23void __init dm355_init(void);
19void dm355_init_spi0(unsigned chipselect_mask, 24void dm355_init_spi0(unsigned chipselect_mask,
20 struct spi_board_info *info, unsigned len); 25 struct spi_board_info *info, unsigned len);
26void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
27void dm355_set_vpfe_config(struct vpfe_config *cfg);
21 28
22#endif /* __ASM_ARCH_DM355_H */ 29#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
new file mode 100644
index 000000000000..09db4343bb4c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009 Texas Instruments Incorporated
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __ASM_ARCH_DM365_H
14#define __ASM_ARCH_DM665_H
15
16#include <linux/platform_device.h>
17#include <mach/hardware.h>
18#include <mach/emac.h>
19
20#define DM365_EMAC_BASE (0x01D07000)
21#define DM365_EMAC_CNTRL_OFFSET (0x0000)
22#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
23#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
24#define DM365_EMAC_MDIO_OFFSET (0x4000)
25#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
26
27void __init dm365_init(void);
28
29#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 15d42b92a8c9..0efb73852c2c 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -25,6 +25,8 @@
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/emac.h> 27#include <mach/emac.h>
28#include <mach/asp.h>
29#include <media/davinci/vpfe_capture.h>
28 30
29#define DM644X_EMAC_BASE (0x01C80000) 31#define DM644X_EMAC_BASE (0x01C80000)
30#define DM644X_EMAC_CNTRL_OFFSET (0x0000) 32#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
@@ -34,5 +36,7 @@
34#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) 36#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
35 37
36void __init dm644x_init(void); 38void __init dm644x_init(void);
39void __init dm644x_init_asp(struct snd_platform_data *pdata);
40void dm644x_set_vpfe_config(struct vpfe_config *cfg);
37 41
38#endif /* __ASM_ARCH_DM644X_H */ 42#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 1fc764c8646e..8cec746ae9d2 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -13,6 +13,9 @@
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/emac.h> 15#include <mach/emac.h>
16#include <mach/asp.h>
17#include <linux/i2c.h>
18#include <linux/videodev2.h>
16 19
17#define DM646X_EMAC_BASE (0x01C80000) 20#define DM646X_EMAC_BASE (0x01C80000)
18#define DM646X_EMAC_CNTRL_OFFSET (0x0000) 21#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
@@ -21,6 +24,68 @@
21#define DM646X_EMAC_MDIO_OFFSET (0x4000) 24#define DM646X_EMAC_MDIO_OFFSET (0x4000)
22#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) 25#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
23 26
27#define DM646X_ATA_REG_BASE (0x01C66000)
28
24void __init dm646x_init(void); 29void __init dm646x_init(void);
30void __init dm646x_init_ide(void);
31void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
32void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
33
34void dm646x_video_init(void);
35
36enum vpif_if_type {
37 VPIF_IF_BT656,
38 VPIF_IF_BT1120,
39 VPIF_IF_RAW_BAYER
40};
41
42struct vpif_interface {
43 enum vpif_if_type if_type;
44 unsigned hd_pol:1;
45 unsigned vd_pol:1;
46 unsigned fid_pol:1;
47};
48
49struct vpif_subdev_info {
50 const char *name;
51 struct i2c_board_info board_info;
52 u32 input;
53 u32 output;
54 unsigned can_route:1;
55 struct vpif_interface vpif_if;
56};
57
58struct vpif_display_config {
59 int (*set_clock)(int, int);
60 struct vpif_subdev_info *subdevinfo;
61 int subdev_count;
62 const char **output;
63 int output_count;
64 const char *card_name;
65};
66
67struct vpif_input {
68 struct v4l2_input input;
69 const char *subdev_name;
70};
71
72#define VPIF_CAPTURE_MAX_CHANNELS 2
73
74struct vpif_capture_chan_config {
75 const struct vpif_input *inputs;
76 int input_count;
77};
78
79struct vpif_capture_config {
80 int (*setup_input_channel_mode)(int);
81 int (*setup_input_path)(int, const char *);
82 struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS];
83 struct vpif_subdev_info *subdev_info;
84 int subdev_count;
85 const char *card_name;
86};
87
88void dm646x_setup_vpif(struct vpif_display_config *,
89 struct vpif_capture_config *);
25 90
26#endif /* __ASM_ARCH_DM646X_H */ 91#endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index 24a379239d7f..eb8bfd7925e7 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -139,6 +139,54 @@ struct edmacc_param {
139#define DAVINCI_DMA_PWM1 53 139#define DAVINCI_DMA_PWM1 53
140#define DAVINCI_DMA_PWM2 54 140#define DAVINCI_DMA_PWM2 54
141 141
142/* DA830 specific EDMA3 information */
143#define EDMA_DA830_NUM_DMACH 32
144#define EDMA_DA830_NUM_TCC 32
145#define EDMA_DA830_NUM_PARAMENTRY 128
146#define EDMA_DA830_NUM_EVQUE 2
147#define EDMA_DA830_NUM_TC 2
148#define EDMA_DA830_CHMAP_EXIST 0
149#define EDMA_DA830_NUM_REGIONS 4
150#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
151#define DA830_DMACH2EVENT_MAP1 0x00000000u
152#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
153
154/* DA830 specific EDMA3 Events Information */
155enum DA830_edma_ch {
156 DA830_DMACH_MCASP0_RX,
157 DA830_DMACH_MCASP0_TX,
158 DA830_DMACH_MCASP1_RX,
159 DA830_DMACH_MCASP1_TX,
160 DA830_DMACH_MCASP2_RX,
161 DA830_DMACH_MCASP2_TX,
162 DA830_DMACH_GPIO_BNK0INT,
163 DA830_DMACH_GPIO_BNK1INT,
164 DA830_DMACH_UART0_RX,
165 DA830_DMACH_UART0_TX,
166 DA830_DMACH_TMR64P0_EVTOUT12,
167 DA830_DMACH_TMR64P0_EVTOUT34,
168 DA830_DMACH_UART1_RX,
169 DA830_DMACH_UART1_TX,
170 DA830_DMACH_SPI0_RX,
171 DA830_DMACH_SPI0_TX,
172 DA830_DMACH_MMCSD_RX,
173 DA830_DMACH_MMCSD_TX,
174 DA830_DMACH_SPI1_RX,
175 DA830_DMACH_SPI1_TX,
176 DA830_DMACH_DMAX_EVTOUT6,
177 DA830_DMACH_DMAX_EVTOUT7,
178 DA830_DMACH_GPIO_BNK2INT,
179 DA830_DMACH_GPIO_BNK3INT,
180 DA830_DMACH_I2C0_RX,
181 DA830_DMACH_I2C0_TX,
182 DA830_DMACH_I2C1_RX,
183 DA830_DMACH_I2C1_TX,
184 DA830_DMACH_GPIO_BNK4INT,
185 DA830_DMACH_GPIO_BNK5INT,
186 DA830_DMACH_UART2_RX,
187 DA830_DMACH_UART2_TX
188};
189
142/*ch_status paramater of callback function possible values*/ 190/*ch_status paramater of callback function possible values*/
143#define DMA_COMPLETE 1 191#define DMA_COMPLETE 1
144#define DMA_CC_ERROR 2 192#define DMA_CC_ERROR 2
@@ -162,6 +210,8 @@ enum fifo_width {
162enum dma_event_q { 210enum dma_event_q {
163 EVENTQ_0 = 0, 211 EVENTQ_0 = 0,
164 EVENTQ_1 = 1, 212 EVENTQ_1 = 1,
213 EVENTQ_2 = 2,
214 EVENTQ_3 = 3,
165 EVENTQ_DEFAULT = -1 215 EVENTQ_DEFAULT = -1
166}; 216};
167 217
@@ -170,8 +220,15 @@ enum sync_dimension {
170 ABSYNC = 1 220 ABSYNC = 1
171}; 221};
172 222
223#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
224#define EDMA_CTLR(i) ((i) >> 16)
225#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
226
173#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ 227#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
174#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ 228#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
229#define EDMA_CONT_PARAMS_ANY 1001
230#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
231#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
175 232
176/* alloc/free DMA channels and their dedicated parameter RAM slots */ 233/* alloc/free DMA channels and their dedicated parameter RAM slots */
177int edma_alloc_channel(int channel, 234int edma_alloc_channel(int channel,
@@ -180,9 +237,13 @@ int edma_alloc_channel(int channel,
180void edma_free_channel(unsigned channel); 237void edma_free_channel(unsigned channel);
181 238
182/* alloc/free parameter RAM slots */ 239/* alloc/free parameter RAM slots */
183int edma_alloc_slot(int slot); 240int edma_alloc_slot(unsigned ctlr, int slot);
184void edma_free_slot(unsigned slot); 241void edma_free_slot(unsigned slot);
185 242
243/* alloc/free a set of contiguous parameter RAM slots */
244int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
245int edma_free_cont_slots(unsigned slot, int count);
246
186/* calls that operate on part of a parameter RAM slot */ 247/* calls that operate on part of a parameter RAM slot */
187void edma_set_src(unsigned slot, dma_addr_t src_port, 248void edma_set_src(unsigned slot, dma_addr_t src_port,
188 enum address_mode mode, enum fifo_width); 249 enum address_mode mode, enum fifo_width);
@@ -216,9 +277,13 @@ struct edma_soc_info {
216 unsigned n_region; 277 unsigned n_region;
217 unsigned n_slot; 278 unsigned n_slot;
218 unsigned n_tc; 279 unsigned n_tc;
280 unsigned n_cc;
281 enum dma_event_q default_queue;
219 282
220 /* list of channels with no even trigger; terminated by "-1" */ 283 /* list of channels with no even trigger; terminated by "-1" */
221 const s8 *noevent; 284 const s8 *noevent;
285 const s8 (*queue_tc_mapping)[2];
286 const s8 (*queue_priority_mapping)[2];
222}; 287};
223 288
224#endif 289#endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index ae0745568316..f3b8ef878158 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -42,6 +42,9 @@
42 */ 42 */
43#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ 43#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
44 44
45/* Convert GPIO signal to GPIO pin number */
46#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
47
45struct gpio_controller { 48struct gpio_controller {
46 u32 dir; 49 u32 dir;
47 u32 out_data; 50 u32 out_data;
@@ -78,6 +81,8 @@ __gpio_to_controller(unsigned gpio)
78 ptr = base + 0x60; 81 ptr = base + 0x60;
79 else if (gpio < 32 * 4) 82 else if (gpio < 32 * 4)
80 ptr = base + 0x88; 83 ptr = base + 0x88;
84 else if (gpio < 32 * 5)
85 ptr = base + 0xb0;
81 else 86 else
82 ptr = NULL; 87 ptr = NULL;
83 return ptr; 88 return ptr;
@@ -142,15 +147,13 @@ static inline int gpio_cansleep(unsigned gpio)
142 147
143static inline int gpio_to_irq(unsigned gpio) 148static inline int gpio_to_irq(unsigned gpio)
144{ 149{
145 if (gpio >= DAVINCI_N_GPIO) 150 return __gpio_to_irq(gpio);
146 return -EINVAL;
147 return davinci_soc_info.intc_irq_num + gpio;
148} 151}
149 152
150static inline int irq_to_gpio(unsigned irq) 153static inline int irq_to_gpio(unsigned irq)
151{ 154{
152 /* caller guarantees gpio_to_irq() succeeded */ 155 /* don't support the reverse mapping */
153 return irq - davinci_soc_info.intc_irq_num; 156 return -ENOSYS;
154} 157}
155 158
156#endif /* __DAVINCI_GPIO_H */ 159#endif /* __DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 48c77934d519..41c89386e39b 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -24,4 +24,21 @@
24/* System control register offsets */ 24/* System control register offsets */
25#define DM64XX_VDD3P3V_PWDN 0x48 25#define DM64XX_VDD3P3V_PWDN 0x48
26 26
27/*
28 * I/O mapping
29 */
30#define IO_PHYS 0x01c00000
31#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
32#define IO_SIZE 0x00400000
33#define IO_VIRT (IO_PHYS + IO_OFFSET)
34#define io_v2p(va) ((va) - IO_OFFSET)
35#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
36#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
37
38#ifdef __ASSEMBLER__
39#define IOMEM(x) x
40#else
41#define IOMEM(x) ((void __force __iomem *)(x))
42#endif
43
27#endif /* __ASM_ARCH_HARDWARE_H */ 44#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 2479785405af..62b0a90309ad 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -14,18 +14,6 @@
14#define IO_SPACE_LIMIT 0xffffffff 14#define IO_SPACE_LIMIT 0xffffffff
15 15
16/* 16/*
17 * ----------------------------------------------------------------------------
18 * I/O mapping
19 * ----------------------------------------------------------------------------
20 */
21#define IO_PHYS 0x01c00000
22#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
23#define IO_SIZE 0x00400000
24#define IO_VIRT (IO_PHYS + IO_OFFSET)
25#define io_v2p(va) ((va) - IO_OFFSET)
26#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
27
28/*
29 * We don't actually have real ISA nor PCI buses, but there is so many 17 * We don't actually have real ISA nor PCI buses, but there is so many
30 * drivers out there that might just work if we fake them... 18 * drivers out there that might just work if we fake them...
31 */ 19 */
@@ -33,19 +21,12 @@
33#define __mem_pci(a) (a) 21#define __mem_pci(a) (a)
34#define __mem_isa(a) (a) 22#define __mem_isa(a) (a)
35 23
36#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) 24#ifndef __ASSEMBLER__
37
38#ifdef __ASSEMBLER__
39#define IOMEM(x) x
40#else
41#define IOMEM(x) ((void __force __iomem *)(x))
42
43#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) 25#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
44#define __arch_iounmap(v) davinci_iounmap(v) 26#define __arch_iounmap(v) davinci_iounmap(v)
45 27
46void __iomem *davinci_ioremap(unsigned long phys, size_t size, 28void __iomem *davinci_ioremap(unsigned long phys, size_t size,
47 unsigned int type); 29 unsigned int type);
48void davinci_iounmap(volatile void __iomem *addr); 30void davinci_iounmap(volatile void __iomem *addr);
49 31#endif
50#endif /* __ASSEMBLER__ */
51#endif /* __ASM_ARCH_IO_H */ 32#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index bc5d6aaa69a3..3c918a772619 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -99,9 +99,6 @@
99#define IRQ_EMUINT 63 99#define IRQ_EMUINT 63
100 100
101#define DAVINCI_N_AINTC_IRQ 64 101#define DAVINCI_N_AINTC_IRQ 64
102#define DAVINCI_N_GPIO 104
103
104#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
105 102
106#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
107 104
@@ -206,4 +203,206 @@
206#define IRQ_DM355_GPIOBNK5 59 203#define IRQ_DM355_GPIOBNK5 59
207#define IRQ_DM355_GPIOBNK6 60 204#define IRQ_DM355_GPIOBNK6 60
208 205
206/* DaVinci DM365-specific Interrupts */
207#define IRQ_DM365_INSFINT 7
208#define IRQ_DM365_IMXINT1 8
209#define IRQ_DM365_IMXINT0 10
210#define IRQ_DM365_KLD_ARMINT 10
211#define IRQ_DM365_IMCOPINT 11
212#define IRQ_DM365_RTOINT 13
213#define IRQ_DM365_TINT5 14
214#define IRQ_DM365_TINT6 15
215#define IRQ_DM365_SPINT2_1 21
216#define IRQ_DM365_TINT7 22
217#define IRQ_DM365_SDIOINT0 23
218#define IRQ_DM365_MMCINT1 27
219#define IRQ_DM365_PWMINT3 28
220#define IRQ_DM365_SDIOINT1 31
221#define IRQ_DM365_SPIINT0_0 42
222#define IRQ_DM365_SPIINT3_0 43
223#define IRQ_DM365_GPIO0 44
224#define IRQ_DM365_GPIO1 45
225#define IRQ_DM365_GPIO2 46
226#define IRQ_DM365_GPIO3 47
227#define IRQ_DM365_GPIO4 48
228#define IRQ_DM365_GPIO5 49
229#define IRQ_DM365_GPIO6 50
230#define IRQ_DM365_GPIO7 51
231#define IRQ_DM365_EMAC_RXTHRESH 52
232#define IRQ_DM365_EMAC_RXPULSE 53
233#define IRQ_DM365_EMAC_TXPULSE 54
234#define IRQ_DM365_EMAC_MISCPULSE 55
235#define IRQ_DM365_GPIO12 56
236#define IRQ_DM365_GPIO13 57
237#define IRQ_DM365_GPIO14 58
238#define IRQ_DM365_GPIO15 59
239#define IRQ_DM365_ADCINT 59
240#define IRQ_DM365_KEYINT 60
241#define IRQ_DM365_TCERRINT2 61
242#define IRQ_DM365_TCERRINT3 62
243#define IRQ_DM365_EMUINT 63
244
245/* DA8XX interrupts */
246#define IRQ_DA8XX_COMMTX 0
247#define IRQ_DA8XX_COMMRX 1
248#define IRQ_DA8XX_NINT 2
249#define IRQ_DA8XX_EVTOUT0 3
250#define IRQ_DA8XX_EVTOUT1 4
251#define IRQ_DA8XX_EVTOUT2 5
252#define IRQ_DA8XX_EVTOUT3 6
253#define IRQ_DA8XX_EVTOUT4 7
254#define IRQ_DA8XX_EVTOUT5 8
255#define IRQ_DA8XX_EVTOUT6 9
256#define IRQ_DA8XX_EVTOUT7 10
257#define IRQ_DA8XX_CCINT0 11
258#define IRQ_DA8XX_CCERRINT 12
259#define IRQ_DA8XX_TCERRINT0 13
260#define IRQ_DA8XX_AEMIFINT 14
261#define IRQ_DA8XX_I2CINT0 15
262#define IRQ_DA8XX_MMCSDINT0 16
263#define IRQ_DA8XX_MMCSDINT1 17
264#define IRQ_DA8XX_ALLINT0 18
265#define IRQ_DA8XX_RTC 19
266#define IRQ_DA8XX_SPINT0 20
267#define IRQ_DA8XX_TINT12_0 21
268#define IRQ_DA8XX_TINT34_0 22
269#define IRQ_DA8XX_TINT12_1 23
270#define IRQ_DA8XX_TINT34_1 24
271#define IRQ_DA8XX_UARTINT0 25
272#define IRQ_DA8XX_KEYMGRINT 26
273#define IRQ_DA8XX_SECINT 26
274#define IRQ_DA8XX_SECKEYERR 26
275#define IRQ_DA8XX_CHIPINT0 28
276#define IRQ_DA8XX_CHIPINT1 29
277#define IRQ_DA8XX_CHIPINT2 30
278#define IRQ_DA8XX_CHIPINT3 31
279#define IRQ_DA8XX_TCERRINT1 32
280#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33
281#define IRQ_DA8XX_C0_RX_PULSE 34
282#define IRQ_DA8XX_C0_TX_PULSE 35
283#define IRQ_DA8XX_C0_MISC_PULSE 36
284#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37
285#define IRQ_DA8XX_C1_RX_PULSE 38
286#define IRQ_DA8XX_C1_TX_PULSE 39
287#define IRQ_DA8XX_C1_MISC_PULSE 40
288#define IRQ_DA8XX_MEMERR 41
289#define IRQ_DA8XX_GPIO0 42
290#define IRQ_DA8XX_GPIO1 43
291#define IRQ_DA8XX_GPIO2 44
292#define IRQ_DA8XX_GPIO3 45
293#define IRQ_DA8XX_GPIO4 46
294#define IRQ_DA8XX_GPIO5 47
295#define IRQ_DA8XX_GPIO6 48
296#define IRQ_DA8XX_GPIO7 49
297#define IRQ_DA8XX_GPIO8 50
298#define IRQ_DA8XX_I2CINT1 51
299#define IRQ_DA8XX_LCDINT 52
300#define IRQ_DA8XX_UARTINT1 53
301#define IRQ_DA8XX_MCASPINT 54
302#define IRQ_DA8XX_ALLINT1 55
303#define IRQ_DA8XX_SPINT1 56
304#define IRQ_DA8XX_UHPI_INT1 57
305#define IRQ_DA8XX_USB_INT 58
306#define IRQ_DA8XX_IRQN 59
307#define IRQ_DA8XX_RWAKEUP 60
308#define IRQ_DA8XX_UARTINT2 61
309#define IRQ_DA8XX_DFTSSINT 62
310#define IRQ_DA8XX_EHRPWM0 63
311#define IRQ_DA8XX_EHRPWM0TZ 64
312#define IRQ_DA8XX_EHRPWM1 65
313#define IRQ_DA8XX_EHRPWM1TZ 66
314#define IRQ_DA8XX_ECAP0 69
315#define IRQ_DA8XX_ECAP1 70
316#define IRQ_DA8XX_ECAP2 71
317#define IRQ_DA8XX_ARMCLKSTOPREQ 90
318
319/* DA830 specific interrupts */
320#define IRQ_DA830_MPUERR 27
321#define IRQ_DA830_IOPUERR 27
322#define IRQ_DA830_BOOTCFGERR 27
323#define IRQ_DA830_EHRPWM2 67
324#define IRQ_DA830_EHRPWM2TZ 68
325#define IRQ_DA830_EQEP0 72
326#define IRQ_DA830_EQEP1 73
327#define IRQ_DA830_T12CMPINT0_0 74
328#define IRQ_DA830_T12CMPINT1_0 75
329#define IRQ_DA830_T12CMPINT2_0 76
330#define IRQ_DA830_T12CMPINT3_0 77
331#define IRQ_DA830_T12CMPINT4_0 78
332#define IRQ_DA830_T12CMPINT5_0 79
333#define IRQ_DA830_T12CMPINT6_0 80
334#define IRQ_DA830_T12CMPINT7_0 81
335#define IRQ_DA830_T12CMPINT0_1 82
336#define IRQ_DA830_T12CMPINT1_1 83
337#define IRQ_DA830_T12CMPINT2_1 84
338#define IRQ_DA830_T12CMPINT3_1 85
339#define IRQ_DA830_T12CMPINT4_1 86
340#define IRQ_DA830_T12CMPINT5_1 87
341#define IRQ_DA830_T12CMPINT6_1 88
342#define IRQ_DA830_T12CMPINT7_1 89
343
344#define DA830_N_CP_INTC_IRQ 96
345
346/* DA850 speicific interrupts */
347#define IRQ_DA850_MPUADDRERR0 27
348#define IRQ_DA850_MPUPROTERR0 27
349#define IRQ_DA850_IOPUADDRERR0 27
350#define IRQ_DA850_IOPUPROTERR0 27
351#define IRQ_DA850_IOPUADDRERR1 27
352#define IRQ_DA850_IOPUPROTERR1 27
353#define IRQ_DA850_IOPUADDRERR2 27
354#define IRQ_DA850_IOPUPROTERR2 27
355#define IRQ_DA850_BOOTCFG_ADDR_ERR 27
356#define IRQ_DA850_BOOTCFG_PROT_ERR 27
357#define IRQ_DA850_MPUADDRERR1 27
358#define IRQ_DA850_MPUPROTERR1 27
359#define IRQ_DA850_IOPUADDRERR3 27
360#define IRQ_DA850_IOPUPROTERR3 27
361#define IRQ_DA850_IOPUADDRERR4 27
362#define IRQ_DA850_IOPUPROTERR4 27
363#define IRQ_DA850_IOPUADDRERR5 27
364#define IRQ_DA850_IOPUPROTERR5 27
365#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27
366#define IRQ_DA850_SATAINT 67
367#define IRQ_DA850_TINT12_2 68
368#define IRQ_DA850_TINT34_2 68
369#define IRQ_DA850_TINTALL_2 68
370#define IRQ_DA850_MMCSDINT0_1 72
371#define IRQ_DA850_MMCSDINT1_1 73
372#define IRQ_DA850_T12CMPINT0_2 74
373#define IRQ_DA850_T12CMPINT1_2 75
374#define IRQ_DA850_T12CMPINT2_2 76
375#define IRQ_DA850_T12CMPINT3_2 77
376#define IRQ_DA850_T12CMPINT4_2 78
377#define IRQ_DA850_T12CMPINT5_2 79
378#define IRQ_DA850_T12CMPINT6_2 80
379#define IRQ_DA850_T12CMPINT7_2 81
380#define IRQ_DA850_T12CMPINT0_3 82
381#define IRQ_DA850_T12CMPINT1_3 83
382#define IRQ_DA850_T12CMPINT2_3 84
383#define IRQ_DA850_T12CMPINT3_3 85
384#define IRQ_DA850_T12CMPINT4_3 86
385#define IRQ_DA850_T12CMPINT5_3 87
386#define IRQ_DA850_T12CMPINT6_3 88
387#define IRQ_DA850_T12CMPINT7_3 89
388#define IRQ_DA850_RPIINT 91
389#define IRQ_DA850_VPIFINT 92
390#define IRQ_DA850_CCINT1 93
391#define IRQ_DA850_CCERRINT1 94
392#define IRQ_DA850_TCERRINT2 95
393#define IRQ_DA850_TINT12_3 96
394#define IRQ_DA850_TINT34_3 96
395#define IRQ_DA850_TINTALL_3 96
396#define IRQ_DA850_MCBSP0RINT 97
397#define IRQ_DA850_MCBSP0XINT 98
398#define IRQ_DA850_MCBSP1RINT 99
399#define IRQ_DA850_MCBSP1XINT 100
400
401#define DA850_N_CP_INTC_IRQ 101
402
403/* da850 currently has the most gpio pins (144) */
404#define DAVINCI_N_GPIO 144
405/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
406#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
407
209#endif /* __ASM_ARCH_IRQS_H */ 408#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index c712c7cdf38f..80309aed534a 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -20,9 +20,16 @@
20/************************************************************************** 20/**************************************************************************
21 * Definitions 21 * Definitions
22 **************************************************************************/ 22 **************************************************************************/
23#define DAVINCI_DDR_BASE 0x80000000 23#define DAVINCI_DDR_BASE 0x80000000
24#define DA8XX_DDR_BASE 0xc0000000
24 25
26#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
27#error Cannot enable DaVinci and DA8XX platforms concurrently
28#elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
29#define PHYS_OFFSET DA8XX_DDR_BASE
30#else
25#define PHYS_OFFSET DAVINCI_DDR_BASE 31#define PHYS_OFFSET DAVINCI_DDR_BASE
32#endif
26 33
27/* 34/*
28 * Increase size of DMA-consistent memory region 35 * Increase size of DMA-consistent memory region
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 27378458542f..bb84893a4e83 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -154,6 +154,737 @@ enum davinci_dm355_index {
154 DM355_EVT8_ASP1_TX, 154 DM355_EVT8_ASP1_TX,
155 DM355_EVT9_ASP1_RX, 155 DM355_EVT9_ASP1_RX,
156 DM355_EVT26_MMC0_RX, 156 DM355_EVT26_MMC0_RX,
157
158 /* Video Out */
159 DM355_VOUT_FIELD,
160 DM355_VOUT_FIELD_G70,
161 DM355_VOUT_HVSYNC,
162 DM355_VOUT_COUTL_EN,
163 DM355_VOUT_COUTH_EN,
164
165 /* Video In Pin Mux */
166 DM355_VIN_PCLK,
167 DM355_VIN_CAM_WEN,
168 DM355_VIN_CAM_VD,
169 DM355_VIN_CAM_HD,
170 DM355_VIN_YIN_EN,
171 DM355_VIN_CINL_EN,
172 DM355_VIN_CINH_EN,
173};
174
175enum davinci_dm365_index {
176 /* MMC/SD 0 */
177 DM365_MMCSD0,
178
179 /* MMC/SD 1 */
180 DM365_SD1_CLK,
181 DM365_SD1_CMD,
182 DM365_SD1_DATA3,
183 DM365_SD1_DATA2,
184 DM365_SD1_DATA1,
185 DM365_SD1_DATA0,
186
187 /* I2C */
188 DM365_I2C_SDA,
189 DM365_I2C_SCL,
190
191 /* AEMIF */
192 DM365_AEMIF_AR,
193 DM365_AEMIF_A3,
194 DM365_AEMIF_A7,
195 DM365_AEMIF_D15_8,
196 DM365_AEMIF_CE0,
197
198 /* ASP0 function */
199 DM365_MCBSP0_BDX,
200 DM365_MCBSP0_X,
201 DM365_MCBSP0_BFSX,
202 DM365_MCBSP0_BDR,
203 DM365_MCBSP0_R,
204 DM365_MCBSP0_BFSR,
205
206 /* SPI0 */
207 DM365_SPI0_SCLK,
208 DM365_SPI0_SDI,
209 DM365_SPI0_SDO,
210 DM365_SPI0_SDENA0,
211 DM365_SPI0_SDENA1,
212
213 /* UART */
214 DM365_UART0_RXD,
215 DM365_UART0_TXD,
216 DM365_UART1_RXD,
217 DM365_UART1_TXD,
218 DM365_UART1_RTS,
219 DM365_UART1_CTS,
220
221 /* EMAC */
222 DM365_EMAC_TX_EN,
223 DM365_EMAC_TX_CLK,
224 DM365_EMAC_COL,
225 DM365_EMAC_TXD3,
226 DM365_EMAC_TXD2,
227 DM365_EMAC_TXD1,
228 DM365_EMAC_TXD0,
229 DM365_EMAC_RXD3,
230 DM365_EMAC_RXD2,
231 DM365_EMAC_RXD1,
232 DM365_EMAC_RXD0,
233 DM365_EMAC_RX_CLK,
234 DM365_EMAC_RX_DV,
235 DM365_EMAC_RX_ER,
236 DM365_EMAC_CRS,
237 DM365_EMAC_MDIO,
238 DM365_EMAC_MDCLK,
239
240 /* Keypad */
241 DM365_KEYPAD,
242
243 /* PWM */
244 DM365_PWM0,
245 DM365_PWM0_G23,
246 DM365_PWM1,
247 DM365_PWM1_G25,
248 DM365_PWM2_G87,
249 DM365_PWM2_G88,
250 DM365_PWM2_G89,
251 DM365_PWM2_G90,
252 DM365_PWM3_G80,
253 DM365_PWM3_G81,
254 DM365_PWM3_G85,
255 DM365_PWM3_G86,
256
257 /* SPI1 */
258 DM365_SPI1_SCLK,
259 DM365_SPI1_SDO,
260 DM365_SPI1_SDI,
261 DM365_SPI1_SDENA0,
262 DM365_SPI1_SDENA1,
263
264 /* SPI2 */
265 DM365_SPI2_SCLK,
266 DM365_SPI2_SDO,
267 DM365_SPI2_SDI,
268 DM365_SPI2_SDENA0,
269 DM365_SPI2_SDENA1,
270
271 /* SPI3 */
272 DM365_SPI3_SCLK,
273 DM365_SPI3_SDO,
274 DM365_SPI3_SDI,
275 DM365_SPI3_SDENA0,
276 DM365_SPI3_SDENA1,
277
278 /* SPI4 */
279 DM365_SPI4_SCLK,
280 DM365_SPI4_SDO,
281 DM365_SPI4_SDI,
282 DM365_SPI4_SDENA0,
283 DM365_SPI4_SDENA1,
284
285 /* GPIO */
286 DM365_GPIO20,
287 DM365_GPIO33,
288 DM365_GPIO40,
289
290 /* Video */
291 DM365_VOUT_FIELD,
292 DM365_VOUT_FIELD_G81,
293 DM365_VOUT_HVSYNC,
294 DM365_VOUT_COUTL_EN,
295 DM365_VOUT_COUTH_EN,
296 DM365_VIN_CAM_WEN,
297 DM365_VIN_CAM_VD,
298 DM365_VIN_CAM_HD,
299 DM365_VIN_YIN4_7_EN,
300 DM365_VIN_YIN0_3_EN,
301
302 /* IRQ muxing */
303 DM365_INT_EDMA_CC,
304 DM365_INT_EDMA_TC0_ERR,
305 DM365_INT_EDMA_TC1_ERR,
306 DM365_INT_EDMA_TC2_ERR,
307 DM365_INT_EDMA_TC3_ERR,
308 DM365_INT_PRTCSS,
309 DM365_INT_EMAC_RXTHRESH,
310 DM365_INT_EMAC_RXPULSE,
311 DM365_INT_EMAC_TXPULSE,
312 DM365_INT_EMAC_MISCPULSE,
313 DM365_INT_IMX0_ENABLE,
314 DM365_INT_IMX0_DISABLE,
315 DM365_INT_HDVICP_ENABLE,
316 DM365_INT_HDVICP_DISABLE,
317 DM365_INT_IMX1_ENABLE,
318 DM365_INT_IMX1_DISABLE,
319 DM365_INT_NSF_ENABLE,
320 DM365_INT_NSF_DISABLE,
321
322 /* EDMA event muxing */
323 DM365_EVT2_ASP_TX,
324 DM365_EVT3_ASP_RX,
325 DM365_EVT26_MMC0_RX,
326};
327
328enum da830_index {
329 DA830_GPIO7_14,
330 DA830_RTCK,
331 DA830_GPIO7_15,
332 DA830_EMU_0,
333 DA830_EMB_SDCKE,
334 DA830_EMB_CLK_GLUE,
335 DA830_EMB_CLK,
336 DA830_NEMB_CS_0,
337 DA830_NEMB_CAS,
338 DA830_NEMB_RAS,
339 DA830_NEMB_WE,
340 DA830_EMB_BA_1,
341 DA830_EMB_BA_0,
342 DA830_EMB_A_0,
343 DA830_EMB_A_1,
344 DA830_EMB_A_2,
345 DA830_EMB_A_3,
346 DA830_EMB_A_4,
347 DA830_EMB_A_5,
348 DA830_GPIO7_0,
349 DA830_GPIO7_1,
350 DA830_GPIO7_2,
351 DA830_GPIO7_3,
352 DA830_GPIO7_4,
353 DA830_GPIO7_5,
354 DA830_GPIO7_6,
355 DA830_GPIO7_7,
356 DA830_EMB_A_6,
357 DA830_EMB_A_7,
358 DA830_EMB_A_8,
359 DA830_EMB_A_9,
360 DA830_EMB_A_10,
361 DA830_EMB_A_11,
362 DA830_EMB_A_12,
363 DA830_EMB_D_31,
364 DA830_GPIO7_8,
365 DA830_GPIO7_9,
366 DA830_GPIO7_10,
367 DA830_GPIO7_11,
368 DA830_GPIO7_12,
369 DA830_GPIO7_13,
370 DA830_GPIO3_13,
371 DA830_EMB_D_30,
372 DA830_EMB_D_29,
373 DA830_EMB_D_28,
374 DA830_EMB_D_27,
375 DA830_EMB_D_26,
376 DA830_EMB_D_25,
377 DA830_EMB_D_24,
378 DA830_EMB_D_23,
379 DA830_EMB_D_22,
380 DA830_EMB_D_21,
381 DA830_EMB_D_20,
382 DA830_EMB_D_19,
383 DA830_EMB_D_18,
384 DA830_EMB_D_17,
385 DA830_EMB_D_16,
386 DA830_NEMB_WE_DQM_3,
387 DA830_NEMB_WE_DQM_2,
388 DA830_EMB_D_0,
389 DA830_EMB_D_1,
390 DA830_EMB_D_2,
391 DA830_EMB_D_3,
392 DA830_EMB_D_4,
393 DA830_EMB_D_5,
394 DA830_EMB_D_6,
395 DA830_GPIO6_0,
396 DA830_GPIO6_1,
397 DA830_GPIO6_2,
398 DA830_GPIO6_3,
399 DA830_GPIO6_4,
400 DA830_GPIO6_5,
401 DA830_GPIO6_6,
402 DA830_EMB_D_7,
403 DA830_EMB_D_8,
404 DA830_EMB_D_9,
405 DA830_EMB_D_10,
406 DA830_EMB_D_11,
407 DA830_EMB_D_12,
408 DA830_EMB_D_13,
409 DA830_EMB_D_14,
410 DA830_GPIO6_7,
411 DA830_GPIO6_8,
412 DA830_GPIO6_9,
413 DA830_GPIO6_10,
414 DA830_GPIO6_11,
415 DA830_GPIO6_12,
416 DA830_GPIO6_13,
417 DA830_GPIO6_14,
418 DA830_EMB_D_15,
419 DA830_NEMB_WE_DQM_1,
420 DA830_NEMB_WE_DQM_0,
421 DA830_SPI0_SOMI_0,
422 DA830_SPI0_SIMO_0,
423 DA830_SPI0_CLK,
424 DA830_NSPI0_ENA,
425 DA830_NSPI0_SCS_0,
426 DA830_EQEP0I,
427 DA830_EQEP0S,
428 DA830_EQEP1I,
429 DA830_NUART0_CTS,
430 DA830_NUART0_RTS,
431 DA830_EQEP0A,
432 DA830_EQEP0B,
433 DA830_GPIO6_15,
434 DA830_GPIO5_14,
435 DA830_GPIO5_15,
436 DA830_GPIO5_0,
437 DA830_GPIO5_1,
438 DA830_GPIO5_2,
439 DA830_GPIO5_3,
440 DA830_GPIO5_4,
441 DA830_SPI1_SOMI_0,
442 DA830_SPI1_SIMO_0,
443 DA830_SPI1_CLK,
444 DA830_UART0_RXD,
445 DA830_UART0_TXD,
446 DA830_AXR1_10,
447 DA830_AXR1_11,
448 DA830_NSPI1_ENA,
449 DA830_I2C1_SCL,
450 DA830_I2C1_SDA,
451 DA830_EQEP1S,
452 DA830_I2C0_SDA,
453 DA830_I2C0_SCL,
454 DA830_UART2_RXD,
455 DA830_TM64P0_IN12,
456 DA830_TM64P0_OUT12,
457 DA830_GPIO5_5,
458 DA830_GPIO5_6,
459 DA830_GPIO5_7,
460 DA830_GPIO5_8,
461 DA830_GPIO5_9,
462 DA830_GPIO5_10,
463 DA830_GPIO5_11,
464 DA830_GPIO5_12,
465 DA830_NSPI1_SCS_0,
466 DA830_USB0_DRVVBUS,
467 DA830_AHCLKX0,
468 DA830_ACLKX0,
469 DA830_AFSX0,
470 DA830_AHCLKR0,
471 DA830_ACLKR0,
472 DA830_AFSR0,
473 DA830_UART2_TXD,
474 DA830_AHCLKX2,
475 DA830_ECAP0_APWM0,
476 DA830_RMII_MHZ_50_CLK,
477 DA830_ECAP1_APWM1,
478 DA830_USB_REFCLKIN,
479 DA830_GPIO5_13,
480 DA830_GPIO4_15,
481 DA830_GPIO2_11,
482 DA830_GPIO2_12,
483 DA830_GPIO2_13,
484 DA830_GPIO2_14,
485 DA830_GPIO2_15,
486 DA830_GPIO3_12,
487 DA830_AMUTE0,
488 DA830_AXR0_0,
489 DA830_AXR0_1,
490 DA830_AXR0_2,
491 DA830_AXR0_3,
492 DA830_AXR0_4,
493 DA830_AXR0_5,
494 DA830_AXR0_6,
495 DA830_RMII_TXD_0,
496 DA830_RMII_TXD_1,
497 DA830_RMII_TXEN,
498 DA830_RMII_CRS_DV,
499 DA830_RMII_RXD_0,
500 DA830_RMII_RXD_1,
501 DA830_RMII_RXER,
502 DA830_AFSR2,
503 DA830_ACLKX2,
504 DA830_AXR2_3,
505 DA830_AXR2_2,
506 DA830_AXR2_1,
507 DA830_AFSX2,
508 DA830_ACLKR2,
509 DA830_NRESETOUT,
510 DA830_GPIO3_0,
511 DA830_GPIO3_1,
512 DA830_GPIO3_2,
513 DA830_GPIO3_3,
514 DA830_GPIO3_4,
515 DA830_GPIO3_5,
516 DA830_GPIO3_6,
517 DA830_AXR0_7,
518 DA830_AXR0_8,
519 DA830_UART1_RXD,
520 DA830_UART1_TXD,
521 DA830_AXR0_11,
522 DA830_AHCLKX1,
523 DA830_ACLKX1,
524 DA830_AFSX1,
525 DA830_MDIO_CLK,
526 DA830_MDIO_D,
527 DA830_AXR0_9,
528 DA830_AXR0_10,
529 DA830_EPWM0B,
530 DA830_EPWM0A,
531 DA830_EPWMSYNCI,
532 DA830_AXR2_0,
533 DA830_EPWMSYNC0,
534 DA830_GPIO3_7,
535 DA830_GPIO3_8,
536 DA830_GPIO3_9,
537 DA830_GPIO3_10,
538 DA830_GPIO3_11,
539 DA830_GPIO3_14,
540 DA830_GPIO3_15,
541 DA830_GPIO4_10,
542 DA830_AHCLKR1,
543 DA830_ACLKR1,
544 DA830_AFSR1,
545 DA830_AMUTE1,
546 DA830_AXR1_0,
547 DA830_AXR1_1,
548 DA830_AXR1_2,
549 DA830_AXR1_3,
550 DA830_ECAP2_APWM2,
551 DA830_EHRPWMGLUETZ,
552 DA830_EQEP1A,
553 DA830_GPIO4_11,
554 DA830_GPIO4_12,
555 DA830_GPIO4_13,
556 DA830_GPIO4_14,
557 DA830_GPIO4_0,
558 DA830_GPIO4_1,
559 DA830_GPIO4_2,
560 DA830_GPIO4_3,
561 DA830_AXR1_4,
562 DA830_AXR1_5,
563 DA830_AXR1_6,
564 DA830_AXR1_7,
565 DA830_AXR1_8,
566 DA830_AXR1_9,
567 DA830_EMA_D_0,
568 DA830_EMA_D_1,
569 DA830_EQEP1B,
570 DA830_EPWM2B,
571 DA830_EPWM2A,
572 DA830_EPWM1B,
573 DA830_EPWM1A,
574 DA830_MMCSD_DAT_0,
575 DA830_MMCSD_DAT_1,
576 DA830_UHPI_HD_0,
577 DA830_UHPI_HD_1,
578 DA830_GPIO4_4,
579 DA830_GPIO4_5,
580 DA830_GPIO4_6,
581 DA830_GPIO4_7,
582 DA830_GPIO4_8,
583 DA830_GPIO4_9,
584 DA830_GPIO0_0,
585 DA830_GPIO0_1,
586 DA830_EMA_D_2,
587 DA830_EMA_D_3,
588 DA830_EMA_D_4,
589 DA830_EMA_D_5,
590 DA830_EMA_D_6,
591 DA830_EMA_D_7,
592 DA830_EMA_D_8,
593 DA830_EMA_D_9,
594 DA830_MMCSD_DAT_2,
595 DA830_MMCSD_DAT_3,
596 DA830_MMCSD_DAT_4,
597 DA830_MMCSD_DAT_5,
598 DA830_MMCSD_DAT_6,
599 DA830_MMCSD_DAT_7,
600 DA830_UHPI_HD_8,
601 DA830_UHPI_HD_9,
602 DA830_UHPI_HD_2,
603 DA830_UHPI_HD_3,
604 DA830_UHPI_HD_4,
605 DA830_UHPI_HD_5,
606 DA830_UHPI_HD_6,
607 DA830_UHPI_HD_7,
608 DA830_LCD_D_8,
609 DA830_LCD_D_9,
610 DA830_GPIO0_2,
611 DA830_GPIO0_3,
612 DA830_GPIO0_4,
613 DA830_GPIO0_5,
614 DA830_GPIO0_6,
615 DA830_GPIO0_7,
616 DA830_GPIO0_8,
617 DA830_GPIO0_9,
618 DA830_EMA_D_10,
619 DA830_EMA_D_11,
620 DA830_EMA_D_12,
621 DA830_EMA_D_13,
622 DA830_EMA_D_14,
623 DA830_EMA_D_15,
624 DA830_EMA_A_0,
625 DA830_EMA_A_1,
626 DA830_UHPI_HD_10,
627 DA830_UHPI_HD_11,
628 DA830_UHPI_HD_12,
629 DA830_UHPI_HD_13,
630 DA830_UHPI_HD_14,
631 DA830_UHPI_HD_15,
632 DA830_LCD_D_7,
633 DA830_MMCSD_CLK,
634 DA830_LCD_D_10,
635 DA830_LCD_D_11,
636 DA830_LCD_D_12,
637 DA830_LCD_D_13,
638 DA830_LCD_D_14,
639 DA830_LCD_D_15,
640 DA830_UHPI_HCNTL0,
641 DA830_GPIO0_10,
642 DA830_GPIO0_11,
643 DA830_GPIO0_12,
644 DA830_GPIO0_13,
645 DA830_GPIO0_14,
646 DA830_GPIO0_15,
647 DA830_GPIO1_0,
648 DA830_GPIO1_1,
649 DA830_EMA_A_2,
650 DA830_EMA_A_3,
651 DA830_EMA_A_4,
652 DA830_EMA_A_5,
653 DA830_EMA_A_6,
654 DA830_EMA_A_7,
655 DA830_EMA_A_8,
656 DA830_EMA_A_9,
657 DA830_MMCSD_CMD,
658 DA830_LCD_D_6,
659 DA830_LCD_D_3,
660 DA830_LCD_D_2,
661 DA830_LCD_D_1,
662 DA830_LCD_D_0,
663 DA830_LCD_PCLK,
664 DA830_LCD_HSYNC,
665 DA830_UHPI_HCNTL1,
666 DA830_GPIO1_2,
667 DA830_GPIO1_3,
668 DA830_GPIO1_4,
669 DA830_GPIO1_5,
670 DA830_GPIO1_6,
671 DA830_GPIO1_7,
672 DA830_GPIO1_8,
673 DA830_GPIO1_9,
674 DA830_EMA_A_10,
675 DA830_EMA_A_11,
676 DA830_EMA_A_12,
677 DA830_EMA_BA_1,
678 DA830_EMA_BA_0,
679 DA830_EMA_CLK,
680 DA830_EMA_SDCKE,
681 DA830_NEMA_CAS,
682 DA830_LCD_VSYNC,
683 DA830_NLCD_AC_ENB_CS,
684 DA830_LCD_MCLK,
685 DA830_LCD_D_5,
686 DA830_LCD_D_4,
687 DA830_OBSCLK,
688 DA830_NEMA_CS_4,
689 DA830_UHPI_HHWIL,
690 DA830_AHCLKR2,
691 DA830_GPIO1_10,
692 DA830_GPIO1_11,
693 DA830_GPIO1_12,
694 DA830_GPIO1_13,
695 DA830_GPIO1_14,
696 DA830_GPIO1_15,
697 DA830_GPIO2_0,
698 DA830_GPIO2_1,
699 DA830_NEMA_RAS,
700 DA830_NEMA_WE,
701 DA830_NEMA_CS_0,
702 DA830_NEMA_CS_2,
703 DA830_NEMA_CS_3,
704 DA830_NEMA_OE,
705 DA830_NEMA_WE_DQM_1,
706 DA830_NEMA_WE_DQM_0,
707 DA830_NEMA_CS_5,
708 DA830_UHPI_HRNW,
709 DA830_NUHPI_HAS,
710 DA830_NUHPI_HCS,
711 DA830_NUHPI_HDS1,
712 DA830_NUHPI_HDS2,
713 DA830_NUHPI_HINT,
714 DA830_AXR0_12,
715 DA830_AMUTE2,
716 DA830_AXR0_13,
717 DA830_AXR0_14,
718 DA830_AXR0_15,
719 DA830_GPIO2_2,
720 DA830_GPIO2_3,
721 DA830_GPIO2_4,
722 DA830_GPIO2_5,
723 DA830_GPIO2_6,
724 DA830_GPIO2_7,
725 DA830_GPIO2_8,
726 DA830_GPIO2_9,
727 DA830_EMA_WAIT_0,
728 DA830_NUHPI_HRDY,
729 DA830_GPIO2_10,
730};
731
732enum davinci_da850_index {
733 /* UART0 function */
734 DA850_NUART0_CTS,
735 DA850_NUART0_RTS,
736 DA850_UART0_RXD,
737 DA850_UART0_TXD,
738
739 /* UART1 function */
740 DA850_NUART1_CTS,
741 DA850_NUART1_RTS,
742 DA850_UART1_RXD,
743 DA850_UART1_TXD,
744
745 /* UART2 function */
746 DA850_NUART2_CTS,
747 DA850_NUART2_RTS,
748 DA850_UART2_RXD,
749 DA850_UART2_TXD,
750
751 /* I2C1 function */
752 DA850_I2C1_SCL,
753 DA850_I2C1_SDA,
754
755 /* I2C0 function */
756 DA850_I2C0_SDA,
757 DA850_I2C0_SCL,
758
759 /* EMAC function */
760 DA850_MII_TXEN,
761 DA850_MII_TXCLK,
762 DA850_MII_COL,
763 DA850_MII_TXD_3,
764 DA850_MII_TXD_2,
765 DA850_MII_TXD_1,
766 DA850_MII_TXD_0,
767 DA850_MII_RXER,
768 DA850_MII_CRS,
769 DA850_MII_RXCLK,
770 DA850_MII_RXDV,
771 DA850_MII_RXD_3,
772 DA850_MII_RXD_2,
773 DA850_MII_RXD_1,
774 DA850_MII_RXD_0,
775 DA850_MDIO_CLK,
776 DA850_MDIO_D,
777
778 /* McASP function */
779 DA850_ACLKR,
780 DA850_ACLKX,
781 DA850_AFSR,
782 DA850_AFSX,
783 DA850_AHCLKR,
784 DA850_AHCLKX,
785 DA850_AMUTE,
786 DA850_AXR_15,
787 DA850_AXR_14,
788 DA850_AXR_13,
789 DA850_AXR_12,
790 DA850_AXR_11,
791 DA850_AXR_10,
792 DA850_AXR_9,
793 DA850_AXR_8,
794 DA850_AXR_7,
795 DA850_AXR_6,
796 DA850_AXR_5,
797 DA850_AXR_4,
798 DA850_AXR_3,
799 DA850_AXR_2,
800 DA850_AXR_1,
801 DA850_AXR_0,
802
803 /* LCD function */
804 DA850_LCD_D_7,
805 DA850_LCD_D_6,
806 DA850_LCD_D_5,
807 DA850_LCD_D_4,
808 DA850_LCD_D_3,
809 DA850_LCD_D_2,
810 DA850_LCD_D_1,
811 DA850_LCD_D_0,
812 DA850_LCD_D_15,
813 DA850_LCD_D_14,
814 DA850_LCD_D_13,
815 DA850_LCD_D_12,
816 DA850_LCD_D_11,
817 DA850_LCD_D_10,
818 DA850_LCD_D_9,
819 DA850_LCD_D_8,
820 DA850_LCD_PCLK,
821 DA850_LCD_HSYNC,
822 DA850_LCD_VSYNC,
823 DA850_NLCD_AC_ENB_CS,
824
825 /* MMC/SD0 function */
826 DA850_MMCSD0_DAT_0,
827 DA850_MMCSD0_DAT_1,
828 DA850_MMCSD0_DAT_2,
829 DA850_MMCSD0_DAT_3,
830 DA850_MMCSD0_CLK,
831 DA850_MMCSD0_CMD,
832
833 /* EMIF2.5/EMIFA function */
834 DA850_EMA_D_7,
835 DA850_EMA_D_6,
836 DA850_EMA_D_5,
837 DA850_EMA_D_4,
838 DA850_EMA_D_3,
839 DA850_EMA_D_2,
840 DA850_EMA_D_1,
841 DA850_EMA_D_0,
842 DA850_EMA_A_1,
843 DA850_EMA_A_2,
844 DA850_NEMA_CS_3,
845 DA850_NEMA_CS_4,
846 DA850_NEMA_WE,
847 DA850_NEMA_OE,
848 DA850_EMA_D_15,
849 DA850_EMA_D_14,
850 DA850_EMA_D_13,
851 DA850_EMA_D_12,
852 DA850_EMA_D_11,
853 DA850_EMA_D_10,
854 DA850_EMA_D_9,
855 DA850_EMA_D_8,
856 DA850_EMA_A_0,
857 DA850_EMA_A_3,
858 DA850_EMA_A_4,
859 DA850_EMA_A_5,
860 DA850_EMA_A_6,
861 DA850_EMA_A_7,
862 DA850_EMA_A_8,
863 DA850_EMA_A_9,
864 DA850_EMA_A_10,
865 DA850_EMA_A_11,
866 DA850_EMA_A_12,
867 DA850_EMA_A_13,
868 DA850_EMA_A_14,
869 DA850_EMA_A_15,
870 DA850_EMA_A_16,
871 DA850_EMA_A_17,
872 DA850_EMA_A_18,
873 DA850_EMA_A_19,
874 DA850_EMA_A_20,
875 DA850_EMA_A_21,
876 DA850_EMA_A_22,
877 DA850_EMA_A_23,
878 DA850_EMA_BA_1,
879 DA850_EMA_CLK,
880 DA850_EMA_WAIT_1,
881 DA850_NEMA_CS_2,
882
883 /* GPIO function */
884 DA850_GPIO2_15,
885 DA850_GPIO8_10,
886 DA850_GPIO4_0,
887 DA850_GPIO4_1,
157}; 888};
158 889
159#ifdef CONFIG_DAVINCI_MUX 890#ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index ab8a2586d1cc..171173c1dbad 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -81,6 +81,24 @@
81#define DM355_LPSC_RTO 12 81#define DM355_LPSC_RTO 12
82#define DM355_LPSC_VPSS_DAC 41 82#define DM355_LPSC_VPSS_DAC 41
83 83
84/* DM365 */
85#define DM365_LPSC_TIMER3 5
86#define DM365_LPSC_SPI1 6
87#define DM365_LPSC_MMC_SD1 7
88#define DM365_LPSC_McBSP1 8
89#define DM365_LPSC_PWM3 10
90#define DM365_LPSC_SPI2 11
91#define DM365_LPSC_RTO 12
92#define DM365_LPSC_TIMER4 17
93#define DM365_LPSC_SPI0 22
94#define DM365_LPSC_SPI3 38
95#define DM365_LPSC_SPI4 39
96#define DM365_LPSC_EMAC 40
97#define DM365_LPSC_VOICE_CODEC 44
98#define DM365_LPSC_DAC_CLK 46
99#define DM365_LPSC_VPSSMSTR 47
100#define DM365_LPSC_MJCP 50
101
84/* 102/*
85 * LPSC Assignments 103 * LPSC Assignments
86 */ 104 */
@@ -118,6 +136,50 @@
118#define DM646X_LPSC_TIMER1 35 136#define DM646X_LPSC_TIMER1 35
119#define DM646X_LPSC_ARM_INTC 45 137#define DM646X_LPSC_ARM_INTC 45
120 138
139/* PSC0 defines */
140#define DA8XX_LPSC0_TPCC 0
141#define DA8XX_LPSC0_TPTC0 1
142#define DA8XX_LPSC0_TPTC1 2
143#define DA8XX_LPSC0_EMIF25 3
144#define DA8XX_LPSC0_SPI0 4
145#define DA8XX_LPSC0_MMC_SD 5
146#define DA8XX_LPSC0_AINTC 6
147#define DA8XX_LPSC0_ARM_RAM_ROM 7
148#define DA8XX_LPSC0_SECU_MGR 8
149#define DA8XX_LPSC0_UART0 9
150#define DA8XX_LPSC0_SCR0_SS 10
151#define DA8XX_LPSC0_SCR1_SS 11
152#define DA8XX_LPSC0_SCR2_SS 12
153#define DA8XX_LPSC0_DMAX 13
154#define DA8XX_LPSC0_ARM 14
155#define DA8XX_LPSC0_GEM 15
156
157/* PSC1 defines */
158#define DA850_LPSC1_TPCC1 0
159#define DA8XX_LPSC1_USB20 1
160#define DA8XX_LPSC1_USB11 2
161#define DA8XX_LPSC1_GPIO 3
162#define DA8XX_LPSC1_UHPI 4
163#define DA8XX_LPSC1_CPGMAC 5
164#define DA8XX_LPSC1_EMIF3C 6
165#define DA8XX_LPSC1_McASP0 7
166#define DA830_LPSC1_McASP1 8
167#define DA850_LPSC1_SATA 8
168#define DA830_LPSC1_McASP2 9
169#define DA8XX_LPSC1_SPI1 10
170#define DA8XX_LPSC1_I2C 11
171#define DA8XX_LPSC1_UART1 12
172#define DA8XX_LPSC1_UART2 13
173#define DA8XX_LPSC1_LCDC 16
174#define DA8XX_LPSC1_PWM 17
175#define DA8XX_LPSC1_ECAP 20
176#define DA830_LPSC1_EQEP 21
177#define DA850_LPSC1_TPTC2 21
178#define DA8XX_LPSC1_SCR_P0_SS 24
179#define DA8XX_LPSC1_SCR_P1_SS 25
180#define DA8XX_LPSC1_CR_P3_SS 26
181#define DA8XX_LPSC1_L3_CBA_RAM 31
182
121extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 183extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
122extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 184extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
123 unsigned int id, char enable); 185 unsigned int id, char enable);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 794fa5cf93c1..a584697a9e70 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,13 +11,17 @@
11#ifndef __ASM_ARCH_SERIAL_H 11#ifndef __ASM_ARCH_SERIAL_H
12#define __ASM_ARCH_SERIAL_H 12#define __ASM_ARCH_SERIAL_H
13 13
14#include <mach/io.h> 14#include <mach/hardware.h>
15 15
16#define DAVINCI_MAX_NR_UARTS 3 16#define DAVINCI_MAX_NR_UARTS 3
17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 17#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20 20
21#define DA8XX_UART0_BASE (IO_PHYS + 0x042000)
22#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
23#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
24
21/* DaVinci UART register offsets */ 25/* DaVinci UART register offsets */
22#define UART_DAVINCI_PWREMU 0x0c 26#define UART_DAVINCI_PWREMU 0x0c
23#define UART_DM646X_SCR 0x10 27#define UART_DM646X_SCR 0x10
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index b7e7036674fa..8e4f10fe1263 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -16,12 +16,12 @@
16 16
17extern void davinci_watchdog_reset(void); 17extern void davinci_watchdog_reset(void);
18 18
19static void arch_idle(void) 19static inline void arch_idle(void)
20{ 20{
21 cpu_do_idle(); 21 cpu_do_idle();
22} 22}
23 23
24static void arch_reset(char mode, const char *cmd) 24static inline void arch_reset(char mode, const char *cmd)
25{ 25{
26 davinci_watchdog_reset(); 26 davinci_watchdog_reset();
27} 27}
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 1e27475f9a23..33796b4db17f 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -21,8 +21,11 @@ static u32 *uart;
21 21
22static u32 *get_uart_base(void) 22static u32 *get_uart_base(void)
23{ 23{
24 /* Add logic here for new platforms, using __macine_arch_type */ 24 if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
25 return (u32 *)DAVINCI_UART0_BASE; 25 __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
26 return (u32 *)DA8XX_UART2_BASE;
27 else
28 return (u32 *)DAVINCI_UART0_BASE;
26} 29}
27 30
28/* PORT_16C550A, in polled non-fifo mode */ 31/* PORT_16C550A, in polled non-fifo mode */
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
index ad51625b6609..d49646a8e206 100644
--- a/arch/arm/mach-davinci/include/mach/vmalloc.h
+++ b/arch/arm/mach-davinci/include/mach/vmalloc.h
@@ -8,7 +8,7 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <mach/io.h> 11#include <mach/hardware.h>
12 12
13/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ 13/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
14#define VMALLOC_END (IO_VIRT - (2<<20)) 14#define VMALLOC_END (IO_VIRT - (2<<20))
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 03:13:54 -0500