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-rw-r--r--Documentation/devicetree/bindings/arm/bcm/bcm11351.txt9
-rw-r--r--Documentation/devicetree/bindings/arm/calxeda.txt13
-rw-r--r--Documentation/devicetree/bindings/arm/vexpress-sysreg.txt50
-rw-r--r--Documentation/devicetree/bindings/arm/vexpress.txt98
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt191
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt9
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt104
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt119
-rw-r--r--Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt17
-rw-r--r--Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt13
-rw-r--r--Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt13
11 files changed, 596 insertions, 40 deletions
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
new file mode 100644
index 000000000000..fb7b5cd2652f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
@@ -0,0 +1,9 @@
1Broadcom BCM11351 device tree bindings
2-------------------------------------------
3
4Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
5bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
6
7Required root node property:
8
9compatible = "bcm,bcm11351";
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
index 4755caaccba6..25fcf96795ca 100644
--- a/Documentation/devicetree/bindings/arm/calxeda.txt
+++ b/Documentation/devicetree/bindings/arm/calxeda.txt
@@ -1,8 +1,15 @@
1Calxeda Highbank Platforms Device Tree Bindings 1Calxeda Platforms Device Tree Bindings
2----------------------------------------------- 2-----------------------------------------------
3 3
4Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following 4Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
5properties. 5following properties.
6 6
7Required root node properties: 7Required root node properties:
8 - compatible = "calxeda,highbank"; 8 - compatible = "calxeda,highbank";
9
10
11Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
12properties.
13
14Required root node properties:
15 - compatible = "calxeda,ecx-2000";
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
new file mode 100644
index 000000000000..9cf3f25544c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
@@ -0,0 +1,50 @@
1ARM Versatile Express system registers
2--------------------------------------
3
4This is a system control registers block, providing multiple low level
5platform functions like board detection and identification, software
6interrupt generation, MMC and NOR Flash control etc.
7
8Required node properties:
9- compatible value : = "arm,vexpress,sysreg";
10- reg : physical base address and the size of the registers window
11- gpio-controller : specifies that the node is a GPIO controller
12- #gpio-cells : size of the GPIO specifier, should be 2:
13 - first cell is the pseudo-GPIO line number:
14 0 - MMC CARDIN
15 1 - MMC WPROT
16 2 - NOR FLASH WPn
17 - second cell can take standard GPIO flags (currently ignored).
18
19Example:
20 v2m_sysreg: sysreg@10000000 {
21 compatible = "arm,vexpress-sysreg";
22 reg = <0x10000000 0x1000>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 };
26
27This block also can also act a bridge to the platform's configuration
28bus via "system control" interface, addressing devices with site number,
29position in the board stack, config controller, function and device
30numbers - see motherboard's TRM for more details.
31
32The node describing a config device must refer to the sysreg node via
33"arm,vexpress,config-bridge" phandle (can be also defined in the node's
34parent) and relies on the board topology properties - see main vexpress
35node documentation for more details. It must must also define the
36following property:
37- arm,vexpress-sysreg,func : must contain two cells:
38 - first cell defines function number (eg. 1 for clock generator,
39 2 for voltage regulators etc.)
40 - device number (eg. osc 0, osc 1 etc.)
41
42Example:
43 mcc {
44 arm,vexpress,config-bridge = <&v2m_sysreg>;
45
46 osc@0 {
47 compatible = "arm,vexpress-osc";
48 arm,vexpress-sysreg,func = <1 0>;
49 };
50 };
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
index ec8b50cbb2e8..ae49161e478a 100644
--- a/Documentation/devicetree/bindings/arm/vexpress.txt
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -11,6 +11,10 @@ the motherboard file using a /include/ directive. As the motherboard
11can be initialized in one of two different configurations ("memory 11can be initialized in one of two different configurations ("memory
12maps"), care must be taken to include the correct one. 12maps"), care must be taken to include the correct one.
13 13
14
15Root node
16---------
17
14Required properties in the root node: 18Required properties in the root node:
15- compatible value: 19- compatible value:
16 compatible = "arm,vexpress,<model>", "arm,vexpress"; 20 compatible = "arm,vexpress,<model>", "arm,vexpress";
@@ -45,6 +49,10 @@ Optional properties in the root node:
45 - Coretile Express A9x4 (V2P-CA9) HBI-0225: 49 - Coretile Express A9x4 (V2P-CA9) HBI-0225:
46 arm,hbi = <0x225>; 50 arm,hbi = <0x225>;
47 51
52
53CPU nodes
54---------
55
48Top-level standard "cpus" node is required. It must contain a node 56Top-level standard "cpus" node is required. It must contain a node
49with device_type = "cpu" property for every available core, eg.: 57with device_type = "cpu" property for every available core, eg.:
50 58
@@ -59,6 +67,52 @@ with device_type = "cpu" property for every available core, eg.:
59 }; 67 };
60 }; 68 };
61 69
70
71Configuration infrastructure
72----------------------------
73
74The platform has an elaborated configuration system, consisting of
75microcontrollers residing on the mother- and daughterboards known
76as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
77The controllers are responsible for the platform initialization
78(reset generation, flash programming, FPGA bitfiles loading etc.)
79but also control clock generators, voltage regulators, gather
80environmental data like temperature, power consumption etc. Even
81the video output switch (FPGA) is controlled that way.
82
83Nodes describing devices controlled by this infrastructure should
84point at the bridge device node:
85- bridge phandle:
86 arm,vexpress,config-bridge = <phandle>;
87This property can be also defined in a parent node (eg. for a DCC)
88and is effective for all children.
89
90
91Platform topology
92-----------------
93
94As Versatile Express can be configured in number of physically
95different setups, the device tree should describe platform topology.
96Root node and main motherboard node must define the following
97property, describing physical location of the children nodes:
98- site number:
99 arm,vexpress,site = <number>;
100 where 0 means motherboard, 1 or 2 are daugtherboard sites,
101 0xf means "master" site (site containing main CPU tile)
102- when daughterboards are stacked on one site, their position
103 in the stack be be described with:
104 arm,vexpress,position = <number>;
105- when describing tiles consisting more than one DCC, its number
106 can be described with:
107 arm,vexpress,dcc = <number>;
108
109Any of the numbers above defaults to zero if not defined in
110the node or any of its parent.
111
112
113Motherboard
114-----------
115
62The motherboard description file provides a single "motherboard" node 116The motherboard description file provides a single "motherboard" node
63using 2 address cells corresponding to the Static Memory Bus used 117using 2 address cells corresponding to the Static Memory Bus used
64between the motherboard and the tile. The first cell defines the Chip 118between the motherboard and the tile. The first cell defines the Chip
@@ -87,22 +141,30 @@ can be used to obtain required phandle in the tile's "aliases" node:
87- SP804 timers: 141- SP804 timers:
88 v2m_timer01 and v2m_timer23 142 v2m_timer01 and v2m_timer23
89 143
90Current Linux implementation requires a "arm,v2m_timer" alias 144The tile description should define a "smb" node, describing the
91pointing at one of the motherboard's SP804 timers, if it is to be 145Static Memory Bus between the tile and motherboard. It must define
92used as the system timer. This alias should be defined in the 146the following properties:
93motherboard files. 147- "simple-bus" compatible value (to ensure creation of the children)
148 compatible = "simple-bus";
149- mapping of the SMB CS/offset addresses into main address space:
150 #address-cells = <2>;
151 #size-cells = <1>;
152 ranges = <...>;
153- interrupts mapping:
154 #interrupt-cells = <1>;
155 interrupt-map-mask = <0 0 63>;
156 interrupt-map = <...>;
94 157
95The tile description must define "ranges", "interrupt-map-mask" and
96"interrupt-map" properties to translate the motherboard's address
97and interrupt space into one used by the tile's processor.
98 158
99Abbreviated example: 159Example of a VE tile description (simplified)
160---------------------------------------------
100 161
101/dts-v1/; 162/dts-v1/;
102 163
103/ { 164/ {
104 model = "V2P-CA5s"; 165 model = "V2P-CA5s";
105 arm,hbi = <0x225>; 166 arm,hbi = <0x225>;
167 arm,vexpress,site = <0xf>;
106 compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; 168 compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
107 interrupt-parent = <&gic>; 169 interrupt-parent = <&gic>;
108 #address-cells = <1>; 170 #address-cells = <1>;
@@ -134,13 +196,29 @@ Abbreviated example:
134 <0x2c000100 0x100>; 196 <0x2c000100 0x100>;
135 }; 197 };
136 198
137 motherboard { 199 dcc {
200 compatible = "simple-bus";
201 arm,vexpress,config-bridge = <&v2m_sysreg>;
202
203 osc@0 {
204 compatible = "arm,vexpress-osc";
205 };
206 };
207
208 smb {
209 compatible = "simple-bus";
210
211 #address-cells = <2>;
212 #size-cells = <1>;
138 /* CS0 is visible at 0x08000000 */ 213 /* CS0 is visible at 0x08000000 */
139 ranges = <0 0 0x08000000 0x04000000>; 214 ranges = <0 0 0x08000000 0x04000000>;
215
216 #interrupt-cells = <1>;
140 interrupt-map-mask = <0 0 63>; 217 interrupt-map-mask = <0 0 63>;
141 /* Active high IRQ 0 is connected to GIC's SPI0 */ 218 /* Active high IRQ 0 is connected to GIC's SPI0 */
142 interrupt-map = <0 0 0 &gic 0 0 4>; 219 interrupt-map = <0 0 0 &gic 0 0 4>;
220
221 /include/ "vexpress-v2m-rs1.dtsi"
143 }; 222 };
144}; 223};
145 224
146/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
new file mode 100644
index 000000000000..04ad47876be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
1* Clock bindings for Freescale i.MX5
2
3Required properties:
4- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX5
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 osc 2
18 ckih1 3
19 ckih2 4
20 ahb 5
21 ipg 6
22 axi_a 7
23 axi_b 8
24 uart_pred 9
25 uart_root 10
26 esdhc_a_pred 11
27 esdhc_b_pred 12
28 esdhc_c_s 13
29 esdhc_d_s 14
30 emi_sel 15
31 emi_slow_podf 16
32 nfc_podf 17
33 ecspi_pred 18
34 ecspi_podf 19
35 usboh3_pred 20
36 usboh3_podf 21
37 usb_phy_pred 22
38 usb_phy_podf 23
39 cpu_podf 24
40 di_pred 25
41 tve_di 26
42 tve_s 27
43 uart1_ipg_gate 28
44 uart1_per_gate 29
45 uart2_ipg_gate 30
46 uart2_per_gate 31
47 uart3_ipg_gate 32
48 uart3_per_gate 33
49 i2c1_gate 34
50 i2c2_gate 35
51 gpt_ipg_gate 36
52 pwm1_ipg_gate 37
53 pwm1_hf_gate 38
54 pwm2_ipg_gate 39
55 pwm2_hf_gate 40
56 gpt_hf_gate 41
57 fec_gate 42
58 usboh3_per_gate 43
59 esdhc1_ipg_gate 44
60 esdhc2_ipg_gate 45
61 esdhc3_ipg_gate 46
62 esdhc4_ipg_gate 47
63 ssi1_ipg_gate 48
64 ssi2_ipg_gate 49
65 ssi3_ipg_gate 50
66 ecspi1_ipg_gate 51
67 ecspi1_per_gate 52
68 ecspi2_ipg_gate 53
69 ecspi2_per_gate 54
70 cspi_ipg_gate 55
71 sdma_gate 56
72 emi_slow_gate 57
73 ipu_s 58
74 ipu_gate 59
75 nfc_gate 60
76 ipu_di1_gate 61
77 vpu_s 62
78 vpu_gate 63
79 vpu_reference_gate 64
80 uart4_ipg_gate 65
81 uart4_per_gate 66
82 uart5_ipg_gate 67
83 uart5_per_gate 68
84 tve_gate 69
85 tve_pred 70
86 esdhc1_per_gate 71
87 esdhc2_per_gate 72
88 esdhc3_per_gate 73
89 esdhc4_per_gate 74
90 usb_phy_gate 75
91 hsi2c_gate 76
92 mipi_hsc1_gate 77
93 mipi_hsc2_gate 78
94 mipi_esc_gate 79
95 mipi_hsp_gate 80
96 ldb_di1_div_3_5 81
97 ldb_di1_div 82
98 ldb_di0_div_3_5 83
99 ldb_di0_div 84
100 ldb_di1_gate 85
101 can2_serial_gate 86
102 can2_ipg_gate 87
103 i2c3_gate 88
104 lp_apm 89
105 periph_apm 90
106 main_bus 91
107 ahb_max 92
108 aips_tz1 93
109 aips_tz2 94
110 tmax1 95
111 tmax2 96
112 tmax3 97
113 spba 98
114 uart_sel 99
115 esdhc_a_sel 100
116 esdhc_b_sel 101
117 esdhc_a_podf 102
118 esdhc_b_podf 103
119 ecspi_sel 104
120 usboh3_sel 105
121 usb_phy_sel 106
122 iim_gate 107
123 usboh3_gate 108
124 emi_fast_gate 109
125 ipu_di0_gate 110
126 gpc_dvfs 111
127 pll1_sw 112
128 pll2_sw 113
129 pll3_sw 114
130 ipu_di0_sel 115
131 ipu_di1_sel 116
132 tve_ext_sel 117
133 mx51_mipi 118
134 pll4_sw 119
135 ldb_di1_sel 120
136 di_pll4_podf 121
137 ldb_di0_sel 122
138 ldb_di0_gate 123
139 usb_phy1_gate 124
140 usb_phy2_gate 125
141 per_lp_apm 126
142 per_pred1 127
143 per_pred2 128
144 per_podf 129
145 per_root 130
146 ssi_apm 131
147 ssi1_root_sel 132
148 ssi2_root_sel 133
149 ssi3_root_sel 134
150 ssi_ext1_sel 135
151 ssi_ext2_sel 136
152 ssi_ext1_com_sel 137
153 ssi_ext2_com_sel 138
154 ssi1_root_pred 139
155 ssi1_root_podf 140
156 ssi2_root_pred 141
157 ssi2_root_podf 142
158 ssi_ext1_pred 143
159 ssi_ext1_podf 144
160 ssi_ext2_pred 145
161 ssi_ext2_podf 146
162 ssi1_root_gate 147
163 ssi2_root_gate 148
164 ssi3_root_gate 149
165 ssi_ext1_gate 150
166 ssi_ext2_gate 151
167 epit1_ipg_gate 152
168 epit1_hf_gate 153
169 epit2_ipg_gate 154
170 epit2_hf_gate 155
171 can_sel 156
172 can1_serial_gate 157
173 can1_ipg_gate 158
174
175Examples (for mx53):
176
177clks: ccm@53fd4000{
178 compatible = "fsl,imx53-ccm";
179 reg = <0x53fd4000 0x4000>;
180 interrupts = <0 71 0x04 0 72 0x04>;
181 #clock-cells = <1>;
182};
183
184can1: can@53fc8000 {
185 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
186 reg = <0x53fc8000 0x4000>;
187 interrupts = <82>;
188 clocks = <&clks 158>, <&clks 157>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 492bd991d52a..d77b4e68dc42 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -187,9 +187,9 @@ clocks and IDs.
187 pll3_usb_otg 172 187 pll3_usb_otg 172
188 pll4_audio 173 188 pll4_audio 173
189 pll5_video 174 189 pll5_video 174
190 pll6_mlb 175 190 pll8_mlb 175
191 pll7_usb_host 176 191 pll7_usb_host 176
192 pll8_enet 177 192 pll6_enet 177
193 ssi1_ipg 178 193 ssi1_ipg 178
194 ssi2_ipg 179 194 ssi2_ipg 179
195 ssi3_ipg 180 195 ssi3_ipg 180
@@ -198,6 +198,11 @@ clocks and IDs.
198 usbphy2 183 198 usbphy2 183
199 ldb_di0_div_3_5 184 199 ldb_di0_div_3_5 184
200 ldb_di1_div_3_5 185 200 ldb_di1_div_3_5 185
201 sata_ref 186
202 sata_ref_100m 187
203 pcie_ref 188
204 pcie_ref_125m 189
205 enet_ref 190
201 206
202Examples: 207Examples:
203 208
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
new file mode 100644
index 000000000000..7f9fb85f5456
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
@@ -0,0 +1,104 @@
1Allwinner Sunxi Interrupt Controller
2
3Required properties:
4
5- compatible : should be "allwinner,sunxi-ic"
6- reg : Specifies base physical address and size of the registers.
7- interrupt-controller : Identifies the node as an interrupt controller
8- #interrupt-cells : Specifies the number of cells needed to encode an
9 interrupt source. The value shall be 1.
10
11The interrupt sources are as follows:
12
130: ENMI
141: UART0
152: UART1
163: UART2
174: UART3
185: IR0
196: IR1
207: I2C0
218: I2C1
229: I2C2
2310: SPI0
2411: SPI1
2512: SPI2
2613: SPDIF
2714: AC97
2815: TS
2916: I2S
3017: UART4
3118: UART5
3219: UART6
3320: UART7
3421: KEYPAD
3522: TIMER0
3623: TIMER1
3724: TIMER2
3825: TIMER3
3926: CAN
4027: DMA
4128: PIO
4229: TOUCH_PANEL
4330: AUDIO_CODEC
4431: LRADC
4532: SDMC0
4633: SDMC1
4734: SDMC2
4835: SDMC3
4936: MEMSTICK
5037: NAND
5138: USB0
5239: USB1
5340: USB2
5441: SCR
5542: CSI0
5643: CSI1
5744: LCDCTRL0
5845: LCDCTRL1
5946: MP
6047: DEFEBE0
6148: DEFEBE1
6249: PMU
6350: SPI3
6451: TZASC
6552: PATA
6653: VE
6754: SS
6855: EMAC
6956: SATA
7057: GPS
7158: HDMI
7259: TVE
7360: ACE
7461: TVD
7562: PS2_0
7663: PS2_1
7764: USB3
7865: USB4
7966: PLE_PFM
8067: TIMER4
8168: TIMER5
8269: GPU_GP
8370: GPU_GPMMU
8471: GPU_PP0
8572: GPU_PPMMU0
8673: GPU_PMU
8774: GPU_RSV0
8875: GPU_RSV1
8976: GPU_RSV2
9077: GPU_RSV3
9178: GPU_RSV4
9279: GPU_RSV5
9380: GPU_RSV6
9482: SYNC_TIMER0
9583: SYNC_TIMER1
96
97Example:
98
99intc: interrupt-controller {
100 compatible = "allwinner,sunxi-ic";
101 reg = <0x01c20400 0x400>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104};
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 03dee50532f5..e97a27856b21 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -8,13 +8,20 @@ on-chip controllers onto these pads.
8Required Properties: 8Required Properties:
9- compatible: should be one of the following. 9- compatible: should be one of the following.
10 - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller. 10 - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
11 - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
11 - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller. 12 - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
12 13
13- reg: Base address of the pin controller hardware module and length of 14- reg: Base address of the pin controller hardware module and length of
14 the address space it occupies. 15 the address space it occupies.
15 16
16- interrupts: interrupt specifier for the controller. The format and value of 17- Pin banks as child nodes: Pin banks of the controller are represented by child
17 the interrupt specifier depends on the interrupt parent for the controller. 18 nodes of the controller node. Bank name is taken from name of the node. Each
19 bank node must contain following properties:
20
21 - gpio-controller: identifies the node as a gpio controller and pin bank.
22 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
23 binding is used, the amount of cells must be specified as 2. See generic
24 GPIO binding documentation for description of particular cells.
18 25
19- Pin mux/config groups as child nodes: The pin mux (selecting pin function 26- Pin mux/config groups as child nodes: The pin mux (selecting pin function
20 mode) and pin config (pull up/down, driver strength) settings are represented 27 mode) and pin config (pull up/down, driver strength) settings are represented
@@ -72,16 +79,24 @@ used as system wakeup events.
72A. External GPIO Interrupts: For supporting external gpio interrupts, the 79A. External GPIO Interrupts: For supporting external gpio interrupts, the
73 following properties should be specified in the pin-controller device node. 80 following properties should be specified in the pin-controller device node.
74 81
75- interrupt-controller: identifies the controller node as interrupt-parent. 82 - interrupt-parent: phandle of the interrupt parent to which the external
76- #interrupt-cells: the value of this property should be 2. 83 GPIO interrupts are forwarded to.
77 - First Cell: represents the external gpio interrupt number local to the 84 - interrupts: interrupt specifier for the controller. The format and value of
78 external gpio interrupt space of the controller. 85 the interrupt specifier depends on the interrupt parent for the controller.
79 - Second Cell: flags to identify the type of the interrupt 86
80 - 1 = rising edge triggered 87 In addition, following properties must be present in node of every bank
81 - 2 = falling edge triggered 88 of pins supporting GPIO interrupts:
82 - 3 = rising and falling edge triggered 89
83 - 4 = high level triggered 90 - interrupt-controller: identifies the controller node as interrupt-parent.
84 - 8 = low level triggered 91 - #interrupt-cells: the value of this property should be 2.
92 - First Cell: represents the external gpio interrupt number local to the
93 external gpio interrupt space of the controller.
94 - Second Cell: flags to identify the type of the interrupt
95 - 1 = rising edge triggered
96 - 2 = falling edge triggered
97 - 3 = rising and falling edge triggered
98 - 4 = high level triggered
99 - 8 = low level triggered
85 100
86B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 101B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
87 child node representing the external wakeup interrupt controller should be 102 child node representing the external wakeup interrupt controller should be
@@ -94,6 +109,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
94 found on Samsung Exynos4210 SoC. 109 found on Samsung Exynos4210 SoC.
95 - interrupt-parent: phandle of the interrupt parent to which the external 110 - interrupt-parent: phandle of the interrupt parent to which the external
96 wakeup interrupts are forwarded to. 111 wakeup interrupts are forwarded to.
112 - interrupts: interrupt used by multiplexed wakeup interrupts.
113
114 In addition, following properties must be present in node of every bank
115 of pins supporting wake-up interrupts:
116
97 - interrupt-controller: identifies the node as interrupt-parent. 117 - interrupt-controller: identifies the node as interrupt-parent.
98 - #interrupt-cells: the value of this property should be 2 118 - #interrupt-cells: the value of this property should be 2
99 - First Cell: represents the external wakeup interrupt number local to 119 - First Cell: represents the external wakeup interrupt number local to
@@ -105,11 +125,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
105 - 4 = high level triggered 125 - 4 = high level triggered
106 - 8 = low level triggered 126 - 8 = low level triggered
107 127
128 Node of every bank of pins supporting direct wake-up interrupts (without
129 multiplexing) must contain following properties:
130
131 - interrupt-parent: phandle of the interrupt parent to which the external
132 wakeup interrupts are forwarded to.
133 - interrupts: interrupts of the interrupt parent which are used for external
134 wakeup interrupts from pins of the bank, must contain interrupts for all
135 pins of the bank.
136
108Aliases: 137Aliases:
109 138
110All the pin controller nodes should be represented in the aliases node using 139All the pin controller nodes should be represented in the aliases node using
111the following format 'pinctrl{n}' where n is a unique number for the alias. 140the following format 'pinctrl{n}' where n is a unique number for the alias.
112 141
142Example: A pin-controller node with pin banks:
143
144 pinctrl_0: pinctrl@11400000 {
145 compatible = "samsung,pinctrl-exynos4210";
146 reg = <0x11400000 0x1000>;
147 interrupts = <0 47 0>;
148
149 /* ... */
150
151 /* Pin bank without external interrupts */
152 gpy0: gpy0 {
153 gpio-controller;
154 #gpio-cells = <2>;
155 };
156
157 /* ... */
158
159 /* Pin bank with external GPIO or muxed wake-up interrupts */
160 gpj0: gpj0 {
161 gpio-controller;
162 #gpio-cells = <2>;
163
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 };
167
168 /* ... */
169
170 /* Pin bank with external direct wake-up interrupts */
171 gpx0: gpx0 {
172 gpio-controller;
173 #gpio-cells = <2>;
174
175 interrupt-controller;
176 interrupt-parent = <&gic>;
177 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
178 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
179 #interrupt-cells = <2>;
180 };
181
182 /* ... */
183 };
184
113Example 1: A pin-controller node with pin groups. 185Example 1: A pin-controller node with pin groups.
114 186
115 pinctrl_0: pinctrl@11400000 { 187 pinctrl_0: pinctrl@11400000 {
@@ -117,6 +189,8 @@ Example 1: A pin-controller node with pin groups.
117 reg = <0x11400000 0x1000>; 189 reg = <0x11400000 0x1000>;
118 interrupts = <0 47 0>; 190 interrupts = <0 47 0>;
119 191
192 /* ... */
193
120 uart0_data: uart0-data { 194 uart0_data: uart0-data {
121 samsung,pins = "gpa0-0", "gpa0-1"; 195 samsung,pins = "gpa0-0", "gpa0-1";
122 samsung,pin-function = <2>; 196 samsung,pin-function = <2>;
@@ -158,20 +232,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node.
158 pinctrl_1: pinctrl@11000000 { 232 pinctrl_1: pinctrl@11000000 {
159 compatible = "samsung,pinctrl-exynos4210"; 233 compatible = "samsung,pinctrl-exynos4210";
160 reg = <0x11000000 0x1000>; 234 reg = <0x11000000 0x1000>;
161 interrupts = <0 46 0>; 235 interrupts = <0 46 0>
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 236
165 wakup_eint: wakeup-interrupt-controller { 237 /* ... */
238
239 wakeup-interrupt-controller {
166 compatible = "samsung,exynos4210-wakeup-eint"; 240 compatible = "samsung,exynos4210-wakeup-eint";
167 interrupt-parent = <&gic>; 241 interrupt-parent = <&gic>;
168 interrupt-controller; 242 interrupts = <0 32 0>;
169 #interrupt-cells = <2>;
170 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
171 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
172 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
173 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
174 <0 32 0>;
175 }; 243 };
176 }; 244 };
177 245
@@ -190,7 +258,8 @@ Example 4: Set up the default pin state for uart controller.
190 258
191 static int s3c24xx_serial_probe(struct platform_device *pdev) { 259 static int s3c24xx_serial_probe(struct platform_device *pdev) {
192 struct pinctrl *pinctrl; 260 struct pinctrl *pinctrl;
193 ... 261
194 ... 262 /* ... */
263
195 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 264 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
196 } 265 }
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
new file mode 100644
index 000000000000..0c7b64e95a61
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
@@ -0,0 +1,17 @@
1Allwinner A1X SoCs Timer Controller
2
3Required properties:
4
5- compatible : should be "allwinner,sunxi-timer"
6- reg : Specifies base physical address and size of the registers.
7- interrupts : The interrupt of the first timer
8- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
9
10Example:
11
12timer {
13 compatible = "allwinner,sunxi-timer";
14 reg = <0x01c20c00 0x400>;
15 interrupts = <22>;
16 clocks = <&osc>;
17};
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
new file mode 100644
index 000000000000..d209366b4a69
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
@@ -0,0 +1,13 @@
1BCM2835 Watchdog timer
2
3Required properties:
4
5- compatible : should be "brcm,bcm2835-pm-wdt"
6- reg : Specifies base physical address and size of the registers.
7
8Example:
9
10watchdog {
11 compatible = "brcm,bcm2835-pm-wdt";
12 reg = <0x7e100000 0x28>;
13};
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
new file mode 100644
index 000000000000..0b2717775600
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -0,0 +1,13 @@
1Allwinner sunXi Watchdog timer
2
3Required properties:
4
5- compatible : should be "allwinner,sunxi-wdt"
6- reg : Specifies base physical address and size of the registers.
7
8Example:
9
10wdt: watchdog@01c20c90 {
11 compatible = "allwinner,sunxi-wdt";
12 reg = <0x01c20c90 0x10>;
13};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 10:46:04 -0500