diff options
189 files changed, 8183 insertions, 5212 deletions
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 8f08a86e03b7..da0151db9964 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README | |||
@@ -88,6 +88,7 @@ EBU Armada family | |||
88 | MV78230 | 88 | MV78230 |
89 | MV78260 | 89 | MV78260 |
90 | MV78460 | 90 | MV78460 |
91 | NOTE: not to be confused with the non-SMP 78xx0 SoCs | ||
91 | 92 | ||
92 | Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf | 93 | Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf |
93 | No public datasheet available. | 94 | No public datasheet available. |
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index e3f93fb9224e..7945238453ed 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README | |||
@@ -10,6 +10,10 @@ SunXi family | |||
10 | Linux kernel mach directory: arch/arm/mach-sunxi | 10 | Linux kernel mach directory: arch/arm/mach-sunxi |
11 | 11 | ||
12 | Flavors: | 12 | Flavors: |
13 | * ARM926 based SoCs | ||
14 | - Allwinner F20 (sun3i) | ||
15 | + Not Supported | ||
16 | |||
13 | * ARM Cortex-A8 based SoCs | 17 | * ARM Cortex-A8 based SoCs |
14 | - Allwinner A10 (sun4i) | 18 | - Allwinner A10 (sun4i) |
15 | + Datasheet | 19 | + Datasheet |
@@ -25,4 +29,24 @@ SunXi family | |||
25 | + Datasheet | 29 | + Datasheet |
26 | http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf | 30 | http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf |
27 | + User Manual | 31 | + User Manual |
28 | http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf | 32 | http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-01-08%29.pdf |
33 | |||
34 | * Dual ARM Cortex-A7 based SoCs | ||
35 | - Allwinner A20 (sun7i) | ||
36 | + User Manual | ||
37 | http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf | ||
38 | |||
39 | - Allwinner A23 | ||
40 | + Not Supported | ||
41 | |||
42 | * Quad ARM Cortex-A7 based SoCs | ||
43 | - Allwinner A31 (sun6i) | ||
44 | + Datasheet | ||
45 | http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf | ||
46 | |||
47 | - Allwinner A31s (sun6i) | ||
48 | + Not Supported | ||
49 | |||
50 | * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs | ||
51 | - Allwinner A80 | ||
52 | + Not Supported \ No newline at end of file | ||
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index db5858e32d3f..5fac246a9530 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards | |||
@@ -9,9 +9,53 @@ Required properties (in root node): | |||
9 | 9 | ||
10 | FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. | 10 | FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. |
11 | 11 | ||
12 | In the root node the Integrator/CP must have a /cpcon node pointing | 12 | Required nodes: |
13 | to the CP control registers, and the Integrator/AP must have a | 13 | |
14 | /syscon node pointing to the Integrator/AP system controller. | 14 | - core-module: the root node to the Integrator platforms must have |
15 | a core-module with regs and the compatible string | ||
16 | "arm,core-module-integrator" | ||
17 | |||
18 | Required properties for the core module: | ||
19 | - regs: the location and size of the core module registers, one | ||
20 | range of 0x200 bytes. | ||
21 | |||
22 | - syscon: the root node of the Integrator platforms must have a | ||
23 | system controller node pointong to the control registers, | ||
24 | with the compatible string | ||
25 | "arm,integrator-ap-syscon" | ||
26 | "arm,integrator-cp-syscon" | ||
27 | respectively. | ||
28 | |||
29 | Required properties for the system controller: | ||
30 | - regs: the location and size of the system controller registers, | ||
31 | one range of 0x100 bytes. | ||
32 | |||
33 | Required properties for the AP system controller: | ||
34 | - interrupts: the AP syscon node must include the logical module | ||
35 | interrupts, stated in order of module instance <module 0>, | ||
36 | <module 1>, <module 2> ... for the CP system controller this | ||
37 | is not required not of any use. | ||
38 | |||
39 | /dts-v1/; | ||
40 | /include/ "integrator.dtsi" | ||
41 | |||
42 | / { | ||
43 | model = "ARM Integrator/AP"; | ||
44 | compatible = "arm,integrator-ap"; | ||
45 | |||
46 | core-module@10000000 { | ||
47 | compatible = "arm,core-module-integrator"; | ||
48 | reg = <0x10000000 0x200>; | ||
49 | }; | ||
50 | |||
51 | syscon { | ||
52 | compatible = "arm,integrator-ap-syscon"; | ||
53 | reg = <0x11000000 0x100>; | ||
54 | interrupt-parent = <&pic>; | ||
55 | /* These are the logic module IRQs */ | ||
56 | interrupts = <9>, <10>, <11>, <12>; | ||
57 | }; | ||
58 | }; | ||
15 | 59 | ||
16 | 60 | ||
17 | ARM Versatile Application and Platform Baseboards | 61 | ARM Versatile Application and Platform Baseboards |
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index 5a90a724b520..6aab72bf67ea 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt | |||
@@ -215,6 +215,11 @@ clocks and IDs. | |||
215 | cko2 200 | 215 | cko2 200 |
216 | cko 201 | 216 | cko 201 |
217 | vdoa 202 | 217 | vdoa 202 |
218 | pll4_audio_div 203 | ||
219 | lvds1_sel 204 | ||
220 | lvds2_sel 205 | ||
221 | lvds1_gate 206 | ||
222 | lvds2_gate 207 | ||
218 | 223 | ||
219 | Examples: | 224 | Examples: |
220 | 225 | ||
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 00a5c26454eb..91a748fed13d 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt | |||
@@ -45,8 +45,8 @@ Additionally, "allwinner,*-gates-clk" clocks require: | |||
45 | 45 | ||
46 | Clock consumers should specify the desired clocks they use with a | 46 | Clock consumers should specify the desired clocks they use with a |
47 | "clocks" phandle cell. Consumers that are using a gated clock should | 47 | "clocks" phandle cell. Consumers that are using a gated clock should |
48 | provide an additional ID in their clock property. The values of this | 48 | provide an additional ID in their clock property. This ID is the |
49 | ID are documented in sunxi/<soc>-gates.txt. | 49 | offset of the bit controlling this particular gate in the register. |
50 | 50 | ||
51 | For example: | 51 | For example: |
52 | 52 | ||
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt deleted file mode 100644 index 6a03475bbfe2..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt +++ /dev/null | |||
@@ -1,93 +0,0 @@ | |||
1 | Gate clock outputs | ||
2 | ------------------ | ||
3 | |||
4 | * AXI gates ("allwinner,sun4i-axi-gates-clk") | ||
5 | |||
6 | DRAM 0 | ||
7 | |||
8 | * AHB gates ("allwinner,sun4i-ahb-gates-clk") | ||
9 | |||
10 | USB0 0 | ||
11 | EHCI0 1 | ||
12 | OHCI0 2* | ||
13 | EHCI1 3 | ||
14 | OHCI1 4* | ||
15 | SS 5 | ||
16 | DMA 6 | ||
17 | BIST 7 | ||
18 | MMC0 8 | ||
19 | MMC1 9 | ||
20 | MMC2 10 | ||
21 | MMC3 11 | ||
22 | MS 12** | ||
23 | NAND 13 | ||
24 | SDRAM 14 | ||
25 | |||
26 | ACE 16 | ||
27 | EMAC 17 | ||
28 | TS 18 | ||
29 | |||
30 | SPI0 20 | ||
31 | SPI1 21 | ||
32 | SPI2 22 | ||
33 | SPI3 23 | ||
34 | PATA 24 | ||
35 | SATA 25** | ||
36 | GPS 26* | ||
37 | |||
38 | VE 32 | ||
39 | TVD 33 | ||
40 | TVE0 34 | ||
41 | TVE1 35 | ||
42 | LCD0 36 | ||
43 | LCD1 37 | ||
44 | |||
45 | CSI0 40 | ||
46 | CSI1 41 | ||
47 | |||
48 | HDMI 43 | ||
49 | DE_BE0 44 | ||
50 | DE_BE1 45 | ||
51 | DE_FE1 46 | ||
52 | DE_FE1 47 | ||
53 | |||
54 | MP 50 | ||
55 | |||
56 | MALI400 52 | ||
57 | |||
58 | * APB0 gates ("allwinner,sun4i-apb0-gates-clk") | ||
59 | |||
60 | CODEC 0 | ||
61 | SPDIF 1* | ||
62 | AC97 2 | ||
63 | IIS 3 | ||
64 | |||
65 | PIO 5 | ||
66 | IR0 6 | ||
67 | IR1 7 | ||
68 | |||
69 | KEYPAD 10 | ||
70 | |||
71 | * APB1 gates ("allwinner,sun4i-apb1-gates-clk") | ||
72 | |||
73 | I2C0 0 | ||
74 | I2C1 1 | ||
75 | I2C2 2 | ||
76 | |||
77 | CAN 4 | ||
78 | SCR 5 | ||
79 | PS20 6 | ||
80 | PS21 7 | ||
81 | |||
82 | UART0 16 | ||
83 | UART1 17 | ||
84 | UART2 18 | ||
85 | UART3 19 | ||
86 | UART4 20 | ||
87 | UART5 21 | ||
88 | UART6 22 | ||
89 | UART7 23 | ||
90 | |||
91 | Notation: | ||
92 | [*]: The datasheet didn't mention these, but they are present on AW code | ||
93 | [**]: The datasheet had this marked as "NC" but they are used on AW code | ||
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt deleted file mode 100644 index d24279fe1429..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt +++ /dev/null | |||
@@ -1,75 +0,0 @@ | |||
1 | Gate clock outputs | ||
2 | ------------------ | ||
3 | |||
4 | * AXI gates ("allwinner,sun4i-axi-gates-clk") | ||
5 | |||
6 | DRAM 0 | ||
7 | |||
8 | * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk") | ||
9 | |||
10 | USB0 0 | ||
11 | EHCI0 1 | ||
12 | OHCI0 2 | ||
13 | |||
14 | SS 5 | ||
15 | DMA 6 | ||
16 | BIST 7 | ||
17 | MMC0 8 | ||
18 | MMC1 9 | ||
19 | MMC2 10 | ||
20 | |||
21 | NAND 13 | ||
22 | SDRAM 14 | ||
23 | |||
24 | EMAC 17 | ||
25 | TS 18 | ||
26 | |||
27 | SPI0 20 | ||
28 | SPI1 21 | ||
29 | SPI2 22 | ||
30 | |||
31 | GPS 26 | ||
32 | |||
33 | HSTIMER 28 | ||
34 | |||
35 | VE 32 | ||
36 | |||
37 | TVE 34 | ||
38 | |||
39 | LCD 36 | ||
40 | |||
41 | CSI 40 | ||
42 | |||
43 | HDMI 43 | ||
44 | DE_BE 44 | ||
45 | |||
46 | DE_FE 46 | ||
47 | |||
48 | IEP 51 | ||
49 | MALI400 52 | ||
50 | |||
51 | * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk") | ||
52 | |||
53 | CODEC 0 | ||
54 | |||
55 | IIS 3 | ||
56 | |||
57 | PIO 5 | ||
58 | IR 6 | ||
59 | |||
60 | KEYPAD 10 | ||
61 | |||
62 | * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk") | ||
63 | |||
64 | I2C0 0 | ||
65 | I2C1 1 | ||
66 | I2C2 2 | ||
67 | |||
68 | UART0 16 | ||
69 | UART1 17 | ||
70 | UART2 18 | ||
71 | UART3 19 | ||
72 | |||
73 | Notation: | ||
74 | [*]: The datasheet didn't mention these, but they are present on AW code | ||
75 | [**]: The datasheet had this marked as "NC" but they are used on AW code | ||
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt deleted file mode 100644 index 006b6dfc4703..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt +++ /dev/null | |||
@@ -1,58 +0,0 @@ | |||
1 | Gate clock outputs | ||
2 | ------------------ | ||
3 | |||
4 | * AXI gates ("allwinner,sun4i-axi-gates-clk") | ||
5 | |||
6 | DRAM 0 | ||
7 | |||
8 | * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk") | ||
9 | |||
10 | USBOTG 0 | ||
11 | EHCI 1 | ||
12 | OHCI 2 | ||
13 | |||
14 | SS 5 | ||
15 | DMA 6 | ||
16 | BIST 7 | ||
17 | MMC0 8 | ||
18 | MMC1 9 | ||
19 | MMC2 10 | ||
20 | |||
21 | NAND 13 | ||
22 | SDRAM 14 | ||
23 | |||
24 | SPI0 20 | ||
25 | SPI1 21 | ||
26 | SPI2 22 | ||
27 | |||
28 | STIMER 28 | ||
29 | |||
30 | VE 32 | ||
31 | |||
32 | LCD 36 | ||
33 | |||
34 | CSI 40 | ||
35 | |||
36 | DE_BE 44 | ||
37 | |||
38 | DE_FE 46 | ||
39 | |||
40 | IEP 51 | ||
41 | MALI400 52 | ||
42 | |||
43 | * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk") | ||
44 | |||
45 | CODEC 0 | ||
46 | |||
47 | PIO 5 | ||
48 | IR 6 | ||
49 | |||
50 | * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk") | ||
51 | |||
52 | I2C0 0 | ||
53 | I2C1 1 | ||
54 | I2C2 2 | ||
55 | |||
56 | UART1 17 | ||
57 | |||
58 | UART3 19 | ||
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt deleted file mode 100644 index fe44932b5c6b..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt +++ /dev/null | |||
@@ -1,83 +0,0 @@ | |||
1 | Gate clock outputs | ||
2 | ------------------ | ||
3 | |||
4 | * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk") | ||
5 | |||
6 | MIPI DSI 1 | ||
7 | |||
8 | SS 5 | ||
9 | DMA 6 | ||
10 | |||
11 | MMC0 8 | ||
12 | MMC1 9 | ||
13 | MMC2 10 | ||
14 | MMC3 11 | ||
15 | |||
16 | NAND1 12 | ||
17 | NAND0 13 | ||
18 | SDRAM 14 | ||
19 | |||
20 | GMAC 17 | ||
21 | TS 18 | ||
22 | HSTIMER 19 | ||
23 | SPI0 20 | ||
24 | SPI1 21 | ||
25 | SPI2 22 | ||
26 | SPI3 23 | ||
27 | USB_OTG 24 | ||
28 | |||
29 | EHCI0 26 | ||
30 | EHCI1 27 | ||
31 | |||
32 | OHCI0 29 | ||
33 | OHCI1 30 | ||
34 | OHCI2 31 | ||
35 | VE 32 | ||
36 | |||
37 | LCD0 36 | ||
38 | LCD1 37 | ||
39 | |||
40 | CSI 40 | ||
41 | |||
42 | HDMI 43 | ||
43 | DE_BE0 44 | ||
44 | DE_BE1 45 | ||
45 | DE_FE1 46 | ||
46 | DE_FE1 47 | ||
47 | |||
48 | MP 50 | ||
49 | |||
50 | GPU 52 | ||
51 | |||
52 | DEU0 55 | ||
53 | DEU1 56 | ||
54 | DRC0 57 | ||
55 | DRC1 58 | ||
56 | |||
57 | * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk") | ||
58 | |||
59 | CODEC 0 | ||
60 | |||
61 | DIGITAL MIC 4 | ||
62 | PIO 5 | ||
63 | |||
64 | DAUDIO0 12 | ||
65 | DAUDIO1 13 | ||
66 | |||
67 | * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk") | ||
68 | |||
69 | I2C0 0 | ||
70 | I2C1 1 | ||
71 | I2C2 2 | ||
72 | I2C3 3 | ||
73 | |||
74 | UART0 16 | ||
75 | UART1 17 | ||
76 | UART2 18 | ||
77 | UART3 19 | ||
78 | UART4 20 | ||
79 | UART5 21 | ||
80 | |||
81 | Notation: | ||
82 | [*]: The datasheet didn't mention these, but they are present on AW code | ||
83 | [**]: The datasheet had this marked as "NC" but they are used on AW code | ||
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt deleted file mode 100644 index 357f4fdc02ef..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | Gate clock outputs | ||
2 | ------------------ | ||
3 | |||
4 | * AXI gates ("allwinner,sun4i-axi-gates-clk") | ||
5 | |||
6 | DRAM 0 | ||
7 | |||
8 | * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk") | ||
9 | |||
10 | USB0 0 | ||
11 | EHCI0 1 | ||
12 | OHCI0 2 | ||
13 | EHCI1 3 | ||
14 | OHCI1 4 | ||
15 | SS 5 | ||
16 | DMA 6 | ||
17 | BIST 7 | ||
18 | MMC0 8 | ||
19 | MMC1 9 | ||
20 | MMC2 10 | ||
21 | MMC3 11 | ||
22 | MS 12 | ||
23 | NAND 13 | ||
24 | SDRAM 14 | ||
25 | |||
26 | ACE 16 | ||
27 | EMAC 17 | ||
28 | TS 18 | ||
29 | |||
30 | SPI0 20 | ||
31 | SPI1 21 | ||
32 | SPI2 22 | ||
33 | SPI3 23 | ||
34 | |||
35 | SATA 25 | ||
36 | |||
37 | HSTIMER 28 | ||
38 | |||
39 | VE 32 | ||
40 | TVD 33 | ||
41 | TVE0 34 | ||
42 | TVE1 35 | ||
43 | LCD0 36 | ||
44 | LCD1 37 | ||
45 | |||
46 | CSI0 40 | ||
47 | CSI1 41 | ||
48 | |||
49 | HDMI1 42 | ||
50 | HDMI0 43 | ||
51 | DE_BE0 44 | ||
52 | DE_BE1 45 | ||
53 | DE_FE1 46 | ||
54 | DE_FE1 47 | ||
55 | |||
56 | GMAC 49 | ||
57 | MP 50 | ||
58 | |||
59 | MALI400 52 | ||
60 | |||
61 | * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk") | ||
62 | |||
63 | CODEC 0 | ||
64 | SPDIF 1 | ||
65 | AC97 2 | ||
66 | IIS0 3 | ||
67 | IIS1 4 | ||
68 | PIO 5 | ||
69 | IR0 6 | ||
70 | IR1 7 | ||
71 | IIS2 8 | ||
72 | |||
73 | KEYPAD 10 | ||
74 | |||
75 | * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk") | ||
76 | |||
77 | I2C0 0 | ||
78 | I2C1 1 | ||
79 | I2C2 2 | ||
80 | I2C3 3 | ||
81 | CAN 4 | ||
82 | SCR 5 | ||
83 | PS20 6 | ||
84 | PS21 7 | ||
85 | |||
86 | I2C4 15 | ||
87 | UART0 16 | ||
88 | UART1 17 | ||
89 | UART2 18 | ||
90 | UART3 19 | ||
91 | UART4 20 | ||
92 | UART5 21 | ||
93 | UART6 22 | ||
94 | UART7 23 | ||
95 | |||
96 | Notation: | ||
97 | [*]: The datasheet didn't mention these, but they are present on AW code | ||
98 | [**]: The datasheet had this marked as "NC" but they are used on AW code | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt index 57edb30dbbca..3d3b2b91e333 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | |||
@@ -8,9 +8,6 @@ Required properties: | |||
8 | - #interrupt-cells : Specifies the number of cells needed to encode an | 8 | - #interrupt-cells : Specifies the number of cells needed to encode an |
9 | interrupt source. The value shall be 1. | 9 | interrupt source. The value shall be 1. |
10 | 10 | ||
11 | For the valid interrupt sources for your SoC, see the documentation in | ||
12 | sunxi/<soc>.txt | ||
13 | |||
14 | Example: | 11 | Example: |
15 | 12 | ||
16 | intc: interrupt-controller { | 13 | intc: interrupt-controller { |
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt deleted file mode 100644 index 76b98c834499..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt +++ /dev/null | |||
@@ -1,89 +0,0 @@ | |||
1 | Allwinner A10 (sun4i) interrupt sources | ||
2 | --------------------------------------- | ||
3 | |||
4 | The interrupt sources available for the Allwinner A10 SoC are the | ||
5 | following one: | ||
6 | |||
7 | 0: ENMI | ||
8 | 1: UART0 | ||
9 | 2: UART1 | ||
10 | 3: UART2 | ||
11 | 4: UART3 | ||
12 | 5: IR0 | ||
13 | 6: IR1 | ||
14 | 7: I2C0 | ||
15 | 8: I2C1 | ||
16 | 9: I2C2 | ||
17 | 10: SPI0 | ||
18 | 11: SPI1 | ||
19 | 12: SPI2 | ||
20 | 13: SPDIF | ||
21 | 14: AC97 | ||
22 | 15: TS | ||
23 | 16: I2S | ||
24 | 17: UART4 | ||
25 | 18: UART5 | ||
26 | 19: UART6 | ||
27 | 20: UART7 | ||
28 | 21: KEYPAD | ||
29 | 22: TIMER0 | ||
30 | 23: TIMER1 | ||
31 | 24: TIMER2 | ||
32 | 25: TIMER3 | ||
33 | 26: CAN | ||
34 | 27: DMA | ||
35 | 28: PIO | ||
36 | 29: TOUCH_PANEL | ||
37 | 30: AUDIO_CODEC | ||
38 | 31: LRADC | ||
39 | 32: MMC0 | ||
40 | 33: MMC1 | ||
41 | 34: MMC2 | ||
42 | 35: MMC3 | ||
43 | 36: MEMSTICK | ||
44 | 37: NAND | ||
45 | 38: USB0 | ||
46 | 39: USB1 | ||
47 | 40: USB2 | ||
48 | 41: SCR | ||
49 | 42: CSI0 | ||
50 | 43: CSI1 | ||
51 | 44: LCDCTRL0 | ||
52 | 45: LCDCTRL1 | ||
53 | 46: MP | ||
54 | 47: DEFEBE0 | ||
55 | 48: DEFEBE1 | ||
56 | 49: PMU | ||
57 | 50: SPI3 | ||
58 | 51: TZASC | ||
59 | 52: PATA | ||
60 | 53: VE | ||
61 | 54: SS | ||
62 | 55: EMAC | ||
63 | 56: SATA | ||
64 | 57: GPS | ||
65 | 58: HDMI | ||
66 | 59: TVE | ||
67 | 60: ACE | ||
68 | 61: TVD | ||
69 | 62: PS2_0 | ||
70 | 63: PS2_1 | ||
71 | 64: USB3 | ||
72 | 65: USB4 | ||
73 | 66: PLE_PFM | ||
74 | 67: TIMER4 | ||
75 | 68: TIMER5 | ||
76 | 69: GPU_GP | ||
77 | 70: GPU_GPMMU | ||
78 | 71: GPU_PP0 | ||
79 | 72: GPU_PPMMU0 | ||
80 | 73: GPU_PMU | ||
81 | 74: GPU_RSV0 | ||
82 | 75: GPU_RSV1 | ||
83 | 76: GPU_RSV2 | ||
84 | 77: GPU_RSV3 | ||
85 | 78: GPU_RSV4 | ||
86 | 79: GPU_RSV5 | ||
87 | 80: GPU_RSV6 | ||
88 | 82: SYNC_TIMER0 | ||
89 | 83: SYNC_TIMER1 | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt deleted file mode 100644 index 2ec3b5ce1a0b..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | Allwinner A13 (sun5i) interrupt sources | ||
2 | --------------------------------------- | ||
3 | |||
4 | The interrupt sources available for the Allwinner A13 SoC are the | ||
5 | following one: | ||
6 | |||
7 | 0: ENMI | ||
8 | 2: UART1 | ||
9 | 4: UART3 | ||
10 | 5: IR | ||
11 | 7: I2C0 | ||
12 | 8: I2C1 | ||
13 | 9: I2C2 | ||
14 | 10: SPI0 | ||
15 | 11: SPI1 | ||
16 | 12: SPI2 | ||
17 | 22: TIMER0 | ||
18 | 23: TIMER1 | ||
19 | 24: TIMER2 | ||
20 | 25: TIMER3 | ||
21 | 27: DMA | ||
22 | 28: PIO | ||
23 | 29: TOUCH_PANEL | ||
24 | 30: AUDIO_CODEC | ||
25 | 31: LRADC | ||
26 | 32: MMC0 | ||
27 | 33: MMC1 | ||
28 | 34: MMC2 | ||
29 | 37: NAND | ||
30 | 38: USB OTG | ||
31 | 39: USB EHCI | ||
32 | 40: USB OHCI | ||
33 | 42: CSI | ||
34 | 44: LCDCTRL | ||
35 | 47: DEFEBE | ||
36 | 49: PMU | ||
37 | 53: VE | ||
38 | 54: SS | ||
39 | 66: PLE_PFM | ||
40 | 67: TIMER4 | ||
41 | 68: TIMER5 | ||
42 | 69: GPU_GP | ||
43 | 70: GPU_GPMMU | ||
44 | 71: GPU_PP0 | ||
45 | 72: GPU_PPMMU0 | ||
46 | 73: GPU_PMU | ||
47 | 74: GPU_RSV0 | ||
48 | 75: GPU_RSV1 | ||
49 | 76: GPU_RSV2 | ||
50 | 77: GPU_RSV3 | ||
51 | 78: GPU_RSV4 | ||
52 | 79: GPU_RSV5 | ||
53 | 80: GPU_RSV6 | ||
54 | 82: SYNC_TIMER0 | ||
55 | 83: SYNC_TIMER1 | ||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e98261cb05bd..9bd3a85d880f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -317,6 +317,7 @@ config ARCH_INTEGRATOR | |||
317 | select NEED_MACH_MEMORY_H | 317 | select NEED_MACH_MEMORY_H |
318 | select PLAT_VERSATILE | 318 | select PLAT_VERSATILE |
319 | select SPARSE_IRQ | 319 | select SPARSE_IRQ |
320 | select USE_OF | ||
320 | select VERSATILE_FPGA_IRQ | 321 | select VERSATILE_FPGA_IRQ |
321 | help | 322 | help |
322 | Support for ARM's Integrator platform. | 323 | Support for ARM's Integrator platform. |
@@ -723,6 +724,7 @@ config ARCH_S3C64XX | |||
723 | select ARM_VIC | 724 | select ARM_VIC |
724 | select CLKDEV_LOOKUP | 725 | select CLKDEV_LOOKUP |
725 | select CLKSRC_SAMSUNG_PWM | 726 | select CLKSRC_SAMSUNG_PWM |
727 | select COMMON_CLK | ||
726 | select CPU_V6 | 728 | select CPU_V6 |
727 | select GENERIC_CLOCKEVENTS | 729 | select GENERIC_CLOCKEVENTS |
728 | select GPIO_SAMSUNG | 730 | select GPIO_SAMSUNG |
@@ -736,7 +738,6 @@ config ARCH_S3C64XX | |||
736 | select S3C_DEV_NAND | 738 | select S3C_DEV_NAND |
737 | select S3C_GPIO_TRACK | 739 | select S3C_GPIO_TRACK |
738 | select SAMSUNG_ATAGS | 740 | select SAMSUNG_ATAGS |
739 | select SAMSUNG_CLKSRC | ||
740 | select SAMSUNG_GPIOLIB_4BIT | 741 | select SAMSUNG_GPIOLIB_4BIT |
741 | select SAMSUNG_WAKEMASK | 742 | select SAMSUNG_WAKEMASK |
742 | select SAMSUNG_WDT_RESET | 743 | select SAMSUNG_WDT_RESET |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 9762c84b4198..d597c6b8488b 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -386,6 +386,13 @@ choice | |||
386 | when u-boot hands over to the kernel, the system | 386 | when u-boot hands over to the kernel, the system |
387 | silently crashes, with no serial output at all. | 387 | silently crashes, with no serial output at all. |
388 | 388 | ||
389 | config DEBUG_VF_UART | ||
390 | bool "Vybrid UART" | ||
391 | depends on SOC_VF610 | ||
392 | help | ||
393 | Say Y here if you want kernel low-level debugging support | ||
394 | on Vybrid based platforms. | ||
395 | |||
389 | config DEBUG_NOMADIK_UART | 396 | config DEBUG_NOMADIK_UART |
390 | bool "Kernel low-level debugging messages via NOMADIK UART" | 397 | bool "Kernel low-level debugging messages via NOMADIK UART" |
391 | depends on ARCH_NOMADIK | 398 | depends on ARCH_NOMADIK |
@@ -906,6 +913,7 @@ config DEBUG_LL_INCLUDE | |||
906 | default "debug/tegra.S" if DEBUG_TEGRA_UART | 913 | default "debug/tegra.S" if DEBUG_TEGRA_UART |
907 | default "debug/ux500.S" if DEBUG_UX500_UART | 914 | default "debug/ux500.S" if DEBUG_UX500_UART |
908 | default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT | 915 | default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT |
916 | default "debug/vf.S" if DEBUG_VF_UART | ||
909 | default "debug/vt8500.S" if DEBUG_VT8500_UART0 | 917 | default "debug/vt8500.S" if DEBUG_VT8500_UART0 |
910 | default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 | 918 | default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 |
911 | default "mach/debug-macro.S" | 919 | default "mach/debug-macro.S" |
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index e8559b753c9d..bc22557d7a6a 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi | |||
@@ -19,6 +19,14 @@ | |||
19 | bootargs = "console=ttyAMA0"; | 19 | bootargs = "console=ttyAMA0"; |
20 | }; | 20 | }; |
21 | 21 | ||
22 | psci { | ||
23 | compatible = "arm,psci"; | ||
24 | method = "smc"; | ||
25 | cpu_suspend = <0x84000002>; | ||
26 | cpu_off = <0x84000004>; | ||
27 | cpu_on = <0x84000006>; | ||
28 | }; | ||
29 | |||
22 | soc { | 30 | soc { |
23 | #address-cells = <1>; | 31 | #address-cells = <1>; |
24 | #size-cells = <1>; | 32 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c46651e4d966..177d9e791a01 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi | |||
@@ -380,7 +380,9 @@ | |||
380 | }; | 380 | }; |
381 | 381 | ||
382 | anatop: anatop@020c8000 { | 382 | anatop: anatop@020c8000 { |
383 | compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; | 383 | compatible = "fsl,imx6sl-anatop", |
384 | "fsl,imx6q-anatop", | ||
385 | "syscon", "simple-bus"; | ||
384 | reg = <0x020c8000 0x1000>; | 386 | reg = <0x020c8000 0x1000>; |
385 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | 387 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
386 | 388 | ||
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 813b91d7bea2..0f06f8687b0b 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi | |||
@@ -5,6 +5,11 @@ | |||
5 | /include/ "skeleton.dtsi" | 5 | /include/ "skeleton.dtsi" |
6 | 6 | ||
7 | / { | 7 | / { |
8 | core-module@10000000 { | ||
9 | compatible = "arm,core-module-integrator"; | ||
10 | reg = <0x10000000 0x200>; | ||
11 | }; | ||
12 | |||
8 | timer@13000000 { | 13 | timer@13000000 { |
9 | reg = <0x13000000 0x100>; | 14 | reg = <0x13000000 0x100>; |
10 | interrupt-parent = <&pic>; | 15 | interrupt-parent = <&pic>; |
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index b6b82eca8d1e..e6be9315ff0a 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts | |||
@@ -19,8 +19,11 @@ | |||
19 | }; | 19 | }; |
20 | 20 | ||
21 | syscon { | 21 | syscon { |
22 | /* AP system controller registers */ | 22 | compatible = "arm,integrator-ap-syscon"; |
23 | reg = <0x11000000 0x100>; | 23 | reg = <0x11000000 0x100>; |
24 | interrupt-parent = <&pic>; | ||
25 | /* These are the logical module IRQs */ | ||
26 | interrupts = <9>, <10>, <11>, <12>; | ||
24 | }; | 27 | }; |
25 | 28 | ||
26 | timer0: timer@13000000 { | 29 | timer0: timer@13000000 { |
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 72693a69f830..7deb3a3182b4 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts | |||
@@ -13,8 +13,8 @@ | |||
13 | bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; | 13 | bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; |
14 | }; | 14 | }; |
15 | 15 | ||
16 | cpcon { | 16 | syscon { |
17 | /* CP controller registers */ | 17 | compatible = "arm,integrator-cp-syscon"; |
18 | reg = <0xcb000000 0x100>; | 18 | reg = <0xcb000000 0x100>; |
19 | }; | 19 | }; |
20 | 20 | ||
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi new file mode 100644 index 000000000000..d6713b113258 --- /dev/null +++ b/arch/arm/boot/dts/keystone-clocks.dtsi | |||
@@ -0,0 +1,821 @@ | |||
1 | /* | ||
2 | * Device Tree Source for Keystone 2 clock tree | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | clocks { | ||
12 | #address-cells = <1>; | ||
13 | #size-cells = <1>; | ||
14 | ranges; | ||
15 | |||
16 | refclkmain: refclkmain { | ||
17 | #clock-cells = <0>; | ||
18 | compatible = "fixed-clock"; | ||
19 | clock-frequency = <122880000>; | ||
20 | clock-output-names = "refclk-main"; | ||
21 | }; | ||
22 | |||
23 | mainpllclk: mainpllclk@2310110 { | ||
24 | #clock-cells = <0>; | ||
25 | compatible = "ti,keystone,main-pll-clock"; | ||
26 | clocks = <&refclkmain>; | ||
27 | reg = <0x02620350 4>, <0x02310110 4>; | ||
28 | reg-names = "control", "multiplier"; | ||
29 | fixed-postdiv = <2>; | ||
30 | }; | ||
31 | |||
32 | papllclk: papllclk@2620358 { | ||
33 | #clock-cells = <0>; | ||
34 | compatible = "ti,keystone,pll-clock"; | ||
35 | clocks = <&refclkmain>; | ||
36 | clock-output-names = "pa-pll-clk"; | ||
37 | reg = <0x02620358 4>; | ||
38 | reg-names = "control"; | ||
39 | fixed-postdiv = <6>; | ||
40 | }; | ||
41 | |||
42 | ddr3allclk: ddr3apllclk@2620360 { | ||
43 | #clock-cells = <0>; | ||
44 | compatible = "ti,keystone,pll-clock"; | ||
45 | clocks = <&refclkmain>; | ||
46 | clock-output-names = "ddr-3a-pll-clk"; | ||
47 | reg = <0x02620360 4>; | ||
48 | reg-names = "control"; | ||
49 | fixed-postdiv = <6>; | ||
50 | }; | ||
51 | |||
52 | ddr3bllclk: ddr3bpllclk@2620368 { | ||
53 | #clock-cells = <0>; | ||
54 | compatible = "ti,keystone,pll-clock"; | ||
55 | clocks = <&refclkmain>; | ||
56 | clock-output-names = "ddr-3b-pll-clk"; | ||
57 | reg = <0x02620368 4>; | ||
58 | reg-names = "control"; | ||
59 | fixed-postdiv = <6>; | ||
60 | }; | ||
61 | |||
62 | armpllclk: armpllclk@2620370 { | ||
63 | #clock-cells = <0>; | ||
64 | compatible = "ti,keystone,pll-clock"; | ||
65 | clocks = <&refclkmain>; | ||
66 | clock-output-names = "arm-pll-clk"; | ||
67 | reg = <0x02620370 4>; | ||
68 | reg-names = "control"; | ||
69 | fixed-postdiv = <6>; | ||
70 | }; | ||
71 | |||
72 | mainmuxclk: mainmuxclk@2310108 { | ||
73 | #clock-cells = <0>; | ||
74 | compatible = "ti,keystone,pll-mux-clock"; | ||
75 | clocks = <&mainpllclk>, <&refclkmain>; | ||
76 | reg = <0x02310108 4>; | ||
77 | bit-shift = <23>; | ||
78 | bit-mask = <1>; | ||
79 | clock-output-names = "mainmuxclk"; | ||
80 | }; | ||
81 | |||
82 | chipclk1: chipclk1 { | ||
83 | #clock-cells = <0>; | ||
84 | compatible = "fixed-factor-clock"; | ||
85 | clocks = <&mainmuxclk>; | ||
86 | clock-div = <1>; | ||
87 | clock-mult = <1>; | ||
88 | clock-output-names = "chipclk1"; | ||
89 | }; | ||
90 | |||
91 | chipclk1rstiso: chipclk1rstiso { | ||
92 | #clock-cells = <0>; | ||
93 | compatible = "fixed-factor-clock"; | ||
94 | clocks = <&mainmuxclk>; | ||
95 | clock-div = <1>; | ||
96 | clock-mult = <1>; | ||
97 | clock-output-names = "chipclk1rstiso"; | ||
98 | }; | ||
99 | |||
100 | gemtraceclk: gemtraceclk@2310120 { | ||
101 | #clock-cells = <0>; | ||
102 | compatible = "ti,keystone,pll-divider-clock"; | ||
103 | clocks = <&mainmuxclk>; | ||
104 | reg = <0x02310120 4>; | ||
105 | bit-shift = <0>; | ||
106 | bit-mask = <8>; | ||
107 | clock-output-names = "gemtraceclk"; | ||
108 | }; | ||
109 | |||
110 | chipstmxptclk: chipstmxptclk { | ||
111 | #clock-cells = <0>; | ||
112 | compatible = "ti,keystone,pll-divider-clock"; | ||
113 | clocks = <&mainmuxclk>; | ||
114 | reg = <0x02310164 4>; | ||
115 | bit-shift = <0>; | ||
116 | bit-mask = <8>; | ||
117 | clock-output-names = "chipstmxptclk"; | ||
118 | }; | ||
119 | |||
120 | chipclk12: chipclk12 { | ||
121 | #clock-cells = <0>; | ||
122 | compatible = "fixed-factor-clock"; | ||
123 | clocks = <&chipclk1>; | ||
124 | clock-div = <2>; | ||
125 | clock-mult = <1>; | ||
126 | clock-output-names = "chipclk12"; | ||
127 | }; | ||
128 | |||
129 | chipclk13: chipclk13 { | ||
130 | #clock-cells = <0>; | ||
131 | compatible = "fixed-factor-clock"; | ||
132 | clocks = <&chipclk1>; | ||
133 | clock-div = <3>; | ||
134 | clock-mult = <1>; | ||
135 | clock-output-names = "chipclk13"; | ||
136 | }; | ||
137 | |||
138 | chipclk14: chipclk14 { | ||
139 | #clock-cells = <0>; | ||
140 | compatible = "fixed-factor-clock"; | ||
141 | clocks = <&chipclk1>; | ||
142 | clock-div = <4>; | ||
143 | clock-mult = <1>; | ||
144 | clock-output-names = "chipclk14"; | ||
145 | }; | ||
146 | |||
147 | chipclk16: chipclk16 { | ||
148 | #clock-cells = <0>; | ||
149 | compatible = "fixed-factor-clock"; | ||
150 | clocks = <&chipclk1>; | ||
151 | clock-div = <6>; | ||
152 | clock-mult = <1>; | ||
153 | clock-output-names = "chipclk16"; | ||
154 | }; | ||
155 | |||
156 | chipclk112: chipclk112 { | ||
157 | #clock-cells = <0>; | ||
158 | compatible = "fixed-factor-clock"; | ||
159 | clocks = <&chipclk1>; | ||
160 | clock-div = <12>; | ||
161 | clock-mult = <1>; | ||
162 | clock-output-names = "chipclk112"; | ||
163 | }; | ||
164 | |||
165 | chipclk124: chipclk124 { | ||
166 | #clock-cells = <0>; | ||
167 | compatible = "fixed-factor-clock"; | ||
168 | clocks = <&chipclk1>; | ||
169 | clock-div = <24>; | ||
170 | clock-mult = <1>; | ||
171 | clock-output-names = "chipclk114"; | ||
172 | }; | ||
173 | |||
174 | chipclk1rstiso13: chipclk1rstiso13 { | ||
175 | #clock-cells = <0>; | ||
176 | compatible = "fixed-factor-clock"; | ||
177 | clocks = <&chipclk1rstiso>; | ||
178 | clock-div = <3>; | ||
179 | clock-mult = <1>; | ||
180 | clock-output-names = "chipclk1rstiso13"; | ||
181 | }; | ||
182 | |||
183 | chipclk1rstiso14: chipclk1rstiso14 { | ||
184 | #clock-cells = <0>; | ||
185 | compatible = "fixed-factor-clock"; | ||
186 | clocks = <&chipclk1rstiso>; | ||
187 | clock-div = <4>; | ||
188 | clock-mult = <1>; | ||
189 | clock-output-names = "chipclk1rstiso14"; | ||
190 | }; | ||
191 | |||
192 | chipclk1rstiso16: chipclk1rstiso16 { | ||
193 | #clock-cells = <0>; | ||
194 | compatible = "fixed-factor-clock"; | ||
195 | clocks = <&chipclk1rstiso>; | ||
196 | clock-div = <6>; | ||
197 | clock-mult = <1>; | ||
198 | clock-output-names = "chipclk1rstiso16"; | ||
199 | }; | ||
200 | |||
201 | chipclk1rstiso112: chipclk1rstiso112 { | ||
202 | #clock-cells = <0>; | ||
203 | compatible = "fixed-factor-clock"; | ||
204 | clocks = <&chipclk1rstiso>; | ||
205 | clock-div = <12>; | ||
206 | clock-mult = <1>; | ||
207 | clock-output-names = "chipclk1rstiso112"; | ||
208 | }; | ||
209 | |||
210 | clkmodrst0: clkmodrst0 { | ||
211 | #clock-cells = <0>; | ||
212 | compatible = "ti,keystone,psc-clock"; | ||
213 | clocks = <&chipclk16>; | ||
214 | clock-output-names = "modrst0"; | ||
215 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
216 | reg-names = "control", "domain"; | ||
217 | domain-id = <0>; | ||
218 | }; | ||
219 | |||
220 | |||
221 | clkusb: clkusb { | ||
222 | #clock-cells = <0>; | ||
223 | compatible = "ti,keystone,psc-clock"; | ||
224 | clocks = <&chipclk16>; | ||
225 | clock-output-names = "usb"; | ||
226 | reg = <0x02350008 0xb00>, <0x02350000 0x400>; | ||
227 | reg-names = "control", "domain"; | ||
228 | domain-id = <0>; | ||
229 | }; | ||
230 | |||
231 | clkaemifspi: clkaemifspi { | ||
232 | #clock-cells = <0>; | ||
233 | compatible = "ti,keystone,psc-clock"; | ||
234 | clocks = <&chipclk16>; | ||
235 | clock-output-names = "aemif-spi"; | ||
236 | reg = <0x0235000c 0xb00>, <0x02350000 0x400>; | ||
237 | reg-names = "control", "domain"; | ||
238 | domain-id = <0>; | ||
239 | }; | ||
240 | |||
241 | |||
242 | clkdebugsstrc: clkdebugsstrc { | ||
243 | #clock-cells = <0>; | ||
244 | compatible = "ti,keystone,psc-clock"; | ||
245 | clocks = <&chipclk13>; | ||
246 | clock-output-names = "debugss-trc"; | ||
247 | reg = <0x02350014 0xb00>, <0x02350000 0x400>; | ||
248 | reg-names = "control", "domain"; | ||
249 | domain-id = <0>; | ||
250 | }; | ||
251 | |||
252 | clktetbtrc: clktetbtrc { | ||
253 | #clock-cells = <0>; | ||
254 | compatible = "ti,keystone,psc-clock"; | ||
255 | clocks = <&chipclk13>; | ||
256 | clock-output-names = "tetb-trc"; | ||
257 | reg = <0x02350018 0xb00>, <0x02350004 0x400>; | ||
258 | reg-names = "control", "domain"; | ||
259 | domain-id = <1>; | ||
260 | }; | ||
261 | |||
262 | clkpa: clkpa { | ||
263 | #clock-cells = <0>; | ||
264 | compatible = "ti,keystone,psc-clock"; | ||
265 | clocks = <&chipclk16>; | ||
266 | clock-output-names = "pa"; | ||
267 | reg = <0x0235001c 0xb00>, <0x02350008 0x400>; | ||
268 | reg-names = "control", "domain"; | ||
269 | domain-id = <2>; | ||
270 | }; | ||
271 | |||
272 | clkcpgmac: clkcpgmac { | ||
273 | #clock-cells = <0>; | ||
274 | compatible = "ti,keystone,psc-clock"; | ||
275 | clocks = <&clkpa>; | ||
276 | clock-output-names = "cpgmac"; | ||
277 | reg = <0x02350020 0xb00>, <0x02350008 0x400>; | ||
278 | reg-names = "control", "domain"; | ||
279 | domain-id = <2>; | ||
280 | }; | ||
281 | |||
282 | clksa: clksa { | ||
283 | #clock-cells = <0>; | ||
284 | compatible = "ti,keystone,psc-clock"; | ||
285 | clocks = <&clkpa>; | ||
286 | clock-output-names = "sa"; | ||
287 | reg = <0x02350024 0xb00>, <0x02350008 0x400>; | ||
288 | reg-names = "control", "domain"; | ||
289 | domain-id = <2>; | ||
290 | }; | ||
291 | |||
292 | clkpcie: clkpcie { | ||
293 | #clock-cells = <0>; | ||
294 | compatible = "ti,keystone,psc-clock"; | ||
295 | clocks = <&chipclk12>; | ||
296 | clock-output-names = "pcie"; | ||
297 | reg = <0x02350028 0xb00>, <0x0235000c 0x400>; | ||
298 | reg-names = "control", "domain"; | ||
299 | domain-id = <3>; | ||
300 | }; | ||
301 | |||
302 | clksrio: clksrio { | ||
303 | #clock-cells = <0>; | ||
304 | compatible = "ti,keystone,psc-clock"; | ||
305 | clocks = <&chipclk1rstiso13>; | ||
306 | clock-output-names = "srio"; | ||
307 | reg = <0x0235002c 0xb00>, <0x02350010 0x400>; | ||
308 | reg-names = "control", "domain"; | ||
309 | domain-id = <4>; | ||
310 | }; | ||
311 | |||
312 | clkhyperlink0: clkhyperlink0 { | ||
313 | #clock-cells = <0>; | ||
314 | compatible = "ti,keystone,psc-clock"; | ||
315 | clocks = <&chipclk12>; | ||
316 | clock-output-names = "hyperlink-0"; | ||
317 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | ||
318 | reg-names = "control", "domain"; | ||
319 | domain-id = <5>; | ||
320 | }; | ||
321 | |||
322 | clksr: clksr { | ||
323 | #clock-cells = <0>; | ||
324 | compatible = "ti,keystone,psc-clock"; | ||
325 | clocks = <&chipclk1rstiso112>; | ||
326 | clock-output-names = "sr"; | ||
327 | reg = <0x02350034 0xb00>, <0x02350018 0x400>; | ||
328 | reg-names = "control", "domain"; | ||
329 | domain-id = <6>; | ||
330 | }; | ||
331 | |||
332 | clkmsmcsram: clkmsmcsram { | ||
333 | #clock-cells = <0>; | ||
334 | compatible = "ti,keystone,psc-clock"; | ||
335 | clocks = <&chipclk1>; | ||
336 | clock-output-names = "msmcsram"; | ||
337 | reg = <0x02350038 0xb00>, <0x0235001c 0x400>; | ||
338 | reg-names = "control", "domain"; | ||
339 | domain-id = <7>; | ||
340 | }; | ||
341 | |||
342 | clkgem0: clkgem0 { | ||
343 | #clock-cells = <0>; | ||
344 | compatible = "ti,keystone,psc-clock"; | ||
345 | clocks = <&chipclk1>; | ||
346 | clock-output-names = "gem0"; | ||
347 | reg = <0x0235003c 0xb00>, <0x02350020 0x400>; | ||
348 | reg-names = "control", "domain"; | ||
349 | domain-id = <8>; | ||
350 | }; | ||
351 | |||
352 | clkgem1: clkgem1 { | ||
353 | #clock-cells = <0>; | ||
354 | compatible = "ti,keystone,psc-clock"; | ||
355 | clocks = <&chipclk1>; | ||
356 | clock-output-names = "gem1"; | ||
357 | reg = <0x02350040 0xb00>, <0x02350024 0x400>; | ||
358 | reg-names = "control", "domain"; | ||
359 | domain-id = <9>; | ||
360 | }; | ||
361 | |||
362 | clkgem2: clkgem2 { | ||
363 | #clock-cells = <0>; | ||
364 | compatible = "ti,keystone,psc-clock"; | ||
365 | clocks = <&chipclk1>; | ||
366 | clock-output-names = "gem2"; | ||
367 | reg = <0x02350044 0xb00>, <0x02350028 0x400>; | ||
368 | reg-names = "control", "domain"; | ||
369 | domain-id = <10>; | ||
370 | }; | ||
371 | |||
372 | clkgem3: clkgem3 { | ||
373 | #clock-cells = <0>; | ||
374 | compatible = "ti,keystone,psc-clock"; | ||
375 | clocks = <&chipclk1>; | ||
376 | clock-output-names = "gem3"; | ||
377 | reg = <0x02350048 0xb00>, <0x0235002c 0x400>; | ||
378 | reg-names = "control", "domain"; | ||
379 | domain-id = <11>; | ||
380 | }; | ||
381 | |||
382 | clkgem4: clkgem4 { | ||
383 | #clock-cells = <0>; | ||
384 | compatible = "ti,keystone,psc-clock"; | ||
385 | clocks = <&chipclk1>; | ||
386 | clock-output-names = "gem4"; | ||
387 | reg = <0x0235004c 0xb00>, <0x02350030 0x400>; | ||
388 | reg-names = "control", "domain"; | ||
389 | domain-id = <12>; | ||
390 | }; | ||
391 | |||
392 | clkgem5: clkgem5 { | ||
393 | #clock-cells = <0>; | ||
394 | compatible = "ti,keystone,psc-clock"; | ||
395 | clocks = <&chipclk1>; | ||
396 | clock-output-names = "gem5"; | ||
397 | reg = <0x02350050 0xb00>, <0x02350034 0x400>; | ||
398 | reg-names = "control", "domain"; | ||
399 | domain-id = <13>; | ||
400 | }; | ||
401 | |||
402 | clkgem6: clkgem6 { | ||
403 | #clock-cells = <0>; | ||
404 | compatible = "ti,keystone,psc-clock"; | ||
405 | clocks = <&chipclk1>; | ||
406 | clock-output-names = "gem6"; | ||
407 | reg = <0x02350054 0xb00>, <0x02350038 0x400>; | ||
408 | reg-names = "control", "domain"; | ||
409 | domain-id = <14>; | ||
410 | }; | ||
411 | |||
412 | clkgem7: clkgem7 { | ||
413 | #clock-cells = <0>; | ||
414 | compatible = "ti,keystone,psc-clock"; | ||
415 | clocks = <&chipclk1>; | ||
416 | clock-output-names = "gem7"; | ||
417 | reg = <0x02350058 0xb00>, <0x0235003c 0x400>; | ||
418 | reg-names = "control", "domain"; | ||
419 | domain-id = <15>; | ||
420 | }; | ||
421 | |||
422 | clkddr30: clkddr30 { | ||
423 | #clock-cells = <0>; | ||
424 | compatible = "ti,keystone,psc-clock"; | ||
425 | clocks = <&chipclk12>; | ||
426 | clock-output-names = "ddr3-0"; | ||
427 | reg = <0x0235005c 0xb00>, <0x02350040 0x400>; | ||
428 | reg-names = "control", "domain"; | ||
429 | domain-id = <16>; | ||
430 | }; | ||
431 | |||
432 | clkddr31: clkddr31 { | ||
433 | #clock-cells = <0>; | ||
434 | compatible = "ti,keystone,psc-clock"; | ||
435 | clocks = <&chipclk13>; | ||
436 | clock-output-names = "ddr3-1"; | ||
437 | reg = <0x02350060 0xb00>, <0x02350040 0x400>; | ||
438 | reg-names = "control", "domain"; | ||
439 | domain-id = <16>; | ||
440 | }; | ||
441 | |||
442 | clktac: clktac { | ||
443 | #clock-cells = <0>; | ||
444 | compatible = "ti,keystone,psc-clock"; | ||
445 | clocks = <&chipclk13>; | ||
446 | clock-output-names = "tac"; | ||
447 | reg = <0x02350064 0xb00>, <0x02350044 0x400>; | ||
448 | reg-names = "control", "domain"; | ||
449 | domain-id = <17>; | ||
450 | }; | ||
451 | |||
452 | clkrac01: clktac01 { | ||
453 | #clock-cells = <0>; | ||
454 | compatible = "ti,keystone,psc-clock"; | ||
455 | clocks = <&chipclk13>; | ||
456 | clock-output-names = "rac-01"; | ||
457 | reg = <0x02350068 0xb00>, <0x02350044 0x400>; | ||
458 | reg-names = "control", "domain"; | ||
459 | domain-id = <17>; | ||
460 | }; | ||
461 | |||
462 | clkrac23: clktac23 { | ||
463 | #clock-cells = <0>; | ||
464 | compatible = "ti,keystone,psc-clock"; | ||
465 | clocks = <&chipclk13>; | ||
466 | clock-output-names = "rac-23"; | ||
467 | reg = <0x0235006c 0xb00>, <0x02350048 0x400>; | ||
468 | reg-names = "control", "domain"; | ||
469 | domain-id = <18>; | ||
470 | }; | ||
471 | |||
472 | clkfftc0: clkfftc0 { | ||
473 | #clock-cells = <0>; | ||
474 | compatible = "ti,keystone,psc-clock"; | ||
475 | clocks = <&chipclk13>; | ||
476 | clock-output-names = "fftc-0"; | ||
477 | reg = <0x02350070 0xb00>, <0x0235004c 0x400>; | ||
478 | reg-names = "control", "domain"; | ||
479 | domain-id = <19>; | ||
480 | }; | ||
481 | |||
482 | clkfftc1: clkfftc1 { | ||
483 | #clock-cells = <0>; | ||
484 | compatible = "ti,keystone,psc-clock"; | ||
485 | clocks = <&chipclk13>; | ||
486 | clock-output-names = "fftc-1"; | ||
487 | reg = <0x02350074 0xb00>, <0x023504c0 0x400>; | ||
488 | reg-names = "control", "domain"; | ||
489 | domain-id = <19>; | ||
490 | }; | ||
491 | |||
492 | clkfftc2: clkfftc2 { | ||
493 | #clock-cells = <0>; | ||
494 | compatible = "ti,keystone,psc-clock"; | ||
495 | clocks = <&chipclk13>; | ||
496 | clock-output-names = "fftc-2"; | ||
497 | reg = <0x02350078 0xb00>, <0x02350050 0x400>; | ||
498 | reg-names = "control", "domain"; | ||
499 | domain-id = <20>; | ||
500 | }; | ||
501 | |||
502 | clkfftc3: clkfftc3 { | ||
503 | #clock-cells = <0>; | ||
504 | compatible = "ti,keystone,psc-clock"; | ||
505 | clocks = <&chipclk13>; | ||
506 | clock-output-names = "fftc-3"; | ||
507 | reg = <0x0235007c 0xb00>, <0x02350050 0x400>; | ||
508 | reg-names = "control", "domain"; | ||
509 | domain-id = <20>; | ||
510 | }; | ||
511 | |||
512 | clkfftc4: clkfftc4 { | ||
513 | #clock-cells = <0>; | ||
514 | compatible = "ti,keystone,psc-clock"; | ||
515 | clocks = <&chipclk13>; | ||
516 | clock-output-names = "fftc-4"; | ||
517 | reg = <0x02350080 0xb00>, <0x02350050 0x400>; | ||
518 | reg-names = "control", "domain"; | ||
519 | domain-id = <20>; | ||
520 | }; | ||
521 | |||
522 | clkfftc5: clkfftc5 { | ||
523 | #clock-cells = <0>; | ||
524 | compatible = "ti,keystone,psc-clock"; | ||
525 | clocks = <&chipclk13>; | ||
526 | clock-output-names = "fftc-5"; | ||
527 | reg = <0x02350084 0xb00>, <0x02350050 0x400>; | ||
528 | reg-names = "control", "domain"; | ||
529 | domain-id = <20>; | ||
530 | }; | ||
531 | |||
532 | clkaif: clkaif { | ||
533 | #clock-cells = <0>; | ||
534 | compatible = "ti,keystone,psc-clock"; | ||
535 | clocks = <&chipclk13>; | ||
536 | clock-output-names = "aif"; | ||
537 | reg = <0x02350088 0xb00>, <0x02350054 0x400>; | ||
538 | reg-names = "control", "domain"; | ||
539 | domain-id = <21>; | ||
540 | }; | ||
541 | |||
542 | clktcp3d0: clktcp3d0 { | ||
543 | #clock-cells = <0>; | ||
544 | compatible = "ti,keystone,psc-clock"; | ||
545 | clocks = <&chipclk13>; | ||
546 | clock-output-names = "tcp3d-0"; | ||
547 | reg = <0x0235008c 0xb00>, <0x02350058 0x400>; | ||
548 | reg-names = "control", "domain"; | ||
549 | domain-id = <22>; | ||
550 | }; | ||
551 | |||
552 | clktcp3d1: clktcp3d1 { | ||
553 | #clock-cells = <0>; | ||
554 | compatible = "ti,keystone,psc-clock"; | ||
555 | clocks = <&chipclk13>; | ||
556 | clock-output-names = "tcp3d-1"; | ||
557 | reg = <0x02350090 0xb00>, <0x02350058 0x400>; | ||
558 | reg-names = "control", "domain"; | ||
559 | domain-id = <22>; | ||
560 | }; | ||
561 | |||
562 | clktcp3d2: clktcp3d2 { | ||
563 | #clock-cells = <0>; | ||
564 | compatible = "ti,keystone,psc-clock"; | ||
565 | clocks = <&chipclk13>; | ||
566 | clock-output-names = "tcp3d-2"; | ||
567 | reg = <0x02350094 0xb00>, <0x0235005c 0x400>; | ||
568 | reg-names = "control", "domain"; | ||
569 | domain-id = <23>; | ||
570 | }; | ||
571 | |||
572 | clktcp3d3: clktcp3d3 { | ||
573 | #clock-cells = <0>; | ||
574 | compatible = "ti,keystone,psc-clock"; | ||
575 | clocks = <&chipclk13>; | ||
576 | clock-output-names = "tcp3d-3"; | ||
577 | reg = <0x02350098 0xb00>, <0x0235005c 0x400>; | ||
578 | reg-names = "control", "domain"; | ||
579 | domain-id = <23>; | ||
580 | }; | ||
581 | |||
582 | clkvcp0: clkvcp0 { | ||
583 | #clock-cells = <0>; | ||
584 | compatible = "ti,keystone,psc-clock"; | ||
585 | clocks = <&chipclk13>; | ||
586 | clock-output-names = "vcp-0"; | ||
587 | reg = <0x0235009c 0xb00>, <0x02350060 0x400>; | ||
588 | reg-names = "control", "domain"; | ||
589 | domain-id = <24>; | ||
590 | }; | ||
591 | |||
592 | clkvcp1: clkvcp1 { | ||
593 | #clock-cells = <0>; | ||
594 | compatible = "ti,keystone,psc-clock"; | ||
595 | clocks = <&chipclk13>; | ||
596 | clock-output-names = "vcp-1"; | ||
597 | reg = <0x023500a0 0xb00>, <0x02350060 0x400>; | ||
598 | reg-names = "control", "domain"; | ||
599 | domain-id = <24>; | ||
600 | }; | ||
601 | |||
602 | clkvcp2: clkvcp2 { | ||
603 | #clock-cells = <0>; | ||
604 | compatible = "ti,keystone,psc-clock"; | ||
605 | clocks = <&chipclk13>; | ||
606 | clock-output-names = "vcp-2"; | ||
607 | reg = <0x023500a4 0xb00>, <0x02350060 0x400>; | ||
608 | reg-names = "control", "domain"; | ||
609 | domain-id = <24>; | ||
610 | }; | ||
611 | |||
612 | clkvcp3: clkvcp3 { | ||
613 | #clock-cells = <0>; | ||
614 | compatible = "ti,keystone,psc-clock"; | ||
615 | clocks = <&chipclk13>; | ||
616 | clock-output-names = "vcp-3"; | ||
617 | reg = <0x0235000a8 0xb00>, <0x02350060 0x400>; | ||
618 | reg-names = "control", "domain"; | ||
619 | domain-id = <24>; | ||
620 | }; | ||
621 | |||
622 | clkvcp4: clkvcp4 { | ||
623 | #clock-cells = <0>; | ||
624 | compatible = "ti,keystone,psc-clock"; | ||
625 | clocks = <&chipclk13>; | ||
626 | clock-output-names = "vcp-4"; | ||
627 | reg = <0x023500ac 0xb00>, <0x02350064 0x400>; | ||
628 | reg-names = "control", "domain"; | ||
629 | domain-id = <25>; | ||
630 | }; | ||
631 | |||
632 | clkvcp5: clkvcp5 { | ||
633 | #clock-cells = <0>; | ||
634 | compatible = "ti,keystone,psc-clock"; | ||
635 | clocks = <&chipclk13>; | ||
636 | clock-output-names = "vcp-5"; | ||
637 | reg = <0x023500b0 0xb00>, <0x02350064 0x400>; | ||
638 | reg-names = "control", "domain"; | ||
639 | domain-id = <25>; | ||
640 | }; | ||
641 | |||
642 | clkvcp6: clkvcp6 { | ||
643 | #clock-cells = <0>; | ||
644 | compatible = "ti,keystone,psc-clock"; | ||
645 | clocks = <&chipclk13>; | ||
646 | clock-output-names = "vcp-6"; | ||
647 | reg = <0x023500b4 0xb00>, <0x02350064 0x400>; | ||
648 | reg-names = "control", "domain"; | ||
649 | domain-id = <25>; | ||
650 | }; | ||
651 | |||
652 | clkvcp7: clkvcp7 { | ||
653 | #clock-cells = <0>; | ||
654 | compatible = "ti,keystone,psc-clock"; | ||
655 | clocks = <&chipclk13>; | ||
656 | clock-output-names = "vcp-7"; | ||
657 | reg = <0x023500b8 0xb00>, <0x02350064 0x400>; | ||
658 | reg-names = "control", "domain"; | ||
659 | domain-id = <25>; | ||
660 | }; | ||
661 | |||
662 | clkbcp: clkbcp { | ||
663 | #clock-cells = <0>; | ||
664 | compatible = "ti,keystone,psc-clock"; | ||
665 | clocks = <&chipclk13>; | ||
666 | clock-output-names = "bcp"; | ||
667 | reg = <0x023500bc 0xb00>, <0x02350068 0x400>; | ||
668 | reg-names = "control", "domain"; | ||
669 | domain-id = <26>; | ||
670 | }; | ||
671 | |||
672 | clkdxb: clkdxb { | ||
673 | #clock-cells = <0>; | ||
674 | compatible = "ti,keystone,psc-clock"; | ||
675 | clocks = <&chipclk13>; | ||
676 | clock-output-names = "dxb"; | ||
677 | reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; | ||
678 | reg-names = "control", "domain"; | ||
679 | domain-id = <27>; | ||
680 | }; | ||
681 | |||
682 | clkhyperlink1: clkhyperlink1 { | ||
683 | #clock-cells = <0>; | ||
684 | compatible = "ti,keystone,psc-clock"; | ||
685 | clocks = <&chipclk12>; | ||
686 | clock-output-names = "hyperlink-1"; | ||
687 | reg = <0x023500c4 0xb00>, <0x02350070 0x400>; | ||
688 | reg-names = "control", "domain"; | ||
689 | domain-id = <28>; | ||
690 | }; | ||
691 | |||
692 | clkxge: clkxge { | ||
693 | #clock-cells = <0>; | ||
694 | compatible = "ti,keystone,psc-clock"; | ||
695 | clocks = <&chipclk13>; | ||
696 | clock-output-names = "xge"; | ||
697 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | ||
698 | reg-names = "control", "domain"; | ||
699 | domain-id = <29>; | ||
700 | }; | ||
701 | |||
702 | clkwdtimer0: clkwdtimer0 { | ||
703 | #clock-cells = <0>; | ||
704 | compatible = "ti,keystone,psc-clock"; | ||
705 | clocks = <&clkmodrst0>; | ||
706 | clock-output-names = "timer0"; | ||
707 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
708 | reg-names = "control", "domain"; | ||
709 | domain-id = <0>; | ||
710 | }; | ||
711 | |||
712 | clkwdtimer1: clkwdtimer1 { | ||
713 | #clock-cells = <0>; | ||
714 | compatible = "ti,keystone,psc-clock"; | ||
715 | clocks = <&clkmodrst0>; | ||
716 | clock-output-names = "timer1"; | ||
717 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
718 | reg-names = "control", "domain"; | ||
719 | domain-id = <0>; | ||
720 | }; | ||
721 | |||
722 | clkwdtimer2: clkwdtimer2 { | ||
723 | #clock-cells = <0>; | ||
724 | compatible = "ti,keystone,psc-clock"; | ||
725 | clocks = <&clkmodrst0>; | ||
726 | clock-output-names = "timer2"; | ||
727 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
728 | reg-names = "control", "domain"; | ||
729 | domain-id = <0>; | ||
730 | }; | ||
731 | |||
732 | clkwdtimer3: clkwdtimer3 { | ||
733 | #clock-cells = <0>; | ||
734 | compatible = "ti,keystone,psc-clock"; | ||
735 | clocks = <&clkmodrst0>; | ||
736 | clock-output-names = "timer3"; | ||
737 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
738 | reg-names = "control", "domain"; | ||
739 | domain-id = <0>; | ||
740 | }; | ||
741 | |||
742 | clkuart0: clkuart0 { | ||
743 | #clock-cells = <0>; | ||
744 | compatible = "ti,keystone,psc-clock"; | ||
745 | clocks = <&clkmodrst0>; | ||
746 | clock-output-names = "uart0"; | ||
747 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
748 | reg-names = "control", "domain"; | ||
749 | domain-id = <0>; | ||
750 | }; | ||
751 | |||
752 | clkuart1: clkuart1 { | ||
753 | #clock-cells = <0>; | ||
754 | compatible = "ti,keystone,psc-clock"; | ||
755 | clocks = <&clkmodrst0>; | ||
756 | clock-output-names = "uart1"; | ||
757 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
758 | reg-names = "control", "domain"; | ||
759 | domain-id = <0>; | ||
760 | }; | ||
761 | |||
762 | clkaemif: clkaemif { | ||
763 | #clock-cells = <0>; | ||
764 | compatible = "ti,keystone,psc-clock"; | ||
765 | clocks = <&clkaemifspi>; | ||
766 | clock-output-names = "aemif"; | ||
767 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
768 | reg-names = "control", "domain"; | ||
769 | domain-id = <0>; | ||
770 | }; | ||
771 | |||
772 | clkusim: clkusim { | ||
773 | #clock-cells = <0>; | ||
774 | compatible = "ti,keystone,psc-clock"; | ||
775 | clocks = <&clkmodrst0>; | ||
776 | clock-output-names = "usim"; | ||
777 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
778 | reg-names = "control", "domain"; | ||
779 | domain-id = <0>; | ||
780 | }; | ||
781 | |||
782 | clki2c: clki2c { | ||
783 | #clock-cells = <0>; | ||
784 | compatible = "ti,keystone,psc-clock"; | ||
785 | clocks = <&clkmodrst0>; | ||
786 | clock-output-names = "i2c"; | ||
787 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
788 | reg-names = "control", "domain"; | ||
789 | domain-id = <0>; | ||
790 | }; | ||
791 | |||
792 | clkspi: clkspi { | ||
793 | #clock-cells = <0>; | ||
794 | compatible = "ti,keystone,psc-clock"; | ||
795 | clocks = <&clkaemifspi>; | ||
796 | clock-output-names = "spi"; | ||
797 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
798 | reg-names = "control", "domain"; | ||
799 | domain-id = <0>; | ||
800 | }; | ||
801 | |||
802 | clkgpio: clkgpio { | ||
803 | #clock-cells = <0>; | ||
804 | compatible = "ti,keystone,psc-clock"; | ||
805 | clocks = <&clkmodrst0>; | ||
806 | clock-output-names = "gpio"; | ||
807 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
808 | reg-names = "control", "domain"; | ||
809 | domain-id = <0>; | ||
810 | }; | ||
811 | |||
812 | clkkeymgr: clkkeymgr { | ||
813 | #clock-cells = <0>; | ||
814 | compatible = "ti,keystone,psc-clock"; | ||
815 | clocks = <&clkmodrst0>; | ||
816 | clock-output-names = "keymgr"; | ||
817 | reg = <0x02350000 0xb00>, <0x02350000 0x400>; | ||
818 | reg-names = "control", "domain"; | ||
819 | domain-id = <0>; | ||
820 | }; | ||
821 | }; | ||
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts index a68e34bbecb2..100bdf52b847 100644 --- a/arch/arm/boot/dts/keystone.dts +++ b/arch/arm/boot/dts/keystone.dts | |||
@@ -100,13 +100,15 @@ | |||
100 | reg = <0x023100e8 4>; /* pll reset control reg */ | 100 | reg = <0x023100e8 4>; /* pll reset control reg */ |
101 | }; | 101 | }; |
102 | 102 | ||
103 | /include/ "keystone-clocks.dtsi" | ||
104 | |||
103 | uart0: serial@02530c00 { | 105 | uart0: serial@02530c00 { |
104 | compatible = "ns16550a"; | 106 | compatible = "ns16550a"; |
105 | current-speed = <115200>; | 107 | current-speed = <115200>; |
106 | reg-shift = <2>; | 108 | reg-shift = <2>; |
107 | reg-io-width = <4>; | 109 | reg-io-width = <4>; |
108 | reg = <0x02530c00 0x100>; | 110 | reg = <0x02530c00 0x100>; |
109 | clock-frequency = <133120000>; | 111 | clocks = <&clkuart0>; |
110 | interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; | 112 | interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; |
111 | }; | 113 | }; |
112 | 114 | ||
@@ -116,9 +118,66 @@ | |||
116 | reg-shift = <2>; | 118 | reg-shift = <2>; |
117 | reg-io-width = <4>; | 119 | reg-io-width = <4>; |
118 | reg = <0x02531000 0x100>; | 120 | reg = <0x02531000 0x100>; |
119 | clock-frequency = <133120000>; | 121 | clocks = <&clkuart1>; |
120 | interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; | 122 | interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; |
121 | }; | 123 | }; |
122 | 124 | ||
125 | i2c0: i2c@2530000 { | ||
126 | compatible = "ti,davinci-i2c"; | ||
127 | reg = <0x02530000 0x400>; | ||
128 | clock-frequency = <100000>; | ||
129 | clocks = <&clki2c>; | ||
130 | interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; | ||
131 | #address-cells = <1>; | ||
132 | #size-cells = <0>; | ||
133 | |||
134 | dtt@50 { | ||
135 | compatible = "at,24c1024"; | ||
136 | reg = <0x50>; | ||
137 | }; | ||
138 | }; | ||
139 | |||
140 | i2c1: i2c@2530400 { | ||
141 | compatible = "ti,davinci-i2c"; | ||
142 | reg = <0x02530400 0x400>; | ||
143 | clock-frequency = <100000>; | ||
144 | clocks = <&clki2c>; | ||
145 | interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; | ||
146 | }; | ||
147 | |||
148 | i2c2: i2c@2530800 { | ||
149 | compatible = "ti,davinci-i2c"; | ||
150 | reg = <0x02530800 0x400>; | ||
151 | clock-frequency = <100000>; | ||
152 | clocks = <&clki2c>; | ||
153 | interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; | ||
154 | }; | ||
155 | |||
156 | spi0: spi@21000400 { | ||
157 | compatible = "ti,dm6441-spi"; | ||
158 | reg = <0x21000400 0x200>; | ||
159 | num-cs = <4>; | ||
160 | ti,davinci-spi-intr-line = <0>; | ||
161 | interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; | ||
162 | clocks = <&clkspi>; | ||
163 | }; | ||
164 | |||
165 | spi1: spi@21000600 { | ||
166 | compatible = "ti,dm6441-spi"; | ||
167 | reg = <0x21000600 0x200>; | ||
168 | num-cs = <4>; | ||
169 | ti,davinci-spi-intr-line = <0>; | ||
170 | interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; | ||
171 | clocks = <&clkspi>; | ||
172 | }; | ||
173 | |||
174 | spi2: spi@21000800 { | ||
175 | compatible = "ti,dm6441-spi"; | ||
176 | reg = <0x21000800 0x200>; | ||
177 | num-cs = <4>; | ||
178 | ti,davinci-spi-intr-line = <0>; | ||
179 | interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; | ||
180 | clocks = <&clkspi>; | ||
181 | }; | ||
123 | }; | 182 | }; |
124 | }; | 183 | }; |
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi new file mode 100644 index 000000000000..46b82aa7dc4e --- /dev/null +++ b/arch/arm/boot/dts/r7s72100.dtsi | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * Device Tree Source for the r7s72100 SoC | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | / { | ||
12 | compatible = "renesas,r7s72100"; | ||
13 | interrupt-parent = <&gic>; | ||
14 | #address-cells = <1>; | ||
15 | #size-cells = <1>; | ||
16 | |||
17 | cpus { | ||
18 | #address-cells = <1>; | ||
19 | #size-cells = <0>; | ||
20 | |||
21 | cpu@0 { | ||
22 | device_type = "cpu"; | ||
23 | compatible = "arm,cortex-a9"; | ||
24 | reg = <0>; | ||
25 | }; | ||
26 | }; | ||
27 | |||
28 | gic: interrupt-controller@e8201000 { | ||
29 | compatible = "arm,cortex-a9-gic"; | ||
30 | #interrupt-cells = <3>; | ||
31 | #address-cells = <0>; | ||
32 | interrupt-controller; | ||
33 | reg = <0xe8201000 0x1000>, | ||
34 | <0xe8202000 0x1000>; | ||
35 | }; | ||
36 | }; | ||
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi new file mode 100644 index 000000000000..bbed43bd9be9 --- /dev/null +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Device Tree Source for the r8a7791 SoC | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Electronics Corporation | ||
5 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public License | ||
8 | * version 2. This program is licensed "as is" without any warranty of any | ||
9 | * kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | / { | ||
13 | compatible = "renesas,r8a7791"; | ||
14 | interrupt-parent = <&gic>; | ||
15 | #address-cells = <2>; | ||
16 | #size-cells = <2>; | ||
17 | |||
18 | cpus { | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | |||
22 | cpu0: cpu@0 { | ||
23 | device_type = "cpu"; | ||
24 | compatible = "arm,cortex-a15"; | ||
25 | reg = <0>; | ||
26 | clock-frequency = <1300000000>; | ||
27 | }; | ||
28 | }; | ||
29 | |||
30 | gic: interrupt-controller@f1001000 { | ||
31 | compatible = "arm,cortex-a15-gic"; | ||
32 | #interrupt-cells = <3>; | ||
33 | #address-cells = <0>; | ||
34 | interrupt-controller; | ||
35 | reg = <0 0xf1001000 0 0x1000>, | ||
36 | <0 0xf1002000 0 0x1000>, | ||
37 | <0 0xf1004000 0 0x2000>, | ||
38 | <0 0xf1006000 0 0x2000>; | ||
39 | interrupts = <1 9 0xf04>; | ||
40 | }; | ||
41 | }; | ||
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 6e4931097dd4..287ac1d7aac7 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig | |||
@@ -1,4 +1,3 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
3 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
4 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
@@ -25,10 +24,9 @@ CONFIG_MODULES=y | |||
25 | CONFIG_MODULE_UNLOAD=y | 24 | CONFIG_MODULE_UNLOAD=y |
26 | # CONFIG_BLK_DEV_BSG is not set | 25 | # CONFIG_BLK_DEV_BSG is not set |
27 | CONFIG_PARTITION_ADVANCED=y | 26 | CONFIG_PARTITION_ADVANCED=y |
28 | CONFIG_EFI_PARTITION=y | ||
29 | CONFIG_ARCH_BCM=y | 27 | CONFIG_ARCH_BCM=y |
28 | CONFIG_ARCH_BCM_MOBILE=y | ||
30 | CONFIG_ARM_THUMBEE=y | 29 | CONFIG_ARM_THUMBEE=y |
31 | CONFIG_ARM_ERRATA_743622=y | ||
32 | CONFIG_PREEMPT=y | 30 | CONFIG_PREEMPT=y |
33 | CONFIG_AEABI=y | 31 | CONFIG_AEABI=y |
34 | # CONFIG_OABI_COMPAT is not set | 32 | # CONFIG_OABI_COMPAT is not set |
@@ -50,7 +48,6 @@ CONFIG_UNIX_DIAG=y | |||
50 | CONFIG_NET_KEY=y | 48 | CONFIG_NET_KEY=y |
51 | CONFIG_INET=y | 49 | CONFIG_INET=y |
52 | CONFIG_IP_MULTICAST=y | 50 | CONFIG_IP_MULTICAST=y |
53 | CONFIG_ARPD=y | ||
54 | CONFIG_SYN_COOKIES=y | 51 | CONFIG_SYN_COOKIES=y |
55 | CONFIG_TCP_MD5SIG=y | 52 | CONFIG_TCP_MD5SIG=y |
56 | CONFIG_IPV6=y | 53 | CONFIG_IPV6=y |
@@ -95,7 +92,6 @@ CONFIG_MMC_UNSAFE_RESUME=y | |||
95 | CONFIG_MMC_BLOCK_MINORS=32 | 92 | CONFIG_MMC_BLOCK_MINORS=32 |
96 | CONFIG_MMC_TEST=y | 93 | CONFIG_MMC_TEST=y |
97 | CONFIG_MMC_SDHCI=y | 94 | CONFIG_MMC_SDHCI=y |
98 | CONFIG_MMC_SDHCI_PLTFM=y | ||
99 | CONFIG_MMC_SDHCI_BCM_KONA=y | 95 | CONFIG_MMC_SDHCI_BCM_KONA=y |
100 | CONFIG_NEW_LEDS=y | 96 | CONFIG_NEW_LEDS=y |
101 | CONFIG_LEDS_CLASS=y | 97 | CONFIG_LEDS_CLASS=y |
@@ -117,12 +113,12 @@ CONFIG_CONFIGFS_FS=y | |||
117 | CONFIG_NLS_CODEPAGE_437=y | 113 | CONFIG_NLS_CODEPAGE_437=y |
118 | CONFIG_NLS_ISO8859_1=y | 114 | CONFIG_NLS_ISO8859_1=y |
119 | CONFIG_PRINTK_TIME=y | 115 | CONFIG_PRINTK_TIME=y |
120 | CONFIG_MAGIC_SYSRQ=y | 116 | CONFIG_DEBUG_INFO=y |
121 | CONFIG_DEBUG_FS=y | 117 | CONFIG_DEBUG_FS=y |
118 | CONFIG_MAGIC_SYSRQ=y | ||
122 | CONFIG_DETECT_HUNG_TASK=y | 119 | CONFIG_DETECT_HUNG_TASK=y |
123 | CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 | 120 | CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 |
124 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y | 121 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y |
125 | CONFIG_DEBUG_INFO=y | ||
126 | # CONFIG_FTRACE is not set | 122 | # CONFIG_FTRACE is not set |
127 | CONFIG_CRC_CCITT=y | 123 | CONFIG_CRC_CCITT=y |
128 | CONFIG_CRC_T10DIF=y | 124 | CONFIG_CRC_T10DIF=y |
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 5d488c24b132..8d0c5a018ed7 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
@@ -132,7 +132,6 @@ CONFIG_TOUCHSCREEN_MC13783=y | |||
132 | CONFIG_INPUT_MISC=y | 132 | CONFIG_INPUT_MISC=y |
133 | CONFIG_INPUT_MMA8450=y | 133 | CONFIG_INPUT_MMA8450=y |
134 | CONFIG_SERIO_SERPORT=m | 134 | CONFIG_SERIO_SERPORT=m |
135 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
136 | # CONFIG_LEGACY_PTYS is not set | 135 | # CONFIG_LEGACY_PTYS is not set |
137 | # CONFIG_DEVKMEM is not set | 136 | # CONFIG_DEVKMEM is not set |
138 | CONFIG_SERIAL_IMX=y | 137 | CONFIG_SERIAL_IMX=y |
@@ -188,22 +187,33 @@ CONFIG_SND_SOC_PHYCORE_AC97=y | |||
188 | CONFIG_SND_SOC_EUKREA_TLV320=y | 187 | CONFIG_SND_SOC_EUKREA_TLV320=y |
189 | CONFIG_SND_SOC_IMX_WM8962=y | 188 | CONFIG_SND_SOC_IMX_WM8962=y |
190 | CONFIG_SND_SOC_IMX_SGTL5000=y | 189 | CONFIG_SND_SOC_IMX_SGTL5000=y |
190 | CONFIG_SND_SOC_IMX_SPDIF=y | ||
191 | CONFIG_SND_SOC_IMX_MC13783=y | 191 | CONFIG_SND_SOC_IMX_MC13783=y |
192 | CONFIG_USB=y | 192 | CONFIG_USB=y |
193 | CONFIG_USB_EHCI_HCD=y | 193 | CONFIG_USB_EHCI_HCD=y |
194 | CONFIG_USB_EHCI_MXC=y | 194 | CONFIG_USB_EHCI_MXC=y |
195 | CONFIG_USB_STORAGE=y | 195 | CONFIG_USB_STORAGE=y |
196 | CONFIG_USB_CHIPIDEA=y | 196 | CONFIG_USB_CHIPIDEA=y |
197 | CONFIG_USB_CHIPIDEA_UDC=y | ||
197 | CONFIG_USB_CHIPIDEA_HOST=y | 198 | CONFIG_USB_CHIPIDEA_HOST=y |
198 | CONFIG_USB_PHY=y | ||
199 | CONFIG_NOP_USB_XCEIV=y | 199 | CONFIG_NOP_USB_XCEIV=y |
200 | CONFIG_USB_MXS_PHY=y | 200 | CONFIG_USB_MXS_PHY=y |
201 | CONFIG_USB_GADGET=y | ||
202 | CONFIG_USB_ETH=m | ||
203 | CONFIG_USB_MASS_STORAGE=m | ||
201 | CONFIG_MMC=y | 204 | CONFIG_MMC=y |
202 | CONFIG_MMC_SDHCI=y | 205 | CONFIG_MMC_SDHCI=y |
203 | CONFIG_MMC_SDHCI_PLTFM=y | 206 | CONFIG_MMC_SDHCI_PLTFM=y |
204 | CONFIG_MMC_SDHCI_ESDHC_IMX=y | 207 | CONFIG_MMC_SDHCI_ESDHC_IMX=y |
205 | CONFIG_NEW_LEDS=y | 208 | CONFIG_NEW_LEDS=y |
206 | CONFIG_LEDS_CLASS=y | 209 | CONFIG_LEDS_CLASS=y |
210 | CONFIG_LEDS_GPIO=y | ||
211 | CONFIG_LEDS_TRIGGERS=y | ||
212 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
213 | CONFIG_LEDS_TRIGGER_ONESHOT=y | ||
214 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
215 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | ||
216 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
207 | CONFIG_RTC_CLASS=y | 217 | CONFIG_RTC_CLASS=y |
208 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | 218 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y |
209 | CONFIG_RTC_DRV_MC13XXX=y | 219 | CONFIG_RTC_DRV_MC13XXX=y |
@@ -246,7 +256,6 @@ CONFIG_UDF_FS=m | |||
246 | CONFIG_MSDOS_FS=m | 256 | CONFIG_MSDOS_FS=m |
247 | CONFIG_VFAT_FS=y | 257 | CONFIG_VFAT_FS=y |
248 | CONFIG_TMPFS=y | 258 | CONFIG_TMPFS=y |
249 | CONFIG_CONFIGFS_FS=m | ||
250 | CONFIG_JFFS2_FS=y | 259 | CONFIG_JFFS2_FS=y |
251 | CONFIG_UBIFS_FS=y | 260 | CONFIG_UBIFS_FS=y |
252 | CONFIG_NFS_FS=y | 261 | CONFIG_NFS_FS=y |
@@ -261,6 +270,7 @@ CONFIG_NLS_ISO8859_15=m | |||
261 | CONFIG_NLS_UTF8=y | 270 | CONFIG_NLS_UTF8=y |
262 | CONFIG_MAGIC_SYSRQ=y | 271 | CONFIG_MAGIC_SYSRQ=y |
263 | # CONFIG_SCHED_DEBUG is not set | 272 | # CONFIG_SCHED_DEBUG is not set |
273 | CONFIG_PROVE_LOCKING=y | ||
264 | # CONFIG_DEBUG_BUGVERBOSE is not set | 274 | # CONFIG_DEBUG_BUGVERBOSE is not set |
265 | # CONFIG_FTRACE is not set | 275 | # CONFIG_FTRACE is not set |
266 | # CONFIG_ARM_UNWIND is not set | 276 | # CONFIG_ARM_UNWIND is not set |
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig index a8314c3ee84d..5bae19557591 100644 --- a/arch/arm/configs/integrator_defconfig +++ b/arch/arm/configs/integrator_defconfig | |||
@@ -1,15 +1,17 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
3 | CONFIG_TINY_RCU=y | 2 | CONFIG_NO_HZ=y |
3 | CONFIG_HIGH_RES_TIMERS=y | ||
4 | CONFIG_IKCONFIG=y | 4 | CONFIG_IKCONFIG=y |
5 | CONFIG_IKCONFIG_PROC=y | 5 | CONFIG_IKCONFIG_PROC=y |
6 | CONFIG_LOG_BUF_SHIFT=14 | 6 | CONFIG_LOG_BUF_SHIFT=14 |
7 | CONFIG_BLK_DEV_INITRD=y | 7 | CONFIG_BLK_DEV_INITRD=y |
8 | CONFIG_MODULES=y | 8 | CONFIG_MODULES=y |
9 | CONFIG_MODULE_UNLOAD=y | 9 | CONFIG_MODULE_UNLOAD=y |
10 | CONFIG_PARTITION_ADVANCED=y | ||
10 | CONFIG_ARCH_INTEGRATOR=y | 11 | CONFIG_ARCH_INTEGRATOR=y |
11 | CONFIG_ARCH_INTEGRATOR_AP=y | 12 | CONFIG_ARCH_INTEGRATOR_AP=y |
12 | CONFIG_ARCH_INTEGRATOR_CP=y | 13 | CONFIG_ARCH_INTEGRATOR_CP=y |
14 | CONFIG_INTEGRATOR_IMPD1=y | ||
13 | CONFIG_CPU_ARM720T=y | 15 | CONFIG_CPU_ARM720T=y |
14 | CONFIG_CPU_ARM920T=y | 16 | CONFIG_CPU_ARM920T=y |
15 | CONFIG_CPU_ARM922T=y | 17 | CONFIG_CPU_ARM922T=y |
@@ -18,12 +20,9 @@ CONFIG_CPU_ARM1020=y | |||
18 | CONFIG_CPU_ARM1022=y | 20 | CONFIG_CPU_ARM1022=y |
19 | CONFIG_CPU_ARM1026=y | 21 | CONFIG_CPU_ARM1026=y |
20 | CONFIG_PCI=y | 22 | CONFIG_PCI=y |
21 | CONFIG_NO_HZ=y | ||
22 | CONFIG_HIGH_RES_TIMERS=y | ||
23 | CONFIG_PREEMPT=y | 23 | CONFIG_PREEMPT=y |
24 | CONFIG_AEABI=y | 24 | CONFIG_AEABI=y |
25 | CONFIG_LEDS=y | 25 | # CONFIG_ATAGS is not set |
26 | CONFIG_LEDS_CPU=y | ||
27 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
28 | CONFIG_ZBOOT_ROM_BSS=0x0 | 27 | CONFIG_ZBOOT_ROM_BSS=0x0 |
29 | CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp" | 28 | CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp" |
@@ -44,24 +43,20 @@ CONFIG_IP_PNP_BOOTP=y | |||
44 | CONFIG_MTD=y | 43 | CONFIG_MTD=y |
45 | CONFIG_MTD_CMDLINE_PARTS=y | 44 | CONFIG_MTD_CMDLINE_PARTS=y |
46 | CONFIG_MTD_AFS_PARTS=y | 45 | CONFIG_MTD_AFS_PARTS=y |
47 | CONFIG_MTD_CHAR=y | ||
48 | CONFIG_MTD_BLOCK=y | 46 | CONFIG_MTD_BLOCK=y |
49 | CONFIG_MTD_CFI=y | 47 | CONFIG_MTD_CFI=y |
50 | CONFIG_MTD_CFI_ADV_OPTIONS=y | 48 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
51 | CONFIG_MTD_CFI_INTELEXT=y | 49 | CONFIG_MTD_CFI_INTELEXT=y |
52 | CONFIG_MTD_PHYSMAP=y | 50 | CONFIG_MTD_PHYSMAP=y |
51 | CONFIG_PROC_DEVICETREE=y | ||
53 | CONFIG_BLK_DEV_LOOP=y | 52 | CONFIG_BLK_DEV_LOOP=y |
54 | CONFIG_BLK_DEV_RAM=y | 53 | CONFIG_BLK_DEV_RAM=y |
55 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 54 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
56 | CONFIG_NETDEVICES=y | 55 | CONFIG_NETDEVICES=y |
57 | CONFIG_NET_ETHERNET=y | ||
58 | CONFIG_NET_PCI=y | ||
59 | CONFIG_E100=y | 56 | CONFIG_E100=y |
60 | CONFIG_SMC91X=y | 57 | CONFIG_SMC91X=y |
61 | # CONFIG_KEYBOARD_ATKBD is not set | 58 | # CONFIG_KEYBOARD_ATKBD is not set |
62 | # CONFIG_SERIO_SERPORT is not set | 59 | # CONFIG_SERIO_SERPORT is not set |
63 | CONFIG_SERIAL_AMBA_PL010=y | ||
64 | CONFIG_SERIAL_AMBA_PL010_CONSOLE=y | ||
65 | CONFIG_FB=y | 60 | CONFIG_FB=y |
66 | CONFIG_FB_MODE_HELPERS=y | 61 | CONFIG_FB_MODE_HELPERS=y |
67 | CONFIG_FB_ARMCLCD=y | 62 | CONFIG_FB_ARMCLCD=y |
@@ -71,19 +66,23 @@ CONFIG_FB_MATROX_MYSTIQUE=y | |||
71 | # CONFIG_VGA_CONSOLE is not set | 66 | # CONFIG_VGA_CONSOLE is not set |
72 | CONFIG_MMC=y | 67 | CONFIG_MMC=y |
73 | CONFIG_MMC_ARMMMCI=y | 68 | CONFIG_MMC_ARMMMCI=y |
69 | CONFIG_NEW_LEDS=y | ||
70 | CONFIG_LEDS_CLASS=y | ||
71 | CONFIG_LEDS_TRIGGERS=y | ||
72 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
73 | CONFIG_LEDS_TRIGGER_CPU=y | ||
74 | CONFIG_RTC_CLASS=y | 74 | CONFIG_RTC_CLASS=y |
75 | CONFIG_RTC_DRV_PL030=y | 75 | CONFIG_RTC_DRV_PL030=y |
76 | CONFIG_COMMON_CLK_DEBUG=y | ||
76 | CONFIG_EXT2_FS=y | 77 | CONFIG_EXT2_FS=y |
77 | CONFIG_VFAT_FS=y | 78 | CONFIG_VFAT_FS=y |
78 | CONFIG_TMPFS=y | 79 | CONFIG_TMPFS=y |
79 | CONFIG_JFFS2_FS=y | 80 | CONFIG_JFFS2_FS=y |
80 | CONFIG_CRAMFS=y | 81 | CONFIG_CRAMFS=y |
81 | CONFIG_NFS_FS=y | 82 | CONFIG_NFS_FS=y |
82 | CONFIG_NFS_V3=y | ||
83 | CONFIG_ROOT_NFS=y | 83 | CONFIG_ROOT_NFS=y |
84 | CONFIG_NFSD=y | 84 | CONFIG_NFSD=y |
85 | CONFIG_NFSD_V3=y | 85 | CONFIG_NFSD_V3=y |
86 | CONFIG_PARTITION_ADVANCED=y | ||
87 | CONFIG_NLS_CODEPAGE_437=y | 86 | CONFIG_NLS_CODEPAGE_437=y |
88 | CONFIG_NLS_ISO8859_1=y | 87 | CONFIG_NLS_ISO8859_1=y |
89 | CONFIG_MAGIC_SYSRQ=y | 88 | CONFIG_MAGIC_SYSRQ=y |
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 1f36b823905f..9943e5da74f1 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig | |||
@@ -123,7 +123,9 @@ CONFIG_SERIAL_OF_PLATFORM=y | |||
123 | CONFIG_I2C=y | 123 | CONFIG_I2C=y |
124 | # CONFIG_I2C_COMPAT is not set | 124 | # CONFIG_I2C_COMPAT is not set |
125 | CONFIG_I2C_CHARDEV=y | 125 | CONFIG_I2C_CHARDEV=y |
126 | CONFIG_I2C_DAVINCI=y | ||
126 | CONFIG_SPI=y | 127 | CONFIG_SPI=y |
128 | CONFIG_SPI_DAVINCI=y | ||
127 | CONFIG_SPI_SPIDEV=y | 129 | CONFIG_SPI_SPIDEV=y |
128 | # CONFIG_HWMON is not set | 130 | # CONFIG_HWMON is not set |
129 | CONFIG_WATCHDOG=y | 131 | CONFIG_WATCHDOG=y |
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 119fc378fc52..4a5903e04827 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig | |||
@@ -6,6 +6,7 @@ CONFIG_ARCH_MVEBU=y | |||
6 | CONFIG_MACH_ARMADA_370=y | 6 | CONFIG_MACH_ARMADA_370=y |
7 | CONFIG_MACH_ARMADA_XP=y | 7 | CONFIG_MACH_ARMADA_XP=y |
8 | CONFIG_ARCH_BCM=y | 8 | CONFIG_ARCH_BCM=y |
9 | CONFIG_ARCH_BCM_MOBILE=y | ||
9 | CONFIG_GPIO_PCA953X=y | 10 | CONFIG_GPIO_PCA953X=y |
10 | CONFIG_ARCH_HIGHBANK=y | 11 | CONFIG_ARCH_HIGHBANK=y |
11 | CONFIG_ARCH_KEYSTONE=y | 12 | CONFIG_ARCH_KEYSTONE=y |
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 4555c025629a..6150108e15de 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig | |||
@@ -76,7 +76,6 @@ CONFIG_INPUT_EVDEV=y | |||
76 | CONFIG_INPUT_TOUCHSCREEN=y | 76 | CONFIG_INPUT_TOUCHSCREEN=y |
77 | CONFIG_TOUCHSCREEN_TSC2007=m | 77 | CONFIG_TOUCHSCREEN_TSC2007=m |
78 | # CONFIG_SERIO is not set | 78 | # CONFIG_SERIO is not set |
79 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
80 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y | 79 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y |
81 | # CONFIG_LEGACY_PTYS is not set | 80 | # CONFIG_LEGACY_PTYS is not set |
82 | # CONFIG_DEVKMEM is not set | 81 | # CONFIG_DEVKMEM is not set |
@@ -91,7 +90,6 @@ CONFIG_I2C_MXS=y | |||
91 | CONFIG_SPI=y | 90 | CONFIG_SPI=y |
92 | CONFIG_SPI_GPIO=m | 91 | CONFIG_SPI_GPIO=m |
93 | CONFIG_SPI_MXS=y | 92 | CONFIG_SPI_MXS=y |
94 | CONFIG_DEBUG_GPIO=y | ||
95 | CONFIG_GPIO_SYSFS=y | 93 | CONFIG_GPIO_SYSFS=y |
96 | # CONFIG_HWMON is not set | 94 | # CONFIG_HWMON is not set |
97 | CONFIG_WATCHDOG=y | 95 | CONFIG_WATCHDOG=y |
@@ -115,9 +113,12 @@ CONFIG_USB=y | |||
115 | CONFIG_USB_EHCI_HCD=y | 113 | CONFIG_USB_EHCI_HCD=y |
116 | CONFIG_USB_STORAGE=y | 114 | CONFIG_USB_STORAGE=y |
117 | CONFIG_USB_CHIPIDEA=y | 115 | CONFIG_USB_CHIPIDEA=y |
116 | CONFIG_USB_CHIPIDEA_UDC=y | ||
118 | CONFIG_USB_CHIPIDEA_HOST=y | 117 | CONFIG_USB_CHIPIDEA_HOST=y |
119 | CONFIG_USB_PHY=y | ||
120 | CONFIG_USB_MXS_PHY=y | 118 | CONFIG_USB_MXS_PHY=y |
119 | CONFIG_USB_GADGET=y | ||
120 | CONFIG_USB_ETH=m | ||
121 | CONFIG_USB_MASS_STORAGE=m | ||
121 | CONFIG_MMC=y | 122 | CONFIG_MMC=y |
122 | CONFIG_MMC_UNSAFE_RESUME=y | 123 | CONFIG_MMC_UNSAFE_RESUME=y |
123 | CONFIG_MMC_MXS=y | 124 | CONFIG_MMC_MXS=y |
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig new file mode 100644 index 000000000000..d57a85badb5e --- /dev/null +++ b/arch/arm/configs/sunxi_defconfig | |||
@@ -0,0 +1,61 @@ | |||
1 | CONFIG_NO_HZ=y | ||
2 | CONFIG_HIGH_RES_TIMERS=y | ||
3 | CONFIG_BLK_DEV_INITRD=y | ||
4 | CONFIG_ARCH_SUNXI=y | ||
5 | CONFIG_SMP=y | ||
6 | CONFIG_AEABI=y | ||
7 | CONFIG_HIGHMEM=y | ||
8 | CONFIG_HIGHPTE=y | ||
9 | CONFIG_VFP=y | ||
10 | CONFIG_NEON=y | ||
11 | CONFIG_NET=y | ||
12 | CONFIG_PACKET=y | ||
13 | CONFIG_UNIX=y | ||
14 | CONFIG_INET=y | ||
15 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
16 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
17 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
18 | # CONFIG_INET_LRO is not set | ||
19 | # CONFIG_INET_DIAG is not set | ||
20 | # CONFIG_IPV6 is not set | ||
21 | # CONFIG_WIRELESS is not set | ||
22 | CONFIG_DEVTMPFS=y | ||
23 | CONFIG_DEVTMPFS_MOUNT=y | ||
24 | CONFIG_NETDEVICES=y | ||
25 | CONFIG_SUN4I_EMAC=y | ||
26 | # CONFIG_NET_CADENCE is not set | ||
27 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
28 | # CONFIG_NET_VENDOR_CIRRUS is not set | ||
29 | # CONFIG_NET_VENDOR_FARADAY is not set | ||
30 | # CONFIG_NET_VENDOR_INTEL is not set | ||
31 | # CONFIG_NET_VENDOR_MARVELL is not set | ||
32 | # CONFIG_NET_VENDOR_MICREL is not set | ||
33 | # CONFIG_NET_VENDOR_NATSEMI is not set | ||
34 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
35 | # CONFIG_NET_VENDOR_SMSC is not set | ||
36 | # CONFIG_NET_VENDOR_STMICRO is not set | ||
37 | # CONFIG_NET_VENDOR_WIZNET is not set | ||
38 | # CONFIG_WLAN is not set | ||
39 | CONFIG_SERIAL_8250=y | ||
40 | CONFIG_SERIAL_8250_CONSOLE=y | ||
41 | CONFIG_SERIAL_8250_NR_UARTS=8 | ||
42 | CONFIG_SERIAL_8250_RUNTIME_UARTS=8 | ||
43 | CONFIG_SERIAL_8250_DW=y | ||
44 | CONFIG_I2C=y | ||
45 | # CONFIG_I2C_COMPAT is not set | ||
46 | CONFIG_I2C_CHARDEV=y | ||
47 | CONFIG_I2C_MV64XXX=y | ||
48 | CONFIG_GPIO_SYSFS=y | ||
49 | # CONFIG_HWMON is not set | ||
50 | CONFIG_WATCHDOG=y | ||
51 | CONFIG_SUNXI_WATCHDOG=y | ||
52 | # CONFIG_USB_SUPPORT is not set | ||
53 | CONFIG_NEW_LEDS=y | ||
54 | CONFIG_LEDS_CLASS=y | ||
55 | CONFIG_LEDS_GPIO=y | ||
56 | CONFIG_LEDS_TRIGGERS=y | ||
57 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
58 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
59 | CONFIG_COMMON_CLK_DEBUG=y | ||
60 | # CONFIG_IOMMU_SUPPORT is not set | ||
61 | CONFIG_NLS=y | ||
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index f2de51f0bd18..f489fdaa19b8 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig | |||
@@ -1,4 +1,3 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | # CONFIG_LOCALVERSION_AUTO is not set | 1 | # CONFIG_LOCALVERSION_AUTO is not set |
3 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
4 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
@@ -8,11 +7,9 @@ CONFIG_CGROUPS=y | |||
8 | CONFIG_CPUSETS=y | 7 | CONFIG_CPUSETS=y |
9 | # CONFIG_UTS_NS is not set | 8 | # CONFIG_UTS_NS is not set |
10 | # CONFIG_IPC_NS is not set | 9 | # CONFIG_IPC_NS is not set |
11 | # CONFIG_USER_NS is not set | ||
12 | # CONFIG_PID_NS is not set | 10 | # CONFIG_PID_NS is not set |
13 | # CONFIG_NET_NS is not set | 11 | # CONFIG_NET_NS is not set |
14 | CONFIG_BLK_DEV_INITRD=y | 12 | CONFIG_BLK_DEV_INITRD=y |
15 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
16 | CONFIG_PROFILING=y | 13 | CONFIG_PROFILING=y |
17 | CONFIG_OPROFILE=y | 14 | CONFIG_OPROFILE=y |
18 | CONFIG_MODULES=y | 15 | CONFIG_MODULES=y |
@@ -23,14 +20,22 @@ CONFIG_MODULE_UNLOAD=y | |||
23 | # CONFIG_IOSCHED_CFQ is not set | 20 | # CONFIG_IOSCHED_CFQ is not set |
24 | CONFIG_ARCH_VEXPRESS=y | 21 | CONFIG_ARCH_VEXPRESS=y |
25 | CONFIG_ARCH_VEXPRESS_CA9X4=y | 22 | CONFIG_ARCH_VEXPRESS_CA9X4=y |
23 | CONFIG_ARCH_VEXPRESS_DCSCB=y | ||
24 | CONFIG_ARCH_VEXPRESS_TC2_PM=y | ||
26 | # CONFIG_SWP_EMULATE is not set | 25 | # CONFIG_SWP_EMULATE is not set |
27 | CONFIG_SMP=y | 26 | CONFIG_SMP=y |
27 | CONFIG_HAVE_ARM_ARCH_TIMER=y | ||
28 | CONFIG_MCPM=y | ||
28 | CONFIG_VMSPLIT_2G=y | 29 | CONFIG_VMSPLIT_2G=y |
29 | CONFIG_HOTPLUG_CPU=y | 30 | CONFIG_NR_CPUS=8 |
31 | CONFIG_ARM_PSCI=y | ||
30 | CONFIG_AEABI=y | 32 | CONFIG_AEABI=y |
33 | CONFIG_CMA=y | ||
31 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 34 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
32 | CONFIG_ZBOOT_ROM_BSS=0x0 | 35 | CONFIG_ZBOOT_ROM_BSS=0x0 |
33 | CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M" | 36 | CONFIG_CMDLINE="console=ttyAMA0" |
37 | CONFIG_CPU_IDLE=y | ||
38 | CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y | ||
34 | CONFIG_VFP=y | 39 | CONFIG_VFP=y |
35 | CONFIG_NEON=y | 40 | CONFIG_NEON=y |
36 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | 41 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set |
@@ -44,37 +49,46 @@ CONFIG_IP_PNP_BOOTP=y | |||
44 | # CONFIG_INET_LRO is not set | 49 | # CONFIG_INET_LRO is not set |
45 | # CONFIG_IPV6 is not set | 50 | # CONFIG_IPV6 is not set |
46 | # CONFIG_WIRELESS is not set | 51 | # CONFIG_WIRELESS is not set |
52 | CONFIG_NET_9P=y | ||
53 | CONFIG_NET_9P_VIRTIO=y | ||
47 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 54 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
55 | CONFIG_DEVTMPFS=y | ||
48 | CONFIG_MTD=y | 56 | CONFIG_MTD=y |
49 | CONFIG_MTD_CONCAT=y | ||
50 | CONFIG_MTD_PARTITIONS=y | ||
51 | CONFIG_MTD_CMDLINE_PARTS=y | 57 | CONFIG_MTD_CMDLINE_PARTS=y |
52 | CONFIG_MTD_CHAR=y | ||
53 | CONFIG_MTD_BLOCK=y | 58 | CONFIG_MTD_BLOCK=y |
54 | CONFIG_MTD_CFI=y | 59 | CONFIG_MTD_CFI=y |
55 | CONFIG_MTD_CFI_INTELEXT=y | 60 | CONFIG_MTD_CFI_INTELEXT=y |
56 | CONFIG_MTD_CFI_AMDSTD=y | 61 | CONFIG_MTD_CFI_AMDSTD=y |
57 | CONFIG_MTD_ARM_INTEGRATOR=y | 62 | CONFIG_MTD_PHYSMAP=y |
58 | CONFIG_MISC_DEVICES=y | 63 | CONFIG_MTD_PHYSMAP_OF=y |
64 | CONFIG_MTD_PLATRAM=y | ||
65 | CONFIG_MTD_UBI=y | ||
66 | CONFIG_PROC_DEVICETREE=y | ||
67 | CONFIG_VIRTIO_BLK=y | ||
59 | # CONFIG_SCSI_PROC_FS is not set | 68 | # CONFIG_SCSI_PROC_FS is not set |
60 | CONFIG_BLK_DEV_SD=y | 69 | CONFIG_BLK_DEV_SD=y |
61 | # CONFIG_SCSI_LOWLEVEL is not set | 70 | CONFIG_SCSI_VIRTIO=y |
62 | CONFIG_ATA=y | 71 | CONFIG_ATA=y |
63 | # CONFIG_SATA_PMP is not set | 72 | # CONFIG_SATA_PMP is not set |
64 | CONFIG_NETDEVICES=y | 73 | CONFIG_NETDEVICES=y |
65 | CONFIG_NET_ETHERNET=y | 74 | CONFIG_VIRTIO_NET=y |
75 | CONFIG_SMC91X=y | ||
66 | CONFIG_SMSC911X=y | 76 | CONFIG_SMSC911X=y |
67 | # CONFIG_NETDEV_1000 is not set | ||
68 | # CONFIG_NETDEV_10000 is not set | ||
69 | # CONFIG_WLAN is not set | 77 | # CONFIG_WLAN is not set |
70 | CONFIG_INPUT_EVDEV=y | 78 | CONFIG_INPUT_EVDEV=y |
71 | # CONFIG_SERIO_SERPORT is not set | 79 | # CONFIG_SERIO_SERPORT is not set |
72 | CONFIG_SERIO_AMBAKMI=y | 80 | CONFIG_SERIO_AMBAKMI=y |
81 | CONFIG_LEGACY_PTY_COUNT=16 | ||
73 | CONFIG_SERIAL_AMBA_PL011=y | 82 | CONFIG_SERIAL_AMBA_PL011=y |
74 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 83 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
75 | CONFIG_LEGACY_PTY_COUNT=16 | 84 | CONFIG_VIRTIO_CONSOLE=y |
76 | # CONFIG_HW_RANDOM is not set | 85 | CONFIG_HW_RANDOM=y |
77 | # CONFIG_HWMON is not set | 86 | CONFIG_HW_RANDOM_VIRTIO=y |
87 | CONFIG_I2C=y | ||
88 | CONFIG_I2C_VERSATILE=y | ||
89 | CONFIG_SENSORS_VEXPRESS=y | ||
90 | CONFIG_REGULATOR=y | ||
91 | CONFIG_REGULATOR_VEXPRESS=y | ||
78 | CONFIG_FB=y | 92 | CONFIG_FB=y |
79 | CONFIG_FB_ARMCLCD=y | 93 | CONFIG_FB_ARMCLCD=y |
80 | CONFIG_FRAMEBUFFER_CONSOLE=y | 94 | CONFIG_FRAMEBUFFER_CONSOLE=y |
@@ -103,38 +117,45 @@ CONFIG_HID_THRUSTMASTER=y | |||
103 | CONFIG_HID_ZEROPLUS=y | 117 | CONFIG_HID_ZEROPLUS=y |
104 | CONFIG_USB=y | 118 | CONFIG_USB=y |
105 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | 119 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y |
106 | # CONFIG_USB_DEVICE_CLASS is not set | ||
107 | CONFIG_USB_MON=y | 120 | CONFIG_USB_MON=y |
108 | CONFIG_USB_ISP1760_HCD=y | 121 | CONFIG_USB_ISP1760_HCD=y |
109 | CONFIG_USB_STORAGE=y | 122 | CONFIG_USB_STORAGE=y |
110 | CONFIG_MMC=y | 123 | CONFIG_MMC=y |
111 | CONFIG_MMC_ARMMMCI=y | 124 | CONFIG_MMC_ARMMMCI=y |
125 | CONFIG_NEW_LEDS=y | ||
126 | CONFIG_LEDS_CLASS=y | ||
127 | CONFIG_LEDS_GPIO=y | ||
128 | CONFIG_LEDS_TRIGGERS=y | ||
129 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
130 | CONFIG_LEDS_TRIGGER_CPU=y | ||
112 | CONFIG_RTC_CLASS=y | 131 | CONFIG_RTC_CLASS=y |
113 | CONFIG_RTC_DRV_PL031=y | 132 | CONFIG_RTC_DRV_PL031=y |
133 | CONFIG_VIRTIO_BALLOON=y | ||
134 | CONFIG_VIRTIO_MMIO=y | ||
135 | CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y | ||
114 | CONFIG_EXT2_FS=y | 136 | CONFIG_EXT2_FS=y |
115 | CONFIG_EXT3_FS=y | 137 | CONFIG_EXT3_FS=y |
116 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 138 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
117 | # CONFIG_EXT3_FS_XATTR is not set | 139 | # CONFIG_EXT3_FS_XATTR is not set |
140 | CONFIG_EXT4_FS=y | ||
118 | CONFIG_VFAT_FS=y | 141 | CONFIG_VFAT_FS=y |
119 | CONFIG_TMPFS=y | 142 | CONFIG_TMPFS=y |
120 | CONFIG_JFFS2_FS=y | 143 | CONFIG_JFFS2_FS=y |
144 | CONFIG_UBIFS_FS=y | ||
121 | CONFIG_CRAMFS=y | 145 | CONFIG_CRAMFS=y |
146 | CONFIG_SQUASHFS=y | ||
147 | CONFIG_SQUASHFS_LZO=y | ||
122 | CONFIG_NFS_FS=y | 148 | CONFIG_NFS_FS=y |
123 | CONFIG_NFS_V3=y | ||
124 | CONFIG_ROOT_NFS=y | 149 | CONFIG_ROOT_NFS=y |
125 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 150 | CONFIG_9P_FS=y |
126 | CONFIG_NLS_CODEPAGE_437=y | 151 | CONFIG_NLS_CODEPAGE_437=y |
127 | CONFIG_NLS_ISO8859_1=y | 152 | CONFIG_NLS_ISO8859_1=y |
128 | CONFIG_MAGIC_SYSRQ=y | 153 | CONFIG_DEBUG_INFO=y |
129 | CONFIG_DEBUG_FS=y | 154 | CONFIG_DEBUG_FS=y |
155 | CONFIG_MAGIC_SYSRQ=y | ||
130 | CONFIG_DEBUG_KERNEL=y | 156 | CONFIG_DEBUG_KERNEL=y |
131 | CONFIG_DETECT_HUNG_TASK=y | 157 | CONFIG_DETECT_HUNG_TASK=y |
132 | # CONFIG_SCHED_DEBUG is not set | 158 | # CONFIG_SCHED_DEBUG is not set |
133 | CONFIG_DEBUG_INFO=y | ||
134 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
135 | CONFIG_DEBUG_USER=y | 159 | CONFIG_DEBUG_USER=y |
136 | CONFIG_DEBUG_ERRORS=y | ||
137 | CONFIG_DEBUG_LL=y | ||
138 | CONFIG_EARLY_PRINTK=y | ||
139 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 160 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
140 | # CONFIG_CRYPTO_HW is not set | 161 | # CONFIG_CRYPTO_HW is not set |
diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S new file mode 100644 index 000000000000..ba12cc44b2cb --- /dev/null +++ b/arch/arm/include/debug/vf.S | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | .macro addruart, rp, rv, tmp | ||
11 | ldr \rp, =0x40028000 @ physical | ||
12 | ldr \rv, =0xfe028000 @ virtual | ||
13 | .endm | ||
14 | |||
15 | .macro senduart, rd, rx | ||
16 | strb \rd, [\rx, #0x7] @ Data Register | ||
17 | .endm | ||
18 | |||
19 | .macro busyuart, rd, rx | ||
20 | 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1 | ||
21 | tst \rd, #1 << 6 @ TC | ||
22 | beq 1001b @ wait until transmit done | ||
23 | .endm | ||
24 | |||
25 | .macro waituart,rd,rx | ||
26 | .endm | ||
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c index 70ded3fb42d9..570a48cc3d64 100644 --- a/arch/arm/kernel/psci_smp.c +++ b/arch/arm/kernel/psci_smp.c | |||
@@ -14,7 +14,6 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/irqchip/arm-gic.h> | ||
18 | #include <linux/smp.h> | 17 | #include <linux/smp.h> |
19 | #include <linux/of.h> | 18 | #include <linux/of.h> |
20 | 19 | ||
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 69d67f714a2f..9fe6d88737ed 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig | |||
@@ -1,5 +1,16 @@ | |||
1 | config ARCH_BCM | 1 | config ARCH_BCM |
2 | bool "Broadcom SoC" if ARCH_MULTI_V7 | 2 | bool "Broadcom SoC Support" |
3 | depends on ARCH_MULTIPLATFORM | ||
4 | help | ||
5 | This enables support for Broadcom ARM based SoC | ||
6 | chips | ||
7 | |||
8 | if ARCH_BCM | ||
9 | |||
10 | menu "Broadcom SoC Selection" | ||
11 | |||
12 | config ARCH_BCM_MOBILE | ||
13 | bool "Broadcom Mobile SoC" if ARCH_MULTI_V7 | ||
3 | depends on MMU | 14 | depends on MMU |
4 | select ARCH_REQUIRE_GPIOLIB | 15 | select ARCH_REQUIRE_GPIOLIB |
5 | select ARM_ERRATA_754322 | 16 | select ARM_ERRATA_754322 |
@@ -9,12 +20,17 @@ config ARCH_BCM | |||
9 | select CLKSRC_OF | 20 | select CLKSRC_OF |
10 | select GENERIC_CLOCKEVENTS | 21 | select GENERIC_CLOCKEVENTS |
11 | select GENERIC_TIME | 22 | select GENERIC_TIME |
12 | select GPIO_BCM | 23 | select GPIO_BCM_KONA |
13 | select SPARSE_IRQ | 24 | select SPARSE_IRQ |
14 | select TICK_ONESHOT | 25 | select TICK_ONESHOT |
15 | select CACHE_L2X0 | 26 | select CACHE_L2X0 |
27 | select HAVE_ARM_ARCH_TIMER | ||
16 | help | 28 | help |
17 | This enables support for system based on Broadcom SoCs. | 29 | This enables support for systems based on Broadcom mobile SoCs. |
18 | It currently supports the 'BCM281XX' family, which includes | 30 | It currently supports the 'BCM281XX' family, which includes |
19 | BCM11130, BCM11140, BCM11351, BCM28145 and | 31 | BCM11130, BCM11140, BCM11351, BCM28145 and |
20 | BCM28155 variants. | 32 | BCM28155 variants. |
33 | |||
34 | endmenu | ||
35 | |||
36 | endif | ||
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index e3d03033a7e2..c2ccd5a0f772 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile | |||
@@ -10,6 +10,6 @@ | |||
10 | # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 10 | # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
11 | # GNU General Public License for more details. | 11 | # GNU General Public License for more details. |
12 | 12 | ||
13 | obj-$(CONFIG_ARCH_BCM) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o | 13 | obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o |
14 | plus_sec := $(call as-instr,.arch_extension sec,+sec) | 14 | plus_sec := $(call as-instr,.arch_extension sec,+sec) |
15 | AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) | 15 | AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) |
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c index 26b2390492b8..cb3dc364405c 100644 --- a/arch/arm/mach-bcm/board_bcm281xx.c +++ b/arch/arm/mach-bcm/board_bcm281xx.c | |||
@@ -67,7 +67,7 @@ static void __init board_init(void) | |||
67 | 67 | ||
68 | static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, }; | 68 | static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, }; |
69 | 69 | ||
70 | DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") | 70 | DT_MACHINE_START(BCM11351_DT, "BCM281xx Broadcom Application Processor") |
71 | .init_machine = board_init, | 71 | .init_machine = board_init, |
72 | .restart = bcm_kona_restart, | 72 | .restart = bcm_kona_restart, |
73 | .dt_compat = bcm11351_dt_compat, | 73 | .dt_compat = bcm11351_dt_compat, |
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index c4bdc0a1c36e..30a44e2df47e 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c | |||
@@ -74,7 +74,7 @@ static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler) | |||
74 | if (handler != NULL) { | 74 | if (handler != NULL) { |
75 | da830_evm_usb_ocic_handler = handler; | 75 | da830_evm_usb_ocic_handler = handler; |
76 | 76 | ||
77 | error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED | | 77 | error = request_irq(irq, da830_evm_usb_ocic_irq, |
78 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | 78 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
79 | "OHCI over-current indicator", NULL); | 79 | "OHCI over-current indicator", NULL); |
80 | if (error) | 80 | if (error) |
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index ab98c75cabb4..e0de2da41b5c 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c | |||
@@ -211,7 +211,7 @@ static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler) | |||
211 | hawk_usb_ocic_handler = handler; | 211 | hawk_usb_ocic_handler = handler; |
212 | 212 | ||
213 | error = request_irq(irq, omapl138_hawk_usb_ocic_irq, | 213 | error = request_irq(irq, omapl138_hawk_usb_ocic_irq, |
214 | IRQF_DISABLED | IRQF_TRIGGER_RISING | | 214 | IRQF_TRIGGER_RISING | |
215 | IRQF_TRIGGER_FALLING, | 215 | IRQF_TRIGGER_FALLING, |
216 | "OHCI over-current indicator", NULL); | 216 | "OHCI over-current indicator", NULL); |
217 | if (error) | 217 | if (error) |
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 7a55b5c95971..56c6eb5266ad 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c | |||
@@ -181,7 +181,7 @@ static struct timer_s timers[] = { | |||
181 | .name = "clockevent", | 181 | .name = "clockevent", |
182 | .opts = TIMER_OPTS_DISABLED, | 182 | .opts = TIMER_OPTS_DISABLED, |
183 | .irqaction = { | 183 | .irqaction = { |
184 | .flags = IRQF_DISABLED | IRQF_TIMER, | 184 | .flags = IRQF_TIMER, |
185 | .handler = timer_interrupt, | 185 | .handler = timer_interrupt, |
186 | } | 186 | } |
187 | }, | 187 | }, |
@@ -190,7 +190,7 @@ static struct timer_s timers[] = { | |||
190 | .period = ~0, | 190 | .period = ~0, |
191 | .opts = TIMER_OPTS_PERIODIC, | 191 | .opts = TIMER_OPTS_PERIODIC, |
192 | .irqaction = { | 192 | .irqaction = { |
193 | .flags = IRQF_DISABLED | IRQF_TIMER, | 193 | .flags = IRQF_TIMER, |
194 | .handler = freerun_interrupt, | 194 | .handler = freerun_interrupt, |
195 | } | 195 | } |
196 | }, | 196 | }, |
@@ -331,7 +331,6 @@ static void davinci_set_mode(enum clock_event_mode mode, | |||
331 | 331 | ||
332 | static struct clock_event_device clockevent_davinci = { | 332 | static struct clock_event_device clockevent_davinci = { |
333 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 333 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
334 | .shift = 32, | ||
335 | .set_next_event = davinci_set_next_event, | 334 | .set_next_event = davinci_set_next_event, |
336 | .set_mode = davinci_set_mode, | 335 | .set_mode = davinci_set_mode, |
337 | }; | 336 | }; |
@@ -397,14 +396,10 @@ void __init davinci_timer_init(void) | |||
397 | 396 | ||
398 | /* setup clockevent */ | 397 | /* setup clockevent */ |
399 | clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; | 398 | clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; |
400 | clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, | ||
401 | clockevent_davinci.shift); | ||
402 | clockevent_davinci.max_delta_ns = | ||
403 | clockevent_delta2ns(0xfffffffe, &clockevent_davinci); | ||
404 | clockevent_davinci.min_delta_ns = 50000; /* 50 usec */ | ||
405 | 399 | ||
406 | clockevent_davinci.cpumask = cpumask_of(0); | 400 | clockevent_davinci.cpumask = cpumask_of(0); |
407 | clockevents_register_device(&clockevent_davinci); | 401 | clockevents_config_and_register(&clockevent_davinci, |
402 | davinci_clock_tick_rate, 1, 0xfffffffe); | ||
408 | 403 | ||
409 | for (i=0; i< ARRAY_SIZE(timers); i++) | 404 | for (i=0; i< ARRAY_SIZE(timers); i++) |
410 | timer32_config(&timers[i]); | 405 | timer32_config(&timers[i]); |
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 616408d76be5..fe98df44579c 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig | |||
@@ -10,6 +10,7 @@ config ARCH_HIGHBANK | |||
10 | select ARM_ERRATA_775420 | 10 | select ARM_ERRATA_775420 |
11 | select ARM_ERRATA_798181 | 11 | select ARM_ERRATA_798181 |
12 | select ARM_GIC | 12 | select ARM_GIC |
13 | select ARM_PSCI | ||
13 | select ARM_TIMER_SP804 | 14 | select ARM_TIMER_SP804 |
14 | select CACHE_L2X0 | 15 | select CACHE_L2X0 |
15 | select COMMON_CLK | 16 | select COMMON_CLK |
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile index 8a1ef576d79f..55840f414d3e 100644 --- a/arch/arm/mach-highbank/Makefile +++ b/arch/arm/mach-highbank/Makefile | |||
@@ -3,6 +3,4 @@ obj-y := highbank.o system.o smc.o | |||
3 | plus_sec := $(call as-instr,.arch_extension sec,+sec) | 3 | plus_sec := $(call as-instr,.arch_extension sec,+sec) |
4 | AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) | 4 | AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) |
5 | 5 | ||
6 | obj-$(CONFIG_SMP) += platsmp.o | ||
7 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
8 | obj-$(CONFIG_PM_SLEEP) += pm.o | 6 | obj-$(CONFIG_PM_SLEEP) += pm.o |
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h index aea1ec5ab6f8..7ec5edcd1336 100644 --- a/arch/arm/mach-highbank/core.h +++ b/arch/arm/mach-highbank/core.h | |||
@@ -3,7 +3,6 @@ | |||
3 | 3 | ||
4 | #include <linux/reboot.h> | 4 | #include <linux/reboot.h> |
5 | 5 | ||
6 | extern void highbank_set_cpu_jump(int cpu, void *jump_addr); | ||
7 | extern void highbank_restart(enum reboot_mode, const char *); | 6 | extern void highbank_restart(enum reboot_mode, const char *); |
8 | extern void __iomem *scu_base_addr; | 7 | extern void __iomem *scu_base_addr; |
9 | 8 | ||
@@ -14,8 +13,5 @@ static inline void highbank_pm_init(void) {} | |||
14 | #endif | 13 | #endif |
15 | 14 | ||
16 | extern void highbank_smc1(int fn, int arg); | 15 | extern void highbank_smc1(int fn, int arg); |
17 | extern void highbank_cpu_die(unsigned int cpu); | ||
18 | |||
19 | extern struct smp_operations highbank_smp_ops; | ||
20 | 16 | ||
21 | #endif | 17 | #endif |
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index e6d6eacea9d0..b3d7e5634b83 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c | |||
@@ -24,10 +24,9 @@ | |||
24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
25 | #include <linux/of_address.h> | 25 | #include <linux/of_address.h> |
26 | #include <linux/amba/bus.h> | 26 | #include <linux/amba/bus.h> |
27 | #include <linux/platform_device.h> | ||
27 | 28 | ||
28 | #include <asm/cacheflush.h> | 29 | #include <asm/psci.h> |
29 | #include <asm/cputype.h> | ||
30 | #include <asm/smp_plat.h> | ||
31 | #include <asm/hardware/cache-l2x0.h> | 30 | #include <asm/hardware/cache-l2x0.h> |
32 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
33 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
@@ -48,17 +47,6 @@ static void __init highbank_scu_map_io(void) | |||
48 | scu_base_addr = ioremap(base, SZ_4K); | 47 | scu_base_addr = ioremap(base, SZ_4K); |
49 | } | 48 | } |
50 | 49 | ||
51 | #define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) | ||
52 | #define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) | ||
53 | |||
54 | void highbank_set_cpu_jump(int cpu, void *jump_addr) | ||
55 | { | ||
56 | cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); | ||
57 | writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); | ||
58 | __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); | ||
59 | outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), | ||
60 | HB_JUMP_TABLE_PHYS(cpu) + 15); | ||
61 | } | ||
62 | 50 | ||
63 | static void highbank_l2x0_disable(void) | 51 | static void highbank_l2x0_disable(void) |
64 | { | 52 | { |
@@ -138,6 +126,10 @@ static struct notifier_block highbank_platform_nb = { | |||
138 | .notifier_call = highbank_platform_notifier, | 126 | .notifier_call = highbank_platform_notifier, |
139 | }; | 127 | }; |
140 | 128 | ||
129 | static struct platform_device highbank_cpuidle_device = { | ||
130 | .name = "cpuidle-calxeda", | ||
131 | }; | ||
132 | |||
141 | static void __init highbank_init(void) | 133 | static void __init highbank_init(void) |
142 | { | 134 | { |
143 | struct device_node *np; | 135 | struct device_node *np; |
@@ -154,6 +146,9 @@ static void __init highbank_init(void) | |||
154 | bus_register_notifier(&amba_bustype, &highbank_amba_nb); | 146 | bus_register_notifier(&amba_bustype, &highbank_amba_nb); |
155 | 147 | ||
156 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 148 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
149 | |||
150 | if (psci_ops.cpu_suspend) | ||
151 | platform_device_register(&highbank_cpuidle_device); | ||
157 | } | 152 | } |
158 | 153 | ||
159 | static const char *highbank_match[] __initconst = { | 154 | static const char *highbank_match[] __initconst = { |
@@ -166,7 +161,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank") | |||
166 | #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) | 161 | #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) |
167 | .dma_zone_size = (4ULL * SZ_1G), | 162 | .dma_zone_size = (4ULL * SZ_1G), |
168 | #endif | 163 | #endif |
169 | .smp = smp_ops(highbank_smp_ops), | ||
170 | .init_irq = highbank_init_irq, | 164 | .init_irq = highbank_init_irq, |
171 | .init_machine = highbank_init, | 165 | .init_machine = highbank_init, |
172 | .dt_compat = highbank_match, | 166 | .dt_compat = highbank_match, |
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c deleted file mode 100644 index a019e4e86e51..000000000000 --- a/arch/arm/mach-highbank/hotplug.c +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Calxeda, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along with | ||
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #include <linux/kernel.h> | ||
17 | #include <asm/cacheflush.h> | ||
18 | |||
19 | #include "core.h" | ||
20 | #include "sysregs.h" | ||
21 | |||
22 | extern void secondary_startup(void); | ||
23 | |||
24 | /* | ||
25 | * platform-specific code to shutdown a CPU | ||
26 | * | ||
27 | */ | ||
28 | void __ref highbank_cpu_die(unsigned int cpu) | ||
29 | { | ||
30 | highbank_set_cpu_jump(cpu, phys_to_virt(0)); | ||
31 | |||
32 | flush_cache_louis(); | ||
33 | highbank_set_core_pwr(); | ||
34 | |||
35 | while (1) | ||
36 | cpu_do_idle(); | ||
37 | } | ||
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c deleted file mode 100644 index 32d75cf55cbc..000000000000 --- a/arch/arm/mach-highbank/platsmp.c +++ /dev/null | |||
@@ -1,68 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2010-2011 Calxeda, Inc. | ||
3 | * Based on platsmp.c, Copyright (C) 2002 ARM Ltd. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms and conditions of the GNU General Public License, | ||
7 | * version 2, as published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along with | ||
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
16 | */ | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/smp.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <asm/smp_scu.h> | ||
22 | |||
23 | #include "core.h" | ||
24 | |||
25 | extern void secondary_startup(void); | ||
26 | |||
27 | static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
28 | { | ||
29 | highbank_set_cpu_jump(cpu, secondary_startup); | ||
30 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); | ||
31 | return 0; | ||
32 | } | ||
33 | |||
34 | /* | ||
35 | * Initialise the CPU possible map early - this describes the CPUs | ||
36 | * which may be present or become present in the system. | ||
37 | */ | ||
38 | static void __init highbank_smp_init_cpus(void) | ||
39 | { | ||
40 | unsigned int i, ncores = 4; | ||
41 | |||
42 | /* sanity check */ | ||
43 | if (ncores > NR_CPUS) { | ||
44 | printk(KERN_WARNING | ||
45 | "highbank: no. of cores (%d) greater than configured " | ||
46 | "maximum of %d - clipping\n", | ||
47 | ncores, NR_CPUS); | ||
48 | ncores = NR_CPUS; | ||
49 | } | ||
50 | |||
51 | for (i = 0; i < ncores; i++) | ||
52 | set_cpu_possible(i, true); | ||
53 | } | ||
54 | |||
55 | static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) | ||
56 | { | ||
57 | if (scu_base_addr) | ||
58 | scu_enable(scu_base_addr); | ||
59 | } | ||
60 | |||
61 | struct smp_operations highbank_smp_ops __initdata = { | ||
62 | .smp_init_cpus = highbank_smp_init_cpus, | ||
63 | .smp_prepare_cpus = highbank_smp_prepare_cpus, | ||
64 | .smp_boot_secondary = highbank_boot_secondary, | ||
65 | #ifdef CONFIG_HOTPLUG_CPU | ||
66 | .cpu_die = highbank_cpu_die, | ||
67 | #endif | ||
68 | }; | ||
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c index 04eddb4f4380..7f2bd85eb935 100644 --- a/arch/arm/mach-highbank/pm.c +++ b/arch/arm/mach-highbank/pm.c | |||
@@ -16,27 +16,19 @@ | |||
16 | 16 | ||
17 | #include <linux/cpu_pm.h> | 17 | #include <linux/cpu_pm.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/io.h> | ||
20 | #include <linux/suspend.h> | 19 | #include <linux/suspend.h> |
21 | 20 | ||
22 | #include <asm/cacheflush.h> | ||
23 | #include <asm/proc-fns.h> | ||
24 | #include <asm/suspend.h> | 21 | #include <asm/suspend.h> |
25 | 22 | #include <asm/psci.h> | |
26 | #include "core.h" | ||
27 | #include "sysregs.h" | ||
28 | 23 | ||
29 | static int highbank_suspend_finish(unsigned long val) | 24 | static int highbank_suspend_finish(unsigned long val) |
30 | { | 25 | { |
31 | outer_flush_all(); | 26 | const struct psci_power_state ps = { |
32 | outer_disable(); | 27 | .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, |
33 | 28 | .affinity_level = 1, | |
34 | highbank_set_pwr_suspend(); | 29 | }; |
35 | |||
36 | cpu_do_idle(); | ||
37 | 30 | ||
38 | highbank_clear_pwr_request(); | 31 | return psci_ops.cpu_suspend(ps, __pa(cpu_resume)); |
39 | return 0; | ||
40 | } | 32 | } |
41 | 33 | ||
42 | static int highbank_pm_enter(suspend_state_t state) | 34 | static int highbank_pm_enter(suspend_state_t state) |
@@ -44,15 +36,11 @@ static int highbank_pm_enter(suspend_state_t state) | |||
44 | cpu_pm_enter(); | 36 | cpu_pm_enter(); |
45 | cpu_cluster_pm_enter(); | 37 | cpu_cluster_pm_enter(); |
46 | 38 | ||
47 | highbank_set_cpu_jump(0, cpu_resume); | ||
48 | cpu_suspend(0, highbank_suspend_finish); | 39 | cpu_suspend(0, highbank_suspend_finish); |
49 | 40 | ||
50 | cpu_cluster_pm_exit(); | 41 | cpu_cluster_pm_exit(); |
51 | cpu_pm_exit(); | 42 | cpu_pm_exit(); |
52 | 43 | ||
53 | highbank_smc1(0x102, 0x1); | ||
54 | if (scu_base_addr) | ||
55 | scu_enable(scu_base_addr); | ||
56 | return 0; | 44 | return 0; |
57 | } | 45 | } |
58 | 46 | ||
@@ -63,5 +51,8 @@ static const struct platform_suspend_ops highbank_pm_ops = { | |||
63 | 51 | ||
64 | void __init highbank_pm_init(void) | 52 | void __init highbank_pm_init(void) |
65 | { | 53 | { |
54 | if (!psci_ops.cpu_suspend) | ||
55 | return; | ||
56 | |||
66 | suspend_set_ops(&highbank_pm_ops); | 57 | suspend_set_ops(&highbank_pm_ops); |
67 | } | 58 | } |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index a91909b95601..7a6e6f710068 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
@@ -11,6 +11,7 @@ config ARCH_MXC | |||
11 | select GENERIC_IRQ_CHIP | 11 | select GENERIC_IRQ_CHIP |
12 | select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 | 12 | select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 |
13 | select MULTI_IRQ_HANDLER | 13 | select MULTI_IRQ_HANDLER |
14 | select SOC_BUS | ||
14 | select SPARSE_IRQ | 15 | select SPARSE_IRQ |
15 | select USE_OF | 16 | select USE_OF |
16 | help | 17 | help |
@@ -24,7 +25,7 @@ config MXC_IRQ_PRIOR | |||
24 | help | 25 | help |
25 | Select this if you want to use prioritized IRQ handling. | 26 | Select this if you want to use prioritized IRQ handling. |
26 | This feature prevents higher priority ISR to be interrupted | 27 | This feature prevents higher priority ISR to be interrupted |
27 | by lower priority IRQ even IRQF_DISABLED flag is not set. | 28 | by lower priority IRQ. |
28 | This may be useful in embedded applications, where are strong | 29 | This may be useful in embedded applications, where are strong |
29 | requirements for timing. | 30 | requirements for timing. |
30 | Say N here, unless you have a specialized requirement. | 31 | Say N here, unless you have a specialized requirement. |
@@ -793,6 +794,8 @@ config SOC_IMX6Q | |||
793 | select HAVE_IMX_SRC | 794 | select HAVE_IMX_SRC |
794 | select HAVE_SMP | 795 | select HAVE_SMP |
795 | select MFD_SYSCON | 796 | select MFD_SYSCON |
797 | select MIGHT_HAVE_PCI | ||
798 | select PCI_DOMAINS if PCI | ||
796 | select PINCTRL | 799 | select PINCTRL |
797 | select PINCTRL_IMX6Q | 800 | select PINCTRL_IMX6Q |
798 | select PL310_ERRATA_588369 if CACHE_PL310 | 801 | select PL310_ERRATA_588369 if CACHE_PL310 |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5383c589ad71..bbe1f5bb799c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
@@ -102,6 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o | |||
102 | 102 | ||
103 | ifeq ($(CONFIG_PM),y) | 103 | ifeq ($(CONFIG_PM),y) |
104 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o | 104 | obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o |
105 | # i.MX6SL reuses pm-imx6q.c | ||
106 | obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o | ||
105 | endif | 107 | endif |
106 | 108 | ||
107 | # i.MX5 based machines | 109 | # i.MX5 based machines |
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index ad3b755abb78..4a40bbb46183 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/mfd/syscon.h> | 16 | #include <linux/mfd/syscon.h> |
17 | #include <linux/regmap.h> | 17 | #include <linux/regmap.h> |
18 | #include "common.h" | 18 | #include "common.h" |
19 | #include "hardware.h" | ||
19 | 20 | ||
20 | #define REG_SET 0x4 | 21 | #define REG_SET 0x4 |
21 | #define REG_CLR 0x8 | 22 | #define REG_CLR 0x8 |
@@ -26,6 +27,7 @@ | |||
26 | #define ANADIG_USB1_CHRG_DETECT 0x1b0 | 27 | #define ANADIG_USB1_CHRG_DETECT 0x1b0 |
27 | #define ANADIG_USB2_CHRG_DETECT 0x210 | 28 | #define ANADIG_USB2_CHRG_DETECT 0x210 |
28 | #define ANADIG_DIGPROG 0x260 | 29 | #define ANADIG_DIGPROG 0x260 |
30 | #define ANADIG_DIGPROG_IMX6SL 0x280 | ||
29 | 31 | ||
30 | #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 | 32 | #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 |
31 | #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 | 33 | #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 |
@@ -76,21 +78,38 @@ static void imx_anatop_usb_chrg_detect_disable(void) | |||
76 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); | 78 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); |
77 | } | 79 | } |
78 | 80 | ||
79 | u32 imx_anatop_get_digprog(void) | 81 | void __init imx_init_revision_from_anatop(void) |
80 | { | 82 | { |
81 | struct device_node *np; | 83 | struct device_node *np; |
82 | void __iomem *anatop_base; | 84 | void __iomem *anatop_base; |
83 | static u32 digprog; | 85 | unsigned int revision; |
84 | 86 | u32 digprog; | |
85 | if (digprog) | 87 | u16 offset = ANADIG_DIGPROG; |
86 | return digprog; | ||
87 | 88 | ||
88 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | 89 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); |
89 | anatop_base = of_iomap(np, 0); | 90 | anatop_base = of_iomap(np, 0); |
90 | WARN_ON(!anatop_base); | 91 | WARN_ON(!anatop_base); |
91 | digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG); | 92 | if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) |
93 | offset = ANADIG_DIGPROG_IMX6SL; | ||
94 | digprog = readl_relaxed(anatop_base + offset); | ||
95 | iounmap(anatop_base); | ||
96 | |||
97 | switch (digprog & 0xff) { | ||
98 | case 0: | ||
99 | revision = IMX_CHIP_REVISION_1_0; | ||
100 | break; | ||
101 | case 1: | ||
102 | revision = IMX_CHIP_REVISION_1_1; | ||
103 | break; | ||
104 | case 2: | ||
105 | revision = IMX_CHIP_REVISION_1_2; | ||
106 | break; | ||
107 | default: | ||
108 | revision = IMX_CHIP_REVISION_UNKNOWN; | ||
109 | } | ||
92 | 110 | ||
93 | return digprog; | 111 | mxc_set_cpu_type(digprog >> 16 & 0xff); |
112 | imx_set_soc_revision(revision); | ||
94 | } | 113 | } |
95 | 114 | ||
96 | void __init imx_anatop_init(void) | 115 | void __init imx_anatop_init(void) |
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index ceaac9cd7b42..ce37af26ff8c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
@@ -14,6 +14,9 @@ | |||
14 | #include <linux/clk-provider.h> | 14 | #include <linux/clk-provider.h> |
15 | #include <linux/of.h> | 15 | #include <linux/of.h> |
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <linux/of.h> | ||
18 | #include <linux/of_address.h> | ||
19 | #include <linux/of_irq.h> | ||
17 | 20 | ||
18 | #include "crm-regs-imx5.h" | 21 | #include "crm-regs-imx5.h" |
19 | #include "clk.h" | 22 | #include "clk.h" |
@@ -472,8 +475,9 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); | |||
472 | 475 | ||
473 | static void __init mx53_clocks_init(struct device_node *np) | 476 | static void __init mx53_clocks_init(struct device_node *np) |
474 | { | 477 | { |
475 | int i; | 478 | int i, irq; |
476 | unsigned long r; | 479 | unsigned long r; |
480 | void __iomem *base; | ||
477 | 481 | ||
478 | clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); | 482 | clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); |
479 | clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | 483 | clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); |
@@ -559,14 +563,17 @@ static void __init mx53_clocks_init(struct device_node *np) | |||
559 | clk_set_rate(clk[esdhc_a_podf], 200000000); | 563 | clk_set_rate(clk[esdhc_a_podf], 200000000); |
560 | clk_set_rate(clk[esdhc_b_podf], 200000000); | 564 | clk_set_rate(clk[esdhc_b_podf], 200000000); |
561 | 565 | ||
562 | /* System timer */ | ||
563 | mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); | ||
564 | |||
565 | clk_prepare_enable(clk[iim_gate]); | 566 | clk_prepare_enable(clk[iim_gate]); |
566 | imx_print_silicon_rev("i.MX53", mx53_revision()); | 567 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
567 | clk_disable_unprepare(clk[iim_gate]); | 568 | clk_disable_unprepare(clk[iim_gate]); |
568 | 569 | ||
569 | r = clk_round_rate(clk[usboh3_per_gate], 54000000); | 570 | r = clk_round_rate(clk[usboh3_per_gate], 54000000); |
570 | clk_set_rate(clk[usboh3_per_gate], r); | 571 | clk_set_rate(clk[usboh3_per_gate], r); |
572 | |||
573 | np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); | ||
574 | base = of_iomap(np, 0); | ||
575 | WARN_ON(!base); | ||
576 | irq = irq_of_parse_and_map(np, 0); | ||
577 | mxc_timer_init(base, irq); | ||
571 | } | 578 | } |
572 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); | 579 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); |
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 9181a241d3a8..d756d91fd741 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
@@ -14,7 +14,6 @@ | |||
14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
15 | #include <linux/clk.h> | 15 | #include <linux/clk.h> |
16 | #include <linux/clkdev.h> | 16 | #include <linux/clkdev.h> |
17 | #include <linux/delay.h> | ||
18 | #include <linux/err.h> | 17 | #include <linux/err.h> |
19 | #include <linux/io.h> | 18 | #include <linux/io.h> |
20 | #include <linux/of.h> | 19 | #include <linux/of.h> |
@@ -25,155 +24,6 @@ | |||
25 | #include "common.h" | 24 | #include "common.h" |
26 | #include "hardware.h" | 25 | #include "hardware.h" |
27 | 26 | ||
28 | #define CCR 0x0 | ||
29 | #define BM_CCR_WB_COUNT (0x7 << 16) | ||
30 | #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) | ||
31 | #define BM_CCR_RBC_EN (0x1 << 27) | ||
32 | |||
33 | #define CCGR0 0x68 | ||
34 | #define CCGR1 0x6c | ||
35 | #define CCGR2 0x70 | ||
36 | #define CCGR3 0x74 | ||
37 | #define CCGR4 0x78 | ||
38 | #define CCGR5 0x7c | ||
39 | #define CCGR6 0x80 | ||
40 | #define CCGR7 0x84 | ||
41 | |||
42 | #define CLPCR 0x54 | ||
43 | #define BP_CLPCR_LPM 0 | ||
44 | #define BM_CLPCR_LPM (0x3 << 0) | ||
45 | #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) | ||
46 | #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | ||
47 | #define BM_CLPCR_SBYOS (0x1 << 6) | ||
48 | #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) | ||
49 | #define BM_CLPCR_VSTBY (0x1 << 8) | ||
50 | #define BP_CLPCR_STBY_COUNT 9 | ||
51 | #define BM_CLPCR_STBY_COUNT (0x3 << 9) | ||
52 | #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) | ||
53 | #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) | ||
54 | #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) | ||
55 | #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) | ||
56 | #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) | ||
57 | #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) | ||
58 | #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) | ||
59 | #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) | ||
60 | #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) | ||
61 | #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) | ||
62 | #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) | ||
63 | |||
64 | #define CGPR 0x64 | ||
65 | #define BM_CGPR_CHICKEN_BIT (0x1 << 17) | ||
66 | |||
67 | static void __iomem *ccm_base; | ||
68 | |||
69 | void imx6q_set_chicken_bit(void) | ||
70 | { | ||
71 | u32 val = readl_relaxed(ccm_base + CGPR); | ||
72 | |||
73 | val |= BM_CGPR_CHICKEN_BIT; | ||
74 | writel_relaxed(val, ccm_base + CGPR); | ||
75 | } | ||
76 | |||
77 | static void imx6q_enable_rbc(bool enable) | ||
78 | { | ||
79 | u32 val; | ||
80 | static bool last_rbc_mode; | ||
81 | |||
82 | if (last_rbc_mode == enable) | ||
83 | return; | ||
84 | /* | ||
85 | * need to mask all interrupts in GPC before | ||
86 | * operating RBC configurations | ||
87 | */ | ||
88 | imx_gpc_mask_all(); | ||
89 | |||
90 | /* configure RBC enable bit */ | ||
91 | val = readl_relaxed(ccm_base + CCR); | ||
92 | val &= ~BM_CCR_RBC_EN; | ||
93 | val |= enable ? BM_CCR_RBC_EN : 0; | ||
94 | writel_relaxed(val, ccm_base + CCR); | ||
95 | |||
96 | /* configure RBC count */ | ||
97 | val = readl_relaxed(ccm_base + CCR); | ||
98 | val &= ~BM_CCR_RBC_BYPASS_COUNT; | ||
99 | val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; | ||
100 | writel(val, ccm_base + CCR); | ||
101 | |||
102 | /* | ||
103 | * need to delay at least 2 cycles of CKIL(32K) | ||
104 | * due to hardware design requirement, which is | ||
105 | * ~61us, here we use 65us for safe | ||
106 | */ | ||
107 | udelay(65); | ||
108 | |||
109 | /* restore GPC interrupt mask settings */ | ||
110 | imx_gpc_restore_all(); | ||
111 | |||
112 | last_rbc_mode = enable; | ||
113 | } | ||
114 | |||
115 | static void imx6q_enable_wb(bool enable) | ||
116 | { | ||
117 | u32 val; | ||
118 | static bool last_wb_mode; | ||
119 | |||
120 | if (last_wb_mode == enable) | ||
121 | return; | ||
122 | |||
123 | /* configure well bias enable bit */ | ||
124 | val = readl_relaxed(ccm_base + CLPCR); | ||
125 | val &= ~BM_CLPCR_WB_PER_AT_LPM; | ||
126 | val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; | ||
127 | writel_relaxed(val, ccm_base + CLPCR); | ||
128 | |||
129 | /* configure well bias count */ | ||
130 | val = readl_relaxed(ccm_base + CCR); | ||
131 | val &= ~BM_CCR_WB_COUNT; | ||
132 | val |= enable ? BM_CCR_WB_COUNT : 0; | ||
133 | writel_relaxed(val, ccm_base + CCR); | ||
134 | |||
135 | last_wb_mode = enable; | ||
136 | } | ||
137 | |||
138 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) | ||
139 | { | ||
140 | u32 val = readl_relaxed(ccm_base + CLPCR); | ||
141 | |||
142 | val &= ~BM_CLPCR_LPM; | ||
143 | switch (mode) { | ||
144 | case WAIT_CLOCKED: | ||
145 | imx6q_enable_wb(false); | ||
146 | imx6q_enable_rbc(false); | ||
147 | break; | ||
148 | case WAIT_UNCLOCKED: | ||
149 | val |= 0x1 << BP_CLPCR_LPM; | ||
150 | val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; | ||
151 | break; | ||
152 | case STOP_POWER_ON: | ||
153 | val |= 0x2 << BP_CLPCR_LPM; | ||
154 | break; | ||
155 | case WAIT_UNCLOCKED_POWER_OFF: | ||
156 | val |= 0x1 << BP_CLPCR_LPM; | ||
157 | val &= ~BM_CLPCR_VSTBY; | ||
158 | val &= ~BM_CLPCR_SBYOS; | ||
159 | break; | ||
160 | case STOP_POWER_OFF: | ||
161 | val |= 0x2 << BP_CLPCR_LPM; | ||
162 | val |= 0x3 << BP_CLPCR_STBY_COUNT; | ||
163 | val |= BM_CLPCR_VSTBY; | ||
164 | val |= BM_CLPCR_SBYOS; | ||
165 | imx6q_enable_wb(true); | ||
166 | imx6q_enable_rbc(true); | ||
167 | break; | ||
168 | default: | ||
169 | return -EINVAL; | ||
170 | } | ||
171 | |||
172 | writel_relaxed(val, ccm_base + CLPCR); | ||
173 | |||
174 | return 0; | ||
175 | } | ||
176 | |||
177 | static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; | 27 | static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; |
178 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | 28 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; |
179 | static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; | 29 | static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; |
@@ -182,7 +32,7 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | |||
182 | static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; | 32 | static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; |
183 | static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; | 33 | static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; |
184 | static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; | 34 | static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; |
185 | static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; | 35 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; |
186 | static const char *gpu_axi_sels[] = { "axi", "ahb", }; | 36 | static const char *gpu_axi_sels[] = { "axi", "ahb", }; |
187 | static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; | 37 | static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; |
188 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; | 38 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; |
@@ -196,7 +46,7 @@ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di | |||
196 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | 46 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; |
197 | static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; | 47 | static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; |
198 | static const char *pcie_axi_sels[] = { "axi", "ahb", }; | 48 | static const char *pcie_axi_sels[] = { "axi", "ahb", }; |
199 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; | 49 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; |
200 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; | 50 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
201 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; | 51 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; |
202 | static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; | 52 | static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; |
@@ -205,7 +55,7 @@ static const char *vdo_axi_sels[] = { "axi", "ahb", }; | |||
205 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | 55 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
206 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", | 56 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", |
207 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", | 57 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", |
208 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; | 58 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; |
209 | static const char *cko2_sels[] = { | 59 | static const char *cko2_sels[] = { |
210 | "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", | 60 | "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", |
211 | "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", | 61 | "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", |
@@ -217,6 +67,11 @@ static const char *cko2_sels[] = { | |||
217 | "uart_serial", "spdif", "asrc", "hsi_tx", | 67 | "uart_serial", "spdif", "asrc", "hsi_tx", |
218 | }; | 68 | }; |
219 | static const char *cko_sels[] = { "cko1", "cko2", }; | 69 | static const char *cko_sels[] = { "cko1", "cko2", }; |
70 | static const char *lvds_sels[] = { | ||
71 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | ||
72 | "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", | ||
73 | "pcie_ref", "sata_ref", | ||
74 | }; | ||
220 | 75 | ||
221 | enum mx6q_clks { | 76 | enum mx6q_clks { |
222 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, | 77 | dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, |
@@ -251,7 +106,8 @@ enum mx6q_clks { | |||
251 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, | 106 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, |
252 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, | 107 | sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, |
253 | usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, | 108 | usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, |
254 | spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max | 109 | spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, |
110 | lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max | ||
255 | }; | 111 | }; |
256 | 112 | ||
257 | static struct clk *clk[clk_max]; | 113 | static struct clk *clk[clk_max]; |
@@ -300,7 +156,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
300 | WARN_ON(!base); | 156 | WARN_ON(!base); |
301 | 157 | ||
302 | /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ | 158 | /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ |
303 | if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) { | 159 | if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { |
304 | post_div_table[1].div = 1; | 160 | post_div_table[1].div = 1; |
305 | post_div_table[2].div = 1; | 161 | post_div_table[2].div = 1; |
306 | video_div_table[1].div = 1; | 162 | video_div_table[1].div = 1; |
@@ -342,6 +198,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
342 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, | 198 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, |
343 | &imx_ccm_lock); | 199 | &imx_ccm_lock); |
344 | 200 | ||
201 | clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | ||
202 | clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | ||
203 | |||
204 | /* | ||
205 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be | ||
206 | * independently configured as clock inputs or outputs. We treat | ||
207 | * the "output_enable" bit as a gate, even though it's really just | ||
208 | * enabling clock output. | ||
209 | */ | ||
210 | clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); | ||
211 | clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); | ||
212 | |||
345 | /* name parent_name reg idx */ | 213 | /* name parent_name reg idx */ |
346 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | 214 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); |
347 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | 215 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); |
@@ -359,13 +227,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
359 | clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); | 227 | clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); |
360 | 228 | ||
361 | clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); | 229 | clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
230 | clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); | ||
362 | clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); | 231 | clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
363 | clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | 232 | clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); |
364 | 233 | ||
365 | np = ccm_node; | 234 | np = ccm_node; |
366 | base = of_iomap(np, 0); | 235 | base = of_iomap(np, 0); |
367 | WARN_ON(!base); | 236 | WARN_ON(!base); |
368 | ccm_base = base; | 237 | |
238 | imx6q_pm_set_ccm_base(base); | ||
369 | 239 | ||
370 | /* name reg shift width parent_names num_parents */ | 240 | /* name reg shift width parent_names num_parents */ |
371 | clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | 241 | clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
@@ -573,7 +443,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
573 | clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); | 443 | clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); |
574 | clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); | 444 | clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); |
575 | 445 | ||
576 | if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { | 446 | if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || |
447 | cpu_is_imx6dl()) { | ||
577 | clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); | 448 | clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); |
578 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); | 449 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); |
579 | } | 450 | } |
@@ -603,8 +474,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
603 | if (ret) | 474 | if (ret) |
604 | pr_warn("failed to set up CLKO: %d\n", ret); | 475 | pr_warn("failed to set up CLKO: %d\n", ret); |
605 | 476 | ||
606 | /* Set initial power mode */ | 477 | /* All existing boards with PCIe use LVDS1 */ |
607 | imx6q_set_lpm(WAIT_CLOCKED); | 478 | if (IS_ENABLED(CONFIG_PCI_IMX6)) |
479 | clk_set_parent(clk[lvds1_sel], clk[sata_ref]); | ||
608 | 480 | ||
609 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); | 481 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); |
610 | base = of_iomap(np, 0); | 482 | base = of_iomap(np, 0); |
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index a5c3c5d21aee..c0c4ef55e35b 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c | |||
@@ -127,6 +127,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) | |||
127 | base = of_iomap(np, 0); | 127 | base = of_iomap(np, 0); |
128 | WARN_ON(!base); | 128 | WARN_ON(!base); |
129 | 129 | ||
130 | /* Reuse imx6q pm code */ | ||
131 | imx6q_pm_set_ccm_base(base); | ||
132 | |||
130 | /* name reg shift width parent_names num_parents */ | 133 | /* name reg shift width parent_names num_parents */ |
131 | clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | 134 | clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
132 | clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | 135 | clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); |
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 28e8ca0871e8..7cbe22d0c6e9 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h | |||
@@ -13,70 +13,73 @@ | |||
13 | 13 | ||
14 | #include <linux/reboot.h> | 14 | #include <linux/reboot.h> |
15 | 15 | ||
16 | struct irq_data; | ||
16 | struct platform_device; | 17 | struct platform_device; |
17 | struct pt_regs; | 18 | struct pt_regs; |
18 | struct clk; | 19 | struct clk; |
19 | enum mxc_cpu_pwr_mode; | 20 | enum mxc_cpu_pwr_mode; |
20 | 21 | ||
21 | extern void mx1_map_io(void); | 22 | void mx1_map_io(void); |
22 | extern void mx21_map_io(void); | 23 | void mx21_map_io(void); |
23 | extern void mx25_map_io(void); | 24 | void mx25_map_io(void); |
24 | extern void mx27_map_io(void); | 25 | void mx27_map_io(void); |
25 | extern void mx31_map_io(void); | 26 | void mx31_map_io(void); |
26 | extern void mx35_map_io(void); | 27 | void mx35_map_io(void); |
27 | extern void mx51_map_io(void); | 28 | void mx51_map_io(void); |
28 | extern void mx53_map_io(void); | 29 | void mx53_map_io(void); |
29 | extern void imx1_init_early(void); | 30 | void imx1_init_early(void); |
30 | extern void imx21_init_early(void); | 31 | void imx21_init_early(void); |
31 | extern void imx25_init_early(void); | 32 | void imx25_init_early(void); |
32 | extern void imx27_init_early(void); | 33 | void imx27_init_early(void); |
33 | extern void imx31_init_early(void); | 34 | void imx31_init_early(void); |
34 | extern void imx35_init_early(void); | 35 | void imx35_init_early(void); |
35 | extern void imx51_init_early(void); | 36 | void imx51_init_early(void); |
36 | extern void imx53_init_early(void); | 37 | void imx53_init_early(void); |
37 | extern void mxc_init_irq(void __iomem *); | 38 | void mxc_init_irq(void __iomem *); |
38 | extern void tzic_init_irq(void __iomem *); | 39 | void tzic_init_irq(void __iomem *); |
39 | extern void mx1_init_irq(void); | 40 | void mx1_init_irq(void); |
40 | extern void mx21_init_irq(void); | 41 | void mx21_init_irq(void); |
41 | extern void mx25_init_irq(void); | 42 | void mx25_init_irq(void); |
42 | extern void mx27_init_irq(void); | 43 | void mx27_init_irq(void); |
43 | extern void mx31_init_irq(void); | 44 | void mx31_init_irq(void); |
44 | extern void mx35_init_irq(void); | 45 | void mx35_init_irq(void); |
45 | extern void mx51_init_irq(void); | 46 | void mx51_init_irq(void); |
46 | extern void mx53_init_irq(void); | 47 | void mx53_init_irq(void); |
47 | extern void imx1_soc_init(void); | 48 | void imx1_soc_init(void); |
48 | extern void imx21_soc_init(void); | 49 | void imx21_soc_init(void); |
49 | extern void imx25_soc_init(void); | 50 | void imx25_soc_init(void); |
50 | extern void imx27_soc_init(void); | 51 | void imx27_soc_init(void); |
51 | extern void imx31_soc_init(void); | 52 | void imx31_soc_init(void); |
52 | extern void imx35_soc_init(void); | 53 | void imx35_soc_init(void); |
53 | extern void imx51_soc_init(void); | 54 | void imx51_soc_init(void); |
54 | extern void imx51_init_late(void); | 55 | void imx51_init_late(void); |
55 | extern void imx53_init_late(void); | 56 | void imx53_init_late(void); |
56 | extern void epit_timer_init(void __iomem *base, int irq); | 57 | void epit_timer_init(void __iomem *base, int irq); |
57 | extern void mxc_timer_init(void __iomem *, int); | 58 | void mxc_timer_init(void __iomem *, int); |
58 | extern int mx1_clocks_init(unsigned long fref); | 59 | int mx1_clocks_init(unsigned long fref); |
59 | extern int mx21_clocks_init(unsigned long lref, unsigned long fref); | 60 | int mx21_clocks_init(unsigned long lref, unsigned long fref); |
60 | extern int mx25_clocks_init(void); | 61 | int mx25_clocks_init(void); |
61 | extern int mx27_clocks_init(unsigned long fref); | 62 | int mx27_clocks_init(unsigned long fref); |
62 | extern int mx31_clocks_init(unsigned long fref); | 63 | int mx31_clocks_init(unsigned long fref); |
63 | extern int mx35_clocks_init(void); | 64 | int mx35_clocks_init(void); |
64 | extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, | 65 | int mx51_clocks_init(unsigned long ckil, unsigned long osc, |
65 | unsigned long ckih1, unsigned long ckih2); | 66 | unsigned long ckih1, unsigned long ckih2); |
66 | extern int mx25_clocks_init_dt(void); | 67 | int mx25_clocks_init_dt(void); |
67 | extern int mx27_clocks_init_dt(void); | 68 | int mx27_clocks_init_dt(void); |
68 | extern int mx31_clocks_init_dt(void); | 69 | int mx31_clocks_init_dt(void); |
69 | extern struct platform_device *mxc_register_gpio(char *name, int id, | 70 | struct platform_device *mxc_register_gpio(char *name, int id, |
70 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); | 71 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
71 | extern void mxc_set_cpu_type(unsigned int type); | 72 | void mxc_set_cpu_type(unsigned int type); |
72 | extern void mxc_restart(enum reboot_mode, const char *); | 73 | void mxc_restart(enum reboot_mode, const char *); |
73 | extern void mxc_arch_reset_init(void __iomem *); | 74 | void mxc_arch_reset_init(void __iomem *); |
74 | extern void mxc_arch_reset_init_dt(void); | 75 | void mxc_arch_reset_init_dt(void); |
75 | extern int mx53_revision(void); | 76 | int mx53_revision(void); |
76 | extern int imx6q_revision(void); | 77 | void imx_set_aips(void __iomem *); |
77 | extern int mx53_display_revision(void); | 78 | int mxc_device_init(void); |
78 | extern void imx_set_aips(void __iomem *); | 79 | void imx_set_soc_revision(unsigned int rev); |
79 | extern int mxc_device_init(void); | 80 | unsigned int imx_get_soc_revision(void); |
81 | void imx_init_revision_from_anatop(void); | ||
82 | struct device *imx_soc_device_init(void); | ||
80 | 83 | ||
81 | enum mxc_cpu_pwr_mode { | 84 | enum mxc_cpu_pwr_mode { |
82 | WAIT_CLOCKED, /* wfi only */ | 85 | WAIT_CLOCKED, /* wfi only */ |
@@ -93,8 +96,8 @@ enum mx3_cpu_pwr_mode { | |||
93 | MX3_SLEEP, | 96 | MX3_SLEEP, |
94 | }; | 97 | }; |
95 | 98 | ||
96 | extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); | 99 | void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); |
97 | extern void imx_print_silicon_rev(const char *cpu, int srev); | 100 | void imx_print_silicon_rev(const char *cpu, int srev); |
98 | 101 | ||
99 | void avic_handle_irq(struct pt_regs *); | 102 | void avic_handle_irq(struct pt_regs *); |
100 | void tzic_handle_irq(struct pt_regs *); | 103 | void tzic_handle_irq(struct pt_regs *); |
@@ -108,54 +111,61 @@ void tzic_handle_irq(struct pt_regs *); | |||
108 | #define imx51_handle_irq tzic_handle_irq | 111 | #define imx51_handle_irq tzic_handle_irq |
109 | #define imx53_handle_irq tzic_handle_irq | 112 | #define imx53_handle_irq tzic_handle_irq |
110 | 113 | ||
111 | extern void imx_enable_cpu(int cpu, bool enable); | 114 | void imx_enable_cpu(int cpu, bool enable); |
112 | extern void imx_set_cpu_jump(int cpu, void *jump_addr); | 115 | void imx_set_cpu_jump(int cpu, void *jump_addr); |
113 | extern u32 imx_get_cpu_arg(int cpu); | 116 | u32 imx_get_cpu_arg(int cpu); |
114 | extern void imx_set_cpu_arg(int cpu, u32 arg); | 117 | void imx_set_cpu_arg(int cpu, u32 arg); |
115 | extern void v7_cpu_resume(void); | 118 | void v7_cpu_resume(void); |
116 | #ifdef CONFIG_SMP | 119 | #ifdef CONFIG_SMP |
117 | extern void v7_secondary_startup(void); | 120 | void v7_secondary_startup(void); |
118 | extern void imx_scu_map_io(void); | 121 | void imx_scu_map_io(void); |
119 | extern void imx_smp_prepare(void); | 122 | void imx_smp_prepare(void); |
120 | extern void imx_scu_standby_enable(void); | 123 | void imx_scu_standby_enable(void); |
121 | #else | 124 | #else |
122 | static inline void imx_scu_map_io(void) {} | 125 | static inline void imx_scu_map_io(void) {} |
123 | static inline void imx_smp_prepare(void) {} | 126 | static inline void imx_smp_prepare(void) {} |
124 | static inline void imx_scu_standby_enable(void) {} | 127 | static inline void imx_scu_standby_enable(void) {} |
125 | #endif | 128 | #endif |
126 | extern void imx_src_init(void); | 129 | void imx_src_init(void); |
127 | extern void imx_src_prepare_restart(void); | 130 | #ifdef CONFIG_HAVE_IMX_SRC |
128 | extern void imx_gpc_init(void); | 131 | void imx_src_prepare_restart(void); |
129 | extern void imx_gpc_pre_suspend(void); | 132 | #else |
130 | extern void imx_gpc_post_resume(void); | 133 | static inline void imx_src_prepare_restart(void) {} |
131 | extern void imx_gpc_mask_all(void); | 134 | #endif |
132 | extern void imx_gpc_restore_all(void); | 135 | void imx_gpc_init(void); |
133 | extern void imx_anatop_init(void); | 136 | void imx_gpc_pre_suspend(void); |
134 | extern void imx_anatop_pre_suspend(void); | 137 | void imx_gpc_post_resume(void); |
135 | extern void imx_anatop_post_resume(void); | 138 | void imx_gpc_mask_all(void); |
136 | extern u32 imx_anatop_get_digprog(void); | 139 | void imx_gpc_restore_all(void); |
137 | extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | 140 | void imx_gpc_irq_mask(struct irq_data *d); |
138 | extern void imx6q_set_chicken_bit(void); | 141 | void imx_gpc_irq_unmask(struct irq_data *d); |
139 | 142 | void imx_anatop_init(void); | |
140 | extern void imx_cpu_die(unsigned int cpu); | 143 | void imx_anatop_pre_suspend(void); |
141 | extern int imx_cpu_kill(unsigned int cpu); | 144 | void imx_anatop_post_resume(void); |
145 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); | ||
146 | void imx6q_set_chicken_bit(void); | ||
147 | |||
148 | void imx_cpu_die(unsigned int cpu); | ||
149 | int imx_cpu_kill(unsigned int cpu); | ||
142 | 150 | ||
143 | #ifdef CONFIG_PM | 151 | #ifdef CONFIG_PM |
144 | extern void imx6q_pm_init(void); | 152 | void imx6q_pm_init(void); |
145 | extern void imx5_pm_init(void); | 153 | void imx6q_pm_set_ccm_base(void __iomem *base); |
154 | void imx5_pm_init(void); | ||
146 | #else | 155 | #else |
147 | static inline void imx6q_pm_init(void) {} | 156 | static inline void imx6q_pm_init(void) {} |
157 | static inline void imx6q_pm_set_ccm_base(void __iomem *base) {} | ||
148 | static inline void imx5_pm_init(void) {} | 158 | static inline void imx5_pm_init(void) {} |
149 | #endif | 159 | #endif |
150 | 160 | ||
151 | #ifdef CONFIG_NEON | 161 | #ifdef CONFIG_NEON |
152 | extern int mx51_neon_fixup(void); | 162 | int mx51_neon_fixup(void); |
153 | #else | 163 | #else |
154 | static inline int mx51_neon_fixup(void) { return 0; } | 164 | static inline int mx51_neon_fixup(void) { return 0; } |
155 | #endif | 165 | #endif |
156 | 166 | ||
157 | #ifdef CONFIG_CACHE_L2X0 | 167 | #ifdef CONFIG_CACHE_L2X0 |
158 | extern void imx_init_l2cache(void); | 168 | void imx_init_l2cache(void); |
159 | #else | 169 | #else |
160 | static inline void imx_init_l2cache(void) {} | 170 | static inline void imx_init_l2cache(void) {} |
161 | #endif | 171 | #endif |
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index e70e3acbf9bd..ba3b498a67ec 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c | |||
@@ -1,6 +1,9 @@ | |||
1 | 1 | #include <linux/err.h> | |
2 | #include <linux/module.h> | 2 | #include <linux/module.h> |
3 | #include <linux/io.h> | 3 | #include <linux/io.h> |
4 | #include <linux/of.h> | ||
5 | #include <linux/slab.h> | ||
6 | #include <linux/sys_soc.h> | ||
4 | 7 | ||
5 | #include "hardware.h" | 8 | #include "hardware.h" |
6 | #include "common.h" | 9 | #include "common.h" |
@@ -8,11 +11,23 @@ | |||
8 | unsigned int __mxc_cpu_type; | 11 | unsigned int __mxc_cpu_type; |
9 | EXPORT_SYMBOL(__mxc_cpu_type); | 12 | EXPORT_SYMBOL(__mxc_cpu_type); |
10 | 13 | ||
14 | static unsigned int imx_soc_revision; | ||
15 | |||
11 | void mxc_set_cpu_type(unsigned int type) | 16 | void mxc_set_cpu_type(unsigned int type) |
12 | { | 17 | { |
13 | __mxc_cpu_type = type; | 18 | __mxc_cpu_type = type; |
14 | } | 19 | } |
15 | 20 | ||
21 | void imx_set_soc_revision(unsigned int rev) | ||
22 | { | ||
23 | imx_soc_revision = rev; | ||
24 | } | ||
25 | |||
26 | unsigned int imx_get_soc_revision(void) | ||
27 | { | ||
28 | return imx_soc_revision; | ||
29 | } | ||
30 | |||
16 | void imx_print_silicon_rev(const char *cpu, int srev) | 31 | void imx_print_silicon_rev(const char *cpu, int srev) |
17 | { | 32 | { |
18 | if (srev == IMX_CHIP_REVISION_UNKNOWN) | 33 | if (srev == IMX_CHIP_REVISION_UNKNOWN) |
@@ -44,3 +59,81 @@ void __init imx_set_aips(void __iomem *base) | |||
44 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | 59 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; |
45 | __raw_writel(reg, base + 0x50); | 60 | __raw_writel(reg, base + 0x50); |
46 | } | 61 | } |
62 | |||
63 | struct device * __init imx_soc_device_init(void) | ||
64 | { | ||
65 | struct soc_device_attribute *soc_dev_attr; | ||
66 | struct soc_device *soc_dev; | ||
67 | struct device_node *root; | ||
68 | const char *soc_id; | ||
69 | int ret; | ||
70 | |||
71 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | ||
72 | if (!soc_dev_attr) | ||
73 | return NULL; | ||
74 | |||
75 | soc_dev_attr->family = "Freescale i.MX"; | ||
76 | |||
77 | root = of_find_node_by_path("/"); | ||
78 | ret = of_property_read_string(root, "model", &soc_dev_attr->machine); | ||
79 | of_node_put(root); | ||
80 | if (ret) | ||
81 | goto free_soc; | ||
82 | |||
83 | switch (__mxc_cpu_type) { | ||
84 | case MXC_CPU_MX1: | ||
85 | soc_id = "i.MX1"; | ||
86 | break; | ||
87 | case MXC_CPU_MX21: | ||
88 | soc_id = "i.MX21"; | ||
89 | break; | ||
90 | case MXC_CPU_MX25: | ||
91 | soc_id = "i.MX25"; | ||
92 | break; | ||
93 | case MXC_CPU_MX27: | ||
94 | soc_id = "i.MX27"; | ||
95 | break; | ||
96 | case MXC_CPU_MX31: | ||
97 | soc_id = "i.MX31"; | ||
98 | break; | ||
99 | case MXC_CPU_MX35: | ||
100 | soc_id = "i.MX35"; | ||
101 | break; | ||
102 | case MXC_CPU_MX51: | ||
103 | soc_id = "i.MX51"; | ||
104 | break; | ||
105 | case MXC_CPU_MX53: | ||
106 | soc_id = "i.MX53"; | ||
107 | break; | ||
108 | case MXC_CPU_IMX6SL: | ||
109 | soc_id = "i.MX6SL"; | ||
110 | break; | ||
111 | case MXC_CPU_IMX6DL: | ||
112 | soc_id = "i.MX6DL"; | ||
113 | break; | ||
114 | case MXC_CPU_IMX6Q: | ||
115 | soc_id = "i.MX6Q"; | ||
116 | break; | ||
117 | default: | ||
118 | soc_id = "Unknown"; | ||
119 | } | ||
120 | soc_dev_attr->soc_id = soc_id; | ||
121 | |||
122 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", | ||
123 | (imx_soc_revision >> 4) & 0xf, | ||
124 | imx_soc_revision & 0xf); | ||
125 | if (!soc_dev_attr->revision) | ||
126 | goto free_soc; | ||
127 | |||
128 | soc_dev = soc_device_register(soc_dev_attr); | ||
129 | if (IS_ERR(soc_dev)) | ||
130 | goto free_rev; | ||
131 | |||
132 | return soc_device_to_device(soc_dev); | ||
133 | |||
134 | free_rev: | ||
135 | kfree(soc_dev_attr->revision); | ||
136 | free_soc: | ||
137 | kfree(soc_dev_attr); | ||
138 | return NULL; | ||
139 | } | ||
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c index e02de188ae83..074b1a81ba76 100644 --- a/arch/arm/mach-imx/epit.c +++ b/arch/arm/mach-imx/epit.c | |||
@@ -171,7 +171,7 @@ static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) | |||
171 | 171 | ||
172 | static struct irqaction epit_timer_irq = { | 172 | static struct irqaction epit_timer_irq = { |
173 | .name = "i.MX EPIT Timer Tick", | 173 | .name = "i.MX EPIT Timer Tick", |
174 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 174 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
175 | .handler = epit_timer_interrupt, | 175 | .handler = epit_timer_interrupt, |
176 | }; | 176 | }; |
177 | 177 | ||
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 44a65e9ff1fc..586e0171a652 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c | |||
@@ -90,7 +90,7 @@ void imx_gpc_restore_all(void) | |||
90 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); | 90 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); |
91 | } | 91 | } |
92 | 92 | ||
93 | static void imx_gpc_irq_unmask(struct irq_data *d) | 93 | void imx_gpc_irq_unmask(struct irq_data *d) |
94 | { | 94 | { |
95 | void __iomem *reg; | 95 | void __iomem *reg; |
96 | u32 val; | 96 | u32 val; |
@@ -105,7 +105,7 @@ static void imx_gpc_irq_unmask(struct irq_data *d) | |||
105 | writel_relaxed(val, reg); | 105 | writel_relaxed(val, reg); |
106 | } | 106 | } |
107 | 107 | ||
108 | static void imx_gpc_irq_mask(struct irq_data *d) | 108 | void imx_gpc_irq_mask(struct irq_data *d) |
109 | { | 109 | { |
110 | void __iomem *reg; | 110 | void __iomem *reg; |
111 | u32 val; | 111 | u32 val; |
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 3daf1ed90579..b35e99cc5e5b 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c | |||
@@ -52,7 +52,9 @@ void imx_cpu_die(unsigned int cpu) | |||
52 | * the register being cleared to kill the cpu. | 52 | * the register being cleared to kill the cpu. |
53 | */ | 53 | */ |
54 | imx_set_cpu_arg(cpu, ~0); | 54 | imx_set_cpu_arg(cpu, ~0); |
55 | cpu_do_idle(); | 55 | |
56 | while (1) | ||
57 | cpu_do_idle(); | ||
56 | } | 58 | } |
57 | 59 | ||
58 | int imx_cpu_kill(unsigned int cpu) | 60 | int imx_cpu_kill(unsigned int cpu) |
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 368a6e3f5926..58b864a3fc20 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c | |||
@@ -404,8 +404,7 @@ static int armadillo5x0_sdhc1_init(struct device *dev, | |||
404 | 404 | ||
405 | /* When supported the trigger type have to be BOTH */ | 405 | /* When supported the trigger type have to be BOTH */ |
406 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), | 406 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), |
407 | detect_irq, | 407 | detect_irq, IRQF_TRIGGER_FALLING, |
408 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | ||
409 | "sdhc-detect", data); | 408 | "sdhc-detect", data); |
410 | 409 | ||
411 | if (ret) | 410 | if (ret) |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 3be0fa0e9796..0f9f24116daa 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
@@ -13,7 +13,6 @@ | |||
13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> | 14 | #include <linux/clkdev.h> |
15 | #include <linux/cpu.h> | 15 | #include <linux/cpu.h> |
16 | #include <linux/delay.h> | ||
17 | #include <linux/export.h> | 16 | #include <linux/export.h> |
18 | #include <linux/init.h> | 17 | #include <linux/init.h> |
19 | #include <linux/io.h> | 18 | #include <linux/io.h> |
@@ -38,64 +37,6 @@ | |||
38 | #include "cpuidle.h" | 37 | #include "cpuidle.h" |
39 | #include "hardware.h" | 38 | #include "hardware.h" |
40 | 39 | ||
41 | static u32 chip_revision; | ||
42 | |||
43 | int imx6q_revision(void) | ||
44 | { | ||
45 | return chip_revision; | ||
46 | } | ||
47 | |||
48 | static void __init imx6q_init_revision(void) | ||
49 | { | ||
50 | u32 rev = imx_anatop_get_digprog(); | ||
51 | |||
52 | switch (rev & 0xff) { | ||
53 | case 0: | ||
54 | chip_revision = IMX_CHIP_REVISION_1_0; | ||
55 | break; | ||
56 | case 1: | ||
57 | chip_revision = IMX_CHIP_REVISION_1_1; | ||
58 | break; | ||
59 | case 2: | ||
60 | chip_revision = IMX_CHIP_REVISION_1_2; | ||
61 | break; | ||
62 | default: | ||
63 | chip_revision = IMX_CHIP_REVISION_UNKNOWN; | ||
64 | } | ||
65 | |||
66 | mxc_set_cpu_type(rev >> 16 & 0xff); | ||
67 | } | ||
68 | |||
69 | static void imx6q_restart(enum reboot_mode mode, const char *cmd) | ||
70 | { | ||
71 | struct device_node *np; | ||
72 | void __iomem *wdog_base; | ||
73 | |||
74 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); | ||
75 | wdog_base = of_iomap(np, 0); | ||
76 | if (!wdog_base) | ||
77 | goto soft; | ||
78 | |||
79 | imx_src_prepare_restart(); | ||
80 | |||
81 | /* enable wdog */ | ||
82 | writew_relaxed(1 << 2, wdog_base); | ||
83 | /* write twice to ensure the request will not get ignored */ | ||
84 | writew_relaxed(1 << 2, wdog_base); | ||
85 | |||
86 | /* wait for reset to assert ... */ | ||
87 | mdelay(500); | ||
88 | |||
89 | pr_err("Watchdog reset failed to assert reset\n"); | ||
90 | |||
91 | /* delay to allow the serial port to show the message */ | ||
92 | mdelay(50); | ||
93 | |||
94 | soft: | ||
95 | /* we'll take a jump through zero as a poor second */ | ||
96 | soft_restart(0); | ||
97 | } | ||
98 | |||
99 | /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ | 40 | /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ |
100 | static int ksz9021rn_phy_fixup(struct phy_device *phydev) | 41 | static int ksz9021rn_phy_fixup(struct phy_device *phydev) |
101 | { | 42 | { |
@@ -190,12 +131,20 @@ static void __init imx6q_1588_init(void) | |||
190 | 131 | ||
191 | static void __init imx6q_init_machine(void) | 132 | static void __init imx6q_init_machine(void) |
192 | { | 133 | { |
134 | struct device *parent; | ||
135 | |||
193 | imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", | 136 | imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", |
194 | imx6q_revision()); | 137 | imx_get_soc_revision()); |
138 | |||
139 | mxc_arch_reset_init_dt(); | ||
140 | |||
141 | parent = imx_soc_device_init(); | ||
142 | if (parent == NULL) | ||
143 | pr_warn("failed to initialize soc device\n"); | ||
195 | 144 | ||
196 | imx6q_enet_phy_init(); | 145 | imx6q_enet_phy_init(); |
197 | 146 | ||
198 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 147 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); |
199 | 148 | ||
200 | imx_anatop_init(); | 149 | imx_anatop_init(); |
201 | imx6q_pm_init(); | 150 | imx6q_pm_init(); |
@@ -270,7 +219,7 @@ static void __init imx6q_init_late(void) | |||
270 | * WAIT mode is broken on TO 1.0 and 1.1, so there is no point | 219 | * WAIT mode is broken on TO 1.0 and 1.1, so there is no point |
271 | * to run cpuidle on them. | 220 | * to run cpuidle on them. |
272 | */ | 221 | */ |
273 | if (imx6q_revision() > IMX_CHIP_REVISION_1_1) | 222 | if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) |
274 | imx6q_cpuidle_init(); | 223 | imx6q_cpuidle_init(); |
275 | 224 | ||
276 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { | 225 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { |
@@ -287,7 +236,7 @@ static void __init imx6q_map_io(void) | |||
287 | 236 | ||
288 | static void __init imx6q_init_irq(void) | 237 | static void __init imx6q_init_irq(void) |
289 | { | 238 | { |
290 | imx6q_init_revision(); | 239 | imx_init_revision_from_anatop(); |
291 | imx_init_l2cache(); | 240 | imx_init_l2cache(); |
292 | imx_src_init(); | 241 | imx_src_init(); |
293 | imx_gpc_init(); | 242 | imx_gpc_init(); |
@@ -307,5 +256,5 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") | |||
307 | .init_machine = imx6q_init_machine, | 256 | .init_machine = imx6q_init_machine, |
308 | .init_late = imx6q_init_late, | 257 | .init_late = imx6q_init_late, |
309 | .dt_compat = imx6q_dt_compat, | 258 | .dt_compat = imx6q_dt_compat, |
310 | .restart = imx6q_restart, | 259 | .restart = mxc_restart, |
311 | MACHINE_END | 260 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index c70bd7c64974..2f952e3fcf89 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c | |||
@@ -10,20 +10,51 @@ | |||
10 | #include <linux/irqchip.h> | 10 | #include <linux/irqchip.h> |
11 | #include <linux/of.h> | 11 | #include <linux/of.h> |
12 | #include <linux/of_platform.h> | 12 | #include <linux/of_platform.h> |
13 | #include <linux/mfd/syscon.h> | ||
14 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | ||
15 | #include <linux/regmap.h> | ||
13 | #include <asm/mach/arch.h> | 16 | #include <asm/mach/arch.h> |
14 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
15 | 18 | ||
16 | #include "common.h" | 19 | #include "common.h" |
17 | 20 | ||
21 | static void __init imx6sl_fec_init(void) | ||
22 | { | ||
23 | struct regmap *gpr; | ||
24 | |||
25 | /* set FEC clock from internal PLL clock source */ | ||
26 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); | ||
27 | if (!IS_ERR(gpr)) { | ||
28 | regmap_update_bits(gpr, IOMUXC_GPR1, | ||
29 | IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); | ||
30 | regmap_update_bits(gpr, IOMUXC_GPR1, | ||
31 | IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); | ||
32 | } else { | ||
33 | pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); | ||
34 | } | ||
35 | } | ||
36 | |||
18 | static void __init imx6sl_init_machine(void) | 37 | static void __init imx6sl_init_machine(void) |
19 | { | 38 | { |
39 | struct device *parent; | ||
40 | |||
20 | mxc_arch_reset_init_dt(); | 41 | mxc_arch_reset_init_dt(); |
21 | 42 | ||
22 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 43 | parent = imx_soc_device_init(); |
44 | if (parent == NULL) | ||
45 | pr_warn("failed to initialize soc device\n"); | ||
46 | |||
47 | of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); | ||
48 | |||
49 | imx6sl_fec_init(); | ||
50 | imx_anatop_init(); | ||
51 | /* Reuse imx6q pm code */ | ||
52 | imx6q_pm_init(); | ||
23 | } | 53 | } |
24 | 54 | ||
25 | static void __init imx6sl_init_irq(void) | 55 | static void __init imx6sl_init_irq(void) |
26 | { | 56 | { |
57 | imx_init_revision_from_anatop(); | ||
27 | imx_init_l2cache(); | 58 | imx_init_l2cache(); |
28 | imx_src_init(); | 59 | imx_src_init(); |
29 | imx_gpc_init(); | 60 | imx_gpc_init(); |
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 1ed916175d41..50044a21b388 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c | |||
@@ -311,7 +311,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev, | |||
311 | } | 311 | } |
312 | 312 | ||
313 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), | 313 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), |
314 | detect_irq, IRQF_DISABLED | | 314 | detect_irq, |
315 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | 315 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
316 | "sdhc1-detect", data); | 316 | "sdhc1-detect", data); |
317 | if (ret) { | 317 | if (ret) { |
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index bc0261e99d39..45303bd62902 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c | |||
@@ -371,8 +371,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, | |||
371 | #endif | 371 | #endif |
372 | 372 | ||
373 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq, | 373 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq, |
374 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | 374 | IRQF_TRIGGER_FALLING, "sdhc-detect", data); |
375 | "sdhc-detect", data); | ||
376 | if (ret) | 375 | if (ret) |
377 | goto err_gpio_free_2; | 376 | goto err_gpio_free_2; |
378 | 377 | ||
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index eb3cce38c70d..d1d52600f458 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/clk.h> | 16 | #include <linux/clk.h> |
17 | #include <linux/pinctrl/machine.h> | 17 | #include <linux/pinctrl/machine.h> |
18 | #include <linux/of_address.h> | ||
18 | 19 | ||
19 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
20 | 21 | ||
@@ -88,8 +89,15 @@ void __init imx51_init_early(void) | |||
88 | 89 | ||
89 | void __init imx53_init_early(void) | 90 | void __init imx53_init_early(void) |
90 | { | 91 | { |
92 | struct device_node *np; | ||
93 | void __iomem *base; | ||
94 | |||
91 | mxc_set_cpu_type(MXC_CPU_MX53); | 95 | mxc_set_cpu_type(MXC_CPU_MX53); |
92 | mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); | 96 | |
97 | np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc"); | ||
98 | base = of_iomap(np, 0); | ||
99 | WARN_ON(!base); | ||
100 | mxc_iomux_v3_init(base); | ||
93 | imx_src_init(); | 101 | imx_src_init(); |
94 | } | 102 | } |
95 | 103 | ||
@@ -100,7 +108,14 @@ void __init mx51_init_irq(void) | |||
100 | 108 | ||
101 | void __init mx53_init_irq(void) | 109 | void __init mx53_init_irq(void) |
102 | { | 110 | { |
103 | tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); | 111 | struct device_node *np; |
112 | void __iomem *base; | ||
113 | |||
114 | np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic"); | ||
115 | base = of_iomap(np, 0); | ||
116 | WARN_ON(!base); | ||
117 | |||
118 | tzic_init_irq(base); | ||
104 | } | 119 | } |
105 | 120 | ||
106 | static struct sdma_platform_data imx51_sdma_pdata __initdata = { | 121 | static struct sdma_platform_data imx51_sdma_pdata __initdata = { |
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c index d4361b80c5fb..649fe49ce85e 100644 --- a/arch/arm/mach-imx/mx31lilly-db.c +++ b/arch/arm/mach-imx/mx31lilly-db.c | |||
@@ -130,8 +130,7 @@ static int mxc_mmc1_init(struct device *dev, | |||
130 | gpio_direction_input(gpio_wp); | 130 | gpio_direction_input(gpio_wp); |
131 | 131 | ||
132 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), | 132 | ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), |
133 | detect_irq, | 133 | detect_irq, IRQF_TRIGGER_FALLING, |
134 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | ||
135 | "MMC detect", data); | 134 | "MMC detect", data); |
136 | if (ret) | 135 | if (ret) |
137 | goto exit_free_wp; | 136 | goto exit_free_wp; |
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 8629e5be7ecd..b08ab3ad4a6d 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h | |||
@@ -34,6 +34,7 @@ | |||
34 | #define MXC_CPU_MX35 35 | 34 | #define MXC_CPU_MX35 35 |
35 | #define MXC_CPU_MX51 51 | 35 | #define MXC_CPU_MX51 51 |
36 | #define MXC_CPU_MX53 53 | 36 | #define MXC_CPU_MX53 53 |
37 | #define MXC_CPU_IMX6SL 0x60 | ||
37 | #define MXC_CPU_IMX6DL 0x61 | 38 | #define MXC_CPU_IMX6DL 0x61 |
38 | #define MXC_CPU_IMX6Q 0x63 | 39 | #define MXC_CPU_IMX6Q 0x63 |
39 | 40 | ||
@@ -152,6 +153,11 @@ extern unsigned int __mxc_cpu_type; | |||
152 | #endif | 153 | #endif |
153 | 154 | ||
154 | #ifndef __ASSEMBLY__ | 155 | #ifndef __ASSEMBLY__ |
156 | static inline bool cpu_is_imx6sl(void) | ||
157 | { | ||
158 | return __mxc_cpu_type == MXC_CPU_IMX6SL; | ||
159 | } | ||
160 | |||
155 | static inline bool cpu_is_imx6dl(void) | 161 | static inline bool cpu_is_imx6dl(void) |
156 | { | 162 | { |
157 | return __mxc_cpu_type == MXC_CPU_IMX6DL; | 163 | return __mxc_cpu_type == MXC_CPU_IMX6DL; |
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 204942749e21..aecd9f8037e0 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c | |||
@@ -10,9 +10,15 @@ | |||
10 | * http://www.gnu.org/copyleft/gpl.html | 10 | * http://www.gnu.org/copyleft/gpl.html |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/delay.h> | ||
13 | #include <linux/init.h> | 14 | #include <linux/init.h> |
14 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/irq.h> | ||
17 | #include <linux/mfd/syscon.h> | ||
18 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | ||
15 | #include <linux/of.h> | 19 | #include <linux/of.h> |
20 | #include <linux/of_address.h> | ||
21 | #include <linux/regmap.h> | ||
16 | #include <linux/suspend.h> | 22 | #include <linux/suspend.h> |
17 | #include <asm/cacheflush.h> | 23 | #include <asm/cacheflush.h> |
18 | #include <asm/proc-fns.h> | 24 | #include <asm/proc-fns.h> |
@@ -22,6 +28,147 @@ | |||
22 | #include "common.h" | 28 | #include "common.h" |
23 | #include "hardware.h" | 29 | #include "hardware.h" |
24 | 30 | ||
31 | #define CCR 0x0 | ||
32 | #define BM_CCR_WB_COUNT (0x7 << 16) | ||
33 | #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) | ||
34 | #define BM_CCR_RBC_EN (0x1 << 27) | ||
35 | |||
36 | #define CLPCR 0x54 | ||
37 | #define BP_CLPCR_LPM 0 | ||
38 | #define BM_CLPCR_LPM (0x3 << 0) | ||
39 | #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) | ||
40 | #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | ||
41 | #define BM_CLPCR_SBYOS (0x1 << 6) | ||
42 | #define BM_CLPCR_DIS_REF_OSC (0x1 << 7) | ||
43 | #define BM_CLPCR_VSTBY (0x1 << 8) | ||
44 | #define BP_CLPCR_STBY_COUNT 9 | ||
45 | #define BM_CLPCR_STBY_COUNT (0x3 << 9) | ||
46 | #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) | ||
47 | #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) | ||
48 | #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) | ||
49 | #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) | ||
50 | #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) | ||
51 | #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) | ||
52 | #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) | ||
53 | #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) | ||
54 | #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) | ||
55 | #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) | ||
56 | #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) | ||
57 | |||
58 | #define CGPR 0x64 | ||
59 | #define BM_CGPR_CHICKEN_BIT (0x1 << 17) | ||
60 | |||
61 | static void __iomem *ccm_base; | ||
62 | |||
63 | void imx6q_set_chicken_bit(void) | ||
64 | { | ||
65 | u32 val = readl_relaxed(ccm_base + CGPR); | ||
66 | |||
67 | val |= BM_CGPR_CHICKEN_BIT; | ||
68 | writel_relaxed(val, ccm_base + CGPR); | ||
69 | } | ||
70 | |||
71 | static void imx6q_enable_rbc(bool enable) | ||
72 | { | ||
73 | u32 val; | ||
74 | |||
75 | /* | ||
76 | * need to mask all interrupts in GPC before | ||
77 | * operating RBC configurations | ||
78 | */ | ||
79 | imx_gpc_mask_all(); | ||
80 | |||
81 | /* configure RBC enable bit */ | ||
82 | val = readl_relaxed(ccm_base + CCR); | ||
83 | val &= ~BM_CCR_RBC_EN; | ||
84 | val |= enable ? BM_CCR_RBC_EN : 0; | ||
85 | writel_relaxed(val, ccm_base + CCR); | ||
86 | |||
87 | /* configure RBC count */ | ||
88 | val = readl_relaxed(ccm_base + CCR); | ||
89 | val &= ~BM_CCR_RBC_BYPASS_COUNT; | ||
90 | val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; | ||
91 | writel(val, ccm_base + CCR); | ||
92 | |||
93 | /* | ||
94 | * need to delay at least 2 cycles of CKIL(32K) | ||
95 | * due to hardware design requirement, which is | ||
96 | * ~61us, here we use 65us for safe | ||
97 | */ | ||
98 | udelay(65); | ||
99 | |||
100 | /* restore GPC interrupt mask settings */ | ||
101 | imx_gpc_restore_all(); | ||
102 | } | ||
103 | |||
104 | static void imx6q_enable_wb(bool enable) | ||
105 | { | ||
106 | u32 val; | ||
107 | |||
108 | /* configure well bias enable bit */ | ||
109 | val = readl_relaxed(ccm_base + CLPCR); | ||
110 | val &= ~BM_CLPCR_WB_PER_AT_LPM; | ||
111 | val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; | ||
112 | writel_relaxed(val, ccm_base + CLPCR); | ||
113 | |||
114 | /* configure well bias count */ | ||
115 | val = readl_relaxed(ccm_base + CCR); | ||
116 | val &= ~BM_CCR_WB_COUNT; | ||
117 | val |= enable ? BM_CCR_WB_COUNT : 0; | ||
118 | writel_relaxed(val, ccm_base + CCR); | ||
119 | } | ||
120 | |||
121 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) | ||
122 | { | ||
123 | struct irq_desc *iomuxc_irq_desc; | ||
124 | u32 val = readl_relaxed(ccm_base + CLPCR); | ||
125 | |||
126 | val &= ~BM_CLPCR_LPM; | ||
127 | switch (mode) { | ||
128 | case WAIT_CLOCKED: | ||
129 | break; | ||
130 | case WAIT_UNCLOCKED: | ||
131 | val |= 0x1 << BP_CLPCR_LPM; | ||
132 | val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; | ||
133 | break; | ||
134 | case STOP_POWER_ON: | ||
135 | val |= 0x2 << BP_CLPCR_LPM; | ||
136 | break; | ||
137 | case WAIT_UNCLOCKED_POWER_OFF: | ||
138 | val |= 0x1 << BP_CLPCR_LPM; | ||
139 | val &= ~BM_CLPCR_VSTBY; | ||
140 | val &= ~BM_CLPCR_SBYOS; | ||
141 | break; | ||
142 | case STOP_POWER_OFF: | ||
143 | val |= 0x2 << BP_CLPCR_LPM; | ||
144 | val |= 0x3 << BP_CLPCR_STBY_COUNT; | ||
145 | val |= BM_CLPCR_VSTBY; | ||
146 | val |= BM_CLPCR_SBYOS; | ||
147 | if (cpu_is_imx6sl()) { | ||
148 | val |= BM_CLPCR_BYPASS_PMIC_READY; | ||
149 | val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; | ||
150 | } else { | ||
151 | val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; | ||
152 | } | ||
153 | break; | ||
154 | default: | ||
155 | return -EINVAL; | ||
156 | } | ||
157 | |||
158 | /* | ||
159 | * Unmask the always pending IOMUXC interrupt #32 as wakeup source to | ||
160 | * deassert dsm_request signal, so that we can ensure dsm_request | ||
161 | * is not asserted when we're going to write CLPCR register to set LPM. | ||
162 | * After setting up LPM bits, we need to mask this wakeup source. | ||
163 | */ | ||
164 | iomuxc_irq_desc = irq_to_desc(32); | ||
165 | imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); | ||
166 | writel_relaxed(val, ccm_base + CLPCR); | ||
167 | imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data); | ||
168 | |||
169 | return 0; | ||
170 | } | ||
171 | |||
25 | static int imx6q_suspend_finish(unsigned long val) | 172 | static int imx6q_suspend_finish(unsigned long val) |
26 | { | 173 | { |
27 | cpu_do_idle(); | 174 | cpu_do_idle(); |
@@ -33,14 +180,19 @@ static int imx6q_pm_enter(suspend_state_t state) | |||
33 | switch (state) { | 180 | switch (state) { |
34 | case PM_SUSPEND_MEM: | 181 | case PM_SUSPEND_MEM: |
35 | imx6q_set_lpm(STOP_POWER_OFF); | 182 | imx6q_set_lpm(STOP_POWER_OFF); |
183 | imx6q_enable_wb(true); | ||
184 | imx6q_enable_rbc(true); | ||
36 | imx_gpc_pre_suspend(); | 185 | imx_gpc_pre_suspend(); |
37 | imx_anatop_pre_suspend(); | 186 | imx_anatop_pre_suspend(); |
38 | imx_set_cpu_jump(0, v7_cpu_resume); | 187 | imx_set_cpu_jump(0, v7_cpu_resume); |
39 | /* Zzz ... */ | 188 | /* Zzz ... */ |
40 | cpu_suspend(0, imx6q_suspend_finish); | 189 | cpu_suspend(0, imx6q_suspend_finish); |
41 | imx_smp_prepare(); | 190 | if (cpu_is_imx6q() || cpu_is_imx6dl()) |
191 | imx_smp_prepare(); | ||
42 | imx_anatop_post_resume(); | 192 | imx_anatop_post_resume(); |
43 | imx_gpc_post_resume(); | 193 | imx_gpc_post_resume(); |
194 | imx6q_enable_rbc(false); | ||
195 | imx6q_enable_wb(false); | ||
44 | imx6q_set_lpm(WAIT_CLOCKED); | 196 | imx6q_set_lpm(WAIT_CLOCKED); |
45 | break; | 197 | break; |
46 | default: | 198 | default: |
@@ -55,7 +207,29 @@ static const struct platform_suspend_ops imx6q_pm_ops = { | |||
55 | .valid = suspend_valid_only_mem, | 207 | .valid = suspend_valid_only_mem, |
56 | }; | 208 | }; |
57 | 209 | ||
210 | void __init imx6q_pm_set_ccm_base(void __iomem *base) | ||
211 | { | ||
212 | ccm_base = base; | ||
213 | } | ||
214 | |||
58 | void __init imx6q_pm_init(void) | 215 | void __init imx6q_pm_init(void) |
59 | { | 216 | { |
217 | struct regmap *gpr; | ||
218 | |||
219 | WARN_ON(!ccm_base); | ||
220 | |||
221 | /* | ||
222 | * Force IOMUXC irq pending, so that the interrupt to GPC can be | ||
223 | * used to deassert dsm_request signal when the signal gets | ||
224 | * asserted unexpectedly. | ||
225 | */ | ||
226 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | ||
227 | if (!IS_ERR(gpr)) | ||
228 | regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, | ||
229 | IMX6Q_GPR1_GINT); | ||
230 | |||
231 | /* Set initial power mode */ | ||
232 | imx6q_set_lpm(WAIT_CLOCKED); | ||
233 | |||
60 | suspend_set_ops(&imx6q_pm_ops); | 234 | suspend_set_ops(&imx6q_pm_ops); |
61 | } | 235 | } |
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 10a6b1a8c5ac..4754373e7e7d 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c | |||
@@ -91,6 +91,7 @@ void imx_enable_cpu(int cpu, bool enable) | |||
91 | spin_lock(&scr_lock); | 91 | spin_lock(&scr_lock); |
92 | val = readl_relaxed(src_base + SRC_SCR); | 92 | val = readl_relaxed(src_base + SRC_SCR); |
93 | val = enable ? val | mask : val & ~mask; | 93 | val = enable ? val | mask : val & ~mask; |
94 | val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); | ||
94 | writel_relaxed(val, src_base + SRC_SCR); | 95 | writel_relaxed(val, src_base + SRC_SCR); |
95 | spin_unlock(&scr_lock); | 96 | spin_unlock(&scr_lock); |
96 | } | 97 | } |
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 80c177c36c5f..e6edcd38b282 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c | |||
@@ -42,6 +42,9 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) | |||
42 | { | 42 | { |
43 | unsigned int wcr_enable; | 43 | unsigned int wcr_enable; |
44 | 44 | ||
45 | if (cpu_is_imx6q() || cpu_is_imx6dl()) | ||
46 | imx_src_prepare_restart(); | ||
47 | |||
45 | if (wdog_clk) | 48 | if (wdog_clk) |
46 | clk_enable(wdog_clk); | 49 | clk_enable(wdog_clk); |
47 | 50 | ||
@@ -52,6 +55,8 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) | |||
52 | 55 | ||
53 | /* Assert SRS signal */ | 56 | /* Assert SRS signal */ |
54 | __raw_writew(wcr_enable, wdog_base); | 57 | __raw_writew(wcr_enable, wdog_base); |
58 | /* write twice to ensure the request will not get ignored */ | ||
59 | __raw_writew(wcr_enable, wdog_base); | ||
55 | 60 | ||
56 | /* wait for reset to assert... */ | 61 | /* wait for reset to assert... */ |
57 | mdelay(500); | 62 | mdelay(500); |
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index cd46529e9eaa..9b6638aadeaa 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c | |||
@@ -250,7 +250,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) | |||
250 | 250 | ||
251 | static struct irqaction mxc_timer_irq = { | 251 | static struct irqaction mxc_timer_irq = { |
252 | .name = "i.MX Timer Tick", | 252 | .name = "i.MX Timer Tick", |
253 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 253 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
254 | .handler = mxc_timer_interrupt, | 254 | .handler = mxc_timer_interrupt, |
255 | }; | 255 | }; |
256 | 256 | ||
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/cm.h index 202e6a57f100..4ecff7bff482 100644 --- a/arch/arm/mach-integrator/include/mach/cm.h +++ b/arch/arm/mach-integrator/cm.h | |||
@@ -1,9 +1,12 @@ | |||
1 | /* | 1 | /* |
2 | * update the core module control register. | 2 | * access the core module control register. |
3 | */ | 3 | */ |
4 | u32 cm_get(void); | ||
4 | void cm_control(u32, u32); | 5 | void cm_control(u32, u32); |
5 | 6 | ||
6 | #define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL) | 7 | struct device_node; |
8 | void cm_init(void); | ||
9 | void cm_clear_irqs(void); | ||
7 | 10 | ||
8 | #define CM_CTRL_LED (1 << 0) | 11 | #define CM_CTRL_LED (1 << 0) |
9 | #define CM_CTRL_nMBDET (1 << 1) | 12 | #define CM_CTRL_nMBDET (1 << 1) |
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 4cdfd7365925..00ddf20ed91b 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
@@ -22,77 +22,30 @@ | |||
22 | #include <linux/amba/serial.h> | 22 | #include <linux/amba/serial.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/stat.h> | 24 | #include <linux/stat.h> |
25 | #include <linux/of.h> | ||
26 | #include <linux/of_address.h> | ||
25 | 27 | ||
26 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
27 | #include <mach/platform.h> | 29 | #include <mach/platform.h> |
28 | #include <mach/cm.h> | ||
29 | #include <mach/irqs.h> | ||
30 | 30 | ||
31 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
32 | #include <asm/mach/time.h> | 32 | #include <asm/mach/time.h> |
33 | #include <asm/pgtable.h> | 33 | #include <asm/pgtable.h> |
34 | 34 | ||
35 | #include "cm.h" | ||
35 | #include "common.h" | 36 | #include "common.h" |
36 | 37 | ||
37 | #ifdef CONFIG_ATAGS | 38 | static DEFINE_RAW_SPINLOCK(cm_lock); |
38 | 39 | static void __iomem *cm_base; | |
39 | #define INTEGRATOR_RTC_IRQ { IRQ_RTCINT } | ||
40 | #define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 } | ||
41 | #define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 } | ||
42 | #define KMI0_IRQ { IRQ_KMIINT0 } | ||
43 | #define KMI1_IRQ { IRQ_KMIINT1 } | ||
44 | |||
45 | static AMBA_APB_DEVICE(rtc, "rtc", 0, | ||
46 | INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL); | ||
47 | |||
48 | static AMBA_APB_DEVICE(uart0, "uart0", 0, | ||
49 | INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL); | ||
50 | |||
51 | static AMBA_APB_DEVICE(uart1, "uart1", 0, | ||
52 | INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL); | ||
53 | |||
54 | static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL); | ||
55 | static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL); | ||
56 | |||
57 | static struct amba_device *amba_devs[] __initdata = { | ||
58 | &rtc_device, | ||
59 | &uart0_device, | ||
60 | &uart1_device, | ||
61 | &kmi0_device, | ||
62 | &kmi1_device, | ||
63 | }; | ||
64 | 40 | ||
65 | int __init integrator_init(bool is_cp) | 41 | /** |
42 | * cm_get - get the value from the CM_CTRL register | ||
43 | */ | ||
44 | u32 cm_get(void) | ||
66 | { | 45 | { |
67 | int i; | 46 | return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); |
68 | |||
69 | /* | ||
70 | * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to | ||
71 | * hard-code them. The Integator/CP and forward have proper cell IDs. | ||
72 | * Else we leave them undefined to the bus driver can autoprobe them. | ||
73 | */ | ||
74 | if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) { | ||
75 | rtc_device.periphid = 0x00041030; | ||
76 | uart0_device.periphid = 0x00041010; | ||
77 | uart1_device.periphid = 0x00041010; | ||
78 | kmi0_device.periphid = 0x00041050; | ||
79 | kmi1_device.periphid = 0x00041050; | ||
80 | uart0_device.dev.platform_data = &ap_uart_data; | ||
81 | uart1_device.dev.platform_data = &ap_uart_data; | ||
82 | } | ||
83 | |||
84 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
85 | struct amba_device *d = amba_devs[i]; | ||
86 | amba_device_register(d, &iomem_resource); | ||
87 | } | ||
88 | |||
89 | return 0; | ||
90 | } | 47 | } |
91 | 48 | ||
92 | #endif | ||
93 | |||
94 | static DEFINE_RAW_SPINLOCK(cm_lock); | ||
95 | |||
96 | /** | 49 | /** |
97 | * cm_control - update the CM_CTRL register. | 50 | * cm_control - update the CM_CTRL register. |
98 | * @mask: bits to change | 51 | * @mask: bits to change |
@@ -104,12 +57,80 @@ void cm_control(u32 mask, u32 set) | |||
104 | u32 val; | 57 | u32 val; |
105 | 58 | ||
106 | raw_spin_lock_irqsave(&cm_lock, flags); | 59 | raw_spin_lock_irqsave(&cm_lock, flags); |
107 | val = readl(CM_CTRL) & ~mask; | 60 | val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; |
108 | writel(val | set, CM_CTRL); | 61 | writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); |
109 | raw_spin_unlock_irqrestore(&cm_lock, flags); | 62 | raw_spin_unlock_irqrestore(&cm_lock, flags); |
110 | } | 63 | } |
111 | 64 | ||
112 | EXPORT_SYMBOL(cm_control); | 65 | static const char *integrator_arch_str(u32 id) |
66 | { | ||
67 | switch ((id >> 16) & 0xff) { | ||
68 | case 0x00: | ||
69 | return "ASB little-endian"; | ||
70 | case 0x01: | ||
71 | return "AHB little-endian"; | ||
72 | case 0x03: | ||
73 | return "AHB-Lite system bus, bi-endian"; | ||
74 | case 0x04: | ||
75 | return "AHB"; | ||
76 | case 0x08: | ||
77 | return "AHB system bus, ASB processor bus"; | ||
78 | default: | ||
79 | return "Unknown"; | ||
80 | } | ||
81 | } | ||
82 | |||
83 | static const char *integrator_fpga_str(u32 id) | ||
84 | { | ||
85 | switch ((id >> 12) & 0xf) { | ||
86 | case 0x01: | ||
87 | return "XC4062"; | ||
88 | case 0x02: | ||
89 | return "XC4085"; | ||
90 | case 0x03: | ||
91 | return "XVC600"; | ||
92 | case 0x04: | ||
93 | return "EPM7256AE (Altera PLD)"; | ||
94 | default: | ||
95 | return "Unknown"; | ||
96 | } | ||
97 | } | ||
98 | |||
99 | void cm_clear_irqs(void) | ||
100 | { | ||
101 | /* disable core module IRQs */ | ||
102 | writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + | ||
103 | IRQ_ENABLE_CLEAR); | ||
104 | } | ||
105 | |||
106 | static const struct of_device_id cm_match[] = { | ||
107 | { .compatible = "arm,core-module-integrator"}, | ||
108 | { }, | ||
109 | }; | ||
110 | |||
111 | void cm_init(void) | ||
112 | { | ||
113 | struct device_node *cm = of_find_matching_node(NULL, cm_match); | ||
114 | u32 val; | ||
115 | |||
116 | if (!cm) { | ||
117 | pr_crit("no core module node found in device tree\n"); | ||
118 | return; | ||
119 | } | ||
120 | cm_base = of_iomap(cm, 0); | ||
121 | if (!cm_base) { | ||
122 | pr_crit("could not remap core module\n"); | ||
123 | return; | ||
124 | } | ||
125 | cm_clear_irqs(); | ||
126 | val = readl(cm_base + INTEGRATOR_HDR_ID_OFFSET); | ||
127 | pr_info("Detected ARM core module:\n"); | ||
128 | pr_info(" Manufacturer: %02x\n", (val >> 24)); | ||
129 | pr_info(" Architecture: %s\n", integrator_arch_str(val)); | ||
130 | pr_info(" FPGA: %s\n", integrator_fpga_str(val)); | ||
131 | pr_info(" Build: %02x\n", (val >> 4) & 0xFF); | ||
132 | pr_info(" Rev: %c\n", ('A' + (val & 0x03))); | ||
133 | } | ||
113 | 134 | ||
114 | /* | 135 | /* |
115 | * We need to stop things allocating the low memory; ideally we need a | 136 | * We need to stop things allocating the low memory; ideally we need a |
@@ -145,27 +166,7 @@ static ssize_t intcp_get_arch(struct device *dev, | |||
145 | struct device_attribute *attr, | 166 | struct device_attribute *attr, |
146 | char *buf) | 167 | char *buf) |
147 | { | 168 | { |
148 | const char *arch; | 169 | return sprintf(buf, "%s\n", integrator_arch_str(integrator_id)); |
149 | |||
150 | switch ((integrator_id >> 16) & 0xff) { | ||
151 | case 0x00: | ||
152 | arch = "ASB little-endian"; | ||
153 | break; | ||
154 | case 0x01: | ||
155 | arch = "AHB little-endian"; | ||
156 | break; | ||
157 | case 0x03: | ||
158 | arch = "AHB-Lite system bus, bi-endian"; | ||
159 | break; | ||
160 | case 0x04: | ||
161 | arch = "AHB"; | ||
162 | break; | ||
163 | default: | ||
164 | arch = "Unknown"; | ||
165 | break; | ||
166 | } | ||
167 | |||
168 | return sprintf(buf, "%s\n", arch); | ||
169 | } | 170 | } |
170 | 171 | ||
171 | static struct device_attribute intcp_arch_attr = | 172 | static struct device_attribute intcp_arch_attr = |
@@ -175,24 +176,7 @@ static ssize_t intcp_get_fpga(struct device *dev, | |||
175 | struct device_attribute *attr, | 176 | struct device_attribute *attr, |
176 | char *buf) | 177 | char *buf) |
177 | { | 178 | { |
178 | const char *fpga; | 179 | return sprintf(buf, "%s\n", integrator_fpga_str(integrator_id)); |
179 | |||
180 | switch ((integrator_id >> 12) & 0xf) { | ||
181 | case 0x01: | ||
182 | fpga = "XC4062"; | ||
183 | break; | ||
184 | case 0x02: | ||
185 | fpga = "XC4085"; | ||
186 | break; | ||
187 | case 0x04: | ||
188 | fpga = "EPM7256AE (Altera PLD)"; | ||
189 | break; | ||
190 | default: | ||
191 | fpga = "Unknown"; | ||
192 | break; | ||
193 | } | ||
194 | |||
195 | return sprintf(buf, "%s\n", fpga); | ||
196 | } | 180 | } |
197 | 181 | ||
198 | static struct device_attribute intcp_fpga_attr = | 182 | static struct device_attribute intcp_fpga_attr = |
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h deleted file mode 100644 index eff0adad9ae3..000000000000 --- a/arch/arm/mach-integrator/include/mach/irqs.h +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-integrator/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | |||
22 | /* | ||
23 | * Interrupt numbers, all of the above are just static reservations | ||
24 | * used so they can be encoded into device resources. They will finally | ||
25 | * be done away with when switching to device tree. | ||
26 | */ | ||
27 | #define IRQ_PIC_START 64 | ||
28 | #define IRQ_SOFTINT (IRQ_PIC_START+0) | ||
29 | #define IRQ_UARTINT0 (IRQ_PIC_START+1) | ||
30 | #define IRQ_UARTINT1 (IRQ_PIC_START+2) | ||
31 | #define IRQ_KMIINT0 (IRQ_PIC_START+3) | ||
32 | #define IRQ_KMIINT1 (IRQ_PIC_START+4) | ||
33 | #define IRQ_TIMERINT0 (IRQ_PIC_START+5) | ||
34 | #define IRQ_TIMERINT1 (IRQ_PIC_START+6) | ||
35 | #define IRQ_TIMERINT2 (IRQ_PIC_START+7) | ||
36 | #define IRQ_RTCINT (IRQ_PIC_START+8) | ||
37 | #define IRQ_AP_EXPINT0 (IRQ_PIC_START+9) | ||
38 | #define IRQ_AP_EXPINT1 (IRQ_PIC_START+10) | ||
39 | #define IRQ_AP_EXPINT2 (IRQ_PIC_START+11) | ||
40 | #define IRQ_AP_EXPINT3 (IRQ_PIC_START+12) | ||
41 | #define IRQ_AP_PCIINT0 (IRQ_PIC_START+13) | ||
42 | #define IRQ_AP_PCIINT1 (IRQ_PIC_START+14) | ||
43 | #define IRQ_AP_PCIINT2 (IRQ_PIC_START+15) | ||
44 | #define IRQ_AP_PCIINT3 (IRQ_PIC_START+16) | ||
45 | #define IRQ_AP_V3INT (IRQ_PIC_START+17) | ||
46 | #define IRQ_AP_CPINT0 (IRQ_PIC_START+18) | ||
47 | #define IRQ_AP_CPINT1 (IRQ_PIC_START+19) | ||
48 | #define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20) | ||
49 | #define IRQ_AP_APCINT (IRQ_PIC_START+21) | ||
50 | #define IRQ_CP_CLCDCINT (IRQ_PIC_START+22) | ||
51 | #define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23) | ||
52 | #define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24) | ||
53 | #define IRQ_CP_AACIINT (IRQ_PIC_START+25) | ||
54 | #define IRQ_CP_CPPLDINT (IRQ_PIC_START+26) | ||
55 | #define IRQ_CP_ETHINT (IRQ_PIC_START+27) | ||
56 | #define IRQ_CP_TSPENINT (IRQ_PIC_START+28) | ||
57 | #define IRQ_PIC_END (IRQ_PIC_START+28) | ||
58 | |||
59 | #define IRQ_CIC_START (IRQ_PIC_END+1) | ||
60 | #define IRQ_CM_SOFTINT (IRQ_CIC_START+0) | ||
61 | #define IRQ_CM_COMMRX (IRQ_CIC_START+1) | ||
62 | #define IRQ_CM_COMMTX (IRQ_CIC_START+2) | ||
63 | #define IRQ_CIC_END (IRQ_CIC_START+2) | ||
64 | |||
65 | /* | ||
66 | * IntegratorCP only | ||
67 | */ | ||
68 | #define IRQ_SIC_START (IRQ_CIC_END+1) | ||
69 | #define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0) | ||
70 | #define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1) | ||
71 | #define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2) | ||
72 | #define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3) | ||
73 | #define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4) | ||
74 | #define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5) | ||
75 | #define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6) | ||
76 | #define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7) | ||
77 | #define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8) | ||
78 | #define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9) | ||
79 | #define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10) | ||
80 | #define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11) | ||
81 | #define IRQ_SIC_END (IRQ_SIC_START+11) | ||
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index d9e95e612fcb..d50dc2dbfd89 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c | |||
@@ -51,13 +51,13 @@ | |||
51 | #include <asm/mach-types.h> | 51 | #include <asm/mach-types.h> |
52 | 52 | ||
53 | #include <mach/lm.h> | 53 | #include <mach/lm.h> |
54 | #include <mach/irqs.h> | ||
55 | 54 | ||
56 | #include <asm/mach/arch.h> | 55 | #include <asm/mach/arch.h> |
57 | #include <asm/mach/irq.h> | 56 | #include <asm/mach/irq.h> |
58 | #include <asm/mach/map.h> | 57 | #include <asm/mach/map.h> |
59 | #include <asm/mach/time.h> | 58 | #include <asm/mach/time.h> |
60 | 59 | ||
60 | #include "cm.h" | ||
61 | #include "common.h" | 61 | #include "common.h" |
62 | #include "pci_v3.h" | 62 | #include "pci_v3.h" |
63 | 63 | ||
@@ -146,7 +146,7 @@ static int irq_suspend(void) | |||
146 | static void irq_resume(void) | 146 | static void irq_resume(void) |
147 | { | 147 | { |
148 | /* disable all irq sources */ | 148 | /* disable all irq sources */ |
149 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | 149 | cm_clear_irqs(); |
150 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | 150 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); |
151 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | 151 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); |
152 | 152 | ||
@@ -402,8 +402,6 @@ void __init ap_init_early(void) | |||
402 | { | 402 | { |
403 | } | 403 | } |
404 | 404 | ||
405 | #ifdef CONFIG_OF | ||
406 | |||
407 | static void __init ap_of_timer_init(void) | 405 | static void __init ap_of_timer_init(void) |
408 | { | 406 | { |
409 | struct device_node *node; | 407 | struct device_node *node; |
@@ -450,8 +448,7 @@ static const struct of_device_id fpga_irq_of_match[] __initconst = { | |||
450 | 448 | ||
451 | static void __init ap_init_irq_of(void) | 449 | static void __init ap_init_irq_of(void) |
452 | { | 450 | { |
453 | /* disable core module IRQs */ | 451 | cm_init(); |
454 | writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | ||
455 | of_irq_init(fpga_irq_of_match); | 452 | of_irq_init(fpga_irq_of_match); |
456 | integrator_clk_init(false); | 453 | integrator_clk_init(false); |
457 | } | 454 | } |
@@ -473,6 +470,11 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { | |||
473 | { /* sentinel */ }, | 470 | { /* sentinel */ }, |
474 | }; | 471 | }; |
475 | 472 | ||
473 | static const struct of_device_id ap_syscon_match[] = { | ||
474 | { .compatible = "arm,integrator-ap-syscon"}, | ||
475 | { }, | ||
476 | }; | ||
477 | |||
476 | static void __init ap_init_of(void) | 478 | static void __init ap_init_of(void) |
477 | { | 479 | { |
478 | unsigned long sc_dec; | 480 | unsigned long sc_dec; |
@@ -489,7 +491,8 @@ static void __init ap_init_of(void) | |||
489 | root = of_find_node_by_path("/"); | 491 | root = of_find_node_by_path("/"); |
490 | if (!root) | 492 | if (!root) |
491 | return; | 493 | return; |
492 | syscon = of_find_node_by_path("/syscon"); | 494 | |
495 | syscon = of_find_matching_node(root, ap_syscon_match); | ||
493 | if (!syscon) | 496 | if (!syscon) |
494 | return; | 497 | return; |
495 | 498 | ||
@@ -541,7 +544,7 @@ static void __init ap_init_of(void) | |||
541 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | 544 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; |
542 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | 545 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; |
543 | lmdev->resource.flags = IORESOURCE_MEM; | 546 | lmdev->resource.flags = IORESOURCE_MEM; |
544 | lmdev->irq = IRQ_AP_EXPINT0 + i; | 547 | lmdev->irq = irq_of_parse_and_map(syscon, i); |
545 | lmdev->id = i; | 548 | lmdev->id = i; |
546 | 549 | ||
547 | lm_device_register(lmdev); | 550 | lm_device_register(lmdev); |
@@ -564,136 +567,3 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") | |||
564 | .restart = integrator_restart, | 567 | .restart = integrator_restart, |
565 | .dt_compat = ap_dt_board_compat, | 568 | .dt_compat = ap_dt_board_compat, |
566 | MACHINE_END | 569 | MACHINE_END |
567 | |||
568 | #endif | ||
569 | |||
570 | #ifdef CONFIG_ATAGS | ||
571 | |||
572 | /* | ||
573 | * For the ATAG boot some static mappings are needed. This will | ||
574 | * go away with the ATAG support down the road. | ||
575 | */ | ||
576 | |||
577 | static struct map_desc ap_io_desc_atag[] __initdata = { | ||
578 | { | ||
579 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), | ||
580 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), | ||
581 | .length = SZ_4K, | ||
582 | .type = MT_DEVICE | ||
583 | }, | ||
584 | }; | ||
585 | |||
586 | static void __init ap_map_io_atag(void) | ||
587 | { | ||
588 | iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag)); | ||
589 | ap_map_io(); | ||
590 | } | ||
591 | |||
592 | /* | ||
593 | * This is where non-devicetree initialization code is collected and stashed | ||
594 | * for eventual deletion. | ||
595 | */ | ||
596 | |||
597 | static struct platform_device pci_v3_device = { | ||
598 | .name = "pci-v3", | ||
599 | .id = 0, | ||
600 | }; | ||
601 | |||
602 | static struct resource cfi_flash_resource = { | ||
603 | .start = INTEGRATOR_FLASH_BASE, | ||
604 | .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, | ||
605 | .flags = IORESOURCE_MEM, | ||
606 | }; | ||
607 | |||
608 | static struct platform_device cfi_flash_device = { | ||
609 | .name = "physmap-flash", | ||
610 | .id = 0, | ||
611 | .dev = { | ||
612 | .platform_data = &ap_flash_data, | ||
613 | }, | ||
614 | .num_resources = 1, | ||
615 | .resource = &cfi_flash_resource, | ||
616 | }; | ||
617 | |||
618 | static void __init ap_timer_init(void) | ||
619 | { | ||
620 | struct clk *clk; | ||
621 | unsigned long rate; | ||
622 | |||
623 | clk = clk_get_sys("ap_timer", NULL); | ||
624 | BUG_ON(IS_ERR(clk)); | ||
625 | clk_prepare_enable(clk); | ||
626 | rate = clk_get_rate(clk); | ||
627 | |||
628 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | ||
629 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
630 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | ||
631 | |||
632 | integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE); | ||
633 | integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE, | ||
634 | IRQ_TIMERINT1); | ||
635 | } | ||
636 | |||
637 | #define INTEGRATOR_SC_VALID_INT 0x003fffff | ||
638 | |||
639 | static void __init ap_init_irq(void) | ||
640 | { | ||
641 | /* Disable all interrupts initially. */ | ||
642 | /* Do the core module ones */ | ||
643 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | ||
644 | |||
645 | /* do the header card stuff next */ | ||
646 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | ||
647 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | ||
648 | |||
649 | fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, | ||
650 | -1, INTEGRATOR_SC_VALID_INT, NULL); | ||
651 | integrator_clk_init(false); | ||
652 | } | ||
653 | |||
654 | static void __init ap_init(void) | ||
655 | { | ||
656 | unsigned long sc_dec; | ||
657 | int i; | ||
658 | |||
659 | platform_device_register(&pci_v3_device); | ||
660 | platform_device_register(&cfi_flash_device); | ||
661 | |||
662 | ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); | ||
663 | sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); | ||
664 | for (i = 0; i < 4; i++) { | ||
665 | struct lm_device *lmdev; | ||
666 | |||
667 | if ((sc_dec & (16 << i)) == 0) | ||
668 | continue; | ||
669 | |||
670 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); | ||
671 | if (!lmdev) | ||
672 | continue; | ||
673 | |||
674 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | ||
675 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | ||
676 | lmdev->resource.flags = IORESOURCE_MEM; | ||
677 | lmdev->irq = IRQ_AP_EXPINT0 + i; | ||
678 | lmdev->id = i; | ||
679 | |||
680 | lm_device_register(lmdev); | ||
681 | } | ||
682 | |||
683 | integrator_init(false); | ||
684 | } | ||
685 | |||
686 | MACHINE_START(INTEGRATOR, "ARM-Integrator") | ||
687 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
688 | .atag_offset = 0x100, | ||
689 | .reserve = integrator_reserve, | ||
690 | .map_io = ap_map_io_atag, | ||
691 | .init_early = ap_init_early, | ||
692 | .init_irq = ap_init_irq, | ||
693 | .handle_irq = fpga_handle_irq, | ||
694 | .init_time = ap_timer_init, | ||
695 | .init_machine = ap_init, | ||
696 | .restart = integrator_restart, | ||
697 | MACHINE_END | ||
698 | |||
699 | #endif | ||
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 8c60fcb08a98..1df6e7602cad 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -36,9 +36,7 @@ | |||
36 | #include <asm/hardware/arm_timer.h> | 36 | #include <asm/hardware/arm_timer.h> |
37 | #include <asm/hardware/icst.h> | 37 | #include <asm/hardware/icst.h> |
38 | 38 | ||
39 | #include <mach/cm.h> | ||
40 | #include <mach/lm.h> | 39 | #include <mach/lm.h> |
41 | #include <mach/irqs.h> | ||
42 | 40 | ||
43 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
44 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
@@ -50,6 +48,7 @@ | |||
50 | #include <plat/clcd.h> | 48 | #include <plat/clcd.h> |
51 | #include <plat/sched_clock.h> | 49 | #include <plat/sched_clock.h> |
52 | 50 | ||
51 | #include "cm.h" | ||
53 | #include "common.h" | 52 | #include "common.h" |
54 | 53 | ||
55 | /* Base address to the CP controller */ | 54 | /* Base address to the CP controller */ |
@@ -249,7 +248,6 @@ static void __init intcp_init_early(void) | |||
249 | #endif | 248 | #endif |
250 | } | 249 | } |
251 | 250 | ||
252 | #ifdef CONFIG_OF | ||
253 | static const struct of_device_id fpga_irq_of_match[] __initconst = { | 251 | static const struct of_device_id fpga_irq_of_match[] __initconst = { |
254 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, | 252 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, |
255 | { /* Sentinel */ } | 253 | { /* Sentinel */ } |
@@ -257,6 +255,7 @@ static const struct of_device_id fpga_irq_of_match[] __initconst = { | |||
257 | 255 | ||
258 | static void __init intcp_init_irq_of(void) | 256 | static void __init intcp_init_irq_of(void) |
259 | { | 257 | { |
258 | cm_init(); | ||
260 | of_irq_init(fpga_irq_of_match); | 259 | of_irq_init(fpga_irq_of_match); |
261 | integrator_clk_init(true); | 260 | integrator_clk_init(true); |
262 | } | 261 | } |
@@ -287,6 +286,11 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { | |||
287 | { /* sentinel */ }, | 286 | { /* sentinel */ }, |
288 | }; | 287 | }; |
289 | 288 | ||
289 | static const struct of_device_id intcp_syscon_match[] = { | ||
290 | { .compatible = "arm,integrator-cp-syscon"}, | ||
291 | { }, | ||
292 | }; | ||
293 | |||
290 | static void __init intcp_init_of(void) | 294 | static void __init intcp_init_of(void) |
291 | { | 295 | { |
292 | struct device_node *root; | 296 | struct device_node *root; |
@@ -301,7 +305,8 @@ static void __init intcp_init_of(void) | |||
301 | root = of_find_node_by_path("/"); | 305 | root = of_find_node_by_path("/"); |
302 | if (!root) | 306 | if (!root) |
303 | return; | 307 | return; |
304 | cpcon = of_find_node_by_path("/cpcon"); | 308 | |
309 | cpcon = of_find_matching_node(root, intcp_syscon_match); | ||
305 | if (!cpcon) | 310 | if (!cpcon) |
306 | return; | 311 | return; |
307 | 312 | ||
@@ -354,175 +359,3 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") | |||
354 | .restart = integrator_restart, | 359 | .restart = integrator_restart, |
355 | .dt_compat = intcp_dt_board_compat, | 360 | .dt_compat = intcp_dt_board_compat, |
356 | MACHINE_END | 361 | MACHINE_END |
357 | |||
358 | #endif | ||
359 | |||
360 | #ifdef CONFIG_ATAGS | ||
361 | |||
362 | /* | ||
363 | * For the ATAG boot some static mappings are needed. This will | ||
364 | * go away with the ATAG support down the road. | ||
365 | */ | ||
366 | |||
367 | static struct map_desc intcp_io_desc_atag[] __initdata = { | ||
368 | { | ||
369 | .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE), | ||
370 | .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE), | ||
371 | .length = SZ_4K, | ||
372 | .type = MT_DEVICE | ||
373 | }, | ||
374 | }; | ||
375 | |||
376 | static void __init intcp_map_io_atag(void) | ||
377 | { | ||
378 | iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag)); | ||
379 | intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE); | ||
380 | intcp_map_io(); | ||
381 | } | ||
382 | |||
383 | |||
384 | /* | ||
385 | * This is where non-devicetree initialization code is collected and stashed | ||
386 | * for eventual deletion. | ||
387 | */ | ||
388 | |||
389 | #define INTCP_FLASH_SIZE SZ_32M | ||
390 | |||
391 | static struct resource intcp_flash_resource = { | ||
392 | .start = INTCP_PA_FLASH_BASE, | ||
393 | .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, | ||
394 | .flags = IORESOURCE_MEM, | ||
395 | }; | ||
396 | |||
397 | static struct platform_device intcp_flash_device = { | ||
398 | .name = "physmap-flash", | ||
399 | .id = 0, | ||
400 | .dev = { | ||
401 | .platform_data = &intcp_flash_data, | ||
402 | }, | ||
403 | .num_resources = 1, | ||
404 | .resource = &intcp_flash_resource, | ||
405 | }; | ||
406 | |||
407 | #define INTCP_ETH_SIZE 0x10 | ||
408 | |||
409 | static struct resource smc91x_resources[] = { | ||
410 | [0] = { | ||
411 | .start = INTEGRATOR_CP_ETH_BASE, | ||
412 | .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, | ||
413 | .flags = IORESOURCE_MEM, | ||
414 | }, | ||
415 | [1] = { | ||
416 | .start = IRQ_CP_ETHINT, | ||
417 | .end = IRQ_CP_ETHINT, | ||
418 | .flags = IORESOURCE_IRQ, | ||
419 | }, | ||
420 | }; | ||
421 | |||
422 | static struct platform_device smc91x_device = { | ||
423 | .name = "smc91x", | ||
424 | .id = 0, | ||
425 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
426 | .resource = smc91x_resources, | ||
427 | }; | ||
428 | |||
429 | static struct platform_device *intcp_devs[] __initdata = { | ||
430 | &intcp_flash_device, | ||
431 | &smc91x_device, | ||
432 | }; | ||
433 | |||
434 | #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) | ||
435 | #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) | ||
436 | #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) | ||
437 | |||
438 | static void __init intcp_init_irq(void) | ||
439 | { | ||
440 | u32 pic_mask, cic_mask, sic_mask; | ||
441 | |||
442 | /* These masks are for the HW IRQ registers */ | ||
443 | pic_mask = ~((~0u) << (11 - 0)); | ||
444 | pic_mask |= (~((~0u) << (29 - 22))) << 22; | ||
445 | cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); | ||
446 | sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); | ||
447 | |||
448 | /* | ||
449 | * Disable all interrupt sources | ||
450 | */ | ||
451 | writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | ||
452 | writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); | ||
453 | writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | ||
454 | writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); | ||
455 | writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | ||
456 | writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); | ||
457 | |||
458 | fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, | ||
459 | -1, pic_mask, NULL); | ||
460 | |||
461 | fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, | ||
462 | -1, cic_mask, NULL); | ||
463 | |||
464 | fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, | ||
465 | IRQ_CP_CPPLDINT, sic_mask, NULL); | ||
466 | |||
467 | integrator_clk_init(true); | ||
468 | } | ||
469 | |||
470 | #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) | ||
471 | #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) | ||
472 | #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) | ||
473 | |||
474 | static void __init cp_timer_init(void) | ||
475 | { | ||
476 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | ||
477 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
478 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | ||
479 | |||
480 | sp804_clocksource_init(TIMER2_VA_BASE, "timer2"); | ||
481 | sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); | ||
482 | } | ||
483 | |||
484 | #define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } | ||
485 | #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } | ||
486 | |||
487 | static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE, | ||
488 | INTEGRATOR_CP_MMC_IRQS, &mmc_data); | ||
489 | |||
490 | static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE, | ||
491 | INTEGRATOR_CP_AACI_IRQS, NULL); | ||
492 | |||
493 | static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE, | ||
494 | { IRQ_CP_CLCDCINT }, &clcd_data); | ||
495 | |||
496 | static struct amba_device *amba_devs[] __initdata = { | ||
497 | &mmc_device, | ||
498 | &aaci_device, | ||
499 | &clcd_device, | ||
500 | }; | ||
501 | |||
502 | static void __init intcp_init(void) | ||
503 | { | ||
504 | int i; | ||
505 | |||
506 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); | ||
507 | |||
508 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
509 | struct amba_device *d = amba_devs[i]; | ||
510 | amba_device_register(d, &iomem_resource); | ||
511 | } | ||
512 | integrator_init(true); | ||
513 | } | ||
514 | |||
515 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") | ||
516 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
517 | .atag_offset = 0x100, | ||
518 | .reserve = integrator_reserve, | ||
519 | .map_io = intcp_map_io_atag, | ||
520 | .init_early = intcp_init_early, | ||
521 | .init_irq = intcp_init_irq, | ||
522 | .handle_irq = fpga_handle_irq, | ||
523 | .init_time = cp_timer_init, | ||
524 | .init_machine = intcp_init, | ||
525 | .restart = integrator_restart, | ||
526 | MACHINE_END | ||
527 | |||
528 | #endif | ||
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c index 7a7f6d3273bf..cb6ac58f5e07 100644 --- a/arch/arm/mach-integrator/leds.c +++ b/arch/arm/mach-integrator/leds.c | |||
@@ -11,10 +11,11 @@ | |||
11 | #include <linux/slab.h> | 11 | #include <linux/slab.h> |
12 | #include <linux/leds.h> | 12 | #include <linux/leds.h> |
13 | 13 | ||
14 | #include <mach/cm.h> | ||
15 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
16 | #include <mach/platform.h> | 15 | #include <mach/platform.h> |
17 | 16 | ||
17 | #include "cm.h" | ||
18 | |||
18 | #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) | 19 | #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) |
19 | 20 | ||
20 | #define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE) | 21 | #define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE) |
@@ -78,7 +79,7 @@ static void cm_led_set(struct led_classdev *cdev, | |||
78 | 79 | ||
79 | static enum led_brightness cm_led_get(struct led_classdev *cdev) | 80 | static enum led_brightness cm_led_get(struct led_classdev *cdev) |
80 | { | 81 | { |
81 | u32 reg = readl(CM_CTRL); | 82 | u32 reg = cm_get(); |
82 | 83 | ||
83 | return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF; | 84 | return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF; |
84 | } | 85 | } |
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index bef100527c42..c9c5a33bc802 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c | |||
@@ -36,7 +36,6 @@ | |||
36 | 36 | ||
37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
38 | #include <mach/platform.h> | 38 | #include <mach/platform.h> |
39 | #include <mach/irqs.h> | ||
40 | 39 | ||
41 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
42 | #include <asm/signal.h> | 41 | #include <asm/signal.h> |
@@ -605,7 +604,7 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) | |||
605 | return 1; | 604 | return 1; |
606 | } | 605 | } |
607 | 606 | ||
608 | static irqreturn_t v3_irq(int dummy, void *devid) | 607 | static irqreturn_t v3_irq(int irq, void *devid) |
609 | { | 608 | { |
610 | #ifdef CONFIG_DEBUG_LL | 609 | #ifdef CONFIG_DEBUG_LL |
611 | struct pt_regs *regs = get_irq_regs(); | 610 | struct pt_regs *regs = get_irq_regs(); |
@@ -615,7 +614,7 @@ static irqreturn_t v3_irq(int dummy, void *devid) | |||
615 | extern void printascii(const char *); | 614 | extern void printascii(const char *); |
616 | 615 | ||
617 | sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " | 616 | sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " |
618 | "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, | 617 | "ISTAT=%02x\n", irq, pc, instr, |
619 | __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), | 618 | __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), |
620 | __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, | 619 | __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, |
621 | v3_readb(V3_LB_ISTAT)); | 620 | v3_readb(V3_LB_ISTAT)); |
@@ -809,32 +808,6 @@ static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) | |||
809 | return pci_common_swizzle(dev, pinp); | 808 | return pci_common_swizzle(dev, pinp); |
810 | } | 809 | } |
811 | 810 | ||
812 | static int irq_tab[4] __initdata = { | ||
813 | IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 | ||
814 | }; | ||
815 | |||
816 | /* | ||
817 | * map the specified device/slot/pin to an IRQ. This works out such | ||
818 | * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. | ||
819 | */ | ||
820 | static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | ||
821 | { | ||
822 | int intnr = ((slot - 9) + (pin - 1)) & 3; | ||
823 | |||
824 | return irq_tab[intnr]; | ||
825 | } | ||
826 | |||
827 | static struct hw_pci pci_v3 __initdata = { | ||
828 | .swizzle = pci_v3_swizzle, | ||
829 | .setup = pci_v3_setup, | ||
830 | .nr_controllers = 1, | ||
831 | .ops = &pci_v3_ops, | ||
832 | .preinit = pci_v3_preinit, | ||
833 | .postinit = pci_v3_postinit, | ||
834 | }; | ||
835 | |||
836 | #ifdef CONFIG_OF | ||
837 | |||
838 | static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) | 811 | static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) |
839 | { | 812 | { |
840 | struct of_irq oirq; | 813 | struct of_irq oirq; |
@@ -851,14 +824,36 @@ static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) | |||
851 | oirq.size); | 824 | oirq.size); |
852 | } | 825 | } |
853 | 826 | ||
854 | static int __init pci_v3_dtprobe(struct platform_device *pdev, | 827 | static struct hw_pci pci_v3 __initdata = { |
855 | struct device_node *np) | 828 | .swizzle = pci_v3_swizzle, |
829 | .setup = pci_v3_setup, | ||
830 | .nr_controllers = 1, | ||
831 | .ops = &pci_v3_ops, | ||
832 | .preinit = pci_v3_preinit, | ||
833 | .postinit = pci_v3_postinit, | ||
834 | }; | ||
835 | |||
836 | static int __init pci_v3_probe(struct platform_device *pdev) | ||
856 | { | 837 | { |
838 | struct device_node *np = pdev->dev.of_node; | ||
857 | struct of_pci_range_parser parser; | 839 | struct of_pci_range_parser parser; |
858 | struct of_pci_range range; | 840 | struct of_pci_range range; |
859 | struct resource *res; | 841 | struct resource *res; |
860 | int irq, ret; | 842 | int irq, ret; |
861 | 843 | ||
844 | /* Remap the Integrator system controller */ | ||
845 | ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100); | ||
846 | if (!ap_syscon_base) { | ||
847 | dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); | ||
848 | return -ENODEV; | ||
849 | } | ||
850 | |||
851 | /* Device tree probe path */ | ||
852 | if (!np) { | ||
853 | dev_err(&pdev->dev, "no device tree node for PCIv3\n"); | ||
854 | return -ENODEV; | ||
855 | } | ||
856 | |||
862 | if (of_pci_range_parser_init(&parser, np)) | 857 | if (of_pci_range_parser_init(&parser, np)) |
863 | return -EINVAL; | 858 | return -EINVAL; |
864 | 859 | ||
@@ -925,76 +920,6 @@ static int __init pci_v3_dtprobe(struct platform_device *pdev, | |||
925 | return 0; | 920 | return 0; |
926 | } | 921 | } |
927 | 922 | ||
928 | #else | ||
929 | |||
930 | static inline int pci_v3_dtprobe(struct platform_device *pdev, | ||
931 | struct device_node *np) | ||
932 | { | ||
933 | return -EINVAL; | ||
934 | } | ||
935 | |||
936 | #endif | ||
937 | |||
938 | static int __init pci_v3_probe(struct platform_device *pdev) | ||
939 | { | ||
940 | struct device_node *np = pdev->dev.of_node; | ||
941 | int ret; | ||
942 | |||
943 | /* Remap the Integrator system controller */ | ||
944 | ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); | ||
945 | if (!ap_syscon_base) { | ||
946 | dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); | ||
947 | return -ENODEV; | ||
948 | } | ||
949 | |||
950 | /* Device tree probe path */ | ||
951 | if (np) | ||
952 | return pci_v3_dtprobe(pdev, np); | ||
953 | |||
954 | pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); | ||
955 | if (!pci_v3_base) { | ||
956 | dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); | ||
957 | return -ENODEV; | ||
958 | } | ||
959 | |||
960 | ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); | ||
961 | if (ret) { | ||
962 | dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", | ||
963 | ret); | ||
964 | return -ENODEV; | ||
965 | } | ||
966 | |||
967 | conf_mem.name = "PCIv3 config"; | ||
968 | conf_mem.start = PHYS_PCI_CONFIG_BASE; | ||
969 | conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1; | ||
970 | conf_mem.flags = IORESOURCE_MEM; | ||
971 | |||
972 | io_mem.name = "PCIv3 I/O"; | ||
973 | io_mem.start = PHYS_PCI_IO_BASE; | ||
974 | io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; | ||
975 | io_mem.flags = IORESOURCE_MEM; | ||
976 | |||
977 | non_mem_pci = 0x00000000; | ||
978 | non_mem_pci_sz = SZ_256M; | ||
979 | non_mem.name = "PCIv3 non-prefetched mem"; | ||
980 | non_mem.start = PHYS_PCI_MEM_BASE; | ||
981 | non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1; | ||
982 | non_mem.flags = IORESOURCE_MEM; | ||
983 | |||
984 | pre_mem_pci = 0x10000000; | ||
985 | pre_mem_pci_sz = SZ_256M; | ||
986 | pre_mem.name = "PCIv3 prefetched mem"; | ||
987 | pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M; | ||
988 | pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1; | ||
989 | pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; | ||
990 | |||
991 | pci_v3.map_irq = pci_v3_map_irq; | ||
992 | |||
993 | pci_common_init_dev(&pdev->dev, &pci_v3); | ||
994 | |||
995 | return 0; | ||
996 | } | ||
997 | |||
998 | static const struct of_device_id pci_ids[] = { | 923 | static const struct of_device_id pci_ids[] = { |
999 | { .compatible = "v3,v360epc-pci", }, | 924 | { .compatible = "v3,v360epc-pci", }, |
1000 | {}, | 925 | {}, |
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 366d1a3b418d..f20c53e75ed9 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig | |||
@@ -9,6 +9,8 @@ config ARCH_KEYSTONE | |||
9 | select GENERIC_CLOCKEVENTS | 9 | select GENERIC_CLOCKEVENTS |
10 | select ARCH_WANT_OPTIONAL_GPIOLIB | 10 | select ARCH_WANT_OPTIONAL_GPIOLIB |
11 | select ARM_ERRATA_798181 if SMP | 11 | select ARM_ERRATA_798181 if SMP |
12 | select COMMON_CLK_KEYSTONE | ||
13 | select TI_EDMA | ||
12 | help | 14 | help |
13 | Support for boards based on the Texas Instruments Keystone family of | 15 | Support for boards based on the Texas Instruments Keystone family of |
14 | SoCs. | 16 | SoCs. |
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index ddc52b05dc84..25d92396fbfa 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile | |||
@@ -4,3 +4,6 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec) | |||
4 | AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) | 4 | AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) |
5 | 5 | ||
6 | obj-$(CONFIG_SMP) += platsmp.o | 6 | obj-$(CONFIG_SMP) += platsmp.o |
7 | |||
8 | # PM domain driver for Keystone SOCs | ||
9 | obj-$(CONFIG_ARCH_KEYSTONE) += pm_domain.o | ||
diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c new file mode 100644 index 000000000000..29625232e954 --- /dev/null +++ b/arch/arm/mach-keystone/pm_domain.c | |||
@@ -0,0 +1,82 @@ | |||
1 | /* | ||
2 | * PM domain driver for Keystone2 devices | ||
3 | * | ||
4 | * Copyright 2013 Texas Instruments, Inc. | ||
5 | * Santosh Shilimkar <santosh.shillimkar@ti.com> | ||
6 | * | ||
7 | * Based on Kevins work on DAVINCI SOCs | ||
8 | * Kevin Hilman <khilman@linaro.org> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms and conditions of the GNU General Public License, | ||
12 | * version 2, as published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/pm_runtime.h> | ||
17 | #include <linux/pm_clock.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/clk-provider.h> | ||
20 | #include <linux/of.h> | ||
21 | |||
22 | #ifdef CONFIG_PM_RUNTIME | ||
23 | static int keystone_pm_runtime_suspend(struct device *dev) | ||
24 | { | ||
25 | int ret; | ||
26 | |||
27 | dev_dbg(dev, "%s\n", __func__); | ||
28 | |||
29 | ret = pm_generic_runtime_suspend(dev); | ||
30 | if (ret) | ||
31 | return ret; | ||
32 | |||
33 | ret = pm_clk_suspend(dev); | ||
34 | if (ret) { | ||
35 | pm_generic_runtime_resume(dev); | ||
36 | return ret; | ||
37 | } | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | static int keystone_pm_runtime_resume(struct device *dev) | ||
43 | { | ||
44 | dev_dbg(dev, "%s\n", __func__); | ||
45 | |||
46 | pm_clk_resume(dev); | ||
47 | |||
48 | return pm_generic_runtime_resume(dev); | ||
49 | } | ||
50 | #endif | ||
51 | |||
52 | static struct dev_pm_domain keystone_pm_domain = { | ||
53 | .ops = { | ||
54 | SET_RUNTIME_PM_OPS(keystone_pm_runtime_suspend, | ||
55 | keystone_pm_runtime_resume, NULL) | ||
56 | USE_PLATFORM_PM_SLEEP_OPS | ||
57 | }, | ||
58 | }; | ||
59 | |||
60 | static struct pm_clk_notifier_block platform_domain_notifier = { | ||
61 | .pm_domain = &keystone_pm_domain, | ||
62 | }; | ||
63 | |||
64 | static struct of_device_id of_keystone_table[] = { | ||
65 | {.compatible = "ti,keystone"}, | ||
66 | { /* end of list */ }, | ||
67 | }; | ||
68 | |||
69 | int __init keystone_pm_runtime_init(void) | ||
70 | { | ||
71 | struct device_node *np; | ||
72 | |||
73 | np = of_find_matching_node(NULL, of_keystone_table); | ||
74 | if (!np) | ||
75 | return 0; | ||
76 | |||
77 | of_clk_init(NULL); | ||
78 | pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier); | ||
79 | |||
80 | return 0; | ||
81 | } | ||
82 | subsys_initcall(keystone_pm_runtime_init); | ||
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index d1f8e3d0793b..144b51102939 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile | |||
@@ -1,5 +1,7 @@ | |||
1 | obj-y += common.o pcie.o | 1 | obj-y += common.o pcie.o |
2 | obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o | 2 | obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o |
3 | obj-$(CONFIG_PM) += pm.o | ||
4 | |||
3 | obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o | 5 | obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o |
4 | obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o | 6 | obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o |
5 | obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o | 7 | obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o |
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index a32a3e507a9d..c9f6fd2d90f5 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c | |||
@@ -13,6 +13,8 @@ | |||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/of.h> | 15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> | ||
17 | #include <linux/of_net.h> | ||
16 | #include <linux/of_platform.h> | 18 | #include <linux/of_platform.h> |
17 | #include <linux/clk-provider.h> | 19 | #include <linux/clk-provider.h> |
18 | #include <linux/dma-mapping.h> | 20 | #include <linux/dma-mapping.h> |
@@ -43,14 +45,6 @@ static void __init kirkwood_legacy_clk_init(void) | |||
43 | clkspec.np = np; | 45 | clkspec.np = np; |
44 | clkspec.args_count = 1; | 46 | clkspec.args_count = 1; |
45 | 47 | ||
46 | clkspec.args[0] = CGC_BIT_PEX0; | ||
47 | orion_clkdev_add("0", "pcie", | ||
48 | of_clk_get_from_provider(&clkspec)); | ||
49 | |||
50 | clkspec.args[0] = CGC_BIT_PEX1; | ||
51 | orion_clkdev_add("1", "pcie", | ||
52 | of_clk_get_from_provider(&clkspec)); | ||
53 | |||
54 | /* | 48 | /* |
55 | * The ethernet interfaces forget the MAC address assigned by | 49 | * The ethernet interfaces forget the MAC address assigned by |
56 | * u-boot if the clocks are turned off. Until proper DT support | 50 | * u-boot if the clocks are turned off. Until proper DT support |
@@ -65,11 +59,83 @@ static void __init kirkwood_legacy_clk_init(void) | |||
65 | clk_prepare_enable(clk); | 59 | clk_prepare_enable(clk); |
66 | } | 60 | } |
67 | 61 | ||
68 | static void __init kirkwood_dt_init_early(void) | 62 | #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 |
63 | #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 | ||
64 | |||
65 | static void __init kirkwood_dt_eth_fixup(void) | ||
69 | { | 66 | { |
70 | mvebu_mbus_init("marvell,kirkwood-mbus", | 67 | struct device_node *np; |
71 | BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, | 68 | |
72 | DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); | 69 | /* |
70 | * The ethernet interfaces forget the MAC address assigned by u-boot | ||
71 | * if the clocks are turned off. Usually, u-boot on kirkwood boards | ||
72 | * has no DT support to properly set local-mac-address property. | ||
73 | * As a workaround, we get the MAC address from mv643xx_eth registers | ||
74 | * and update the port device node if no valid MAC address is set. | ||
75 | */ | ||
76 | for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") { | ||
77 | struct device_node *pnp = of_get_parent(np); | ||
78 | struct clk *clk; | ||
79 | struct property *pmac; | ||
80 | void __iomem *io; | ||
81 | u8 *macaddr; | ||
82 | u32 reg; | ||
83 | |||
84 | if (!pnp) | ||
85 | continue; | ||
86 | |||
87 | /* skip disabled nodes or nodes with valid MAC address*/ | ||
88 | if (!of_device_is_available(pnp) || of_get_mac_address(np)) | ||
89 | goto eth_fixup_skip; | ||
90 | |||
91 | clk = of_clk_get(pnp, 0); | ||
92 | if (IS_ERR(clk)) | ||
93 | goto eth_fixup_skip; | ||
94 | |||
95 | io = of_iomap(pnp, 0); | ||
96 | if (!io) | ||
97 | goto eth_fixup_no_map; | ||
98 | |||
99 | /* ensure port clock is not gated to not hang CPU */ | ||
100 | clk_prepare_enable(clk); | ||
101 | |||
102 | /* store MAC address register contents in local-mac-address */ | ||
103 | pr_err(FW_INFO "%s: local-mac-address is not set\n", | ||
104 | np->full_name); | ||
105 | |||
106 | pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); | ||
107 | if (!pmac) | ||
108 | goto eth_fixup_no_mem; | ||
109 | |||
110 | pmac->value = pmac + 1; | ||
111 | pmac->length = 6; | ||
112 | pmac->name = kstrdup("local-mac-address", GFP_KERNEL); | ||
113 | if (!pmac->name) { | ||
114 | kfree(pmac); | ||
115 | goto eth_fixup_no_mem; | ||
116 | } | ||
117 | |||
118 | macaddr = pmac->value; | ||
119 | reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH); | ||
120 | macaddr[0] = (reg >> 24) & 0xff; | ||
121 | macaddr[1] = (reg >> 16) & 0xff; | ||
122 | macaddr[2] = (reg >> 8) & 0xff; | ||
123 | macaddr[3] = reg & 0xff; | ||
124 | |||
125 | reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW); | ||
126 | macaddr[4] = (reg >> 8) & 0xff; | ||
127 | macaddr[5] = reg & 0xff; | ||
128 | |||
129 | of_update_property(np, pmac); | ||
130 | |||
131 | eth_fixup_no_mem: | ||
132 | iounmap(io); | ||
133 | clk_disable_unprepare(clk); | ||
134 | eth_fixup_no_map: | ||
135 | clk_put(clk); | ||
136 | eth_fixup_skip: | ||
137 | of_node_put(pnp); | ||
138 | } | ||
73 | } | 139 | } |
74 | 140 | ||
75 | static void __init kirkwood_dt_init(void) | 141 | static void __init kirkwood_dt_init(void) |
@@ -90,11 +156,12 @@ static void __init kirkwood_dt_init(void) | |||
90 | kirkwood_l2_init(); | 156 | kirkwood_l2_init(); |
91 | 157 | ||
92 | kirkwood_cpufreq_init(); | 158 | kirkwood_cpufreq_init(); |
93 | 159 | kirkwood_cpuidle_init(); | |
94 | /* Setup clocks for legacy devices */ | 160 | /* Setup clocks for legacy devices */ |
95 | kirkwood_legacy_clk_init(); | 161 | kirkwood_legacy_clk_init(); |
96 | 162 | ||
97 | kirkwood_cpuidle_init(); | 163 | kirkwood_pm_init(); |
164 | kirkwood_dt_eth_fixup(); | ||
98 | 165 | ||
99 | #ifdef CONFIG_KEXEC | 166 | #ifdef CONFIG_KEXEC |
100 | kexec_reinit = kirkwood_enable_pcie; | 167 | kexec_reinit = kirkwood_enable_pcie; |
@@ -114,7 +181,6 @@ static const char * const kirkwood_dt_board_compat[] = { | |||
114 | DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") | 181 | DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") |
115 | /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ | 182 | /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ |
116 | .map_io = kirkwood_map_io, | 183 | .map_io = kirkwood_map_io, |
117 | .init_early = kirkwood_dt_init_early, | ||
118 | .init_machine = kirkwood_dt_init, | 184 | .init_machine = kirkwood_dt_init, |
119 | .restart = kirkwood_restart, | 185 | .restart = kirkwood_restart, |
120 | .dt_compat = kirkwood_dt_board_compat, | 186 | .dt_compat = kirkwood_dt_board_compat, |
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 176761134a66..f3407a5db216 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
@@ -721,6 +721,7 @@ void __init kirkwood_init(void) | |||
721 | kirkwood_xor1_init(); | 721 | kirkwood_xor1_init(); |
722 | kirkwood_crypto_init(); | 722 | kirkwood_crypto_init(); |
723 | 723 | ||
724 | kirkwood_pm_init(); | ||
724 | kirkwood_cpuidle_init(); | 725 | kirkwood_cpuidle_init(); |
725 | #ifdef CONFIG_KEXEC | 726 | #ifdef CONFIG_KEXEC |
726 | kexec_reinit = kirkwood_enable_pcie; | 727 | kexec_reinit = kirkwood_enable_pcie; |
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 1296de94febf..05fd648df543 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h | |||
@@ -58,6 +58,12 @@ void kirkwood_cpufreq_init(void); | |||
58 | void kirkwood_restart(enum reboot_mode, const char *); | 58 | void kirkwood_restart(enum reboot_mode, const char *); |
59 | void kirkwood_clk_init(void); | 59 | void kirkwood_clk_init(void); |
60 | 60 | ||
61 | #ifdef CONFIG_PM | ||
62 | void kirkwood_pm_init(void); | ||
63 | #else | ||
64 | static inline void kirkwood_pm_init(void) {}; | ||
65 | #endif | ||
66 | |||
61 | /* board init functions for boards not fully converted to fdt */ | 67 | /* board init functions for boards not fully converted to fdt */ |
62 | #ifdef CONFIG_MACH_MV88F6281GTW_GE_DT | 68 | #ifdef CONFIG_MACH_MV88F6281GTW_GE_DT |
63 | void mv88f6281gtw_ge_init(void); | 69 | void mv88f6281gtw_ge_init(void); |
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 91242c944d7a..8b9d1c9ff199 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |||
@@ -78,4 +78,6 @@ | |||
78 | #define CGC_TDM (1 << 20) | 78 | #define CGC_TDM (1 << 20) |
79 | #define CGC_RESERVED (0x6 << 21) | 79 | #define CGC_RESERVED (0x6 << 21) |
80 | 80 | ||
81 | #define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118) | ||
82 | |||
81 | #endif | 83 | #endif |
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c new file mode 100644 index 000000000000..8783a7184e73 --- /dev/null +++ b/arch/arm/mach-kirkwood/pm.c | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Power Management driver for Marvell Kirkwood SoCs | ||
3 | * | ||
4 | * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> | ||
5 | * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License, | ||
9 | * version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/suspend.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <mach/bridge-regs.h> | ||
21 | |||
22 | static void __iomem *ddr_operation_base; | ||
23 | |||
24 | static void kirkwood_low_power(void) | ||
25 | { | ||
26 | u32 mem_pm_ctrl; | ||
27 | |||
28 | mem_pm_ctrl = readl(MEMORY_PM_CTRL); | ||
29 | |||
30 | /* Set peripherals to low-power mode */ | ||
31 | writel_relaxed(~0, MEMORY_PM_CTRL); | ||
32 | |||
33 | /* Set DDR in self-refresh */ | ||
34 | writel_relaxed(0x7, ddr_operation_base); | ||
35 | |||
36 | /* | ||
37 | * Set CPU in wait-for-interrupt state. | ||
38 | * This disables the CPU core clocks, | ||
39 | * the array clocks, and also the L2 controller. | ||
40 | */ | ||
41 | cpu_do_idle(); | ||
42 | |||
43 | writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL); | ||
44 | } | ||
45 | |||
46 | static int kirkwood_suspend_enter(suspend_state_t state) | ||
47 | { | ||
48 | switch (state) { | ||
49 | case PM_SUSPEND_STANDBY: | ||
50 | kirkwood_low_power(); | ||
51 | break; | ||
52 | default: | ||
53 | return -EINVAL; | ||
54 | } | ||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | static int kirkwood_pm_valid_standby(suspend_state_t state) | ||
59 | { | ||
60 | return state == PM_SUSPEND_STANDBY; | ||
61 | } | ||
62 | |||
63 | static const struct platform_suspend_ops kirkwood_suspend_ops = { | ||
64 | .enter = kirkwood_suspend_enter, | ||
65 | .valid = kirkwood_pm_valid_standby, | ||
66 | }; | ||
67 | |||
68 | int __init kirkwood_pm_init(void) | ||
69 | { | ||
70 | ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); | ||
71 | suspend_set_ops(&kirkwood_suspend_ops); | ||
72 | return 0; | ||
73 | } | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index afb457c3135b..cb7b527d61bd 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -112,13 +112,13 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o | |||
112 | obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o | 112 | obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o |
113 | obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o | 113 | obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o |
114 | obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o | 114 | obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o |
115 | obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o | ||
116 | omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ | 115 | omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ |
117 | prcm_mpu44xx.o prminst44xx.o \ | 116 | prcm_mpu44xx.o prminst44xx.o \ |
118 | vc44xx_data.o vp44xx_data.o | 117 | vc44xx_data.o vp44xx_data.o |
119 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) | 118 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) |
120 | obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) | 119 | obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) |
121 | obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) | 120 | obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) |
121 | obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) | ||
122 | 122 | ||
123 | # OMAP voltage domains | 123 | # OMAP voltage domains |
124 | voltagedomain-common := voltage.o vc.o vp.o | 124 | voltagedomain-common := voltage.o vc.o vp.o |
@@ -146,6 +146,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o | |||
146 | obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) | 146 | obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) |
147 | obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o | 147 | obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o |
148 | obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) | 148 | obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) |
149 | obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o | ||
149 | obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) | 150 | obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) |
150 | obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o | 151 | obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o |
151 | obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) | 152 | obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) |
@@ -165,6 +166,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o | |||
165 | obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) | 166 | obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) |
166 | obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o | 167 | obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o |
167 | obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) | 168 | obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) |
169 | obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o | ||
168 | obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) | 170 | obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) |
169 | obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o | 171 | obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o |
170 | obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) | 172 | obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) |
@@ -210,6 +212,11 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o | |||
210 | obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o | 212 | obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o |
211 | obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o | 213 | obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o |
212 | obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o | 214 | obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o |
215 | obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o | ||
216 | obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o | ||
217 | obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o | ||
218 | obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o | ||
219 | obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o | ||
213 | obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o | 220 | obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o |
214 | obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o | 221 | obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o |
215 | obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o | 222 | obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o |
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 4b03394fa0c5..f17f00697cc0 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h | |||
@@ -132,7 +132,7 @@ struct clockdomain { | |||
132 | u8 _flags; | 132 | u8 _flags; |
133 | const u8 dep_bit; | 133 | const u8 dep_bit; |
134 | const u8 prcm_partition; | 134 | const u8 prcm_partition; |
135 | const s16 cm_inst; | 135 | const u16 cm_inst; |
136 | const u16 clkdm_offs; | 136 | const u16 clkdm_offs; |
137 | struct clkdm_dep *wkdep_srcs; | 137 | struct clkdm_dep *wkdep_srcs; |
138 | struct clkdm_dep *sleepdep_srcs; | 138 | struct clkdm_dep *sleepdep_srcs; |
@@ -218,6 +218,7 @@ extern void __init am33xx_clockdomains_init(void); | |||
218 | extern void __init omap44xx_clockdomains_init(void); | 218 | extern void __init omap44xx_clockdomains_init(void); |
219 | extern void __init omap54xx_clockdomains_init(void); | 219 | extern void __init omap54xx_clockdomains_init(void); |
220 | extern void __init dra7xx_clockdomains_init(void); | 220 | extern void __init dra7xx_clockdomains_init(void); |
221 | void am43xx_clockdomains_init(void); | ||
221 | 222 | ||
222 | extern void clkdm_add_autodeps(struct clockdomain *clkdm); | 223 | extern void clkdm_add_autodeps(struct clockdomain *clkdm); |
223 | extern void clkdm_del_autodeps(struct clockdomain *clkdm); | 224 | extern void clkdm_del_autodeps(struct clockdomain *clkdm); |
@@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_operations; | |||
226 | extern struct clkdm_ops omap3_clkdm_operations; | 227 | extern struct clkdm_ops omap3_clkdm_operations; |
227 | extern struct clkdm_ops omap4_clkdm_operations; | 228 | extern struct clkdm_ops omap4_clkdm_operations; |
228 | extern struct clkdm_ops am33xx_clkdm_operations; | 229 | extern struct clkdm_ops am33xx_clkdm_operations; |
230 | extern struct clkdm_ops am43xx_clkdm_operations; | ||
229 | 231 | ||
230 | extern struct clkdm_dep gfx_24xx_wkdeps[]; | 232 | extern struct clkdm_dep gfx_24xx_wkdeps[]; |
231 | extern struct clkdm_dep dsp_24xx_wkdeps[]; | 233 | extern struct clkdm_dep dsp_24xx_wkdeps[]; |
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c new file mode 100644 index 000000000000..6d71c6082a24 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains43xx_data.c | |||
@@ -0,0 +1,196 @@ | |||
1 | /* | ||
2 | * AM43xx Clock domains framework | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/io.h> | ||
13 | |||
14 | #include "clockdomain.h" | ||
15 | #include "prcm44xx.h" | ||
16 | #include "prcm43xx.h" | ||
17 | |||
18 | static struct clockdomain l4_cefuse_43xx_clkdm = { | ||
19 | .name = "l4_cefuse_clkdm", | ||
20 | .pwrdm = { .name = "cefuse_pwrdm" }, | ||
21 | .prcm_partition = AM43XX_CM_PARTITION, | ||
22 | .cm_inst = AM43XX_CM_CEFUSE_INST, | ||
23 | .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS, | ||
24 | .flags = CLKDM_CAN_SWSUP, | ||
25 | }; | ||
26 | |||
27 | static struct clockdomain mpu_43xx_clkdm = { | ||
28 | .name = "mpu_clkdm", | ||
29 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
30 | .prcm_partition = AM43XX_CM_PARTITION, | ||
31 | .cm_inst = AM43XX_CM_MPU_INST, | ||
32 | .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS, | ||
33 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
34 | }; | ||
35 | |||
36 | static struct clockdomain l4ls_43xx_clkdm = { | ||
37 | .name = "l4ls_clkdm", | ||
38 | .pwrdm = { .name = "per_pwrdm" }, | ||
39 | .prcm_partition = AM43XX_CM_PARTITION, | ||
40 | .cm_inst = AM43XX_CM_PER_INST, | ||
41 | .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS, | ||
42 | .flags = CLKDM_CAN_SWSUP, | ||
43 | }; | ||
44 | |||
45 | static struct clockdomain tamper_43xx_clkdm = { | ||
46 | .name = "tamper_clkdm", | ||
47 | .pwrdm = { .name = "tamper_pwrdm" }, | ||
48 | .prcm_partition = AM43XX_CM_PARTITION, | ||
49 | .cm_inst = AM43XX_CM_TAMPER_INST, | ||
50 | .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS, | ||
51 | .flags = CLKDM_CAN_SWSUP, | ||
52 | }; | ||
53 | |||
54 | static struct clockdomain l4_rtc_43xx_clkdm = { | ||
55 | .name = "l4_rtc_clkdm", | ||
56 | .pwrdm = { .name = "rtc_pwrdm" }, | ||
57 | .prcm_partition = AM43XX_CM_PARTITION, | ||
58 | .cm_inst = AM43XX_CM_RTC_INST, | ||
59 | .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS, | ||
60 | .flags = CLKDM_CAN_SWSUP, | ||
61 | }; | ||
62 | |||
63 | static struct clockdomain pruss_ocp_43xx_clkdm = { | ||
64 | .name = "pruss_ocp_clkdm", | ||
65 | .pwrdm = { .name = "per_pwrdm" }, | ||
66 | .prcm_partition = AM43XX_CM_PARTITION, | ||
67 | .cm_inst = AM43XX_CM_PER_INST, | ||
68 | .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS, | ||
69 | .flags = CLKDM_CAN_SWSUP, | ||
70 | }; | ||
71 | |||
72 | static struct clockdomain ocpwp_l3_43xx_clkdm = { | ||
73 | .name = "ocpwp_l3_clkdm", | ||
74 | .pwrdm = { .name = "per_pwrdm" }, | ||
75 | .prcm_partition = AM43XX_CM_PARTITION, | ||
76 | .cm_inst = AM43XX_CM_PER_INST, | ||
77 | .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS, | ||
78 | .flags = CLKDM_CAN_SWSUP, | ||
79 | }; | ||
80 | |||
81 | static struct clockdomain l3s_tsc_43xx_clkdm = { | ||
82 | .name = "l3s_tsc_clkdm", | ||
83 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
84 | .prcm_partition = AM43XX_CM_PARTITION, | ||
85 | .cm_inst = AM43XX_CM_WKUP_INST, | ||
86 | .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS, | ||
87 | .flags = CLKDM_CAN_SWSUP, | ||
88 | }; | ||
89 | |||
90 | static struct clockdomain dss_43xx_clkdm = { | ||
91 | .name = "dss_clkdm", | ||
92 | .pwrdm = { .name = "per_pwrdm" }, | ||
93 | .prcm_partition = AM43XX_CM_PARTITION, | ||
94 | .cm_inst = AM43XX_CM_PER_INST, | ||
95 | .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS, | ||
96 | .flags = CLKDM_CAN_SWSUP, | ||
97 | }; | ||
98 | |||
99 | static struct clockdomain l3_aon_43xx_clkdm = { | ||
100 | .name = "l3_aon_clkdm", | ||
101 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
102 | .prcm_partition = AM43XX_CM_PARTITION, | ||
103 | .cm_inst = AM43XX_CM_WKUP_INST, | ||
104 | .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS, | ||
105 | .flags = CLKDM_CAN_SWSUP, | ||
106 | }; | ||
107 | |||
108 | static struct clockdomain emif_43xx_clkdm = { | ||
109 | .name = "emif_clkdm", | ||
110 | .pwrdm = { .name = "per_pwrdm" }, | ||
111 | .prcm_partition = AM43XX_CM_PARTITION, | ||
112 | .cm_inst = AM43XX_CM_PER_INST, | ||
113 | .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS, | ||
114 | .flags = CLKDM_CAN_SWSUP, | ||
115 | }; | ||
116 | |||
117 | static struct clockdomain l4_wkup_aon_43xx_clkdm = { | ||
118 | .name = "l4_wkup_aon_clkdm", | ||
119 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
120 | .prcm_partition = AM43XX_CM_PARTITION, | ||
121 | .cm_inst = AM43XX_CM_WKUP_INST, | ||
122 | .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS, | ||
123 | }; | ||
124 | |||
125 | static struct clockdomain l3_43xx_clkdm = { | ||
126 | .name = "l3_clkdm", | ||
127 | .pwrdm = { .name = "per_pwrdm" }, | ||
128 | .prcm_partition = AM43XX_CM_PARTITION, | ||
129 | .cm_inst = AM43XX_CM_PER_INST, | ||
130 | .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS, | ||
131 | .flags = CLKDM_CAN_SWSUP, | ||
132 | }; | ||
133 | |||
134 | static struct clockdomain l4_wkup_43xx_clkdm = { | ||
135 | .name = "l4_wkup_clkdm", | ||
136 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
137 | .prcm_partition = AM43XX_CM_PARTITION, | ||
138 | .cm_inst = AM43XX_CM_WKUP_INST, | ||
139 | .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS, | ||
140 | .flags = CLKDM_CAN_SWSUP, | ||
141 | }; | ||
142 | |||
143 | static struct clockdomain cpsw_125mhz_43xx_clkdm = { | ||
144 | .name = "cpsw_125mhz_clkdm", | ||
145 | .pwrdm = { .name = "per_pwrdm" }, | ||
146 | .prcm_partition = AM43XX_CM_PARTITION, | ||
147 | .cm_inst = AM43XX_CM_PER_INST, | ||
148 | .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS, | ||
149 | .flags = CLKDM_CAN_SWSUP, | ||
150 | }; | ||
151 | |||
152 | static struct clockdomain gfx_l3_43xx_clkdm = { | ||
153 | .name = "gfx_l3_clkdm", | ||
154 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
155 | .prcm_partition = AM43XX_CM_PARTITION, | ||
156 | .cm_inst = AM43XX_CM_GFX_INST, | ||
157 | .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS, | ||
158 | .flags = CLKDM_CAN_SWSUP, | ||
159 | }; | ||
160 | |||
161 | static struct clockdomain l3s_43xx_clkdm = { | ||
162 | .name = "l3s_clkdm", | ||
163 | .pwrdm = { .name = "per_pwrdm" }, | ||
164 | .prcm_partition = AM43XX_CM_PARTITION, | ||
165 | .cm_inst = AM43XX_CM_PER_INST, | ||
166 | .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS, | ||
167 | .flags = CLKDM_CAN_SWSUP, | ||
168 | }; | ||
169 | |||
170 | static struct clockdomain *clockdomains_am43xx[] __initdata = { | ||
171 | &l4_cefuse_43xx_clkdm, | ||
172 | &mpu_43xx_clkdm, | ||
173 | &l4ls_43xx_clkdm, | ||
174 | &tamper_43xx_clkdm, | ||
175 | &l4_rtc_43xx_clkdm, | ||
176 | &pruss_ocp_43xx_clkdm, | ||
177 | &ocpwp_l3_43xx_clkdm, | ||
178 | &l3s_tsc_43xx_clkdm, | ||
179 | &dss_43xx_clkdm, | ||
180 | &l3_aon_43xx_clkdm, | ||
181 | &emif_43xx_clkdm, | ||
182 | &l4_wkup_aon_43xx_clkdm, | ||
183 | &l3_43xx_clkdm, | ||
184 | &l4_wkup_43xx_clkdm, | ||
185 | &cpsw_125mhz_43xx_clkdm, | ||
186 | &gfx_l3_43xx_clkdm, | ||
187 | &l3s_43xx_clkdm, | ||
188 | NULL | ||
189 | }; | ||
190 | |||
191 | void __init am43xx_clockdomains_init(void) | ||
192 | { | ||
193 | clkdm_register_platform_funcs(&am43xx_clkdm_operations); | ||
194 | clkdm_register_clkdms(clockdomains_am43xx); | ||
195 | clkdm_complete_init(); | ||
196 | } | ||
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index 325a51576576..40a22e5649ae 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c | |||
@@ -48,13 +48,13 @@ | |||
48 | /* Private functions */ | 48 | /* Private functions */ |
49 | 49 | ||
50 | /* Read a register in a CM instance */ | 50 | /* Read a register in a CM instance */ |
51 | static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) | 51 | static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) |
52 | { | 52 | { |
53 | return __raw_readl(cm_base + inst + idx); | 53 | return __raw_readl(cm_base + inst + idx); |
54 | } | 54 | } |
55 | 55 | ||
56 | /* Write into a register in a CM */ | 56 | /* Write into a register in a CM */ |
57 | static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) | 57 | static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) |
58 | { | 58 | { |
59 | __raw_writel(val, cm_base + inst + idx); | 59 | __raw_writel(val, cm_base + inst + idx); |
60 | } | 60 | } |
@@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) | |||
138 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function | 138 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function |
139 | * will handle the shift itself. | 139 | * will handle the shift itself. |
140 | */ | 140 | */ |
141 | static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) | 141 | static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) |
142 | { | 142 | { |
143 | u32 v; | 143 | u32 v; |
144 | 144 | ||
@@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) | |||
158 | * Returns true if the clockdomain referred to by (@inst, @cdoffs) | 158 | * Returns true if the clockdomain referred to by (@inst, @cdoffs) |
159 | * is in hardware-supervised idle mode, or 0 otherwise. | 159 | * is in hardware-supervised idle mode, or 0 otherwise. |
160 | */ | 160 | */ |
161 | bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) | 161 | bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) |
162 | { | 162 | { |
163 | u32 v; | 163 | u32 v; |
164 | 164 | ||
@@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) | |||
177 | * Put a clockdomain referred to by (@inst, @cdoffs) into | 177 | * Put a clockdomain referred to by (@inst, @cdoffs) into |
178 | * hardware-supervised idle mode. No return value. | 178 | * hardware-supervised idle mode. No return value. |
179 | */ | 179 | */ |
180 | void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) | 180 | void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) |
181 | { | 181 | { |
182 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); | 182 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); |
183 | } | 183 | } |
@@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) | |||
191 | * software-supervised idle mode, i.e., controlled manually by the | 191 | * software-supervised idle mode, i.e., controlled manually by the |
192 | * Linux OMAP clockdomain code. No return value. | 192 | * Linux OMAP clockdomain code. No return value. |
193 | */ | 193 | */ |
194 | void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) | 194 | void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) |
195 | { | 195 | { |
196 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); | 196 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); |
197 | } | 197 | } |
@@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) | |||
204 | * Put a clockdomain referred to by (@inst, @cdoffs) into idle | 204 | * Put a clockdomain referred to by (@inst, @cdoffs) into idle |
205 | * No return value. | 205 | * No return value. |
206 | */ | 206 | */ |
207 | void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) | 207 | void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) |
208 | { | 208 | { |
209 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); | 209 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); |
210 | } | 210 | } |
@@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) | |||
217 | * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, | 217 | * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, |
218 | * waking it up. No return value. | 218 | * waking it up. No return value. |
219 | */ | 219 | */ |
220 | void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) | 220 | void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs) |
221 | { | 221 | { |
222 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); | 222 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); |
223 | } | 223 | } |
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index 9d1f4fcdebbb..cfb8891b0c0e 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h | |||
@@ -377,13 +377,13 @@ | |||
377 | 377 | ||
378 | 378 | ||
379 | #ifndef __ASSEMBLER__ | 379 | #ifndef __ASSEMBLER__ |
380 | extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); | 380 | bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs); |
381 | extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); | 381 | void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs); |
382 | extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); | 382 | void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs); |
383 | extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); | 383 | void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs); |
384 | extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); | 384 | void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs); |
385 | 385 | ||
386 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) | 386 | #ifdef CONFIG_SOC_AM33XX |
387 | extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, | 387 | extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, |
388 | u16 clkctrl_offs); | 388 | u16 clkctrl_offs); |
389 | extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, | 389 | extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, |
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index f0290f5566fe..731ca134348c 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c | |||
@@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) | |||
111 | /* Public functions */ | 111 | /* Public functions */ |
112 | 112 | ||
113 | /* Read a register in a CM instance */ | 113 | /* Read a register in a CM instance */ |
114 | u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) | 114 | u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) |
115 | { | 115 | { |
116 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || | 116 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || |
117 | part == OMAP4430_INVALID_PRCM_PARTITION || | 117 | part == OMAP4430_INVALID_PRCM_PARTITION || |
@@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) | |||
120 | } | 120 | } |
121 | 121 | ||
122 | /* Write into a register in a CM instance */ | 122 | /* Write into a register in a CM instance */ |
123 | void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) | 123 | void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) |
124 | { | 124 | { |
125 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || | 125 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || |
126 | part == OMAP4430_INVALID_PRCM_PARTITION || | 126 | part == OMAP4430_INVALID_PRCM_PARTITION || |
@@ -129,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) | |||
129 | } | 129 | } |
130 | 130 | ||
131 | /* Read-modify-write a register in CM1. Caller must lock */ | 131 | /* Read-modify-write a register in CM1. Caller must lock */ |
132 | u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, | 132 | u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, |
133 | s16 idx) | 133 | s16 idx) |
134 | { | 134 | { |
135 | u32 v; | 135 | u32 v; |
@@ -142,12 +142,12 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, | |||
142 | return v; | 142 | return v; |
143 | } | 143 | } |
144 | 144 | ||
145 | u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) | 145 | u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) |
146 | { | 146 | { |
147 | return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); | 147 | return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); |
148 | } | 148 | } |
149 | 149 | ||
150 | u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) | 150 | u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) |
151 | { | 151 | { |
152 | return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); | 152 | return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); |
153 | } | 153 | } |
@@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) | |||
177 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function | 177 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function |
178 | * will handle the shift itself. | 178 | * will handle the shift itself. |
179 | */ | 179 | */ |
180 | static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) | 180 | static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) |
181 | { | 181 | { |
182 | u32 v; | 182 | u32 v; |
183 | 183 | ||
@@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) | |||
196 | * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) | 196 | * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) |
197 | * is in hardware-supervised idle mode, or 0 otherwise. | 197 | * is in hardware-supervised idle mode, or 0 otherwise. |
198 | */ | 198 | */ |
199 | bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) | 199 | bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) |
200 | { | 200 | { |
201 | u32 v; | 201 | u32 v; |
202 | 202 | ||
@@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) | |||
216 | * Put a clockdomain referred to by (@part, @inst, @cdoffs) into | 216 | * Put a clockdomain referred to by (@part, @inst, @cdoffs) into |
217 | * hardware-supervised idle mode. No return value. | 217 | * hardware-supervised idle mode. No return value. |
218 | */ | 218 | */ |
219 | void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) | 219 | void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) |
220 | { | 220 | { |
221 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); | 221 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); |
222 | } | 222 | } |
@@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) | |||
231 | * software-supervised idle mode, i.e., controlled manually by the | 231 | * software-supervised idle mode, i.e., controlled manually by the |
232 | * Linux OMAP clockdomain code. No return value. | 232 | * Linux OMAP clockdomain code. No return value. |
233 | */ | 233 | */ |
234 | void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) | 234 | void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) |
235 | { | 235 | { |
236 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); | 236 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); |
237 | } | 237 | } |
@@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) | |||
245 | * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, | 245 | * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, |
246 | * waking it up. No return value. | 246 | * waking it up. No return value. |
247 | */ | 247 | */ |
248 | void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) | 248 | void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) |
249 | { | 249 | { |
250 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); | 250 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); |
251 | } | 251 | } |
@@ -483,3 +483,12 @@ struct clkdm_ops omap4_clkdm_operations = { | |||
483 | .clkdm_clk_enable = omap4_clkdm_clk_enable, | 483 | .clkdm_clk_enable = omap4_clkdm_clk_enable, |
484 | .clkdm_clk_disable = omap4_clkdm_clk_disable, | 484 | .clkdm_clk_disable = omap4_clkdm_clk_disable, |
485 | }; | 485 | }; |
486 | |||
487 | struct clkdm_ops am43xx_clkdm_operations = { | ||
488 | .clkdm_sleep = omap4_clkdm_sleep, | ||
489 | .clkdm_wakeup = omap4_clkdm_wakeup, | ||
490 | .clkdm_allow_idle = omap4_clkdm_allow_idle, | ||
491 | .clkdm_deny_idle = omap4_clkdm_deny_idle, | ||
492 | .clkdm_clk_enable = omap4_clkdm_clk_enable, | ||
493 | .clkdm_clk_disable = omap4_clkdm_clk_disable, | ||
494 | }; | ||
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h index bd7bab889745..7f56ea444bc4 100644 --- a/arch/arm/mach-omap2/cminst44xx.h +++ b/arch/arm/mach-omap2/cminst44xx.h | |||
@@ -11,11 +11,11 @@ | |||
11 | #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H | 11 | #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H |
12 | #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H | 12 | #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H |
13 | 13 | ||
14 | extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs); | 14 | bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs); |
15 | extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs); | 15 | void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs); |
16 | extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); | 16 | void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs); |
17 | extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); | 17 | void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs); |
18 | extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); | 18 | void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs); |
19 | extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); | 19 | extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); |
20 | extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, | 20 | extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, |
21 | u16 clkctrl_offs); | 21 | u16 clkctrl_offs); |
@@ -27,14 +27,14 @@ extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, | |||
27 | * In an ideal world, we would not export these low-level functions, | 27 | * In an ideal world, we would not export these low-level functions, |
28 | * but this will probably take some time to fix properly | 28 | * but this will probably take some time to fix properly |
29 | */ | 29 | */ |
30 | extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); | 30 | u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx); |
31 | extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); | 31 | void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx); |
32 | extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, | 32 | u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, |
33 | s16 inst, s16 idx); | 33 | u16 inst, s16 idx); |
34 | extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, | 34 | u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, |
35 | s16 idx); | 35 | s16 idx); |
36 | extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, | 36 | u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, |
37 | s16 idx); | 37 | s16 idx); |
38 | extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, | 38 | extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, |
39 | u32 mask); | 39 | u32 mask); |
40 | 40 | ||
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index ef32d11c4bca..9428c5f9d4f2 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
@@ -588,8 +588,8 @@ void __init omap5xxx_check_revision(void) | |||
588 | case 0xb942: | 588 | case 0xb942: |
589 | switch (rev) { | 589 | switch (rev) { |
590 | case 0: | 590 | case 0: |
591 | omap_revision = OMAP5430_REV_ES1_0; | 591 | /* No support for ES1.0 Test chip */ |
592 | break; | 592 | BUG(); |
593 | case 1: | 593 | case 1: |
594 | default: | 594 | default: |
595 | omap_revision = OMAP5430_REV_ES2_0; | 595 | omap_revision = OMAP5430_REV_ES2_0; |
@@ -599,8 +599,8 @@ void __init omap5xxx_check_revision(void) | |||
599 | case 0xb998: | 599 | case 0xb998: |
600 | switch (rev) { | 600 | switch (rev) { |
601 | case 0: | 601 | case 0: |
602 | omap_revision = OMAP5432_REV_ES1_0; | 602 | /* No support for ES1.0 Test chip */ |
603 | break; | 603 | BUG(); |
604 | case 1: | 604 | case 1: |
605 | default: | 605 | default: |
606 | omap_revision = OMAP5432_REV_ES2_0; | 606 | omap_revision = OMAP5432_REV_ES2_0; |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index ff2113ce4014..c90f64765a3d 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -594,7 +594,13 @@ void __init am43xx_init_early(void) | |||
594 | NULL); | 594 | NULL); |
595 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); | 595 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); |
596 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); | 596 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); |
597 | omap_prm_base_init(); | ||
598 | omap_cm_base_init(); | ||
597 | omap3xxx_check_revision(); | 599 | omap3xxx_check_revision(); |
600 | am43xx_powerdomains_init(); | ||
601 | am43xx_clockdomains_init(); | ||
602 | am43xx_hwmod_init(); | ||
603 | omap_hwmod_init_postsetup(); | ||
598 | } | 604 | } |
599 | #endif | 605 | #endif |
600 | 606 | ||
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 0e729170c46b..a5ee09d20ac9 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h | |||
@@ -42,6 +42,8 @@ | |||
42 | #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 | 42 | #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 |
43 | #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 | 43 | #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 |
44 | 44 | ||
45 | #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 | ||
46 | |||
45 | /* Secure PPA(Primary Protected Application) APIs */ | 47 | /* Secure PPA(Primary Protected Application) APIs */ |
46 | #define OMAP4_PPA_L2_POR_INDEX 0x23 | 48 | #define OMAP4_PPA_L2_POR_INDEX 0x23 |
47 | #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 | 49 | #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 |
@@ -60,5 +62,7 @@ extern int omap_barrier_reserve_memblock(void); | |||
60 | static inline void omap_barrier_reserve_memblock(void) | 62 | static inline void omap_barrier_reserve_memblock(void) |
61 | { } | 63 | { } |
62 | #endif | 64 | #endif |
65 | |||
66 | void set_cntfreq(void); | ||
63 | #endif /* __ASSEMBLER__ */ | 67 | #endif /* __ASSEMBLER__ */ |
64 | #endif /* OMAP_ARCH_OMAP_SECURE_H */ | 68 | #endif /* OMAP_ARCH_OMAP_SECURE_H */ |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 891211093295..75e95d4fb448 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
@@ -66,6 +66,13 @@ static void omap4_secondary_init(unsigned int cpu) | |||
66 | 4, 0, 0, 0, 0, 0); | 66 | 4, 0, 0, 0, 0, 0); |
67 | 67 | ||
68 | /* | 68 | /* |
69 | * Configure the CNTFRQ register for the secondary cpu's which | ||
70 | * indicates the frequency of the cpu local timers. | ||
71 | */ | ||
72 | if (soc_is_omap54xx() || soc_is_dra7xx()) | ||
73 | set_cntfreq(); | ||
74 | |||
75 | /* | ||
69 | * Synchronise with the boot thread. | 76 | * Synchronise with the boot thread. |
70 | */ | 77 | */ |
71 | spin_lock(&boot_lock); | 78 | spin_lock(&boot_lock); |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index d9ee0ff094d4..e3f0ecaf87dd 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -2357,25 +2357,29 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np, | |||
2357 | /** | 2357 | /** |
2358 | * _init_mpu_rt_base - populate the virtual address for a hwmod | 2358 | * _init_mpu_rt_base - populate the virtual address for a hwmod |
2359 | * @oh: struct omap_hwmod * to locate the virtual address | 2359 | * @oh: struct omap_hwmod * to locate the virtual address |
2360 | * @data: (unused, caller should pass NULL) | ||
2361 | * @np: struct device_node * of the IP block's device node in the DT data | ||
2360 | * | 2362 | * |
2361 | * Cache the virtual address used by the MPU to access this IP block's | 2363 | * Cache the virtual address used by the MPU to access this IP block's |
2362 | * registers. This address is needed early so the OCP registers that | 2364 | * registers. This address is needed early so the OCP registers that |
2363 | * are part of the device's address space can be ioremapped properly. | 2365 | * are part of the device's address space can be ioremapped properly. |
2364 | * No return value. | 2366 | * |
2367 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and | ||
2368 | * -ENXIO on absent or invalid register target address space. | ||
2365 | */ | 2369 | */ |
2366 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | 2370 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
2371 | struct device_node *np) | ||
2367 | { | 2372 | { |
2368 | struct omap_hwmod_addr_space *mem; | 2373 | struct omap_hwmod_addr_space *mem; |
2369 | void __iomem *va_start = NULL; | 2374 | void __iomem *va_start = NULL; |
2370 | struct device_node *np; | ||
2371 | 2375 | ||
2372 | if (!oh) | 2376 | if (!oh) |
2373 | return; | 2377 | return -EINVAL; |
2374 | 2378 | ||
2375 | _save_mpu_port_index(oh); | 2379 | _save_mpu_port_index(oh); |
2376 | 2380 | ||
2377 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | 2381 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2378 | return; | 2382 | return -ENXIO; |
2379 | 2383 | ||
2380 | mem = _find_mpu_rt_addr_space(oh); | 2384 | mem = _find_mpu_rt_addr_space(oh); |
2381 | if (!mem) { | 2385 | if (!mem) { |
@@ -2383,25 +2387,24 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |||
2383 | oh->name); | 2387 | oh->name); |
2384 | 2388 | ||
2385 | /* Extract the IO space from device tree blob */ | 2389 | /* Extract the IO space from device tree blob */ |
2386 | if (!of_have_populated_dt()) | 2390 | if (!np) |
2387 | return; | 2391 | return -ENXIO; |
2388 | 2392 | ||
2389 | np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); | 2393 | va_start = of_iomap(np, oh->mpu_rt_idx); |
2390 | if (np) | ||
2391 | va_start = of_iomap(np, oh->mpu_rt_idx); | ||
2392 | } else { | 2394 | } else { |
2393 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | 2395 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); |
2394 | } | 2396 | } |
2395 | 2397 | ||
2396 | if (!va_start) { | 2398 | if (!va_start) { |
2397 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | 2399 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); |
2398 | return; | 2400 | return -ENXIO; |
2399 | } | 2401 | } |
2400 | 2402 | ||
2401 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | 2403 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
2402 | oh->name, va_start); | 2404 | oh->name, va_start); |
2403 | 2405 | ||
2404 | oh->_mpu_rt_va = va_start; | 2406 | oh->_mpu_rt_va = va_start; |
2407 | return 0; | ||
2405 | } | 2408 | } |
2406 | 2409 | ||
2407 | /** | 2410 | /** |
@@ -2414,18 +2417,28 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |||
2414 | * registered at this point. This is the first of two phases for | 2417 | * registered at this point. This is the first of two phases for |
2415 | * hwmod initialization. Code called here does not touch any hardware | 2418 | * hwmod initialization. Code called here does not touch any hardware |
2416 | * registers, it simply prepares internal data structures. Returns 0 | 2419 | * registers, it simply prepares internal data structures. Returns 0 |
2417 | * upon success or if the hwmod isn't registered, or -EINVAL upon | 2420 | * upon success or if the hwmod isn't registered or if the hwmod's |
2418 | * failure. | 2421 | * address space is not defined, or -EINVAL upon failure. |
2419 | */ | 2422 | */ |
2420 | static int __init _init(struct omap_hwmod *oh, void *data) | 2423 | static int __init _init(struct omap_hwmod *oh, void *data) |
2421 | { | 2424 | { |
2422 | int r; | 2425 | int r; |
2426 | struct device_node *np = NULL; | ||
2423 | 2427 | ||
2424 | if (oh->_state != _HWMOD_STATE_REGISTERED) | 2428 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
2425 | return 0; | 2429 | return 0; |
2426 | 2430 | ||
2427 | if (oh->class->sysc) | 2431 | if (of_have_populated_dt()) |
2428 | _init_mpu_rt_base(oh, NULL); | 2432 | np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); |
2433 | |||
2434 | if (oh->class->sysc) { | ||
2435 | r = _init_mpu_rt_base(oh, NULL, np); | ||
2436 | if (r < 0) { | ||
2437 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | ||
2438 | oh->name); | ||
2439 | return 0; | ||
2440 | } | ||
2441 | } | ||
2429 | 2442 | ||
2430 | r = _init_clocks(oh, NULL); | 2443 | r = _init_clocks(oh, NULL); |
2431 | if (r < 0) { | 2444 | if (r < 0) { |
@@ -2433,6 +2446,12 @@ static int __init _init(struct omap_hwmod *oh, void *data) | |||
2433 | return -EINVAL; | 2446 | return -EINVAL; |
2434 | } | 2447 | } |
2435 | 2448 | ||
2449 | if (np) | ||
2450 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) | ||
2451 | oh->flags |= HWMOD_INIT_NO_RESET; | ||
2452 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | ||
2453 | oh->flags |= HWMOD_INIT_NO_IDLE; | ||
2454 | |||
2436 | oh->_state = _HWMOD_STATE_INITIALIZED; | 2455 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2437 | 2456 | ||
2438 | return 0; | 2457 | return 0; |
@@ -4125,6 +4144,14 @@ void __init omap_hwmod_init(void) | |||
4125 | soc_ops.init_clkdm = _init_clkdm; | 4144 | soc_ops.init_clkdm = _init_clkdm; |
4126 | soc_ops.update_context_lost = _omap4_update_context_lost; | 4145 | soc_ops.update_context_lost = _omap4_update_context_lost; |
4127 | soc_ops.get_context_lost = _omap4_get_context_lost; | 4146 | soc_ops.get_context_lost = _omap4_get_context_lost; |
4147 | } else if (soc_is_am43xx()) { | ||
4148 | soc_ops.enable_module = _omap4_enable_module; | ||
4149 | soc_ops.disable_module = _omap4_disable_module; | ||
4150 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | ||
4151 | soc_ops.assert_hardreset = _omap4_assert_hardreset; | ||
4152 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | ||
4153 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | ||
4154 | soc_ops.init_clkdm = _init_clkdm; | ||
4128 | } else if (soc_is_am33xx()) { | 4155 | } else if (soc_is_am33xx()) { |
4129 | soc_ops.enable_module = _am33xx_enable_module; | 4156 | soc_ops.enable_module = _am33xx_enable_module; |
4130 | soc_ops.disable_module = _am33xx_disable_module; | 4157 | soc_ops.disable_module = _am33xx_disable_module; |
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index d02acf9308d3..0f97d635ff90 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h | |||
@@ -752,6 +752,7 @@ extern int omap44xx_hwmod_init(void); | |||
752 | extern int omap54xx_hwmod_init(void); | 752 | extern int omap54xx_hwmod_init(void); |
753 | extern int am33xx_hwmod_init(void); | 753 | extern int am33xx_hwmod_init(void); |
754 | extern int dra7xx_hwmod_init(void); | 754 | extern int dra7xx_hwmod_init(void); |
755 | int am43xx_hwmod_init(void); | ||
755 | 756 | ||
756 | extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); | 757 | extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); |
757 | 758 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h new file mode 100644 index 000000000000..130332c0534d --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h | |||
@@ -0,0 +1,163 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
4 | * | ||
5 | * Data common for AM335x and AM43x | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License as | ||
9 | * published by the Free Software Foundation version 2. | ||
10 | * | ||
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
12 | * kind, whether express or implied; without even the implied warranty | ||
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H | ||
18 | #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H | ||
19 | |||
20 | extern struct omap_hwmod_ocp_if am33xx_mpu__l3_main; | ||
21 | extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s; | ||
22 | extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls; | ||
23 | extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup; | ||
24 | extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr; | ||
25 | extern struct omap_hwmod_ocp_if am33xx_mpu__prcm; | ||
26 | extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; | ||
27 | extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main; | ||
28 | extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; | ||
29 | extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; | ||
30 | extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc; | ||
31 | extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0; | ||
32 | extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1; | ||
33 | extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio1; | ||
34 | extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio2; | ||
35 | extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3; | ||
36 | extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio; | ||
37 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm; | ||
38 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0; | ||
39 | extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0; | ||
40 | extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0; | ||
41 | extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0; | ||
42 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1; | ||
43 | extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1; | ||
44 | extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1; | ||
45 | extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1; | ||
46 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2; | ||
47 | extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2; | ||
48 | extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2; | ||
49 | extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2; | ||
50 | extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; | ||
51 | extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2; | ||
52 | extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3; | ||
53 | extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox; | ||
54 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock; | ||
55 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0; | ||
56 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1; | ||
57 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0; | ||
58 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1; | ||
59 | extern struct omap_hwmod_ocp_if am33xx_l3_s__mmc2; | ||
60 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0; | ||
61 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1; | ||
62 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; | ||
63 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3; | ||
64 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4; | ||
65 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5; | ||
66 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6; | ||
67 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7; | ||
68 | extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc; | ||
69 | extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0; | ||
70 | extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1; | ||
71 | extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2; | ||
72 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart2; | ||
73 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart3; | ||
74 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart4; | ||
75 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart5; | ||
76 | extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6; | ||
77 | extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; | ||
78 | extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0; | ||
79 | extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0; | ||
80 | |||
81 | extern struct omap_hwmod am33xx_l3_main_hwmod; | ||
82 | extern struct omap_hwmod am33xx_l3_s_hwmod; | ||
83 | extern struct omap_hwmod am33xx_l3_instr_hwmod; | ||
84 | extern struct omap_hwmod am33xx_l4_ls_hwmod; | ||
85 | extern struct omap_hwmod am33xx_l4_wkup_hwmod; | ||
86 | extern struct omap_hwmod am33xx_mpu_hwmod; | ||
87 | extern struct omap_hwmod am33xx_pruss_hwmod; | ||
88 | extern struct omap_hwmod am33xx_gfx_hwmod; | ||
89 | extern struct omap_hwmod am33xx_prcm_hwmod; | ||
90 | extern struct omap_hwmod am33xx_aes0_hwmod; | ||
91 | extern struct omap_hwmod am33xx_sha0_hwmod; | ||
92 | extern struct omap_hwmod am33xx_ocmcram_hwmod; | ||
93 | extern struct omap_hwmod am33xx_smartreflex0_hwmod; | ||
94 | extern struct omap_hwmod am33xx_smartreflex1_hwmod; | ||
95 | extern struct omap_hwmod am33xx_cpgmac0_hwmod; | ||
96 | extern struct omap_hwmod am33xx_mdio_hwmod; | ||
97 | extern struct omap_hwmod am33xx_dcan0_hwmod; | ||
98 | extern struct omap_hwmod am33xx_dcan1_hwmod; | ||
99 | extern struct omap_hwmod am33xx_elm_hwmod; | ||
100 | extern struct omap_hwmod am33xx_epwmss0_hwmod; | ||
101 | extern struct omap_hwmod am33xx_ecap0_hwmod; | ||
102 | extern struct omap_hwmod am33xx_eqep0_hwmod; | ||
103 | extern struct omap_hwmod am33xx_ehrpwm0_hwmod; | ||
104 | extern struct omap_hwmod am33xx_epwmss1_hwmod; | ||
105 | extern struct omap_hwmod am33xx_ecap1_hwmod; | ||
106 | extern struct omap_hwmod am33xx_eqep1_hwmod; | ||
107 | extern struct omap_hwmod am33xx_ehrpwm1_hwmod; | ||
108 | extern struct omap_hwmod am33xx_epwmss2_hwmod; | ||
109 | extern struct omap_hwmod am33xx_ecap2_hwmod; | ||
110 | extern struct omap_hwmod am33xx_eqep2_hwmod; | ||
111 | extern struct omap_hwmod am33xx_ehrpwm2_hwmod; | ||
112 | extern struct omap_hwmod am33xx_gpio1_hwmod; | ||
113 | extern struct omap_hwmod am33xx_gpio2_hwmod; | ||
114 | extern struct omap_hwmod am33xx_gpio3_hwmod; | ||
115 | extern struct omap_hwmod am33xx_gpmc_hwmod; | ||
116 | extern struct omap_hwmod am33xx_i2c1_hwmod; | ||
117 | extern struct omap_hwmod am33xx_i2c2_hwmod; | ||
118 | extern struct omap_hwmod am33xx_i2c3_hwmod; | ||
119 | extern struct omap_hwmod am33xx_mailbox_hwmod; | ||
120 | extern struct omap_hwmod am33xx_mcasp0_hwmod; | ||
121 | extern struct omap_hwmod am33xx_mcasp1_hwmod; | ||
122 | extern struct omap_hwmod am33xx_mmc0_hwmod; | ||
123 | extern struct omap_hwmod am33xx_mmc1_hwmod; | ||
124 | extern struct omap_hwmod am33xx_mmc2_hwmod; | ||
125 | extern struct omap_hwmod am33xx_rtc_hwmod; | ||
126 | extern struct omap_hwmod am33xx_spi0_hwmod; | ||
127 | extern struct omap_hwmod am33xx_spi1_hwmod; | ||
128 | extern struct omap_hwmod am33xx_spinlock_hwmod; | ||
129 | extern struct omap_hwmod am33xx_timer1_hwmod; | ||
130 | extern struct omap_hwmod am33xx_timer2_hwmod; | ||
131 | extern struct omap_hwmod am33xx_timer3_hwmod; | ||
132 | extern struct omap_hwmod am33xx_timer4_hwmod; | ||
133 | extern struct omap_hwmod am33xx_timer5_hwmod; | ||
134 | extern struct omap_hwmod am33xx_timer6_hwmod; | ||
135 | extern struct omap_hwmod am33xx_timer7_hwmod; | ||
136 | extern struct omap_hwmod am33xx_tpcc_hwmod; | ||
137 | extern struct omap_hwmod am33xx_tptc0_hwmod; | ||
138 | extern struct omap_hwmod am33xx_tptc1_hwmod; | ||
139 | extern struct omap_hwmod am33xx_tptc2_hwmod; | ||
140 | extern struct omap_hwmod am33xx_uart1_hwmod; | ||
141 | extern struct omap_hwmod am33xx_uart2_hwmod; | ||
142 | extern struct omap_hwmod am33xx_uart3_hwmod; | ||
143 | extern struct omap_hwmod am33xx_uart4_hwmod; | ||
144 | extern struct omap_hwmod am33xx_uart5_hwmod; | ||
145 | extern struct omap_hwmod am33xx_uart6_hwmod; | ||
146 | extern struct omap_hwmod am33xx_wd_timer1_hwmod; | ||
147 | |||
148 | extern struct omap_hwmod_class am33xx_l4_hwmod_class; | ||
149 | extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class; | ||
150 | extern struct omap_hwmod_class am33xx_control_hwmod_class; | ||
151 | extern struct omap_hwmod_class am33xx_gpio_hwmod_class; | ||
152 | extern struct omap_hwmod_class am33xx_timer_hwmod_class; | ||
153 | extern struct omap_hwmod_class am33xx_epwmss_hwmod_class; | ||
154 | extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; | ||
155 | extern struct omap_hwmod_class am33xx_spi_hwmod_class; | ||
156 | |||
157 | extern struct omap_gpio_dev_attr gpio_dev_attr; | ||
158 | extern struct omap2_mcspi_dev_attr mcspi_attrib; | ||
159 | |||
160 | void omap_hwmod_am33xx_reg(void); | ||
161 | void omap_hwmod_am43xx_reg(void); | ||
162 | |||
163 | #endif | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c new file mode 100644 index 000000000000..e2db378b849e --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c | |||
@@ -0,0 +1,643 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
4 | * | ||
5 | * Interconnects common for AM335x and AM43x | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License as | ||
9 | * published by the Free Software Foundation version 2. | ||
10 | * | ||
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
12 | * kind, whether express or implied; without even the implied warranty | ||
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/sizes.h> | ||
18 | #include "omap_hwmod.h" | ||
19 | #include "omap_hwmod_33xx_43xx_common_data.h" | ||
20 | |||
21 | /* mpu -> l3 main */ | ||
22 | struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | ||
23 | .master = &am33xx_mpu_hwmod, | ||
24 | .slave = &am33xx_l3_main_hwmod, | ||
25 | .clk = "dpll_mpu_m2_ck", | ||
26 | .user = OCP_USER_MPU, | ||
27 | }; | ||
28 | |||
29 | /* l3 main -> l3 s */ | ||
30 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | ||
31 | .master = &am33xx_l3_main_hwmod, | ||
32 | .slave = &am33xx_l3_s_hwmod, | ||
33 | .clk = "l3s_gclk", | ||
34 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
35 | }; | ||
36 | |||
37 | /* l3 s -> l4 per/ls */ | ||
38 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | ||
39 | .master = &am33xx_l3_s_hwmod, | ||
40 | .slave = &am33xx_l4_ls_hwmod, | ||
41 | .clk = "l3s_gclk", | ||
42 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
43 | }; | ||
44 | |||
45 | /* l3 s -> l4 wkup */ | ||
46 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | ||
47 | .master = &am33xx_l3_s_hwmod, | ||
48 | .slave = &am33xx_l4_wkup_hwmod, | ||
49 | .clk = "l3s_gclk", | ||
50 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
51 | }; | ||
52 | |||
53 | /* l3 main -> l3 instr */ | ||
54 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | ||
55 | .master = &am33xx_l3_main_hwmod, | ||
56 | .slave = &am33xx_l3_instr_hwmod, | ||
57 | .clk = "l3s_gclk", | ||
58 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
59 | }; | ||
60 | |||
61 | /* mpu -> prcm */ | ||
62 | struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | ||
63 | .master = &am33xx_mpu_hwmod, | ||
64 | .slave = &am33xx_prcm_hwmod, | ||
65 | .clk = "dpll_mpu_m2_ck", | ||
66 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
67 | }; | ||
68 | |||
69 | /* l3 s -> l3 main*/ | ||
70 | struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | ||
71 | .master = &am33xx_l3_s_hwmod, | ||
72 | .slave = &am33xx_l3_main_hwmod, | ||
73 | .clk = "l3s_gclk", | ||
74 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
75 | }; | ||
76 | |||
77 | /* pru-icss -> l3 main */ | ||
78 | struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | ||
79 | .master = &am33xx_pruss_hwmod, | ||
80 | .slave = &am33xx_l3_main_hwmod, | ||
81 | .clk = "l3_gclk", | ||
82 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
83 | }; | ||
84 | |||
85 | /* gfx -> l3 main */ | ||
86 | struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | ||
87 | .master = &am33xx_gfx_hwmod, | ||
88 | .slave = &am33xx_l3_main_hwmod, | ||
89 | .clk = "dpll_core_m4_ck", | ||
90 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
91 | }; | ||
92 | |||
93 | /* l3 main -> gfx */ | ||
94 | struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { | ||
95 | .master = &am33xx_l3_main_hwmod, | ||
96 | .slave = &am33xx_gfx_hwmod, | ||
97 | .clk = "dpll_core_m4_ck", | ||
98 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
99 | }; | ||
100 | |||
101 | /* l4 wkup -> rtc */ | ||
102 | struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { | ||
103 | .master = &am33xx_l4_wkup_hwmod, | ||
104 | .slave = &am33xx_rtc_hwmod, | ||
105 | .clk = "clkdiv32k_ick", | ||
106 | .user = OCP_USER_MPU, | ||
107 | }; | ||
108 | |||
109 | /* l4 per/ls -> DCAN0 */ | ||
110 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { | ||
111 | .master = &am33xx_l4_ls_hwmod, | ||
112 | .slave = &am33xx_dcan0_hwmod, | ||
113 | .clk = "l4ls_gclk", | ||
114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
115 | }; | ||
116 | |||
117 | /* l4 per/ls -> DCAN1 */ | ||
118 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { | ||
119 | .master = &am33xx_l4_ls_hwmod, | ||
120 | .slave = &am33xx_dcan1_hwmod, | ||
121 | .clk = "l4ls_gclk", | ||
122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
123 | }; | ||
124 | |||
125 | /* l4 per/ls -> GPIO2 */ | ||
126 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { | ||
127 | .master = &am33xx_l4_ls_hwmod, | ||
128 | .slave = &am33xx_gpio1_hwmod, | ||
129 | .clk = "l4ls_gclk", | ||
130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
131 | }; | ||
132 | |||
133 | /* l4 per/ls -> gpio3 */ | ||
134 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { | ||
135 | .master = &am33xx_l4_ls_hwmod, | ||
136 | .slave = &am33xx_gpio2_hwmod, | ||
137 | .clk = "l4ls_gclk", | ||
138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
139 | }; | ||
140 | |||
141 | /* l4 per/ls -> gpio4 */ | ||
142 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { | ||
143 | .master = &am33xx_l4_ls_hwmod, | ||
144 | .slave = &am33xx_gpio3_hwmod, | ||
145 | .clk = "l4ls_gclk", | ||
146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
147 | }; | ||
148 | |||
149 | struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { | ||
150 | .master = &am33xx_cpgmac0_hwmod, | ||
151 | .slave = &am33xx_mdio_hwmod, | ||
152 | .user = OCP_USER_MPU, | ||
153 | }; | ||
154 | |||
155 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { | ||
156 | { | ||
157 | .pa_start = 0x48080000, | ||
158 | .pa_end = 0x48080000 + SZ_8K - 1, | ||
159 | .flags = ADDR_TYPE_RT | ||
160 | }, | ||
161 | { } | ||
162 | }; | ||
163 | |||
164 | struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { | ||
165 | .master = &am33xx_l4_ls_hwmod, | ||
166 | .slave = &am33xx_elm_hwmod, | ||
167 | .clk = "l4ls_gclk", | ||
168 | .addr = am33xx_elm_addr_space, | ||
169 | .user = OCP_USER_MPU, | ||
170 | }; | ||
171 | |||
172 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { | ||
173 | { | ||
174 | .pa_start = 0x48300000, | ||
175 | .pa_end = 0x48300000 + SZ_16 - 1, | ||
176 | .flags = ADDR_TYPE_RT | ||
177 | }, | ||
178 | { } | ||
179 | }; | ||
180 | |||
181 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { | ||
182 | .master = &am33xx_l4_ls_hwmod, | ||
183 | .slave = &am33xx_epwmss0_hwmod, | ||
184 | .clk = "l4ls_gclk", | ||
185 | .addr = am33xx_epwmss0_addr_space, | ||
186 | .user = OCP_USER_MPU, | ||
187 | }; | ||
188 | |||
189 | struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { | ||
190 | .master = &am33xx_epwmss0_hwmod, | ||
191 | .slave = &am33xx_ecap0_hwmod, | ||
192 | .clk = "l4ls_gclk", | ||
193 | .user = OCP_USER_MPU, | ||
194 | }; | ||
195 | |||
196 | struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { | ||
197 | .master = &am33xx_epwmss0_hwmod, | ||
198 | .slave = &am33xx_eqep0_hwmod, | ||
199 | .clk = "l4ls_gclk", | ||
200 | .user = OCP_USER_MPU, | ||
201 | }; | ||
202 | |||
203 | struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { | ||
204 | .master = &am33xx_epwmss0_hwmod, | ||
205 | .slave = &am33xx_ehrpwm0_hwmod, | ||
206 | .clk = "l4ls_gclk", | ||
207 | .user = OCP_USER_MPU, | ||
208 | }; | ||
209 | |||
210 | |||
211 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { | ||
212 | { | ||
213 | .pa_start = 0x48302000, | ||
214 | .pa_end = 0x48302000 + SZ_16 - 1, | ||
215 | .flags = ADDR_TYPE_RT | ||
216 | }, | ||
217 | { } | ||
218 | }; | ||
219 | |||
220 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { | ||
221 | .master = &am33xx_l4_ls_hwmod, | ||
222 | .slave = &am33xx_epwmss1_hwmod, | ||
223 | .clk = "l4ls_gclk", | ||
224 | .addr = am33xx_epwmss1_addr_space, | ||
225 | .user = OCP_USER_MPU, | ||
226 | }; | ||
227 | |||
228 | struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { | ||
229 | .master = &am33xx_epwmss1_hwmod, | ||
230 | .slave = &am33xx_ecap1_hwmod, | ||
231 | .clk = "l4ls_gclk", | ||
232 | .user = OCP_USER_MPU, | ||
233 | }; | ||
234 | |||
235 | struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { | ||
236 | .master = &am33xx_epwmss1_hwmod, | ||
237 | .slave = &am33xx_eqep1_hwmod, | ||
238 | .clk = "l4ls_gclk", | ||
239 | .user = OCP_USER_MPU, | ||
240 | }; | ||
241 | |||
242 | struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { | ||
243 | .master = &am33xx_epwmss1_hwmod, | ||
244 | .slave = &am33xx_ehrpwm1_hwmod, | ||
245 | .clk = "l4ls_gclk", | ||
246 | .user = OCP_USER_MPU, | ||
247 | }; | ||
248 | |||
249 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { | ||
250 | { | ||
251 | .pa_start = 0x48304000, | ||
252 | .pa_end = 0x48304000 + SZ_16 - 1, | ||
253 | .flags = ADDR_TYPE_RT | ||
254 | }, | ||
255 | { } | ||
256 | }; | ||
257 | |||
258 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { | ||
259 | .master = &am33xx_l4_ls_hwmod, | ||
260 | .slave = &am33xx_epwmss2_hwmod, | ||
261 | .clk = "l4ls_gclk", | ||
262 | .addr = am33xx_epwmss2_addr_space, | ||
263 | .user = OCP_USER_MPU, | ||
264 | }; | ||
265 | |||
266 | struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { | ||
267 | .master = &am33xx_epwmss2_hwmod, | ||
268 | .slave = &am33xx_ecap2_hwmod, | ||
269 | .clk = "l4ls_gclk", | ||
270 | .user = OCP_USER_MPU, | ||
271 | }; | ||
272 | |||
273 | struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { | ||
274 | .master = &am33xx_epwmss2_hwmod, | ||
275 | .slave = &am33xx_eqep2_hwmod, | ||
276 | .clk = "l4ls_gclk", | ||
277 | .user = OCP_USER_MPU, | ||
278 | }; | ||
279 | |||
280 | struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { | ||
281 | .master = &am33xx_epwmss2_hwmod, | ||
282 | .slave = &am33xx_ehrpwm2_hwmod, | ||
283 | .clk = "l4ls_gclk", | ||
284 | .user = OCP_USER_MPU, | ||
285 | }; | ||
286 | |||
287 | /* l3s cfg -> gpmc */ | ||
288 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { | ||
289 | { | ||
290 | .pa_start = 0x50000000, | ||
291 | .pa_end = 0x50000000 + SZ_8K - 1, | ||
292 | .flags = ADDR_TYPE_RT, | ||
293 | }, | ||
294 | { } | ||
295 | }; | ||
296 | |||
297 | struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | ||
298 | .master = &am33xx_l3_s_hwmod, | ||
299 | .slave = &am33xx_gpmc_hwmod, | ||
300 | .clk = "l3s_gclk", | ||
301 | .addr = am33xx_gpmc_addr_space, | ||
302 | .user = OCP_USER_MPU, | ||
303 | }; | ||
304 | |||
305 | /* i2c2 */ | ||
306 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { | ||
307 | .master = &am33xx_l4_ls_hwmod, | ||
308 | .slave = &am33xx_i2c2_hwmod, | ||
309 | .clk = "l4ls_gclk", | ||
310 | .user = OCP_USER_MPU, | ||
311 | }; | ||
312 | |||
313 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { | ||
314 | .master = &am33xx_l4_ls_hwmod, | ||
315 | .slave = &am33xx_i2c3_hwmod, | ||
316 | .clk = "l4ls_gclk", | ||
317 | .user = OCP_USER_MPU, | ||
318 | }; | ||
319 | |||
320 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { | ||
321 | { | ||
322 | .pa_start = 0x480C8000, | ||
323 | .pa_end = 0x480C8000 + (SZ_4K - 1), | ||
324 | .flags = ADDR_TYPE_RT | ||
325 | }, | ||
326 | { } | ||
327 | }; | ||
328 | |||
329 | /* l4 ls -> mailbox */ | ||
330 | struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | ||
331 | .master = &am33xx_l4_ls_hwmod, | ||
332 | .slave = &am33xx_mailbox_hwmod, | ||
333 | .clk = "l4ls_gclk", | ||
334 | .addr = am33xx_mailbox_addrs, | ||
335 | .user = OCP_USER_MPU, | ||
336 | }; | ||
337 | |||
338 | /* l4 ls -> spinlock */ | ||
339 | struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { | ||
340 | .master = &am33xx_l4_ls_hwmod, | ||
341 | .slave = &am33xx_spinlock_hwmod, | ||
342 | .clk = "l4ls_gclk", | ||
343 | .user = OCP_USER_MPU, | ||
344 | }; | ||
345 | |||
346 | /* l4 ls -> mcasp0 */ | ||
347 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | ||
348 | { | ||
349 | .pa_start = 0x48038000, | ||
350 | .pa_end = 0x48038000 + SZ_8K - 1, | ||
351 | .flags = ADDR_TYPE_RT | ||
352 | }, | ||
353 | { } | ||
354 | }; | ||
355 | |||
356 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | ||
357 | .master = &am33xx_l4_ls_hwmod, | ||
358 | .slave = &am33xx_mcasp0_hwmod, | ||
359 | .clk = "l4ls_gclk", | ||
360 | .addr = am33xx_mcasp0_addr_space, | ||
361 | .user = OCP_USER_MPU, | ||
362 | }; | ||
363 | |||
364 | /* l4 ls -> mcasp1 */ | ||
365 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | ||
366 | { | ||
367 | .pa_start = 0x4803C000, | ||
368 | .pa_end = 0x4803C000 + SZ_8K - 1, | ||
369 | .flags = ADDR_TYPE_RT | ||
370 | }, | ||
371 | { } | ||
372 | }; | ||
373 | |||
374 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | ||
375 | .master = &am33xx_l4_ls_hwmod, | ||
376 | .slave = &am33xx_mcasp1_hwmod, | ||
377 | .clk = "l4ls_gclk", | ||
378 | .addr = am33xx_mcasp1_addr_space, | ||
379 | .user = OCP_USER_MPU, | ||
380 | }; | ||
381 | |||
382 | /* l4 ls -> mmc0 */ | ||
383 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | ||
384 | { | ||
385 | .pa_start = 0x48060100, | ||
386 | .pa_end = 0x48060100 + SZ_4K - 1, | ||
387 | .flags = ADDR_TYPE_RT, | ||
388 | }, | ||
389 | { } | ||
390 | }; | ||
391 | |||
392 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | ||
393 | .master = &am33xx_l4_ls_hwmod, | ||
394 | .slave = &am33xx_mmc0_hwmod, | ||
395 | .clk = "l4ls_gclk", | ||
396 | .addr = am33xx_mmc0_addr_space, | ||
397 | .user = OCP_USER_MPU, | ||
398 | }; | ||
399 | |||
400 | /* l4 ls -> mmc1 */ | ||
401 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | ||
402 | { | ||
403 | .pa_start = 0x481d8100, | ||
404 | .pa_end = 0x481d8100 + SZ_4K - 1, | ||
405 | .flags = ADDR_TYPE_RT, | ||
406 | }, | ||
407 | { } | ||
408 | }; | ||
409 | |||
410 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | ||
411 | .master = &am33xx_l4_ls_hwmod, | ||
412 | .slave = &am33xx_mmc1_hwmod, | ||
413 | .clk = "l4ls_gclk", | ||
414 | .addr = am33xx_mmc1_addr_space, | ||
415 | .user = OCP_USER_MPU, | ||
416 | }; | ||
417 | |||
418 | /* l3 s -> mmc2 */ | ||
419 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | ||
420 | { | ||
421 | .pa_start = 0x47810100, | ||
422 | .pa_end = 0x47810100 + SZ_64K - 1, | ||
423 | .flags = ADDR_TYPE_RT, | ||
424 | }, | ||
425 | { } | ||
426 | }; | ||
427 | |||
428 | struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | ||
429 | .master = &am33xx_l3_s_hwmod, | ||
430 | .slave = &am33xx_mmc2_hwmod, | ||
431 | .clk = "l3s_gclk", | ||
432 | .addr = am33xx_mmc2_addr_space, | ||
433 | .user = OCP_USER_MPU, | ||
434 | }; | ||
435 | |||
436 | /* l4 ls -> mcspi0 */ | ||
437 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { | ||
438 | .master = &am33xx_l4_ls_hwmod, | ||
439 | .slave = &am33xx_spi0_hwmod, | ||
440 | .clk = "l4ls_gclk", | ||
441 | .user = OCP_USER_MPU, | ||
442 | }; | ||
443 | |||
444 | /* l4 ls -> mcspi1 */ | ||
445 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { | ||
446 | .master = &am33xx_l4_ls_hwmod, | ||
447 | .slave = &am33xx_spi1_hwmod, | ||
448 | .clk = "l4ls_gclk", | ||
449 | .user = OCP_USER_MPU, | ||
450 | }; | ||
451 | |||
452 | /* l4 per -> timer2 */ | ||
453 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { | ||
454 | .master = &am33xx_l4_ls_hwmod, | ||
455 | .slave = &am33xx_timer2_hwmod, | ||
456 | .clk = "l4ls_gclk", | ||
457 | .user = OCP_USER_MPU, | ||
458 | }; | ||
459 | |||
460 | /* l4 per -> timer3 */ | ||
461 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { | ||
462 | .master = &am33xx_l4_ls_hwmod, | ||
463 | .slave = &am33xx_timer3_hwmod, | ||
464 | .clk = "l4ls_gclk", | ||
465 | .user = OCP_USER_MPU, | ||
466 | }; | ||
467 | |||
468 | /* l4 per -> timer4 */ | ||
469 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { | ||
470 | .master = &am33xx_l4_ls_hwmod, | ||
471 | .slave = &am33xx_timer4_hwmod, | ||
472 | .clk = "l4ls_gclk", | ||
473 | .user = OCP_USER_MPU, | ||
474 | }; | ||
475 | |||
476 | /* l4 per -> timer5 */ | ||
477 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { | ||
478 | .master = &am33xx_l4_ls_hwmod, | ||
479 | .slave = &am33xx_timer5_hwmod, | ||
480 | .clk = "l4ls_gclk", | ||
481 | .user = OCP_USER_MPU, | ||
482 | }; | ||
483 | |||
484 | /* l4 per -> timer6 */ | ||
485 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { | ||
486 | .master = &am33xx_l4_ls_hwmod, | ||
487 | .slave = &am33xx_timer6_hwmod, | ||
488 | .clk = "l4ls_gclk", | ||
489 | .user = OCP_USER_MPU, | ||
490 | }; | ||
491 | |||
492 | /* l4 per -> timer7 */ | ||
493 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { | ||
494 | .master = &am33xx_l4_ls_hwmod, | ||
495 | .slave = &am33xx_timer7_hwmod, | ||
496 | .clk = "l4ls_gclk", | ||
497 | .user = OCP_USER_MPU, | ||
498 | }; | ||
499 | |||
500 | /* l3 main -> tpcc */ | ||
501 | struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { | ||
502 | .master = &am33xx_l3_main_hwmod, | ||
503 | .slave = &am33xx_tpcc_hwmod, | ||
504 | .clk = "l3_gclk", | ||
505 | .user = OCP_USER_MPU, | ||
506 | }; | ||
507 | |||
508 | /* l3 main -> tpcc0 */ | ||
509 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | ||
510 | { | ||
511 | .pa_start = 0x49800000, | ||
512 | .pa_end = 0x49800000 + SZ_8K - 1, | ||
513 | .flags = ADDR_TYPE_RT, | ||
514 | }, | ||
515 | { } | ||
516 | }; | ||
517 | |||
518 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | ||
519 | .master = &am33xx_l3_main_hwmod, | ||
520 | .slave = &am33xx_tptc0_hwmod, | ||
521 | .clk = "l3_gclk", | ||
522 | .addr = am33xx_tptc0_addr_space, | ||
523 | .user = OCP_USER_MPU, | ||
524 | }; | ||
525 | |||
526 | /* l3 main -> tpcc1 */ | ||
527 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | ||
528 | { | ||
529 | .pa_start = 0x49900000, | ||
530 | .pa_end = 0x49900000 + SZ_8K - 1, | ||
531 | .flags = ADDR_TYPE_RT, | ||
532 | }, | ||
533 | { } | ||
534 | }; | ||
535 | |||
536 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | ||
537 | .master = &am33xx_l3_main_hwmod, | ||
538 | .slave = &am33xx_tptc1_hwmod, | ||
539 | .clk = "l3_gclk", | ||
540 | .addr = am33xx_tptc1_addr_space, | ||
541 | .user = OCP_USER_MPU, | ||
542 | }; | ||
543 | |||
544 | /* l3 main -> tpcc2 */ | ||
545 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | ||
546 | { | ||
547 | .pa_start = 0x49a00000, | ||
548 | .pa_end = 0x49a00000 + SZ_8K - 1, | ||
549 | .flags = ADDR_TYPE_RT, | ||
550 | }, | ||
551 | { } | ||
552 | }; | ||
553 | |||
554 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | ||
555 | .master = &am33xx_l3_main_hwmod, | ||
556 | .slave = &am33xx_tptc2_hwmod, | ||
557 | .clk = "l3_gclk", | ||
558 | .addr = am33xx_tptc2_addr_space, | ||
559 | .user = OCP_USER_MPU, | ||
560 | }; | ||
561 | |||
562 | /* l4 ls -> uart2 */ | ||
563 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { | ||
564 | .master = &am33xx_l4_ls_hwmod, | ||
565 | .slave = &am33xx_uart2_hwmod, | ||
566 | .clk = "l4ls_gclk", | ||
567 | .user = OCP_USER_MPU, | ||
568 | }; | ||
569 | |||
570 | /* l4 ls -> uart3 */ | ||
571 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { | ||
572 | .master = &am33xx_l4_ls_hwmod, | ||
573 | .slave = &am33xx_uart3_hwmod, | ||
574 | .clk = "l4ls_gclk", | ||
575 | .user = OCP_USER_MPU, | ||
576 | }; | ||
577 | |||
578 | /* l4 ls -> uart4 */ | ||
579 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { | ||
580 | .master = &am33xx_l4_ls_hwmod, | ||
581 | .slave = &am33xx_uart4_hwmod, | ||
582 | .clk = "l4ls_gclk", | ||
583 | .user = OCP_USER_MPU, | ||
584 | }; | ||
585 | |||
586 | /* l4 ls -> uart5 */ | ||
587 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { | ||
588 | .master = &am33xx_l4_ls_hwmod, | ||
589 | .slave = &am33xx_uart5_hwmod, | ||
590 | .clk = "l4ls_gclk", | ||
591 | .user = OCP_USER_MPU, | ||
592 | }; | ||
593 | |||
594 | /* l4 ls -> uart6 */ | ||
595 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { | ||
596 | .master = &am33xx_l4_ls_hwmod, | ||
597 | .slave = &am33xx_uart6_hwmod, | ||
598 | .clk = "l4ls_gclk", | ||
599 | .user = OCP_USER_MPU, | ||
600 | }; | ||
601 | |||
602 | /* l3 main -> ocmc */ | ||
603 | struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | ||
604 | .master = &am33xx_l3_main_hwmod, | ||
605 | .slave = &am33xx_ocmcram_hwmod, | ||
606 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
607 | }; | ||
608 | |||
609 | /* l3 main -> sha0 HIB2 */ | ||
610 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | ||
611 | { | ||
612 | .pa_start = 0x53100000, | ||
613 | .pa_end = 0x53100000 + SZ_512 - 1, | ||
614 | .flags = ADDR_TYPE_RT | ||
615 | }, | ||
616 | { } | ||
617 | }; | ||
618 | |||
619 | struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | ||
620 | .master = &am33xx_l3_main_hwmod, | ||
621 | .slave = &am33xx_sha0_hwmod, | ||
622 | .clk = "sha0_fck", | ||
623 | .addr = am33xx_sha0_addrs, | ||
624 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
625 | }; | ||
626 | |||
627 | /* l3 main -> AES0 HIB2 */ | ||
628 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | ||
629 | { | ||
630 | .pa_start = 0x53500000, | ||
631 | .pa_end = 0x53500000 + SZ_1M - 1, | ||
632 | .flags = ADDR_TYPE_RT | ||
633 | }, | ||
634 | { } | ||
635 | }; | ||
636 | |||
637 | struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | ||
638 | .master = &am33xx_l3_main_hwmod, | ||
639 | .slave = &am33xx_aes0_hwmod, | ||
640 | .clk = "aes0_fck", | ||
641 | .addr = am33xx_aes0_addrs, | ||
642 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
643 | }; | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c new file mode 100644 index 000000000000..0f178623e7da --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | |||
@@ -0,0 +1,1469 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
4 | * | ||
5 | * Hwmod common for AM335x and AM43x | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License as | ||
9 | * published by the Free Software Foundation version 2. | ||
10 | * | ||
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
12 | * kind, whether express or implied; without even the implied warranty | ||
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/platform_data/gpio-omap.h> | ||
18 | #include <linux/platform_data/spi-omap2-mcspi.h> | ||
19 | #include "omap_hwmod.h" | ||
20 | #include "i2c.h" | ||
21 | #include "mmc.h" | ||
22 | #include "wd_timer.h" | ||
23 | #include "cm33xx.h" | ||
24 | #include "prm33xx.h" | ||
25 | #include "omap_hwmod_33xx_43xx_common_data.h" | ||
26 | #include "prcm43xx.h" | ||
27 | |||
28 | #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) | ||
29 | #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) | ||
30 | #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst)) | ||
31 | |||
32 | /* | ||
33 | * 'l3' class | ||
34 | * instance(s): l3_main, l3_s, l3_instr | ||
35 | */ | ||
36 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { | ||
37 | .name = "l3", | ||
38 | }; | ||
39 | |||
40 | struct omap_hwmod am33xx_l3_main_hwmod = { | ||
41 | .name = "l3_main", | ||
42 | .class = &am33xx_l3_hwmod_class, | ||
43 | .clkdm_name = "l3_clkdm", | ||
44 | .flags = HWMOD_INIT_NO_IDLE, | ||
45 | .main_clk = "l3_gclk", | ||
46 | .prcm = { | ||
47 | .omap4 = { | ||
48 | .modulemode = MODULEMODE_SWCTRL, | ||
49 | }, | ||
50 | }, | ||
51 | }; | ||
52 | |||
53 | /* l3_s */ | ||
54 | struct omap_hwmod am33xx_l3_s_hwmod = { | ||
55 | .name = "l3_s", | ||
56 | .class = &am33xx_l3_hwmod_class, | ||
57 | .clkdm_name = "l3s_clkdm", | ||
58 | }; | ||
59 | |||
60 | /* l3_instr */ | ||
61 | struct omap_hwmod am33xx_l3_instr_hwmod = { | ||
62 | .name = "l3_instr", | ||
63 | .class = &am33xx_l3_hwmod_class, | ||
64 | .clkdm_name = "l3_clkdm", | ||
65 | .flags = HWMOD_INIT_NO_IDLE, | ||
66 | .main_clk = "l3_gclk", | ||
67 | .prcm = { | ||
68 | .omap4 = { | ||
69 | .modulemode = MODULEMODE_SWCTRL, | ||
70 | }, | ||
71 | }, | ||
72 | }; | ||
73 | |||
74 | /* | ||
75 | * 'l4' class | ||
76 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw | ||
77 | */ | ||
78 | struct omap_hwmod_class am33xx_l4_hwmod_class = { | ||
79 | .name = "l4", | ||
80 | }; | ||
81 | |||
82 | /* l4_ls */ | ||
83 | struct omap_hwmod am33xx_l4_ls_hwmod = { | ||
84 | .name = "l4_ls", | ||
85 | .class = &am33xx_l4_hwmod_class, | ||
86 | .clkdm_name = "l4ls_clkdm", | ||
87 | .flags = HWMOD_INIT_NO_IDLE, | ||
88 | .main_clk = "l4ls_gclk", | ||
89 | .prcm = { | ||
90 | .omap4 = { | ||
91 | .modulemode = MODULEMODE_SWCTRL, | ||
92 | }, | ||
93 | }, | ||
94 | }; | ||
95 | |||
96 | /* l4_wkup */ | ||
97 | struct omap_hwmod am33xx_l4_wkup_hwmod = { | ||
98 | .name = "l4_wkup", | ||
99 | .class = &am33xx_l4_hwmod_class, | ||
100 | .clkdm_name = "l4_wkup_clkdm", | ||
101 | .flags = HWMOD_INIT_NO_IDLE, | ||
102 | .prcm = { | ||
103 | .omap4 = { | ||
104 | .modulemode = MODULEMODE_SWCTRL, | ||
105 | }, | ||
106 | }, | ||
107 | }; | ||
108 | |||
109 | /* | ||
110 | * 'mpu' class | ||
111 | */ | ||
112 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | ||
113 | .name = "mpu", | ||
114 | }; | ||
115 | |||
116 | struct omap_hwmod am33xx_mpu_hwmod = { | ||
117 | .name = "mpu", | ||
118 | .class = &am33xx_mpu_hwmod_class, | ||
119 | .clkdm_name = "mpu_clkdm", | ||
120 | .flags = HWMOD_INIT_NO_IDLE, | ||
121 | .main_clk = "dpll_mpu_m2_ck", | ||
122 | .prcm = { | ||
123 | .omap4 = { | ||
124 | .modulemode = MODULEMODE_SWCTRL, | ||
125 | }, | ||
126 | }, | ||
127 | }; | ||
128 | |||
129 | /* | ||
130 | * 'wakeup m3' class | ||
131 | * Wakeup controller sub-system under wakeup domain | ||
132 | */ | ||
133 | struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { | ||
134 | .name = "wkup_m3", | ||
135 | }; | ||
136 | |||
137 | /* | ||
138 | * 'pru-icss' class | ||
139 | * Programmable Real-Time Unit and Industrial Communication Subsystem | ||
140 | */ | ||
141 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { | ||
142 | .name = "pruss", | ||
143 | }; | ||
144 | |||
145 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | ||
146 | { .name = "pruss", .rst_shift = 1 }, | ||
147 | }; | ||
148 | |||
149 | /* pru-icss */ | ||
150 | /* Pseudo hwmod for reset control purpose only */ | ||
151 | struct omap_hwmod am33xx_pruss_hwmod = { | ||
152 | .name = "pruss", | ||
153 | .class = &am33xx_pruss_hwmod_class, | ||
154 | .clkdm_name = "pruss_ocp_clkdm", | ||
155 | .main_clk = "pruss_ocp_gclk", | ||
156 | .prcm = { | ||
157 | .omap4 = { | ||
158 | .modulemode = MODULEMODE_SWCTRL, | ||
159 | }, | ||
160 | }, | ||
161 | .rst_lines = am33xx_pruss_resets, | ||
162 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), | ||
163 | }; | ||
164 | |||
165 | /* gfx */ | ||
166 | /* Pseudo hwmod for reset control purpose only */ | ||
167 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { | ||
168 | .name = "gfx", | ||
169 | }; | ||
170 | |||
171 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | ||
172 | { .name = "gfx", .rst_shift = 0, .st_shift = 0}, | ||
173 | }; | ||
174 | |||
175 | struct omap_hwmod am33xx_gfx_hwmod = { | ||
176 | .name = "gfx", | ||
177 | .class = &am33xx_gfx_hwmod_class, | ||
178 | .clkdm_name = "gfx_l3_clkdm", | ||
179 | .main_clk = "gfx_fck_div_ck", | ||
180 | .prcm = { | ||
181 | .omap4 = { | ||
182 | .modulemode = MODULEMODE_SWCTRL, | ||
183 | }, | ||
184 | }, | ||
185 | .rst_lines = am33xx_gfx_resets, | ||
186 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), | ||
187 | }; | ||
188 | |||
189 | /* | ||
190 | * 'prcm' class | ||
191 | * power and reset manager (whole prcm infrastructure) | ||
192 | */ | ||
193 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { | ||
194 | .name = "prcm", | ||
195 | }; | ||
196 | |||
197 | /* prcm */ | ||
198 | struct omap_hwmod am33xx_prcm_hwmod = { | ||
199 | .name = "prcm", | ||
200 | .class = &am33xx_prcm_hwmod_class, | ||
201 | .clkdm_name = "l4_wkup_clkdm", | ||
202 | }; | ||
203 | |||
204 | /* | ||
205 | * 'aes0' class | ||
206 | */ | ||
207 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { | ||
208 | .rev_offs = 0x80, | ||
209 | .sysc_offs = 0x84, | ||
210 | .syss_offs = 0x88, | ||
211 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
212 | }; | ||
213 | |||
214 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | ||
215 | .name = "aes0", | ||
216 | .sysc = &am33xx_aes0_sysc, | ||
217 | }; | ||
218 | |||
219 | struct omap_hwmod am33xx_aes0_hwmod = { | ||
220 | .name = "aes", | ||
221 | .class = &am33xx_aes0_hwmod_class, | ||
222 | .clkdm_name = "l3_clkdm", | ||
223 | .main_clk = "aes0_fck", | ||
224 | .prcm = { | ||
225 | .omap4 = { | ||
226 | .modulemode = MODULEMODE_SWCTRL, | ||
227 | }, | ||
228 | }, | ||
229 | }; | ||
230 | |||
231 | /* sha0 HIB2 (the 'P' (public) device) */ | ||
232 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { | ||
233 | .rev_offs = 0x100, | ||
234 | .sysc_offs = 0x110, | ||
235 | .syss_offs = 0x114, | ||
236 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
237 | }; | ||
238 | |||
239 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { | ||
240 | .name = "sha0", | ||
241 | .sysc = &am33xx_sha0_sysc, | ||
242 | }; | ||
243 | |||
244 | struct omap_hwmod am33xx_sha0_hwmod = { | ||
245 | .name = "sham", | ||
246 | .class = &am33xx_sha0_hwmod_class, | ||
247 | .clkdm_name = "l3_clkdm", | ||
248 | .main_clk = "l3_gclk", | ||
249 | .prcm = { | ||
250 | .omap4 = { | ||
251 | .modulemode = MODULEMODE_SWCTRL, | ||
252 | }, | ||
253 | }, | ||
254 | }; | ||
255 | |||
256 | /* ocmcram */ | ||
257 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | ||
258 | .name = "ocmcram", | ||
259 | }; | ||
260 | |||
261 | struct omap_hwmod am33xx_ocmcram_hwmod = { | ||
262 | .name = "ocmcram", | ||
263 | .class = &am33xx_ocmcram_hwmod_class, | ||
264 | .clkdm_name = "l3_clkdm", | ||
265 | .flags = HWMOD_INIT_NO_IDLE, | ||
266 | .main_clk = "l3_gclk", | ||
267 | .prcm = { | ||
268 | .omap4 = { | ||
269 | .modulemode = MODULEMODE_SWCTRL, | ||
270 | }, | ||
271 | }, | ||
272 | }; | ||
273 | |||
274 | /* 'smartreflex' class */ | ||
275 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | ||
276 | .name = "smartreflex", | ||
277 | }; | ||
278 | |||
279 | /* smartreflex0 */ | ||
280 | struct omap_hwmod am33xx_smartreflex0_hwmod = { | ||
281 | .name = "smartreflex0", | ||
282 | .class = &am33xx_smartreflex_hwmod_class, | ||
283 | .clkdm_name = "l4_wkup_clkdm", | ||
284 | .main_clk = "smartreflex0_fck", | ||
285 | .prcm = { | ||
286 | .omap4 = { | ||
287 | .modulemode = MODULEMODE_SWCTRL, | ||
288 | }, | ||
289 | }, | ||
290 | }; | ||
291 | |||
292 | /* smartreflex1 */ | ||
293 | struct omap_hwmod am33xx_smartreflex1_hwmod = { | ||
294 | .name = "smartreflex1", | ||
295 | .class = &am33xx_smartreflex_hwmod_class, | ||
296 | .clkdm_name = "l4_wkup_clkdm", | ||
297 | .main_clk = "smartreflex1_fck", | ||
298 | .prcm = { | ||
299 | .omap4 = { | ||
300 | .modulemode = MODULEMODE_SWCTRL, | ||
301 | }, | ||
302 | }, | ||
303 | }; | ||
304 | |||
305 | /* | ||
306 | * 'control' module class | ||
307 | */ | ||
308 | struct omap_hwmod_class am33xx_control_hwmod_class = { | ||
309 | .name = "control", | ||
310 | }; | ||
311 | |||
312 | /* | ||
313 | * 'cpgmac' class | ||
314 | * cpsw/cpgmac sub system | ||
315 | */ | ||
316 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { | ||
317 | .rev_offs = 0x0, | ||
318 | .sysc_offs = 0x8, | ||
319 | .syss_offs = 0x4, | ||
320 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | ||
321 | SYSS_HAS_RESET_STATUS), | ||
322 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | ||
323 | MSTANDBY_NO), | ||
324 | .sysc_fields = &omap_hwmod_sysc_type3, | ||
325 | }; | ||
326 | |||
327 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | ||
328 | .name = "cpgmac0", | ||
329 | .sysc = &am33xx_cpgmac_sysc, | ||
330 | }; | ||
331 | |||
332 | struct omap_hwmod am33xx_cpgmac0_hwmod = { | ||
333 | .name = "cpgmac0", | ||
334 | .class = &am33xx_cpgmac0_hwmod_class, | ||
335 | .clkdm_name = "cpsw_125mhz_clkdm", | ||
336 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | ||
337 | .main_clk = "cpsw_125mhz_gclk", | ||
338 | .mpu_rt_idx = 1, | ||
339 | .prcm = { | ||
340 | .omap4 = { | ||
341 | .modulemode = MODULEMODE_SWCTRL, | ||
342 | }, | ||
343 | }, | ||
344 | }; | ||
345 | |||
346 | /* | ||
347 | * mdio class | ||
348 | */ | ||
349 | static struct omap_hwmod_class am33xx_mdio_hwmod_class = { | ||
350 | .name = "davinci_mdio", | ||
351 | }; | ||
352 | |||
353 | struct omap_hwmod am33xx_mdio_hwmod = { | ||
354 | .name = "davinci_mdio", | ||
355 | .class = &am33xx_mdio_hwmod_class, | ||
356 | .clkdm_name = "cpsw_125mhz_clkdm", | ||
357 | .main_clk = "cpsw_125mhz_gclk", | ||
358 | }; | ||
359 | |||
360 | /* | ||
361 | * dcan class | ||
362 | */ | ||
363 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | ||
364 | .name = "d_can", | ||
365 | }; | ||
366 | |||
367 | /* dcan0 */ | ||
368 | struct omap_hwmod am33xx_dcan0_hwmod = { | ||
369 | .name = "d_can0", | ||
370 | .class = &am33xx_dcan_hwmod_class, | ||
371 | .clkdm_name = "l4ls_clkdm", | ||
372 | .main_clk = "dcan0_fck", | ||
373 | .prcm = { | ||
374 | .omap4 = { | ||
375 | .modulemode = MODULEMODE_SWCTRL, | ||
376 | }, | ||
377 | }, | ||
378 | }; | ||
379 | |||
380 | /* dcan1 */ | ||
381 | struct omap_hwmod am33xx_dcan1_hwmod = { | ||
382 | .name = "d_can1", | ||
383 | .class = &am33xx_dcan_hwmod_class, | ||
384 | .clkdm_name = "l4ls_clkdm", | ||
385 | .main_clk = "dcan1_fck", | ||
386 | .prcm = { | ||
387 | .omap4 = { | ||
388 | .modulemode = MODULEMODE_SWCTRL, | ||
389 | }, | ||
390 | }, | ||
391 | }; | ||
392 | |||
393 | /* elm */ | ||
394 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { | ||
395 | .rev_offs = 0x0000, | ||
396 | .sysc_offs = 0x0010, | ||
397 | .syss_offs = 0x0014, | ||
398 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
399 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
400 | SYSS_HAS_RESET_STATUS), | ||
401 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
402 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
403 | }; | ||
404 | |||
405 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { | ||
406 | .name = "elm", | ||
407 | .sysc = &am33xx_elm_sysc, | ||
408 | }; | ||
409 | |||
410 | struct omap_hwmod am33xx_elm_hwmod = { | ||
411 | .name = "elm", | ||
412 | .class = &am33xx_elm_hwmod_class, | ||
413 | .clkdm_name = "l4ls_clkdm", | ||
414 | .main_clk = "l4ls_gclk", | ||
415 | .prcm = { | ||
416 | .omap4 = { | ||
417 | .modulemode = MODULEMODE_SWCTRL, | ||
418 | }, | ||
419 | }, | ||
420 | }; | ||
421 | |||
422 | /* pwmss */ | ||
423 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { | ||
424 | .rev_offs = 0x0, | ||
425 | .sysc_offs = 0x4, | ||
426 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | ||
427 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
428 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | ||
429 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | ||
430 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
431 | }; | ||
432 | |||
433 | struct omap_hwmod_class am33xx_epwmss_hwmod_class = { | ||
434 | .name = "epwmss", | ||
435 | .sysc = &am33xx_epwmss_sysc, | ||
436 | }; | ||
437 | |||
438 | static struct omap_hwmod_class am33xx_ecap_hwmod_class = { | ||
439 | .name = "ecap", | ||
440 | }; | ||
441 | |||
442 | static struct omap_hwmod_class am33xx_eqep_hwmod_class = { | ||
443 | .name = "eqep", | ||
444 | }; | ||
445 | |||
446 | struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { | ||
447 | .name = "ehrpwm", | ||
448 | }; | ||
449 | |||
450 | /* epwmss0 */ | ||
451 | struct omap_hwmod am33xx_epwmss0_hwmod = { | ||
452 | .name = "epwmss0", | ||
453 | .class = &am33xx_epwmss_hwmod_class, | ||
454 | .clkdm_name = "l4ls_clkdm", | ||
455 | .main_clk = "l4ls_gclk", | ||
456 | .prcm = { | ||
457 | .omap4 = { | ||
458 | .modulemode = MODULEMODE_SWCTRL, | ||
459 | }, | ||
460 | }, | ||
461 | }; | ||
462 | |||
463 | /* ecap0 */ | ||
464 | struct omap_hwmod am33xx_ecap0_hwmod = { | ||
465 | .name = "ecap0", | ||
466 | .class = &am33xx_ecap_hwmod_class, | ||
467 | .clkdm_name = "l4ls_clkdm", | ||
468 | .main_clk = "l4ls_gclk", | ||
469 | }; | ||
470 | |||
471 | /* eqep0 */ | ||
472 | struct omap_hwmod am33xx_eqep0_hwmod = { | ||
473 | .name = "eqep0", | ||
474 | .class = &am33xx_eqep_hwmod_class, | ||
475 | .clkdm_name = "l4ls_clkdm", | ||
476 | .main_clk = "l4ls_gclk", | ||
477 | }; | ||
478 | |||
479 | /* ehrpwm0 */ | ||
480 | struct omap_hwmod am33xx_ehrpwm0_hwmod = { | ||
481 | .name = "ehrpwm0", | ||
482 | .class = &am33xx_ehrpwm_hwmod_class, | ||
483 | .clkdm_name = "l4ls_clkdm", | ||
484 | .main_clk = "l4ls_gclk", | ||
485 | }; | ||
486 | |||
487 | /* epwmss1 */ | ||
488 | struct omap_hwmod am33xx_epwmss1_hwmod = { | ||
489 | .name = "epwmss1", | ||
490 | .class = &am33xx_epwmss_hwmod_class, | ||
491 | .clkdm_name = "l4ls_clkdm", | ||
492 | .main_clk = "l4ls_gclk", | ||
493 | .prcm = { | ||
494 | .omap4 = { | ||
495 | .modulemode = MODULEMODE_SWCTRL, | ||
496 | }, | ||
497 | }, | ||
498 | }; | ||
499 | |||
500 | /* ecap1 */ | ||
501 | struct omap_hwmod am33xx_ecap1_hwmod = { | ||
502 | .name = "ecap1", | ||
503 | .class = &am33xx_ecap_hwmod_class, | ||
504 | .clkdm_name = "l4ls_clkdm", | ||
505 | .main_clk = "l4ls_gclk", | ||
506 | }; | ||
507 | |||
508 | /* eqep1 */ | ||
509 | struct omap_hwmod am33xx_eqep1_hwmod = { | ||
510 | .name = "eqep1", | ||
511 | .class = &am33xx_eqep_hwmod_class, | ||
512 | .clkdm_name = "l4ls_clkdm", | ||
513 | .main_clk = "l4ls_gclk", | ||
514 | }; | ||
515 | |||
516 | /* ehrpwm1 */ | ||
517 | struct omap_hwmod am33xx_ehrpwm1_hwmod = { | ||
518 | .name = "ehrpwm1", | ||
519 | .class = &am33xx_ehrpwm_hwmod_class, | ||
520 | .clkdm_name = "l4ls_clkdm", | ||
521 | .main_clk = "l4ls_gclk", | ||
522 | }; | ||
523 | |||
524 | /* epwmss2 */ | ||
525 | struct omap_hwmod am33xx_epwmss2_hwmod = { | ||
526 | .name = "epwmss2", | ||
527 | .class = &am33xx_epwmss_hwmod_class, | ||
528 | .clkdm_name = "l4ls_clkdm", | ||
529 | .main_clk = "l4ls_gclk", | ||
530 | .prcm = { | ||
531 | .omap4 = { | ||
532 | .modulemode = MODULEMODE_SWCTRL, | ||
533 | }, | ||
534 | }, | ||
535 | }; | ||
536 | |||
537 | /* ecap2 */ | ||
538 | struct omap_hwmod am33xx_ecap2_hwmod = { | ||
539 | .name = "ecap2", | ||
540 | .class = &am33xx_ecap_hwmod_class, | ||
541 | .clkdm_name = "l4ls_clkdm", | ||
542 | .main_clk = "l4ls_gclk", | ||
543 | }; | ||
544 | |||
545 | /* eqep2 */ | ||
546 | struct omap_hwmod am33xx_eqep2_hwmod = { | ||
547 | .name = "eqep2", | ||
548 | .class = &am33xx_eqep_hwmod_class, | ||
549 | .clkdm_name = "l4ls_clkdm", | ||
550 | .main_clk = "l4ls_gclk", | ||
551 | }; | ||
552 | |||
553 | /* ehrpwm2 */ | ||
554 | struct omap_hwmod am33xx_ehrpwm2_hwmod = { | ||
555 | .name = "ehrpwm2", | ||
556 | .class = &am33xx_ehrpwm_hwmod_class, | ||
557 | .clkdm_name = "l4ls_clkdm", | ||
558 | .main_clk = "l4ls_gclk", | ||
559 | }; | ||
560 | |||
561 | /* | ||
562 | * 'gpio' class: for gpio 0,1,2,3 | ||
563 | */ | ||
564 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { | ||
565 | .rev_offs = 0x0000, | ||
566 | .sysc_offs = 0x0010, | ||
567 | .syss_offs = 0x0114, | ||
568 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | ||
569 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
570 | SYSS_HAS_RESET_STATUS), | ||
571 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
572 | SIDLE_SMART_WKUP), | ||
573 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
574 | }; | ||
575 | |||
576 | struct omap_hwmod_class am33xx_gpio_hwmod_class = { | ||
577 | .name = "gpio", | ||
578 | .sysc = &am33xx_gpio_sysc, | ||
579 | .rev = 2, | ||
580 | }; | ||
581 | |||
582 | struct omap_gpio_dev_attr gpio_dev_attr = { | ||
583 | .bank_width = 32, | ||
584 | .dbck_flag = true, | ||
585 | }; | ||
586 | |||
587 | /* gpio1 */ | ||
588 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | ||
589 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | ||
590 | }; | ||
591 | |||
592 | struct omap_hwmod am33xx_gpio1_hwmod = { | ||
593 | .name = "gpio2", | ||
594 | .class = &am33xx_gpio_hwmod_class, | ||
595 | .clkdm_name = "l4ls_clkdm", | ||
596 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
597 | .main_clk = "l4ls_gclk", | ||
598 | .prcm = { | ||
599 | .omap4 = { | ||
600 | .modulemode = MODULEMODE_SWCTRL, | ||
601 | }, | ||
602 | }, | ||
603 | .opt_clks = gpio1_opt_clks, | ||
604 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | ||
605 | .dev_attr = &gpio_dev_attr, | ||
606 | }; | ||
607 | |||
608 | /* gpio2 */ | ||
609 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | ||
610 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | ||
611 | }; | ||
612 | |||
613 | struct omap_hwmod am33xx_gpio2_hwmod = { | ||
614 | .name = "gpio3", | ||
615 | .class = &am33xx_gpio_hwmod_class, | ||
616 | .clkdm_name = "l4ls_clkdm", | ||
617 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
618 | .main_clk = "l4ls_gclk", | ||
619 | .prcm = { | ||
620 | .omap4 = { | ||
621 | .modulemode = MODULEMODE_SWCTRL, | ||
622 | }, | ||
623 | }, | ||
624 | .opt_clks = gpio2_opt_clks, | ||
625 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | ||
626 | .dev_attr = &gpio_dev_attr, | ||
627 | }; | ||
628 | |||
629 | /* gpio3 */ | ||
630 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | ||
631 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | ||
632 | }; | ||
633 | |||
634 | struct omap_hwmod am33xx_gpio3_hwmod = { | ||
635 | .name = "gpio4", | ||
636 | .class = &am33xx_gpio_hwmod_class, | ||
637 | .clkdm_name = "l4ls_clkdm", | ||
638 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
639 | .main_clk = "l4ls_gclk", | ||
640 | .prcm = { | ||
641 | .omap4 = { | ||
642 | .modulemode = MODULEMODE_SWCTRL, | ||
643 | }, | ||
644 | }, | ||
645 | .opt_clks = gpio3_opt_clks, | ||
646 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | ||
647 | .dev_attr = &gpio_dev_attr, | ||
648 | }; | ||
649 | |||
650 | /* gpmc */ | ||
651 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { | ||
652 | .rev_offs = 0x0, | ||
653 | .sysc_offs = 0x10, | ||
654 | .syss_offs = 0x14, | ||
655 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | ||
656 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
657 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
658 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
659 | }; | ||
660 | |||
661 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | ||
662 | .name = "gpmc", | ||
663 | .sysc = &gpmc_sysc, | ||
664 | }; | ||
665 | |||
666 | struct omap_hwmod am33xx_gpmc_hwmod = { | ||
667 | .name = "gpmc", | ||
668 | .class = &am33xx_gpmc_hwmod_class, | ||
669 | .clkdm_name = "l3s_clkdm", | ||
670 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
671 | .main_clk = "l3s_gclk", | ||
672 | .prcm = { | ||
673 | .omap4 = { | ||
674 | .modulemode = MODULEMODE_SWCTRL, | ||
675 | }, | ||
676 | }, | ||
677 | }; | ||
678 | |||
679 | /* 'i2c' class */ | ||
680 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { | ||
681 | .sysc_offs = 0x0010, | ||
682 | .syss_offs = 0x0090, | ||
683 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
684 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
685 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
686 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
687 | SIDLE_SMART_WKUP), | ||
688 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
689 | }; | ||
690 | |||
691 | static struct omap_hwmod_class i2c_class = { | ||
692 | .name = "i2c", | ||
693 | .sysc = &am33xx_i2c_sysc, | ||
694 | .rev = OMAP_I2C_IP_VERSION_2, | ||
695 | .reset = &omap_i2c_reset, | ||
696 | }; | ||
697 | |||
698 | static struct omap_i2c_dev_attr i2c_dev_attr = { | ||
699 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | ||
700 | }; | ||
701 | |||
702 | /* i2c1 */ | ||
703 | struct omap_hwmod am33xx_i2c1_hwmod = { | ||
704 | .name = "i2c1", | ||
705 | .class = &i2c_class, | ||
706 | .clkdm_name = "l4_wkup_clkdm", | ||
707 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | ||
708 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | ||
709 | .prcm = { | ||
710 | .omap4 = { | ||
711 | .modulemode = MODULEMODE_SWCTRL, | ||
712 | }, | ||
713 | }, | ||
714 | .dev_attr = &i2c_dev_attr, | ||
715 | }; | ||
716 | |||
717 | /* i2c1 */ | ||
718 | struct omap_hwmod am33xx_i2c2_hwmod = { | ||
719 | .name = "i2c2", | ||
720 | .class = &i2c_class, | ||
721 | .clkdm_name = "l4ls_clkdm", | ||
722 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | ||
723 | .main_clk = "dpll_per_m2_div4_ck", | ||
724 | .prcm = { | ||
725 | .omap4 = { | ||
726 | .modulemode = MODULEMODE_SWCTRL, | ||
727 | }, | ||
728 | }, | ||
729 | .dev_attr = &i2c_dev_attr, | ||
730 | }; | ||
731 | |||
732 | /* i2c3 */ | ||
733 | struct omap_hwmod am33xx_i2c3_hwmod = { | ||
734 | .name = "i2c3", | ||
735 | .class = &i2c_class, | ||
736 | .clkdm_name = "l4ls_clkdm", | ||
737 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | ||
738 | .main_clk = "dpll_per_m2_div4_ck", | ||
739 | .prcm = { | ||
740 | .omap4 = { | ||
741 | .modulemode = MODULEMODE_SWCTRL, | ||
742 | }, | ||
743 | }, | ||
744 | .dev_attr = &i2c_dev_attr, | ||
745 | }; | ||
746 | |||
747 | /* | ||
748 | * 'mailbox' class | ||
749 | * mailbox module allowing communication between the on-chip processors using a | ||
750 | * queued mailbox-interrupt mechanism. | ||
751 | */ | ||
752 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { | ||
753 | .rev_offs = 0x0000, | ||
754 | .sysc_offs = 0x0010, | ||
755 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | ||
756 | SYSC_HAS_SOFTRESET), | ||
757 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
758 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
759 | }; | ||
760 | |||
761 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | ||
762 | .name = "mailbox", | ||
763 | .sysc = &am33xx_mailbox_sysc, | ||
764 | }; | ||
765 | |||
766 | struct omap_hwmod am33xx_mailbox_hwmod = { | ||
767 | .name = "mailbox", | ||
768 | .class = &am33xx_mailbox_hwmod_class, | ||
769 | .clkdm_name = "l4ls_clkdm", | ||
770 | .main_clk = "l4ls_gclk", | ||
771 | .prcm = { | ||
772 | .omap4 = { | ||
773 | .modulemode = MODULEMODE_SWCTRL, | ||
774 | }, | ||
775 | }, | ||
776 | }; | ||
777 | |||
778 | /* | ||
779 | * 'mcasp' class | ||
780 | */ | ||
781 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { | ||
782 | .rev_offs = 0x0, | ||
783 | .sysc_offs = 0x4, | ||
784 | .sysc_flags = SYSC_HAS_SIDLEMODE, | ||
785 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
786 | .sysc_fields = &omap_hwmod_sysc_type3, | ||
787 | }; | ||
788 | |||
789 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | ||
790 | .name = "mcasp", | ||
791 | .sysc = &am33xx_mcasp_sysc, | ||
792 | }; | ||
793 | |||
794 | /* mcasp0 */ | ||
795 | struct omap_hwmod am33xx_mcasp0_hwmod = { | ||
796 | .name = "mcasp0", | ||
797 | .class = &am33xx_mcasp_hwmod_class, | ||
798 | .clkdm_name = "l3s_clkdm", | ||
799 | .main_clk = "mcasp0_fck", | ||
800 | .prcm = { | ||
801 | .omap4 = { | ||
802 | .modulemode = MODULEMODE_SWCTRL, | ||
803 | }, | ||
804 | }, | ||
805 | }; | ||
806 | |||
807 | /* mcasp1 */ | ||
808 | struct omap_hwmod am33xx_mcasp1_hwmod = { | ||
809 | .name = "mcasp1", | ||
810 | .class = &am33xx_mcasp_hwmod_class, | ||
811 | .clkdm_name = "l3s_clkdm", | ||
812 | .main_clk = "mcasp1_fck", | ||
813 | .prcm = { | ||
814 | .omap4 = { | ||
815 | .modulemode = MODULEMODE_SWCTRL, | ||
816 | }, | ||
817 | }, | ||
818 | }; | ||
819 | |||
820 | /* 'mmc' class */ | ||
821 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { | ||
822 | .rev_offs = 0x1fc, | ||
823 | .sysc_offs = 0x10, | ||
824 | .syss_offs = 0x14, | ||
825 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
826 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | ||
827 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | ||
828 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
829 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
830 | }; | ||
831 | |||
832 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | ||
833 | .name = "mmc", | ||
834 | .sysc = &am33xx_mmc_sysc, | ||
835 | }; | ||
836 | |||
837 | /* mmc0 */ | ||
838 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { | ||
839 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | ||
840 | }; | ||
841 | |||
842 | struct omap_hwmod am33xx_mmc0_hwmod = { | ||
843 | .name = "mmc1", | ||
844 | .class = &am33xx_mmc_hwmod_class, | ||
845 | .clkdm_name = "l4ls_clkdm", | ||
846 | .main_clk = "mmc_clk", | ||
847 | .prcm = { | ||
848 | .omap4 = { | ||
849 | .modulemode = MODULEMODE_SWCTRL, | ||
850 | }, | ||
851 | }, | ||
852 | .dev_attr = &am33xx_mmc0_dev_attr, | ||
853 | }; | ||
854 | |||
855 | /* mmc1 */ | ||
856 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { | ||
857 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | ||
858 | }; | ||
859 | |||
860 | struct omap_hwmod am33xx_mmc1_hwmod = { | ||
861 | .name = "mmc2", | ||
862 | .class = &am33xx_mmc_hwmod_class, | ||
863 | .clkdm_name = "l4ls_clkdm", | ||
864 | .main_clk = "mmc_clk", | ||
865 | .prcm = { | ||
866 | .omap4 = { | ||
867 | .modulemode = MODULEMODE_SWCTRL, | ||
868 | }, | ||
869 | }, | ||
870 | .dev_attr = &am33xx_mmc1_dev_attr, | ||
871 | }; | ||
872 | |||
873 | /* mmc2 */ | ||
874 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { | ||
875 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | ||
876 | }; | ||
877 | struct omap_hwmod am33xx_mmc2_hwmod = { | ||
878 | .name = "mmc3", | ||
879 | .class = &am33xx_mmc_hwmod_class, | ||
880 | .clkdm_name = "l3s_clkdm", | ||
881 | .main_clk = "mmc_clk", | ||
882 | .prcm = { | ||
883 | .omap4 = { | ||
884 | .modulemode = MODULEMODE_SWCTRL, | ||
885 | }, | ||
886 | }, | ||
887 | .dev_attr = &am33xx_mmc2_dev_attr, | ||
888 | }; | ||
889 | |||
890 | /* | ||
891 | * 'rtc' class | ||
892 | * rtc subsystem | ||
893 | */ | ||
894 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { | ||
895 | .rev_offs = 0x0074, | ||
896 | .sysc_offs = 0x0078, | ||
897 | .sysc_flags = SYSC_HAS_SIDLEMODE, | ||
898 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | | ||
899 | SIDLE_SMART | SIDLE_SMART_WKUP), | ||
900 | .sysc_fields = &omap_hwmod_sysc_type3, | ||
901 | }; | ||
902 | |||
903 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | ||
904 | .name = "rtc", | ||
905 | .sysc = &am33xx_rtc_sysc, | ||
906 | }; | ||
907 | |||
908 | struct omap_hwmod am33xx_rtc_hwmod = { | ||
909 | .name = "rtc", | ||
910 | .class = &am33xx_rtc_hwmod_class, | ||
911 | .clkdm_name = "l4_rtc_clkdm", | ||
912 | .main_clk = "clk_32768_ck", | ||
913 | .prcm = { | ||
914 | .omap4 = { | ||
915 | .modulemode = MODULEMODE_SWCTRL, | ||
916 | }, | ||
917 | }, | ||
918 | }; | ||
919 | |||
920 | /* 'spi' class */ | ||
921 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { | ||
922 | .rev_offs = 0x0000, | ||
923 | .sysc_offs = 0x0110, | ||
924 | .syss_offs = 0x0114, | ||
925 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
926 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
927 | SYSS_HAS_RESET_STATUS), | ||
928 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
929 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
930 | }; | ||
931 | |||
932 | struct omap_hwmod_class am33xx_spi_hwmod_class = { | ||
933 | .name = "mcspi", | ||
934 | .sysc = &am33xx_mcspi_sysc, | ||
935 | .rev = OMAP4_MCSPI_REV, | ||
936 | }; | ||
937 | |||
938 | /* spi0 */ | ||
939 | struct omap2_mcspi_dev_attr mcspi_attrib = { | ||
940 | .num_chipselect = 2, | ||
941 | }; | ||
942 | struct omap_hwmod am33xx_spi0_hwmod = { | ||
943 | .name = "spi0", | ||
944 | .class = &am33xx_spi_hwmod_class, | ||
945 | .clkdm_name = "l4ls_clkdm", | ||
946 | .main_clk = "dpll_per_m2_div4_ck", | ||
947 | .prcm = { | ||
948 | .omap4 = { | ||
949 | .modulemode = MODULEMODE_SWCTRL, | ||
950 | }, | ||
951 | }, | ||
952 | .dev_attr = &mcspi_attrib, | ||
953 | }; | ||
954 | |||
955 | /* spi1 */ | ||
956 | struct omap_hwmod am33xx_spi1_hwmod = { | ||
957 | .name = "spi1", | ||
958 | .class = &am33xx_spi_hwmod_class, | ||
959 | .clkdm_name = "l4ls_clkdm", | ||
960 | .main_clk = "dpll_per_m2_div4_ck", | ||
961 | .prcm = { | ||
962 | .omap4 = { | ||
963 | .modulemode = MODULEMODE_SWCTRL, | ||
964 | }, | ||
965 | }, | ||
966 | .dev_attr = &mcspi_attrib, | ||
967 | }; | ||
968 | |||
969 | /* | ||
970 | * 'spinlock' class | ||
971 | * spinlock provides hardware assistance for synchronizing the | ||
972 | * processes running on multiple processors | ||
973 | */ | ||
974 | |||
975 | static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = { | ||
976 | .rev_offs = 0x0000, | ||
977 | .sysc_offs = 0x0010, | ||
978 | .syss_offs = 0x0014, | ||
979 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
980 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
981 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
982 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
983 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
984 | }; | ||
985 | |||
986 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { | ||
987 | .name = "spinlock", | ||
988 | .sysc = &am33xx_spinlock_sysc, | ||
989 | }; | ||
990 | |||
991 | struct omap_hwmod am33xx_spinlock_hwmod = { | ||
992 | .name = "spinlock", | ||
993 | .class = &am33xx_spinlock_hwmod_class, | ||
994 | .clkdm_name = "l4ls_clkdm", | ||
995 | .main_clk = "l4ls_gclk", | ||
996 | .prcm = { | ||
997 | .omap4 = { | ||
998 | .modulemode = MODULEMODE_SWCTRL, | ||
999 | }, | ||
1000 | }, | ||
1001 | }; | ||
1002 | |||
1003 | /* 'timer 2-7' class */ | ||
1004 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { | ||
1005 | .rev_offs = 0x0000, | ||
1006 | .sysc_offs = 0x0010, | ||
1007 | .syss_offs = 0x0014, | ||
1008 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | ||
1009 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1010 | SIDLE_SMART_WKUP), | ||
1011 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
1012 | }; | ||
1013 | |||
1014 | struct omap_hwmod_class am33xx_timer_hwmod_class = { | ||
1015 | .name = "timer", | ||
1016 | .sysc = &am33xx_timer_sysc, | ||
1017 | }; | ||
1018 | |||
1019 | /* timer1 1ms */ | ||
1020 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { | ||
1021 | .rev_offs = 0x0000, | ||
1022 | .sysc_offs = 0x0010, | ||
1023 | .syss_offs = 0x0014, | ||
1024 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
1025 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
1026 | SYSS_HAS_RESET_STATUS), | ||
1027 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1028 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1029 | }; | ||
1030 | |||
1031 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | ||
1032 | .name = "timer", | ||
1033 | .sysc = &am33xx_timer1ms_sysc, | ||
1034 | }; | ||
1035 | |||
1036 | struct omap_hwmod am33xx_timer1_hwmod = { | ||
1037 | .name = "timer1", | ||
1038 | .class = &am33xx_timer1ms_hwmod_class, | ||
1039 | .clkdm_name = "l4_wkup_clkdm", | ||
1040 | .main_clk = "timer1_fck", | ||
1041 | .prcm = { | ||
1042 | .omap4 = { | ||
1043 | .modulemode = MODULEMODE_SWCTRL, | ||
1044 | }, | ||
1045 | }, | ||
1046 | }; | ||
1047 | |||
1048 | struct omap_hwmod am33xx_timer2_hwmod = { | ||
1049 | .name = "timer2", | ||
1050 | .class = &am33xx_timer_hwmod_class, | ||
1051 | .clkdm_name = "l4ls_clkdm", | ||
1052 | .main_clk = "timer2_fck", | ||
1053 | .prcm = { | ||
1054 | .omap4 = { | ||
1055 | .modulemode = MODULEMODE_SWCTRL, | ||
1056 | }, | ||
1057 | }, | ||
1058 | }; | ||
1059 | |||
1060 | struct omap_hwmod am33xx_timer3_hwmod = { | ||
1061 | .name = "timer3", | ||
1062 | .class = &am33xx_timer_hwmod_class, | ||
1063 | .clkdm_name = "l4ls_clkdm", | ||
1064 | .main_clk = "timer3_fck", | ||
1065 | .prcm = { | ||
1066 | .omap4 = { | ||
1067 | .modulemode = MODULEMODE_SWCTRL, | ||
1068 | }, | ||
1069 | }, | ||
1070 | }; | ||
1071 | |||
1072 | struct omap_hwmod am33xx_timer4_hwmod = { | ||
1073 | .name = "timer4", | ||
1074 | .class = &am33xx_timer_hwmod_class, | ||
1075 | .clkdm_name = "l4ls_clkdm", | ||
1076 | .main_clk = "timer4_fck", | ||
1077 | .prcm = { | ||
1078 | .omap4 = { | ||
1079 | .modulemode = MODULEMODE_SWCTRL, | ||
1080 | }, | ||
1081 | }, | ||
1082 | }; | ||
1083 | |||
1084 | struct omap_hwmod am33xx_timer5_hwmod = { | ||
1085 | .name = "timer5", | ||
1086 | .class = &am33xx_timer_hwmod_class, | ||
1087 | .clkdm_name = "l4ls_clkdm", | ||
1088 | .main_clk = "timer5_fck", | ||
1089 | .prcm = { | ||
1090 | .omap4 = { | ||
1091 | .modulemode = MODULEMODE_SWCTRL, | ||
1092 | }, | ||
1093 | }, | ||
1094 | }; | ||
1095 | |||
1096 | struct omap_hwmod am33xx_timer6_hwmod = { | ||
1097 | .name = "timer6", | ||
1098 | .class = &am33xx_timer_hwmod_class, | ||
1099 | .clkdm_name = "l4ls_clkdm", | ||
1100 | .main_clk = "timer6_fck", | ||
1101 | .prcm = { | ||
1102 | .omap4 = { | ||
1103 | .modulemode = MODULEMODE_SWCTRL, | ||
1104 | }, | ||
1105 | }, | ||
1106 | }; | ||
1107 | |||
1108 | struct omap_hwmod am33xx_timer7_hwmod = { | ||
1109 | .name = "timer7", | ||
1110 | .class = &am33xx_timer_hwmod_class, | ||
1111 | .clkdm_name = "l4ls_clkdm", | ||
1112 | .main_clk = "timer7_fck", | ||
1113 | .prcm = { | ||
1114 | .omap4 = { | ||
1115 | .modulemode = MODULEMODE_SWCTRL, | ||
1116 | }, | ||
1117 | }, | ||
1118 | }; | ||
1119 | |||
1120 | /* tpcc */ | ||
1121 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | ||
1122 | .name = "tpcc", | ||
1123 | }; | ||
1124 | |||
1125 | struct omap_hwmod am33xx_tpcc_hwmod = { | ||
1126 | .name = "tpcc", | ||
1127 | .class = &am33xx_tpcc_hwmod_class, | ||
1128 | .clkdm_name = "l3_clkdm", | ||
1129 | .main_clk = "l3_gclk", | ||
1130 | .prcm = { | ||
1131 | .omap4 = { | ||
1132 | .modulemode = MODULEMODE_SWCTRL, | ||
1133 | }, | ||
1134 | }, | ||
1135 | }; | ||
1136 | |||
1137 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { | ||
1138 | .rev_offs = 0x0, | ||
1139 | .sysc_offs = 0x10, | ||
1140 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
1141 | SYSC_HAS_MIDLEMODE), | ||
1142 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), | ||
1143 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
1144 | }; | ||
1145 | |||
1146 | /* 'tptc' class */ | ||
1147 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | ||
1148 | .name = "tptc", | ||
1149 | .sysc = &am33xx_tptc_sysc, | ||
1150 | }; | ||
1151 | |||
1152 | /* tptc0 */ | ||
1153 | struct omap_hwmod am33xx_tptc0_hwmod = { | ||
1154 | .name = "tptc0", | ||
1155 | .class = &am33xx_tptc_hwmod_class, | ||
1156 | .clkdm_name = "l3_clkdm", | ||
1157 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | ||
1158 | .main_clk = "l3_gclk", | ||
1159 | .prcm = { | ||
1160 | .omap4 = { | ||
1161 | .modulemode = MODULEMODE_SWCTRL, | ||
1162 | }, | ||
1163 | }, | ||
1164 | }; | ||
1165 | |||
1166 | /* tptc1 */ | ||
1167 | struct omap_hwmod am33xx_tptc1_hwmod = { | ||
1168 | .name = "tptc1", | ||
1169 | .class = &am33xx_tptc_hwmod_class, | ||
1170 | .clkdm_name = "l3_clkdm", | ||
1171 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | ||
1172 | .main_clk = "l3_gclk", | ||
1173 | .prcm = { | ||
1174 | .omap4 = { | ||
1175 | .modulemode = MODULEMODE_SWCTRL, | ||
1176 | }, | ||
1177 | }, | ||
1178 | }; | ||
1179 | |||
1180 | /* tptc2 */ | ||
1181 | struct omap_hwmod am33xx_tptc2_hwmod = { | ||
1182 | .name = "tptc2", | ||
1183 | .class = &am33xx_tptc_hwmod_class, | ||
1184 | .clkdm_name = "l3_clkdm", | ||
1185 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | ||
1186 | .main_clk = "l3_gclk", | ||
1187 | .prcm = { | ||
1188 | .omap4 = { | ||
1189 | .modulemode = MODULEMODE_SWCTRL, | ||
1190 | }, | ||
1191 | }, | ||
1192 | }; | ||
1193 | |||
1194 | /* 'uart' class */ | ||
1195 | static struct omap_hwmod_class_sysconfig uart_sysc = { | ||
1196 | .rev_offs = 0x50, | ||
1197 | .sysc_offs = 0x54, | ||
1198 | .syss_offs = 0x58, | ||
1199 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | ||
1200 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
1201 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1202 | SIDLE_SMART_WKUP), | ||
1203 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1204 | }; | ||
1205 | |||
1206 | static struct omap_hwmod_class uart_class = { | ||
1207 | .name = "uart", | ||
1208 | .sysc = &uart_sysc, | ||
1209 | }; | ||
1210 | |||
1211 | struct omap_hwmod am33xx_uart1_hwmod = { | ||
1212 | .name = "uart1", | ||
1213 | .class = &uart_class, | ||
1214 | .clkdm_name = "l4_wkup_clkdm", | ||
1215 | .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, | ||
1216 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | ||
1217 | .prcm = { | ||
1218 | .omap4 = { | ||
1219 | .modulemode = MODULEMODE_SWCTRL, | ||
1220 | }, | ||
1221 | }, | ||
1222 | }; | ||
1223 | |||
1224 | struct omap_hwmod am33xx_uart2_hwmod = { | ||
1225 | .name = "uart2", | ||
1226 | .class = &uart_class, | ||
1227 | .clkdm_name = "l4ls_clkdm", | ||
1228 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1229 | .main_clk = "dpll_per_m2_div4_ck", | ||
1230 | .prcm = { | ||
1231 | .omap4 = { | ||
1232 | .modulemode = MODULEMODE_SWCTRL, | ||
1233 | }, | ||
1234 | }, | ||
1235 | }; | ||
1236 | |||
1237 | /* uart3 */ | ||
1238 | struct omap_hwmod am33xx_uart3_hwmod = { | ||
1239 | .name = "uart3", | ||
1240 | .class = &uart_class, | ||
1241 | .clkdm_name = "l4ls_clkdm", | ||
1242 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1243 | .main_clk = "dpll_per_m2_div4_ck", | ||
1244 | .prcm = { | ||
1245 | .omap4 = { | ||
1246 | .modulemode = MODULEMODE_SWCTRL, | ||
1247 | }, | ||
1248 | }, | ||
1249 | }; | ||
1250 | |||
1251 | struct omap_hwmod am33xx_uart4_hwmod = { | ||
1252 | .name = "uart4", | ||
1253 | .class = &uart_class, | ||
1254 | .clkdm_name = "l4ls_clkdm", | ||
1255 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1256 | .main_clk = "dpll_per_m2_div4_ck", | ||
1257 | .prcm = { | ||
1258 | .omap4 = { | ||
1259 | .modulemode = MODULEMODE_SWCTRL, | ||
1260 | }, | ||
1261 | }, | ||
1262 | }; | ||
1263 | |||
1264 | struct omap_hwmod am33xx_uart5_hwmod = { | ||
1265 | .name = "uart5", | ||
1266 | .class = &uart_class, | ||
1267 | .clkdm_name = "l4ls_clkdm", | ||
1268 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1269 | .main_clk = "dpll_per_m2_div4_ck", | ||
1270 | .prcm = { | ||
1271 | .omap4 = { | ||
1272 | .modulemode = MODULEMODE_SWCTRL, | ||
1273 | }, | ||
1274 | }, | ||
1275 | }; | ||
1276 | |||
1277 | struct omap_hwmod am33xx_uart6_hwmod = { | ||
1278 | .name = "uart6", | ||
1279 | .class = &uart_class, | ||
1280 | .clkdm_name = "l4ls_clkdm", | ||
1281 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1282 | .main_clk = "dpll_per_m2_div4_ck", | ||
1283 | .prcm = { | ||
1284 | .omap4 = { | ||
1285 | .modulemode = MODULEMODE_SWCTRL, | ||
1286 | }, | ||
1287 | }, | ||
1288 | }; | ||
1289 | |||
1290 | /* 'wd_timer' class */ | ||
1291 | static struct omap_hwmod_class_sysconfig wdt_sysc = { | ||
1292 | .rev_offs = 0x0, | ||
1293 | .sysc_offs = 0x10, | ||
1294 | .syss_offs = 0x14, | ||
1295 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | ||
1296 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
1297 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1298 | SIDLE_SMART_WKUP), | ||
1299 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1300 | }; | ||
1301 | |||
1302 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { | ||
1303 | .name = "wd_timer", | ||
1304 | .sysc = &wdt_sysc, | ||
1305 | .pre_shutdown = &omap2_wd_timer_disable, | ||
1306 | }; | ||
1307 | |||
1308 | /* | ||
1309 | * XXX: device.c file uses hardcoded name for watchdog timer | ||
1310 | * driver "wd_timer2, so we are also using same name as of now... | ||
1311 | */ | ||
1312 | struct omap_hwmod am33xx_wd_timer1_hwmod = { | ||
1313 | .name = "wd_timer2", | ||
1314 | .class = &am33xx_wd_timer_hwmod_class, | ||
1315 | .clkdm_name = "l4_wkup_clkdm", | ||
1316 | .flags = HWMOD_SWSUP_SIDLE, | ||
1317 | .main_clk = "wdt1_fck", | ||
1318 | .prcm = { | ||
1319 | .omap4 = { | ||
1320 | .modulemode = MODULEMODE_SWCTRL, | ||
1321 | }, | ||
1322 | }, | ||
1323 | }; | ||
1324 | |||
1325 | static void omap_hwmod_am33xx_clkctrl(void) | ||
1326 | { | ||
1327 | CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET); | ||
1328 | CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET); | ||
1329 | CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET); | ||
1330 | CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET); | ||
1331 | CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET); | ||
1332 | CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET); | ||
1333 | CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET); | ||
1334 | CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET); | ||
1335 | CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); | ||
1336 | CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); | ||
1337 | CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); | ||
1338 | CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET); | ||
1339 | CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET); | ||
1340 | CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET); | ||
1341 | CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET); | ||
1342 | CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET); | ||
1343 | CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET); | ||
1344 | CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET); | ||
1345 | CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET); | ||
1346 | CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET); | ||
1347 | CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET); | ||
1348 | CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET); | ||
1349 | CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET); | ||
1350 | CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); | ||
1351 | CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); | ||
1352 | CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET); | ||
1353 | CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET); | ||
1354 | CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET); | ||
1355 | CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET); | ||
1356 | CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET); | ||
1357 | CLKCTRL(am33xx_smartreflex0_hwmod, | ||
1358 | AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); | ||
1359 | CLKCTRL(am33xx_smartreflex1_hwmod, | ||
1360 | AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); | ||
1361 | CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET); | ||
1362 | CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); | ||
1363 | CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET); | ||
1364 | CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET); | ||
1365 | CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET); | ||
1366 | CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET); | ||
1367 | CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); | ||
1368 | CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); | ||
1369 | CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); | ||
1370 | CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); | ||
1371 | CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET); | ||
1372 | CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET); | ||
1373 | CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET); | ||
1374 | CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET); | ||
1375 | CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET); | ||
1376 | CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET); | ||
1377 | CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET); | ||
1378 | CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); | ||
1379 | CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); | ||
1380 | CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); | ||
1381 | CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET); | ||
1382 | CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); | ||
1383 | } | ||
1384 | |||
1385 | static void omap_hwmod_am33xx_rst(void) | ||
1386 | { | ||
1387 | RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET); | ||
1388 | RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET); | ||
1389 | RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET); | ||
1390 | } | ||
1391 | |||
1392 | void omap_hwmod_am33xx_reg(void) | ||
1393 | { | ||
1394 | omap_hwmod_am33xx_clkctrl(); | ||
1395 | omap_hwmod_am33xx_rst(); | ||
1396 | } | ||
1397 | |||
1398 | static void omap_hwmod_am43xx_clkctrl(void) | ||
1399 | { | ||
1400 | CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET); | ||
1401 | CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET); | ||
1402 | CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET); | ||
1403 | CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET); | ||
1404 | CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET); | ||
1405 | CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET); | ||
1406 | CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET); | ||
1407 | CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET); | ||
1408 | CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); | ||
1409 | CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); | ||
1410 | CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); | ||
1411 | CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET); | ||
1412 | CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET); | ||
1413 | CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET); | ||
1414 | CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET); | ||
1415 | CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET); | ||
1416 | CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET); | ||
1417 | CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET); | ||
1418 | CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET); | ||
1419 | CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET); | ||
1420 | CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET); | ||
1421 | CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET); | ||
1422 | CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET); | ||
1423 | CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); | ||
1424 | CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET); | ||
1425 | CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET); | ||
1426 | CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET); | ||
1427 | CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET); | ||
1428 | CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET); | ||
1429 | CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET); | ||
1430 | CLKCTRL(am33xx_smartreflex0_hwmod, | ||
1431 | AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); | ||
1432 | CLKCTRL(am33xx_smartreflex1_hwmod, | ||
1433 | AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); | ||
1434 | CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET); | ||
1435 | CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); | ||
1436 | CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET); | ||
1437 | CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET); | ||
1438 | CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET); | ||
1439 | CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET); | ||
1440 | CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET); | ||
1441 | CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); | ||
1442 | CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); | ||
1443 | CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); | ||
1444 | CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET); | ||
1445 | CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET); | ||
1446 | CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET); | ||
1447 | CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET); | ||
1448 | CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET); | ||
1449 | CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET); | ||
1450 | CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET); | ||
1451 | CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); | ||
1452 | CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); | ||
1453 | CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); | ||
1454 | CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET); | ||
1455 | CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); | ||
1456 | } | ||
1457 | |||
1458 | static void omap_hwmod_am43xx_rst(void) | ||
1459 | { | ||
1460 | RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET); | ||
1461 | RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); | ||
1462 | RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); | ||
1463 | } | ||
1464 | |||
1465 | void omap_hwmod_am43xx_reg(void) | ||
1466 | { | ||
1467 | omap_hwmod_am43xx_clkctrl(); | ||
1468 | omap_hwmod_am43xx_rst(); | ||
1469 | } | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 215894f8910d..6b406ca4bd3b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include "i2c.h" | 29 | #include "i2c.h" |
30 | #include "mmc.h" | 30 | #include "mmc.h" |
31 | #include "wd_timer.h" | 31 | #include "wd_timer.h" |
32 | #include "omap_hwmod_33xx_43xx_common_data.h" | ||
32 | 33 | ||
33 | /* | 34 | /* |
34 | * IP blocks | 35 | * IP blocks |
@@ -52,7 +53,7 @@ static struct omap_hwmod am33xx_emif_hwmod = { | |||
52 | .name = "emif", | 53 | .name = "emif", |
53 | .class = &am33xx_emif_hwmod_class, | 54 | .class = &am33xx_emif_hwmod_class, |
54 | .clkdm_name = "l3_clkdm", | 55 | .clkdm_name = "l3_clkdm", |
55 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 56 | .flags = HWMOD_INIT_NO_IDLE, |
56 | .main_clk = "dpll_ddr_m2_div2_ck", | 57 | .main_clk = "dpll_ddr_m2_div2_ck", |
57 | .prcm = { | 58 | .prcm = { |
58 | .omap4 = { | 59 | .omap4 = { |
@@ -62,79 +63,12 @@ static struct omap_hwmod am33xx_emif_hwmod = { | |||
62 | }, | 63 | }, |
63 | }; | 64 | }; |
64 | 65 | ||
65 | /* | ||
66 | * 'l3' class | ||
67 | * instance(s): l3_main, l3_s, l3_instr | ||
68 | */ | ||
69 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { | ||
70 | .name = "l3", | ||
71 | }; | ||
72 | |||
73 | static struct omap_hwmod am33xx_l3_main_hwmod = { | ||
74 | .name = "l3_main", | ||
75 | .class = &am33xx_l3_hwmod_class, | ||
76 | .clkdm_name = "l3_clkdm", | ||
77 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
78 | .main_clk = "l3_gclk", | ||
79 | .prcm = { | ||
80 | .omap4 = { | ||
81 | .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, | ||
82 | .modulemode = MODULEMODE_SWCTRL, | ||
83 | }, | ||
84 | }, | ||
85 | }; | ||
86 | |||
87 | /* l3_s */ | ||
88 | static struct omap_hwmod am33xx_l3_s_hwmod = { | ||
89 | .name = "l3_s", | ||
90 | .class = &am33xx_l3_hwmod_class, | ||
91 | .clkdm_name = "l3s_clkdm", | ||
92 | }; | ||
93 | |||
94 | /* l3_instr */ | ||
95 | static struct omap_hwmod am33xx_l3_instr_hwmod = { | ||
96 | .name = "l3_instr", | ||
97 | .class = &am33xx_l3_hwmod_class, | ||
98 | .clkdm_name = "l3_clkdm", | ||
99 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
100 | .main_clk = "l3_gclk", | ||
101 | .prcm = { | ||
102 | .omap4 = { | ||
103 | .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, | ||
104 | .modulemode = MODULEMODE_SWCTRL, | ||
105 | }, | ||
106 | }, | ||
107 | }; | ||
108 | |||
109 | /* | ||
110 | * 'l4' class | ||
111 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw | ||
112 | */ | ||
113 | static struct omap_hwmod_class am33xx_l4_hwmod_class = { | ||
114 | .name = "l4", | ||
115 | }; | ||
116 | |||
117 | /* l4_ls */ | ||
118 | static struct omap_hwmod am33xx_l4_ls_hwmod = { | ||
119 | .name = "l4_ls", | ||
120 | .class = &am33xx_l4_hwmod_class, | ||
121 | .clkdm_name = "l4ls_clkdm", | ||
122 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
123 | .main_clk = "l4ls_gclk", | ||
124 | .prcm = { | ||
125 | .omap4 = { | ||
126 | .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, | ||
127 | .modulemode = MODULEMODE_SWCTRL, | ||
128 | }, | ||
129 | }, | ||
130 | }; | ||
131 | |||
132 | /* l4_hs */ | 66 | /* l4_hs */ |
133 | static struct omap_hwmod am33xx_l4_hs_hwmod = { | 67 | static struct omap_hwmod am33xx_l4_hs_hwmod = { |
134 | .name = "l4_hs", | 68 | .name = "l4_hs", |
135 | .class = &am33xx_l4_hwmod_class, | 69 | .class = &am33xx_l4_hwmod_class, |
136 | .clkdm_name = "l4hs_clkdm", | 70 | .clkdm_name = "l4hs_clkdm", |
137 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 71 | .flags = HWMOD_INIT_NO_IDLE, |
138 | .main_clk = "l4hs_gclk", | 72 | .main_clk = "l4hs_gclk", |
139 | .prcm = { | 73 | .prcm = { |
140 | .omap4 = { | 74 | .omap4 = { |
@@ -144,50 +78,6 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = { | |||
144 | }, | 78 | }, |
145 | }; | 79 | }; |
146 | 80 | ||
147 | |||
148 | /* l4_wkup */ | ||
149 | static struct omap_hwmod am33xx_l4_wkup_hwmod = { | ||
150 | .name = "l4_wkup", | ||
151 | .class = &am33xx_l4_hwmod_class, | ||
152 | .clkdm_name = "l4_wkup_clkdm", | ||
153 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
154 | .prcm = { | ||
155 | .omap4 = { | ||
156 | .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | ||
157 | .modulemode = MODULEMODE_SWCTRL, | ||
158 | }, | ||
159 | }, | ||
160 | }; | ||
161 | |||
162 | /* | ||
163 | * 'mpu' class | ||
164 | */ | ||
165 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | ||
166 | .name = "mpu", | ||
167 | }; | ||
168 | |||
169 | static struct omap_hwmod am33xx_mpu_hwmod = { | ||
170 | .name = "mpu", | ||
171 | .class = &am33xx_mpu_hwmod_class, | ||
172 | .clkdm_name = "mpu_clkdm", | ||
173 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
174 | .main_clk = "dpll_mpu_m2_ck", | ||
175 | .prcm = { | ||
176 | .omap4 = { | ||
177 | .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, | ||
178 | .modulemode = MODULEMODE_SWCTRL, | ||
179 | }, | ||
180 | }, | ||
181 | }; | ||
182 | |||
183 | /* | ||
184 | * 'wakeup m3' class | ||
185 | * Wakeup controller sub-system under wakeup domain | ||
186 | */ | ||
187 | static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { | ||
188 | .name = "wkup_m3", | ||
189 | }; | ||
190 | |||
191 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | 81 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { |
192 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | 82 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, |
193 | }; | 83 | }; |
@@ -213,78 +103,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { | |||
213 | }; | 103 | }; |
214 | 104 | ||
215 | /* | 105 | /* |
216 | * 'pru-icss' class | ||
217 | * Programmable Real-Time Unit and Industrial Communication Subsystem | ||
218 | */ | ||
219 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { | ||
220 | .name = "pruss", | ||
221 | }; | ||
222 | |||
223 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | ||
224 | { .name = "pruss", .rst_shift = 1 }, | ||
225 | }; | ||
226 | |||
227 | /* pru-icss */ | ||
228 | /* Pseudo hwmod for reset control purpose only */ | ||
229 | static struct omap_hwmod am33xx_pruss_hwmod = { | ||
230 | .name = "pruss", | ||
231 | .class = &am33xx_pruss_hwmod_class, | ||
232 | .clkdm_name = "pruss_ocp_clkdm", | ||
233 | .main_clk = "pruss_ocp_gclk", | ||
234 | .prcm = { | ||
235 | .omap4 = { | ||
236 | .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, | ||
237 | .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, | ||
238 | .modulemode = MODULEMODE_SWCTRL, | ||
239 | }, | ||
240 | }, | ||
241 | .rst_lines = am33xx_pruss_resets, | ||
242 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), | ||
243 | }; | ||
244 | |||
245 | /* gfx */ | ||
246 | /* Pseudo hwmod for reset control purpose only */ | ||
247 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { | ||
248 | .name = "gfx", | ||
249 | }; | ||
250 | |||
251 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | ||
252 | { .name = "gfx", .rst_shift = 0, .st_shift = 0}, | ||
253 | }; | ||
254 | |||
255 | static struct omap_hwmod am33xx_gfx_hwmod = { | ||
256 | .name = "gfx", | ||
257 | .class = &am33xx_gfx_hwmod_class, | ||
258 | .clkdm_name = "gfx_l3_clkdm", | ||
259 | .main_clk = "gfx_fck_div_ck", | ||
260 | .prcm = { | ||
261 | .omap4 = { | ||
262 | .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, | ||
263 | .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, | ||
264 | .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, | ||
265 | .modulemode = MODULEMODE_SWCTRL, | ||
266 | }, | ||
267 | }, | ||
268 | .rst_lines = am33xx_gfx_resets, | ||
269 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), | ||
270 | }; | ||
271 | |||
272 | /* | ||
273 | * 'prcm' class | ||
274 | * power and reset manager (whole prcm infrastructure) | ||
275 | */ | ||
276 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { | ||
277 | .name = "prcm", | ||
278 | }; | ||
279 | |||
280 | /* prcm */ | ||
281 | static struct omap_hwmod am33xx_prcm_hwmod = { | ||
282 | .name = "prcm", | ||
283 | .class = &am33xx_prcm_hwmod_class, | ||
284 | .clkdm_name = "l4_wkup_clkdm", | ||
285 | }; | ||
286 | |||
287 | /* | ||
288 | * 'adc/tsc' class | 106 | * 'adc/tsc' class |
289 | * TouchScreen Controller (Anolog-To-Digital Converter) | 107 | * TouchScreen Controller (Anolog-To-Digital Converter) |
290 | */ | 108 | */ |
@@ -388,79 +206,6 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { | |||
388 | #endif | 206 | #endif |
389 | 207 | ||
390 | /* | 208 | /* |
391 | * 'aes0' class | ||
392 | */ | ||
393 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { | ||
394 | .rev_offs = 0x80, | ||
395 | .sysc_offs = 0x84, | ||
396 | .syss_offs = 0x88, | ||
397 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
398 | }; | ||
399 | |||
400 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | ||
401 | .name = "aes0", | ||
402 | .sysc = &am33xx_aes0_sysc, | ||
403 | }; | ||
404 | |||
405 | static struct omap_hwmod am33xx_aes0_hwmod = { | ||
406 | .name = "aes", | ||
407 | .class = &am33xx_aes0_hwmod_class, | ||
408 | .clkdm_name = "l3_clkdm", | ||
409 | .main_clk = "aes0_fck", | ||
410 | .prcm = { | ||
411 | .omap4 = { | ||
412 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, | ||
413 | .modulemode = MODULEMODE_SWCTRL, | ||
414 | }, | ||
415 | }, | ||
416 | }; | ||
417 | |||
418 | /* sha0 HIB2 (the 'P' (public) device) */ | ||
419 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { | ||
420 | .rev_offs = 0x100, | ||
421 | .sysc_offs = 0x110, | ||
422 | .syss_offs = 0x114, | ||
423 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
424 | }; | ||
425 | |||
426 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { | ||
427 | .name = "sha0", | ||
428 | .sysc = &am33xx_sha0_sysc, | ||
429 | }; | ||
430 | |||
431 | static struct omap_hwmod am33xx_sha0_hwmod = { | ||
432 | .name = "sham", | ||
433 | .class = &am33xx_sha0_hwmod_class, | ||
434 | .clkdm_name = "l3_clkdm", | ||
435 | .main_clk = "l3_gclk", | ||
436 | .prcm = { | ||
437 | .omap4 = { | ||
438 | .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, | ||
439 | .modulemode = MODULEMODE_SWCTRL, | ||
440 | }, | ||
441 | }, | ||
442 | }; | ||
443 | |||
444 | /* ocmcram */ | ||
445 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | ||
446 | .name = "ocmcram", | ||
447 | }; | ||
448 | |||
449 | static struct omap_hwmod am33xx_ocmcram_hwmod = { | ||
450 | .name = "ocmcram", | ||
451 | .class = &am33xx_ocmcram_hwmod_class, | ||
452 | .clkdm_name = "l3_clkdm", | ||
453 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
454 | .main_clk = "l3_gclk", | ||
455 | .prcm = { | ||
456 | .omap4 = { | ||
457 | .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, | ||
458 | .modulemode = MODULEMODE_SWCTRL, | ||
459 | }, | ||
460 | }, | ||
461 | }; | ||
462 | |||
463 | /* | ||
464 | * 'debugss' class | 209 | * 'debugss' class |
465 | * debug sub system | 210 | * debug sub system |
466 | */ | 211 | */ |
@@ -488,51 +233,11 @@ static struct omap_hwmod am33xx_debugss_hwmod = { | |||
488 | .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), | 233 | .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), |
489 | }; | 234 | }; |
490 | 235 | ||
491 | /* 'smartreflex' class */ | ||
492 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | ||
493 | .name = "smartreflex", | ||
494 | }; | ||
495 | |||
496 | /* smartreflex0 */ | ||
497 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { | ||
498 | .name = "smartreflex0", | ||
499 | .class = &am33xx_smartreflex_hwmod_class, | ||
500 | .clkdm_name = "l4_wkup_clkdm", | ||
501 | .main_clk = "smartreflex0_fck", | ||
502 | .prcm = { | ||
503 | .omap4 = { | ||
504 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, | ||
505 | .modulemode = MODULEMODE_SWCTRL, | ||
506 | }, | ||
507 | }, | ||
508 | }; | ||
509 | |||
510 | /* smartreflex1 */ | ||
511 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { | ||
512 | .name = "smartreflex1", | ||
513 | .class = &am33xx_smartreflex_hwmod_class, | ||
514 | .clkdm_name = "l4_wkup_clkdm", | ||
515 | .main_clk = "smartreflex1_fck", | ||
516 | .prcm = { | ||
517 | .omap4 = { | ||
518 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, | ||
519 | .modulemode = MODULEMODE_SWCTRL, | ||
520 | }, | ||
521 | }, | ||
522 | }; | ||
523 | |||
524 | /* | ||
525 | * 'control' module class | ||
526 | */ | ||
527 | static struct omap_hwmod_class am33xx_control_hwmod_class = { | ||
528 | .name = "control", | ||
529 | }; | ||
530 | |||
531 | static struct omap_hwmod am33xx_control_hwmod = { | 236 | static struct omap_hwmod am33xx_control_hwmod = { |
532 | .name = "control", | 237 | .name = "control", |
533 | .class = &am33xx_control_hwmod_class, | 238 | .class = &am33xx_control_hwmod_class, |
534 | .clkdm_name = "l4_wkup_clkdm", | 239 | .clkdm_name = "l4_wkup_clkdm", |
535 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | 240 | .flags = HWMOD_INIT_NO_IDLE, |
536 | .main_clk = "dpll_core_m4_div2_ck", | 241 | .main_clk = "dpll_core_m4_div2_ck", |
537 | .prcm = { | 242 | .prcm = { |
538 | .omap4 = { | 243 | .omap4 = { |
@@ -542,288 +247,6 @@ static struct omap_hwmod am33xx_control_hwmod = { | |||
542 | }, | 247 | }, |
543 | }; | 248 | }; |
544 | 249 | ||
545 | /* | ||
546 | * 'cpgmac' class | ||
547 | * cpsw/cpgmac sub system | ||
548 | */ | ||
549 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { | ||
550 | .rev_offs = 0x0, | ||
551 | .sysc_offs = 0x8, | ||
552 | .syss_offs = 0x4, | ||
553 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | ||
554 | SYSS_HAS_RESET_STATUS), | ||
555 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | ||
556 | MSTANDBY_NO), | ||
557 | .sysc_fields = &omap_hwmod_sysc_type3, | ||
558 | }; | ||
559 | |||
560 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | ||
561 | .name = "cpgmac0", | ||
562 | .sysc = &am33xx_cpgmac_sysc, | ||
563 | }; | ||
564 | |||
565 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { | ||
566 | .name = "cpgmac0", | ||
567 | .class = &am33xx_cpgmac0_hwmod_class, | ||
568 | .clkdm_name = "cpsw_125mhz_clkdm", | ||
569 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | ||
570 | .main_clk = "cpsw_125mhz_gclk", | ||
571 | .mpu_rt_idx = 1, | ||
572 | .prcm = { | ||
573 | .omap4 = { | ||
574 | .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, | ||
575 | .modulemode = MODULEMODE_SWCTRL, | ||
576 | }, | ||
577 | }, | ||
578 | }; | ||
579 | |||
580 | /* | ||
581 | * mdio class | ||
582 | */ | ||
583 | static struct omap_hwmod_class am33xx_mdio_hwmod_class = { | ||
584 | .name = "davinci_mdio", | ||
585 | }; | ||
586 | |||
587 | static struct omap_hwmod am33xx_mdio_hwmod = { | ||
588 | .name = "davinci_mdio", | ||
589 | .class = &am33xx_mdio_hwmod_class, | ||
590 | .clkdm_name = "cpsw_125mhz_clkdm", | ||
591 | .main_clk = "cpsw_125mhz_gclk", | ||
592 | }; | ||
593 | |||
594 | /* | ||
595 | * dcan class | ||
596 | */ | ||
597 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | ||
598 | .name = "d_can", | ||
599 | }; | ||
600 | |||
601 | /* dcan0 */ | ||
602 | static struct omap_hwmod am33xx_dcan0_hwmod = { | ||
603 | .name = "d_can0", | ||
604 | .class = &am33xx_dcan_hwmod_class, | ||
605 | .clkdm_name = "l4ls_clkdm", | ||
606 | .main_clk = "dcan0_fck", | ||
607 | .prcm = { | ||
608 | .omap4 = { | ||
609 | .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, | ||
610 | .modulemode = MODULEMODE_SWCTRL, | ||
611 | }, | ||
612 | }, | ||
613 | }; | ||
614 | |||
615 | /* dcan1 */ | ||
616 | static struct omap_hwmod am33xx_dcan1_hwmod = { | ||
617 | .name = "d_can1", | ||
618 | .class = &am33xx_dcan_hwmod_class, | ||
619 | .clkdm_name = "l4ls_clkdm", | ||
620 | .main_clk = "dcan1_fck", | ||
621 | .prcm = { | ||
622 | .omap4 = { | ||
623 | .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, | ||
624 | .modulemode = MODULEMODE_SWCTRL, | ||
625 | }, | ||
626 | }, | ||
627 | }; | ||
628 | |||
629 | /* elm */ | ||
630 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { | ||
631 | .rev_offs = 0x0000, | ||
632 | .sysc_offs = 0x0010, | ||
633 | .syss_offs = 0x0014, | ||
634 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
635 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
636 | SYSS_HAS_RESET_STATUS), | ||
637 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
638 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
639 | }; | ||
640 | |||
641 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { | ||
642 | .name = "elm", | ||
643 | .sysc = &am33xx_elm_sysc, | ||
644 | }; | ||
645 | |||
646 | static struct omap_hwmod am33xx_elm_hwmod = { | ||
647 | .name = "elm", | ||
648 | .class = &am33xx_elm_hwmod_class, | ||
649 | .clkdm_name = "l4ls_clkdm", | ||
650 | .main_clk = "l4ls_gclk", | ||
651 | .prcm = { | ||
652 | .omap4 = { | ||
653 | .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, | ||
654 | .modulemode = MODULEMODE_SWCTRL, | ||
655 | }, | ||
656 | }, | ||
657 | }; | ||
658 | |||
659 | /* pwmss */ | ||
660 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { | ||
661 | .rev_offs = 0x0, | ||
662 | .sysc_offs = 0x4, | ||
663 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | ||
664 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
665 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | ||
666 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | ||
667 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
668 | }; | ||
669 | |||
670 | static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { | ||
671 | .name = "epwmss", | ||
672 | .sysc = &am33xx_epwmss_sysc, | ||
673 | }; | ||
674 | |||
675 | static struct omap_hwmod_class am33xx_ecap_hwmod_class = { | ||
676 | .name = "ecap", | ||
677 | }; | ||
678 | |||
679 | static struct omap_hwmod_class am33xx_eqep_hwmod_class = { | ||
680 | .name = "eqep", | ||
681 | }; | ||
682 | |||
683 | static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { | ||
684 | .name = "ehrpwm", | ||
685 | }; | ||
686 | |||
687 | /* epwmss0 */ | ||
688 | static struct omap_hwmod am33xx_epwmss0_hwmod = { | ||
689 | .name = "epwmss0", | ||
690 | .class = &am33xx_epwmss_hwmod_class, | ||
691 | .clkdm_name = "l4ls_clkdm", | ||
692 | .main_clk = "l4ls_gclk", | ||
693 | .prcm = { | ||
694 | .omap4 = { | ||
695 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, | ||
696 | .modulemode = MODULEMODE_SWCTRL, | ||
697 | }, | ||
698 | }, | ||
699 | }; | ||
700 | |||
701 | /* ecap0 */ | ||
702 | static struct omap_hwmod am33xx_ecap0_hwmod = { | ||
703 | .name = "ecap0", | ||
704 | .class = &am33xx_ecap_hwmod_class, | ||
705 | .clkdm_name = "l4ls_clkdm", | ||
706 | .main_clk = "l4ls_gclk", | ||
707 | }; | ||
708 | |||
709 | /* eqep0 */ | ||
710 | static struct omap_hwmod am33xx_eqep0_hwmod = { | ||
711 | .name = "eqep0", | ||
712 | .class = &am33xx_eqep_hwmod_class, | ||
713 | .clkdm_name = "l4ls_clkdm", | ||
714 | .main_clk = "l4ls_gclk", | ||
715 | }; | ||
716 | |||
717 | /* ehrpwm0 */ | ||
718 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { | ||
719 | .name = "ehrpwm0", | ||
720 | .class = &am33xx_ehrpwm_hwmod_class, | ||
721 | .clkdm_name = "l4ls_clkdm", | ||
722 | .main_clk = "l4ls_gclk", | ||
723 | }; | ||
724 | |||
725 | /* epwmss1 */ | ||
726 | static struct omap_hwmod am33xx_epwmss1_hwmod = { | ||
727 | .name = "epwmss1", | ||
728 | .class = &am33xx_epwmss_hwmod_class, | ||
729 | .clkdm_name = "l4ls_clkdm", | ||
730 | .main_clk = "l4ls_gclk", | ||
731 | .prcm = { | ||
732 | .omap4 = { | ||
733 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, | ||
734 | .modulemode = MODULEMODE_SWCTRL, | ||
735 | }, | ||
736 | }, | ||
737 | }; | ||
738 | |||
739 | /* ecap1 */ | ||
740 | static struct omap_hwmod am33xx_ecap1_hwmod = { | ||
741 | .name = "ecap1", | ||
742 | .class = &am33xx_ecap_hwmod_class, | ||
743 | .clkdm_name = "l4ls_clkdm", | ||
744 | .main_clk = "l4ls_gclk", | ||
745 | }; | ||
746 | |||
747 | /* eqep1 */ | ||
748 | static struct omap_hwmod am33xx_eqep1_hwmod = { | ||
749 | .name = "eqep1", | ||
750 | .class = &am33xx_eqep_hwmod_class, | ||
751 | .clkdm_name = "l4ls_clkdm", | ||
752 | .main_clk = "l4ls_gclk", | ||
753 | }; | ||
754 | |||
755 | /* ehrpwm1 */ | ||
756 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { | ||
757 | .name = "ehrpwm1", | ||
758 | .class = &am33xx_ehrpwm_hwmod_class, | ||
759 | .clkdm_name = "l4ls_clkdm", | ||
760 | .main_clk = "l4ls_gclk", | ||
761 | }; | ||
762 | |||
763 | /* epwmss2 */ | ||
764 | static struct omap_hwmod am33xx_epwmss2_hwmod = { | ||
765 | .name = "epwmss2", | ||
766 | .class = &am33xx_epwmss_hwmod_class, | ||
767 | .clkdm_name = "l4ls_clkdm", | ||
768 | .main_clk = "l4ls_gclk", | ||
769 | .prcm = { | ||
770 | .omap4 = { | ||
771 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, | ||
772 | .modulemode = MODULEMODE_SWCTRL, | ||
773 | }, | ||
774 | }, | ||
775 | }; | ||
776 | |||
777 | /* ecap2 */ | ||
778 | static struct omap_hwmod am33xx_ecap2_hwmod = { | ||
779 | .name = "ecap2", | ||
780 | .class = &am33xx_ecap_hwmod_class, | ||
781 | .clkdm_name = "l4ls_clkdm", | ||
782 | .main_clk = "l4ls_gclk", | ||
783 | }; | ||
784 | |||
785 | /* eqep2 */ | ||
786 | static struct omap_hwmod am33xx_eqep2_hwmod = { | ||
787 | .name = "eqep2", | ||
788 | .class = &am33xx_eqep_hwmod_class, | ||
789 | .clkdm_name = "l4ls_clkdm", | ||
790 | .main_clk = "l4ls_gclk", | ||
791 | }; | ||
792 | |||
793 | /* ehrpwm2 */ | ||
794 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { | ||
795 | .name = "ehrpwm2", | ||
796 | .class = &am33xx_ehrpwm_hwmod_class, | ||
797 | .clkdm_name = "l4ls_clkdm", | ||
798 | .main_clk = "l4ls_gclk", | ||
799 | }; | ||
800 | |||
801 | /* | ||
802 | * 'gpio' class: for gpio 0,1,2,3 | ||
803 | */ | ||
804 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { | ||
805 | .rev_offs = 0x0000, | ||
806 | .sysc_offs = 0x0010, | ||
807 | .syss_offs = 0x0114, | ||
808 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | ||
809 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
810 | SYSS_HAS_RESET_STATUS), | ||
811 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
812 | SIDLE_SMART_WKUP), | ||
813 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
814 | }; | ||
815 | |||
816 | static struct omap_hwmod_class am33xx_gpio_hwmod_class = { | ||
817 | .name = "gpio", | ||
818 | .sysc = &am33xx_gpio_sysc, | ||
819 | .rev = 2, | ||
820 | }; | ||
821 | |||
822 | static struct omap_gpio_dev_attr gpio_dev_attr = { | ||
823 | .bank_width = 32, | ||
824 | .dbck_flag = true, | ||
825 | }; | ||
826 | |||
827 | /* gpio0 */ | 250 | /* gpio0 */ |
828 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | 251 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { |
829 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | 252 | { .role = "dbclk", .clk = "gpio0_dbclk" }, |
@@ -846,174 +269,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = { | |||
846 | .dev_attr = &gpio_dev_attr, | 269 | .dev_attr = &gpio_dev_attr, |
847 | }; | 270 | }; |
848 | 271 | ||
849 | /* gpio1 */ | ||
850 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | ||
851 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | ||
852 | }; | ||
853 | |||
854 | static struct omap_hwmod am33xx_gpio1_hwmod = { | ||
855 | .name = "gpio2", | ||
856 | .class = &am33xx_gpio_hwmod_class, | ||
857 | .clkdm_name = "l4ls_clkdm", | ||
858 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
859 | .main_clk = "l4ls_gclk", | ||
860 | .prcm = { | ||
861 | .omap4 = { | ||
862 | .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, | ||
863 | .modulemode = MODULEMODE_SWCTRL, | ||
864 | }, | ||
865 | }, | ||
866 | .opt_clks = gpio1_opt_clks, | ||
867 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | ||
868 | .dev_attr = &gpio_dev_attr, | ||
869 | }; | ||
870 | |||
871 | /* gpio2 */ | ||
872 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | ||
873 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | ||
874 | }; | ||
875 | |||
876 | static struct omap_hwmod am33xx_gpio2_hwmod = { | ||
877 | .name = "gpio3", | ||
878 | .class = &am33xx_gpio_hwmod_class, | ||
879 | .clkdm_name = "l4ls_clkdm", | ||
880 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
881 | .main_clk = "l4ls_gclk", | ||
882 | .prcm = { | ||
883 | .omap4 = { | ||
884 | .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, | ||
885 | .modulemode = MODULEMODE_SWCTRL, | ||
886 | }, | ||
887 | }, | ||
888 | .opt_clks = gpio2_opt_clks, | ||
889 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | ||
890 | .dev_attr = &gpio_dev_attr, | ||
891 | }; | ||
892 | |||
893 | /* gpio3 */ | ||
894 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | ||
895 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | ||
896 | }; | ||
897 | |||
898 | static struct omap_hwmod am33xx_gpio3_hwmod = { | ||
899 | .name = "gpio4", | ||
900 | .class = &am33xx_gpio_hwmod_class, | ||
901 | .clkdm_name = "l4ls_clkdm", | ||
902 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
903 | .main_clk = "l4ls_gclk", | ||
904 | .prcm = { | ||
905 | .omap4 = { | ||
906 | .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, | ||
907 | .modulemode = MODULEMODE_SWCTRL, | ||
908 | }, | ||
909 | }, | ||
910 | .opt_clks = gpio3_opt_clks, | ||
911 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | ||
912 | .dev_attr = &gpio_dev_attr, | ||
913 | }; | ||
914 | |||
915 | /* gpmc */ | ||
916 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { | ||
917 | .rev_offs = 0x0, | ||
918 | .sysc_offs = 0x10, | ||
919 | .syss_offs = 0x14, | ||
920 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | ||
921 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
922 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
923 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
924 | }; | ||
925 | |||
926 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | ||
927 | .name = "gpmc", | ||
928 | .sysc = &gpmc_sysc, | ||
929 | }; | ||
930 | |||
931 | static struct omap_hwmod am33xx_gpmc_hwmod = { | ||
932 | .name = "gpmc", | ||
933 | .class = &am33xx_gpmc_hwmod_class, | ||
934 | .clkdm_name = "l3s_clkdm", | ||
935 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
936 | .main_clk = "l3s_gclk", | ||
937 | .prcm = { | ||
938 | .omap4 = { | ||
939 | .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, | ||
940 | .modulemode = MODULEMODE_SWCTRL, | ||
941 | }, | ||
942 | }, | ||
943 | }; | ||
944 | |||
945 | /* 'i2c' class */ | ||
946 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { | ||
947 | .sysc_offs = 0x0010, | ||
948 | .syss_offs = 0x0090, | ||
949 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
950 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
951 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
952 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
953 | SIDLE_SMART_WKUP), | ||
954 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
955 | }; | ||
956 | |||
957 | static struct omap_hwmod_class i2c_class = { | ||
958 | .name = "i2c", | ||
959 | .sysc = &am33xx_i2c_sysc, | ||
960 | .rev = OMAP_I2C_IP_VERSION_2, | ||
961 | .reset = &omap_i2c_reset, | ||
962 | }; | ||
963 | |||
964 | static struct omap_i2c_dev_attr i2c_dev_attr = { | ||
965 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | ||
966 | }; | ||
967 | |||
968 | /* i2c1 */ | ||
969 | static struct omap_hwmod am33xx_i2c1_hwmod = { | ||
970 | .name = "i2c1", | ||
971 | .class = &i2c_class, | ||
972 | .clkdm_name = "l4_wkup_clkdm", | ||
973 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | ||
974 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | ||
975 | .prcm = { | ||
976 | .omap4 = { | ||
977 | .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, | ||
978 | .modulemode = MODULEMODE_SWCTRL, | ||
979 | }, | ||
980 | }, | ||
981 | .dev_attr = &i2c_dev_attr, | ||
982 | }; | ||
983 | |||
984 | /* i2c1 */ | ||
985 | static struct omap_hwmod am33xx_i2c2_hwmod = { | ||
986 | .name = "i2c2", | ||
987 | .class = &i2c_class, | ||
988 | .clkdm_name = "l4ls_clkdm", | ||
989 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | ||
990 | .main_clk = "dpll_per_m2_div4_ck", | ||
991 | .prcm = { | ||
992 | .omap4 = { | ||
993 | .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, | ||
994 | .modulemode = MODULEMODE_SWCTRL, | ||
995 | }, | ||
996 | }, | ||
997 | .dev_attr = &i2c_dev_attr, | ||
998 | }; | ||
999 | |||
1000 | /* i2c3 */ | ||
1001 | static struct omap_hwmod am33xx_i2c3_hwmod = { | ||
1002 | .name = "i2c3", | ||
1003 | .class = &i2c_class, | ||
1004 | .clkdm_name = "l4ls_clkdm", | ||
1005 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | ||
1006 | .main_clk = "dpll_per_m2_div4_ck", | ||
1007 | .prcm = { | ||
1008 | .omap4 = { | ||
1009 | .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, | ||
1010 | .modulemode = MODULEMODE_SWCTRL, | ||
1011 | }, | ||
1012 | }, | ||
1013 | .dev_attr = &i2c_dev_attr, | ||
1014 | }; | ||
1015 | |||
1016 | |||
1017 | /* lcdc */ | 272 | /* lcdc */ |
1018 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { | 273 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { |
1019 | .rev_offs = 0x0, | 274 | .rev_offs = 0x0, |
@@ -1043,600 +298,6 @@ static struct omap_hwmod am33xx_lcdc_hwmod = { | |||
1043 | }; | 298 | }; |
1044 | 299 | ||
1045 | /* | 300 | /* |
1046 | * 'mailbox' class | ||
1047 | * mailbox module allowing communication between the on-chip processors using a | ||
1048 | * queued mailbox-interrupt mechanism. | ||
1049 | */ | ||
1050 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { | ||
1051 | .rev_offs = 0x0000, | ||
1052 | .sysc_offs = 0x0010, | ||
1053 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | ||
1054 | SYSC_HAS_SOFTRESET), | ||
1055 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1056 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
1057 | }; | ||
1058 | |||
1059 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | ||
1060 | .name = "mailbox", | ||
1061 | .sysc = &am33xx_mailbox_sysc, | ||
1062 | }; | ||
1063 | |||
1064 | static struct omap_hwmod am33xx_mailbox_hwmod = { | ||
1065 | .name = "mailbox", | ||
1066 | .class = &am33xx_mailbox_hwmod_class, | ||
1067 | .clkdm_name = "l4ls_clkdm", | ||
1068 | .main_clk = "l4ls_gclk", | ||
1069 | .prcm = { | ||
1070 | .omap4 = { | ||
1071 | .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, | ||
1072 | .modulemode = MODULEMODE_SWCTRL, | ||
1073 | }, | ||
1074 | }, | ||
1075 | }; | ||
1076 | |||
1077 | /* | ||
1078 | * 'mcasp' class | ||
1079 | */ | ||
1080 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { | ||
1081 | .rev_offs = 0x0, | ||
1082 | .sysc_offs = 0x4, | ||
1083 | .sysc_flags = SYSC_HAS_SIDLEMODE, | ||
1084 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1085 | .sysc_fields = &omap_hwmod_sysc_type3, | ||
1086 | }; | ||
1087 | |||
1088 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | ||
1089 | .name = "mcasp", | ||
1090 | .sysc = &am33xx_mcasp_sysc, | ||
1091 | }; | ||
1092 | |||
1093 | /* mcasp0 */ | ||
1094 | static struct omap_hwmod am33xx_mcasp0_hwmod = { | ||
1095 | .name = "mcasp0", | ||
1096 | .class = &am33xx_mcasp_hwmod_class, | ||
1097 | .clkdm_name = "l3s_clkdm", | ||
1098 | .main_clk = "mcasp0_fck", | ||
1099 | .prcm = { | ||
1100 | .omap4 = { | ||
1101 | .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, | ||
1102 | .modulemode = MODULEMODE_SWCTRL, | ||
1103 | }, | ||
1104 | }, | ||
1105 | }; | ||
1106 | |||
1107 | /* mcasp1 */ | ||
1108 | static struct omap_hwmod am33xx_mcasp1_hwmod = { | ||
1109 | .name = "mcasp1", | ||
1110 | .class = &am33xx_mcasp_hwmod_class, | ||
1111 | .clkdm_name = "l3s_clkdm", | ||
1112 | .main_clk = "mcasp1_fck", | ||
1113 | .prcm = { | ||
1114 | .omap4 = { | ||
1115 | .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, | ||
1116 | .modulemode = MODULEMODE_SWCTRL, | ||
1117 | }, | ||
1118 | }, | ||
1119 | }; | ||
1120 | |||
1121 | /* 'mmc' class */ | ||
1122 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { | ||
1123 | .rev_offs = 0x1fc, | ||
1124 | .sysc_offs = 0x10, | ||
1125 | .syss_offs = 0x14, | ||
1126 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
1127 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | ||
1128 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | ||
1129 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1130 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1131 | }; | ||
1132 | |||
1133 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | ||
1134 | .name = "mmc", | ||
1135 | .sysc = &am33xx_mmc_sysc, | ||
1136 | }; | ||
1137 | |||
1138 | /* mmc0 */ | ||
1139 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { | ||
1140 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | ||
1141 | }; | ||
1142 | |||
1143 | static struct omap_hwmod am33xx_mmc0_hwmod = { | ||
1144 | .name = "mmc1", | ||
1145 | .class = &am33xx_mmc_hwmod_class, | ||
1146 | .clkdm_name = "l4ls_clkdm", | ||
1147 | .main_clk = "mmc_clk", | ||
1148 | .prcm = { | ||
1149 | .omap4 = { | ||
1150 | .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, | ||
1151 | .modulemode = MODULEMODE_SWCTRL, | ||
1152 | }, | ||
1153 | }, | ||
1154 | .dev_attr = &am33xx_mmc0_dev_attr, | ||
1155 | }; | ||
1156 | |||
1157 | /* mmc1 */ | ||
1158 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { | ||
1159 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | ||
1160 | }; | ||
1161 | |||
1162 | static struct omap_hwmod am33xx_mmc1_hwmod = { | ||
1163 | .name = "mmc2", | ||
1164 | .class = &am33xx_mmc_hwmod_class, | ||
1165 | .clkdm_name = "l4ls_clkdm", | ||
1166 | .main_clk = "mmc_clk", | ||
1167 | .prcm = { | ||
1168 | .omap4 = { | ||
1169 | .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, | ||
1170 | .modulemode = MODULEMODE_SWCTRL, | ||
1171 | }, | ||
1172 | }, | ||
1173 | .dev_attr = &am33xx_mmc1_dev_attr, | ||
1174 | }; | ||
1175 | |||
1176 | /* mmc2 */ | ||
1177 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { | ||
1178 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | ||
1179 | }; | ||
1180 | static struct omap_hwmod am33xx_mmc2_hwmod = { | ||
1181 | .name = "mmc3", | ||
1182 | .class = &am33xx_mmc_hwmod_class, | ||
1183 | .clkdm_name = "l3s_clkdm", | ||
1184 | .main_clk = "mmc_clk", | ||
1185 | .prcm = { | ||
1186 | .omap4 = { | ||
1187 | .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, | ||
1188 | .modulemode = MODULEMODE_SWCTRL, | ||
1189 | }, | ||
1190 | }, | ||
1191 | .dev_attr = &am33xx_mmc2_dev_attr, | ||
1192 | }; | ||
1193 | |||
1194 | /* | ||
1195 | * 'rtc' class | ||
1196 | * rtc subsystem | ||
1197 | */ | ||
1198 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { | ||
1199 | .rev_offs = 0x0074, | ||
1200 | .sysc_offs = 0x0078, | ||
1201 | .sysc_flags = SYSC_HAS_SIDLEMODE, | ||
1202 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | | ||
1203 | SIDLE_SMART | SIDLE_SMART_WKUP), | ||
1204 | .sysc_fields = &omap_hwmod_sysc_type3, | ||
1205 | }; | ||
1206 | |||
1207 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | ||
1208 | .name = "rtc", | ||
1209 | .sysc = &am33xx_rtc_sysc, | ||
1210 | }; | ||
1211 | |||
1212 | static struct omap_hwmod am33xx_rtc_hwmod = { | ||
1213 | .name = "rtc", | ||
1214 | .class = &am33xx_rtc_hwmod_class, | ||
1215 | .clkdm_name = "l4_rtc_clkdm", | ||
1216 | .main_clk = "clk_32768_ck", | ||
1217 | .prcm = { | ||
1218 | .omap4 = { | ||
1219 | .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, | ||
1220 | .modulemode = MODULEMODE_SWCTRL, | ||
1221 | }, | ||
1222 | }, | ||
1223 | }; | ||
1224 | |||
1225 | /* 'spi' class */ | ||
1226 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { | ||
1227 | .rev_offs = 0x0000, | ||
1228 | .sysc_offs = 0x0110, | ||
1229 | .syss_offs = 0x0114, | ||
1230 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
1231 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
1232 | SYSS_HAS_RESET_STATUS), | ||
1233 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1234 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1235 | }; | ||
1236 | |||
1237 | static struct omap_hwmod_class am33xx_spi_hwmod_class = { | ||
1238 | .name = "mcspi", | ||
1239 | .sysc = &am33xx_mcspi_sysc, | ||
1240 | .rev = OMAP4_MCSPI_REV, | ||
1241 | }; | ||
1242 | |||
1243 | /* spi0 */ | ||
1244 | static struct omap2_mcspi_dev_attr mcspi_attrib = { | ||
1245 | .num_chipselect = 2, | ||
1246 | }; | ||
1247 | static struct omap_hwmod am33xx_spi0_hwmod = { | ||
1248 | .name = "spi0", | ||
1249 | .class = &am33xx_spi_hwmod_class, | ||
1250 | .clkdm_name = "l4ls_clkdm", | ||
1251 | .main_clk = "dpll_per_m2_div4_ck", | ||
1252 | .prcm = { | ||
1253 | .omap4 = { | ||
1254 | .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, | ||
1255 | .modulemode = MODULEMODE_SWCTRL, | ||
1256 | }, | ||
1257 | }, | ||
1258 | .dev_attr = &mcspi_attrib, | ||
1259 | }; | ||
1260 | |||
1261 | /* spi1 */ | ||
1262 | static struct omap_hwmod am33xx_spi1_hwmod = { | ||
1263 | .name = "spi1", | ||
1264 | .class = &am33xx_spi_hwmod_class, | ||
1265 | .clkdm_name = "l4ls_clkdm", | ||
1266 | .main_clk = "dpll_per_m2_div4_ck", | ||
1267 | .prcm = { | ||
1268 | .omap4 = { | ||
1269 | .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, | ||
1270 | .modulemode = MODULEMODE_SWCTRL, | ||
1271 | }, | ||
1272 | }, | ||
1273 | .dev_attr = &mcspi_attrib, | ||
1274 | }; | ||
1275 | |||
1276 | /* | ||
1277 | * 'spinlock' class | ||
1278 | * spinlock provides hardware assistance for synchronizing the | ||
1279 | * processes running on multiple processors | ||
1280 | */ | ||
1281 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { | ||
1282 | .name = "spinlock", | ||
1283 | }; | ||
1284 | |||
1285 | static struct omap_hwmod am33xx_spinlock_hwmod = { | ||
1286 | .name = "spinlock", | ||
1287 | .class = &am33xx_spinlock_hwmod_class, | ||
1288 | .clkdm_name = "l4ls_clkdm", | ||
1289 | .main_clk = "l4ls_gclk", | ||
1290 | .prcm = { | ||
1291 | .omap4 = { | ||
1292 | .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, | ||
1293 | .modulemode = MODULEMODE_SWCTRL, | ||
1294 | }, | ||
1295 | }, | ||
1296 | }; | ||
1297 | |||
1298 | /* 'timer 2-7' class */ | ||
1299 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { | ||
1300 | .rev_offs = 0x0000, | ||
1301 | .sysc_offs = 0x0010, | ||
1302 | .syss_offs = 0x0014, | ||
1303 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | ||
1304 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1305 | SIDLE_SMART_WKUP), | ||
1306 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
1307 | }; | ||
1308 | |||
1309 | static struct omap_hwmod_class am33xx_timer_hwmod_class = { | ||
1310 | .name = "timer", | ||
1311 | .sysc = &am33xx_timer_sysc, | ||
1312 | }; | ||
1313 | |||
1314 | /* timer1 1ms */ | ||
1315 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { | ||
1316 | .rev_offs = 0x0000, | ||
1317 | .sysc_offs = 0x0010, | ||
1318 | .syss_offs = 0x0014, | ||
1319 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
1320 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | ||
1321 | SYSS_HAS_RESET_STATUS), | ||
1322 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1323 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1324 | }; | ||
1325 | |||
1326 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | ||
1327 | .name = "timer", | ||
1328 | .sysc = &am33xx_timer1ms_sysc, | ||
1329 | }; | ||
1330 | |||
1331 | static struct omap_hwmod am33xx_timer1_hwmod = { | ||
1332 | .name = "timer1", | ||
1333 | .class = &am33xx_timer1ms_hwmod_class, | ||
1334 | .clkdm_name = "l4_wkup_clkdm", | ||
1335 | .main_clk = "timer1_fck", | ||
1336 | .prcm = { | ||
1337 | .omap4 = { | ||
1338 | .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, | ||
1339 | .modulemode = MODULEMODE_SWCTRL, | ||
1340 | }, | ||
1341 | }, | ||
1342 | }; | ||
1343 | |||
1344 | static struct omap_hwmod am33xx_timer2_hwmod = { | ||
1345 | .name = "timer2", | ||
1346 | .class = &am33xx_timer_hwmod_class, | ||
1347 | .clkdm_name = "l4ls_clkdm", | ||
1348 | .main_clk = "timer2_fck", | ||
1349 | .prcm = { | ||
1350 | .omap4 = { | ||
1351 | .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, | ||
1352 | .modulemode = MODULEMODE_SWCTRL, | ||
1353 | }, | ||
1354 | }, | ||
1355 | }; | ||
1356 | |||
1357 | static struct omap_hwmod am33xx_timer3_hwmod = { | ||
1358 | .name = "timer3", | ||
1359 | .class = &am33xx_timer_hwmod_class, | ||
1360 | .clkdm_name = "l4ls_clkdm", | ||
1361 | .main_clk = "timer3_fck", | ||
1362 | .prcm = { | ||
1363 | .omap4 = { | ||
1364 | .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, | ||
1365 | .modulemode = MODULEMODE_SWCTRL, | ||
1366 | }, | ||
1367 | }, | ||
1368 | }; | ||
1369 | |||
1370 | static struct omap_hwmod am33xx_timer4_hwmod = { | ||
1371 | .name = "timer4", | ||
1372 | .class = &am33xx_timer_hwmod_class, | ||
1373 | .clkdm_name = "l4ls_clkdm", | ||
1374 | .main_clk = "timer4_fck", | ||
1375 | .prcm = { | ||
1376 | .omap4 = { | ||
1377 | .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, | ||
1378 | .modulemode = MODULEMODE_SWCTRL, | ||
1379 | }, | ||
1380 | }, | ||
1381 | }; | ||
1382 | |||
1383 | static struct omap_hwmod am33xx_timer5_hwmod = { | ||
1384 | .name = "timer5", | ||
1385 | .class = &am33xx_timer_hwmod_class, | ||
1386 | .clkdm_name = "l4ls_clkdm", | ||
1387 | .main_clk = "timer5_fck", | ||
1388 | .prcm = { | ||
1389 | .omap4 = { | ||
1390 | .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, | ||
1391 | .modulemode = MODULEMODE_SWCTRL, | ||
1392 | }, | ||
1393 | }, | ||
1394 | }; | ||
1395 | |||
1396 | static struct omap_hwmod am33xx_timer6_hwmod = { | ||
1397 | .name = "timer6", | ||
1398 | .class = &am33xx_timer_hwmod_class, | ||
1399 | .clkdm_name = "l4ls_clkdm", | ||
1400 | .main_clk = "timer6_fck", | ||
1401 | .prcm = { | ||
1402 | .omap4 = { | ||
1403 | .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, | ||
1404 | .modulemode = MODULEMODE_SWCTRL, | ||
1405 | }, | ||
1406 | }, | ||
1407 | }; | ||
1408 | |||
1409 | static struct omap_hwmod am33xx_timer7_hwmod = { | ||
1410 | .name = "timer7", | ||
1411 | .class = &am33xx_timer_hwmod_class, | ||
1412 | .clkdm_name = "l4ls_clkdm", | ||
1413 | .main_clk = "timer7_fck", | ||
1414 | .prcm = { | ||
1415 | .omap4 = { | ||
1416 | .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, | ||
1417 | .modulemode = MODULEMODE_SWCTRL, | ||
1418 | }, | ||
1419 | }, | ||
1420 | }; | ||
1421 | |||
1422 | /* tpcc */ | ||
1423 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | ||
1424 | .name = "tpcc", | ||
1425 | }; | ||
1426 | |||
1427 | static struct omap_hwmod am33xx_tpcc_hwmod = { | ||
1428 | .name = "tpcc", | ||
1429 | .class = &am33xx_tpcc_hwmod_class, | ||
1430 | .clkdm_name = "l3_clkdm", | ||
1431 | .main_clk = "l3_gclk", | ||
1432 | .prcm = { | ||
1433 | .omap4 = { | ||
1434 | .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, | ||
1435 | .modulemode = MODULEMODE_SWCTRL, | ||
1436 | }, | ||
1437 | }, | ||
1438 | }; | ||
1439 | |||
1440 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { | ||
1441 | .rev_offs = 0x0, | ||
1442 | .sysc_offs = 0x10, | ||
1443 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
1444 | SYSC_HAS_MIDLEMODE), | ||
1445 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), | ||
1446 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
1447 | }; | ||
1448 | |||
1449 | /* 'tptc' class */ | ||
1450 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | ||
1451 | .name = "tptc", | ||
1452 | .sysc = &am33xx_tptc_sysc, | ||
1453 | }; | ||
1454 | |||
1455 | /* tptc0 */ | ||
1456 | static struct omap_hwmod am33xx_tptc0_hwmod = { | ||
1457 | .name = "tptc0", | ||
1458 | .class = &am33xx_tptc_hwmod_class, | ||
1459 | .clkdm_name = "l3_clkdm", | ||
1460 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | ||
1461 | .main_clk = "l3_gclk", | ||
1462 | .prcm = { | ||
1463 | .omap4 = { | ||
1464 | .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, | ||
1465 | .modulemode = MODULEMODE_SWCTRL, | ||
1466 | }, | ||
1467 | }, | ||
1468 | }; | ||
1469 | |||
1470 | /* tptc1 */ | ||
1471 | static struct omap_hwmod am33xx_tptc1_hwmod = { | ||
1472 | .name = "tptc1", | ||
1473 | .class = &am33xx_tptc_hwmod_class, | ||
1474 | .clkdm_name = "l3_clkdm", | ||
1475 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | ||
1476 | .main_clk = "l3_gclk", | ||
1477 | .prcm = { | ||
1478 | .omap4 = { | ||
1479 | .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, | ||
1480 | .modulemode = MODULEMODE_SWCTRL, | ||
1481 | }, | ||
1482 | }, | ||
1483 | }; | ||
1484 | |||
1485 | /* tptc2 */ | ||
1486 | static struct omap_hwmod am33xx_tptc2_hwmod = { | ||
1487 | .name = "tptc2", | ||
1488 | .class = &am33xx_tptc_hwmod_class, | ||
1489 | .clkdm_name = "l3_clkdm", | ||
1490 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | ||
1491 | .main_clk = "l3_gclk", | ||
1492 | .prcm = { | ||
1493 | .omap4 = { | ||
1494 | .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, | ||
1495 | .modulemode = MODULEMODE_SWCTRL, | ||
1496 | }, | ||
1497 | }, | ||
1498 | }; | ||
1499 | |||
1500 | /* 'uart' class */ | ||
1501 | static struct omap_hwmod_class_sysconfig uart_sysc = { | ||
1502 | .rev_offs = 0x50, | ||
1503 | .sysc_offs = 0x54, | ||
1504 | .syss_offs = 0x58, | ||
1505 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | ||
1506 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
1507 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1508 | SIDLE_SMART_WKUP), | ||
1509 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1510 | }; | ||
1511 | |||
1512 | static struct omap_hwmod_class uart_class = { | ||
1513 | .name = "uart", | ||
1514 | .sysc = &uart_sysc, | ||
1515 | }; | ||
1516 | |||
1517 | /* uart1 */ | ||
1518 | static struct omap_hwmod am33xx_uart1_hwmod = { | ||
1519 | .name = "uart1", | ||
1520 | .class = &uart_class, | ||
1521 | .clkdm_name = "l4_wkup_clkdm", | ||
1522 | .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, | ||
1523 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | ||
1524 | .prcm = { | ||
1525 | .omap4 = { | ||
1526 | .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, | ||
1527 | .modulemode = MODULEMODE_SWCTRL, | ||
1528 | }, | ||
1529 | }, | ||
1530 | }; | ||
1531 | |||
1532 | static struct omap_hwmod am33xx_uart2_hwmod = { | ||
1533 | .name = "uart2", | ||
1534 | .class = &uart_class, | ||
1535 | .clkdm_name = "l4ls_clkdm", | ||
1536 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1537 | .main_clk = "dpll_per_m2_div4_ck", | ||
1538 | .prcm = { | ||
1539 | .omap4 = { | ||
1540 | .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, | ||
1541 | .modulemode = MODULEMODE_SWCTRL, | ||
1542 | }, | ||
1543 | }, | ||
1544 | }; | ||
1545 | |||
1546 | /* uart3 */ | ||
1547 | static struct omap_hwmod am33xx_uart3_hwmod = { | ||
1548 | .name = "uart3", | ||
1549 | .class = &uart_class, | ||
1550 | .clkdm_name = "l4ls_clkdm", | ||
1551 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1552 | .main_clk = "dpll_per_m2_div4_ck", | ||
1553 | .prcm = { | ||
1554 | .omap4 = { | ||
1555 | .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, | ||
1556 | .modulemode = MODULEMODE_SWCTRL, | ||
1557 | }, | ||
1558 | }, | ||
1559 | }; | ||
1560 | |||
1561 | static struct omap_hwmod am33xx_uart4_hwmod = { | ||
1562 | .name = "uart4", | ||
1563 | .class = &uart_class, | ||
1564 | .clkdm_name = "l4ls_clkdm", | ||
1565 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1566 | .main_clk = "dpll_per_m2_div4_ck", | ||
1567 | .prcm = { | ||
1568 | .omap4 = { | ||
1569 | .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, | ||
1570 | .modulemode = MODULEMODE_SWCTRL, | ||
1571 | }, | ||
1572 | }, | ||
1573 | }; | ||
1574 | |||
1575 | static struct omap_hwmod am33xx_uart5_hwmod = { | ||
1576 | .name = "uart5", | ||
1577 | .class = &uart_class, | ||
1578 | .clkdm_name = "l4ls_clkdm", | ||
1579 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1580 | .main_clk = "dpll_per_m2_div4_ck", | ||
1581 | .prcm = { | ||
1582 | .omap4 = { | ||
1583 | .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, | ||
1584 | .modulemode = MODULEMODE_SWCTRL, | ||
1585 | }, | ||
1586 | }, | ||
1587 | }; | ||
1588 | |||
1589 | static struct omap_hwmod am33xx_uart6_hwmod = { | ||
1590 | .name = "uart6", | ||
1591 | .class = &uart_class, | ||
1592 | .clkdm_name = "l4ls_clkdm", | ||
1593 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
1594 | .main_clk = "dpll_per_m2_div4_ck", | ||
1595 | .prcm = { | ||
1596 | .omap4 = { | ||
1597 | .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, | ||
1598 | .modulemode = MODULEMODE_SWCTRL, | ||
1599 | }, | ||
1600 | }, | ||
1601 | }; | ||
1602 | |||
1603 | /* 'wd_timer' class */ | ||
1604 | static struct omap_hwmod_class_sysconfig wdt_sysc = { | ||
1605 | .rev_offs = 0x0, | ||
1606 | .sysc_offs = 0x10, | ||
1607 | .syss_offs = 0x14, | ||
1608 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | ||
1609 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
1610 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1611 | SIDLE_SMART_WKUP), | ||
1612 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1613 | }; | ||
1614 | |||
1615 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { | ||
1616 | .name = "wd_timer", | ||
1617 | .sysc = &wdt_sysc, | ||
1618 | .pre_shutdown = &omap2_wd_timer_disable, | ||
1619 | }; | ||
1620 | |||
1621 | /* | ||
1622 | * XXX: device.c file uses hardcoded name for watchdog timer | ||
1623 | * driver "wd_timer2, so we are also using same name as of now... | ||
1624 | */ | ||
1625 | static struct omap_hwmod am33xx_wd_timer1_hwmod = { | ||
1626 | .name = "wd_timer2", | ||
1627 | .class = &am33xx_wd_timer_hwmod_class, | ||
1628 | .clkdm_name = "l4_wkup_clkdm", | ||
1629 | .flags = HWMOD_SWSUP_SIDLE, | ||
1630 | .main_clk = "wdt1_fck", | ||
1631 | .prcm = { | ||
1632 | .omap4 = { | ||
1633 | .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, | ||
1634 | .modulemode = MODULEMODE_SWCTRL, | ||
1635 | }, | ||
1636 | }, | ||
1637 | }; | ||
1638 | |||
1639 | /* | ||
1640 | * 'usb_otg' class | 301 | * 'usb_otg' class |
1641 | * high-speed on-the-go universal serial bus (usb_otg) controller | 302 | * high-speed on-the-go universal serial bus (usb_otg) controller |
1642 | */ | 303 | */ |
@@ -1690,14 +351,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { | |||
1690 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 351 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1691 | }; | 352 | }; |
1692 | 353 | ||
1693 | /* mpu -> l3 main */ | ||
1694 | static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | ||
1695 | .master = &am33xx_mpu_hwmod, | ||
1696 | .slave = &am33xx_l3_main_hwmod, | ||
1697 | .clk = "dpll_mpu_m2_ck", | ||
1698 | .user = OCP_USER_MPU, | ||
1699 | }; | ||
1700 | |||
1701 | /* l3 main -> l4 hs */ | 354 | /* l3 main -> l4 hs */ |
1702 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { | 355 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { |
1703 | .master = &am33xx_l3_main_hwmod, | 356 | .master = &am33xx_l3_main_hwmod, |
@@ -1706,62 +359,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { | |||
1706 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1707 | }; | 360 | }; |
1708 | 361 | ||
1709 | /* l3 main -> l3 s */ | ||
1710 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | ||
1711 | .master = &am33xx_l3_main_hwmod, | ||
1712 | .slave = &am33xx_l3_s_hwmod, | ||
1713 | .clk = "l3s_gclk", | ||
1714 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1715 | }; | ||
1716 | |||
1717 | /* l3 s -> l4 per/ls */ | ||
1718 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | ||
1719 | .master = &am33xx_l3_s_hwmod, | ||
1720 | .slave = &am33xx_l4_ls_hwmod, | ||
1721 | .clk = "l3s_gclk", | ||
1722 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1723 | }; | ||
1724 | |||
1725 | /* l3 s -> l4 wkup */ | ||
1726 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | ||
1727 | .master = &am33xx_l3_s_hwmod, | ||
1728 | .slave = &am33xx_l4_wkup_hwmod, | ||
1729 | .clk = "l3s_gclk", | ||
1730 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1731 | }; | ||
1732 | |||
1733 | /* l3 main -> l3 instr */ | ||
1734 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | ||
1735 | .master = &am33xx_l3_main_hwmod, | ||
1736 | .slave = &am33xx_l3_instr_hwmod, | ||
1737 | .clk = "l3s_gclk", | ||
1738 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1739 | }; | ||
1740 | |||
1741 | /* mpu -> prcm */ | ||
1742 | static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | ||
1743 | .master = &am33xx_mpu_hwmod, | ||
1744 | .slave = &am33xx_prcm_hwmod, | ||
1745 | .clk = "dpll_mpu_m2_ck", | ||
1746 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1747 | }; | ||
1748 | |||
1749 | /* l3 s -> l3 main*/ | ||
1750 | static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | ||
1751 | .master = &am33xx_l3_s_hwmod, | ||
1752 | .slave = &am33xx_l3_main_hwmod, | ||
1753 | .clk = "l3s_gclk", | ||
1754 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1755 | }; | ||
1756 | |||
1757 | /* pru-icss -> l3 main */ | ||
1758 | static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | ||
1759 | .master = &am33xx_pruss_hwmod, | ||
1760 | .slave = &am33xx_l3_main_hwmod, | ||
1761 | .clk = "l3_gclk", | ||
1762 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1763 | }; | ||
1764 | |||
1765 | /* wkup m3 -> l4 wkup */ | 362 | /* wkup m3 -> l4 wkup */ |
1766 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { | 363 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { |
1767 | .master = &am33xx_wkup_m3_hwmod, | 364 | .master = &am33xx_wkup_m3_hwmod, |
@@ -1770,14 +367,6 @@ static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { | |||
1770 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 367 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1771 | }; | 368 | }; |
1772 | 369 | ||
1773 | /* gfx -> l3 main */ | ||
1774 | static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | ||
1775 | .master = &am33xx_gfx_hwmod, | ||
1776 | .slave = &am33xx_l3_main_hwmod, | ||
1777 | .clk = "dpll_core_m4_ck", | ||
1778 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1779 | }; | ||
1780 | |||
1781 | /* l4 wkup -> wkup m3 */ | 370 | /* l4 wkup -> wkup m3 */ |
1782 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { | 371 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { |
1783 | .master = &am33xx_l4_wkup_hwmod, | 372 | .master = &am33xx_l4_wkup_hwmod, |
@@ -1794,14 +383,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { | |||
1794 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 383 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1795 | }; | 384 | }; |
1796 | 385 | ||
1797 | /* l3 main -> gfx */ | ||
1798 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { | ||
1799 | .master = &am33xx_l3_main_hwmod, | ||
1800 | .slave = &am33xx_gfx_hwmod, | ||
1801 | .clk = "dpll_core_m4_ck", | ||
1802 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1803 | }; | ||
1804 | |||
1805 | /* l3_main -> debugss */ | 386 | /* l3_main -> debugss */ |
1806 | static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { | 387 | static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { |
1807 | { | 388 | { |
@@ -1844,54 +425,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { | |||
1844 | .user = OCP_USER_MPU, | 425 | .user = OCP_USER_MPU, |
1845 | }; | 426 | }; |
1846 | 427 | ||
1847 | /* l4 wkup -> rtc */ | ||
1848 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { | ||
1849 | .master = &am33xx_l4_wkup_hwmod, | ||
1850 | .slave = &am33xx_rtc_hwmod, | ||
1851 | .clk = "clkdiv32k_ick", | ||
1852 | .user = OCP_USER_MPU, | ||
1853 | }; | ||
1854 | |||
1855 | /* l4 per/ls -> DCAN0 */ | ||
1856 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { | ||
1857 | .master = &am33xx_l4_ls_hwmod, | ||
1858 | .slave = &am33xx_dcan0_hwmod, | ||
1859 | .clk = "l4ls_gclk", | ||
1860 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1861 | }; | ||
1862 | |||
1863 | /* l4 per/ls -> DCAN1 */ | ||
1864 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { | ||
1865 | .master = &am33xx_l4_ls_hwmod, | ||
1866 | .slave = &am33xx_dcan1_hwmod, | ||
1867 | .clk = "l4ls_gclk", | ||
1868 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1869 | }; | ||
1870 | |||
1871 | /* l4 per/ls -> GPIO2 */ | ||
1872 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { | ||
1873 | .master = &am33xx_l4_ls_hwmod, | ||
1874 | .slave = &am33xx_gpio1_hwmod, | ||
1875 | .clk = "l4ls_gclk", | ||
1876 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1877 | }; | ||
1878 | |||
1879 | /* l4 per/ls -> gpio3 */ | ||
1880 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { | ||
1881 | .master = &am33xx_l4_ls_hwmod, | ||
1882 | .slave = &am33xx_gpio2_hwmod, | ||
1883 | .clk = "l4ls_gclk", | ||
1884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1885 | }; | ||
1886 | |||
1887 | /* l4 per/ls -> gpio4 */ | ||
1888 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { | ||
1889 | .master = &am33xx_l4_ls_hwmod, | ||
1890 | .slave = &am33xx_gpio3_hwmod, | ||
1891 | .clk = "l4ls_gclk", | ||
1892 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
1893 | }; | ||
1894 | |||
1895 | /* L4 WKUP -> I2C1 */ | 428 | /* L4 WKUP -> I2C1 */ |
1896 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { | 429 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { |
1897 | .master = &am33xx_l4_wkup_hwmod, | 430 | .master = &am33xx_l4_wkup_hwmod, |
@@ -1933,177 +466,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { | |||
1933 | .user = OCP_USER_MPU, | 466 | .user = OCP_USER_MPU, |
1934 | }; | 467 | }; |
1935 | 468 | ||
1936 | static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { | ||
1937 | .master = &am33xx_cpgmac0_hwmod, | ||
1938 | .slave = &am33xx_mdio_hwmod, | ||
1939 | .user = OCP_USER_MPU, | ||
1940 | }; | ||
1941 | |||
1942 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { | ||
1943 | { | ||
1944 | .pa_start = 0x48080000, | ||
1945 | .pa_end = 0x48080000 + SZ_8K - 1, | ||
1946 | .flags = ADDR_TYPE_RT | ||
1947 | }, | ||
1948 | { } | ||
1949 | }; | ||
1950 | |||
1951 | static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { | ||
1952 | .master = &am33xx_l4_ls_hwmod, | ||
1953 | .slave = &am33xx_elm_hwmod, | ||
1954 | .clk = "l4ls_gclk", | ||
1955 | .addr = am33xx_elm_addr_space, | ||
1956 | .user = OCP_USER_MPU, | ||
1957 | }; | ||
1958 | |||
1959 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { | ||
1960 | { | ||
1961 | .pa_start = 0x48300000, | ||
1962 | .pa_end = 0x48300000 + SZ_16 - 1, | ||
1963 | .flags = ADDR_TYPE_RT | ||
1964 | }, | ||
1965 | { } | ||
1966 | }; | ||
1967 | |||
1968 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { | ||
1969 | .master = &am33xx_l4_ls_hwmod, | ||
1970 | .slave = &am33xx_epwmss0_hwmod, | ||
1971 | .clk = "l4ls_gclk", | ||
1972 | .addr = am33xx_epwmss0_addr_space, | ||
1973 | .user = OCP_USER_MPU, | ||
1974 | }; | ||
1975 | |||
1976 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { | ||
1977 | .master = &am33xx_epwmss0_hwmod, | ||
1978 | .slave = &am33xx_ecap0_hwmod, | ||
1979 | .clk = "l4ls_gclk", | ||
1980 | .user = OCP_USER_MPU, | ||
1981 | }; | ||
1982 | |||
1983 | static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { | ||
1984 | .master = &am33xx_epwmss0_hwmod, | ||
1985 | .slave = &am33xx_eqep0_hwmod, | ||
1986 | .clk = "l4ls_gclk", | ||
1987 | .user = OCP_USER_MPU, | ||
1988 | }; | ||
1989 | |||
1990 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { | ||
1991 | .master = &am33xx_epwmss0_hwmod, | ||
1992 | .slave = &am33xx_ehrpwm0_hwmod, | ||
1993 | .clk = "l4ls_gclk", | ||
1994 | .user = OCP_USER_MPU, | ||
1995 | }; | ||
1996 | |||
1997 | |||
1998 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { | ||
1999 | { | ||
2000 | .pa_start = 0x48302000, | ||
2001 | .pa_end = 0x48302000 + SZ_16 - 1, | ||
2002 | .flags = ADDR_TYPE_RT | ||
2003 | }, | ||
2004 | { } | ||
2005 | }; | ||
2006 | |||
2007 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { | ||
2008 | .master = &am33xx_l4_ls_hwmod, | ||
2009 | .slave = &am33xx_epwmss1_hwmod, | ||
2010 | .clk = "l4ls_gclk", | ||
2011 | .addr = am33xx_epwmss1_addr_space, | ||
2012 | .user = OCP_USER_MPU, | ||
2013 | }; | ||
2014 | |||
2015 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { | ||
2016 | .master = &am33xx_epwmss1_hwmod, | ||
2017 | .slave = &am33xx_ecap1_hwmod, | ||
2018 | .clk = "l4ls_gclk", | ||
2019 | .user = OCP_USER_MPU, | ||
2020 | }; | ||
2021 | |||
2022 | static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { | ||
2023 | .master = &am33xx_epwmss1_hwmod, | ||
2024 | .slave = &am33xx_eqep1_hwmod, | ||
2025 | .clk = "l4ls_gclk", | ||
2026 | .user = OCP_USER_MPU, | ||
2027 | }; | ||
2028 | |||
2029 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { | ||
2030 | .master = &am33xx_epwmss1_hwmod, | ||
2031 | .slave = &am33xx_ehrpwm1_hwmod, | ||
2032 | .clk = "l4ls_gclk", | ||
2033 | .user = OCP_USER_MPU, | ||
2034 | }; | ||
2035 | |||
2036 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { | ||
2037 | { | ||
2038 | .pa_start = 0x48304000, | ||
2039 | .pa_end = 0x48304000 + SZ_16 - 1, | ||
2040 | .flags = ADDR_TYPE_RT | ||
2041 | }, | ||
2042 | { } | ||
2043 | }; | ||
2044 | |||
2045 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { | ||
2046 | .master = &am33xx_l4_ls_hwmod, | ||
2047 | .slave = &am33xx_epwmss2_hwmod, | ||
2048 | .clk = "l4ls_gclk", | ||
2049 | .addr = am33xx_epwmss2_addr_space, | ||
2050 | .user = OCP_USER_MPU, | ||
2051 | }; | ||
2052 | |||
2053 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { | ||
2054 | .master = &am33xx_epwmss2_hwmod, | ||
2055 | .slave = &am33xx_ecap2_hwmod, | ||
2056 | .clk = "l4ls_gclk", | ||
2057 | .user = OCP_USER_MPU, | ||
2058 | }; | ||
2059 | |||
2060 | static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { | ||
2061 | .master = &am33xx_epwmss2_hwmod, | ||
2062 | .slave = &am33xx_eqep2_hwmod, | ||
2063 | .clk = "l4ls_gclk", | ||
2064 | .user = OCP_USER_MPU, | ||
2065 | }; | ||
2066 | |||
2067 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { | ||
2068 | .master = &am33xx_epwmss2_hwmod, | ||
2069 | .slave = &am33xx_ehrpwm2_hwmod, | ||
2070 | .clk = "l4ls_gclk", | ||
2071 | .user = OCP_USER_MPU, | ||
2072 | }; | ||
2073 | |||
2074 | /* l3s cfg -> gpmc */ | ||
2075 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { | ||
2076 | { | ||
2077 | .pa_start = 0x50000000, | ||
2078 | .pa_end = 0x50000000 + SZ_8K - 1, | ||
2079 | .flags = ADDR_TYPE_RT, | ||
2080 | }, | ||
2081 | { } | ||
2082 | }; | ||
2083 | |||
2084 | static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | ||
2085 | .master = &am33xx_l3_s_hwmod, | ||
2086 | .slave = &am33xx_gpmc_hwmod, | ||
2087 | .clk = "l3s_gclk", | ||
2088 | .addr = am33xx_gpmc_addr_space, | ||
2089 | .user = OCP_USER_MPU, | ||
2090 | }; | ||
2091 | |||
2092 | /* i2c2 */ | ||
2093 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { | ||
2094 | .master = &am33xx_l4_ls_hwmod, | ||
2095 | .slave = &am33xx_i2c2_hwmod, | ||
2096 | .clk = "l4ls_gclk", | ||
2097 | .user = OCP_USER_MPU, | ||
2098 | }; | ||
2099 | |||
2100 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { | ||
2101 | .master = &am33xx_l4_ls_hwmod, | ||
2102 | .slave = &am33xx_i2c3_hwmod, | ||
2103 | .clk = "l4ls_gclk", | ||
2104 | .user = OCP_USER_MPU, | ||
2105 | }; | ||
2106 | |||
2107 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { | 469 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { |
2108 | { | 470 | { |
2109 | .pa_start = 0x4830E000, | 471 | .pa_start = 0x4830E000, |
@@ -2121,138 +483,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { | |||
2121 | .user = OCP_USER_MPU, | 483 | .user = OCP_USER_MPU, |
2122 | }; | 484 | }; |
2123 | 485 | ||
2124 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { | ||
2125 | { | ||
2126 | .pa_start = 0x480C8000, | ||
2127 | .pa_end = 0x480C8000 + (SZ_4K - 1), | ||
2128 | .flags = ADDR_TYPE_RT | ||
2129 | }, | ||
2130 | { } | ||
2131 | }; | ||
2132 | |||
2133 | /* l4 ls -> mailbox */ | ||
2134 | static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | ||
2135 | .master = &am33xx_l4_ls_hwmod, | ||
2136 | .slave = &am33xx_mailbox_hwmod, | ||
2137 | .clk = "l4ls_gclk", | ||
2138 | .addr = am33xx_mailbox_addrs, | ||
2139 | .user = OCP_USER_MPU, | ||
2140 | }; | ||
2141 | |||
2142 | /* l4 ls -> spinlock */ | ||
2143 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { | ||
2144 | .master = &am33xx_l4_ls_hwmod, | ||
2145 | .slave = &am33xx_spinlock_hwmod, | ||
2146 | .clk = "l4ls_gclk", | ||
2147 | .user = OCP_USER_MPU, | ||
2148 | }; | ||
2149 | |||
2150 | /* l4 ls -> mcasp0 */ | ||
2151 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | ||
2152 | { | ||
2153 | .pa_start = 0x48038000, | ||
2154 | .pa_end = 0x48038000 + SZ_8K - 1, | ||
2155 | .flags = ADDR_TYPE_RT | ||
2156 | }, | ||
2157 | { } | ||
2158 | }; | ||
2159 | |||
2160 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | ||
2161 | .master = &am33xx_l4_ls_hwmod, | ||
2162 | .slave = &am33xx_mcasp0_hwmod, | ||
2163 | .clk = "l4ls_gclk", | ||
2164 | .addr = am33xx_mcasp0_addr_space, | ||
2165 | .user = OCP_USER_MPU, | ||
2166 | }; | ||
2167 | |||
2168 | /* l4 ls -> mcasp1 */ | ||
2169 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | ||
2170 | { | ||
2171 | .pa_start = 0x4803C000, | ||
2172 | .pa_end = 0x4803C000 + SZ_8K - 1, | ||
2173 | .flags = ADDR_TYPE_RT | ||
2174 | }, | ||
2175 | { } | ||
2176 | }; | ||
2177 | |||
2178 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | ||
2179 | .master = &am33xx_l4_ls_hwmod, | ||
2180 | .slave = &am33xx_mcasp1_hwmod, | ||
2181 | .clk = "l4ls_gclk", | ||
2182 | .addr = am33xx_mcasp1_addr_space, | ||
2183 | .user = OCP_USER_MPU, | ||
2184 | }; | ||
2185 | |||
2186 | /* l4 ls -> mmc0 */ | ||
2187 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | ||
2188 | { | ||
2189 | .pa_start = 0x48060100, | ||
2190 | .pa_end = 0x48060100 + SZ_4K - 1, | ||
2191 | .flags = ADDR_TYPE_RT, | ||
2192 | }, | ||
2193 | { } | ||
2194 | }; | ||
2195 | |||
2196 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | ||
2197 | .master = &am33xx_l4_ls_hwmod, | ||
2198 | .slave = &am33xx_mmc0_hwmod, | ||
2199 | .clk = "l4ls_gclk", | ||
2200 | .addr = am33xx_mmc0_addr_space, | ||
2201 | .user = OCP_USER_MPU, | ||
2202 | }; | ||
2203 | |||
2204 | /* l4 ls -> mmc1 */ | ||
2205 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | ||
2206 | { | ||
2207 | .pa_start = 0x481d8100, | ||
2208 | .pa_end = 0x481d8100 + SZ_4K - 1, | ||
2209 | .flags = ADDR_TYPE_RT, | ||
2210 | }, | ||
2211 | { } | ||
2212 | }; | ||
2213 | |||
2214 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | ||
2215 | .master = &am33xx_l4_ls_hwmod, | ||
2216 | .slave = &am33xx_mmc1_hwmod, | ||
2217 | .clk = "l4ls_gclk", | ||
2218 | .addr = am33xx_mmc1_addr_space, | ||
2219 | .user = OCP_USER_MPU, | ||
2220 | }; | ||
2221 | |||
2222 | /* l3 s -> mmc2 */ | ||
2223 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | ||
2224 | { | ||
2225 | .pa_start = 0x47810100, | ||
2226 | .pa_end = 0x47810100 + SZ_64K - 1, | ||
2227 | .flags = ADDR_TYPE_RT, | ||
2228 | }, | ||
2229 | { } | ||
2230 | }; | ||
2231 | |||
2232 | static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | ||
2233 | .master = &am33xx_l3_s_hwmod, | ||
2234 | .slave = &am33xx_mmc2_hwmod, | ||
2235 | .clk = "l3s_gclk", | ||
2236 | .addr = am33xx_mmc2_addr_space, | ||
2237 | .user = OCP_USER_MPU, | ||
2238 | }; | ||
2239 | |||
2240 | /* l4 ls -> mcspi0 */ | ||
2241 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { | ||
2242 | .master = &am33xx_l4_ls_hwmod, | ||
2243 | .slave = &am33xx_spi0_hwmod, | ||
2244 | .clk = "l4ls_gclk", | ||
2245 | .user = OCP_USER_MPU, | ||
2246 | }; | ||
2247 | |||
2248 | /* l4 ls -> mcspi1 */ | ||
2249 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { | ||
2250 | .master = &am33xx_l4_ls_hwmod, | ||
2251 | .slave = &am33xx_spi1_hwmod, | ||
2252 | .clk = "l4ls_gclk", | ||
2253 | .user = OCP_USER_MPU, | ||
2254 | }; | ||
2255 | |||
2256 | /* l4 wkup -> timer1 */ | 486 | /* l4 wkup -> timer1 */ |
2257 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { | 487 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { |
2258 | .master = &am33xx_l4_wkup_hwmod, | 488 | .master = &am33xx_l4_wkup_hwmod, |
@@ -2261,116 +491,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { | |||
2261 | .user = OCP_USER_MPU, | 491 | .user = OCP_USER_MPU, |
2262 | }; | 492 | }; |
2263 | 493 | ||
2264 | /* l4 per -> timer2 */ | ||
2265 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { | ||
2266 | .master = &am33xx_l4_ls_hwmod, | ||
2267 | .slave = &am33xx_timer2_hwmod, | ||
2268 | .clk = "l4ls_gclk", | ||
2269 | .user = OCP_USER_MPU, | ||
2270 | }; | ||
2271 | |||
2272 | /* l4 per -> timer3 */ | ||
2273 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { | ||
2274 | .master = &am33xx_l4_ls_hwmod, | ||
2275 | .slave = &am33xx_timer3_hwmod, | ||
2276 | .clk = "l4ls_gclk", | ||
2277 | .user = OCP_USER_MPU, | ||
2278 | }; | ||
2279 | |||
2280 | /* l4 per -> timer4 */ | ||
2281 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { | ||
2282 | .master = &am33xx_l4_ls_hwmod, | ||
2283 | .slave = &am33xx_timer4_hwmod, | ||
2284 | .clk = "l4ls_gclk", | ||
2285 | .user = OCP_USER_MPU, | ||
2286 | }; | ||
2287 | |||
2288 | /* l4 per -> timer5 */ | ||
2289 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { | ||
2290 | .master = &am33xx_l4_ls_hwmod, | ||
2291 | .slave = &am33xx_timer5_hwmod, | ||
2292 | .clk = "l4ls_gclk", | ||
2293 | .user = OCP_USER_MPU, | ||
2294 | }; | ||
2295 | |||
2296 | /* l4 per -> timer6 */ | ||
2297 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { | ||
2298 | .master = &am33xx_l4_ls_hwmod, | ||
2299 | .slave = &am33xx_timer6_hwmod, | ||
2300 | .clk = "l4ls_gclk", | ||
2301 | .user = OCP_USER_MPU, | ||
2302 | }; | ||
2303 | |||
2304 | /* l4 per -> timer7 */ | ||
2305 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { | ||
2306 | .master = &am33xx_l4_ls_hwmod, | ||
2307 | .slave = &am33xx_timer7_hwmod, | ||
2308 | .clk = "l4ls_gclk", | ||
2309 | .user = OCP_USER_MPU, | ||
2310 | }; | ||
2311 | |||
2312 | /* l3 main -> tpcc */ | ||
2313 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { | ||
2314 | .master = &am33xx_l3_main_hwmod, | ||
2315 | .slave = &am33xx_tpcc_hwmod, | ||
2316 | .clk = "l3_gclk", | ||
2317 | .user = OCP_USER_MPU, | ||
2318 | }; | ||
2319 | |||
2320 | /* l3 main -> tpcc0 */ | ||
2321 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | ||
2322 | { | ||
2323 | .pa_start = 0x49800000, | ||
2324 | .pa_end = 0x49800000 + SZ_8K - 1, | ||
2325 | .flags = ADDR_TYPE_RT, | ||
2326 | }, | ||
2327 | { } | ||
2328 | }; | ||
2329 | |||
2330 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | ||
2331 | .master = &am33xx_l3_main_hwmod, | ||
2332 | .slave = &am33xx_tptc0_hwmod, | ||
2333 | .clk = "l3_gclk", | ||
2334 | .addr = am33xx_tptc0_addr_space, | ||
2335 | .user = OCP_USER_MPU, | ||
2336 | }; | ||
2337 | |||
2338 | /* l3 main -> tpcc1 */ | ||
2339 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | ||
2340 | { | ||
2341 | .pa_start = 0x49900000, | ||
2342 | .pa_end = 0x49900000 + SZ_8K - 1, | ||
2343 | .flags = ADDR_TYPE_RT, | ||
2344 | }, | ||
2345 | { } | ||
2346 | }; | ||
2347 | |||
2348 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | ||
2349 | .master = &am33xx_l3_main_hwmod, | ||
2350 | .slave = &am33xx_tptc1_hwmod, | ||
2351 | .clk = "l3_gclk", | ||
2352 | .addr = am33xx_tptc1_addr_space, | ||
2353 | .user = OCP_USER_MPU, | ||
2354 | }; | ||
2355 | |||
2356 | /* l3 main -> tpcc2 */ | ||
2357 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | ||
2358 | { | ||
2359 | .pa_start = 0x49a00000, | ||
2360 | .pa_end = 0x49a00000 + SZ_8K - 1, | ||
2361 | .flags = ADDR_TYPE_RT, | ||
2362 | }, | ||
2363 | { } | ||
2364 | }; | ||
2365 | |||
2366 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | ||
2367 | .master = &am33xx_l3_main_hwmod, | ||
2368 | .slave = &am33xx_tptc2_hwmod, | ||
2369 | .clk = "l3_gclk", | ||
2370 | .addr = am33xx_tptc2_addr_space, | ||
2371 | .user = OCP_USER_MPU, | ||
2372 | }; | ||
2373 | |||
2374 | /* l4 wkup -> uart1 */ | 494 | /* l4 wkup -> uart1 */ |
2375 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { | 495 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { |
2376 | .master = &am33xx_l4_wkup_hwmod, | 496 | .master = &am33xx_l4_wkup_hwmod, |
@@ -2379,46 +499,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { | |||
2379 | .user = OCP_USER_MPU, | 499 | .user = OCP_USER_MPU, |
2380 | }; | 500 | }; |
2381 | 501 | ||
2382 | /* l4 ls -> uart2 */ | ||
2383 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { | ||
2384 | .master = &am33xx_l4_ls_hwmod, | ||
2385 | .slave = &am33xx_uart2_hwmod, | ||
2386 | .clk = "l4ls_gclk", | ||
2387 | .user = OCP_USER_MPU, | ||
2388 | }; | ||
2389 | |||
2390 | /* l4 ls -> uart3 */ | ||
2391 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { | ||
2392 | .master = &am33xx_l4_ls_hwmod, | ||
2393 | .slave = &am33xx_uart3_hwmod, | ||
2394 | .clk = "l4ls_gclk", | ||
2395 | .user = OCP_USER_MPU, | ||
2396 | }; | ||
2397 | |||
2398 | /* l4 ls -> uart4 */ | ||
2399 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { | ||
2400 | .master = &am33xx_l4_ls_hwmod, | ||
2401 | .slave = &am33xx_uart4_hwmod, | ||
2402 | .clk = "l4ls_gclk", | ||
2403 | .user = OCP_USER_MPU, | ||
2404 | }; | ||
2405 | |||
2406 | /* l4 ls -> uart5 */ | ||
2407 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { | ||
2408 | .master = &am33xx_l4_ls_hwmod, | ||
2409 | .slave = &am33xx_uart5_hwmod, | ||
2410 | .clk = "l4ls_gclk", | ||
2411 | .user = OCP_USER_MPU, | ||
2412 | }; | ||
2413 | |||
2414 | /* l4 ls -> uart6 */ | ||
2415 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { | ||
2416 | .master = &am33xx_l4_ls_hwmod, | ||
2417 | .slave = &am33xx_uart6_hwmod, | ||
2418 | .clk = "l4ls_gclk", | ||
2419 | .user = OCP_USER_MPU, | ||
2420 | }; | ||
2421 | |||
2422 | /* l4 wkup -> wd_timer1 */ | 502 | /* l4 wkup -> wd_timer1 */ |
2423 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { | 503 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { |
2424 | .master = &am33xx_l4_wkup_hwmod, | 504 | .master = &am33xx_l4_wkup_hwmod, |
@@ -2437,47 +517,39 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { | |||
2437 | .flags = OCPIF_SWSUP_IDLE, | 517 | .flags = OCPIF_SWSUP_IDLE, |
2438 | }; | 518 | }; |
2439 | 519 | ||
2440 | /* l3 main -> ocmc */ | 520 | /* rng */ |
2441 | static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | 521 | static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { |
2442 | .master = &am33xx_l3_main_hwmod, | 522 | .rev_offs = 0x1fe0, |
2443 | .slave = &am33xx_ocmcram_hwmod, | 523 | .sysc_offs = 0x1fe4, |
2444 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 524 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, |
2445 | }; | 525 | .idlemodes = SIDLE_FORCE | SIDLE_NO, |
2446 | 526 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2447 | /* l3 main -> sha0 HIB2 */ | ||
2448 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | ||
2449 | { | ||
2450 | .pa_start = 0x53100000, | ||
2451 | .pa_end = 0x53100000 + SZ_512 - 1, | ||
2452 | .flags = ADDR_TYPE_RT | ||
2453 | }, | ||
2454 | { } | ||
2455 | }; | 527 | }; |
2456 | 528 | ||
2457 | static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | 529 | static struct omap_hwmod_class am33xx_rng_hwmod_class = { |
2458 | .master = &am33xx_l3_main_hwmod, | 530 | .name = "rng", |
2459 | .slave = &am33xx_sha0_hwmod, | 531 | .sysc = &am33xx_rng_sysc, |
2460 | .clk = "sha0_fck", | ||
2461 | .addr = am33xx_sha0_addrs, | ||
2462 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2463 | }; | 532 | }; |
2464 | 533 | ||
2465 | /* l3 main -> AES0 HIB2 */ | 534 | static struct omap_hwmod am33xx_rng_hwmod = { |
2466 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | 535 | .name = "rng", |
2467 | { | 536 | .class = &am33xx_rng_hwmod_class, |
2468 | .pa_start = 0x53500000, | 537 | .clkdm_name = "l4ls_clkdm", |
2469 | .pa_end = 0x53500000 + SZ_1M - 1, | 538 | .flags = HWMOD_SWSUP_SIDLE, |
2470 | .flags = ADDR_TYPE_RT | 539 | .main_clk = "rng_fck", |
540 | .prcm = { | ||
541 | .omap4 = { | ||
542 | .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET, | ||
543 | .modulemode = MODULEMODE_SWCTRL, | ||
544 | }, | ||
2471 | }, | 545 | }, |
2472 | { } | ||
2473 | }; | 546 | }; |
2474 | 547 | ||
2475 | static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | 548 | static struct omap_hwmod_ocp_if am33xx_l4_per__rng = { |
2476 | .master = &am33xx_l3_main_hwmod, | 549 | .master = &am33xx_l4_ls_hwmod, |
2477 | .slave = &am33xx_aes0_hwmod, | 550 | .slave = &am33xx_rng_hwmod, |
2478 | .clk = "aes0_fck", | 551 | .clk = "rng_fck", |
2479 | .addr = am33xx_aes0_addrs, | 552 | .user = OCP_USER_MPU, |
2480 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2481 | }; | 553 | }; |
2482 | 554 | ||
2483 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | 555 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
@@ -2559,11 +631,13 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | |||
2559 | &am33xx_cpgmac0__mdio, | 631 | &am33xx_cpgmac0__mdio, |
2560 | &am33xx_l3_main__sha0, | 632 | &am33xx_l3_main__sha0, |
2561 | &am33xx_l3_main__aes0, | 633 | &am33xx_l3_main__aes0, |
634 | &am33xx_l4_per__rng, | ||
2562 | NULL, | 635 | NULL, |
2563 | }; | 636 | }; |
2564 | 637 | ||
2565 | int __init am33xx_hwmod_init(void) | 638 | int __init am33xx_hwmod_init(void) |
2566 | { | 639 | { |
640 | omap_hwmod_am33xx_reg(); | ||
2567 | omap_hwmod_init(); | 641 | omap_hwmod_init(); |
2568 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); | 642 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); |
2569 | } | 643 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 0c3a427da544..9e56fabd7fa3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
@@ -3693,6 +3693,53 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { | |||
3693 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3693 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3694 | }; | 3694 | }; |
3695 | 3695 | ||
3696 | /* | ||
3697 | * 'ssi' class | ||
3698 | * synchronous serial interface (multichannel and full-duplex serial if) | ||
3699 | */ | ||
3700 | |||
3701 | static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { | ||
3702 | .rev_offs = 0x0000, | ||
3703 | .sysc_offs = 0x0010, | ||
3704 | .syss_offs = 0x0014, | ||
3705 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | ||
3706 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | ||
3707 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
3708 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
3709 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | ||
3710 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | ||
3711 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
3712 | }; | ||
3713 | |||
3714 | static struct omap_hwmod_class omap34xx_ssi_hwmod_class = { | ||
3715 | .name = "ssi", | ||
3716 | .sysc = &omap34xx_ssi_sysc, | ||
3717 | }; | ||
3718 | |||
3719 | static struct omap_hwmod omap34xx_ssi_hwmod = { | ||
3720 | .name = "ssi", | ||
3721 | .class = &omap34xx_ssi_hwmod_class, | ||
3722 | .clkdm_name = "core_l4_clkdm", | ||
3723 | .main_clk = "ssi_ssr_fck", | ||
3724 | .prcm = { | ||
3725 | .omap2 = { | ||
3726 | .prcm_reg_id = 1, | ||
3727 | .module_bit = OMAP3430_EN_SSI_SHIFT, | ||
3728 | .module_offs = CORE_MOD, | ||
3729 | .idlest_reg_id = 1, | ||
3730 | .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, | ||
3731 | }, | ||
3732 | }, | ||
3733 | }; | ||
3734 | |||
3735 | /* L4 CORE -> SSI */ | ||
3736 | static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = { | ||
3737 | .master = &omap3xxx_l4_core_hwmod, | ||
3738 | .slave = &omap34xx_ssi_hwmod, | ||
3739 | .clk = "ssi_ick", | ||
3740 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
3741 | }; | ||
3742 | |||
3696 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { | 3743 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3697 | &omap3xxx_l3_main__l4_core, | 3744 | &omap3xxx_l3_main__l4_core, |
3698 | &omap3xxx_l3_main__l4_per, | 3745 | &omap3xxx_l3_main__l4_per, |
@@ -3818,6 +3865,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |||
3818 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | 3865 | #ifdef CONFIG_OMAP_IOMMU_IVA2 |
3819 | &omap3xxx_l3_main__mmu_iva, | 3866 | &omap3xxx_l3_main__mmu_iva, |
3820 | #endif | 3867 | #endif |
3868 | &omap34xx_l4_core__ssi, | ||
3821 | NULL | 3869 | NULL |
3822 | }; | 3870 | }; |
3823 | 3871 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c new file mode 100644 index 000000000000..9002fca76699 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c | |||
@@ -0,0 +1,758 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
3 | * | ||
4 | * Hwmod present only in AM43x and those that differ other than register | ||
5 | * offsets as compared to AM335x. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License as | ||
9 | * published by the Free Software Foundation version 2. | ||
10 | * | ||
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
12 | * kind, whether express or implied; without even the implied warranty | ||
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/platform_data/gpio-omap.h> | ||
18 | #include <linux/platform_data/spi-omap2-mcspi.h> | ||
19 | #include "omap_hwmod.h" | ||
20 | #include "omap_hwmod_33xx_43xx_common_data.h" | ||
21 | #include "prcm43xx.h" | ||
22 | |||
23 | /* IP blocks */ | ||
24 | static struct omap_hwmod am43xx_l4_hs_hwmod = { | ||
25 | .name = "l4_hs", | ||
26 | .class = &am33xx_l4_hwmod_class, | ||
27 | .clkdm_name = "l3_clkdm", | ||
28 | .flags = HWMOD_INIT_NO_IDLE, | ||
29 | .main_clk = "l4hs_gclk", | ||
30 | .prcm = { | ||
31 | .omap4 = { | ||
32 | .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET, | ||
33 | .modulemode = MODULEMODE_SWCTRL, | ||
34 | }, | ||
35 | }, | ||
36 | }; | ||
37 | |||
38 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | ||
39 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | ||
40 | }; | ||
41 | |||
42 | static struct omap_hwmod am43xx_wkup_m3_hwmod = { | ||
43 | .name = "wkup_m3", | ||
44 | .class = &am33xx_wkup_m3_hwmod_class, | ||
45 | .clkdm_name = "l4_wkup_aon_clkdm", | ||
46 | /* Keep hardreset asserted */ | ||
47 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, | ||
48 | .main_clk = "sys_clkin_ck", | ||
49 | .prcm = { | ||
50 | .omap4 = { | ||
51 | .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, | ||
52 | .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET, | ||
53 | .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET, | ||
54 | .modulemode = MODULEMODE_SWCTRL, | ||
55 | }, | ||
56 | }, | ||
57 | .rst_lines = am33xx_wkup_m3_resets, | ||
58 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), | ||
59 | }; | ||
60 | |||
61 | static struct omap_hwmod am43xx_control_hwmod = { | ||
62 | .name = "control", | ||
63 | .class = &am33xx_control_hwmod_class, | ||
64 | .clkdm_name = "l4_wkup_clkdm", | ||
65 | .flags = HWMOD_INIT_NO_IDLE, | ||
66 | .main_clk = "sys_clkin_ck", | ||
67 | .prcm = { | ||
68 | .omap4 = { | ||
69 | .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, | ||
70 | .modulemode = MODULEMODE_SWCTRL, | ||
71 | }, | ||
72 | }, | ||
73 | }; | ||
74 | |||
75 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | ||
76 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | ||
77 | }; | ||
78 | |||
79 | static struct omap_hwmod am43xx_gpio0_hwmod = { | ||
80 | .name = "gpio1", | ||
81 | .class = &am33xx_gpio_hwmod_class, | ||
82 | .clkdm_name = "l4_wkup_clkdm", | ||
83 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
84 | .main_clk = "sys_clkin_ck", | ||
85 | .prcm = { | ||
86 | .omap4 = { | ||
87 | .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, | ||
88 | .modulemode = MODULEMODE_SWCTRL, | ||
89 | }, | ||
90 | }, | ||
91 | .opt_clks = gpio0_opt_clks, | ||
92 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), | ||
93 | .dev_attr = &gpio_dev_attr, | ||
94 | }; | ||
95 | |||
96 | static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { | ||
97 | .rev_offs = 0x0, | ||
98 | .sysc_offs = 0x4, | ||
99 | .sysc_flags = SYSC_HAS_SIDLEMODE, | ||
100 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | ||
101 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
102 | }; | ||
103 | |||
104 | static struct omap_hwmod_class am43xx_synctimer_hwmod_class = { | ||
105 | .name = "synctimer", | ||
106 | .sysc = &am43xx_synctimer_sysc, | ||
107 | }; | ||
108 | |||
109 | static struct omap_hwmod am43xx_synctimer_hwmod = { | ||
110 | .name = "counter_32k", | ||
111 | .class = &am43xx_synctimer_hwmod_class, | ||
112 | .clkdm_name = "l4_wkup_aon_clkdm", | ||
113 | .flags = HWMOD_SWSUP_SIDLE, | ||
114 | .main_clk = "synctimer_32kclk", | ||
115 | .prcm = { | ||
116 | .omap4 = { | ||
117 | .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, | ||
118 | .modulemode = MODULEMODE_SWCTRL, | ||
119 | }, | ||
120 | }, | ||
121 | }; | ||
122 | |||
123 | static struct omap_hwmod am43xx_timer8_hwmod = { | ||
124 | .name = "timer8", | ||
125 | .class = &am33xx_timer_hwmod_class, | ||
126 | .clkdm_name = "l4ls_clkdm", | ||
127 | .main_clk = "timer8_fck", | ||
128 | .prcm = { | ||
129 | .omap4 = { | ||
130 | .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET, | ||
131 | .modulemode = MODULEMODE_SWCTRL, | ||
132 | }, | ||
133 | }, | ||
134 | }; | ||
135 | |||
136 | static struct omap_hwmod am43xx_timer9_hwmod = { | ||
137 | .name = "timer9", | ||
138 | .class = &am33xx_timer_hwmod_class, | ||
139 | .clkdm_name = "l4ls_clkdm", | ||
140 | .main_clk = "timer9_fck", | ||
141 | .prcm = { | ||
142 | .omap4 = { | ||
143 | .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET, | ||
144 | .modulemode = MODULEMODE_SWCTRL, | ||
145 | }, | ||
146 | }, | ||
147 | }; | ||
148 | |||
149 | static struct omap_hwmod am43xx_timer10_hwmod = { | ||
150 | .name = "timer10", | ||
151 | .class = &am33xx_timer_hwmod_class, | ||
152 | .clkdm_name = "l4ls_clkdm", | ||
153 | .main_clk = "timer10_fck", | ||
154 | .prcm = { | ||
155 | .omap4 = { | ||
156 | .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET, | ||
157 | .modulemode = MODULEMODE_SWCTRL, | ||
158 | }, | ||
159 | }, | ||
160 | }; | ||
161 | |||
162 | static struct omap_hwmod am43xx_timer11_hwmod = { | ||
163 | .name = "timer11", | ||
164 | .class = &am33xx_timer_hwmod_class, | ||
165 | .clkdm_name = "l4ls_clkdm", | ||
166 | .main_clk = "timer11_fck", | ||
167 | .prcm = { | ||
168 | .omap4 = { | ||
169 | .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET, | ||
170 | .modulemode = MODULEMODE_SWCTRL, | ||
171 | }, | ||
172 | }, | ||
173 | }; | ||
174 | |||
175 | static struct omap_hwmod am43xx_epwmss3_hwmod = { | ||
176 | .name = "epwmss3", | ||
177 | .class = &am33xx_epwmss_hwmod_class, | ||
178 | .clkdm_name = "l4ls_clkdm", | ||
179 | .main_clk = "l4ls_gclk", | ||
180 | .prcm = { | ||
181 | .omap4 = { | ||
182 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET, | ||
183 | .modulemode = MODULEMODE_SWCTRL, | ||
184 | }, | ||
185 | }, | ||
186 | }; | ||
187 | |||
188 | static struct omap_hwmod am43xx_ehrpwm3_hwmod = { | ||
189 | .name = "ehrpwm3", | ||
190 | .class = &am33xx_ehrpwm_hwmod_class, | ||
191 | .clkdm_name = "l4ls_clkdm", | ||
192 | .main_clk = "l4ls_gclk", | ||
193 | }; | ||
194 | |||
195 | static struct omap_hwmod am43xx_epwmss4_hwmod = { | ||
196 | .name = "epwmss4", | ||
197 | .class = &am33xx_epwmss_hwmod_class, | ||
198 | .clkdm_name = "l4ls_clkdm", | ||
199 | .main_clk = "l4ls_gclk", | ||
200 | .prcm = { | ||
201 | .omap4 = { | ||
202 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET, | ||
203 | .modulemode = MODULEMODE_SWCTRL, | ||
204 | }, | ||
205 | }, | ||
206 | }; | ||
207 | |||
208 | static struct omap_hwmod am43xx_ehrpwm4_hwmod = { | ||
209 | .name = "ehrpwm4", | ||
210 | .class = &am33xx_ehrpwm_hwmod_class, | ||
211 | .clkdm_name = "l4ls_clkdm", | ||
212 | .main_clk = "l4ls_gclk", | ||
213 | }; | ||
214 | |||
215 | static struct omap_hwmod am43xx_epwmss5_hwmod = { | ||
216 | .name = "epwmss5", | ||
217 | .class = &am33xx_epwmss_hwmod_class, | ||
218 | .clkdm_name = "l4ls_clkdm", | ||
219 | .main_clk = "l4ls_gclk", | ||
220 | .prcm = { | ||
221 | .omap4 = { | ||
222 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET, | ||
223 | .modulemode = MODULEMODE_SWCTRL, | ||
224 | }, | ||
225 | }, | ||
226 | }; | ||
227 | |||
228 | static struct omap_hwmod am43xx_ehrpwm5_hwmod = { | ||
229 | .name = "ehrpwm5", | ||
230 | .class = &am33xx_ehrpwm_hwmod_class, | ||
231 | .clkdm_name = "l4ls_clkdm", | ||
232 | .main_clk = "l4ls_gclk", | ||
233 | }; | ||
234 | |||
235 | static struct omap_hwmod am43xx_spi2_hwmod = { | ||
236 | .name = "spi2", | ||
237 | .class = &am33xx_spi_hwmod_class, | ||
238 | .clkdm_name = "l4ls_clkdm", | ||
239 | .main_clk = "dpll_per_m2_div4_ck", | ||
240 | .prcm = { | ||
241 | .omap4 = { | ||
242 | .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET, | ||
243 | .modulemode = MODULEMODE_SWCTRL, | ||
244 | }, | ||
245 | }, | ||
246 | .dev_attr = &mcspi_attrib, | ||
247 | }; | ||
248 | |||
249 | static struct omap_hwmod am43xx_spi3_hwmod = { | ||
250 | .name = "spi3", | ||
251 | .class = &am33xx_spi_hwmod_class, | ||
252 | .clkdm_name = "l4ls_clkdm", | ||
253 | .main_clk = "dpll_per_m2_div4_ck", | ||
254 | .prcm = { | ||
255 | .omap4 = { | ||
256 | .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET, | ||
257 | .modulemode = MODULEMODE_SWCTRL, | ||
258 | }, | ||
259 | }, | ||
260 | .dev_attr = &mcspi_attrib, | ||
261 | }; | ||
262 | |||
263 | static struct omap_hwmod am43xx_spi4_hwmod = { | ||
264 | .name = "spi4", | ||
265 | .class = &am33xx_spi_hwmod_class, | ||
266 | .clkdm_name = "l4ls_clkdm", | ||
267 | .main_clk = "dpll_per_m2_div4_ck", | ||
268 | .prcm = { | ||
269 | .omap4 = { | ||
270 | .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET, | ||
271 | .modulemode = MODULEMODE_SWCTRL, | ||
272 | }, | ||
273 | }, | ||
274 | .dev_attr = &mcspi_attrib, | ||
275 | }; | ||
276 | |||
277 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | ||
278 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | ||
279 | }; | ||
280 | |||
281 | static struct omap_hwmod am43xx_gpio4_hwmod = { | ||
282 | .name = "gpio5", | ||
283 | .class = &am33xx_gpio_hwmod_class, | ||
284 | .clkdm_name = "l4ls_clkdm", | ||
285 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
286 | .main_clk = "l4ls_gclk", | ||
287 | .prcm = { | ||
288 | .omap4 = { | ||
289 | .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET, | ||
290 | .modulemode = MODULEMODE_SWCTRL, | ||
291 | }, | ||
292 | }, | ||
293 | .opt_clks = gpio4_opt_clks, | ||
294 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | ||
295 | .dev_attr = &gpio_dev_attr, | ||
296 | }; | ||
297 | |||
298 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | ||
299 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | ||
300 | }; | ||
301 | |||
302 | static struct omap_hwmod am43xx_gpio5_hwmod = { | ||
303 | .name = "gpio6", | ||
304 | .class = &am33xx_gpio_hwmod_class, | ||
305 | .clkdm_name = "l4ls_clkdm", | ||
306 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
307 | .main_clk = "l4ls_gclk", | ||
308 | .prcm = { | ||
309 | .omap4 = { | ||
310 | .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET, | ||
311 | .modulemode = MODULEMODE_SWCTRL, | ||
312 | }, | ||
313 | }, | ||
314 | .opt_clks = gpio5_opt_clks, | ||
315 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | ||
316 | .dev_attr = &gpio_dev_attr, | ||
317 | }; | ||
318 | |||
319 | static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { | ||
320 | .name = "ocp2scp", | ||
321 | }; | ||
322 | |||
323 | static struct omap_hwmod am43xx_ocp2scp0_hwmod = { | ||
324 | .name = "ocp2scp0", | ||
325 | .class = &am43xx_ocp2scp_hwmod_class, | ||
326 | .clkdm_name = "l4ls_clkdm", | ||
327 | .main_clk = "l4ls_gclk", | ||
328 | .prcm = { | ||
329 | .omap4 = { | ||
330 | .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET, | ||
331 | .modulemode = MODULEMODE_SWCTRL, | ||
332 | }, | ||
333 | }, | ||
334 | }; | ||
335 | |||
336 | static struct omap_hwmod am43xx_ocp2scp1_hwmod = { | ||
337 | .name = "ocp2scp1", | ||
338 | .class = &am43xx_ocp2scp_hwmod_class, | ||
339 | .clkdm_name = "l4ls_clkdm", | ||
340 | .main_clk = "l4ls_gclk", | ||
341 | .prcm = { | ||
342 | .omap4 = { | ||
343 | .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET, | ||
344 | .modulemode = MODULEMODE_SWCTRL, | ||
345 | }, | ||
346 | }, | ||
347 | }; | ||
348 | |||
349 | static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { | ||
350 | .rev_offs = 0x0000, | ||
351 | .sysc_offs = 0x0010, | ||
352 | .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | | ||
353 | SYSC_HAS_SIDLEMODE), | ||
354 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
355 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | | ||
356 | MSTANDBY_NO | MSTANDBY_SMART | | ||
357 | MSTANDBY_SMART_WKUP), | ||
358 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
359 | }; | ||
360 | |||
361 | static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = { | ||
362 | .name = "usb_otg_ss", | ||
363 | .sysc = &am43xx_usb_otg_ss_sysc, | ||
364 | }; | ||
365 | |||
366 | static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = { | ||
367 | .name = "usb_otg_ss0", | ||
368 | .class = &am43xx_usb_otg_ss_hwmod_class, | ||
369 | .clkdm_name = "l3s_clkdm", | ||
370 | .main_clk = "l3s_gclk", | ||
371 | .prcm = { | ||
372 | .omap4 = { | ||
373 | .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET, | ||
374 | .modulemode = MODULEMODE_SWCTRL, | ||
375 | }, | ||
376 | }, | ||
377 | }; | ||
378 | |||
379 | static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { | ||
380 | .name = "usb_otg_ss1", | ||
381 | .class = &am43xx_usb_otg_ss_hwmod_class, | ||
382 | .clkdm_name = "l3s_clkdm", | ||
383 | .main_clk = "l3s_gclk", | ||
384 | .prcm = { | ||
385 | .omap4 = { | ||
386 | .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET, | ||
387 | .modulemode = MODULEMODE_SWCTRL, | ||
388 | }, | ||
389 | }, | ||
390 | }; | ||
391 | |||
392 | static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = { | ||
393 | .sysc_offs = 0x0010, | ||
394 | .sysc_flags = SYSC_HAS_SIDLEMODE, | ||
395 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
396 | SIDLE_SMART_WKUP), | ||
397 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
398 | }; | ||
399 | |||
400 | static struct omap_hwmod_class am43xx_qspi_hwmod_class = { | ||
401 | .name = "qspi", | ||
402 | .sysc = &am43xx_qspi_sysc, | ||
403 | }; | ||
404 | |||
405 | static struct omap_hwmod am43xx_qspi_hwmod = { | ||
406 | .name = "qspi", | ||
407 | .class = &am43xx_qspi_hwmod_class, | ||
408 | .clkdm_name = "l3s_clkdm", | ||
409 | .main_clk = "l3s_gclk", | ||
410 | .prcm = { | ||
411 | .omap4 = { | ||
412 | .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET, | ||
413 | .modulemode = MODULEMODE_SWCTRL, | ||
414 | }, | ||
415 | }, | ||
416 | }; | ||
417 | |||
418 | /* Interfaces */ | ||
419 | static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { | ||
420 | .master = &am33xx_l3_main_hwmod, | ||
421 | .slave = &am43xx_l4_hs_hwmod, | ||
422 | .clk = "l3s_gclk", | ||
423 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
424 | }; | ||
425 | |||
426 | static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = { | ||
427 | .master = &am43xx_wkup_m3_hwmod, | ||
428 | .slave = &am33xx_l4_wkup_hwmod, | ||
429 | .clk = "sys_clkin_ck", | ||
430 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
431 | }; | ||
432 | |||
433 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = { | ||
434 | .master = &am33xx_l4_wkup_hwmod, | ||
435 | .slave = &am43xx_wkup_m3_hwmod, | ||
436 | .clk = "sys_clkin_ck", | ||
437 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
438 | }; | ||
439 | |||
440 | static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = { | ||
441 | .master = &am33xx_l3_main_hwmod, | ||
442 | .slave = &am33xx_pruss_hwmod, | ||
443 | .clk = "dpll_core_m4_ck", | ||
444 | .user = OCP_USER_MPU, | ||
445 | }; | ||
446 | |||
447 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { | ||
448 | .master = &am33xx_l4_wkup_hwmod, | ||
449 | .slave = &am33xx_smartreflex0_hwmod, | ||
450 | .clk = "sys_clkin_ck", | ||
451 | .user = OCP_USER_MPU, | ||
452 | }; | ||
453 | |||
454 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { | ||
455 | .master = &am33xx_l4_wkup_hwmod, | ||
456 | .slave = &am33xx_smartreflex1_hwmod, | ||
457 | .clk = "sys_clkin_ck", | ||
458 | .user = OCP_USER_MPU, | ||
459 | }; | ||
460 | |||
461 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { | ||
462 | .master = &am33xx_l4_wkup_hwmod, | ||
463 | .slave = &am43xx_control_hwmod, | ||
464 | .clk = "sys_clkin_ck", | ||
465 | .user = OCP_USER_MPU, | ||
466 | }; | ||
467 | |||
468 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = { | ||
469 | .master = &am33xx_l4_wkup_hwmod, | ||
470 | .slave = &am33xx_i2c1_hwmod, | ||
471 | .clk = "sys_clkin_ck", | ||
472 | .user = OCP_USER_MPU, | ||
473 | }; | ||
474 | |||
475 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = { | ||
476 | .master = &am33xx_l4_wkup_hwmod, | ||
477 | .slave = &am43xx_gpio0_hwmod, | ||
478 | .clk = "sys_clkin_ck", | ||
479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
480 | }; | ||
481 | |||
482 | static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = { | ||
483 | .master = &am43xx_l4_hs_hwmod, | ||
484 | .slave = &am33xx_cpgmac0_hwmod, | ||
485 | .clk = "cpsw_125mhz_gclk", | ||
486 | .user = OCP_USER_MPU, | ||
487 | }; | ||
488 | |||
489 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { | ||
490 | .master = &am33xx_l4_wkup_hwmod, | ||
491 | .slave = &am33xx_timer1_hwmod, | ||
492 | .clk = "sys_clkin_ck", | ||
493 | .user = OCP_USER_MPU, | ||
494 | }; | ||
495 | |||
496 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = { | ||
497 | .master = &am33xx_l4_wkup_hwmod, | ||
498 | .slave = &am33xx_uart1_hwmod, | ||
499 | .clk = "sys_clkin_ck", | ||
500 | .user = OCP_USER_MPU, | ||
501 | }; | ||
502 | |||
503 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = { | ||
504 | .master = &am33xx_l4_wkup_hwmod, | ||
505 | .slave = &am33xx_wd_timer1_hwmod, | ||
506 | .clk = "sys_clkin_ck", | ||
507 | .user = OCP_USER_MPU, | ||
508 | }; | ||
509 | |||
510 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = { | ||
511 | .master = &am33xx_l4_wkup_hwmod, | ||
512 | .slave = &am43xx_synctimer_hwmod, | ||
513 | .clk = "sys_clkin_ck", | ||
514 | .user = OCP_USER_MPU, | ||
515 | }; | ||
516 | |||
517 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = { | ||
518 | .master = &am33xx_l4_ls_hwmod, | ||
519 | .slave = &am43xx_timer8_hwmod, | ||
520 | .clk = "l4ls_gclk", | ||
521 | .user = OCP_USER_MPU, | ||
522 | }; | ||
523 | |||
524 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = { | ||
525 | .master = &am33xx_l4_ls_hwmod, | ||
526 | .slave = &am43xx_timer9_hwmod, | ||
527 | .clk = "l4ls_gclk", | ||
528 | .user = OCP_USER_MPU, | ||
529 | }; | ||
530 | |||
531 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = { | ||
532 | .master = &am33xx_l4_ls_hwmod, | ||
533 | .slave = &am43xx_timer10_hwmod, | ||
534 | .clk = "l4ls_gclk", | ||
535 | .user = OCP_USER_MPU, | ||
536 | }; | ||
537 | |||
538 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = { | ||
539 | .master = &am33xx_l4_ls_hwmod, | ||
540 | .slave = &am43xx_timer11_hwmod, | ||
541 | .clk = "l4ls_gclk", | ||
542 | .user = OCP_USER_MPU, | ||
543 | }; | ||
544 | |||
545 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = { | ||
546 | .master = &am33xx_l4_ls_hwmod, | ||
547 | .slave = &am43xx_epwmss3_hwmod, | ||
548 | .clk = "l4ls_gclk", | ||
549 | .user = OCP_USER_MPU, | ||
550 | }; | ||
551 | |||
552 | static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = { | ||
553 | .master = &am43xx_epwmss3_hwmod, | ||
554 | .slave = &am43xx_ehrpwm3_hwmod, | ||
555 | .clk = "l4ls_gclk", | ||
556 | .user = OCP_USER_MPU, | ||
557 | }; | ||
558 | |||
559 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { | ||
560 | .master = &am33xx_l4_ls_hwmod, | ||
561 | .slave = &am43xx_epwmss4_hwmod, | ||
562 | .clk = "l4ls_gclk", | ||
563 | .user = OCP_USER_MPU, | ||
564 | }; | ||
565 | |||
566 | static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = { | ||
567 | .master = &am43xx_epwmss4_hwmod, | ||
568 | .slave = &am43xx_ehrpwm4_hwmod, | ||
569 | .clk = "l4ls_gclk", | ||
570 | .user = OCP_USER_MPU, | ||
571 | }; | ||
572 | |||
573 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { | ||
574 | .master = &am33xx_l4_ls_hwmod, | ||
575 | .slave = &am43xx_epwmss5_hwmod, | ||
576 | .clk = "l4ls_gclk", | ||
577 | .user = OCP_USER_MPU, | ||
578 | }; | ||
579 | |||
580 | static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = { | ||
581 | .master = &am43xx_epwmss5_hwmod, | ||
582 | .slave = &am43xx_ehrpwm5_hwmod, | ||
583 | .clk = "l4ls_gclk", | ||
584 | .user = OCP_USER_MPU, | ||
585 | }; | ||
586 | |||
587 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { | ||
588 | .master = &am33xx_l4_ls_hwmod, | ||
589 | .slave = &am43xx_spi2_hwmod, | ||
590 | .clk = "l4ls_gclk", | ||
591 | .user = OCP_USER_MPU, | ||
592 | }; | ||
593 | |||
594 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = { | ||
595 | .master = &am33xx_l4_ls_hwmod, | ||
596 | .slave = &am43xx_spi3_hwmod, | ||
597 | .clk = "l4ls_gclk", | ||
598 | .user = OCP_USER_MPU, | ||
599 | }; | ||
600 | |||
601 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = { | ||
602 | .master = &am33xx_l4_ls_hwmod, | ||
603 | .slave = &am43xx_spi4_hwmod, | ||
604 | .clk = "l4ls_gclk", | ||
605 | .user = OCP_USER_MPU, | ||
606 | }; | ||
607 | |||
608 | static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = { | ||
609 | .master = &am33xx_l4_ls_hwmod, | ||
610 | .slave = &am43xx_gpio4_hwmod, | ||
611 | .clk = "l4ls_gclk", | ||
612 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
613 | }; | ||
614 | |||
615 | static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = { | ||
616 | .master = &am33xx_l4_ls_hwmod, | ||
617 | .slave = &am43xx_gpio5_hwmod, | ||
618 | .clk = "l4ls_gclk", | ||
619 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
620 | }; | ||
621 | |||
622 | static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = { | ||
623 | .master = &am33xx_l4_ls_hwmod, | ||
624 | .slave = &am43xx_ocp2scp0_hwmod, | ||
625 | .clk = "l4ls_gclk", | ||
626 | .user = OCP_USER_MPU, | ||
627 | }; | ||
628 | |||
629 | static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = { | ||
630 | .master = &am33xx_l4_ls_hwmod, | ||
631 | .slave = &am43xx_ocp2scp1_hwmod, | ||
632 | .clk = "l4ls_gclk", | ||
633 | .user = OCP_USER_MPU, | ||
634 | }; | ||
635 | |||
636 | static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { | ||
637 | .master = &am33xx_l3_s_hwmod, | ||
638 | .slave = &am43xx_usb_otg_ss0_hwmod, | ||
639 | .clk = "l3s_gclk", | ||
640 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
641 | }; | ||
642 | |||
643 | static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { | ||
644 | .master = &am33xx_l3_s_hwmod, | ||
645 | .slave = &am43xx_usb_otg_ss1_hwmod, | ||
646 | .clk = "l3s_gclk", | ||
647 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
648 | }; | ||
649 | |||
650 | static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { | ||
651 | .master = &am33xx_l3_s_hwmod, | ||
652 | .slave = &am43xx_qspi_hwmod, | ||
653 | .clk = "l3s_gclk", | ||
654 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
655 | }; | ||
656 | |||
657 | static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { | ||
658 | &am33xx_l4_wkup__synctimer, | ||
659 | &am43xx_l4_ls__timer8, | ||
660 | &am43xx_l4_ls__timer9, | ||
661 | &am43xx_l4_ls__timer10, | ||
662 | &am43xx_l4_ls__timer11, | ||
663 | &am43xx_l4_ls__epwmss3, | ||
664 | &am43xx_epwmss3__ehrpwm3, | ||
665 | &am43xx_l4_ls__epwmss4, | ||
666 | &am43xx_epwmss4__ehrpwm4, | ||
667 | &am43xx_l4_ls__epwmss5, | ||
668 | &am43xx_epwmss5__ehrpwm5, | ||
669 | &am43xx_l4_ls__mcspi2, | ||
670 | &am43xx_l4_ls__mcspi3, | ||
671 | &am43xx_l4_ls__mcspi4, | ||
672 | &am43xx_l4_ls__gpio4, | ||
673 | &am43xx_l4_ls__gpio5, | ||
674 | &am43xx_l3_main__pruss, | ||
675 | &am33xx_mpu__l3_main, | ||
676 | &am33xx_mpu__prcm, | ||
677 | &am33xx_l3_s__l4_ls, | ||
678 | &am33xx_l3_s__l4_wkup, | ||
679 | &am43xx_l3_main__l4_hs, | ||
680 | &am33xx_l3_main__l3_s, | ||
681 | &am33xx_l3_main__l3_instr, | ||
682 | &am33xx_l3_main__gfx, | ||
683 | &am33xx_l3_s__l3_main, | ||
684 | &am33xx_pruss__l3_main, | ||
685 | &am43xx_wkup_m3__l4_wkup, | ||
686 | &am33xx_gfx__l3_main, | ||
687 | &am43xx_l4_wkup__wkup_m3, | ||
688 | &am43xx_l4_wkup__control, | ||
689 | &am43xx_l4_wkup__smartreflex0, | ||
690 | &am43xx_l4_wkup__smartreflex1, | ||
691 | &am43xx_l4_wkup__uart1, | ||
692 | &am43xx_l4_wkup__timer1, | ||
693 | &am43xx_l4_wkup__i2c1, | ||
694 | &am43xx_l4_wkup__gpio0, | ||
695 | &am43xx_l4_wkup__wd_timer1, | ||
696 | &am43xx_l3_s__qspi, | ||
697 | &am33xx_l4_per__dcan0, | ||
698 | &am33xx_l4_per__dcan1, | ||
699 | &am33xx_l4_per__gpio1, | ||
700 | &am33xx_l4_per__gpio2, | ||
701 | &am33xx_l4_per__gpio3, | ||
702 | &am33xx_l4_per__i2c2, | ||
703 | &am33xx_l4_per__i2c3, | ||
704 | &am33xx_l4_per__mailbox, | ||
705 | &am33xx_l4_ls__mcasp0, | ||
706 | &am33xx_l4_ls__mcasp1, | ||
707 | &am33xx_l4_ls__mmc0, | ||
708 | &am33xx_l4_ls__mmc1, | ||
709 | &am33xx_l3_s__mmc2, | ||
710 | &am33xx_l4_ls__timer2, | ||
711 | &am33xx_l4_ls__timer3, | ||
712 | &am33xx_l4_ls__timer4, | ||
713 | &am33xx_l4_ls__timer5, | ||
714 | &am33xx_l4_ls__timer6, | ||
715 | &am33xx_l4_ls__timer7, | ||
716 | &am33xx_l3_main__tpcc, | ||
717 | &am33xx_l4_ls__uart2, | ||
718 | &am33xx_l4_ls__uart3, | ||
719 | &am33xx_l4_ls__uart4, | ||
720 | &am33xx_l4_ls__uart5, | ||
721 | &am33xx_l4_ls__uart6, | ||
722 | &am33xx_l4_ls__elm, | ||
723 | &am33xx_l4_ls__epwmss0, | ||
724 | &am33xx_epwmss0__ecap0, | ||
725 | &am33xx_epwmss0__eqep0, | ||
726 | &am33xx_epwmss0__ehrpwm0, | ||
727 | &am33xx_l4_ls__epwmss1, | ||
728 | &am33xx_epwmss1__ecap1, | ||
729 | &am33xx_epwmss1__eqep1, | ||
730 | &am33xx_epwmss1__ehrpwm1, | ||
731 | &am33xx_l4_ls__epwmss2, | ||
732 | &am33xx_epwmss2__ecap2, | ||
733 | &am33xx_epwmss2__eqep2, | ||
734 | &am33xx_epwmss2__ehrpwm2, | ||
735 | &am33xx_l3_s__gpmc, | ||
736 | &am33xx_l4_ls__mcspi0, | ||
737 | &am33xx_l4_ls__mcspi1, | ||
738 | &am33xx_l3_main__tptc0, | ||
739 | &am33xx_l3_main__tptc1, | ||
740 | &am33xx_l3_main__tptc2, | ||
741 | &am33xx_l3_main__ocmc, | ||
742 | &am43xx_l4_hs__cpgmac0, | ||
743 | &am33xx_cpgmac0__mdio, | ||
744 | &am33xx_l3_main__sha0, | ||
745 | &am33xx_l3_main__aes0, | ||
746 | &am43xx_l4_ls__ocp2scp0, | ||
747 | &am43xx_l4_ls__ocp2scp1, | ||
748 | &am43xx_l3_s__usbotgss0, | ||
749 | &am43xx_l3_s__usbotgss1, | ||
750 | NULL, | ||
751 | }; | ||
752 | |||
753 | int __init am43xx_hwmod_init(void) | ||
754 | { | ||
755 | omap_hwmod_am43xx_reg(); | ||
756 | omap_hwmod_init(); | ||
757 | return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); | ||
758 | } | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 9c3b504477d7..1e5b12cb8246 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -914,7 +914,7 @@ static struct omap_hwmod omap44xx_emif1_hwmod = { | |||
914 | .name = "emif1", | 914 | .name = "emif1", |
915 | .class = &omap44xx_emif_hwmod_class, | 915 | .class = &omap44xx_emif_hwmod_class, |
916 | .clkdm_name = "l3_emif_clkdm", | 916 | .clkdm_name = "l3_emif_clkdm", |
917 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 917 | .flags = HWMOD_INIT_NO_IDLE, |
918 | .main_clk = "ddrphy_ck", | 918 | .main_clk = "ddrphy_ck", |
919 | .prcm = { | 919 | .prcm = { |
920 | .omap4 = { | 920 | .omap4 = { |
@@ -930,7 +930,7 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { | |||
930 | .name = "emif2", | 930 | .name = "emif2", |
931 | .class = &omap44xx_emif_hwmod_class, | 931 | .class = &omap44xx_emif_hwmod_class, |
932 | .clkdm_name = "l3_emif_clkdm", | 932 | .clkdm_name = "l3_emif_clkdm", |
933 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 933 | .flags = HWMOD_INIT_NO_IDLE, |
934 | .main_clk = "ddrphy_ck", | 934 | .main_clk = "ddrphy_ck", |
935 | .prcm = { | 935 | .prcm = { |
936 | .omap4 = { | 936 | .omap4 = { |
@@ -2193,7 +2193,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { | |||
2193 | .name = "mpu", | 2193 | .name = "mpu", |
2194 | .class = &omap44xx_mpu_hwmod_class, | 2194 | .class = &omap44xx_mpu_hwmod_class, |
2195 | .clkdm_name = "mpuss_clkdm", | 2195 | .clkdm_name = "mpuss_clkdm", |
2196 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 2196 | .flags = HWMOD_INIT_NO_IDLE, |
2197 | .main_clk = "dpll_mpu_m2_ck", | 2197 | .main_clk = "dpll_mpu_m2_ck", |
2198 | .prcm = { | 2198 | .prcm = { |
2199 | .omap4 = { | 2199 | .omap4 = { |
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index cde415570e04..9e08d6994a0b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c | |||
@@ -352,7 +352,7 @@ static struct omap_hwmod omap54xx_emif1_hwmod = { | |||
352 | .name = "emif1", | 352 | .name = "emif1", |
353 | .class = &omap54xx_emif_hwmod_class, | 353 | .class = &omap54xx_emif_hwmod_class, |
354 | .clkdm_name = "emif_clkdm", | 354 | .clkdm_name = "emif_clkdm", |
355 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 355 | .flags = HWMOD_INIT_NO_IDLE, |
356 | .main_clk = "dpll_core_h11x2_ck", | 356 | .main_clk = "dpll_core_h11x2_ck", |
357 | .prcm = { | 357 | .prcm = { |
358 | .omap4 = { | 358 | .omap4 = { |
@@ -368,7 +368,7 @@ static struct omap_hwmod omap54xx_emif2_hwmod = { | |||
368 | .name = "emif2", | 368 | .name = "emif2", |
369 | .class = &omap54xx_emif_hwmod_class, | 369 | .class = &omap54xx_emif_hwmod_class, |
370 | .clkdm_name = "emif_clkdm", | 370 | .clkdm_name = "emif_clkdm", |
371 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 371 | .flags = HWMOD_INIT_NO_IDLE, |
372 | .main_clk = "dpll_core_h11x2_ck", | 372 | .main_clk = "dpll_core_h11x2_ck", |
373 | .prcm = { | 373 | .prcm = { |
374 | .omap4 = { | 374 | .omap4 = { |
@@ -1135,7 +1135,7 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { | |||
1135 | .name = "mpu", | 1135 | .name = "mpu", |
1136 | .class = &omap54xx_mpu_hwmod_class, | 1136 | .class = &omap54xx_mpu_hwmod_class, |
1137 | .clkdm_name = "mpu_clkdm", | 1137 | .clkdm_name = "mpu_clkdm", |
1138 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 1138 | .flags = HWMOD_INIT_NO_IDLE, |
1139 | .main_clk = "dpll_mpu_m2_ck", | 1139 | .main_clk = "dpll_mpu_m2_ck", |
1140 | .prcm = { | 1140 | .prcm = { |
1141 | .omap4 = { | 1141 | .omap4 = { |
@@ -1146,6 +1146,77 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { | |||
1146 | }; | 1146 | }; |
1147 | 1147 | ||
1148 | /* | 1148 | /* |
1149 | * 'spinlock' class | ||
1150 | * spinlock provides hardware assistance for synchronizing the processes | ||
1151 | * running on multiple processors | ||
1152 | */ | ||
1153 | |||
1154 | static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = { | ||
1155 | .rev_offs = 0x0000, | ||
1156 | .sysc_offs = 0x0010, | ||
1157 | .syss_offs = 0x0014, | ||
1158 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
1159 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
1160 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
1161 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1162 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1163 | }; | ||
1164 | |||
1165 | static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = { | ||
1166 | .name = "spinlock", | ||
1167 | .sysc = &omap54xx_spinlock_sysc, | ||
1168 | }; | ||
1169 | |||
1170 | /* spinlock */ | ||
1171 | static struct omap_hwmod omap54xx_spinlock_hwmod = { | ||
1172 | .name = "spinlock", | ||
1173 | .class = &omap54xx_spinlock_hwmod_class, | ||
1174 | .clkdm_name = "l4cfg_clkdm", | ||
1175 | .prcm = { | ||
1176 | .omap4 = { | ||
1177 | .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, | ||
1178 | .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, | ||
1179 | }, | ||
1180 | }, | ||
1181 | }; | ||
1182 | |||
1183 | /* | ||
1184 | * 'ocp2scp' class | ||
1185 | * bridge to transform ocp interface protocol to scp (serial control port) | ||
1186 | * protocol | ||
1187 | */ | ||
1188 | |||
1189 | static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = { | ||
1190 | .rev_offs = 0x0000, | ||
1191 | .sysc_offs = 0x0010, | ||
1192 | .syss_offs = 0x0014, | ||
1193 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | ||
1194 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
1195 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1196 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1197 | }; | ||
1198 | |||
1199 | static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = { | ||
1200 | .name = "ocp2scp", | ||
1201 | .sysc = &omap54xx_ocp2scp_sysc, | ||
1202 | }; | ||
1203 | |||
1204 | /* ocp2scp1 */ | ||
1205 | static struct omap_hwmod omap54xx_ocp2scp1_hwmod = { | ||
1206 | .name = "ocp2scp1", | ||
1207 | .class = &omap54xx_ocp2scp_hwmod_class, | ||
1208 | .clkdm_name = "l3init_clkdm", | ||
1209 | .main_clk = "l4_root_clk_div", | ||
1210 | .prcm = { | ||
1211 | .omap4 = { | ||
1212 | .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, | ||
1213 | .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, | ||
1214 | .modulemode = MODULEMODE_HWCTRL, | ||
1215 | }, | ||
1216 | }, | ||
1217 | }; | ||
1218 | |||
1219 | /* | ||
1149 | * 'timer' class | 1220 | * 'timer' class |
1150 | * general purpose timer module with accurate 1ms tick | 1221 | * general purpose timer module with accurate 1ms tick |
1151 | * This class contains several variants: ['timer_1ms', 'timer'] | 1222 | * This class contains several variants: ['timer_1ms', 'timer'] |
@@ -1465,6 +1536,123 @@ static struct omap_hwmod omap54xx_uart6_hwmod = { | |||
1465 | }; | 1536 | }; |
1466 | 1537 | ||
1467 | /* | 1538 | /* |
1539 | * 'usb_host_hs' class | ||
1540 | * high-speed multi-port usb host controller | ||
1541 | */ | ||
1542 | |||
1543 | static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = { | ||
1544 | .rev_offs = 0x0000, | ||
1545 | .sysc_offs = 0x0010, | ||
1546 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | ||
1547 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | ||
1548 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
1549 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | ||
1550 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | ||
1551 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
1552 | }; | ||
1553 | |||
1554 | static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = { | ||
1555 | .name = "usb_host_hs", | ||
1556 | .sysc = &omap54xx_usb_host_hs_sysc, | ||
1557 | }; | ||
1558 | |||
1559 | static struct omap_hwmod omap54xx_usb_host_hs_hwmod = { | ||
1560 | .name = "usb_host_hs", | ||
1561 | .class = &omap54xx_usb_host_hs_hwmod_class, | ||
1562 | .clkdm_name = "l3init_clkdm", | ||
1563 | /* | ||
1564 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | ||
1565 | * id: i660 | ||
1566 | * | ||
1567 | * Description: | ||
1568 | * In the following configuration : | ||
1569 | * - USBHOST module is set to smart-idle mode | ||
1570 | * - PRCM asserts idle_req to the USBHOST module ( This typically | ||
1571 | * happens when the system is going to a low power mode : all ports | ||
1572 | * have been suspended, the master part of the USBHOST module has | ||
1573 | * entered the standby state, and SW has cut the functional clocks) | ||
1574 | * - an USBHOST interrupt occurs before the module is able to answer | ||
1575 | * idle_ack, typically a remote wakeup IRQ. | ||
1576 | * Then the USB HOST module will enter a deadlock situation where it | ||
1577 | * is no more accessible nor functional. | ||
1578 | * | ||
1579 | * Workaround: | ||
1580 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | ||
1581 | */ | ||
1582 | |||
1583 | /* | ||
1584 | * Errata: USB host EHCI may stall when entering smart-standby mode | ||
1585 | * Id: i571 | ||
1586 | * | ||
1587 | * Description: | ||
1588 | * When the USBHOST module is set to smart-standby mode, and when it is | ||
1589 | * ready to enter the standby state (i.e. all ports are suspended and | ||
1590 | * all attached devices are in suspend mode), then it can wrongly assert | ||
1591 | * the Mstandby signal too early while there are still some residual OCP | ||
1592 | * transactions ongoing. If this condition occurs, the internal state | ||
1593 | * machine may go to an undefined state and the USB link may be stuck | ||
1594 | * upon the next resume. | ||
1595 | * | ||
1596 | * Workaround: | ||
1597 | * Don't use smart standby; use only force standby, | ||
1598 | * hence HWMOD_SWSUP_MSTANDBY | ||
1599 | */ | ||
1600 | |||
1601 | /* | ||
1602 | * During system boot; If the hwmod framework resets the module | ||
1603 | * the module will have smart idle settings; which can lead to deadlock | ||
1604 | * (above Errata Id:i660); so, dont reset the module during boot; | ||
1605 | * Use HWMOD_INIT_NO_RESET. | ||
1606 | */ | ||
1607 | |||
1608 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | ||
1609 | HWMOD_INIT_NO_RESET, | ||
1610 | .main_clk = "l3init_60m_fclk", | ||
1611 | .prcm = { | ||
1612 | .omap4 = { | ||
1613 | .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET, | ||
1614 | .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET, | ||
1615 | .modulemode = MODULEMODE_SWCTRL, | ||
1616 | }, | ||
1617 | }, | ||
1618 | }; | ||
1619 | |||
1620 | /* | ||
1621 | * 'usb_tll_hs' class | ||
1622 | * usb_tll_hs module is the adapter on the usb_host_hs ports | ||
1623 | */ | ||
1624 | |||
1625 | static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = { | ||
1626 | .rev_offs = 0x0000, | ||
1627 | .sysc_offs = 0x0010, | ||
1628 | .syss_offs = 0x0014, | ||
1629 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
1630 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
1631 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
1632 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
1633 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
1634 | }; | ||
1635 | |||
1636 | static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = { | ||
1637 | .name = "usb_tll_hs", | ||
1638 | .sysc = &omap54xx_usb_tll_hs_sysc, | ||
1639 | }; | ||
1640 | |||
1641 | static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = { | ||
1642 | .name = "usb_tll_hs", | ||
1643 | .class = &omap54xx_usb_tll_hs_hwmod_class, | ||
1644 | .clkdm_name = "l3init_clkdm", | ||
1645 | .main_clk = "l4_root_clk_div", | ||
1646 | .prcm = { | ||
1647 | .omap4 = { | ||
1648 | .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET, | ||
1649 | .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET, | ||
1650 | .modulemode = MODULEMODE_HWCTRL, | ||
1651 | }, | ||
1652 | }, | ||
1653 | }; | ||
1654 | |||
1655 | /* | ||
1468 | * 'usb_otg_ss' class | 1656 | * 'usb_otg_ss' class |
1469 | * 2.0 super speed (usb_otg_ss) controller | 1657 | * 2.0 super speed (usb_otg_ss) controller |
1470 | */ | 1658 | */ |
@@ -1960,6 +2148,22 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { | |||
1960 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 2148 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1961 | }; | 2149 | }; |
1962 | 2150 | ||
2151 | /* l4_cfg -> spinlock */ | ||
2152 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = { | ||
2153 | .master = &omap54xx_l4_cfg_hwmod, | ||
2154 | .slave = &omap54xx_spinlock_hwmod, | ||
2155 | .clk = "l4_root_clk_div", | ||
2156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2157 | }; | ||
2158 | |||
2159 | /* l4_cfg -> ocp2scp1 */ | ||
2160 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = { | ||
2161 | .master = &omap54xx_l4_cfg_hwmod, | ||
2162 | .slave = &omap54xx_ocp2scp1_hwmod, | ||
2163 | .clk = "l4_root_clk_div", | ||
2164 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2165 | }; | ||
2166 | |||
1963 | /* l4_wkup -> timer1 */ | 2167 | /* l4_wkup -> timer1 */ |
1964 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { | 2168 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { |
1965 | .master = &omap54xx_l4_wkup_hwmod, | 2169 | .master = &omap54xx_l4_wkup_hwmod, |
@@ -2096,6 +2300,22 @@ static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = { | |||
2096 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 2300 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2097 | }; | 2301 | }; |
2098 | 2302 | ||
2303 | /* l4_cfg -> usb_host_hs */ | ||
2304 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { | ||
2305 | .master = &omap54xx_l4_cfg_hwmod, | ||
2306 | .slave = &omap54xx_usb_host_hs_hwmod, | ||
2307 | .clk = "l3_iclk_div", | ||
2308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2309 | }; | ||
2310 | |||
2311 | /* l4_cfg -> usb_tll_hs */ | ||
2312 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = { | ||
2313 | .master = &omap54xx_l4_cfg_hwmod, | ||
2314 | .slave = &omap54xx_usb_tll_hs_hwmod, | ||
2315 | .clk = "l4_root_clk_div", | ||
2316 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2317 | }; | ||
2318 | |||
2099 | /* l4_cfg -> usb_otg_ss */ | 2319 | /* l4_cfg -> usb_otg_ss */ |
2100 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { | 2320 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { |
2101 | .master = &omap54xx_l4_cfg_hwmod, | 2321 | .master = &omap54xx_l4_cfg_hwmod, |
@@ -2163,6 +2383,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |||
2163 | &omap54xx_l4_per__mmc4, | 2383 | &omap54xx_l4_per__mmc4, |
2164 | &omap54xx_l4_per__mmc5, | 2384 | &omap54xx_l4_per__mmc5, |
2165 | &omap54xx_l4_cfg__mpu, | 2385 | &omap54xx_l4_cfg__mpu, |
2386 | &omap54xx_l4_cfg__spinlock, | ||
2387 | &omap54xx_l4_cfg__ocp2scp1, | ||
2166 | &omap54xx_l4_wkup__timer1, | 2388 | &omap54xx_l4_wkup__timer1, |
2167 | &omap54xx_l4_per__timer2, | 2389 | &omap54xx_l4_per__timer2, |
2168 | &omap54xx_l4_per__timer3, | 2390 | &omap54xx_l4_per__timer3, |
@@ -2180,6 +2402,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |||
2180 | &omap54xx_l4_per__uart4, | 2402 | &omap54xx_l4_per__uart4, |
2181 | &omap54xx_l4_per__uart5, | 2403 | &omap54xx_l4_per__uart5, |
2182 | &omap54xx_l4_per__uart6, | 2404 | &omap54xx_l4_per__uart6, |
2405 | &omap54xx_l4_cfg__usb_host_hs, | ||
2406 | &omap54xx_l4_cfg__usb_tll_hs, | ||
2183 | &omap54xx_l4_cfg__usb_otg_ss, | 2407 | &omap54xx_l4_cfg__usb_otg_ss, |
2184 | &omap54xx_l4_wkup__wd_timer2, | 2408 | &omap54xx_l4_wkup__wd_timer2, |
2185 | NULL, | 2409 | NULL, |
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index baf3d8bf6bea..da5a59ae77b6 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h | |||
@@ -257,6 +257,7 @@ extern void am33xx_powerdomains_init(void); | |||
257 | extern void omap44xx_powerdomains_init(void); | 257 | extern void omap44xx_powerdomains_init(void); |
258 | extern void omap54xx_powerdomains_init(void); | 258 | extern void omap54xx_powerdomains_init(void); |
259 | extern void dra7xx_powerdomains_init(void); | 259 | extern void dra7xx_powerdomains_init(void); |
260 | void am43xx_powerdomains_init(void); | ||
260 | 261 | ||
261 | extern struct pwrdm_ops omap2_pwrdm_operations; | 262 | extern struct pwrdm_ops omap2_pwrdm_operations; |
262 | extern struct pwrdm_ops omap3_pwrdm_operations; | 263 | extern struct pwrdm_ops omap3_pwrdm_operations; |
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c new file mode 100644 index 000000000000..95fee54c38ab --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains43xx_data.c | |||
@@ -0,0 +1,136 @@ | |||
1 | /* | ||
2 | * AM43xx Power domains framework | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/init.h> | ||
13 | |||
14 | #include "powerdomain.h" | ||
15 | |||
16 | #include "prcm-common.h" | ||
17 | #include "prcm44xx.h" | ||
18 | #include "prcm43xx.h" | ||
19 | |||
20 | static struct powerdomain gfx_43xx_pwrdm = { | ||
21 | .name = "gfx_pwrdm", | ||
22 | .voltdm = { .name = "core" }, | ||
23 | .prcm_offs = AM43XX_PRM_GFX_INST, | ||
24 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
25 | .pwrsts = PWRSTS_OFF_ON, | ||
26 | .banks = 1, | ||
27 | .pwrsts_mem_on = { | ||
28 | [0] = PWRSTS_ON, /* gfx_mem */ | ||
29 | }, | ||
30 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
31 | }; | ||
32 | |||
33 | static struct powerdomain mpu_43xx_pwrdm = { | ||
34 | .name = "mpu_pwrdm", | ||
35 | .voltdm = { .name = "mpu" }, | ||
36 | .prcm_offs = AM43XX_PRM_MPU_INST, | ||
37 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
38 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
39 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
40 | .banks = 3, | ||
41 | .pwrsts_mem_ret = { | ||
42 | [0] = PWRSTS_OFF_RET, /* mpu_l1 */ | ||
43 | [1] = PWRSTS_OFF_RET, /* mpu_l2 */ | ||
44 | [2] = PWRSTS_OFF_RET, /* mpu_ram */ | ||
45 | }, | ||
46 | .pwrsts_mem_on = { | ||
47 | [0] = PWRSTS_ON, /* mpu_l1 */ | ||
48 | [1] = PWRSTS_ON, /* mpu_l2 */ | ||
49 | [2] = PWRSTS_ON, /* mpu_ram */ | ||
50 | }, | ||
51 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
52 | }; | ||
53 | |||
54 | static struct powerdomain rtc_43xx_pwrdm = { | ||
55 | .name = "rtc_pwrdm", | ||
56 | .voltdm = { .name = "rtc" }, | ||
57 | .prcm_offs = AM43XX_PRM_RTC_INST, | ||
58 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
59 | .pwrsts = PWRSTS_ON, | ||
60 | }; | ||
61 | |||
62 | static struct powerdomain wkup_43xx_pwrdm = { | ||
63 | .name = "wkup_pwrdm", | ||
64 | .voltdm = { .name = "core" }, | ||
65 | .prcm_offs = AM43XX_PRM_WKUP_INST, | ||
66 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
67 | .pwrsts = PWRSTS_ON, | ||
68 | .banks = 1, | ||
69 | .pwrsts_mem_on = { | ||
70 | [0] = PWRSTS_ON, /* debugss_mem */ | ||
71 | }, | ||
72 | }; | ||
73 | |||
74 | static struct powerdomain tamper_43xx_pwrdm = { | ||
75 | .name = "tamper_pwrdm", | ||
76 | .voltdm = { .name = "tamper" }, | ||
77 | .prcm_offs = AM43XX_PRM_TAMPER_INST, | ||
78 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
79 | .pwrsts = PWRSTS_ON, | ||
80 | }; | ||
81 | |||
82 | static struct powerdomain cefuse_43xx_pwrdm = { | ||
83 | .name = "cefuse_pwrdm", | ||
84 | .voltdm = { .name = "core" }, | ||
85 | .prcm_offs = AM43XX_PRM_CEFUSE_INST, | ||
86 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
87 | .pwrsts = PWRSTS_OFF_ON, | ||
88 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
89 | }; | ||
90 | |||
91 | static struct powerdomain per_43xx_pwrdm = { | ||
92 | .name = "per_pwrdm", | ||
93 | .voltdm = { .name = "core" }, | ||
94 | .prcm_offs = AM43XX_PRM_PER_INST, | ||
95 | .prcm_partition = AM43XX_PRM_PARTITION, | ||
96 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
97 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
98 | .banks = 4, | ||
99 | .pwrsts_mem_ret = { | ||
100 | [0] = PWRSTS_OFF_RET, /* icss_mem */ | ||
101 | [1] = PWRSTS_OFF_RET, /* per_mem */ | ||
102 | [2] = PWRSTS_OFF_RET, /* ram1_mem */ | ||
103 | [3] = PWRSTS_OFF_RET, /* ram2_mem */ | ||
104 | }, | ||
105 | .pwrsts_mem_on = { | ||
106 | [0] = PWRSTS_ON, /* icss_mem */ | ||
107 | [1] = PWRSTS_ON, /* per_mem */ | ||
108 | [2] = PWRSTS_ON, /* ram1_mem */ | ||
109 | [3] = PWRSTS_ON, /* ram2_mem */ | ||
110 | }, | ||
111 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
112 | }; | ||
113 | |||
114 | static struct powerdomain *powerdomains_am43xx[] __initdata = { | ||
115 | &gfx_43xx_pwrdm, | ||
116 | &mpu_43xx_pwrdm, | ||
117 | &rtc_43xx_pwrdm, | ||
118 | &wkup_43xx_pwrdm, | ||
119 | &tamper_43xx_pwrdm, | ||
120 | &cefuse_43xx_pwrdm, | ||
121 | &per_43xx_pwrdm, | ||
122 | NULL | ||
123 | }; | ||
124 | |||
125 | static int am43xx_check_vcvp(void) | ||
126 | { | ||
127 | return 0; | ||
128 | } | ||
129 | |||
130 | void __init am43xx_powerdomains_init(void) | ||
131 | { | ||
132 | omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp; | ||
133 | pwrdm_register_platform_funcs(&omap4_pwrdm_operations); | ||
134 | pwrdm_register_pwrdms(powerdomains_am43xx); | ||
135 | pwrdm_complete_init(); | ||
136 | } | ||
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h new file mode 100644 index 000000000000..7785be984edd --- /dev/null +++ b/arch/arm/mach-omap2/prcm43xx.h | |||
@@ -0,0 +1,146 @@ | |||
1 | /* | ||
2 | * AM43x PRCM defines | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H | ||
12 | #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H | ||
13 | |||
14 | #define AM43XX_PRM_PARTITION 1 | ||
15 | #define AM43XX_CM_PARTITION 1 | ||
16 | |||
17 | /* PRM instances */ | ||
18 | #define AM43XX_PRM_OCP_SOCKET_INST 0x0000 | ||
19 | #define AM43XX_PRM_MPU_INST 0x0300 | ||
20 | #define AM43XX_PRM_GFX_INST 0x0400 | ||
21 | #define AM43XX_PRM_RTC_INST 0x0500 | ||
22 | #define AM43XX_PRM_TAMPER_INST 0x0600 | ||
23 | #define AM43XX_PRM_CEFUSE_INST 0x0700 | ||
24 | #define AM43XX_PRM_PER_INST 0x0800 | ||
25 | #define AM43XX_PRM_WKUP_INST 0x2000 | ||
26 | #define AM43XX_PRM_DEVICE_INST 0x4000 | ||
27 | |||
28 | /* RM RSTCTRL offsets */ | ||
29 | #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 | ||
30 | #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 | ||
31 | #define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 | ||
32 | |||
33 | /* RM RSTST offsets */ | ||
34 | #define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 | ||
35 | #define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 | ||
36 | |||
37 | /* CM instances */ | ||
38 | #define AM43XX_CM_WKUP_INST 0x2800 | ||
39 | #define AM43XX_CM_DEVICE_INST 0x4100 | ||
40 | #define AM43XX_CM_DPLL_INST 0x4200 | ||
41 | #define AM43XX_CM_MPU_INST 0x8300 | ||
42 | #define AM43XX_CM_GFX_INST 0x8400 | ||
43 | #define AM43XX_CM_RTC_INST 0x8500 | ||
44 | #define AM43XX_CM_TAMPER_INST 0x8600 | ||
45 | #define AM43XX_CM_CEFUSE_INST 0x8700 | ||
46 | #define AM43XX_CM_PER_INST 0x8800 | ||
47 | |||
48 | /* CD offsets */ | ||
49 | #define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000 | ||
50 | #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100 | ||
51 | #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200 | ||
52 | #define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300 | ||
53 | #define AM43XX_CM_MPU_MPU_CDOFFS 0x0000 | ||
54 | #define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000 | ||
55 | #define AM43XX_CM_RTC_RTC_CDOFFS 0x0000 | ||
56 | #define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000 | ||
57 | #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000 | ||
58 | #define AM43XX_CM_PER_L3_CDOFFS 0x0000 | ||
59 | #define AM43XX_CM_PER_L3S_CDOFFS 0x0200 | ||
60 | #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 | ||
61 | #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 | ||
62 | #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 | ||
63 | #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 | ||
64 | #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 | ||
65 | #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 | ||
66 | |||
67 | /* CLK CTRL offsets */ | ||
68 | #define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 | ||
69 | #define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 | ||
70 | #define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 | ||
71 | #define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 | ||
72 | #define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 | ||
73 | #define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 | ||
74 | #define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 | ||
75 | #define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 | ||
76 | #define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 | ||
77 | #define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 | ||
78 | #define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 | ||
79 | #define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 | ||
80 | #define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 | ||
81 | #define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 | ||
82 | #define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 | ||
83 | #define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 | ||
84 | #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 | ||
85 | #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 | ||
86 | #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 | ||
87 | #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 | ||
88 | #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 | ||
89 | #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 | ||
90 | #define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 | ||
91 | #define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 | ||
92 | #define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 | ||
93 | #define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 | ||
94 | #define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 | ||
95 | #define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 | ||
96 | #define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 | ||
97 | #define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 | ||
98 | #define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 | ||
99 | #define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 | ||
100 | #define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 | ||
101 | #define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 | ||
102 | #define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 | ||
103 | #define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 | ||
104 | #define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 | ||
105 | #define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 | ||
106 | #define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 | ||
107 | #define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 | ||
108 | #define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 | ||
109 | #define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 | ||
110 | #define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 | ||
111 | #define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 | ||
112 | #define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 | ||
113 | #define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 | ||
114 | #define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 | ||
115 | #define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 | ||
116 | #define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 | ||
117 | #define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 | ||
118 | #define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 | ||
119 | #define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 | ||
120 | #define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 | ||
121 | #define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 | ||
122 | #define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 | ||
123 | #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 | ||
124 | #define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 | ||
125 | #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 | ||
126 | #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 | ||
127 | #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 | ||
128 | #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 | ||
129 | #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 | ||
130 | #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 | ||
131 | #define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 | ||
132 | #define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 | ||
133 | #define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 | ||
134 | #define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 | ||
135 | #define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 | ||
136 | #define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 | ||
137 | #define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 | ||
138 | #define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 | ||
139 | #define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 | ||
140 | #define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 | ||
141 | #define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 | ||
142 | #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 | ||
143 | #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 | ||
144 | #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 | ||
145 | |||
146 | #endif | ||
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 4588df1447ed..076bd90a6ce0 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h | |||
@@ -455,9 +455,7 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
455 | #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) | 455 | #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) |
456 | 456 | ||
457 | #define OMAP54XX_CLASS 0x54000054 | 457 | #define OMAP54XX_CLASS 0x54000054 |
458 | #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) | ||
459 | #define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) | 458 | #define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) |
460 | #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) | ||
461 | #define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) | 459 | #define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) |
462 | 460 | ||
463 | void omap2xxx_check_revision(void); | 461 | void omap2xxx_check_revision(void); |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 538e7cda5eea..3ca81e0ada5e 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -55,6 +55,7 @@ | |||
55 | #include "soc.h" | 55 | #include "soc.h" |
56 | #include "common.h" | 56 | #include "common.h" |
57 | #include "powerdomain.h" | 57 | #include "powerdomain.h" |
58 | #include "omap-secure.h" | ||
58 | 59 | ||
59 | #define REALTIME_COUNTER_BASE 0x48243200 | 60 | #define REALTIME_COUNTER_BASE 0x48243200 |
60 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | 61 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 |
@@ -66,6 +67,15 @@ | |||
66 | static struct omap_dm_timer clkev; | 67 | static struct omap_dm_timer clkev; |
67 | static struct clock_event_device clockevent_gpt; | 68 | static struct clock_event_device clockevent_gpt; |
68 | 69 | ||
70 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER | ||
71 | static unsigned long arch_timer_freq; | ||
72 | |||
73 | void set_cntfreq(void) | ||
74 | { | ||
75 | omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); | ||
76 | } | ||
77 | #endif | ||
78 | |||
69 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) | 79 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
70 | { | 80 | { |
71 | struct clock_event_device *evt = &clockevent_gpt; | 81 | struct clock_event_device *evt = &clockevent_gpt; |
@@ -515,6 +525,10 @@ static void __init realtime_counter_init(void) | |||
515 | num = 8; | 525 | num = 8; |
516 | den = 25; | 526 | den = 25; |
517 | break; | 527 | break; |
528 | case 20000000: | ||
529 | num = 192; | ||
530 | den = 625; | ||
531 | break; | ||
518 | case 2600000: | 532 | case 2600000: |
519 | num = 384; | 533 | num = 384; |
520 | den = 1625; | 534 | den = 1625; |
@@ -542,6 +556,9 @@ static void __init realtime_counter_init(void) | |||
542 | reg |= den; | 556 | reg |= den; |
543 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | 557 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); |
544 | 558 | ||
559 | arch_timer_freq = (rate / den) * num; | ||
560 | set_cntfreq(); | ||
561 | |||
545 | iounmap(base); | 562 | iounmap(base); |
546 | } | 563 | } |
547 | #else | 564 | #else |
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 31d0c9101272..645a8fe55f8d 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
@@ -12,7 +12,7 @@ obj- := | |||
12 | 12 | ||
13 | # Core | 13 | # Core |
14 | 14 | ||
15 | obj-y += common.o clock.o | 15 | obj-y += common.o |
16 | 16 | ||
17 | # Core support | 17 | # Core support |
18 | 18 | ||
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c deleted file mode 100644 index c1bcc4a6d3a8..000000000000 --- a/arch/arm/mach-s3c64xx/clock.c +++ /dev/null | |||
@@ -1,1007 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/clock.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX Base clock support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/ioport.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/err.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <mach/map.h> | ||
25 | |||
26 | #include <mach/regs-clock.h> | ||
27 | |||
28 | #include <plat/cpu.h> | ||
29 | #include <plat/devs.h> | ||
30 | #include <plat/cpu-freq.h> | ||
31 | #include <plat/clock.h> | ||
32 | #include <plat/clock-clksrc.h> | ||
33 | #include <plat/pll.h> | ||
34 | |||
35 | #include "regs-sys.h" | ||
36 | |||
37 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | ||
38 | * ext_xtal_mux for want of an actual name from the manual. | ||
39 | */ | ||
40 | |||
41 | static struct clk clk_ext_xtal_mux = { | ||
42 | .name = "ext_xtal", | ||
43 | }; | ||
44 | |||
45 | #define clk_fin_apll clk_ext_xtal_mux | ||
46 | #define clk_fin_mpll clk_ext_xtal_mux | ||
47 | #define clk_fin_epll clk_ext_xtal_mux | ||
48 | |||
49 | #define clk_fout_mpll clk_mpll | ||
50 | #define clk_fout_epll clk_epll | ||
51 | |||
52 | struct clk clk_h2 = { | ||
53 | .name = "hclk2", | ||
54 | .rate = 0, | ||
55 | }; | ||
56 | |||
57 | struct clk clk_27m = { | ||
58 | .name = "clk_27m", | ||
59 | .rate = 27000000, | ||
60 | }; | ||
61 | |||
62 | static int clk_48m_ctrl(struct clk *clk, int enable) | ||
63 | { | ||
64 | unsigned long flags; | ||
65 | u32 val; | ||
66 | |||
67 | /* can't rely on clock lock, this register has other usages */ | ||
68 | local_irq_save(flags); | ||
69 | |||
70 | val = __raw_readl(S3C64XX_OTHERS); | ||
71 | if (enable) | ||
72 | val |= S3C64XX_OTHERS_USBMASK; | ||
73 | else | ||
74 | val &= ~S3C64XX_OTHERS_USBMASK; | ||
75 | |||
76 | __raw_writel(val, S3C64XX_OTHERS); | ||
77 | local_irq_restore(flags); | ||
78 | |||
79 | return 0; | ||
80 | } | ||
81 | |||
82 | struct clk clk_48m = { | ||
83 | .name = "clk_48m", | ||
84 | .rate = 48000000, | ||
85 | .enable = clk_48m_ctrl, | ||
86 | }; | ||
87 | |||
88 | struct clk clk_xusbxti = { | ||
89 | .name = "xusbxti", | ||
90 | .rate = 48000000, | ||
91 | }; | ||
92 | |||
93 | static int inline s3c64xx_gate(void __iomem *reg, | ||
94 | struct clk *clk, | ||
95 | int enable) | ||
96 | { | ||
97 | unsigned int ctrlbit = clk->ctrlbit; | ||
98 | u32 con; | ||
99 | |||
100 | con = __raw_readl(reg); | ||
101 | |||
102 | if (enable) | ||
103 | con |= ctrlbit; | ||
104 | else | ||
105 | con &= ~ctrlbit; | ||
106 | |||
107 | __raw_writel(con, reg); | ||
108 | return 0; | ||
109 | } | ||
110 | |||
111 | static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) | ||
112 | { | ||
113 | return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); | ||
114 | } | ||
115 | |||
116 | static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) | ||
117 | { | ||
118 | return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); | ||
119 | } | ||
120 | |||
121 | int s3c64xx_sclk_ctrl(struct clk *clk, int enable) | ||
122 | { | ||
123 | return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); | ||
124 | } | ||
125 | |||
126 | static struct clk init_clocks_off[] = { | ||
127 | { | ||
128 | .name = "nand", | ||
129 | .parent = &clk_h, | ||
130 | }, { | ||
131 | .name = "rtc", | ||
132 | .parent = &clk_p, | ||
133 | .enable = s3c64xx_pclk_ctrl, | ||
134 | .ctrlbit = S3C_CLKCON_PCLK_RTC, | ||
135 | }, { | ||
136 | .name = "adc", | ||
137 | .parent = &clk_p, | ||
138 | .enable = s3c64xx_pclk_ctrl, | ||
139 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, | ||
140 | }, { | ||
141 | .name = "i2c", | ||
142 | .devname = "s3c2440-i2c.0", | ||
143 | .parent = &clk_p, | ||
144 | .enable = s3c64xx_pclk_ctrl, | ||
145 | .ctrlbit = S3C_CLKCON_PCLK_IIC, | ||
146 | }, { | ||
147 | .name = "i2c", | ||
148 | .devname = "s3c2440-i2c.1", | ||
149 | .parent = &clk_p, | ||
150 | .enable = s3c64xx_pclk_ctrl, | ||
151 | .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, | ||
152 | }, { | ||
153 | .name = "keypad", | ||
154 | .parent = &clk_p, | ||
155 | .enable = s3c64xx_pclk_ctrl, | ||
156 | .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, | ||
157 | }, { | ||
158 | .name = "spi", | ||
159 | .devname = "s3c6410-spi.0", | ||
160 | .parent = &clk_p, | ||
161 | .enable = s3c64xx_pclk_ctrl, | ||
162 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, | ||
163 | }, { | ||
164 | .name = "spi", | ||
165 | .devname = "s3c6410-spi.1", | ||
166 | .parent = &clk_p, | ||
167 | .enable = s3c64xx_pclk_ctrl, | ||
168 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, | ||
169 | }, { | ||
170 | .name = "48m", | ||
171 | .devname = "s3c-sdhci.0", | ||
172 | .parent = &clk_48m, | ||
173 | .enable = s3c64xx_sclk_ctrl, | ||
174 | .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, | ||
175 | }, { | ||
176 | .name = "48m", | ||
177 | .devname = "s3c-sdhci.1", | ||
178 | .parent = &clk_48m, | ||
179 | .enable = s3c64xx_sclk_ctrl, | ||
180 | .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, | ||
181 | }, { | ||
182 | .name = "48m", | ||
183 | .devname = "s3c-sdhci.2", | ||
184 | .parent = &clk_48m, | ||
185 | .enable = s3c64xx_sclk_ctrl, | ||
186 | .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, | ||
187 | }, { | ||
188 | .name = "ac97", | ||
189 | .parent = &clk_p, | ||
190 | .ctrlbit = S3C_CLKCON_PCLK_AC97, | ||
191 | }, { | ||
192 | .name = "cfcon", | ||
193 | .parent = &clk_h, | ||
194 | .enable = s3c64xx_hclk_ctrl, | ||
195 | .ctrlbit = S3C_CLKCON_HCLK_IHOST, | ||
196 | }, { | ||
197 | .name = "dma0", | ||
198 | .parent = &clk_h, | ||
199 | .enable = s3c64xx_hclk_ctrl, | ||
200 | .ctrlbit = S3C_CLKCON_HCLK_DMA0, | ||
201 | }, { | ||
202 | .name = "dma1", | ||
203 | .parent = &clk_h, | ||
204 | .enable = s3c64xx_hclk_ctrl, | ||
205 | .ctrlbit = S3C_CLKCON_HCLK_DMA1, | ||
206 | }, { | ||
207 | .name = "3dse", | ||
208 | .parent = &clk_h, | ||
209 | .enable = s3c64xx_hclk_ctrl, | ||
210 | .ctrlbit = S3C_CLKCON_HCLK_3DSE, | ||
211 | }, { | ||
212 | .name = "hclk_secur", | ||
213 | .parent = &clk_h, | ||
214 | .enable = s3c64xx_hclk_ctrl, | ||
215 | .ctrlbit = S3C_CLKCON_HCLK_SECUR, | ||
216 | }, { | ||
217 | .name = "sdma1", | ||
218 | .parent = &clk_h, | ||
219 | .enable = s3c64xx_hclk_ctrl, | ||
220 | .ctrlbit = S3C_CLKCON_HCLK_SDMA1, | ||
221 | }, { | ||
222 | .name = "sdma0", | ||
223 | .parent = &clk_h, | ||
224 | .enable = s3c64xx_hclk_ctrl, | ||
225 | .ctrlbit = S3C_CLKCON_HCLK_SDMA0, | ||
226 | }, { | ||
227 | .name = "hclk_jpeg", | ||
228 | .parent = &clk_h, | ||
229 | .enable = s3c64xx_hclk_ctrl, | ||
230 | .ctrlbit = S3C_CLKCON_HCLK_JPEG, | ||
231 | }, { | ||
232 | .name = "camif", | ||
233 | .parent = &clk_h, | ||
234 | .enable = s3c64xx_hclk_ctrl, | ||
235 | .ctrlbit = S3C_CLKCON_HCLK_CAMIF, | ||
236 | }, { | ||
237 | .name = "hclk_scaler", | ||
238 | .parent = &clk_h, | ||
239 | .enable = s3c64xx_hclk_ctrl, | ||
240 | .ctrlbit = S3C_CLKCON_HCLK_SCALER, | ||
241 | }, { | ||
242 | .name = "2d", | ||
243 | .parent = &clk_h, | ||
244 | .enable = s3c64xx_hclk_ctrl, | ||
245 | .ctrlbit = S3C_CLKCON_HCLK_2D, | ||
246 | }, { | ||
247 | .name = "tv", | ||
248 | .parent = &clk_h, | ||
249 | .enable = s3c64xx_hclk_ctrl, | ||
250 | .ctrlbit = S3C_CLKCON_HCLK_TV, | ||
251 | }, { | ||
252 | .name = "post0", | ||
253 | .parent = &clk_h, | ||
254 | .enable = s3c64xx_hclk_ctrl, | ||
255 | .ctrlbit = S3C_CLKCON_HCLK_POST0, | ||
256 | }, { | ||
257 | .name = "rot", | ||
258 | .parent = &clk_h, | ||
259 | .enable = s3c64xx_hclk_ctrl, | ||
260 | .ctrlbit = S3C_CLKCON_HCLK_ROT, | ||
261 | }, { | ||
262 | .name = "hclk_mfc", | ||
263 | .parent = &clk_h, | ||
264 | .enable = s3c64xx_hclk_ctrl, | ||
265 | .ctrlbit = S3C_CLKCON_HCLK_MFC, | ||
266 | }, { | ||
267 | .name = "pclk_mfc", | ||
268 | .parent = &clk_p, | ||
269 | .enable = s3c64xx_pclk_ctrl, | ||
270 | .ctrlbit = S3C_CLKCON_PCLK_MFC, | ||
271 | }, { | ||
272 | .name = "dac27", | ||
273 | .enable = s3c64xx_sclk_ctrl, | ||
274 | .ctrlbit = S3C_CLKCON_SCLK_DAC27, | ||
275 | }, { | ||
276 | .name = "tv27", | ||
277 | .enable = s3c64xx_sclk_ctrl, | ||
278 | .ctrlbit = S3C_CLKCON_SCLK_TV27, | ||
279 | }, { | ||
280 | .name = "scaler27", | ||
281 | .enable = s3c64xx_sclk_ctrl, | ||
282 | .ctrlbit = S3C_CLKCON_SCLK_SCALER27, | ||
283 | }, { | ||
284 | .name = "sclk_scaler", | ||
285 | .enable = s3c64xx_sclk_ctrl, | ||
286 | .ctrlbit = S3C_CLKCON_SCLK_SCALER, | ||
287 | }, { | ||
288 | .name = "post0_27", | ||
289 | .enable = s3c64xx_sclk_ctrl, | ||
290 | .ctrlbit = S3C_CLKCON_SCLK_POST0_27, | ||
291 | }, { | ||
292 | .name = "secur", | ||
293 | .enable = s3c64xx_sclk_ctrl, | ||
294 | .ctrlbit = S3C_CLKCON_SCLK_SECUR, | ||
295 | }, { | ||
296 | .name = "sclk_mfc", | ||
297 | .enable = s3c64xx_sclk_ctrl, | ||
298 | .ctrlbit = S3C_CLKCON_SCLK_MFC, | ||
299 | }, { | ||
300 | .name = "sclk_jpeg", | ||
301 | .enable = s3c64xx_sclk_ctrl, | ||
302 | .ctrlbit = S3C_CLKCON_SCLK_JPEG, | ||
303 | }, | ||
304 | }; | ||
305 | |||
306 | static struct clk clk_48m_spi0 = { | ||
307 | .name = "spi_48m", | ||
308 | .devname = "s3c6410-spi.0", | ||
309 | .parent = &clk_48m, | ||
310 | .enable = s3c64xx_sclk_ctrl, | ||
311 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, | ||
312 | }; | ||
313 | |||
314 | static struct clk clk_48m_spi1 = { | ||
315 | .name = "spi_48m", | ||
316 | .devname = "s3c6410-spi.1", | ||
317 | .parent = &clk_48m, | ||
318 | .enable = s3c64xx_sclk_ctrl, | ||
319 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, | ||
320 | }; | ||
321 | |||
322 | static struct clk clk_i2s0 = { | ||
323 | .name = "iis", | ||
324 | .devname = "samsung-i2s.0", | ||
325 | .parent = &clk_p, | ||
326 | .enable = s3c64xx_pclk_ctrl, | ||
327 | .ctrlbit = S3C_CLKCON_PCLK_IIS0, | ||
328 | }; | ||
329 | |||
330 | static struct clk clk_i2s1 = { | ||
331 | .name = "iis", | ||
332 | .devname = "samsung-i2s.1", | ||
333 | .parent = &clk_p, | ||
334 | .enable = s3c64xx_pclk_ctrl, | ||
335 | .ctrlbit = S3C_CLKCON_PCLK_IIS1, | ||
336 | }; | ||
337 | |||
338 | #ifdef CONFIG_CPU_S3C6410 | ||
339 | static struct clk clk_i2s2 = { | ||
340 | .name = "iis", | ||
341 | .devname = "samsung-i2s.2", | ||
342 | .parent = &clk_p, | ||
343 | .enable = s3c64xx_pclk_ctrl, | ||
344 | .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, | ||
345 | }; | ||
346 | #endif | ||
347 | |||
348 | static struct clk init_clocks[] = { | ||
349 | { | ||
350 | .name = "lcd", | ||
351 | .parent = &clk_h, | ||
352 | .enable = s3c64xx_hclk_ctrl, | ||
353 | .ctrlbit = S3C_CLKCON_HCLK_LCD, | ||
354 | }, { | ||
355 | .name = "gpio", | ||
356 | .parent = &clk_p, | ||
357 | .enable = s3c64xx_pclk_ctrl, | ||
358 | .ctrlbit = S3C_CLKCON_PCLK_GPIO, | ||
359 | }, { | ||
360 | .name = "usb-host", | ||
361 | .parent = &clk_h, | ||
362 | .enable = s3c64xx_hclk_ctrl, | ||
363 | .ctrlbit = S3C_CLKCON_HCLK_UHOST, | ||
364 | }, { | ||
365 | .name = "otg", | ||
366 | .parent = &clk_h, | ||
367 | .enable = s3c64xx_hclk_ctrl, | ||
368 | .ctrlbit = S3C_CLKCON_HCLK_USB, | ||
369 | }, { | ||
370 | .name = "timers", | ||
371 | .parent = &clk_p, | ||
372 | .enable = s3c64xx_pclk_ctrl, | ||
373 | .ctrlbit = S3C_CLKCON_PCLK_PWM, | ||
374 | }, { | ||
375 | .name = "uart", | ||
376 | .devname = "s3c6400-uart.0", | ||
377 | .parent = &clk_p, | ||
378 | .enable = s3c64xx_pclk_ctrl, | ||
379 | .ctrlbit = S3C_CLKCON_PCLK_UART0, | ||
380 | }, { | ||
381 | .name = "uart", | ||
382 | .devname = "s3c6400-uart.1", | ||
383 | .parent = &clk_p, | ||
384 | .enable = s3c64xx_pclk_ctrl, | ||
385 | .ctrlbit = S3C_CLKCON_PCLK_UART1, | ||
386 | }, { | ||
387 | .name = "uart", | ||
388 | .devname = "s3c6400-uart.2", | ||
389 | .parent = &clk_p, | ||
390 | .enable = s3c64xx_pclk_ctrl, | ||
391 | .ctrlbit = S3C_CLKCON_PCLK_UART2, | ||
392 | }, { | ||
393 | .name = "uart", | ||
394 | .devname = "s3c6400-uart.3", | ||
395 | .parent = &clk_p, | ||
396 | .enable = s3c64xx_pclk_ctrl, | ||
397 | .ctrlbit = S3C_CLKCON_PCLK_UART3, | ||
398 | }, { | ||
399 | .name = "watchdog", | ||
400 | .parent = &clk_p, | ||
401 | .ctrlbit = S3C_CLKCON_PCLK_WDT, | ||
402 | }, | ||
403 | }; | ||
404 | |||
405 | static struct clk clk_hsmmc0 = { | ||
406 | .name = "hsmmc", | ||
407 | .devname = "s3c-sdhci.0", | ||
408 | .parent = &clk_h, | ||
409 | .enable = s3c64xx_hclk_ctrl, | ||
410 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, | ||
411 | }; | ||
412 | |||
413 | static struct clk clk_hsmmc1 = { | ||
414 | .name = "hsmmc", | ||
415 | .devname = "s3c-sdhci.1", | ||
416 | .parent = &clk_h, | ||
417 | .enable = s3c64xx_hclk_ctrl, | ||
418 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, | ||
419 | }; | ||
420 | |||
421 | static struct clk clk_hsmmc2 = { | ||
422 | .name = "hsmmc", | ||
423 | .devname = "s3c-sdhci.2", | ||
424 | .parent = &clk_h, | ||
425 | .enable = s3c64xx_hclk_ctrl, | ||
426 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, | ||
427 | }; | ||
428 | |||
429 | static struct clk clk_fout_apll = { | ||
430 | .name = "fout_apll", | ||
431 | }; | ||
432 | |||
433 | static struct clk *clk_src_apll_list[] = { | ||
434 | [0] = &clk_fin_apll, | ||
435 | [1] = &clk_fout_apll, | ||
436 | }; | ||
437 | |||
438 | static struct clksrc_sources clk_src_apll = { | ||
439 | .sources = clk_src_apll_list, | ||
440 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | ||
441 | }; | ||
442 | |||
443 | static struct clksrc_clk clk_mout_apll = { | ||
444 | .clk = { | ||
445 | .name = "mout_apll", | ||
446 | }, | ||
447 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, | ||
448 | .sources = &clk_src_apll, | ||
449 | }; | ||
450 | |||
451 | static struct clk *clk_src_epll_list[] = { | ||
452 | [0] = &clk_fin_epll, | ||
453 | [1] = &clk_fout_epll, | ||
454 | }; | ||
455 | |||
456 | static struct clksrc_sources clk_src_epll = { | ||
457 | .sources = clk_src_epll_list, | ||
458 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | ||
459 | }; | ||
460 | |||
461 | static struct clksrc_clk clk_mout_epll = { | ||
462 | .clk = { | ||
463 | .name = "mout_epll", | ||
464 | }, | ||
465 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, | ||
466 | .sources = &clk_src_epll, | ||
467 | }; | ||
468 | |||
469 | static struct clk *clk_src_mpll_list[] = { | ||
470 | [0] = &clk_fin_mpll, | ||
471 | [1] = &clk_fout_mpll, | ||
472 | }; | ||
473 | |||
474 | static struct clksrc_sources clk_src_mpll = { | ||
475 | .sources = clk_src_mpll_list, | ||
476 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | ||
477 | }; | ||
478 | |||
479 | static struct clksrc_clk clk_mout_mpll = { | ||
480 | .clk = { | ||
481 | .name = "mout_mpll", | ||
482 | }, | ||
483 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, | ||
484 | .sources = &clk_src_mpll, | ||
485 | }; | ||
486 | |||
487 | static unsigned int armclk_mask; | ||
488 | |||
489 | static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) | ||
490 | { | ||
491 | unsigned long rate = clk_get_rate(clk->parent); | ||
492 | u32 clkdiv; | ||
493 | |||
494 | /* divisor mask starts at bit0, so no need to shift */ | ||
495 | clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; | ||
496 | |||
497 | return rate / (clkdiv + 1); | ||
498 | } | ||
499 | |||
500 | static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, | ||
501 | unsigned long rate) | ||
502 | { | ||
503 | unsigned long parent = clk_get_rate(clk->parent); | ||
504 | u32 div; | ||
505 | |||
506 | if (parent < rate) | ||
507 | return parent; | ||
508 | |||
509 | div = (parent / rate) - 1; | ||
510 | if (div > armclk_mask) | ||
511 | div = armclk_mask; | ||
512 | |||
513 | return parent / (div + 1); | ||
514 | } | ||
515 | |||
516 | static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) | ||
517 | { | ||
518 | unsigned long parent = clk_get_rate(clk->parent); | ||
519 | u32 div; | ||
520 | u32 val; | ||
521 | |||
522 | if (rate < parent / (armclk_mask + 1)) | ||
523 | return -EINVAL; | ||
524 | |||
525 | rate = clk_round_rate(clk, rate); | ||
526 | div = clk_get_rate(clk->parent) / rate; | ||
527 | |||
528 | val = __raw_readl(S3C_CLK_DIV0); | ||
529 | val &= ~armclk_mask; | ||
530 | val |= (div - 1); | ||
531 | __raw_writel(val, S3C_CLK_DIV0); | ||
532 | |||
533 | return 0; | ||
534 | |||
535 | } | ||
536 | |||
537 | static struct clk clk_arm = { | ||
538 | .name = "armclk", | ||
539 | .parent = &clk_mout_apll.clk, | ||
540 | .ops = &(struct clk_ops) { | ||
541 | .get_rate = s3c64xx_clk_arm_get_rate, | ||
542 | .set_rate = s3c64xx_clk_arm_set_rate, | ||
543 | .round_rate = s3c64xx_clk_arm_round_rate, | ||
544 | }, | ||
545 | }; | ||
546 | |||
547 | static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) | ||
548 | { | ||
549 | unsigned long rate = clk_get_rate(clk->parent); | ||
550 | |||
551 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
552 | |||
553 | if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) | ||
554 | rate /= 2; | ||
555 | |||
556 | return rate; | ||
557 | } | ||
558 | |||
559 | static struct clk_ops clk_dout_ops = { | ||
560 | .get_rate = s3c64xx_clk_doutmpll_get_rate, | ||
561 | }; | ||
562 | |||
563 | static struct clk clk_dout_mpll = { | ||
564 | .name = "dout_mpll", | ||
565 | .parent = &clk_mout_mpll.clk, | ||
566 | .ops = &clk_dout_ops, | ||
567 | }; | ||
568 | |||
569 | static struct clk *clkset_spi_mmc_list[] = { | ||
570 | &clk_mout_epll.clk, | ||
571 | &clk_dout_mpll, | ||
572 | &clk_fin_epll, | ||
573 | &clk_27m, | ||
574 | }; | ||
575 | |||
576 | static struct clksrc_sources clkset_spi_mmc = { | ||
577 | .sources = clkset_spi_mmc_list, | ||
578 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), | ||
579 | }; | ||
580 | |||
581 | static struct clk *clkset_irda_list[] = { | ||
582 | &clk_mout_epll.clk, | ||
583 | &clk_dout_mpll, | ||
584 | NULL, | ||
585 | &clk_27m, | ||
586 | }; | ||
587 | |||
588 | static struct clksrc_sources clkset_irda = { | ||
589 | .sources = clkset_irda_list, | ||
590 | .nr_sources = ARRAY_SIZE(clkset_irda_list), | ||
591 | }; | ||
592 | |||
593 | static struct clk *clkset_uart_list[] = { | ||
594 | &clk_mout_epll.clk, | ||
595 | &clk_dout_mpll, | ||
596 | NULL, | ||
597 | NULL | ||
598 | }; | ||
599 | |||
600 | static struct clksrc_sources clkset_uart = { | ||
601 | .sources = clkset_uart_list, | ||
602 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
603 | }; | ||
604 | |||
605 | static struct clk *clkset_uhost_list[] = { | ||
606 | &clk_48m, | ||
607 | &clk_mout_epll.clk, | ||
608 | &clk_dout_mpll, | ||
609 | &clk_fin_epll, | ||
610 | }; | ||
611 | |||
612 | static struct clksrc_sources clkset_uhost = { | ||
613 | .sources = clkset_uhost_list, | ||
614 | .nr_sources = ARRAY_SIZE(clkset_uhost_list), | ||
615 | }; | ||
616 | |||
617 | /* The peripheral clocks are all controlled via clocksource followed | ||
618 | * by an optional divider and gate stage. We currently roll this into | ||
619 | * one clock which hides the intermediate clock from the mux. | ||
620 | * | ||
621 | * Note, the JPEG clock can only be an even divider... | ||
622 | * | ||
623 | * The scaler and LCD clocks depend on the S3C64XX version, and also | ||
624 | * have a common parent divisor so are not included here. | ||
625 | */ | ||
626 | |||
627 | /* clocks that feed other parts of the clock source tree */ | ||
628 | |||
629 | static struct clk clk_iis_cd0 = { | ||
630 | .name = "iis_cdclk0", | ||
631 | }; | ||
632 | |||
633 | static struct clk clk_iis_cd1 = { | ||
634 | .name = "iis_cdclk1", | ||
635 | }; | ||
636 | |||
637 | static struct clk clk_iisv4_cd = { | ||
638 | .name = "iis_cdclk_v4", | ||
639 | }; | ||
640 | |||
641 | static struct clk clk_pcm_cd = { | ||
642 | .name = "pcm_cdclk", | ||
643 | }; | ||
644 | |||
645 | static struct clk *clkset_audio0_list[] = { | ||
646 | [0] = &clk_mout_epll.clk, | ||
647 | [1] = &clk_dout_mpll, | ||
648 | [2] = &clk_fin_epll, | ||
649 | [3] = &clk_iis_cd0, | ||
650 | [4] = &clk_pcm_cd, | ||
651 | }; | ||
652 | |||
653 | static struct clksrc_sources clkset_audio0 = { | ||
654 | .sources = clkset_audio0_list, | ||
655 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), | ||
656 | }; | ||
657 | |||
658 | static struct clk *clkset_audio1_list[] = { | ||
659 | [0] = &clk_mout_epll.clk, | ||
660 | [1] = &clk_dout_mpll, | ||
661 | [2] = &clk_fin_epll, | ||
662 | [3] = &clk_iis_cd1, | ||
663 | [4] = &clk_pcm_cd, | ||
664 | }; | ||
665 | |||
666 | static struct clksrc_sources clkset_audio1 = { | ||
667 | .sources = clkset_audio1_list, | ||
668 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | ||
669 | }; | ||
670 | |||
671 | #ifdef CONFIG_CPU_S3C6410 | ||
672 | static struct clk *clkset_audio2_list[] = { | ||
673 | [0] = &clk_mout_epll.clk, | ||
674 | [1] = &clk_dout_mpll, | ||
675 | [2] = &clk_fin_epll, | ||
676 | [3] = &clk_iisv4_cd, | ||
677 | [4] = &clk_pcm_cd, | ||
678 | }; | ||
679 | |||
680 | static struct clksrc_sources clkset_audio2 = { | ||
681 | .sources = clkset_audio2_list, | ||
682 | .nr_sources = ARRAY_SIZE(clkset_audio2_list), | ||
683 | }; | ||
684 | #endif | ||
685 | |||
686 | static struct clksrc_clk clksrcs[] = { | ||
687 | { | ||
688 | .clk = { | ||
689 | .name = "usb-bus-host", | ||
690 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | ||
691 | .enable = s3c64xx_sclk_ctrl, | ||
692 | }, | ||
693 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, | ||
694 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, | ||
695 | .sources = &clkset_uhost, | ||
696 | }, { | ||
697 | .clk = { | ||
698 | .name = "irda-bus", | ||
699 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, | ||
700 | .enable = s3c64xx_sclk_ctrl, | ||
701 | }, | ||
702 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, | ||
703 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, | ||
704 | .sources = &clkset_irda, | ||
705 | }, { | ||
706 | .clk = { | ||
707 | .name = "camera", | ||
708 | .ctrlbit = S3C_CLKCON_SCLK_CAM, | ||
709 | .enable = s3c64xx_sclk_ctrl, | ||
710 | .parent = &clk_h2, | ||
711 | }, | ||
712 | .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, | ||
713 | }, | ||
714 | }; | ||
715 | |||
716 | /* Where does UCLK0 come from? */ | ||
717 | static struct clksrc_clk clk_sclk_uclk = { | ||
718 | .clk = { | ||
719 | .name = "uclk1", | ||
720 | .ctrlbit = S3C_CLKCON_SCLK_UART, | ||
721 | .enable = s3c64xx_sclk_ctrl, | ||
722 | }, | ||
723 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, | ||
724 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, | ||
725 | .sources = &clkset_uart, | ||
726 | }; | ||
727 | |||
728 | static struct clksrc_clk clk_sclk_mmc0 = { | ||
729 | .clk = { | ||
730 | .name = "mmc_bus", | ||
731 | .devname = "s3c-sdhci.0", | ||
732 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, | ||
733 | .enable = s3c64xx_sclk_ctrl, | ||
734 | }, | ||
735 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, | ||
736 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, | ||
737 | .sources = &clkset_spi_mmc, | ||
738 | }; | ||
739 | |||
740 | static struct clksrc_clk clk_sclk_mmc1 = { | ||
741 | .clk = { | ||
742 | .name = "mmc_bus", | ||
743 | .devname = "s3c-sdhci.1", | ||
744 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, | ||
745 | .enable = s3c64xx_sclk_ctrl, | ||
746 | }, | ||
747 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, | ||
748 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, | ||
749 | .sources = &clkset_spi_mmc, | ||
750 | }; | ||
751 | |||
752 | static struct clksrc_clk clk_sclk_mmc2 = { | ||
753 | .clk = { | ||
754 | .name = "mmc_bus", | ||
755 | .devname = "s3c-sdhci.2", | ||
756 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, | ||
757 | .enable = s3c64xx_sclk_ctrl, | ||
758 | }, | ||
759 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, | ||
760 | .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, | ||
761 | .sources = &clkset_spi_mmc, | ||
762 | }; | ||
763 | |||
764 | static struct clksrc_clk clk_sclk_spi0 = { | ||
765 | .clk = { | ||
766 | .name = "spi-bus", | ||
767 | .devname = "s3c6410-spi.0", | ||
768 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, | ||
769 | .enable = s3c64xx_sclk_ctrl, | ||
770 | }, | ||
771 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, | ||
772 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, | ||
773 | .sources = &clkset_spi_mmc, | ||
774 | }; | ||
775 | |||
776 | static struct clksrc_clk clk_sclk_spi1 = { | ||
777 | .clk = { | ||
778 | .name = "spi-bus", | ||
779 | .devname = "s3c6410-spi.1", | ||
780 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, | ||
781 | .enable = s3c64xx_sclk_ctrl, | ||
782 | }, | ||
783 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, | ||
784 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, | ||
785 | .sources = &clkset_spi_mmc, | ||
786 | }; | ||
787 | |||
788 | static struct clksrc_clk clk_audio_bus0 = { | ||
789 | .clk = { | ||
790 | .name = "audio-bus", | ||
791 | .devname = "samsung-i2s.0", | ||
792 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, | ||
793 | .enable = s3c64xx_sclk_ctrl, | ||
794 | }, | ||
795 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, | ||
796 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, | ||
797 | .sources = &clkset_audio0, | ||
798 | }; | ||
799 | |||
800 | static struct clksrc_clk clk_audio_bus1 = { | ||
801 | .clk = { | ||
802 | .name = "audio-bus", | ||
803 | .devname = "samsung-i2s.1", | ||
804 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, | ||
805 | .enable = s3c64xx_sclk_ctrl, | ||
806 | }, | ||
807 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, | ||
808 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, | ||
809 | .sources = &clkset_audio1, | ||
810 | }; | ||
811 | |||
812 | #ifdef CONFIG_CPU_S3C6410 | ||
813 | static struct clksrc_clk clk_audio_bus2 = { | ||
814 | .clk = { | ||
815 | .name = "audio-bus", | ||
816 | .devname = "samsung-i2s.2", | ||
817 | .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, | ||
818 | .enable = s3c64xx_sclk_ctrl, | ||
819 | }, | ||
820 | .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 }, | ||
821 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 }, | ||
822 | .sources = &clkset_audio2, | ||
823 | }; | ||
824 | #endif | ||
825 | /* Clock initialisation code */ | ||
826 | |||
827 | static struct clksrc_clk *init_parents[] = { | ||
828 | &clk_mout_apll, | ||
829 | &clk_mout_epll, | ||
830 | &clk_mout_mpll, | ||
831 | }; | ||
832 | |||
833 | static struct clksrc_clk *clksrc_cdev[] = { | ||
834 | &clk_sclk_uclk, | ||
835 | &clk_sclk_mmc0, | ||
836 | &clk_sclk_mmc1, | ||
837 | &clk_sclk_mmc2, | ||
838 | &clk_sclk_spi0, | ||
839 | &clk_sclk_spi1, | ||
840 | &clk_audio_bus0, | ||
841 | &clk_audio_bus1, | ||
842 | }; | ||
843 | |||
844 | static struct clk *clk_cdev[] = { | ||
845 | &clk_hsmmc0, | ||
846 | &clk_hsmmc1, | ||
847 | &clk_hsmmc2, | ||
848 | &clk_48m_spi0, | ||
849 | &clk_48m_spi1, | ||
850 | &clk_i2s0, | ||
851 | &clk_i2s1, | ||
852 | }; | ||
853 | |||
854 | static struct clk_lookup s3c64xx_clk_lookup[] = { | ||
855 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), | ||
856 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), | ||
857 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), | ||
858 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), | ||
859 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), | ||
860 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | ||
861 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | ||
862 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | ||
863 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | ||
864 | CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | ||
865 | CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0), | ||
866 | CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | ||
867 | CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1), | ||
868 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), | ||
869 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk), | ||
870 | CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1), | ||
871 | CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk), | ||
872 | #ifdef CONFIG_CPU_S3C6410 | ||
873 | CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2), | ||
874 | CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk), | ||
875 | #endif | ||
876 | }; | ||
877 | |||
878 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | ||
879 | |||
880 | void __init_or_cpufreq s3c64xx_setup_clocks(void) | ||
881 | { | ||
882 | struct clk *xtal_clk; | ||
883 | unsigned long xtal; | ||
884 | unsigned long fclk; | ||
885 | unsigned long hclk; | ||
886 | unsigned long hclk2; | ||
887 | unsigned long pclk; | ||
888 | unsigned long epll; | ||
889 | unsigned long apll; | ||
890 | unsigned long mpll; | ||
891 | unsigned int ptr; | ||
892 | u32 clkdiv0; | ||
893 | |||
894 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
895 | |||
896 | clkdiv0 = __raw_readl(S3C_CLK_DIV0); | ||
897 | printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); | ||
898 | |||
899 | xtal_clk = clk_get(NULL, "xtal"); | ||
900 | BUG_ON(IS_ERR(xtal_clk)); | ||
901 | |||
902 | xtal = clk_get_rate(xtal_clk); | ||
903 | clk_put(xtal_clk); | ||
904 | |||
905 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
906 | |||
907 | /* For now assume the mux always selects the crystal */ | ||
908 | clk_ext_xtal_mux.parent = xtal_clk; | ||
909 | |||
910 | epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0), | ||
911 | __raw_readl(S3C_EPLL_CON1)); | ||
912 | mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); | ||
913 | apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); | ||
914 | |||
915 | fclk = mpll; | ||
916 | |||
917 | printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", | ||
918 | apll, mpll, epll); | ||
919 | |||
920 | if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL) | ||
921 | /* Synchronous mode */ | ||
922 | hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); | ||
923 | else | ||
924 | /* Asynchronous mode */ | ||
925 | hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); | ||
926 | |||
927 | hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); | ||
928 | pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); | ||
929 | |||
930 | printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", | ||
931 | hclk2, hclk, pclk); | ||
932 | |||
933 | clk_fout_mpll.rate = mpll; | ||
934 | clk_fout_epll.rate = epll; | ||
935 | clk_fout_apll.rate = apll; | ||
936 | |||
937 | clk_h2.rate = hclk2; | ||
938 | clk_h.rate = hclk; | ||
939 | clk_p.rate = pclk; | ||
940 | clk_f.rate = fclk; | ||
941 | |||
942 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
943 | s3c_set_clksrc(init_parents[ptr], true); | ||
944 | |||
945 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
946 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
947 | } | ||
948 | |||
949 | static struct clk *clks1[] __initdata = { | ||
950 | &clk_ext_xtal_mux, | ||
951 | &clk_iis_cd0, | ||
952 | &clk_iis_cd1, | ||
953 | &clk_iisv4_cd, | ||
954 | &clk_pcm_cd, | ||
955 | &clk_mout_epll.clk, | ||
956 | &clk_mout_mpll.clk, | ||
957 | &clk_dout_mpll, | ||
958 | &clk_arm, | ||
959 | }; | ||
960 | |||
961 | static struct clk *clks[] __initdata = { | ||
962 | &clk_ext, | ||
963 | &clk_epll, | ||
964 | &clk_27m, | ||
965 | &clk_48m, | ||
966 | &clk_h2, | ||
967 | &clk_xusbxti, | ||
968 | }; | ||
969 | |||
970 | /** | ||
971 | * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410 | ||
972 | * @xtal: The rate for the clock crystal feeding the PLLs. | ||
973 | * @armclk_divlimit: Divisor mask for ARMCLK. | ||
974 | * | ||
975 | * Register the clocks for the S3C6400 and S3C6410 SoC range, such | ||
976 | * as ARMCLK as well as the necessary parent clocks. | ||
977 | * | ||
978 | * This call does not setup the clocks, which is left to the | ||
979 | * s3c64xx_setup_clocks() call which may be needed by the cpufreq | ||
980 | * or resume code to re-set the clocks if the bootloader has changed | ||
981 | * them. | ||
982 | */ | ||
983 | void __init s3c64xx_register_clocks(unsigned long xtal, | ||
984 | unsigned armclk_divlimit) | ||
985 | { | ||
986 | unsigned int cnt; | ||
987 | |||
988 | armclk_mask = armclk_divlimit; | ||
989 | |||
990 | s3c24xx_register_baseclocks(xtal); | ||
991 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
992 | |||
993 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
994 | |||
995 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
996 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
997 | |||
998 | s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); | ||
999 | for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) | ||
1000 | s3c_disable_clocks(clk_cdev[cnt], 1); | ||
1001 | |||
1002 | s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); | ||
1003 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
1004 | for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) | ||
1005 | s3c_register_clksrc(clksrc_cdev[cnt], 1); | ||
1006 | clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup)); | ||
1007 | } | ||
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 73d79cf5e141..7d3cb58f1856 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | #include <linux/clk-provider.h> | ||
20 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
21 | #include <linux/ioport.h> | 22 | #include <linux/ioport.h> |
22 | #include <linux/serial_core.h> | 23 | #include <linux/serial_core.h> |
@@ -38,7 +39,6 @@ | |||
38 | #include <mach/regs-gpio.h> | 39 | #include <mach/regs-gpio.h> |
39 | 40 | ||
40 | #include <plat/cpu.h> | 41 | #include <plat/cpu.h> |
41 | #include <plat/clock.h> | ||
42 | #include <plat/devs.h> | 42 | #include <plat/devs.h> |
43 | #include <plat/pm.h> | 43 | #include <plat/pm.h> |
44 | #include <plat/gpio-cfg.h> | 44 | #include <plat/gpio-cfg.h> |
@@ -50,6 +50,19 @@ | |||
50 | 50 | ||
51 | #include "common.h" | 51 | #include "common.h" |
52 | 52 | ||
53 | /* External clock frequency */ | ||
54 | static unsigned long xtal_f = 12000000, xusbxti_f = 48000000; | ||
55 | |||
56 | void __init s3c64xx_set_xtal_freq(unsigned long freq) | ||
57 | { | ||
58 | xtal_f = freq; | ||
59 | } | ||
60 | |||
61 | void __init s3c64xx_set_xusbxti_freq(unsigned long freq) | ||
62 | { | ||
63 | xusbxti_f = freq; | ||
64 | } | ||
65 | |||
53 | /* uart registration process */ | 66 | /* uart registration process */ |
54 | 67 | ||
55 | static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | 68 | static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
@@ -67,7 +80,6 @@ static struct cpu_table cpu_ids[] __initdata = { | |||
67 | .idcode = S3C6400_CPU_ID, | 80 | .idcode = S3C6400_CPU_ID, |
68 | .idmask = S3C64XX_CPU_MASK, | 81 | .idmask = S3C64XX_CPU_MASK, |
69 | .map_io = s3c6400_map_io, | 82 | .map_io = s3c6400_map_io, |
70 | .init_clocks = s3c6400_init_clocks, | ||
71 | .init_uarts = s3c64xx_init_uarts, | 83 | .init_uarts = s3c64xx_init_uarts, |
72 | .init = s3c6400_init, | 84 | .init = s3c6400_init, |
73 | .name = name_s3c6400, | 85 | .name = name_s3c6400, |
@@ -75,7 +87,6 @@ static struct cpu_table cpu_ids[] __initdata = { | |||
75 | .idcode = S3C6410_CPU_ID, | 87 | .idcode = S3C6410_CPU_ID, |
76 | .idmask = S3C64XX_CPU_MASK, | 88 | .idmask = S3C64XX_CPU_MASK, |
77 | .map_io = s3c6410_map_io, | 89 | .map_io = s3c6410_map_io, |
78 | .init_clocks = s3c6410_init_clocks, | ||
79 | .init_uarts = s3c64xx_init_uarts, | 90 | .init_uarts = s3c64xx_init_uarts, |
80 | .init = s3c6410_init, | 91 | .init = s3c6410_init, |
81 | .name = name_s3c6410, | 92 | .name = name_s3c6410, |
@@ -213,8 +224,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) | |||
213 | { | 224 | { |
214 | /* | 225 | /* |
215 | * FIXME: there is no better place to put this at the moment | 226 | * FIXME: there is no better place to put this at the moment |
216 | * (samsung_wdt_reset_init needs clocks) | 227 | * (s3c64xx_clk_init needs ioremap and must happen before init_time |
228 | * samsung_wdt_reset_init needs clocks) | ||
217 | */ | 229 | */ |
230 | s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS); | ||
218 | samsung_wdt_reset_init(S3C_VA_WATCHDOG); | 231 | samsung_wdt_reset_init(S3C_VA_WATCHDOG); |
219 | 232 | ||
220 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | 233 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h index e8f990b37665..bd3bd562011e 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c64xx/common.h | |||
@@ -22,21 +22,21 @@ | |||
22 | void s3c64xx_init_irq(u32 vic0, u32 vic1); | 22 | void s3c64xx_init_irq(u32 vic0, u32 vic1); |
23 | void s3c64xx_init_io(struct map_desc *mach_desc, int size); | 23 | void s3c64xx_init_io(struct map_desc *mach_desc, int size); |
24 | 24 | ||
25 | void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit); | ||
26 | void s3c64xx_setup_clocks(void); | ||
27 | |||
28 | void s3c64xx_restart(enum reboot_mode mode, const char *cmd); | 25 | void s3c64xx_restart(enum reboot_mode mode, const char *cmd); |
29 | void s3c64xx_init_late(void); | 26 | void s3c64xx_init_late(void); |
30 | 27 | ||
28 | void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, | ||
29 | unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base); | ||
30 | void s3c64xx_set_xtal_freq(unsigned long freq); | ||
31 | void s3c64xx_set_xusbxti_freq(unsigned long freq); | ||
32 | |||
31 | #ifdef CONFIG_CPU_S3C6400 | 33 | #ifdef CONFIG_CPU_S3C6400 |
32 | 34 | ||
33 | extern int s3c6400_init(void); | 35 | extern int s3c6400_init(void); |
34 | extern void s3c6400_init_irq(void); | 36 | extern void s3c6400_init_irq(void); |
35 | extern void s3c6400_map_io(void); | 37 | extern void s3c6400_map_io(void); |
36 | extern void s3c6400_init_clocks(int xtal); | ||
37 | 38 | ||
38 | #else | 39 | #else |
39 | #define s3c6400_init_clocks NULL | ||
40 | #define s3c6400_map_io NULL | 40 | #define s3c6400_map_io NULL |
41 | #define s3c6400_init NULL | 41 | #define s3c6400_init NULL |
42 | #endif | 42 | #endif |
@@ -46,10 +46,8 @@ extern void s3c6400_init_clocks(int xtal); | |||
46 | extern int s3c6410_init(void); | 46 | extern int s3c6410_init(void); |
47 | extern void s3c6410_init_irq(void); | 47 | extern void s3c6410_init_irq(void); |
48 | extern void s3c6410_map_io(void); | 48 | extern void s3c6410_map_io(void); |
49 | extern void s3c6410_init_clocks(int xtal); | ||
50 | 49 | ||
51 | #else | 50 | #else |
52 | #define s3c6410_init_clocks NULL | ||
53 | #define s3c6410_map_io NULL | 51 | #define s3c6410_map_io NULL |
54 | #define s3c6410_init NULL | 52 | #define s3c6410_init NULL |
55 | #endif | 53 | #endif |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 759846c28d12..c511dfaae148 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c | |||
@@ -677,7 +677,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, | |||
677 | goto err_map; | 677 | goto err_map; |
678 | } | 678 | } |
679 | 679 | ||
680 | clk_enable(dmac->clk); | 680 | clk_prepare_enable(dmac->clk); |
681 | 681 | ||
682 | dmac->regs = regs; | 682 | dmac->regs = regs; |
683 | dmac->chanbase = chbase; | 683 | dmac->chanbase = chbase; |
@@ -711,7 +711,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, | |||
711 | return 0; | 711 | return 0; |
712 | 712 | ||
713 | err_clk: | 713 | err_clk: |
714 | clk_disable(dmac->clk); | 714 | clk_disable_unprepare(dmac->clk); |
715 | clk_put(dmac->clk); | 715 | clk_put(dmac->clk); |
716 | err_map: | 716 | err_map: |
717 | iounmap(regs); | 717 | iounmap(regs); |
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 05332b998ec0..4f44aac77092 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h | |||
@@ -15,145 +15,21 @@ | |||
15 | #ifndef __PLAT_REGS_CLOCK_H | 15 | #ifndef __PLAT_REGS_CLOCK_H |
16 | #define __PLAT_REGS_CLOCK_H __FILE__ | 16 | #define __PLAT_REGS_CLOCK_H __FILE__ |
17 | 17 | ||
18 | /* | ||
19 | * FIXME: Remove remaining definitions | ||
20 | */ | ||
21 | |||
18 | #define S3C_CLKREG(x) (S3C_VA_SYS + (x)) | 22 | #define S3C_CLKREG(x) (S3C_VA_SYS + (x)) |
19 | 23 | ||
20 | #define S3C_APLL_LOCK S3C_CLKREG(0x00) | ||
21 | #define S3C_MPLL_LOCK S3C_CLKREG(0x04) | ||
22 | #define S3C_EPLL_LOCK S3C_CLKREG(0x08) | ||
23 | #define S3C_APLL_CON S3C_CLKREG(0x0C) | ||
24 | #define S3C_MPLL_CON S3C_CLKREG(0x10) | ||
25 | #define S3C_EPLL_CON0 S3C_CLKREG(0x14) | ||
26 | #define S3C_EPLL_CON1 S3C_CLKREG(0x18) | ||
27 | #define S3C_CLK_SRC S3C_CLKREG(0x1C) | ||
28 | #define S3C_CLK_DIV0 S3C_CLKREG(0x20) | ||
29 | #define S3C_CLK_DIV1 S3C_CLKREG(0x24) | ||
30 | #define S3C_CLK_DIV2 S3C_CLKREG(0x28) | ||
31 | #define S3C_CLK_OUT S3C_CLKREG(0x2C) | ||
32 | #define S3C_HCLK_GATE S3C_CLKREG(0x30) | ||
33 | #define S3C_PCLK_GATE S3C_CLKREG(0x34) | 24 | #define S3C_PCLK_GATE S3C_CLKREG(0x34) |
34 | #define S3C_SCLK_GATE S3C_CLKREG(0x38) | ||
35 | #define S3C_MEM0_GATE S3C_CLKREG(0x3C) | ||
36 | #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) | 25 | #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) |
37 | #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) | 26 | #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) |
38 | 27 | ||
39 | /* CLKDIV0 */ | ||
40 | #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) | ||
41 | #define S3C6400_CLKDIV0_PCLK_SHIFT (12) | ||
42 | #define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) | ||
43 | #define S3C6400_CLKDIV0_HCLK2_SHIFT (9) | ||
44 | #define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) | ||
45 | #define S3C6400_CLKDIV0_HCLK_SHIFT (8) | ||
46 | #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) | ||
47 | #define S3C6400_CLKDIV0_MPLL_SHIFT (4) | ||
48 | |||
49 | #define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) | ||
50 | #define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) | ||
51 | #define S3C6400_CLKDIV0_ARM_SHIFT (0) | ||
52 | |||
53 | /* HCLK GATE Registers */ | ||
54 | #define S3C_CLKCON_HCLK_3DSE (1<<31) | ||
55 | #define S3C_CLKCON_HCLK_UHOST (1<<29) | ||
56 | #define S3C_CLKCON_HCLK_SECUR (1<<28) | ||
57 | #define S3C_CLKCON_HCLK_SDMA1 (1<<27) | ||
58 | #define S3C_CLKCON_HCLK_SDMA0 (1<<26) | ||
59 | #define S3C_CLKCON_HCLK_IROM (1<<25) | ||
60 | #define S3C_CLKCON_HCLK_DDR1 (1<<24) | ||
61 | #define S3C_CLKCON_HCLK_DDR0 (1<<23) | ||
62 | #define S3C_CLKCON_HCLK_MEM1 (1<<22) | ||
63 | #define S3C_CLKCON_HCLK_MEM0 (1<<21) | ||
64 | #define S3C_CLKCON_HCLK_USB (1<<20) | ||
65 | #define S3C_CLKCON_HCLK_HSMMC2 (1<<19) | ||
66 | #define S3C_CLKCON_HCLK_HSMMC1 (1<<18) | ||
67 | #define S3C_CLKCON_HCLK_HSMMC0 (1<<17) | ||
68 | #define S3C_CLKCON_HCLK_MDP (1<<16) | ||
69 | #define S3C_CLKCON_HCLK_DHOST (1<<15) | ||
70 | #define S3C_CLKCON_HCLK_IHOST (1<<14) | ||
71 | #define S3C_CLKCON_HCLK_DMA1 (1<<13) | ||
72 | #define S3C_CLKCON_HCLK_DMA0 (1<<12) | ||
73 | #define S3C_CLKCON_HCLK_JPEG (1<<11) | ||
74 | #define S3C_CLKCON_HCLK_CAMIF (1<<10) | ||
75 | #define S3C_CLKCON_HCLK_SCALER (1<<9) | ||
76 | #define S3C_CLKCON_HCLK_2D (1<<8) | ||
77 | #define S3C_CLKCON_HCLK_TV (1<<7) | ||
78 | #define S3C_CLKCON_HCLK_POST0 (1<<5) | ||
79 | #define S3C_CLKCON_HCLK_ROT (1<<4) | ||
80 | #define S3C_CLKCON_HCLK_LCD (1<<3) | ||
81 | #define S3C_CLKCON_HCLK_TZIC (1<<2) | ||
82 | #define S3C_CLKCON_HCLK_INTC (1<<1) | ||
83 | #define S3C_CLKCON_HCLK_MFC (1<<0) | ||
84 | |||
85 | /* PCLK GATE Registers */ | 28 | /* PCLK GATE Registers */ |
86 | #define S3C6410_CLKCON_PCLK_I2C1 (1<<27) | ||
87 | #define S3C6410_CLKCON_PCLK_IIS2 (1<<26) | ||
88 | #define S3C_CLKCON_PCLK_SKEY (1<<24) | ||
89 | #define S3C_CLKCON_PCLK_CHIPID (1<<23) | ||
90 | #define S3C_CLKCON_PCLK_SPI1 (1<<22) | ||
91 | #define S3C_CLKCON_PCLK_SPI0 (1<<21) | ||
92 | #define S3C_CLKCON_PCLK_HSIRX (1<<20) | ||
93 | #define S3C_CLKCON_PCLK_HSITX (1<<19) | ||
94 | #define S3C_CLKCON_PCLK_GPIO (1<<18) | ||
95 | #define S3C_CLKCON_PCLK_IIC (1<<17) | ||
96 | #define S3C_CLKCON_PCLK_IIS1 (1<<16) | ||
97 | #define S3C_CLKCON_PCLK_IIS0 (1<<15) | ||
98 | #define S3C_CLKCON_PCLK_AC97 (1<<14) | ||
99 | #define S3C_CLKCON_PCLK_TZPC (1<<13) | ||
100 | #define S3C_CLKCON_PCLK_TSADC (1<<12) | ||
101 | #define S3C_CLKCON_PCLK_KEYPAD (1<<11) | ||
102 | #define S3C_CLKCON_PCLK_IRDA (1<<10) | ||
103 | #define S3C_CLKCON_PCLK_PCM1 (1<<9) | ||
104 | #define S3C_CLKCON_PCLK_PCM0 (1<<8) | ||
105 | #define S3C_CLKCON_PCLK_PWM (1<<7) | ||
106 | #define S3C_CLKCON_PCLK_RTC (1<<6) | ||
107 | #define S3C_CLKCON_PCLK_WDT (1<<5) | ||
108 | #define S3C_CLKCON_PCLK_UART3 (1<<4) | 29 | #define S3C_CLKCON_PCLK_UART3 (1<<4) |
109 | #define S3C_CLKCON_PCLK_UART2 (1<<3) | 30 | #define S3C_CLKCON_PCLK_UART2 (1<<3) |
110 | #define S3C_CLKCON_PCLK_UART1 (1<<2) | 31 | #define S3C_CLKCON_PCLK_UART1 (1<<2) |
111 | #define S3C_CLKCON_PCLK_UART0 (1<<1) | 32 | #define S3C_CLKCON_PCLK_UART0 (1<<1) |
112 | #define S3C_CLKCON_PCLK_MFC (1<<0) | ||
113 | |||
114 | /* SCLK GATE Registers */ | ||
115 | #define S3C_CLKCON_SCLK_UHOST (1<<30) | ||
116 | #define S3C_CLKCON_SCLK_MMC2_48 (1<<29) | ||
117 | #define S3C_CLKCON_SCLK_MMC1_48 (1<<28) | ||
118 | #define S3C_CLKCON_SCLK_MMC0_48 (1<<27) | ||
119 | #define S3C_CLKCON_SCLK_MMC2 (1<<26) | ||
120 | #define S3C_CLKCON_SCLK_MMC1 (1<<25) | ||
121 | #define S3C_CLKCON_SCLK_MMC0 (1<<24) | ||
122 | #define S3C_CLKCON_SCLK_SPI1_48 (1<<23) | ||
123 | #define S3C_CLKCON_SCLK_SPI0_48 (1<<22) | ||
124 | #define S3C_CLKCON_SCLK_SPI1 (1<<21) | ||
125 | #define S3C_CLKCON_SCLK_SPI0 (1<<20) | ||
126 | #define S3C_CLKCON_SCLK_DAC27 (1<<19) | ||
127 | #define S3C_CLKCON_SCLK_TV27 (1<<18) | ||
128 | #define S3C_CLKCON_SCLK_SCALER27 (1<<17) | ||
129 | #define S3C_CLKCON_SCLK_SCALER (1<<16) | ||
130 | #define S3C_CLKCON_SCLK_LCD27 (1<<15) | ||
131 | #define S3C_CLKCON_SCLK_LCD (1<<14) | ||
132 | #define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) | ||
133 | #define S3C6410_CLKCON_FIMC (1<<13) | ||
134 | #define S3C_CLKCON_SCLK_POST0_27 (1<<12) | ||
135 | #define S3C6400_CLKCON_SCLK_POST1 (1<<11) | ||
136 | #define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) | ||
137 | #define S3C_CLKCON_SCLK_POST0 (1<<10) | ||
138 | #define S3C_CLKCON_SCLK_AUDIO1 (1<<9) | ||
139 | #define S3C_CLKCON_SCLK_AUDIO0 (1<<8) | ||
140 | #define S3C_CLKCON_SCLK_SECUR (1<<7) | ||
141 | #define S3C_CLKCON_SCLK_IRDA (1<<6) | ||
142 | #define S3C_CLKCON_SCLK_UART (1<<5) | ||
143 | #define S3C_CLKCON_SCLK_ONENAND (1<<4) | ||
144 | #define S3C_CLKCON_SCLK_MFC (1<<3) | ||
145 | #define S3C_CLKCON_SCLK_CAM (1<<2) | ||
146 | #define S3C_CLKCON_SCLK_JPEG (1<<1) | ||
147 | |||
148 | /* CLKSRC */ | ||
149 | |||
150 | #define S3C6400_CLKSRC_APLL_MOUT (1 << 0) | ||
151 | #define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) | ||
152 | #define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) | ||
153 | #define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) | ||
154 | #define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) | ||
155 | #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) | ||
156 | #define S3C6400_CLKSRC_MFC (1 << 4) | ||
157 | 33 | ||
158 | /* MEM_SYS_CFG */ | 34 | /* MEM_SYS_CFG */ |
159 | #define MEM_SYS_CFG_INDEP_CF 0x4000 | 35 | #define MEM_SYS_CFG_INDEP_CF 0x4000 |
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index 35e3f54574ef..d266dd5f7060 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c | |||
@@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = { | |||
207 | static void __init anw6410_map_io(void) | 207 | static void __init anw6410_map_io(void) |
208 | { | 208 | { |
209 | s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); | 209 | s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); |
210 | s3c24xx_init_clocks(12000000); | 210 | s3c64xx_set_xtal_freq(12000000); |
211 | s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); | 211 | s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); |
212 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 212 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
213 | 213 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index eb8e5a1aca42..1a911df9e451 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c | |||
@@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = { | |||
743 | static void __init crag6410_map_io(void) | 743 | static void __init crag6410_map_io(void) |
744 | { | 744 | { |
745 | s3c64xx_init_io(NULL, 0); | 745 | s3c64xx_init_io(NULL, 0); |
746 | s3c24xx_init_clocks(12000000); | 746 | s3c64xx_set_xtal_freq(12000000); |
747 | s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); | 747 | s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); |
748 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 748 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
749 | 749 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index f39569e0f2e6..e8064044ef79 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c | |||
@@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = { | |||
247 | static void __init hmt_map_io(void) | 247 | static void __init hmt_map_io(void) |
248 | { | 248 | { |
249 | s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); | 249 | s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); |
250 | s3c24xx_init_clocks(12000000); | 250 | s3c64xx_set_xtal_freq(12000000); |
251 | s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); | 251 | s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); |
252 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 252 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
253 | } | 253 | } |
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index fc043e3ecdf8..58d46a3d7b78 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c | |||
@@ -231,7 +231,7 @@ static void __init mini6410_map_io(void) | |||
231 | u32 tmp; | 231 | u32 tmp; |
232 | 232 | ||
233 | s3c64xx_init_io(NULL, 0); | 233 | s3c64xx_init_io(NULL, 0); |
234 | s3c24xx_init_clocks(12000000); | 234 | s3c64xx_set_xtal_freq(12000000); |
235 | s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs)); | 235 | s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs)); |
236 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 236 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
237 | 237 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index 7e2c3908f1f8..2067b0bf55b4 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c | |||
@@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {}; | |||
86 | static void __init ncp_map_io(void) | 86 | static void __init ncp_map_io(void) |
87 | { | 87 | { |
88 | s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc)); | 88 | s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc)); |
89 | s3c24xx_init_clocks(12000000); | 89 | s3c64xx_set_xtal_freq(12000000); |
90 | s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs)); | 90 | s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs)); |
91 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 91 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
92 | } | 92 | } |
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 86d980b448fd..0f47237be3b2 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c | |||
@@ -337,13 +337,6 @@ err: | |||
337 | return ret; | 337 | return ret; |
338 | } | 338 | } |
339 | 339 | ||
340 | static int __init smartq_usb_otg_init(void) | ||
341 | { | ||
342 | clk_xusbxti.rate = 12000000; | ||
343 | |||
344 | return 0; | ||
345 | } | ||
346 | |||
347 | static int __init smartq_wifi_init(void) | 340 | static int __init smartq_wifi_init(void) |
348 | { | 341 | { |
349 | int ret; | 342 | int ret; |
@@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {}; | |||
377 | void __init smartq_map_io(void) | 370 | void __init smartq_map_io(void) |
378 | { | 371 | { |
379 | s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); | 372 | s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); |
380 | s3c24xx_init_clocks(12000000); | 373 | s3c64xx_set_xtal_freq(12000000); |
374 | s3c64xx_set_xusbxti_freq(12000000); | ||
381 | s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); | 375 | s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); |
382 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 376 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
383 | 377 | ||
@@ -399,7 +393,6 @@ void __init smartq_machine_init(void) | |||
399 | WARN_ON(smartq_lcd_setup_gpio()); | 393 | WARN_ON(smartq_lcd_setup_gpio()); |
400 | WARN_ON(smartq_power_off_init()); | 394 | WARN_ON(smartq_power_off_init()); |
401 | WARN_ON(smartq_usb_host_init()); | 395 | WARN_ON(smartq_usb_host_init()); |
402 | WARN_ON(smartq_usb_otg_init()); | ||
403 | WARN_ON(smartq_wifi_init()); | 396 | WARN_ON(smartq_wifi_init()); |
404 | 397 | ||
405 | platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); | 398 | platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index d70c0843aea2..27381cfcabbe 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c | |||
@@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {}; | |||
65 | static void __init smdk6400_map_io(void) | 65 | static void __init smdk6400_map_io(void) |
66 | { | 66 | { |
67 | s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); | 67 | s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); |
68 | s3c24xx_init_clocks(12000000); | 68 | s3c64xx_set_xtal_freq(12000000); |
69 | s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); | 69 | s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); |
70 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 70 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
71 | } | 71 | } |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d90b450c5645..2a7b32ca5c96 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c | |||
@@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void) | |||
634 | u32 tmp; | 634 | u32 tmp; |
635 | 635 | ||
636 | s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); | 636 | s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); |
637 | s3c24xx_init_clocks(12000000); | 637 | s3c64xx_set_xtal_freq(12000000); |
638 | s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); | 638 | s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); |
639 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | 639 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
640 | 640 | ||
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index 6a1f91fea678..8cdb824a3b43 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c | |||
@@ -194,29 +194,8 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear) | |||
194 | #endif | 194 | #endif |
195 | 195 | ||
196 | static struct sleep_save core_save[] = { | 196 | static struct sleep_save core_save[] = { |
197 | SAVE_ITEM(S3C_APLL_LOCK), | ||
198 | SAVE_ITEM(S3C_MPLL_LOCK), | ||
199 | SAVE_ITEM(S3C_EPLL_LOCK), | ||
200 | SAVE_ITEM(S3C_CLK_SRC), | ||
201 | SAVE_ITEM(S3C_CLK_DIV0), | ||
202 | SAVE_ITEM(S3C_CLK_DIV1), | ||
203 | SAVE_ITEM(S3C_CLK_DIV2), | ||
204 | SAVE_ITEM(S3C_CLK_OUT), | ||
205 | SAVE_ITEM(S3C_HCLK_GATE), | ||
206 | SAVE_ITEM(S3C_PCLK_GATE), | ||
207 | SAVE_ITEM(S3C_SCLK_GATE), | ||
208 | SAVE_ITEM(S3C_MEM0_GATE), | ||
209 | |||
210 | SAVE_ITEM(S3C_EPLL_CON1), | ||
211 | SAVE_ITEM(S3C_EPLL_CON0), | ||
212 | |||
213 | SAVE_ITEM(S3C64XX_MEM0DRVCON), | 197 | SAVE_ITEM(S3C64XX_MEM0DRVCON), |
214 | SAVE_ITEM(S3C64XX_MEM1DRVCON), | 198 | SAVE_ITEM(S3C64XX_MEM1DRVCON), |
215 | |||
216 | #ifndef CONFIG_CPU_FREQ | ||
217 | SAVE_ITEM(S3C_APLL_CON), | ||
218 | SAVE_ITEM(S3C_MPLL_CON), | ||
219 | #endif | ||
220 | }; | 199 | }; |
221 | 200 | ||
222 | static struct sleep_save misc_save[] = { | 201 | static struct sleep_save misc_save[] = { |
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 4869714c6f1b..331fe8e58145 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c | |||
@@ -58,12 +58,6 @@ void __init s3c6400_map_io(void) | |||
58 | s3c64xx_onenand1_setname("s3c6400-onenand"); | 58 | s3c64xx_onenand1_setname("s3c6400-onenand"); |
59 | } | 59 | } |
60 | 60 | ||
61 | void __init s3c6400_init_clocks(int xtal) | ||
62 | { | ||
63 | s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK); | ||
64 | s3c64xx_setup_clocks(); | ||
65 | } | ||
66 | |||
67 | void __init s3c6400_init_irq(void) | 61 | void __init s3c6400_init_irq(void) |
68 | { | 62 | { |
69 | /* VIC0 does not have IRQS 5..7, | 63 | /* VIC0 does not have IRQS 5..7, |
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 31c29fdf1800..7e6fa125584a 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c | |||
@@ -62,13 +62,6 @@ void __init s3c6410_map_io(void) | |||
62 | s3c_cfcon_setname("s3c64xx-pata"); | 62 | s3c_cfcon_setname("s3c64xx-pata"); |
63 | } | 63 | } |
64 | 64 | ||
65 | void __init s3c6410_init_clocks(int xtal) | ||
66 | { | ||
67 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); | ||
68 | s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK); | ||
69 | s3c64xx_setup_clocks(); | ||
70 | } | ||
71 | |||
72 | void __init s3c6410_init_irq(void) | 65 | void __init s3c6410_init_irq(void) |
73 | { | 66 | { |
74 | /* VIC0 is missing IRQ7, VIC1 is fully populated. */ | 67 | /* VIC0 is missing IRQ7, VIC1 is fully populated. */ |
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 1f94c310c477..5dd5f9f7897a 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
@@ -101,12 +101,24 @@ config ARCH_R8A7790 | |||
101 | select SH_CLK_CPG | 101 | select SH_CLK_CPG |
102 | select RENESAS_IRQC | 102 | select RENESAS_IRQC |
103 | 103 | ||
104 | config ARCH_R8A7791 | ||
105 | bool "R-Car M2 (R8A77910)" | ||
106 | select ARM_GIC | ||
107 | select CPU_V7 | ||
108 | select SH_CLK_CPG | ||
109 | |||
104 | config ARCH_EMEV2 | 110 | config ARCH_EMEV2 |
105 | bool "Emma Mobile EV2" | 111 | bool "Emma Mobile EV2" |
106 | select ARCH_WANT_OPTIONAL_GPIOLIB | 112 | select ARCH_WANT_OPTIONAL_GPIOLIB |
107 | select ARM_GIC | 113 | select ARM_GIC |
108 | select CPU_V7 | 114 | select CPU_V7 |
109 | 115 | ||
116 | config ARCH_R7S72100 | ||
117 | bool "RZ/A1H (R7S72100)" | ||
118 | select ARM_GIC | ||
119 | select CPU_V7 | ||
120 | select SH_CLK_CPG | ||
121 | |||
110 | comment "SH-Mobile Board Type" | 122 | comment "SH-Mobile Board Type" |
111 | 123 | ||
112 | config MACH_APE6EVM | 124 | config MACH_APE6EVM |
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 2705bfa8c113..f2d40edadcc9 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
@@ -15,7 +15,10 @@ obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o | |||
15 | obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o | 15 | obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o |
16 | obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o | 16 | obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o |
17 | obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o | 17 | obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o |
18 | obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o setup-rcar-gen2.o | ||
19 | obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o setup-rcar-gen2.o | ||
18 | obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o | 20 | obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o |
21 | obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o | ||
19 | 22 | ||
20 | # Clock objects | 23 | # Clock objects |
21 | ifndef CONFIG_COMMON_CLK | 24 | ifndef CONFIG_COMMON_CLK |
@@ -27,13 +30,17 @@ obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o | |||
27 | obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o | 30 | obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o |
28 | obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o | 31 | obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o |
29 | obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o | 32 | obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o |
33 | obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o | ||
30 | obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o | 34 | obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o |
35 | obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o | ||
31 | endif | 36 | endif |
32 | 37 | ||
33 | # SMP objects | 38 | # SMP objects |
34 | smp-y := platsmp.o headsmp.o | 39 | smp-y := platsmp.o headsmp.o |
35 | smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o | 40 | smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o |
36 | smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o | 41 | smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o |
42 | smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o platsmp-apmu.o | ||
43 | smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o platsmp-apmu.o | ||
37 | smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o | 44 | smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o |
38 | 45 | ||
39 | # IRQ objects | 46 | # IRQ objects |
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 2856f51ff8a6..1a1a4a888632 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c | |||
@@ -38,8 +38,9 @@ static const char *lager_boards_compat_dt[] __initdata = { | |||
38 | }; | 38 | }; |
39 | 39 | ||
40 | DT_MACHINE_START(LAGER_DT, "lager") | 40 | DT_MACHINE_START(LAGER_DT, "lager") |
41 | .smp = smp_ops(r8a7790_smp_ops), | ||
41 | .init_early = r8a7790_init_early, | 42 | .init_early = r8a7790_init_early, |
43 | .init_time = rcar_gen2_timer_init, | ||
42 | .init_machine = lager_add_standard_devices, | 44 | .init_machine = lager_add_standard_devices, |
43 | .init_time = r8a7790_timer_init, | ||
44 | .dt_compat = lager_boards_compat_dt, | 45 | .dt_compat = lager_boards_compat_dt, |
45 | MACHINE_END | 46 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 66edb7e10089..fd6146ca7a5a 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c | |||
@@ -186,8 +186,9 @@ static const char * const lager_boards_compat_dt[] __initconst = { | |||
186 | }; | 186 | }; |
187 | 187 | ||
188 | DT_MACHINE_START(LAGER_DT, "lager") | 188 | DT_MACHINE_START(LAGER_DT, "lager") |
189 | .smp = smp_ops(r8a7790_smp_ops), | ||
189 | .init_early = r8a7790_init_early, | 190 | .init_early = r8a7790_init_early, |
190 | .init_time = r8a7790_timer_init, | 191 | .init_time = rcar_gen2_timer_init, |
191 | .init_machine = lager_init, | 192 | .init_machine = lager_init, |
192 | .dt_compat = lager_boards_compat_dt, | 193 | .dt_compat = lager_boards_compat_dt, |
193 | MACHINE_END | 194 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c new file mode 100644 index 000000000000..4aba20ca127e --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r7s72100.c | |||
@@ -0,0 +1,202 @@ | |||
1 | /* | ||
2 | * r7a72100 clock framework support | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
5 | * Copyright (C) 2012 Phil Edworthy | ||
6 | * Copyright (C) 2011 Magnus Damm | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; version 2 of the License. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | */ | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <linux/sh_clk.h> | ||
21 | #include <linux/clkdev.h> | ||
22 | #include <mach/common.h> | ||
23 | #include <mach/r7s72100.h> | ||
24 | |||
25 | /* registers */ | ||
26 | #define FRQCR 0xfcfe0010 | ||
27 | #define FRQCR2 0xfcfe0014 | ||
28 | #define STBCR3 0xfcfe0420 | ||
29 | #define STBCR4 0xfcfe0424 | ||
30 | |||
31 | #define PLL_RATE 30 | ||
32 | |||
33 | static struct clk_mapping cpg_mapping = { | ||
34 | .phys = 0xfcfe0000, | ||
35 | .len = 0x1000, | ||
36 | }; | ||
37 | |||
38 | /* Fixed 32 KHz root clock for RTC */ | ||
39 | static struct clk r_clk = { | ||
40 | .rate = 32768, | ||
41 | }; | ||
42 | |||
43 | /* | ||
44 | * Default rate for the root input clock, reset this with clk_set_rate() | ||
45 | * from the platform code. | ||
46 | */ | ||
47 | static struct clk extal_clk = { | ||
48 | .rate = 13330000, | ||
49 | .mapping = &cpg_mapping, | ||
50 | }; | ||
51 | |||
52 | static unsigned long pll_recalc(struct clk *clk) | ||
53 | { | ||
54 | return clk->parent->rate * PLL_RATE; | ||
55 | } | ||
56 | |||
57 | static struct sh_clk_ops pll_clk_ops = { | ||
58 | .recalc = pll_recalc, | ||
59 | }; | ||
60 | |||
61 | static struct clk pll_clk = { | ||
62 | .ops = &pll_clk_ops, | ||
63 | .parent = &extal_clk, | ||
64 | .flags = CLK_ENABLE_ON_INIT, | ||
65 | }; | ||
66 | |||
67 | static unsigned long bus_recalc(struct clk *clk) | ||
68 | { | ||
69 | return clk->parent->rate * 2 / 3; | ||
70 | } | ||
71 | |||
72 | static struct sh_clk_ops bus_clk_ops = { | ||
73 | .recalc = bus_recalc, | ||
74 | }; | ||
75 | |||
76 | static struct clk bus_clk = { | ||
77 | .ops = &bus_clk_ops, | ||
78 | .parent = &pll_clk, | ||
79 | .flags = CLK_ENABLE_ON_INIT, | ||
80 | }; | ||
81 | |||
82 | static unsigned long peripheral0_recalc(struct clk *clk) | ||
83 | { | ||
84 | return clk->parent->rate / 12; | ||
85 | } | ||
86 | |||
87 | static struct sh_clk_ops peripheral0_clk_ops = { | ||
88 | .recalc = peripheral0_recalc, | ||
89 | }; | ||
90 | |||
91 | static struct clk peripheral0_clk = { | ||
92 | .ops = &peripheral0_clk_ops, | ||
93 | .parent = &pll_clk, | ||
94 | .flags = CLK_ENABLE_ON_INIT, | ||
95 | }; | ||
96 | |||
97 | static unsigned long peripheral1_recalc(struct clk *clk) | ||
98 | { | ||
99 | return clk->parent->rate / 6; | ||
100 | } | ||
101 | |||
102 | static struct sh_clk_ops peripheral1_clk_ops = { | ||
103 | .recalc = peripheral1_recalc, | ||
104 | }; | ||
105 | |||
106 | static struct clk peripheral1_clk = { | ||
107 | .ops = &peripheral1_clk_ops, | ||
108 | .parent = &pll_clk, | ||
109 | .flags = CLK_ENABLE_ON_INIT, | ||
110 | }; | ||
111 | |||
112 | struct clk *main_clks[] = { | ||
113 | &r_clk, | ||
114 | &extal_clk, | ||
115 | &pll_clk, | ||
116 | &bus_clk, | ||
117 | &peripheral0_clk, | ||
118 | &peripheral1_clk, | ||
119 | }; | ||
120 | |||
121 | static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */ | ||
122 | static int multipliers[] = { 1, 2, 1, 1 }; | ||
123 | |||
124 | static struct clk_div_mult_table div4_div_mult_table = { | ||
125 | .divisors = div2, | ||
126 | .nr_divisors = ARRAY_SIZE(div2), | ||
127 | .multipliers = multipliers, | ||
128 | .nr_multipliers = ARRAY_SIZE(multipliers), | ||
129 | }; | ||
130 | |||
131 | static struct clk_div4_table div4_table = { | ||
132 | .div_mult_table = &div4_div_mult_table, | ||
133 | }; | ||
134 | |||
135 | enum { DIV4_I, | ||
136 | DIV4_NR }; | ||
137 | |||
138 | #define DIV4(_reg, _bit, _mask, _flags) \ | ||
139 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) | ||
140 | |||
141 | /* The mask field specifies the div2 entries that are valid */ | ||
142 | struct clk div4_clks[DIV4_NR] = { | ||
143 | [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT | ||
144 | | CLK_ENABLE_ON_INIT), | ||
145 | }; | ||
146 | |||
147 | enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | ||
148 | MSTP33, MSTP_NR }; | ||
149 | |||
150 | static struct clk mstp_clks[MSTP_NR] = { | ||
151 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ | ||
152 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ | ||
153 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ | ||
154 | [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */ | ||
155 | [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */ | ||
156 | [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */ | ||
157 | [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */ | ||
158 | [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */ | ||
159 | [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */ | ||
160 | }; | ||
161 | |||
162 | static struct clk_lookup lookups[] = { | ||
163 | /* main clocks */ | ||
164 | CLKDEV_CON_ID("rclk", &r_clk), | ||
165 | CLKDEV_CON_ID("extal", &extal_clk), | ||
166 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
167 | CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk), | ||
168 | |||
169 | /* DIV4 clocks */ | ||
170 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
171 | |||
172 | /* MSTP clocks */ | ||
173 | CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), | ||
174 | CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), | ||
175 | CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), | ||
176 | CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]), | ||
177 | CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]), | ||
178 | CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]), | ||
179 | CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]), | ||
180 | CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]), | ||
181 | }; | ||
182 | |||
183 | void __init r7s72100_clock_init(void) | ||
184 | { | ||
185 | int k, ret = 0; | ||
186 | |||
187 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | ||
188 | ret = clk_register(main_clks[k]); | ||
189 | |||
190 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
191 | |||
192 | if (!ret) | ||
193 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | ||
194 | |||
195 | if (!ret) | ||
196 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); | ||
197 | |||
198 | if (!ret) | ||
199 | shmobile_clk_init(); | ||
200 | else | ||
201 | panic("failed to setup rza1 clocks\n"); | ||
202 | } | ||
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 5bd2e851e3c7..571409b611d3 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c | |||
@@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = { | |||
504 | 504 | ||
505 | /* MSTP */ | 505 | /* MSTP */ |
506 | enum { | 506 | enum { |
507 | MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, | 507 | MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, |
508 | MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, | 508 | MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, |
509 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, | 509 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, |
510 | MSTP411, MSTP410, MSTP409, | 510 | MSTP411, MSTP410, MSTP409, |
@@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
519 | [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ | 519 | [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ |
520 | [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ | 520 | [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ |
521 | [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ | 521 | [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ |
522 | [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */ | ||
522 | [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ | 523 | [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ |
523 | [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ | 524 | [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ |
524 | [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ | 525 | [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ |
@@ -578,6 +579,8 @@ static struct clk_lookup lookups[] = { | |||
578 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), | 579 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), |
579 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), | 580 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), |
580 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), | 581 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), |
582 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), | ||
583 | CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]), | ||
581 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | 584 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), |
582 | CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), | 585 | CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), |
583 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), | 586 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), |
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index c4bf2d8fb111..fb6af83858e3 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c | |||
@@ -69,6 +69,15 @@ static struct clk extal_clk = { | |||
69 | .mapping = &cpg_mapping, | 69 | .mapping = &cpg_mapping, |
70 | }; | 70 | }; |
71 | 71 | ||
72 | static struct clk audio_clk_a = { | ||
73 | }; | ||
74 | |||
75 | static struct clk audio_clk_b = { | ||
76 | }; | ||
77 | |||
78 | static struct clk audio_clk_c = { | ||
79 | }; | ||
80 | |||
72 | /* | 81 | /* |
73 | * clock ratio of these clock will be updated | 82 | * clock ratio of these clock will be updated |
74 | * on r8a7778_clock_init() | 83 | * on r8a7778_clock_init() |
@@ -100,18 +109,23 @@ static struct clk *main_clks[] = { | |||
100 | &p_clk, | 109 | &p_clk, |
101 | &g_clk, | 110 | &g_clk, |
102 | &z_clk, | 111 | &z_clk, |
112 | &audio_clk_a, | ||
113 | &audio_clk_b, | ||
114 | &audio_clk_c, | ||
103 | }; | 115 | }; |
104 | 116 | ||
105 | enum { | 117 | enum { |
106 | MSTP331, | 118 | MSTP331, |
107 | MSTP323, MSTP322, MSTP321, | 119 | MSTP323, MSTP322, MSTP321, |
120 | MSTP311, MSTP310, | ||
121 | MSTP309, MSTP308, MSTP307, | ||
108 | MSTP114, | 122 | MSTP114, |
109 | MSTP110, MSTP109, | 123 | MSTP110, MSTP109, |
110 | MSTP100, | 124 | MSTP100, |
111 | MSTP030, | 125 | MSTP030, |
112 | MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, | 126 | MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, |
113 | MSTP016, MSTP015, | 127 | MSTP016, MSTP015, MSTP012, MSTP011, MSTP010, |
114 | MSTP007, | 128 | MSTP009, MSTP008, MSTP007, |
115 | MSTP_NR }; | 129 | MSTP_NR }; |
116 | 130 | ||
117 | static struct clk mstp_clks[MSTP_NR] = { | 131 | static struct clk mstp_clks[MSTP_NR] = { |
@@ -119,6 +133,11 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
119 | [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ | 133 | [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ |
120 | [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ | 134 | [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ |
121 | [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ | 135 | [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ |
136 | [MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */ | ||
137 | [MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */ | ||
138 | [MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */ | ||
139 | [MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */ | ||
140 | [MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */ | ||
122 | [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ | 141 | [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ |
123 | [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ | 142 | [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ |
124 | [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ | 143 | [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ |
@@ -135,11 +154,20 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
135 | [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ | 154 | [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ |
136 | [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ | 155 | [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ |
137 | [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ | 156 | [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ |
157 | [MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */ | ||
158 | [MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */ | ||
159 | [MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */ | ||
160 | [MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */ | ||
161 | [MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */ | ||
138 | [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ | 162 | [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ |
139 | }; | 163 | }; |
140 | 164 | ||
141 | static struct clk_lookup lookups[] = { | 165 | static struct clk_lookup lookups[] = { |
142 | /* main */ | 166 | /* main */ |
167 | CLKDEV_CON_ID("audio_clk_a", &audio_clk_a), | ||
168 | CLKDEV_CON_ID("audio_clk_b", &audio_clk_b), | ||
169 | CLKDEV_CON_ID("audio_clk_c", &audio_clk_c), | ||
170 | CLKDEV_CON_ID("audio_clk_internal", &s1_clk), | ||
143 | CLKDEV_CON_ID("shyway_clk", &s_clk), | 171 | CLKDEV_CON_ID("shyway_clk", &s_clk), |
144 | CLKDEV_CON_ID("peripheral_clk", &p_clk), | 172 | CLKDEV_CON_ID("peripheral_clk", &p_clk), |
145 | 173 | ||
@@ -153,6 +181,7 @@ static struct clk_lookup lookups[] = { | |||
153 | CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ | 181 | CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ |
154 | CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ | 182 | CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ |
155 | CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ | 183 | CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ |
184 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ | ||
156 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ | 185 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ |
157 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ | 186 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ |
158 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ | 187 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ |
@@ -168,6 +197,17 @@ static struct clk_lookup lookups[] = { | |||
168 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ | 197 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ |
169 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ | 198 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ |
170 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ | 199 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ |
200 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ | ||
201 | |||
202 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), | ||
203 | CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]), | ||
204 | CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]), | ||
205 | CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]), | ||
206 | CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]), | ||
207 | CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]), | ||
208 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), | ||
209 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), | ||
210 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), | ||
171 | }; | 211 | }; |
172 | 212 | ||
173 | void __init r8a7778_clock_init(void) | 213 | void __init r8a7778_clock_init(void) |
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index bd6ad922eb7e..1f7080fab0a5 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c | |||
@@ -200,7 +200,7 @@ static struct clk_lookup lookups[] = { | |||
200 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ | 200 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ |
201 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ | 201 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ |
202 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ | 202 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ |
203 | CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ | 203 | CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ |
204 | }; | 204 | }; |
205 | 205 | ||
206 | void __init r8a7779_clock_init(void) | 206 | void __init r8a7779_clock_init(void) |
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index fc36d3db0b4d..a64f965c7da1 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
@@ -52,6 +52,7 @@ | |||
52 | #define SMSTPCR5 0xe6150144 | 52 | #define SMSTPCR5 0xe6150144 |
53 | #define SMSTPCR7 0xe615014c | 53 | #define SMSTPCR7 0xe615014c |
54 | #define SMSTPCR8 0xe6150990 | 54 | #define SMSTPCR8 0xe6150990 |
55 | #define SMSTPCR9 0xe6150994 | ||
55 | 56 | ||
56 | #define SDCKCR 0xE6150074 | 57 | #define SDCKCR 0xE6150074 |
57 | #define SD2CKCR 0xE6150078 | 58 | #define SD2CKCR 0xE6150078 |
@@ -181,8 +182,9 @@ static struct clk div6_clks[DIV6_NR] = { | |||
181 | 182 | ||
182 | /* MSTP */ | 183 | /* MSTP */ |
183 | enum { | 184 | enum { |
185 | MSTP931, MSTP930, MSTP929, MSTP928, | ||
184 | MSTP813, | 186 | MSTP813, |
185 | MSTP721, MSTP720, | 187 | MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, |
186 | MSTP717, MSTP716, | 188 | MSTP717, MSTP716, |
187 | MSTP522, | 189 | MSTP522, |
188 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, | 190 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, |
@@ -192,7 +194,16 @@ enum { | |||
192 | }; | 194 | }; |
193 | 195 | ||
194 | static struct clk mstp_clks[MSTP_NR] = { | 196 | static struct clk mstp_clks[MSTP_NR] = { |
197 | [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ | ||
198 | [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ | ||
199 | [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ | ||
200 | [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ | ||
195 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ | 201 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ |
202 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ | ||
203 | [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ | ||
204 | [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ | ||
205 | [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ | ||
206 | [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */ | ||
196 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ | 207 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ |
197 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | 208 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
198 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ | 209 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ |
@@ -251,6 +262,11 @@ static struct clk_lookup lookups[] = { | |||
251 | CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), | 262 | CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), |
252 | 263 | ||
253 | /* MSTP */ | 264 | /* MSTP */ |
265 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), | ||
266 | CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), | ||
267 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), | ||
268 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), | ||
269 | CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), | ||
254 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), | 270 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), |
255 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), | 271 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), |
256 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), | 272 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), |
@@ -261,6 +277,10 @@ static struct clk_lookup lookups[] = { | |||
261 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), | 277 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), |
262 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), | 278 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), |
263 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), | 279 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), |
280 | CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), | ||
281 | CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), | ||
282 | CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), | ||
283 | CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), | ||
264 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), | 284 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), |
265 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | 285 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), |
266 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), | 286 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), |
@@ -290,7 +310,7 @@ static struct clk_lookup lookups[] = { | |||
290 | 310 | ||
291 | void __init r8a7790_clock_init(void) | 311 | void __init r8a7790_clock_init(void) |
292 | { | 312 | { |
293 | u32 mode = r8a7790_read_mode_pins(); | 313 | u32 mode = rcar_gen2_read_mode_pins(); |
294 | int k, ret = 0; | 314 | int k, ret = 0; |
295 | 315 | ||
296 | switch (mode & (MD(14) | MD(13))) { | 316 | switch (mode & (MD(14) | MD(13))) { |
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c new file mode 100644 index 000000000000..c9a26f16ce5b --- /dev/null +++ b/arch/arm/mach-shmobile/clock-r8a7791.c | |||
@@ -0,0 +1,237 @@ | |||
1 | /* | ||
2 | * r8a7791 clock framework support | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Electronics Corporation | ||
5 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
6 | * Copyright (C) 2013 Magnus Damm | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; version 2 of the License. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
20 | */ | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/sh_clk.h> | ||
25 | #include <linux/clkdev.h> | ||
26 | #include <mach/clock.h> | ||
27 | #include <mach/common.h> | ||
28 | |||
29 | /* | ||
30 | * MD EXTAL PLL0 PLL1 PLL3 | ||
31 | * 14 13 19 (MHz) *1 *1 | ||
32 | *--------------------------------------------------- | ||
33 | * 0 0 0 15 x 1 x172/2 x208/2 x106 | ||
34 | * 0 0 1 15 x 1 x172/2 x208/2 x88 | ||
35 | * 0 1 0 20 x 1 x130/2 x156/2 x80 | ||
36 | * 0 1 1 20 x 1 x130/2 x156/2 x66 | ||
37 | * 1 0 0 26 / 2 x200/2 x240/2 x122 | ||
38 | * 1 0 1 26 / 2 x200/2 x240/2 x102 | ||
39 | * 1 1 0 30 / 2 x172/2 x208/2 x106 | ||
40 | * 1 1 1 30 / 2 x172/2 x208/2 x88 | ||
41 | * | ||
42 | * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) | ||
43 | * see "p1 / 2" on R8A7791_CLOCK_ROOT() below | ||
44 | */ | ||
45 | |||
46 | #define MD(nr) (1 << nr) | ||
47 | |||
48 | #define CPG_BASE 0xe6150000 | ||
49 | #define CPG_LEN 0x1000 | ||
50 | |||
51 | #define SMSTPCR0 0xE6150130 | ||
52 | #define SMSTPCR1 0xE6150134 | ||
53 | #define SMSTPCR2 0xe6150138 | ||
54 | #define SMSTPCR3 0xE615013C | ||
55 | #define SMSTPCR5 0xE6150144 | ||
56 | #define SMSTPCR7 0xe615014c | ||
57 | #define SMSTPCR8 0xE6150990 | ||
58 | #define SMSTPCR9 0xE6150994 | ||
59 | #define SMSTPCR10 0xE6150998 | ||
60 | #define SMSTPCR11 0xE615099C | ||
61 | |||
62 | #define MODEMR 0xE6160060 | ||
63 | #define SDCKCR 0xE6150074 | ||
64 | #define SD2CKCR 0xE6150078 | ||
65 | #define SD3CKCR 0xE615007C | ||
66 | #define MMC0CKCR 0xE6150240 | ||
67 | #define MMC1CKCR 0xE6150244 | ||
68 | #define SSPCKCR 0xE6150248 | ||
69 | #define SSPRSCKCR 0xE615024C | ||
70 | |||
71 | static struct clk_mapping cpg_mapping = { | ||
72 | .phys = CPG_BASE, | ||
73 | .len = CPG_LEN, | ||
74 | }; | ||
75 | |||
76 | static struct clk extal_clk = { | ||
77 | /* .rate will be updated on r8a7791_clock_init() */ | ||
78 | .mapping = &cpg_mapping, | ||
79 | }; | ||
80 | |||
81 | static struct sh_clk_ops followparent_clk_ops = { | ||
82 | .recalc = followparent_recalc, | ||
83 | }; | ||
84 | |||
85 | static struct clk main_clk = { | ||
86 | /* .parent will be set r8a73a4_clock_init */ | ||
87 | .ops = &followparent_clk_ops, | ||
88 | }; | ||
89 | |||
90 | /* | ||
91 | * clock ratio of these clock will be updated | ||
92 | * on r8a7791_clock_init() | ||
93 | */ | ||
94 | SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1); | ||
95 | SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1); | ||
96 | |||
97 | /* fixed ratio clock */ | ||
98 | SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2); | ||
99 | SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2); | ||
100 | |||
101 | SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2); | ||
102 | SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); | ||
103 | SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); | ||
104 | SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); | ||
105 | SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); | ||
106 | |||
107 | static struct clk *main_clks[] = { | ||
108 | &extal_clk, | ||
109 | &extal_div2_clk, | ||
110 | &main_clk, | ||
111 | &pll1_clk, | ||
112 | &pll1_div2_clk, | ||
113 | &pll3_clk, | ||
114 | &hp_clk, | ||
115 | &p_clk, | ||
116 | &rclk_clk, | ||
117 | &mp_clk, | ||
118 | &cp_clk, | ||
119 | }; | ||
120 | |||
121 | /* MSTP */ | ||
122 | enum { | ||
123 | MSTP721, MSTP720, | ||
124 | MSTP719, MSTP718, MSTP715, MSTP714, | ||
125 | MSTP216, MSTP207, MSTP206, | ||
126 | MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, | ||
127 | MSTP124, | ||
128 | MSTP_NR | ||
129 | }; | ||
130 | |||
131 | static struct clk mstp_clks[MSTP_NR] = { | ||
132 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ | ||
133 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | ||
134 | [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ | ||
135 | [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ | ||
136 | [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ | ||
137 | [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ | ||
138 | [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ | ||
139 | [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ | ||
140 | [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ | ||
141 | [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ | ||
142 | [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ | ||
143 | [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ | ||
144 | [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */ | ||
145 | [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */ | ||
146 | [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */ | ||
147 | [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */ | ||
148 | }; | ||
149 | |||
150 | static struct clk_lookup lookups[] = { | ||
151 | |||
152 | /* main clocks */ | ||
153 | CLKDEV_CON_ID("extal", &extal_clk), | ||
154 | CLKDEV_CON_ID("extal_div2", &extal_div2_clk), | ||
155 | CLKDEV_CON_ID("main", &main_clk), | ||
156 | CLKDEV_CON_ID("pll1", &pll1_clk), | ||
157 | CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), | ||
158 | CLKDEV_CON_ID("pll3", &pll3_clk), | ||
159 | CLKDEV_CON_ID("hp", &hp_clk), | ||
160 | CLKDEV_CON_ID("p", &p_clk), | ||
161 | CLKDEV_CON_ID("rclk", &rclk_clk), | ||
162 | CLKDEV_CON_ID("mp", &mp_clk), | ||
163 | CLKDEV_CON_ID("cp", &cp_clk), | ||
164 | CLKDEV_CON_ID("peripheral_clk", &hp_clk), | ||
165 | |||
166 | /* MSTP */ | ||
167 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ | ||
168 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ | ||
169 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ | ||
170 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */ | ||
171 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */ | ||
172 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */ | ||
173 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */ | ||
174 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */ | ||
175 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */ | ||
176 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */ | ||
177 | CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */ | ||
178 | CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */ | ||
179 | CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */ | ||
180 | CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ | ||
181 | CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ | ||
182 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | ||
183 | }; | ||
184 | |||
185 | #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ | ||
186 | extal_clk.rate = e * 1000 * 1000; \ | ||
187 | main_clk.parent = m; \ | ||
188 | SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \ | ||
189 | if (mode & MD(19)) \ | ||
190 | SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \ | ||
191 | else \ | ||
192 | SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1) | ||
193 | |||
194 | |||
195 | void __init r8a7791_clock_init(void) | ||
196 | { | ||
197 | void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); | ||
198 | u32 mode; | ||
199 | int k, ret = 0; | ||
200 | |||
201 | BUG_ON(!modemr); | ||
202 | mode = ioread32(modemr); | ||
203 | iounmap(modemr); | ||
204 | |||
205 | switch (mode & (MD(14) | MD(13))) { | ||
206 | case 0: | ||
207 | R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); | ||
208 | break; | ||
209 | case MD(13): | ||
210 | R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); | ||
211 | break; | ||
212 | case MD(14): | ||
213 | R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); | ||
214 | break; | ||
215 | case MD(13) | MD(14): | ||
216 | R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); | ||
217 | break; | ||
218 | } | ||
219 | |||
220 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | ||
221 | ret = clk_register(main_clks[k]); | ||
222 | |||
223 | if (!ret) | ||
224 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); | ||
225 | |||
226 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
227 | |||
228 | if (!ret) | ||
229 | shmobile_clk_init(); | ||
230 | else | ||
231 | goto epanic; | ||
232 | |||
233 | return; | ||
234 | |||
235 | epanic: | ||
236 | panic("failed to setup r8a7791 clocks\n"); | ||
237 | } | ||
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index f93751caf5cb..e5be5c88644b 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S | |||
@@ -40,6 +40,9 @@ shmobile_boot_fn: | |||
40 | .globl shmobile_boot_arg | 40 | .globl shmobile_boot_arg |
41 | shmobile_boot_arg: | 41 | shmobile_boot_arg: |
42 | 2: .space 4 | 42 | 2: .space 4 |
43 | .globl shmobile_boot_size | ||
44 | shmobile_boot_size: | ||
45 | .long . - shmobile_boot_vector | ||
43 | 46 | ||
44 | /* | 47 | /* |
45 | * Per-CPU SMP boot function/argument selection code based on MPIDR | 48 | * Per-CPU SMP boot function/argument selection code based on MPIDR |
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 7b938681e756..e31980590eb4 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h | |||
@@ -9,16 +9,23 @@ extern void shmobile_setup_console(void); | |||
9 | extern void shmobile_boot_vector(void); | 9 | extern void shmobile_boot_vector(void); |
10 | extern unsigned long shmobile_boot_fn; | 10 | extern unsigned long shmobile_boot_fn; |
11 | extern unsigned long shmobile_boot_arg; | 11 | extern unsigned long shmobile_boot_arg; |
12 | extern unsigned long shmobile_boot_size; | ||
12 | extern void shmobile_smp_boot(void); | 13 | extern void shmobile_smp_boot(void); |
13 | extern void shmobile_smp_sleep(void); | 14 | extern void shmobile_smp_sleep(void); |
14 | extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, | 15 | extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, |
15 | unsigned long arg); | 16 | unsigned long arg); |
17 | extern int shmobile_smp_cpu_disable(unsigned int cpu); | ||
18 | extern void shmobile_invalidate_start(void); | ||
16 | extern void shmobile_boot_scu(void); | 19 | extern void shmobile_boot_scu(void); |
17 | extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); | 20 | extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); |
18 | extern int shmobile_smp_scu_boot_secondary(unsigned int cpu, | ||
19 | struct task_struct *idle); | ||
20 | extern void shmobile_smp_scu_cpu_die(unsigned int cpu); | 21 | extern void shmobile_smp_scu_cpu_die(unsigned int cpu); |
21 | extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); | 22 | extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); |
23 | extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus); | ||
24 | extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu, | ||
25 | struct task_struct *idle); | ||
26 | extern void shmobile_smp_apmu_cpu_die(unsigned int cpu); | ||
27 | extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu); | ||
28 | extern void shmobile_invalidate_start(void); | ||
22 | struct clk; | 29 | struct clk; |
23 | extern int shmobile_clk_init(void); | 30 | extern int shmobile_clk_init(void); |
24 | extern void shmobile_handle_irq_intc(struct pt_regs *); | 31 | extern void shmobile_handle_irq_intc(struct pt_regs *); |
@@ -39,7 +46,6 @@ static inline int shmobile_cpuidle_init(void) { return 0; } | |||
39 | #endif | 46 | #endif |
40 | 47 | ||
41 | extern void __iomem *shmobile_scu_base; | 48 | extern void __iomem *shmobile_scu_base; |
42 | extern void shmobile_smp_init_cpus(unsigned int ncores); | ||
43 | 49 | ||
44 | static inline void __init shmobile_init_late(void) | 50 | static inline void __init shmobile_init_late(void) |
45 | { | 51 | { |
diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/include/mach/r7s72100.h new file mode 100644 index 000000000000..5f34b20ecd4a --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r7s72100.h | |||
@@ -0,0 +1,8 @@ | |||
1 | #ifndef __ASM_R7S72100_H__ | ||
2 | #define __ASM_R7S72100_H__ | ||
3 | |||
4 | void r7s72100_add_dt_devices(void); | ||
5 | void r7s72100_clock_init(void); | ||
6 | void r7s72100_init_early(void); | ||
7 | |||
8 | #endif /* __ASM_R7S72100_H__ */ | ||
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 5214338a6a47..ce8bdd1d8a8a 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h | |||
@@ -1,6 +1,15 @@ | |||
1 | #ifndef __ASM_R8A73A4_H__ | 1 | #ifndef __ASM_R8A73A4_H__ |
2 | #define __ASM_R8A73A4_H__ | 2 | #define __ASM_R8A73A4_H__ |
3 | 3 | ||
4 | /* DMA slave IDs */ | ||
5 | enum { | ||
6 | SHDMA_SLAVE_INVALID, | ||
7 | SHDMA_SLAVE_MMCIF0_TX, | ||
8 | SHDMA_SLAVE_MMCIF0_RX, | ||
9 | SHDMA_SLAVE_MMCIF1_TX, | ||
10 | SHDMA_SLAVE_MMCIF1_RX, | ||
11 | }; | ||
12 | |||
4 | void r8a73a4_add_standard_devices(void); | 13 | void r8a73a4_add_standard_devices(void); |
5 | void r8a73a4_add_dt_devices(void); | 14 | void r8a73a4_add_dt_devices(void); |
6 | void r8a73a4_clock_init(void); | 15 | void r8a73a4_clock_init(void); |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 48933def0d55..441886c9714b 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h | |||
@@ -1,6 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2013 Renesas Solutions Corp. | 2 | * Copyright (C) 2013 Renesas Solutions Corp. |
3 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 3 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
4 | * Copyright (C) 2013 Cogent Embedded, Inc. | ||
4 | * | 5 | * |
5 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
@@ -21,6 +22,13 @@ | |||
21 | #include <linux/sh_eth.h> | 22 | #include <linux/sh_eth.h> |
22 | #include <linux/platform_data/camera-rcar.h> | 23 | #include <linux/platform_data/camera-rcar.h> |
23 | 24 | ||
25 | /* HPB-DMA slave IDs */ | ||
26 | enum { | ||
27 | HPBDMA_SLAVE_DUMMY, | ||
28 | HPBDMA_SLAVE_SDHI0_TX, | ||
29 | HPBDMA_SLAVE_SDHI0_RX, | ||
30 | }; | ||
31 | |||
24 | extern void r8a7778_add_standard_devices(void); | 32 | extern void r8a7778_add_standard_devices(void); |
25 | extern void r8a7778_add_standard_devices_dt(void); | 33 | extern void r8a7778_add_standard_devices_dt(void); |
26 | extern void r8a7778_add_dt_devices(void); | 34 | extern void r8a7778_add_dt_devices(void); |
@@ -30,6 +38,9 @@ extern void r8a7778_init_delay(void); | |||
30 | extern void r8a7778_init_irq_dt(void); | 38 | extern void r8a7778_init_irq_dt(void); |
31 | extern void r8a7778_clock_init(void); | 39 | extern void r8a7778_clock_init(void); |
32 | extern void r8a7778_init_irq_extpin(int irlm); | 40 | extern void r8a7778_init_irq_extpin(int irlm); |
41 | extern void r8a7778_init_irq_extpin_dt(int irlm); | ||
33 | extern void r8a7778_pinmux_init(void); | 42 | extern void r8a7778_pinmux_init(void); |
34 | 43 | ||
44 | extern int r8a7778_usb_phy_power(bool enable); | ||
45 | |||
35 | #endif /* __ASM_R8A7778_H__ */ | 46 | #endif /* __ASM_R8A7778_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 11c740047e14..17af34ed89c8 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h | |||
@@ -6,6 +6,13 @@ | |||
6 | #include <linux/sh_eth.h> | 6 | #include <linux/sh_eth.h> |
7 | #include <linux/platform_data/camera-rcar.h> | 7 | #include <linux/platform_data/camera-rcar.h> |
8 | 8 | ||
9 | /* HPB-DMA slave IDs */ | ||
10 | enum { | ||
11 | HPBDMA_SLAVE_DUMMY, | ||
12 | HPBDMA_SLAVE_SDHI0_TX, | ||
13 | HPBDMA_SLAVE_SDHI0_RX, | ||
14 | }; | ||
15 | |||
9 | struct platform_device; | 16 | struct platform_device; |
10 | 17 | ||
11 | struct r8a7779_pm_ch { | 18 | struct r8a7779_pm_ch { |
@@ -26,6 +33,7 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) | |||
26 | 33 | ||
27 | extern void r8a7779_init_delay(void); | 34 | extern void r8a7779_init_delay(void); |
28 | extern void r8a7779_init_irq_extpin(int irlm); | 35 | extern void r8a7779_init_irq_extpin(int irlm); |
36 | extern void r8a7779_init_irq_extpin_dt(int irlm); | ||
29 | extern void r8a7779_init_irq_dt(void); | 37 | extern void r8a7779_init_irq_dt(void); |
30 | extern void r8a7779_map_io(void); | 38 | extern void r8a7779_map_io(void); |
31 | extern void r8a7779_earlytimer_init(void); | 39 | extern void r8a7779_earlytimer_init(void); |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 177a8372abb7..5fbfa28b40b6 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h | |||
@@ -1,14 +1,13 @@ | |||
1 | #ifndef __ASM_R8A7790_H__ | 1 | #ifndef __ASM_R8A7790_H__ |
2 | #define __ASM_R8A7790_H__ | 2 | #define __ASM_R8A7790_H__ |
3 | 3 | ||
4 | #include <mach/rcar-gen2.h> | ||
5 | |||
4 | void r8a7790_add_standard_devices(void); | 6 | void r8a7790_add_standard_devices(void); |
5 | void r8a7790_add_dt_devices(void); | 7 | void r8a7790_add_dt_devices(void); |
6 | void r8a7790_clock_init(void); | 8 | void r8a7790_clock_init(void); |
7 | void r8a7790_pinmux_init(void); | 9 | void r8a7790_pinmux_init(void); |
8 | void r8a7790_init_early(void); | 10 | void r8a7790_init_early(void); |
9 | void r8a7790_timer_init(void); | 11 | extern struct smp_operations r8a7790_smp_ops; |
10 | |||
11 | #define MD(nr) BIT(nr) | ||
12 | u32 r8a7790_read_mode_pins(void); | ||
13 | 12 | ||
14 | #endif /* __ASM_R8A7790_H__ */ | 13 | #endif /* __ASM_R8A7790_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h new file mode 100644 index 000000000000..051ead3c286e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h | |||
@@ -0,0 +1,10 @@ | |||
1 | #ifndef __ASM_R8A7791_H__ | ||
2 | #define __ASM_R8A7791_H__ | ||
3 | |||
4 | void r8a7791_add_standard_devices(void); | ||
5 | void r8a7791_add_dt_devices(void); | ||
6 | void r8a7791_clock_init(void); | ||
7 | void r8a7791_init_early(void); | ||
8 | extern struct smp_operations r8a7791_smp_ops; | ||
9 | |||
10 | #endif /* __ASM_R8A7791_H__ */ | ||
diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h new file mode 100644 index 000000000000..43f606eb2d82 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h | |||
@@ -0,0 +1,8 @@ | |||
1 | #ifndef __ASM_RCAR_GEN2_H__ | ||
2 | #define __ASM_RCAR_GEN2_H__ | ||
3 | |||
4 | void rcar_gen2_timer_init(void); | ||
5 | #define MD(nr) BIT(nr) | ||
6 | u32 rcar_gen2_read_mode_pins(void); | ||
7 | |||
8 | #endif /* __ASM_RCAR_GEN2_H__ */ | ||
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c new file mode 100644 index 000000000000..1da5a72d9642 --- /dev/null +++ b/arch/arm/mach-shmobile/platsmp-apmu.c | |||
@@ -0,0 +1,195 @@ | |||
1 | /* | ||
2 | * SMP support for SoCs with APMU | ||
3 | * | ||
4 | * Copyright (C) 2013 Magnus Damm | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <linux/delay.h> | ||
11 | #include <linux/init.h> | ||
12 | #include <linux/io.h> | ||
13 | #include <linux/ioport.h> | ||
14 | #include <linux/of_address.h> | ||
15 | #include <linux/smp.h> | ||
16 | #include <asm/cacheflush.h> | ||
17 | #include <asm/cp15.h> | ||
18 | #include <asm/smp_plat.h> | ||
19 | #include <mach/common.h> | ||
20 | |||
21 | static struct { | ||
22 | void __iomem *iomem; | ||
23 | int bit; | ||
24 | } apmu_cpus[CONFIG_NR_CPUS]; | ||
25 | |||
26 | #define WUPCR_OFFS 0x10 | ||
27 | #define PSTR_OFFS 0x40 | ||
28 | #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) | ||
29 | |||
30 | static int apmu_power_on(void __iomem *p, int bit) | ||
31 | { | ||
32 | /* request power on */ | ||
33 | writel_relaxed(BIT(bit), p + WUPCR_OFFS); | ||
34 | |||
35 | /* wait for APMU to finish */ | ||
36 | while (readl_relaxed(p + WUPCR_OFFS) != 0) | ||
37 | ; | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | static int apmu_power_off(void __iomem *p, int bit) | ||
43 | { | ||
44 | /* request Core Standby for next WFI */ | ||
45 | writel_relaxed(3, p + CPUNCR_OFFS(bit)); | ||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | static int apmu_power_off_poll(void __iomem *p, int bit) | ||
50 | { | ||
51 | int k; | ||
52 | |||
53 | for (k = 0; k < 1000; k++) { | ||
54 | if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) | ||
55 | return 1; | ||
56 | |||
57 | mdelay(1); | ||
58 | } | ||
59 | |||
60 | return 0; | ||
61 | } | ||
62 | |||
63 | static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) | ||
64 | { | ||
65 | void __iomem *p = apmu_cpus[cpu].iomem; | ||
66 | |||
67 | return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL; | ||
68 | } | ||
69 | |||
70 | static void apmu_init_cpu(struct resource *res, int cpu, int bit) | ||
71 | { | ||
72 | if (apmu_cpus[cpu].iomem) | ||
73 | return; | ||
74 | |||
75 | apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res)); | ||
76 | apmu_cpus[cpu].bit = bit; | ||
77 | |||
78 | pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit, | ||
79 | res->start, resource_size(res)); | ||
80 | } | ||
81 | |||
82 | static struct { | ||
83 | struct resource iomem; | ||
84 | int cpus[4]; | ||
85 | } apmu_config[] = { | ||
86 | { | ||
87 | .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), | ||
88 | .cpus = { 0, 1, 2, 3 }, | ||
89 | }, | ||
90 | { | ||
91 | .iomem = DEFINE_RES_MEM(0xe6151000, 0x88), | ||
92 | .cpus = { 0x100, 0x101, 0x102, 0x103 }, | ||
93 | } | ||
94 | }; | ||
95 | |||
96 | static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit)) | ||
97 | { | ||
98 | u32 id; | ||
99 | int k; | ||
100 | int bit, index; | ||
101 | bool is_allowed; | ||
102 | |||
103 | for (k = 0; k < ARRAY_SIZE(apmu_config); k++) { | ||
104 | /* only enable the cluster that includes the boot CPU */ | ||
105 | is_allowed = false; | ||
106 | for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { | ||
107 | id = apmu_config[k].cpus[bit]; | ||
108 | if (id >= 0) { | ||
109 | if (id == cpu_logical_map(0)) | ||
110 | is_allowed = true; | ||
111 | } | ||
112 | } | ||
113 | if (!is_allowed) | ||
114 | continue; | ||
115 | |||
116 | for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { | ||
117 | id = apmu_config[k].cpus[bit]; | ||
118 | if (id >= 0) { | ||
119 | index = get_logical_index(id); | ||
120 | if (index >= 0) | ||
121 | fn(&apmu_config[k].iomem, index, bit); | ||
122 | } | ||
123 | } | ||
124 | } | ||
125 | } | ||
126 | |||
127 | void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus) | ||
128 | { | ||
129 | /* install boot code shared by all CPUs */ | ||
130 | shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); | ||
131 | shmobile_boot_arg = MPIDR_HWID_BITMASK; | ||
132 | |||
133 | /* perform per-cpu setup */ | ||
134 | apmu_parse_cfg(apmu_init_cpu); | ||
135 | } | ||
136 | |||
137 | int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
138 | { | ||
139 | /* For this particular CPU register boot vector */ | ||
140 | shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); | ||
141 | |||
142 | return apmu_wrap(cpu, apmu_power_on); | ||
143 | } | ||
144 | |||
145 | #ifdef CONFIG_HOTPLUG_CPU | ||
146 | /* nicked from arch/arm/mach-exynos/hotplug.c */ | ||
147 | static inline void cpu_enter_lowpower_a15(void) | ||
148 | { | ||
149 | unsigned int v; | ||
150 | |||
151 | asm volatile( | ||
152 | " mrc p15, 0, %0, c1, c0, 0\n" | ||
153 | " bic %0, %0, %1\n" | ||
154 | " mcr p15, 0, %0, c1, c0, 0\n" | ||
155 | : "=&r" (v) | ||
156 | : "Ir" (CR_C) | ||
157 | : "cc"); | ||
158 | |||
159 | flush_cache_louis(); | ||
160 | |||
161 | asm volatile( | ||
162 | /* | ||
163 | * Turn off coherency | ||
164 | */ | ||
165 | " mrc p15, 0, %0, c1, c0, 1\n" | ||
166 | " bic %0, %0, %1\n" | ||
167 | " mcr p15, 0, %0, c1, c0, 1\n" | ||
168 | : "=&r" (v) | ||
169 | : "Ir" (0x40) | ||
170 | : "cc"); | ||
171 | |||
172 | isb(); | ||
173 | dsb(); | ||
174 | } | ||
175 | |||
176 | void shmobile_smp_apmu_cpu_die(unsigned int cpu) | ||
177 | { | ||
178 | /* For this particular CPU deregister boot vector */ | ||
179 | shmobile_smp_hook(cpu, 0, 0); | ||
180 | |||
181 | /* Select next sleep mode using the APMU */ | ||
182 | apmu_wrap(cpu, apmu_power_off); | ||
183 | |||
184 | /* Do ARM specific CPU shutdown */ | ||
185 | cpu_enter_lowpower_a15(); | ||
186 | |||
187 | /* jump to shared mach-shmobile sleep / reset code */ | ||
188 | shmobile_smp_sleep(); | ||
189 | } | ||
190 | |||
191 | int shmobile_smp_apmu_cpu_kill(unsigned int cpu) | ||
192 | { | ||
193 | return apmu_wrap(cpu, apmu_power_off_poll); | ||
194 | } | ||
195 | #endif | ||
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index c96f50160be6..673ad6e80869 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c | |||
@@ -7,6 +7,7 @@ | |||
7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | #include <linux/cpu.h> | ||
10 | #include <linux/delay.h> | 11 | #include <linux/delay.h> |
11 | #include <linux/init.h> | 12 | #include <linux/init.h> |
12 | #include <linux/io.h> | 13 | #include <linux/io.h> |
@@ -16,6 +17,26 @@ | |||
16 | #include <asm/smp_scu.h> | 17 | #include <asm/smp_scu.h> |
17 | #include <mach/common.h> | 18 | #include <mach/common.h> |
18 | 19 | ||
20 | static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb, | ||
21 | unsigned long action, void *hcpu) | ||
22 | { | ||
23 | unsigned int cpu = (long)hcpu; | ||
24 | |||
25 | switch (action) { | ||
26 | case CPU_UP_PREPARE: | ||
27 | /* For this particular CPU register SCU SMP boot vector */ | ||
28 | shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), | ||
29 | (unsigned long)shmobile_scu_base); | ||
30 | break; | ||
31 | }; | ||
32 | |||
33 | return NOTIFY_OK; | ||
34 | } | ||
35 | |||
36 | static struct notifier_block shmobile_smp_scu_notifier = { | ||
37 | .notifier_call = shmobile_smp_scu_notifier_call, | ||
38 | }; | ||
39 | |||
19 | void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) | 40 | void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) |
20 | { | 41 | { |
21 | /* install boot code shared by all CPUs */ | 42 | /* install boot code shared by all CPUs */ |
@@ -25,14 +46,9 @@ void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) | |||
25 | /* enable SCU and cache coherency on booting CPU */ | 46 | /* enable SCU and cache coherency on booting CPU */ |
26 | scu_enable(shmobile_scu_base); | 47 | scu_enable(shmobile_scu_base); |
27 | scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); | 48 | scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); |
28 | } | ||
29 | 49 | ||
30 | int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle) | 50 | /* Use CPU notifier for reset vector control */ |
31 | { | 51 | register_cpu_notifier(&shmobile_smp_scu_notifier); |
32 | /* For this particular CPU register SCU boot vector */ | ||
33 | shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), | ||
34 | (unsigned long)shmobile_scu_base); | ||
35 | return 0; | ||
36 | } | 52 | } |
37 | 53 | ||
38 | #ifdef CONFIG_HOTPLUG_CPU | 54 | #ifdef CONFIG_HOTPLUG_CPU |
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index d4ae616bcedb..9ebc246b8d7d 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c | |||
@@ -11,25 +11,10 @@ | |||
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/smp.h> | ||
15 | #include <asm/cacheflush.h> | 14 | #include <asm/cacheflush.h> |
16 | #include <asm/smp_plat.h> | 15 | #include <asm/smp_plat.h> |
17 | #include <mach/common.h> | 16 | #include <mach/common.h> |
18 | 17 | ||
19 | void __init shmobile_smp_init_cpus(unsigned int ncores) | ||
20 | { | ||
21 | unsigned int i; | ||
22 | |||
23 | if (ncores > nr_cpu_ids) { | ||
24 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | ||
25 | ncores, nr_cpu_ids); | ||
26 | ncores = nr_cpu_ids; | ||
27 | } | ||
28 | |||
29 | for (i = 0; i < ncores; i++) | ||
30 | set_cpu_possible(i, true); | ||
31 | } | ||
32 | |||
33 | extern unsigned long shmobile_smp_fn[]; | 18 | extern unsigned long shmobile_smp_fn[]; |
34 | extern unsigned long shmobile_smp_arg[]; | 19 | extern unsigned long shmobile_smp_arg[]; |
35 | extern unsigned long shmobile_smp_mpidr[]; | 20 | extern unsigned long shmobile_smp_mpidr[]; |
@@ -44,3 +29,10 @@ void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg) | |||
44 | shmobile_smp_arg[cpu] = arg; | 29 | shmobile_smp_arg[cpu] = arg; |
45 | flush_cache_all(); | 30 | flush_cache_all(); |
46 | } | 31 | } |
32 | |||
33 | #ifdef CONFIG_HOTPLUG_CPU | ||
34 | int shmobile_smp_cpu_disable(unsigned int cpu) | ||
35 | { | ||
36 | return 0; /* Hotplug of any CPU is supported */ | ||
37 | } | ||
38 | #endif | ||
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c new file mode 100644 index 000000000000..d4eb509a1c87 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r7s72100.c | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * r7s72100 processor support | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
5 | * Copyright (C) 2013 Magnus Damm | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/irq.h> | ||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/of_platform.h> | ||
24 | #include <linux/serial_sci.h> | ||
25 | #include <mach/common.h> | ||
26 | #include <mach/irqs.h> | ||
27 | #include <mach/r7s72100.h> | ||
28 | #include <asm/mach/arch.h> | ||
29 | |||
30 | #define SCIF_DATA(index, baseaddr, irq) \ | ||
31 | [index] = { \ | ||
32 | .type = PORT_SCIF, \ | ||
33 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ | ||
34 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | ||
35 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
36 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ | ||
37 | SCSCR_REIE, \ | ||
38 | .mapbase = baseaddr, \ | ||
39 | .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ | ||
40 | } | ||
41 | |||
42 | enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; | ||
43 | |||
44 | static const struct plat_sci_port scif[] __initconst = { | ||
45 | SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ | ||
46 | SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ | ||
47 | SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ | ||
48 | SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ | ||
49 | SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ | ||
50 | SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ | ||
51 | SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ | ||
52 | SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */ | ||
53 | }; | ||
54 | |||
55 | static inline void r7s72100_register_scif(int idx) | ||
56 | { | ||
57 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | ||
58 | sizeof(struct plat_sci_port)); | ||
59 | } | ||
60 | |||
61 | void __init r7s72100_add_dt_devices(void) | ||
62 | { | ||
63 | r7s72100_register_scif(SCIF0); | ||
64 | r7s72100_register_scif(SCIF1); | ||
65 | r7s72100_register_scif(SCIF2); | ||
66 | r7s72100_register_scif(SCIF3); | ||
67 | r7s72100_register_scif(SCIF4); | ||
68 | r7s72100_register_scif(SCIF5); | ||
69 | r7s72100_register_scif(SCIF6); | ||
70 | r7s72100_register_scif(SCIF7); | ||
71 | } | ||
72 | |||
73 | void __init r7s72100_init_early(void) | ||
74 | { | ||
75 | shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */ | ||
76 | } | ||
77 | |||
78 | #ifdef CONFIG_USE_OF | ||
79 | static const char *r7s72100_boards_compat_dt[] __initdata = { | ||
80 | "renesas,r7s72100", | ||
81 | NULL, | ||
82 | }; | ||
83 | |||
84 | DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") | ||
85 | .init_early = r7s72100_init_early, | ||
86 | .dt_compat = r7s72100_boards_compat_dt, | ||
87 | MACHINE_END | ||
88 | #endif /* CONFIG_USE_OF */ | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index 53a896275cae..b0f2749071be 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c | |||
@@ -22,8 +22,10 @@ | |||
22 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
23 | #include <linux/platform_data/irq-renesas-irqc.h> | 23 | #include <linux/platform_data/irq-renesas-irqc.h> |
24 | #include <linux/serial_sci.h> | 24 | #include <linux/serial_sci.h> |
25 | #include <linux/sh_dma.h> | ||
25 | #include <linux/sh_timer.h> | 26 | #include <linux/sh_timer.h> |
26 | #include <mach/common.h> | 27 | #include <mach/common.h> |
28 | #include <mach/dma-register.h> | ||
27 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
28 | #include <mach/r8a73a4.h> | 30 | #include <mach/r8a73a4.h> |
29 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
@@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void) | |||
199 | r8a7790_register_cmt(10); | 201 | r8a7790_register_cmt(10); |
200 | } | 202 | } |
201 | 203 | ||
204 | /* DMA */ | ||
205 | static const struct sh_dmae_slave_config dma_slaves[] = { | ||
206 | { | ||
207 | .slave_id = SHDMA_SLAVE_MMCIF0_TX, | ||
208 | .addr = 0xee200034, | ||
209 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | ||
210 | .mid_rid = 0xd1, | ||
211 | }, { | ||
212 | .slave_id = SHDMA_SLAVE_MMCIF0_RX, | ||
213 | .addr = 0xee200034, | ||
214 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | ||
215 | .mid_rid = 0xd2, | ||
216 | }, { | ||
217 | .slave_id = SHDMA_SLAVE_MMCIF1_TX, | ||
218 | .addr = 0xee220034, | ||
219 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | ||
220 | .mid_rid = 0xe1, | ||
221 | }, { | ||
222 | .slave_id = SHDMA_SLAVE_MMCIF1_RX, | ||
223 | .addr = 0xee220034, | ||
224 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | ||
225 | .mid_rid = 0xe2, | ||
226 | }, | ||
227 | }; | ||
228 | |||
229 | #define DMAE_CHANNEL(a, b) \ | ||
230 | { \ | ||
231 | .offset = (a) - 0x20, \ | ||
232 | .dmars = (a) - 0x20 + 0x40, \ | ||
233 | .chclr_bit = (b), \ | ||
234 | .chclr_offset = 0x80 - 0x20, \ | ||
235 | } | ||
236 | |||
237 | static const struct sh_dmae_channel dma_channels[] = { | ||
238 | DMAE_CHANNEL(0x8000, 0), | ||
239 | DMAE_CHANNEL(0x8080, 1), | ||
240 | DMAE_CHANNEL(0x8100, 2), | ||
241 | DMAE_CHANNEL(0x8180, 3), | ||
242 | DMAE_CHANNEL(0x8200, 4), | ||
243 | DMAE_CHANNEL(0x8280, 5), | ||
244 | DMAE_CHANNEL(0x8300, 6), | ||
245 | DMAE_CHANNEL(0x8380, 7), | ||
246 | DMAE_CHANNEL(0x8400, 8), | ||
247 | DMAE_CHANNEL(0x8480, 9), | ||
248 | DMAE_CHANNEL(0x8500, 10), | ||
249 | DMAE_CHANNEL(0x8580, 11), | ||
250 | DMAE_CHANNEL(0x8600, 12), | ||
251 | DMAE_CHANNEL(0x8680, 13), | ||
252 | DMAE_CHANNEL(0x8700, 14), | ||
253 | DMAE_CHANNEL(0x8780, 15), | ||
254 | DMAE_CHANNEL(0x8800, 16), | ||
255 | DMAE_CHANNEL(0x8880, 17), | ||
256 | DMAE_CHANNEL(0x8900, 18), | ||
257 | DMAE_CHANNEL(0x8980, 19), | ||
258 | }; | ||
259 | |||
260 | static const struct sh_dmae_pdata dma_pdata = { | ||
261 | .slave = dma_slaves, | ||
262 | .slave_num = ARRAY_SIZE(dma_slaves), | ||
263 | .channel = dma_channels, | ||
264 | .channel_num = ARRAY_SIZE(dma_channels), | ||
265 | .ts_low_shift = TS_LOW_SHIFT, | ||
266 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | ||
267 | .ts_high_shift = TS_HI_SHIFT, | ||
268 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | ||
269 | .ts_shift = dma_ts_shift, | ||
270 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | ||
271 | .dmaor_init = DMAOR_DME, | ||
272 | .chclr_present = 1, | ||
273 | .chclr_bitwise = 1, | ||
274 | }; | ||
275 | |||
276 | static struct resource dma_resources[] = { | ||
277 | DEFINE_RES_MEM(0xe6700020, 0x89e0), | ||
278 | DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), | ||
279 | { | ||
280 | /* IRQ for channels 0-19 */ | ||
281 | .start = gic_spi(200), | ||
282 | .end = gic_spi(219), | ||
283 | .flags = IORESOURCE_IRQ, | ||
284 | }, | ||
285 | }; | ||
286 | |||
287 | #define r8a73a4_register_dmac() \ | ||
288 | platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \ | ||
289 | dma_resources, ARRAY_SIZE(dma_resources), \ | ||
290 | &dma_pdata, sizeof(dma_pdata)) | ||
291 | |||
202 | void __init r8a73a4_add_standard_devices(void) | 292 | void __init r8a73a4_add_standard_devices(void) |
203 | { | 293 | { |
204 | r8a73a4_add_dt_devices(); | 294 | r8a73a4_add_dt_devices(); |
205 | r8a73a4_register_irqc(0); | 295 | r8a73a4_register_irqc(0); |
206 | r8a73a4_register_irqc(1); | 296 | r8a73a4_register_irqc(1); |
207 | r8a73a4_register_thermal(); | 297 | r8a73a4_register_thermal(); |
298 | r8a73a4_register_dmac(); | ||
208 | } | 299 | } |
209 | 300 | ||
210 | void __init r8a73a4_init_early(void) | 301 | void __init r8a73a4_init_early(void) |
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 468ee6551184..03fcc5974ef9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/irqchip/arm-gic.h> | 24 | #include <linux/irqchip/arm-gic.h> |
25 | #include <linux/of.h> | 25 | #include <linux/of.h> |
26 | #include <linux/of_platform.h> | 26 | #include <linux/of_platform.h> |
27 | #include <linux/platform_data/dma-rcar-hpbdma.h> | ||
27 | #include <linux/platform_data/gpio-rcar.h> | 28 | #include <linux/platform_data/gpio-rcar.h> |
28 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> | 29 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
29 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
@@ -95,29 +96,46 @@ static struct sh_timer_config sh_tmu1_platform_data __initdata = { | |||
95 | &sh_tmu##idx##_platform_data, \ | 96 | &sh_tmu##idx##_platform_data, \ |
96 | sizeof(sh_tmu##idx##_platform_data)) | 97 | sizeof(sh_tmu##idx##_platform_data)) |
97 | 98 | ||
98 | /* USB */ | 99 | int r8a7778_usb_phy_power(bool enable) |
99 | static struct usb_phy *phy; | 100 | { |
101 | static struct usb_phy *phy = NULL; | ||
102 | int ret = 0; | ||
103 | |||
104 | if (!phy) | ||
105 | phy = usb_get_phy(USB_PHY_TYPE_USB2); | ||
106 | |||
107 | if (IS_ERR(phy)) { | ||
108 | pr_err("kernel doesn't have usb phy driver\n"); | ||
109 | return PTR_ERR(phy); | ||
110 | } | ||
111 | |||
112 | if (enable) | ||
113 | ret = usb_phy_init(phy); | ||
114 | else | ||
115 | usb_phy_shutdown(phy); | ||
100 | 116 | ||
117 | return ret; | ||
118 | } | ||
119 | |||
120 | /* USB */ | ||
101 | static int usb_power_on(struct platform_device *pdev) | 121 | static int usb_power_on(struct platform_device *pdev) |
102 | { | 122 | { |
103 | if (IS_ERR(phy)) | 123 | int ret = r8a7778_usb_phy_power(true); |
104 | return PTR_ERR(phy); | 124 | |
125 | if (ret) | ||
126 | return ret; | ||
105 | 127 | ||
106 | pm_runtime_enable(&pdev->dev); | 128 | pm_runtime_enable(&pdev->dev); |
107 | pm_runtime_get_sync(&pdev->dev); | 129 | pm_runtime_get_sync(&pdev->dev); |
108 | 130 | ||
109 | usb_phy_init(phy); | ||
110 | |||
111 | return 0; | 131 | return 0; |
112 | } | 132 | } |
113 | 133 | ||
114 | static void usb_power_off(struct platform_device *pdev) | 134 | static void usb_power_off(struct platform_device *pdev) |
115 | { | 135 | { |
116 | if (IS_ERR(phy)) | 136 | if (r8a7778_usb_phy_power(false)) |
117 | return; | 137 | return; |
118 | 138 | ||
119 | usb_phy_shutdown(phy); | ||
120 | |||
121 | pm_runtime_put_sync(&pdev->dev); | 139 | pm_runtime_put_sync(&pdev->dev); |
122 | pm_runtime_disable(&pdev->dev); | 140 | pm_runtime_disable(&pdev->dev); |
123 | } | 141 | } |
@@ -291,6 +309,88 @@ void __init r8a7778_add_dt_devices(void) | |||
291 | r8a7778_register_tmu(1); | 309 | r8a7778_register_tmu(1); |
292 | } | 310 | } |
293 | 311 | ||
312 | /* HPB-DMA */ | ||
313 | |||
314 | /* Asynchronous mode register (ASYNCMDR) bits */ | ||
315 | #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ | ||
316 | #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ | ||
317 | #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ | ||
318 | #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ | ||
319 | #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ | ||
320 | #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ | ||
321 | |||
322 | static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { | ||
323 | { | ||
324 | .id = HPBDMA_SLAVE_SDHI0_TX, | ||
325 | .addr = 0xffe4c000 + 0x30, | ||
326 | .dcr = HPB_DMAE_DCR_SPDS_16BIT | | ||
327 | HPB_DMAE_DCR_DMDL | | ||
328 | HPB_DMAE_DCR_DPDS_16BIT, | ||
329 | .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | | ||
330 | HPB_DMAE_ASYNCRSTR_ASRST22 | | ||
331 | HPB_DMAE_ASYNCRSTR_ASRST23, | ||
332 | .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, | ||
333 | .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, | ||
334 | .port = 0x0D0C, | ||
335 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, | ||
336 | .dma_ch = 21, | ||
337 | }, { | ||
338 | .id = HPBDMA_SLAVE_SDHI0_RX, | ||
339 | .addr = 0xffe4c000 + 0x30, | ||
340 | .dcr = HPB_DMAE_DCR_SMDL | | ||
341 | HPB_DMAE_DCR_SPDS_16BIT | | ||
342 | HPB_DMAE_DCR_DPDS_16BIT, | ||
343 | .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | | ||
344 | HPB_DMAE_ASYNCRSTR_ASRST22 | | ||
345 | HPB_DMAE_ASYNCRSTR_ASRST23, | ||
346 | .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, | ||
347 | .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, | ||
348 | .port = 0x0D0C, | ||
349 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, | ||
350 | .dma_ch = 22, | ||
351 | }, | ||
352 | }; | ||
353 | |||
354 | static const struct hpb_dmae_channel hpb_dmae_channels[] = { | ||
355 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ | ||
356 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ | ||
357 | }; | ||
358 | |||
359 | static struct hpb_dmae_pdata dma_platform_data __initdata = { | ||
360 | .slaves = hpb_dmae_slaves, | ||
361 | .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), | ||
362 | .channels = hpb_dmae_channels, | ||
363 | .num_channels = ARRAY_SIZE(hpb_dmae_channels), | ||
364 | .ts_shift = { | ||
365 | [XMIT_SZ_8BIT] = 0, | ||
366 | [XMIT_SZ_16BIT] = 1, | ||
367 | [XMIT_SZ_32BIT] = 2, | ||
368 | }, | ||
369 | .num_hw_channels = 39, | ||
370 | }; | ||
371 | |||
372 | static struct resource hpb_dmae_resources[] __initdata = { | ||
373 | /* Channel registers */ | ||
374 | DEFINE_RES_MEM(0xffc08000, 0x1000), | ||
375 | /* Common registers */ | ||
376 | DEFINE_RES_MEM(0xffc09000, 0x170), | ||
377 | /* Asynchronous reset registers */ | ||
378 | DEFINE_RES_MEM(0xffc00300, 4), | ||
379 | /* Asynchronous mode registers */ | ||
380 | DEFINE_RES_MEM(0xffc00400, 4), | ||
381 | /* IRQ for DMA channels */ | ||
382 | DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), | ||
383 | }; | ||
384 | |||
385 | static void __init r8a7778_register_hpb_dmae(void) | ||
386 | { | ||
387 | platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, | ||
388 | hpb_dmae_resources, | ||
389 | ARRAY_SIZE(hpb_dmae_resources), | ||
390 | &dma_platform_data, | ||
391 | sizeof(dma_platform_data)); | ||
392 | } | ||
393 | |||
294 | void __init r8a7778_add_standard_devices(void) | 394 | void __init r8a7778_add_standard_devices(void) |
295 | { | 395 | { |
296 | r8a7778_add_dt_devices(); | 396 | r8a7778_add_dt_devices(); |
@@ -301,12 +401,12 @@ void __init r8a7778_add_standard_devices(void) | |||
301 | r8a7778_register_hspi(0); | 401 | r8a7778_register_hspi(0); |
302 | r8a7778_register_hspi(1); | 402 | r8a7778_register_hspi(1); |
303 | r8a7778_register_hspi(2); | 403 | r8a7778_register_hspi(2); |
404 | |||
405 | r8a7778_register_hpb_dmae(); | ||
304 | } | 406 | } |
305 | 407 | ||
306 | void __init r8a7778_init_late(void) | 408 | void __init r8a7778_init_late(void) |
307 | { | 409 | { |
308 | phy = usb_get_phy(USB_PHY_TYPE_USB2); | ||
309 | |||
310 | platform_device_register_full(&ehci_info); | 410 | platform_device_register_full(&ehci_info); |
311 | platform_device_register_full(&ohci_info); | 411 | platform_device_register_full(&ohci_info); |
312 | } | 412 | } |
@@ -328,7 +428,7 @@ static struct resource irqpin_resources[] __initdata = { | |||
328 | DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ | 428 | DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ |
329 | }; | 429 | }; |
330 | 430 | ||
331 | void __init r8a7778_init_irq_extpin(int irlm) | 431 | void __init r8a7778_init_irq_extpin_dt(int irlm) |
332 | { | 432 | { |
333 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); | 433 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); |
334 | unsigned long tmp; | 434 | unsigned long tmp; |
@@ -346,7 +446,11 @@ void __init r8a7778_init_irq_extpin(int irlm) | |||
346 | tmp |= (1 << 21); /* LVLMODE = 1 */ | 446 | tmp |= (1 << 21); /* LVLMODE = 1 */ |
347 | iowrite32(tmp, icr0); | 447 | iowrite32(tmp, icr0); |
348 | iounmap(icr0); | 448 | iounmap(icr0); |
449 | } | ||
349 | 450 | ||
451 | void __init r8a7778_init_irq_extpin(int irlm) | ||
452 | { | ||
453 | r8a7778_init_irq_extpin_dt(irlm); | ||
350 | if (irlm) | 454 | if (irlm) |
351 | platform_device_register_resndata( | 455 | platform_device_register_resndata( |
352 | &platform_bus, "renesas_intc_irqpin", -1, | 456 | &platform_bus, "renesas_intc_irqpin", -1, |
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index ecd0148ee1e1..13049e9d691c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/irqchip.h> | 25 | #include <linux/irqchip.h> |
26 | #include <linux/irqchip/arm-gic.h> | 26 | #include <linux/irqchip/arm-gic.h> |
27 | #include <linux/of_platform.h> | 27 | #include <linux/of_platform.h> |
28 | #include <linux/platform_data/dma-rcar-hpbdma.h> | ||
28 | #include <linux/platform_data/gpio-rcar.h> | 29 | #include <linux/platform_data/gpio-rcar.h> |
29 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> | 30 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
30 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
@@ -97,7 +98,7 @@ static struct resource irqpin0_resources[] __initdata = { | |||
97 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ | 98 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ |
98 | }; | 99 | }; |
99 | 100 | ||
100 | void __init r8a7779_init_irq_extpin(int irlm) | 101 | void __init r8a7779_init_irq_extpin_dt(int irlm) |
101 | { | 102 | { |
102 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); | 103 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); |
103 | u32 tmp; | 104 | u32 tmp; |
@@ -115,7 +116,11 @@ void __init r8a7779_init_irq_extpin(int irlm) | |||
115 | tmp |= (1 << 21); /* LVLMODE = 1 */ | 116 | tmp |= (1 << 21); /* LVLMODE = 1 */ |
116 | iowrite32(tmp, icr0); | 117 | iowrite32(tmp, icr0); |
117 | iounmap(icr0); | 118 | iounmap(icr0); |
119 | } | ||
118 | 120 | ||
121 | void __init r8a7779_init_irq_extpin(int irlm) | ||
122 | { | ||
123 | r8a7779_init_irq_extpin_dt(irlm); | ||
119 | if (irlm) | 124 | if (irlm) |
120 | platform_device_register_resndata( | 125 | platform_device_register_resndata( |
121 | &platform_bus, "renesas_intc_irqpin", -1, | 126 | &platform_bus, "renesas_intc_irqpin", -1, |
@@ -632,6 +637,158 @@ static struct platform_device_info *vin_info_table[] __initdata = { | |||
632 | &vin3_info, | 637 | &vin3_info, |
633 | }; | 638 | }; |
634 | 639 | ||
640 | /* HPB-DMA */ | ||
641 | |||
642 | /* Asynchronous mode register bits */ | ||
643 | #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ | ||
644 | #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ | ||
645 | #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ | ||
646 | #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ | ||
647 | #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ | ||
648 | #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ | ||
649 | #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ | ||
650 | #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ | ||
651 | #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ | ||
652 | #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ | ||
653 | #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ | ||
654 | #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ | ||
655 | #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ | ||
656 | #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ | ||
657 | #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ | ||
658 | #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ | ||
659 | #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ | ||
660 | #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ | ||
661 | #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ | ||
662 | #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ | ||
663 | #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ | ||
664 | #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ | ||
665 | #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ | ||
666 | #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ | ||
667 | #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ | ||
668 | #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ | ||
669 | #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ | ||
670 | #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ | ||
671 | #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ | ||
672 | #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ | ||
673 | #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ | ||
674 | #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ | ||
675 | #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ | ||
676 | #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ | ||
677 | #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ | ||
678 | #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ | ||
679 | #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ | ||
680 | #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ | ||
681 | #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ | ||
682 | #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ | ||
683 | #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ | ||
684 | #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ | ||
685 | #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ | ||
686 | #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ | ||
687 | #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ | ||
688 | #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ | ||
689 | #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ | ||
690 | #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ | ||
691 | #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ | ||
692 | #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ | ||
693 | #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ | ||
694 | #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ | ||
695 | #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ | ||
696 | #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ | ||
697 | #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ | ||
698 | #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ | ||
699 | #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ | ||
700 | #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ | ||
701 | #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ | ||
702 | #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ | ||
703 | #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ | ||
704 | #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ | ||
705 | #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ | ||
706 | #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ | ||
707 | #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ | ||
708 | #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ | ||
709 | #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ | ||
710 | #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ | ||
711 | #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ | ||
712 | #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ | ||
713 | #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ | ||
714 | #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ | ||
715 | |||
716 | static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { | ||
717 | { | ||
718 | .id = HPBDMA_SLAVE_SDHI0_TX, | ||
719 | .addr = 0xffe4c000 + 0x30, | ||
720 | .dcr = HPB_DMAE_DCR_SPDS_16BIT | | ||
721 | HPB_DMAE_DCR_DMDL | | ||
722 | HPB_DMAE_DCR_DPDS_16BIT, | ||
723 | .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | | ||
724 | HPB_DMAE_ASYNCRSTR_ASRST22 | | ||
725 | HPB_DMAE_ASYNCRSTR_ASRST23, | ||
726 | .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | | ||
727 | HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, | ||
728 | .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | | ||
729 | HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, | ||
730 | .port = 0x0D0C, | ||
731 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, | ||
732 | .dma_ch = 21, | ||
733 | }, { | ||
734 | .id = HPBDMA_SLAVE_SDHI0_RX, | ||
735 | .addr = 0xffe4c000 + 0x30, | ||
736 | .dcr = HPB_DMAE_DCR_SMDL | | ||
737 | HPB_DMAE_DCR_SPDS_16BIT | | ||
738 | HPB_DMAE_DCR_DPDS_16BIT, | ||
739 | .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | | ||
740 | HPB_DMAE_ASYNCRSTR_ASRST22 | | ||
741 | HPB_DMAE_ASYNCRSTR_ASRST23, | ||
742 | .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | | ||
743 | HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, | ||
744 | .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | | ||
745 | HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, | ||
746 | .port = 0x0D0C, | ||
747 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, | ||
748 | .dma_ch = 22, | ||
749 | }, | ||
750 | }; | ||
751 | |||
752 | static const struct hpb_dmae_channel hpb_dmae_channels[] = { | ||
753 | HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ | ||
754 | HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ | ||
755 | }; | ||
756 | |||
757 | static struct hpb_dmae_pdata dma_platform_data __initdata = { | ||
758 | .slaves = hpb_dmae_slaves, | ||
759 | .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), | ||
760 | .channels = hpb_dmae_channels, | ||
761 | .num_channels = ARRAY_SIZE(hpb_dmae_channels), | ||
762 | .ts_shift = { | ||
763 | [XMIT_SZ_8BIT] = 0, | ||
764 | [XMIT_SZ_16BIT] = 1, | ||
765 | [XMIT_SZ_32BIT] = 2, | ||
766 | }, | ||
767 | .num_hw_channels = 44, | ||
768 | }; | ||
769 | |||
770 | static struct resource hpb_dmae_resources[] __initdata = { | ||
771 | /* Channel registers */ | ||
772 | DEFINE_RES_MEM(0xffc08000, 0x1000), | ||
773 | /* Common registers */ | ||
774 | DEFINE_RES_MEM(0xffc09000, 0x170), | ||
775 | /* Asynchronous reset registers */ | ||
776 | DEFINE_RES_MEM(0xffc00300, 4), | ||
777 | /* Asynchronous mode registers */ | ||
778 | DEFINE_RES_MEM(0xffc00400, 4), | ||
779 | /* IRQ for DMA channels */ | ||
780 | DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), | ||
781 | }; | ||
782 | |||
783 | static void __init r8a7779_register_hpb_dmae(void) | ||
784 | { | ||
785 | platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, | ||
786 | hpb_dmae_resources, | ||
787 | ARRAY_SIZE(hpb_dmae_resources), | ||
788 | &dma_platform_data, | ||
789 | sizeof(dma_platform_data)); | ||
790 | } | ||
791 | |||
635 | static struct platform_device *r8a7779_devices_dt[] __initdata = { | 792 | static struct platform_device *r8a7779_devices_dt[] __initdata = { |
636 | &scif0_device, | 793 | &scif0_device, |
637 | &scif1_device, | 794 | &scif1_device, |
@@ -665,6 +822,7 @@ void __init r8a7779_add_standard_devices(void) | |||
665 | ARRAY_SIZE(r8a7779_devices_dt)); | 822 | ARRAY_SIZE(r8a7779_devices_dt)); |
666 | platform_add_devices(r8a7779_standard_devices, | 823 | platform_add_devices(r8a7779_standard_devices, |
667 | ARRAY_SIZE(r8a7779_standard_devices)); | 824 | ARRAY_SIZE(r8a7779_standard_devices)); |
825 | r8a7779_register_hpb_dmae(); | ||
668 | } | 826 | } |
669 | 827 | ||
670 | void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) | 828 | void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) |
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index e0d29a265c2d..c47bcebbcb00 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c | |||
@@ -18,7 +18,6 @@ | |||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/clocksource.h> | ||
22 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
23 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
24 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
@@ -203,71 +202,6 @@ void __init r8a7790_add_standard_devices(void) | |||
203 | r8a7790_register_thermal(); | 202 | r8a7790_register_thermal(); |
204 | } | 203 | } |
205 | 204 | ||
206 | #define MODEMR 0xe6160060 | ||
207 | |||
208 | u32 __init r8a7790_read_mode_pins(void) | ||
209 | { | ||
210 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); | ||
211 | u32 mode; | ||
212 | |||
213 | BUG_ON(!modemr); | ||
214 | mode = ioread32(modemr); | ||
215 | iounmap(modemr); | ||
216 | |||
217 | return mode; | ||
218 | } | ||
219 | |||
220 | #define CNTCR 0 | ||
221 | #define CNTFID0 0x20 | ||
222 | |||
223 | void __init r8a7790_timer_init(void) | ||
224 | { | ||
225 | #ifdef CONFIG_ARM_ARCH_TIMER | ||
226 | u32 mode = r8a7790_read_mode_pins(); | ||
227 | void __iomem *base; | ||
228 | int extal_mhz = 0; | ||
229 | u32 freq; | ||
230 | |||
231 | /* At Linux boot time the r8a7790 arch timer comes up | ||
232 | * with the counter disabled. Moreover, it may also report | ||
233 | * a potentially incorrect fixed 13 MHz frequency. To be | ||
234 | * correct these registers need to be updated to use the | ||
235 | * frequency EXTAL / 2 which can be determined by the MD pins. | ||
236 | */ | ||
237 | |||
238 | switch (mode & (MD(14) | MD(13))) { | ||
239 | case 0: | ||
240 | extal_mhz = 15; | ||
241 | break; | ||
242 | case MD(13): | ||
243 | extal_mhz = 20; | ||
244 | break; | ||
245 | case MD(14): | ||
246 | extal_mhz = 26; | ||
247 | break; | ||
248 | case MD(13) | MD(14): | ||
249 | extal_mhz = 30; | ||
250 | break; | ||
251 | } | ||
252 | |||
253 | /* The arch timer frequency equals EXTAL / 2 */ | ||
254 | freq = extal_mhz * (1000000 / 2); | ||
255 | |||
256 | /* Remap "armgcnt address map" space */ | ||
257 | base = ioremap(0xe6080000, PAGE_SIZE); | ||
258 | |||
259 | /* Update registers with correct frequency */ | ||
260 | iowrite32(freq, base + CNTFID0); | ||
261 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | ||
262 | |||
263 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
264 | iowrite32(1, base + CNTCR); | ||
265 | iounmap(base); | ||
266 | #endif /* CONFIG_ARM_ARCH_TIMER */ | ||
267 | |||
268 | clocksource_of_init(); | ||
269 | } | ||
270 | |||
271 | void __init r8a7790_init_early(void) | 205 | void __init r8a7790_init_early(void) |
272 | { | 206 | { |
273 | #ifndef CONFIG_ARM_ARCH_TIMER | 207 | #ifndef CONFIG_ARM_ARCH_TIMER |
@@ -283,8 +217,9 @@ static const char * const r8a7790_boards_compat_dt[] __initconst = { | |||
283 | }; | 217 | }; |
284 | 218 | ||
285 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") | 219 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") |
220 | .smp = smp_ops(r8a7790_smp_ops), | ||
286 | .init_early = r8a7790_init_early, | 221 | .init_early = r8a7790_init_early, |
287 | .init_time = r8a7790_timer_init, | 222 | .init_time = rcar_gen2_timer_init, |
288 | .dt_compat = r8a7790_boards_compat_dt, | 223 | .dt_compat = r8a7790_boards_compat_dt, |
289 | MACHINE_END | 224 | MACHINE_END |
290 | #endif /* CONFIG_USE_OF */ | 225 | #endif /* CONFIG_USE_OF */ |
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c new file mode 100644 index 000000000000..d9393d61ee27 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-r8a7791.c | |||
@@ -0,0 +1,184 @@ | |||
1 | /* | ||
2 | * r8a7791 processor support | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Electronics Corporation | ||
5 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
6 | * Copyright (C) 2013 Magnus Damm | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; version 2 of the License. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
20 | */ | ||
21 | |||
22 | #include <linux/irq.h> | ||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/of_platform.h> | ||
25 | #include <linux/platform_data/irq-renesas-irqc.h> | ||
26 | #include <linux/serial_sci.h> | ||
27 | #include <linux/sh_timer.h> | ||
28 | #include <mach/common.h> | ||
29 | #include <mach/irqs.h> | ||
30 | #include <mach/r8a7791.h> | ||
31 | #include <mach/rcar-gen2.h> | ||
32 | #include <asm/mach/arch.h> | ||
33 | |||
34 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | ||
35 | .type = scif_type, \ | ||
36 | .mapbase = baseaddr, \ | ||
37 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | ||
38 | .irqs = SCIx_IRQ_MUXED(irq) | ||
39 | |||
40 | #define SCIFA_DATA(index, baseaddr, irq) \ | ||
41 | [index] = { \ | ||
42 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | ||
43 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
44 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
45 | } | ||
46 | |||
47 | #define SCIFB_DATA(index, baseaddr, irq) \ | ||
48 | [index] = { \ | ||
49 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | ||
50 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
51 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
52 | } | ||
53 | |||
54 | #define SCIF_DATA(index, baseaddr, irq) \ | ||
55 | [index] = { \ | ||
56 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | ||
57 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
58 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
59 | } | ||
60 | |||
61 | #define HSCIF_DATA(index, baseaddr, irq) \ | ||
62 | [index] = { \ | ||
63 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | ||
64 | .scbrr_algo_id = SCBRR_ALGO_6, \ | ||
65 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
66 | } | ||
67 | |||
68 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | ||
69 | SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; | ||
70 | |||
71 | static const struct plat_sci_port scif[] __initconst = { | ||
72 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | ||
73 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | ||
74 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | ||
75 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | ||
76 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | ||
77 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | ||
78 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | ||
79 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | ||
80 | SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ | ||
81 | SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ | ||
82 | SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ | ||
83 | SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ | ||
84 | SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ | ||
85 | SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ | ||
86 | SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ | ||
87 | }; | ||
88 | |||
89 | static inline void r8a7791_register_scif(int idx) | ||
90 | { | ||
91 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | ||
92 | sizeof(struct plat_sci_port)); | ||
93 | } | ||
94 | |||
95 | static const struct sh_timer_config cmt00_platform_data __initconst = { | ||
96 | .name = "CMT00", | ||
97 | .timer_bit = 0, | ||
98 | .clockevent_rating = 80, | ||
99 | }; | ||
100 | |||
101 | static const struct resource cmt00_resources[] __initconst = { | ||
102 | DEFINE_RES_MEM(0xffca0510, 0x0c), | ||
103 | DEFINE_RES_MEM(0xffca0500, 0x04), | ||
104 | DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ | ||
105 | }; | ||
106 | |||
107 | #define r8a7791_register_cmt(idx) \ | ||
108 | platform_device_register_resndata(&platform_bus, "sh_cmt", \ | ||
109 | idx, cmt##idx##_resources, \ | ||
110 | ARRAY_SIZE(cmt##idx##_resources), \ | ||
111 | &cmt##idx##_platform_data, \ | ||
112 | sizeof(struct sh_timer_config)) | ||
113 | |||
114 | static struct renesas_irqc_config irqc0_data = { | ||
115 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */ | ||
116 | }; | ||
117 | |||
118 | static struct resource irqc0_resources[] = { | ||
119 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ | ||
120 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ | ||
121 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ | ||
122 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ | ||
123 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ | ||
124 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */ | ||
125 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */ | ||
126 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */ | ||
127 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */ | ||
128 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */ | ||
129 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */ | ||
130 | }; | ||
131 | |||
132 | #define r8a7791_register_irqc(idx) \ | ||
133 | platform_device_register_resndata(&platform_bus, "renesas_irqc", \ | ||
134 | idx, irqc##idx##_resources, \ | ||
135 | ARRAY_SIZE(irqc##idx##_resources), \ | ||
136 | &irqc##idx##_data, \ | ||
137 | sizeof(struct renesas_irqc_config)) | ||
138 | |||
139 | void __init r8a7791_add_dt_devices(void) | ||
140 | { | ||
141 | r8a7791_register_scif(SCIFA0); | ||
142 | r8a7791_register_scif(SCIFA1); | ||
143 | r8a7791_register_scif(SCIFB0); | ||
144 | r8a7791_register_scif(SCIFB1); | ||
145 | r8a7791_register_scif(SCIFB2); | ||
146 | r8a7791_register_scif(SCIFA2); | ||
147 | r8a7791_register_scif(SCIF0); | ||
148 | r8a7791_register_scif(SCIF1); | ||
149 | r8a7791_register_scif(SCIF2); | ||
150 | r8a7791_register_scif(SCIF3); | ||
151 | r8a7791_register_scif(SCIF4); | ||
152 | r8a7791_register_scif(SCIF5); | ||
153 | r8a7791_register_scif(SCIFA3); | ||
154 | r8a7791_register_scif(SCIFA4); | ||
155 | r8a7791_register_scif(SCIFA5); | ||
156 | r8a7791_register_cmt(00); | ||
157 | } | ||
158 | |||
159 | void __init r8a7791_add_standard_devices(void) | ||
160 | { | ||
161 | r8a7791_add_dt_devices(); | ||
162 | r8a7791_register_irqc(0); | ||
163 | } | ||
164 | |||
165 | void __init r8a7791_init_early(void) | ||
166 | { | ||
167 | #ifndef CONFIG_ARM_ARCH_TIMER | ||
168 | shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ | ||
169 | #endif | ||
170 | } | ||
171 | |||
172 | #ifdef CONFIG_USE_OF | ||
173 | static const char *r8a7791_boards_compat_dt[] __initdata = { | ||
174 | "renesas,r8a7791", | ||
175 | NULL, | ||
176 | }; | ||
177 | |||
178 | DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)") | ||
179 | .smp = smp_ops(r8a7791_smp_ops), | ||
180 | .init_early = r8a7791_init_early, | ||
181 | .init_time = rcar_gen2_timer_init, | ||
182 | .dt_compat = r8a7791_boards_compat_dt, | ||
183 | MACHINE_END | ||
184 | #endif /* CONFIG_USE_OF */ | ||
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c new file mode 100644 index 000000000000..5734c24bf6c7 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * R-Car Generation 2 support | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
5 | * Copyright (C) 2013 Magnus Damm | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/clocksource.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/kernel.h> | ||
24 | #include <mach/common.h> | ||
25 | #include <mach/rcar-gen2.h> | ||
26 | #include <asm/mach/arch.h> | ||
27 | |||
28 | #define MODEMR 0xe6160060 | ||
29 | |||
30 | u32 __init rcar_gen2_read_mode_pins(void) | ||
31 | { | ||
32 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); | ||
33 | u32 mode; | ||
34 | |||
35 | BUG_ON(!modemr); | ||
36 | mode = ioread32(modemr); | ||
37 | iounmap(modemr); | ||
38 | |||
39 | return mode; | ||
40 | } | ||
41 | |||
42 | #define CNTCR 0 | ||
43 | #define CNTFID0 0x20 | ||
44 | |||
45 | void __init rcar_gen2_timer_init(void) | ||
46 | { | ||
47 | #ifdef CONFIG_ARM_ARCH_TIMER | ||
48 | u32 mode = rcar_gen2_read_mode_pins(); | ||
49 | void __iomem *base; | ||
50 | int extal_mhz = 0; | ||
51 | u32 freq; | ||
52 | |||
53 | /* At Linux boot time the r8a7790 arch timer comes up | ||
54 | * with the counter disabled. Moreover, it may also report | ||
55 | * a potentially incorrect fixed 13 MHz frequency. To be | ||
56 | * correct these registers need to be updated to use the | ||
57 | * frequency EXTAL / 2 which can be determined by the MD pins. | ||
58 | */ | ||
59 | |||
60 | switch (mode & (MD(14) | MD(13))) { | ||
61 | case 0: | ||
62 | extal_mhz = 15; | ||
63 | break; | ||
64 | case MD(13): | ||
65 | extal_mhz = 20; | ||
66 | break; | ||
67 | case MD(14): | ||
68 | extal_mhz = 26; | ||
69 | break; | ||
70 | case MD(13) | MD(14): | ||
71 | extal_mhz = 30; | ||
72 | break; | ||
73 | } | ||
74 | |||
75 | /* The arch timer frequency equals EXTAL / 2 */ | ||
76 | freq = extal_mhz * (1000000 / 2); | ||
77 | |||
78 | /* Remap "armgcnt address map" space */ | ||
79 | base = ioremap(0xe6080000, PAGE_SIZE); | ||
80 | |||
81 | /* Update registers with correct frequency */ | ||
82 | iowrite32(freq, base + CNTFID0); | ||
83 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | ||
84 | |||
85 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
86 | iowrite32(1, base + CNTCR); | ||
87 | iounmap(base); | ||
88 | #endif /* CONFIG_ARM_ARCH_TIMER */ | ||
89 | |||
90 | clocksource_of_init(); | ||
91 | } | ||
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 522de5ebb55f..f2ca92308f75 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c | |||
@@ -34,12 +34,6 @@ | |||
34 | 34 | ||
35 | static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) | 35 | static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) |
36 | { | 36 | { |
37 | int ret; | ||
38 | |||
39 | ret = shmobile_smp_scu_boot_secondary(cpu, idle); | ||
40 | if (ret) | ||
41 | return ret; | ||
42 | |||
43 | arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); | 37 | arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); |
44 | return 0; | 38 | return 0; |
45 | } | 39 | } |
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 0f05e9fb722f..627c1f0d9478 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c | |||
@@ -87,10 +87,6 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
87 | unsigned int lcpu = cpu_logical_map(cpu); | 87 | unsigned int lcpu = cpu_logical_map(cpu); |
88 | int ret; | 88 | int ret; |
89 | 89 | ||
90 | ret = shmobile_smp_scu_boot_secondary(cpu, idle); | ||
91 | if (ret) | ||
92 | return ret; | ||
93 | |||
94 | if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu)) | 90 | if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu)) |
95 | ch = r8a7779_ch_cpu[lcpu]; | 91 | ch = r8a7779_ch_cpu[lcpu]; |
96 | 92 | ||
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c new file mode 100644 index 000000000000..015e2753de1f --- /dev/null +++ b/arch/arm/mach-shmobile/smp-r8a7790.c | |||
@@ -0,0 +1,67 @@ | |||
1 | /* | ||
2 | * SMP support for r8a7790 | ||
3 | * | ||
4 | * Copyright (C) 2012-2013 Renesas Solutions Corp. | ||
5 | * Copyright (C) 2012 Takashi Yoshii <takashi.yoshii.ze@renesas.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/smp.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <asm/smp_plat.h> | ||
21 | #include <mach/common.h> | ||
22 | |||
23 | #define RST 0xe6160000 | ||
24 | #define CA15BAR 0x0020 | ||
25 | #define CA7BAR 0x0030 | ||
26 | #define CA15RESCNT 0x0040 | ||
27 | #define CA7RESCNT 0x0044 | ||
28 | #define MERAM 0xe8080000 | ||
29 | |||
30 | static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus) | ||
31 | { | ||
32 | void __iomem *p; | ||
33 | u32 bar; | ||
34 | |||
35 | /* let APMU code install data related to shmobile_boot_vector */ | ||
36 | shmobile_smp_apmu_prepare_cpus(max_cpus); | ||
37 | |||
38 | /* MERAM for jump stub, because BAR requires 256KB aligned address */ | ||
39 | p = ioremap_nocache(MERAM, shmobile_boot_size); | ||
40 | memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); | ||
41 | iounmap(p); | ||
42 | |||
43 | /* setup reset vectors */ | ||
44 | p = ioremap_nocache(RST, 0x63); | ||
45 | bar = (MERAM >> 8) & 0xfffffc00; | ||
46 | writel_relaxed(bar, p + CA15BAR); | ||
47 | writel_relaxed(bar, p + CA7BAR); | ||
48 | writel_relaxed(bar | 0x10, p + CA15BAR); | ||
49 | writel_relaxed(bar | 0x10, p + CA7BAR); | ||
50 | |||
51 | /* enable clocks to all CPUs */ | ||
52 | writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000, | ||
53 | p + CA15RESCNT); | ||
54 | writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000, | ||
55 | p + CA7RESCNT); | ||
56 | iounmap(p); | ||
57 | } | ||
58 | |||
59 | struct smp_operations r8a7790_smp_ops __initdata = { | ||
60 | .smp_prepare_cpus = r8a7790_smp_prepare_cpus, | ||
61 | .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, | ||
62 | #ifdef CONFIG_HOTPLUG_CPU | ||
63 | .cpu_disable = shmobile_smp_cpu_disable, | ||
64 | .cpu_die = shmobile_smp_apmu_cpu_die, | ||
65 | .cpu_kill = shmobile_smp_apmu_cpu_kill, | ||
66 | #endif | ||
67 | }; | ||
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c new file mode 100644 index 000000000000..2df5bd190fe4 --- /dev/null +++ b/arch/arm/mach-shmobile/smp-r8a7791.c | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * SMP support for r8a7791 | ||
3 | * | ||
4 | * Copyright (C) 2013 Renesas Solutions Corp. | ||
5 | * Copyright (C) 2013 Magnus Damm | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/smp.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <asm/smp_plat.h> | ||
21 | #include <mach/common.h> | ||
22 | #include <mach/r8a7791.h> | ||
23 | |||
24 | #define RST 0xe6160000 | ||
25 | #define CA15BAR 0x0020 | ||
26 | #define CA15RESCNT 0x0040 | ||
27 | #define RAM 0xe6300000 | ||
28 | |||
29 | static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) | ||
30 | { | ||
31 | void __iomem *p; | ||
32 | u32 bar; | ||
33 | |||
34 | /* let APMU code install data related to shmobile_boot_vector */ | ||
35 | shmobile_smp_apmu_prepare_cpus(max_cpus); | ||
36 | |||
37 | /* RAM for jump stub, because BAR requires 256KB aligned address */ | ||
38 | p = ioremap_nocache(RAM, shmobile_boot_size); | ||
39 | memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); | ||
40 | iounmap(p); | ||
41 | |||
42 | /* setup reset vectors */ | ||
43 | p = ioremap_nocache(RST, 0x63); | ||
44 | bar = (RAM >> 8) & 0xfffffc00; | ||
45 | writel_relaxed(bar, p + CA15BAR); | ||
46 | writel_relaxed(bar | 0x10, p + CA15BAR); | ||
47 | |||
48 | /* enable clocks to all CPUs */ | ||
49 | writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000, | ||
50 | p + CA15RESCNT); | ||
51 | iounmap(p); | ||
52 | } | ||
53 | |||
54 | struct smp_operations r8a7791_smp_ops __initdata = { | ||
55 | .smp_prepare_cpus = r8a7791_smp_prepare_cpus, | ||
56 | .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, | ||
57 | #ifdef CONFIG_HOTPLUG_CPU | ||
58 | .cpu_disable = shmobile_smp_cpu_disable, | ||
59 | .cpu_die = shmobile_smp_apmu_cpu_die, | ||
60 | .cpu_kill = shmobile_smp_apmu_cpu_kill, | ||
61 | #endif | ||
62 | }; | ||
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 0baa24443793..13ba36a6831f 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
@@ -46,11 +46,6 @@ void __init sh73a0_register_twd(void) | |||
46 | static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) | 46 | static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) |
47 | { | 47 | { |
48 | unsigned int lcpu = cpu_logical_map(cpu); | 48 | unsigned int lcpu = cpu_logical_map(cpu); |
49 | int ret; | ||
50 | |||
51 | ret = shmobile_smp_scu_boot_secondary(cpu, idle); | ||
52 | if (ret) | ||
53 | return ret; | ||
54 | 49 | ||
55 | if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) | 50 | if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) |
56 | __raw_writel(1 << lcpu, WUPCR); /* wake up */ | 51 | __raw_writel(1 << lcpu, WUPCR); /* wake up */ |
@@ -71,18 +66,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) | |||
71 | shmobile_smp_scu_prepare_cpus(max_cpus); | 66 | shmobile_smp_scu_prepare_cpus(max_cpus); |
72 | } | 67 | } |
73 | 68 | ||
74 | #ifdef CONFIG_HOTPLUG_CPU | ||
75 | static int sh73a0_cpu_disable(unsigned int cpu) | ||
76 | { | ||
77 | return 0; /* CPU0 and CPU1 supported */ | ||
78 | } | ||
79 | #endif /* CONFIG_HOTPLUG_CPU */ | ||
80 | |||
81 | struct smp_operations sh73a0_smp_ops __initdata = { | 69 | struct smp_operations sh73a0_smp_ops __initdata = { |
82 | .smp_prepare_cpus = sh73a0_smp_prepare_cpus, | 70 | .smp_prepare_cpus = sh73a0_smp_prepare_cpus, |
83 | .smp_boot_secondary = sh73a0_boot_secondary, | 71 | .smp_boot_secondary = sh73a0_boot_secondary, |
84 | #ifdef CONFIG_HOTPLUG_CPU | 72 | #ifdef CONFIG_HOTPLUG_CPU |
85 | .cpu_disable = sh73a0_cpu_disable, | 73 | .cpu_disable = shmobile_smp_cpu_disable, |
86 | .cpu_die = shmobile_smp_scu_cpu_die, | 74 | .cpu_die = shmobile_smp_scu_cpu_die, |
87 | .cpu_kill = shmobile_smp_scu_cpu_kill, | 75 | .cpu_kill = shmobile_smp_scu_cpu_kill, |
88 | #endif | 76 | #endif |
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3ab2f65f8a50..c9e72c89066a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig | |||
@@ -1,14 +1,14 @@ | |||
1 | config ARCH_SUNXI | 1 | config ARCH_SUNXI |
2 | bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 | 2 | bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 |
3 | select ARCH_REQUIRE_GPIOLIB | 3 | select ARCH_REQUIRE_GPIOLIB |
4 | select ARM_GIC | ||
4 | select CLKSRC_MMIO | 5 | select CLKSRC_MMIO |
5 | select CLKSRC_OF | 6 | select CLKSRC_OF |
6 | select COMMON_CLK | 7 | select COMMON_CLK |
7 | select GENERIC_CLOCKEVENTS | 8 | select GENERIC_CLOCKEVENTS |
8 | select GENERIC_IRQ_CHIP | 9 | select GENERIC_IRQ_CHIP |
10 | select HAVE_SMP | ||
9 | select PINCTRL | 11 | select PINCTRL |
12 | select PINCTRL_SUNXI | ||
10 | select SPARSE_IRQ | 13 | select SPARSE_IRQ |
11 | select SUN4I_TIMER | 14 | select SUN4I_TIMER |
12 | select PINCTRL_SUNXI | ||
13 | select ARM_GIC | ||
14 | select HAVE_SMP | ||
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 90dda6228510..61d3a387f01c 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c | |||
@@ -90,14 +90,13 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd) | |||
90 | } | 90 | } |
91 | 91 | ||
92 | static struct of_device_id sunxi_restart_ids[] = { | 92 | static struct of_device_id sunxi_restart_ids[] = { |
93 | { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, | 93 | { .compatible = "allwinner,sun4i-wdt" }, |
94 | { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart }, | 94 | { .compatible = "allwinner,sun6i-wdt" }, |
95 | { /*sentinel*/ } | 95 | { /*sentinel*/ } |
96 | }; | 96 | }; |
97 | 97 | ||
98 | static void sunxi_setup_restart(void) | 98 | static void sunxi_setup_restart(void) |
99 | { | 99 | { |
100 | const struct of_device_id *of_id; | ||
101 | struct device_node *np; | 100 | struct device_node *np; |
102 | 101 | ||
103 | np = of_find_matching_node(NULL, sunxi_restart_ids); | 102 | np = of_find_matching_node(NULL, sunxi_restart_ids); |
@@ -106,11 +105,6 @@ static void sunxi_setup_restart(void) | |||
106 | 105 | ||
107 | wdt_base = of_iomap(np, 0); | 106 | wdt_base = of_iomap(np, 0); |
108 | WARN(!wdt_base, "failed to map watchdog base address"); | 107 | WARN(!wdt_base, "failed to map watchdog base address"); |
109 | |||
110 | of_id = of_match_node(sunxi_restart_ids, np); | ||
111 | WARN(!of_id, "restart function not available"); | ||
112 | |||
113 | arm_pm_restart = of_id->data; | ||
114 | } | 108 | } |
115 | 109 | ||
116 | static void __init sunxi_dt_init(void) | 110 | static void __init sunxi_dt_init(void) |
@@ -124,12 +118,33 @@ static const char * const sunxi_board_dt_compat[] = { | |||
124 | "allwinner,sun4i-a10", | 118 | "allwinner,sun4i-a10", |
125 | "allwinner,sun5i-a10s", | 119 | "allwinner,sun5i-a10s", |
126 | "allwinner,sun5i-a13", | 120 | "allwinner,sun5i-a13", |
127 | "allwinner,sun6i-a31", | ||
128 | "allwinner,sun7i-a20", | ||
129 | NULL, | 121 | NULL, |
130 | }; | 122 | }; |
131 | 123 | ||
132 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") | 124 | DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") |
133 | .init_machine = sunxi_dt_init, | 125 | .init_machine = sunxi_dt_init, |
134 | .dt_compat = sunxi_board_dt_compat, | 126 | .dt_compat = sunxi_board_dt_compat, |
127 | .restart = sun4i_restart, | ||
128 | MACHINE_END | ||
129 | |||
130 | static const char * const sun6i_board_dt_compat[] = { | ||
131 | "allwinner,sun6i-a31", | ||
132 | NULL, | ||
133 | }; | ||
134 | |||
135 | DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") | ||
136 | .init_machine = sunxi_dt_init, | ||
137 | .dt_compat = sun6i_board_dt_compat, | ||
138 | .restart = sun6i_restart, | ||
139 | MACHINE_END | ||
140 | |||
141 | static const char * const sun7i_board_dt_compat[] = { | ||
142 | "allwinner,sun7i-a20", | ||
143 | NULL, | ||
144 | }; | ||
145 | |||
146 | DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") | ||
147 | .init_machine = sunxi_dt_init, | ||
148 | .dt_compat = sun7i_board_dt_compat, | ||
149 | .restart = sun4i_restart, | ||
135 | MACHINE_END | 150 | MACHINE_END |
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 56bb6c35d958..0bf04a0bca9d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
@@ -59,6 +59,14 @@ config ARCH_TEGRA_114_SOC | |||
59 | Support for NVIDIA Tegra T114 processor family, based on the | 59 | Support for NVIDIA Tegra T114 processor family, based on the |
60 | ARM CortexA15MP CPU | 60 | ARM CortexA15MP CPU |
61 | 61 | ||
62 | config ARCH_TEGRA_124_SOC | ||
63 | bool "Enable support for Tegra124 family" | ||
64 | select ARM_L1_CACHE_SHIFT_6 | ||
65 | select HAVE_ARM_ARCH_TIMER | ||
66 | help | ||
67 | Support for NVIDIA Tegra T124 processor family, based on the | ||
68 | ARM CortexA15MP CPU | ||
69 | |||
62 | config TEGRA_AHB | 70 | config TEGRA_AHB |
63 | bool "Enable AHB driver for NVIDIA Tegra SoCs" | 71 | bool "Enable AHB driver for NVIDIA Tegra SoCs" |
64 | default y | 72 | default y |
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 97eb48e977e5..019bb1758662 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
@@ -35,5 +35,10 @@ obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o | |||
35 | ifeq ($(CONFIG_CPU_IDLE),y) | 35 | ifeq ($(CONFIG_CPU_IDLE),y) |
36 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o | 36 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o |
37 | endif | 37 | endif |
38 | obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o | ||
39 | obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o | ||
40 | ifeq ($(CONFIG_CPU_IDLE),y) | ||
41 | obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o | ||
42 | endif | ||
38 | 43 | ||
39 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o | 44 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o |
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 0961dfcf83a4..7bc5d8d667fe 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c | |||
@@ -39,7 +39,9 @@ void __init tegra_cpuidle_init(void) | |||
39 | tegra30_cpuidle_init(); | 39 | tegra30_cpuidle_init(); |
40 | break; | 40 | break; |
41 | case TEGRA114: | 41 | case TEGRA114: |
42 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | 42 | case TEGRA124: |
43 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || | ||
44 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | ||
43 | tegra114_cpuidle_init(); | 45 | tegra114_cpuidle_init(); |
44 | break; | 46 | break; |
45 | } | 47 | } |
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index 5348543382bf..ce8ab8abf061 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c | |||
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) | |||
87 | break; | 87 | break; |
88 | case TEGRA30: | 88 | case TEGRA30: |
89 | case TEGRA114: | 89 | case TEGRA114: |
90 | case TEGRA124: | ||
90 | /* clear wfe bitmap */ | 91 | /* clear wfe bitmap */ |
91 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; | 92 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; |
92 | /* clear wfi bitmap */ | 93 | /* clear wfi bitmap */ |
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) | |||
125 | break; | 126 | break; |
126 | case TEGRA30: | 127 | case TEGRA30: |
127 | case TEGRA114: | 128 | case TEGRA114: |
129 | case TEGRA124: | ||
128 | /* clear wfe bitmap */ | 130 | /* clear wfe bitmap */ |
129 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; | 131 | reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; |
130 | /* clear wfi bitmap */ | 132 | /* clear wfi bitmap */ |
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index f3b5d0d7b620..d4639c506622 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c | |||
@@ -21,14 +21,26 @@ | |||
21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/export.h> | 23 | #include <linux/export.h> |
24 | #include <linux/random.h> | ||
24 | #include <linux/tegra-soc.h> | 25 | #include <linux/tegra-soc.h> |
25 | 26 | ||
26 | #include "fuse.h" | 27 | #include "fuse.h" |
27 | #include "iomap.h" | 28 | #include "iomap.h" |
28 | #include "apbio.h" | 29 | #include "apbio.h" |
29 | 30 | ||
31 | /* Tegra20 only */ | ||
30 | #define FUSE_UID_LOW 0x108 | 32 | #define FUSE_UID_LOW 0x108 |
31 | #define FUSE_UID_HIGH 0x10c | 33 | #define FUSE_UID_HIGH 0x10c |
34 | |||
35 | /* Tegra30 and later */ | ||
36 | #define FUSE_VENDOR_CODE 0x200 | ||
37 | #define FUSE_FAB_CODE 0x204 | ||
38 | #define FUSE_LOT_CODE_0 0x208 | ||
39 | #define FUSE_LOT_CODE_1 0x20c | ||
40 | #define FUSE_WAFER_ID 0x210 | ||
41 | #define FUSE_X_COORDINATE 0x214 | ||
42 | #define FUSE_Y_COORDINATE 0x218 | ||
43 | |||
32 | #define FUSE_SKU_INFO 0x110 | 44 | #define FUSE_SKU_INFO 0x110 |
33 | 45 | ||
34 | #define TEGRA20_FUSE_SPARE_BIT 0x200 | 46 | #define TEGRA20_FUSE_SPARE_BIT 0x200 |
@@ -112,21 +124,51 @@ u32 tegra_read_chipid(void) | |||
112 | return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); | 124 | return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); |
113 | } | 125 | } |
114 | 126 | ||
127 | static void __init tegra20_fuse_init_randomness(void) | ||
128 | { | ||
129 | u32 randomness[2]; | ||
130 | |||
131 | randomness[0] = tegra_fuse_readl(FUSE_UID_LOW); | ||
132 | randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH); | ||
133 | |||
134 | add_device_randomness(randomness, sizeof(randomness)); | ||
135 | } | ||
136 | |||
137 | /* Applies to Tegra30 or later */ | ||
138 | static void __init tegra30_fuse_init_randomness(void) | ||
139 | { | ||
140 | u32 randomness[7]; | ||
141 | |||
142 | randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE); | ||
143 | randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE); | ||
144 | randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0); | ||
145 | randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1); | ||
146 | randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID); | ||
147 | randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE); | ||
148 | randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE); | ||
149 | |||
150 | add_device_randomness(randomness, sizeof(randomness)); | ||
151 | } | ||
152 | |||
115 | void __init tegra_init_fuse(void) | 153 | void __init tegra_init_fuse(void) |
116 | { | 154 | { |
117 | u32 id; | 155 | u32 id; |
156 | u32 randomness[5]; | ||
118 | 157 | ||
119 | u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); | 158 | u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); |
120 | reg |= 1 << 28; | 159 | reg |= 1 << 28; |
121 | writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); | 160 | writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); |
122 | 161 | ||
123 | reg = tegra_fuse_readl(FUSE_SKU_INFO); | 162 | reg = tegra_fuse_readl(FUSE_SKU_INFO); |
163 | randomness[0] = reg; | ||
124 | tegra_sku_id = reg & 0xFF; | 164 | tegra_sku_id = reg & 0xFF; |
125 | 165 | ||
126 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); | 166 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); |
167 | randomness[1] = reg; | ||
127 | tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; | 168 | tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; |
128 | 169 | ||
129 | id = tegra_read_chipid(); | 170 | id = tegra_read_chipid(); |
171 | randomness[2] = id; | ||
130 | tegra_chip_id = (id >> 8) & 0xff; | 172 | tegra_chip_id = (id >> 8) & 0xff; |
131 | 173 | ||
132 | switch (tegra_chip_id) { | 174 | switch (tegra_chip_id) { |
@@ -149,6 +191,18 @@ void __init tegra_init_fuse(void) | |||
149 | 191 | ||
150 | tegra_revision = tegra_get_revision(id); | 192 | tegra_revision = tegra_get_revision(id); |
151 | tegra_init_speedo_data(); | 193 | tegra_init_speedo_data(); |
194 | randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id; | ||
195 | randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id; | ||
196 | |||
197 | add_device_randomness(randomness, sizeof(randomness)); | ||
198 | switch (tegra_chip_id) { | ||
199 | case TEGRA20: | ||
200 | tegra20_fuse_init_randomness(); | ||
201 | case TEGRA30: | ||
202 | case TEGRA114: | ||
203 | default: | ||
204 | tegra30_fuse_init_randomness(); | ||
205 | } | ||
152 | 206 | ||
153 | pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", | 207 | pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", |
154 | tegra_revision_name[tegra_revision], | 208 | tegra_revision_name[tegra_revision], |
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index def79683bef6..c01d04785d67 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h | |||
@@ -29,6 +29,7 @@ | |||
29 | #define TEGRA20 0x20 | 29 | #define TEGRA20 0x20 |
30 | #define TEGRA30 0x30 | 30 | #define TEGRA30 0x30 |
31 | #define TEGRA114 0x35 | 31 | #define TEGRA114 0x35 |
32 | #define TEGRA124 0x40 | ||
32 | 33 | ||
33 | #ifndef __ASSEMBLY__ | 34 | #ifndef __ASSEMBLY__ |
34 | enum tegra_revision { | 35 | enum tegra_revision { |
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index 04de2e860923..ff26af26bd0c 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c | |||
@@ -57,4 +57,6 @@ void __init tegra_hotplug_init(void) | |||
57 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | 57 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
58 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) | 58 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) |
59 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | 59 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
60 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124) | ||
61 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | ||
60 | } | 62 | } |
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index cbee57fc4fd8..26b1c2ad0ceb 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h | |||
@@ -105,6 +105,9 @@ | |||
105 | #define TEGRA_EMC1_BASE 0x7001A800 | 105 | #define TEGRA_EMC1_BASE 0x7001A800 |
106 | #define TEGRA_EMC1_SIZE SZ_2K | 106 | #define TEGRA_EMC1_SIZE SZ_2K |
107 | 107 | ||
108 | #define TEGRA124_EMC_BASE 0x7001B000 | ||
109 | #define TEGRA124_EMC_SIZE SZ_2K | ||
110 | |||
108 | #define TEGRA_CSITE_BASE 0x70040000 | 111 | #define TEGRA_CSITE_BASE 0x70040000 |
109 | #define TEGRA_CSITE_SIZE SZ_256K | 112 | #define TEGRA_CSITE_SIZE SZ_256K |
110 | 113 | ||
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 2d0203627fbb..eb72ae709124 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
@@ -176,6 +176,8 @@ static int tegra_boot_secondary(unsigned int cpu, | |||
176 | return tegra30_boot_secondary(cpu, idle); | 176 | return tegra30_boot_secondary(cpu, idle); |
177 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) | 177 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) |
178 | return tegra114_boot_secondary(cpu, idle); | 178 | return tegra114_boot_secondary(cpu, idle); |
179 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124) | ||
180 | return tegra114_boot_secondary(cpu, idle); | ||
179 | 181 | ||
180 | return -EINVAL; | 182 | return -EINVAL; |
181 | } | 183 | } |
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 36ed88af1cc1..4ae0286b468d 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void) | |||
59 | break; | 59 | break; |
60 | case TEGRA30: | 60 | case TEGRA30: |
61 | case TEGRA114: | 61 | case TEGRA114: |
62 | case TEGRA124: | ||
62 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || | 63 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || |
63 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | 64 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
65 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | ||
64 | tegra_tear_down_cpu = tegra30_tear_down_cpu; | 66 | tegra_tear_down_cpu = tegra30_tear_down_cpu; |
65 | break; | 67 | break; |
66 | } | 68 | } |
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void) | |||
216 | break; | 218 | break; |
217 | case TEGRA30: | 219 | case TEGRA30: |
218 | case TEGRA114: | 220 | case TEGRA114: |
221 | case TEGRA124: | ||
219 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || | 222 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || |
220 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | 223 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
224 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | ||
221 | tegra30_lp1_iram_hook(); | 225 | tegra30_lp1_iram_hook(); |
222 | break; | 226 | break; |
223 | default: | 227 | default: |
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void) | |||
244 | break; | 248 | break; |
245 | case TEGRA30: | 249 | case TEGRA30: |
246 | case TEGRA114: | 250 | case TEGRA114: |
251 | case TEGRA124: | ||
247 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || | 252 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || |
248 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) | 253 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
254 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | ||
249 | tegra30_sleep_core_init(); | 255 | tegra30_sleep_core_init(); |
250 | break; | 256 | break; |
251 | default: | 257 | default: |
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 93a4dbcde27e..fb7920201ab4 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include <linux/of.h> | 21 | #include <linux/of.h> |
22 | #include <linux/of_address.h> | 22 | #include <linux/of_address.h> |
23 | #include <linux/tegra-powergate.h> | ||
23 | 24 | ||
24 | #include "flowctrl.h" | 25 | #include "flowctrl.h" |
25 | #include "fuse.h" | 26 | #include "fuse.h" |
@@ -43,12 +44,6 @@ | |||
43 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | 44 | #define PMC_CPUPWRGOOD_TIMER 0xc8 |
44 | #define PMC_CPUPWROFF_TIMER 0xcc | 45 | #define PMC_CPUPWROFF_TIMER 0xcc |
45 | 46 | ||
46 | #define TEGRA_POWERGATE_PCIE 3 | ||
47 | #define TEGRA_POWERGATE_VDEC 4 | ||
48 | #define TEGRA_POWERGATE_CPU1 9 | ||
49 | #define TEGRA_POWERGATE_CPU2 10 | ||
50 | #define TEGRA_POWERGATE_CPU3 11 | ||
51 | |||
52 | static u8 tegra_cpu_domains[] = { | 47 | static u8 tegra_cpu_domains[] = { |
53 | 0xFF, /* not available for CPU0 */ | 48 | 0xFF, /* not available for CPU0 */ |
54 | TEGRA_POWERGATE_CPU1, | 49 | TEGRA_POWERGATE_CPU1, |
@@ -288,6 +283,7 @@ void tegra_pmc_suspend_init(void) | |||
288 | #endif | 283 | #endif |
289 | 284 | ||
290 | static const struct of_device_id matches[] __initconst = { | 285 | static const struct of_device_id matches[] __initconst = { |
286 | { .compatible = "nvidia,tegra124-pmc" }, | ||
291 | { .compatible = "nvidia,tegra114-pmc" }, | 287 | { .compatible = "nvidia,tegra114-pmc" }, |
292 | { .compatible = "nvidia,tegra30-pmc" }, | 288 | { .compatible = "nvidia,tegra30-pmc" }, |
293 | { .compatible = "nvidia,tegra20-pmc" }, | 289 | { .compatible = "nvidia,tegra20-pmc" }, |
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index f076f0f80fcd..85d28e756bb7 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c | |||
@@ -42,8 +42,16 @@ | |||
42 | 42 | ||
43 | static int tegra_num_powerdomains; | 43 | static int tegra_num_powerdomains; |
44 | static int tegra_num_cpu_domains; | 44 | static int tegra_num_cpu_domains; |
45 | static u8 *tegra_cpu_domains; | 45 | static const u8 *tegra_cpu_domains; |
46 | static u8 tegra30_cpu_domains[] = { | 46 | |
47 | static const u8 tegra30_cpu_domains[] = { | ||
48 | TEGRA_POWERGATE_CPU, | ||
49 | TEGRA_POWERGATE_CPU1, | ||
50 | TEGRA_POWERGATE_CPU2, | ||
51 | TEGRA_POWERGATE_CPU3, | ||
52 | }; | ||
53 | |||
54 | static const u8 tegra114_cpu_domains[] = { | ||
47 | TEGRA_POWERGATE_CPU0, | 55 | TEGRA_POWERGATE_CPU0, |
48 | TEGRA_POWERGATE_CPU1, | 56 | TEGRA_POWERGATE_CPU1, |
49 | TEGRA_POWERGATE_CPU2, | 57 | TEGRA_POWERGATE_CPU2, |
@@ -189,6 +197,11 @@ int __init tegra_powergate_init(void) | |||
189 | tegra_num_cpu_domains = 4; | 197 | tegra_num_cpu_domains = 4; |
190 | tegra_cpu_domains = tegra30_cpu_domains; | 198 | tegra_cpu_domains = tegra30_cpu_domains; |
191 | break; | 199 | break; |
200 | case TEGRA114: | ||
201 | tegra_num_powerdomains = 23; | ||
202 | tegra_num_cpu_domains = 4; | ||
203 | tegra_cpu_domains = tegra114_cpu_domains; | ||
204 | break; | ||
192 | default: | 205 | default: |
193 | /* Unknown Tegra variant. Disable powergating */ | 206 | /* Unknown Tegra variant. Disable powergating */ |
194 | tegra_num_powerdomains = 0; | 207 | tegra_num_powerdomains = 0; |
@@ -229,6 +242,27 @@ static const char * const powergate_name_t30[] = { | |||
229 | [TEGRA_POWERGATE_3D1] = "3d1", | 242 | [TEGRA_POWERGATE_3D1] = "3d1", |
230 | }; | 243 | }; |
231 | 244 | ||
245 | static const char * const powergate_name_t114[] = { | ||
246 | [TEGRA_POWERGATE_CPU] = "cpu0", | ||
247 | [TEGRA_POWERGATE_3D] = "3d", | ||
248 | [TEGRA_POWERGATE_VENC] = "venc", | ||
249 | [TEGRA_POWERGATE_VDEC] = "vdec", | ||
250 | [TEGRA_POWERGATE_MPE] = "mpe", | ||
251 | [TEGRA_POWERGATE_HEG] = "heg", | ||
252 | [TEGRA_POWERGATE_CPU1] = "cpu1", | ||
253 | [TEGRA_POWERGATE_CPU2] = "cpu2", | ||
254 | [TEGRA_POWERGATE_CPU3] = "cpu3", | ||
255 | [TEGRA_POWERGATE_CELP] = "celp", | ||
256 | [TEGRA_POWERGATE_CPU0] = "cpu0", | ||
257 | [TEGRA_POWERGATE_C0NC] = "c0nc", | ||
258 | [TEGRA_POWERGATE_C1NC] = "c1nc", | ||
259 | [TEGRA_POWERGATE_DIS] = "dis", | ||
260 | [TEGRA_POWERGATE_DISB] = "disb", | ||
261 | [TEGRA_POWERGATE_XUSBA] = "xusba", | ||
262 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | ||
263 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | ||
264 | }; | ||
265 | |||
232 | static int powergate_show(struct seq_file *s, void *data) | 266 | static int powergate_show(struct seq_file *s, void *data) |
233 | { | 267 | { |
234 | int i; | 268 | int i; |
@@ -236,9 +270,14 @@ static int powergate_show(struct seq_file *s, void *data) | |||
236 | seq_printf(s, " powergate powered\n"); | 270 | seq_printf(s, " powergate powered\n"); |
237 | seq_printf(s, "------------------\n"); | 271 | seq_printf(s, "------------------\n"); |
238 | 272 | ||
239 | for (i = 0; i < tegra_num_powerdomains; i++) | 273 | for (i = 0; i < tegra_num_powerdomains; i++) { |
274 | if (!powergate_name[i]) | ||
275 | continue; | ||
276 | |||
240 | seq_printf(s, " %9s %7s\n", powergate_name[i], | 277 | seq_printf(s, " %9s %7s\n", powergate_name[i], |
241 | tegra_powergate_is_powered(i) ? "yes" : "no"); | 278 | tegra_powergate_is_powered(i) ? "yes" : "no"); |
279 | } | ||
280 | |||
242 | return 0; | 281 | return 0; |
243 | } | 282 | } |
244 | 283 | ||
@@ -265,6 +304,9 @@ int __init tegra_powergate_debugfs_init(void) | |||
265 | case TEGRA30: | 304 | case TEGRA30: |
266 | powergate_name = powergate_name_t30; | 305 | powergate_name = powergate_name_t30; |
267 | break; | 306 | break; |
307 | case TEGRA114: | ||
308 | powergate_name = powergate_name_t114; | ||
309 | break; | ||
268 | } | 310 | } |
269 | 311 | ||
270 | if (powergate_name) { | 312 | if (powergate_name) { |
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index f527b2c2dea7..8c1ba4fea384 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S | |||
@@ -45,17 +45,11 @@ | |||
45 | ENTRY(tegra_resume) | 45 | ENTRY(tegra_resume) |
46 | check_cpu_part_num 0xc09, r8, r9 | 46 | check_cpu_part_num 0xc09, r8, r9 |
47 | bleq v7_invalidate_l1 | 47 | bleq v7_invalidate_l1 |
48 | blne tegra_init_l2_for_a15 | ||
49 | 48 | ||
50 | cpu_id r0 | 49 | cpu_id r0 |
51 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 | ||
52 | cmp r6, #TEGRA114 | ||
53 | beq no_cpu0_chk | ||
54 | |||
55 | cmp r0, #0 @ CPU0? | 50 | cmp r0, #0 @ CPU0? |
56 | THUMB( it ne ) | 51 | THUMB( it ne ) |
57 | bne cpu_resume @ no | 52 | bne cpu_resume @ no |
58 | no_cpu0_chk: | ||
59 | 53 | ||
60 | /* Are we on Tegra20? */ | 54 | /* Are we on Tegra20? */ |
61 | cmp r6, #TEGRA20 | 55 | cmp r6, #TEGRA20 |
@@ -75,7 +69,7 @@ no_cpu0_chk: | |||
75 | 69 | ||
76 | mov32 r9, 0xc09 | 70 | mov32 r9, 0xc09 |
77 | cmp r8, r9 | 71 | cmp r8, r9 |
78 | bne not_ca9 | 72 | bne end_ca9_scu_l2_resume |
79 | #ifdef CONFIG_HAVE_ARM_SCU | 73 | #ifdef CONFIG_HAVE_ARM_SCU |
80 | /* enable SCU */ | 74 | /* enable SCU */ |
81 | mov32 r0, TEGRA_ARM_PERIF_BASE | 75 | mov32 r0, TEGRA_ARM_PERIF_BASE |
@@ -86,7 +80,10 @@ no_cpu0_chk: | |||
86 | 80 | ||
87 | /* L2 cache resume & re-enable */ | 81 | /* L2 cache resume & re-enable */ |
88 | l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr | 82 | l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr |
89 | not_ca9: | 83 | end_ca9_scu_l2_resume: |
84 | mov32 r9, 0xc0f | ||
85 | cmp r8, r9 | ||
86 | bleq tegra_init_l2_for_a15 | ||
90 | 87 | ||
91 | b cpu_resume | 88 | b cpu_resume |
92 | ENDPROC(tegra_resume) | 89 | ENDPROC(tegra_resume) |
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index c6fc15cb25df..b16d4a57fa59 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S | |||
@@ -383,7 +383,7 @@ _pll_m_c_x_done: | |||
383 | add r1, r1, #LOCK_DELAY | 383 | add r1, r1, #LOCK_DELAY |
384 | wait_until r1, r7, r3 | 384 | wait_until r1, r7, r3 |
385 | 385 | ||
386 | adr r5, tegra30_sdram_pad_save | 386 | adr r5, tegra_sdram_pad_save |
387 | 387 | ||
388 | ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT | 388 | ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT |
389 | str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] | 389 | str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] |
@@ -408,8 +408,12 @@ _pll_m_c_x_done: | |||
408 | cmp r10, #TEGRA30 | 408 | cmp r10, #TEGRA30 |
409 | movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base | 409 | movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base |
410 | movteq r0, #:upper16:TEGRA_EMC_BASE | 410 | movteq r0, #:upper16:TEGRA_EMC_BASE |
411 | movwne r0, #:lower16:TEGRA_EMC0_BASE | 411 | cmp r10, #TEGRA114 |
412 | movtne r0, #:upper16:TEGRA_EMC0_BASE | 412 | movweq r0, #:lower16:TEGRA_EMC0_BASE |
413 | movteq r0, #:upper16:TEGRA_EMC0_BASE | ||
414 | cmp r10, #TEGRA124 | ||
415 | movweq r0, #:lower16:TEGRA124_EMC_BASE | ||
416 | movteq r0, #:upper16:TEGRA124_EMC_BASE | ||
413 | 417 | ||
414 | exit_self_refresh: | 418 | exit_self_refresh: |
415 | ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL | 419 | ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL |
@@ -538,6 +542,7 @@ tegra30_sdram_pad_address: | |||
538 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | 542 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 |
539 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | 543 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 |
540 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | 544 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c |
545 | tegra30_sdram_pad_address_end: | ||
541 | 546 | ||
542 | tegra114_sdram_pad_address: | 547 | tegra114_sdram_pad_address: |
543 | .word TEGRA_EMC0_BASE + EMC_CFG @0x0 | 548 | .word TEGRA_EMC0_BASE + EMC_CFG @0x0 |
@@ -553,16 +558,28 @@ tegra114_sdram_pad_address: | |||
553 | .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 | 558 | .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 |
554 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c | 559 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c |
555 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 | 560 | .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 |
561 | tegra114_sdram_pad_adress_end: | ||
562 | |||
563 | tegra124_sdram_pad_address: | ||
564 | .word TEGRA124_EMC_BASE + EMC_CFG @0x0 | ||
565 | .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 | ||
566 | .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 | ||
567 | .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc | ||
568 | .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 | ||
569 | .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 | ||
570 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 | ||
571 | .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c | ||
572 | tegra124_sdram_pad_address_end: | ||
556 | 573 | ||
557 | tegra30_sdram_pad_size: | 574 | tegra30_sdram_pad_size: |
558 | .word tegra114_sdram_pad_address - tegra30_sdram_pad_address | 575 | .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address |
559 | 576 | ||
560 | tegra114_sdram_pad_size: | 577 | tegra114_sdram_pad_size: |
561 | .word tegra30_sdram_pad_size - tegra114_sdram_pad_address | 578 | .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address |
562 | 579 | ||
563 | .type tegra30_sdram_pad_save, %object | 580 | .type tegra_sdram_pad_save, %object |
564 | tegra30_sdram_pad_save: | 581 | tegra_sdram_pad_save: |
565 | .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4 | 582 | .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4 |
566 | .long 0 | 583 | .long 0 |
567 | .endr | 584 | .endr |
568 | 585 | ||
@@ -693,13 +710,18 @@ halted: | |||
693 | */ | 710 | */ |
694 | tegra30_sdram_self_refresh: | 711 | tegra30_sdram_self_refresh: |
695 | 712 | ||
696 | adr r8, tegra30_sdram_pad_save | 713 | adr r8, tegra_sdram_pad_save |
697 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 | 714 | tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 |
698 | cmp r10, #TEGRA30 | 715 | cmp r10, #TEGRA30 |
699 | adreq r2, tegra30_sdram_pad_address | 716 | adreq r2, tegra30_sdram_pad_address |
700 | ldreq r3, tegra30_sdram_pad_size | 717 | ldreq r3, tegra30_sdram_pad_size |
701 | adrne r2, tegra114_sdram_pad_address | 718 | cmp r10, #TEGRA114 |
702 | ldrne r3, tegra114_sdram_pad_size | 719 | adreq r2, tegra114_sdram_pad_address |
720 | ldreq r3, tegra114_sdram_pad_size | ||
721 | cmp r10, #TEGRA124 | ||
722 | adreq r2, tegra124_sdram_pad_address | ||
723 | ldreq r3, tegra30_sdram_pad_size | ||
724 | |||
703 | mov r9, #0 | 725 | mov r9, #0 |
704 | 726 | ||
705 | padsave: | 727 | padsave: |
@@ -717,7 +739,10 @@ padsave_done: | |||
717 | 739 | ||
718 | cmp r10, #TEGRA30 | 740 | cmp r10, #TEGRA30 |
719 | ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr | 741 | ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr |
720 | ldrne r0, =TEGRA_EMC0_BASE | 742 | cmp r10, #TEGRA114 |
743 | ldreq r0, =TEGRA_EMC0_BASE | ||
744 | cmp r10, #TEGRA124 | ||
745 | ldreq r0, =TEGRA124_EMC_BASE | ||
721 | 746 | ||
722 | enter_self_refresh: | 747 | enter_self_refresh: |
723 | cmp r10, #TEGRA30 | 748 | cmp r10, #TEGRA30 |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 386115ae5c03..ce553d557c31 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
@@ -173,6 +173,7 @@ static void __init tegra_dt_init_late(void) | |||
173 | } | 173 | } |
174 | 174 | ||
175 | static const char * const tegra_dt_board_compat[] = { | 175 | static const char * const tegra_dt_board_compat[] = { |
176 | "nvidia,tegra124", | ||
176 | "nvidia,tegra114", | 177 | "nvidia,tegra114", |
177 | "nvidia,tegra30", | 178 | "nvidia,tegra30", |
178 | "nvidia,tegra20", | 179 | "nvidia,tegra20", |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 4fb1f03a10d1..335beb341355 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -87,8 +87,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) | |||
87 | #endif | 87 | #endif |
88 | 88 | ||
89 | #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) | 89 | #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) |
90 | # define soc_is_s3c6400() is_samsung_s3c6400() | ||
91 | # define soc_is_s3c6410() is_samsung_s3c6410() | ||
90 | # define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) | 92 | # define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) |
91 | #else | 93 | #else |
94 | # define soc_is_s3c6400() 0 | ||
95 | # define soc_is_s3c6410() 0 | ||
92 | # define soc_is_s3c64xx() 0 | 96 | # define soc_is_s3c64xx() 0 |
93 | #endif | 97 | #endif |
94 | 98 | ||
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 3413380086d5..8eb4799237f0 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile | |||
@@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o | |||
8 | obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o | 8 | obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o |
9 | obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o | 9 | obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o |
10 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o | 10 | obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o |
11 | ifdef CONFIG_COMMON_CLK | ||
12 | obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o | 11 | obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o |
13 | endif | ||
diff --git a/drivers/cpufreq/integrator-cpufreq.c b/drivers/cpufreq/integrator-cpufreq.c index f7c99df0880b..3d79bca47433 100644 --- a/drivers/cpufreq/integrator-cpufreq.c +++ b/drivers/cpufreq/integrator-cpufreq.c | |||
@@ -15,18 +15,19 @@ | |||
15 | #include <linux/smp.h> | 15 | #include <linux/smp.h> |
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/of.h> | ||
20 | #include <linux/of_address.h> | ||
18 | 21 | ||
19 | #include <mach/hardware.h> | ||
20 | #include <mach/platform.h> | ||
21 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
22 | #include <asm/hardware/icst.h> | 23 | #include <asm/hardware/icst.h> |
23 | 24 | ||
24 | static struct cpufreq_driver integrator_driver; | 25 | static void __iomem *cm_base; |
26 | /* The cpufreq driver only use the OSC register */ | ||
27 | #define INTEGRATOR_HDR_OSC_OFFSET 0x08 | ||
28 | #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 | ||
25 | 29 | ||
26 | #define CM_ID __io_address(INTEGRATOR_HDR_ID) | 30 | static struct cpufreq_driver integrator_driver; |
27 | #define CM_OSC __io_address(INTEGRATOR_HDR_OSC) | ||
28 | #define CM_STAT __io_address(INTEGRATOR_HDR_STAT) | ||
29 | #define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK) | ||
30 | 31 | ||
31 | static const struct icst_params lclk_params = { | 32 | static const struct icst_params lclk_params = { |
32 | .ref = 24000000, | 33 | .ref = 24000000, |
@@ -100,7 +101,7 @@ static int integrator_set_target(struct cpufreq_policy *policy, | |||
100 | BUG_ON(cpu != smp_processor_id()); | 101 | BUG_ON(cpu != smp_processor_id()); |
101 | 102 | ||
102 | /* get current setting */ | 103 | /* get current setting */ |
103 | cm_osc = __raw_readl(CM_OSC); | 104 | cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); |
104 | 105 | ||
105 | if (machine_is_integrator()) { | 106 | if (machine_is_integrator()) { |
106 | vco.s = (cm_osc >> 8) & 7; | 107 | vco.s = (cm_osc >> 8) & 7; |
@@ -128,7 +129,7 @@ static int integrator_set_target(struct cpufreq_policy *policy, | |||
128 | 129 | ||
129 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); | 130 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
130 | 131 | ||
131 | cm_osc = __raw_readl(CM_OSC); | 132 | cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); |
132 | 133 | ||
133 | if (machine_is_integrator()) { | 134 | if (machine_is_integrator()) { |
134 | cm_osc &= 0xfffff800; | 135 | cm_osc &= 0xfffff800; |
@@ -138,9 +139,9 @@ static int integrator_set_target(struct cpufreq_policy *policy, | |||
138 | } | 139 | } |
139 | cm_osc |= vco.v; | 140 | cm_osc |= vco.v; |
140 | 141 | ||
141 | __raw_writel(0xa05f, CM_LOCK); | 142 | __raw_writel(0xa05f, cm_base + INTEGRATOR_HDR_LOCK_OFFSET); |
142 | __raw_writel(cm_osc, CM_OSC); | 143 | __raw_writel(cm_osc, cm_base + INTEGRATOR_HDR_OSC_OFFSET); |
143 | __raw_writel(0, CM_LOCK); | 144 | __raw_writel(0, cm_base + INTEGRATOR_HDR_LOCK_OFFSET); |
144 | 145 | ||
145 | /* | 146 | /* |
146 | * Restore the CPUs allowed mask. | 147 | * Restore the CPUs allowed mask. |
@@ -165,7 +166,7 @@ static unsigned int integrator_get(unsigned int cpu) | |||
165 | BUG_ON(cpu != smp_processor_id()); | 166 | BUG_ON(cpu != smp_processor_id()); |
166 | 167 | ||
167 | /* detect memory etc. */ | 168 | /* detect memory etc. */ |
168 | cm_osc = __raw_readl(CM_OSC); | 169 | cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET); |
169 | 170 | ||
170 | if (machine_is_integrator()) { | 171 | if (machine_is_integrator()) { |
171 | vco.s = (cm_osc >> 8) & 7; | 172 | vco.s = (cm_osc >> 8) & 7; |
@@ -202,19 +203,43 @@ static struct cpufreq_driver integrator_driver = { | |||
202 | .name = "integrator", | 203 | .name = "integrator", |
203 | }; | 204 | }; |
204 | 205 | ||
205 | static int __init integrator_cpu_init(void) | 206 | static int __init integrator_cpufreq_probe(struct platform_device *pdev) |
206 | { | 207 | { |
208 | struct resource *res; | ||
209 | |||
210 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
211 | if (!res) | ||
212 | return -ENODEV; | ||
213 | |||
214 | cm_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
215 | if (!cm_base) | ||
216 | return -ENODEV; | ||
217 | |||
207 | return cpufreq_register_driver(&integrator_driver); | 218 | return cpufreq_register_driver(&integrator_driver); |
208 | } | 219 | } |
209 | 220 | ||
210 | static void __exit integrator_cpu_exit(void) | 221 | static void __exit integrator_cpufreq_remove(struct platform_device *pdev) |
211 | { | 222 | { |
212 | cpufreq_unregister_driver(&integrator_driver); | 223 | cpufreq_unregister_driver(&integrator_driver); |
213 | } | 224 | } |
214 | 225 | ||
226 | static const struct of_device_id integrator_cpufreq_match[] = { | ||
227 | { .compatible = "arm,core-module-integrator"}, | ||
228 | { }, | ||
229 | }; | ||
230 | |||
231 | static struct platform_driver integrator_cpufreq_driver = { | ||
232 | .driver = { | ||
233 | .name = "integrator-cpufreq", | ||
234 | .owner = THIS_MODULE, | ||
235 | .of_match_table = integrator_cpufreq_match, | ||
236 | }, | ||
237 | .remove = __exit_p(integrator_cpufreq_remove), | ||
238 | }; | ||
239 | |||
240 | module_platform_driver_probe(integrator_cpufreq_driver, | ||
241 | integrator_cpufreq_probe); | ||
242 | |||
215 | MODULE_AUTHOR ("Russell M. King"); | 243 | MODULE_AUTHOR ("Russell M. King"); |
216 | MODULE_DESCRIPTION ("cpufreq driver for ARM Integrator CPUs"); | 244 | MODULE_DESCRIPTION ("cpufreq driver for ARM Integrator CPUs"); |
217 | MODULE_LICENSE ("GPL"); | 245 | MODULE_LICENSE ("GPL"); |
218 | |||
219 | module_init(integrator_cpu_init); | ||
220 | module_exit(integrator_cpu_exit); | ||
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 8e3660322308..d6f57d5d9631 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm | |||
@@ -4,7 +4,7 @@ | |||
4 | 4 | ||
5 | config ARM_HIGHBANK_CPUIDLE | 5 | config ARM_HIGHBANK_CPUIDLE |
6 | bool "CPU Idle Driver for Calxeda processors" | 6 | bool "CPU Idle Driver for Calxeda processors" |
7 | depends on ARCH_HIGHBANK | 7 | depends on ARM_PSCI |
8 | select ARM_CPU_SUSPEND | 8 | select ARM_CPU_SUSPEND |
9 | help | 9 | help |
10 | Select this to enable cpuidle on Calxeda processors. | 10 | Select this to enable cpuidle on Calxeda processors. |
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c index 346058479572..36795639df0d 100644 --- a/drivers/cpuidle/cpuidle-calxeda.c +++ b/drivers/cpuidle/cpuidle-calxeda.c | |||
@@ -21,53 +21,30 @@ | |||
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include <linux/cpuidle.h> | 23 | #include <linux/cpuidle.h> |
24 | #include <linux/cpu_pm.h> | ||
24 | #include <linux/init.h> | 25 | #include <linux/init.h> |
25 | #include <linux/io.h> | 26 | #include <linux/mm.h> |
26 | #include <linux/of.h> | 27 | #include <linux/platform_device.h> |
27 | #include <linux/time.h> | ||
28 | #include <linux/delay.h> | ||
29 | #include <linux/suspend.h> | ||
30 | #include <asm/cpuidle.h> | 28 | #include <asm/cpuidle.h> |
31 | #include <asm/proc-fns.h> | ||
32 | #include <asm/smp_scu.h> | ||
33 | #include <asm/suspend.h> | 29 | #include <asm/suspend.h> |
34 | #include <asm/cacheflush.h> | 30 | #include <asm/psci.h> |
35 | #include <asm/cp15.h> | ||
36 | |||
37 | extern void highbank_set_cpu_jump(int cpu, void *jump_addr); | ||
38 | extern void __iomem *scu_base_addr; | ||
39 | |||
40 | static noinline void calxeda_idle_restore(void) | ||
41 | { | ||
42 | set_cr(get_cr() | CR_C); | ||
43 | set_auxcr(get_auxcr() | 0x40); | ||
44 | scu_power_mode(scu_base_addr, SCU_PM_NORMAL); | ||
45 | } | ||
46 | 31 | ||
47 | static int calxeda_idle_finish(unsigned long val) | 32 | static int calxeda_idle_finish(unsigned long val) |
48 | { | 33 | { |
49 | /* Already flushed cache, but do it again as the outer cache functions | 34 | const struct psci_power_state ps = { |
50 | * dirty the cache with spinlocks */ | 35 | .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, |
51 | flush_cache_all(); | 36 | }; |
52 | 37 | return psci_ops.cpu_suspend(ps, __pa(cpu_resume)); | |
53 | set_auxcr(get_auxcr() & ~0x40); | ||
54 | set_cr(get_cr() & ~CR_C); | ||
55 | |||
56 | scu_power_mode(scu_base_addr, SCU_PM_DORMANT); | ||
57 | |||
58 | cpu_do_idle(); | ||
59 | |||
60 | /* Restore things if we didn't enter power-gating */ | ||
61 | calxeda_idle_restore(); | ||
62 | return 1; | ||
63 | } | 38 | } |
64 | 39 | ||
65 | static int calxeda_pwrdown_idle(struct cpuidle_device *dev, | 40 | static int calxeda_pwrdown_idle(struct cpuidle_device *dev, |
66 | struct cpuidle_driver *drv, | 41 | struct cpuidle_driver *drv, |
67 | int index) | 42 | int index) |
68 | { | 43 | { |
69 | highbank_set_cpu_jump(smp_processor_id(), cpu_resume); | 44 | cpu_pm_enter(); |
70 | cpu_suspend(0, calxeda_idle_finish); | 45 | cpu_suspend(0, calxeda_idle_finish); |
46 | cpu_pm_exit(); | ||
47 | |||
71 | return index; | 48 | return index; |
72 | } | 49 | } |
73 | 50 | ||
@@ -88,11 +65,17 @@ static struct cpuidle_driver calxeda_idle_driver = { | |||
88 | .state_count = 2, | 65 | .state_count = 2, |
89 | }; | 66 | }; |
90 | 67 | ||
91 | static int __init calxeda_cpuidle_init(void) | 68 | static int __init calxeda_cpuidle_probe(struct platform_device *pdev) |
92 | { | 69 | { |
93 | if (!of_machine_is_compatible("calxeda,highbank")) | ||
94 | return -ENODEV; | ||
95 | |||
96 | return cpuidle_register(&calxeda_idle_driver, NULL); | 70 | return cpuidle_register(&calxeda_idle_driver, NULL); |
97 | } | 71 | } |
98 | module_init(calxeda_cpuidle_init); | 72 | |
73 | static struct platform_driver calxeda_cpuidle_plat_driver = { | ||
74 | .driver = { | ||
75 | .name = "cpuidle-calxeda", | ||
76 | .owner = THIS_MODULE, | ||
77 | }, | ||
78 | .probe = calxeda_cpuidle_probe, | ||
79 | }; | ||
80 | |||
81 | module_platform_driver(calxeda_cpuidle_plat_driver); | ||
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f238cfd33847..56fe803adcb1 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig | |||
@@ -195,7 +195,7 @@ config SIRF_DMA | |||
195 | 195 | ||
196 | config TI_EDMA | 196 | config TI_EDMA |
197 | bool "TI EDMA support" | 197 | bool "TI EDMA support" |
198 | depends on ARCH_DAVINCI || ARCH_OMAP | 198 | depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE |
199 | select DMA_ENGINE | 199 | select DMA_ENGINE |
200 | select DMA_VIRTUAL_CHANNELS | 200 | select DMA_VIRTUAL_CHANNELS |
201 | select TI_PRIV_EDMA | 201 | select TI_PRIV_EDMA |
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c index be3429e08d90..f90101b9cdb9 100644 --- a/drivers/usb/host/ohci-s3c2410.c +++ b/drivers/usb/host/ohci-s3c2410.c | |||
@@ -64,10 +64,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd) | |||
64 | 64 | ||
65 | dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); | 65 | dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); |
66 | 66 | ||
67 | clk_enable(usb_clk); | 67 | clk_prepare_enable(usb_clk); |
68 | mdelay(2); /* let the bus clock stabilise */ | 68 | mdelay(2); /* let the bus clock stabilise */ |
69 | 69 | ||
70 | clk_enable(clk); | 70 | clk_prepare_enable(clk); |
71 | 71 | ||
72 | if (info != NULL) { | 72 | if (info != NULL) { |
73 | info->hcd = hcd; | 73 | info->hcd = hcd; |
@@ -92,8 +92,8 @@ static void s3c2410_stop_hc(struct platform_device *dev) | |||
92 | (info->enable_oc)(info, 0); | 92 | (info->enable_oc)(info, 0); |
93 | } | 93 | } |
94 | 94 | ||
95 | clk_disable(clk); | 95 | clk_disable_unprepare(clk); |
96 | clk_disable(usb_clk); | 96 | clk_disable_unprepare(usb_clk); |
97 | } | 97 | } |
98 | 98 | ||
99 | /* ohci_s3c2410_hub_status_data | 99 | /* ohci_s3c2410_hub_status_data |
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index b6bdcd66c07d..7086b2248c8f 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |||
@@ -363,4 +363,9 @@ | |||
363 | #define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2) | 363 | #define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2) |
364 | #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) | 364 | #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) |
365 | #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) | 365 | #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) |
366 | |||
367 | /* For imx6sl iomux gpr register field define */ | ||
368 | #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) | ||
369 | #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) | ||
370 | |||
366 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ | 371 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h index 55c29a8d5015..c98cfa406952 100644 --- a/include/linux/tegra-powergate.h +++ b/include/linux/tegra-powergate.h | |||
@@ -34,8 +34,15 @@ struct clk; | |||
34 | #define TEGRA_POWERGATE_CPU3 11 | 34 | #define TEGRA_POWERGATE_CPU3 11 |
35 | #define TEGRA_POWERGATE_CELP 12 | 35 | #define TEGRA_POWERGATE_CELP 12 |
36 | #define TEGRA_POWERGATE_3D1 13 | 36 | #define TEGRA_POWERGATE_3D1 13 |
37 | #define TEGRA_POWERGATE_CPU0 14 | ||
38 | #define TEGRA_POWERGATE_C0NC 15 | ||
39 | #define TEGRA_POWERGATE_C1NC 16 | ||
40 | #define TEGRA_POWERGATE_DIS 18 | ||
41 | #define TEGRA_POWERGATE_DISB 19 | ||
42 | #define TEGRA_POWERGATE_XUSBA 20 | ||
43 | #define TEGRA_POWERGATE_XUSBB 21 | ||
44 | #define TEGRA_POWERGATE_XUSBC 22 | ||
37 | 45 | ||
38 | #define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU | ||
39 | #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D | 46 | #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D |
40 | 47 | ||
41 | int tegra_powergate_is_powered(int id); | 48 | int tegra_powergate_is_powered(int id); |