Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New and updated SoC support.  Among the things new for this release
  are:

   - More support for the AM33xx platforms from TI
   - Tegra 124 support, and some updates to older tegra families as well
   - imx cleanups and updates across the board
   - A rename of Broadcom's Mobile platforms which were introduced as
     ARCH_BCM, and turned out to be too broad a name.  New name is
     ARCH_BCM_MOBILE.
   - A whole bunch of updates and fixes for integrator, making the
     platform code more modern and switches over to DT-only booting.
   - Support for two new Renesas shmobile chipsets.  Next up for them is
     more work on consolidation instead of introduction of new
     non-multiplatform SoCs, we're all looking forward to that!
   - Misc cleanups for older Samsung platforms, some Allwinner updates,
     etc"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (159 commits)
  ARM: bcm281xx: Add ARCH_BCM_MOBILE to bcm config
  ARM: bcm_defconfig: Run "make savedefconfig"
  ARM: bcm281xx: Add ARCH Timers to config
  rename ARCH_BCM to ARCH_BCM_MOBILE (mach-bcm)
  ARM: vexpress: Enable platform-specific options in defconfig
  ARM: vexpress: Make defconfig work again
  ARM: sunxi: remove .init_time hooks
  ARM: imx: enable suspend for imx6sl
  ARM: imx: ensure dsm_request signal is not asserted when setting LPM
  ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter()
  ARM: imx6q: move low-power code out of clock driver
  ARM: imx: drop extern with function prototypes in common.h
  ARM: imx: reset core along with enable/disable operation
  ARM: imx: do not return from imx_cpu_die() call
  ARM: imx_v6_v7_defconfig: Select CONFIG_PROVE_LOCKING
  ARM: imx_v6_v7_defconfig: Enable LEDS_GPIO related options
  ARM: mxs_defconfig: Turn off CONFIG_DEBUG_GPIO
  ARM: imx: replace imx6q_restart() with mxc_restart()
  ARM: mach-imx: mm-imx5: Retrieve iomuxc base address from dt
  ARM: mach-imx: mm-imx5: Retrieve tzic base address from dt
  ...

189 files changed, 8183 insertions, 5212 deletions

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index 8f08a86e03b7..da0151db9964 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -88,6 +88,7 @@ EBU Armada family
         MV78230
         MV78260
         MV78460
+    NOTE: not to be confused with the non-SMP 78xx0 SoCs
 
   Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
   No public datasheet available.
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index e3f93fb9224e..7945238453ed 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -10,6 +10,10 @@ SunXi family
   Linux kernel mach directory: arch/arm/mach-sunxi
 
   Flavors:
+    * ARM926 based SoCs
+      - Allwinner F20 (sun3i)
+        + Not Supported
+
     * ARM Cortex-A8 based SoCs
       - Allwinner A10 (sun4i)
         + Datasheet
@@ -25,4 +29,24 @@ SunXi family
         + Datasheet
           http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
         + User Manual
-          http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf
+          http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-01-08%29.pdf
+
+    * Dual ARM Cortex-A7 based SoCs
+      - Allwinner A20 (sun7i)
+        + User Manual
+          http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
+
+      - Allwinner A23
+        + Not Supported
+
+    * Quad ARM Cortex-A7 based SoCs
+      - Allwinner A31 (sun6i)
+        + Datasheet
+          http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf
+
+      - Allwinner A31s (sun6i)
+        + Not Supported
+
+    * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
+      - Allwinner A80
+        + Not Supported
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index db5858e32d3f..5fac246a9530 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -9,9 +9,53 @@ Required properties (in root node):
 
 FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
 
-In the root node the Integrator/CP must have a /cpcon node pointing
-to the CP control registers, and the Integrator/AP must have a
-/syscon node pointing to the Integrator/AP system controller.
+Required nodes:
+
+- core-module: the root node to the Integrator platforms must have
+  a core-module with regs and the compatible string
+  "arm,core-module-integrator"
+
+  Required properties for the core module:
+  - regs: the location and size of the core module registers, one
+    range of 0x200 bytes.
+
+- syscon: the root node of the Integrator platforms must have a
+  system controller node pointong to the control registers,
+  with the compatible string
+  "arm,integrator-ap-syscon"
+  "arm,integrator-cp-syscon"
+  respectively.
+
+  Required properties for the system controller:
+  - regs: the location and size of the system controller registers,
+    one range of 0x100 bytes.
+
+  Required properties for the AP system controller:
+  - interrupts: the AP syscon node must include the logical module
+    interrupts, stated in order of module instance <module 0>,
+    <module 1>, <module 2> ... for the CP system controller this
+    is not required not of any use.
+
+/dts-v1/;
+/include/ "integrator.dtsi"
+
+/ {
+        model = "ARM Integrator/AP";
+        compatible = "arm,integrator-ap";
+
+        core-module@10000000 {
+                compatible = "arm,core-module-integrator";
+                reg = <0x10000000 0x200>;
+        };
+
+        syscon {
+                compatible = "arm,integrator-ap-syscon";
+                reg = <0x11000000 0x100>;
+                interrupt-parent = <&pic>;
+                /* These are the logic module IRQs */
+                interrupts = <9>, <10>, <11>, <12>;
+        };
+};
 
 
 ARM Versatile Application and Platform Baseboards
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 5a90a724b520..6aab72bf67ea 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -215,6 +215,11 @@ clocks and IDs.
         cko2                    200
         cko                     201
         vdoa                    202
+        pll4_audio_div          203
+        lvds1_sel               204
+        lvds2_sel               205
+        lvds1_gate              206
+        lvds2_gate              207
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 00a5c26454eb..91a748fed13d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -45,8 +45,8 @@ Additionally, "allwinner,*-gates-clk" clocks require:
 
 Clock consumers should specify the desired clocks they use with a
 "clocks" phandle cell. Consumers that are using a gated clock should
-provide an additional ID in their clock property. The values of this
-ID are documented in sunxi/<soc>-gates.txt.
+provide an additional ID in their clock property. This ID is the
+offset of the bit controlling this particular gate in the register.
 
 For example:
 
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
deleted file mode 100644
index 6a03475bbfe2..000000000000
--- a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-Gate clock outputs
-------------------
-
-  * AXI gates ("allwinner,sun4i-axi-gates-clk")
-
-    DRAM                                        0
-
-  * AHB gates ("allwinner,sun4i-ahb-gates-clk")
-
-    USB0                                        0
-    EHCI0                                       1
-    OHCI0                                       2*
-    EHCI1                                       3
-    OHCI1                                       4*
-    SS                                          5
-    DMA                                         6
-    BIST                                        7
-    MMC0                                        8
-    MMC1                                        9
-    MMC2                                        10
-    MMC3                                        11
-    MS                                          12**
-    NAND                                        13
-    SDRAM                                       14
-
-    ACE                                         16
-    EMAC                                        17
-    TS                                          18
-
-    SPI0                                        20
-    SPI1                                        21
-    SPI2                                        22
-    SPI3                                        23
-    PATA                                        24
-    SATA                                        25**
-    GPS                                         26*
-
-    VE                                          32
-    TVD                                         33
-    TVE0                                        34
-    TVE1                                        35
-    LCD0                                        36
-    LCD1                                        37
-
-    CSI0                                        40
-    CSI1                                        41
-
-    HDMI                                        43
-    DE_BE0                                      44
-    DE_BE1                                      45
-    DE_FE1                                      46
-    DE_FE1                                      47
-
-    MP                                          50
-
-    MALI400                                     52
-
-  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
-
-    CODEC                                       0
-    SPDIF                                       1*
-    AC97                                        2
-    IIS                                         3
-
-    PIO                                         5
-    IR0                                         6
-    IR1                                         7
-
-    KEYPAD                                      10
-
-  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
-
-    I2C0                                        0
-    I2C1                                        1
-    I2C2                                        2
-
-    CAN                                         4
-    SCR                                         5
-    PS20                                        6
-    PS21                                        7
-
-    UART0                                       16
-    UART1                                       17
-    UART2                                       18
-    UART3                                       19
-    UART4                                       20
-    UART5                                       21
-    UART6                                       22
-    UART7                                       23
-
-Notation:
- [*]:  The datasheet didn't mention these, but they are present on AW code
- [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
deleted file mode 100644
index d24279fe1429..000000000000
--- a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-Gate clock outputs
-------------------
-
-  * AXI gates ("allwinner,sun4i-axi-gates-clk")
-
-    DRAM                                        0
-
-  * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
-
-    USB0                                        0
-    EHCI0                                       1
-    OHCI0                                       2
-
-    SS                                          5
-    DMA                                         6
-    BIST                                        7
-    MMC0                                        8
-    MMC1                                        9
-    MMC2                                        10
-
-    NAND                                        13
-    SDRAM                                       14
-
-    EMAC                                        17
-    TS                                          18
-
-    SPI0                                        20
-    SPI1                                        21
-    SPI2                                        22
-
-    GPS                                         26
-
-    HSTIMER                                     28
-
-    VE                                          32
-
-    TVE                                         34
-
-    LCD                                         36
-
-    CSI                                         40
-
-    HDMI                                        43
-    DE_BE                                       44
-
-    DE_FE                                       46
-
-    IEP                                         51
-    MALI400                                     52
-
-  * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
-
-    CODEC                                       0
-
-    IIS                                         3
-
-    PIO                                         5
-    IR                                          6
-
-    KEYPAD                                      10
-
-  * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
-
-    I2C0                                        0
-    I2C1                                        1
-    I2C2                                        2
-
-    UART0                                       16
-    UART1                                       17
-    UART2                                       18
-    UART3                                       19
-
-Notation:
- [*]:  The datasheet didn't mention these, but they are present on AW code
- [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
deleted file mode 100644
index 006b6dfc4703..000000000000
--- a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-Gate clock outputs
-------------------
-
-  * AXI gates ("allwinner,sun4i-axi-gates-clk")
-
-    DRAM                                        0
-
-  * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
-
-    USBOTG                                      0
-    EHCI                                        1
-    OHCI                                        2
-
-    SS                                          5
-    DMA                                         6
-    BIST                                        7
-    MMC0                                        8
-    MMC1                                        9
-    MMC2                                        10
-
-    NAND                                        13
-    SDRAM                                       14
-
-    SPI0                                        20
-    SPI1                                        21
-    SPI2                                        22
-
-    STIMER                                      28
-
-    VE                                          32
-
-    LCD                                         36
-
-    CSI                                         40
-
-    DE_BE                                       44
-
-    DE_FE                                       46
-
-    IEP                                         51
-    MALI400                                     52
-
-  * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
-
-    CODEC                                       0
-
-    PIO                                         5
-    IR                                          6
-
-  * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
-
-    I2C0                                        0
-    I2C1                                        1
-    I2C2                                        2
-
-    UART1                                       17
-
-    UART3                                       19
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
deleted file mode 100644
index fe44932b5c6b..000000000000
--- a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Gate clock outputs
-------------------
-
-  * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk")
-
-    MIPI DSI                                    1
-
-    SS                                          5
-    DMA                                         6
-
-    MMC0                                        8
-    MMC1                                        9
-    MMC2                                        10
-    MMC3                                        11
-
-    NAND1                                       12
-    NAND0                                       13
-    SDRAM                                       14
-
-    GMAC                                        17
-    TS                                          18
-    HSTIMER                                     19
-    SPI0                                        20
-    SPI1                                        21
-    SPI2                                        22
-    SPI3                                        23
-    USB_OTG                                     24
-
-    EHCI0                                       26
-    EHCI1                                       27
-
-    OHCI0                                       29
-    OHCI1                                       30
-    OHCI2                                       31
-    VE                                          32
-
-    LCD0                                        36
-    LCD1                                        37
-
-    CSI                                         40
-
-    HDMI                                        43
-    DE_BE0                                      44
-    DE_BE1                                      45
-    DE_FE1                                      46
-    DE_FE1                                      47
-
-    MP                                          50
-
-    GPU                                         52
-
-    DEU0                                        55
-    DEU1                                        56
-    DRC0                                        57
-    DRC1                                        58
-
-  * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk")
-
-    CODEC                                       0
-
-    DIGITAL MIC                                 4
-    PIO                                         5
-
-    DAUDIO0                                     12
-    DAUDIO1                                     13
-
-  * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk")
-
-    I2C0                                        0
-    I2C1                                        1
-    I2C2                                        2
-    I2C3                                        3
-
-    UART0                                       16
-    UART1                                       17
-    UART2                                       18
-    UART3                                       19
-    UART4                                       20
-    UART5                                       21
-
-Notation:
- [*]:  The datasheet didn't mention these, but they are present on AW code
- [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
deleted file mode 100644
index 357f4fdc02ef..000000000000
--- a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Gate clock outputs
-------------------
-
-  * AXI gates ("allwinner,sun4i-axi-gates-clk")
-
-    DRAM                                        0
-
-  * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk")
-
-    USB0                                        0
-    EHCI0                                       1
-    OHCI0                                       2
-    EHCI1                                       3
-    OHCI1                                       4
-    SS                                          5
-    DMA                                         6
-    BIST                                        7
-    MMC0                                        8
-    MMC1                                        9
-    MMC2                                        10
-    MMC3                                        11
-    MS                                          12
-    NAND                                        13
-    SDRAM                                       14
-
-    ACE                                         16
-    EMAC                                        17
-    TS                                          18
-
-    SPI0                                        20
-    SPI1                                        21
-    SPI2                                        22
-    SPI3                                        23
-
-    SATA                                        25
-
-    HSTIMER                                     28
-
-    VE                                          32
-    TVD                                         33
-    TVE0                                        34
-    TVE1                                        35
-    LCD0                                        36
-    LCD1                                        37
-
-    CSI0                                        40
-    CSI1                                        41
-
-    HDMI1                                       42
-    HDMI0                                       43
-    DE_BE0                                      44
-    DE_BE1                                      45
-    DE_FE1                                      46
-    DE_FE1                                      47
-
-    GMAC                                        49
-    MP                                          50
-
-    MALI400                                     52
-
-  * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk")
-
-    CODEC                                       0
-    SPDIF                                       1
-    AC97                                        2
-    IIS0                                        3
-    IIS1                                        4
-    PIO                                         5
-    IR0                                         6
-    IR1                                         7
-    IIS2                                        8
-
-    KEYPAD                                      10
-
-  * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk")
-
-    I2C0                                        0
-    I2C1                                        1
-    I2C2                                        2
-    I2C3                                        3
-    CAN                                         4
-    SCR                                         5
-    PS20                                        6
-    PS21                                        7
-
-    I2C4                                        15
-    UART0                                       16
-    UART1                                       17
-    UART2                                       18
-    UART3                                       19
-    UART4                                       20
-    UART5                                       21
-    UART6                                       22
-    UART7                                       23
-
-Notation:
- [*]:  The datasheet didn't mention these, but they are present on AW code
- [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index 57edb30dbbca..3d3b2b91e333 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -8,9 +8,6 @@ Required properties:
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source. The value shall be 1.
 
-For the valid interrupt sources for your SoC, see the documentation in
-sunxi/<soc>.txt
-
 Example:
 
 intc: interrupt-controller {
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
deleted file mode 100644
index 76b98c834499..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
+++ /dev/null
@@ -1,89 +0,0 @@
-Allwinner A10 (sun4i) interrupt sources
----------------------------------------
-
-The interrupt sources available for the Allwinner A10 SoC are the
-following one:
-
-0: ENMI
-1: UART0
-2: UART1
-3: UART2
-4: UART3
-5: IR0
-6: IR1
-7: I2C0
-8: I2C1
-9: I2C2
-10: SPI0
-11: SPI1
-12: SPI2
-13: SPDIF
-14: AC97
-15: TS
-16: I2S
-17: UART4
-18: UART5
-19: UART6
-20: UART7
-21: KEYPAD
-22: TIMER0
-23: TIMER1
-24: TIMER2
-25: TIMER3
-26: CAN
-27: DMA
-28: PIO
-29: TOUCH_PANEL
-30: AUDIO_CODEC
-31: LRADC
-32: MMC0
-33: MMC1
-34: MMC2
-35: MMC3
-36: MEMSTICK
-37: NAND
-38: USB0
-39: USB1
-40: USB2
-41: SCR
-42: CSI0
-43: CSI1
-44: LCDCTRL0
-45: LCDCTRL1
-46: MP
-47: DEFEBE0
-48: DEFEBE1
-49: PMU
-50: SPI3
-51: TZASC
-52: PATA
-53: VE
-54: SS
-55: EMAC
-56: SATA
-57: GPS
-58: HDMI
-59: TVE
-60: ACE
-61: TVD
-62: PS2_0
-63: PS2_1
-64: USB3
-65: USB4
-66: PLE_PFM
-67: TIMER4
-68: TIMER5
-69: GPU_GP
-70: GPU_GPMMU
-71: GPU_PP0
-72: GPU_PPMMU0
-73: GPU_PMU
-74: GPU_RSV0
-75: GPU_RSV1
-76: GPU_RSV2
-77: GPU_RSV3
-78: GPU_RSV4
-79: GPU_RSV5
-80: GPU_RSV6
-82: SYNC_TIMER0
-83: SYNC_TIMER1
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
deleted file mode 100644
index 2ec3b5ce1a0b..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Allwinner A13 (sun5i) interrupt sources
----------------------------------------
-
-The interrupt sources available for the Allwinner A13 SoC are the
-following one:
-
-0: ENMI
-2: UART1
-4: UART3
-5: IR
-7: I2C0
-8: I2C1
-9: I2C2
-10: SPI0
-11: SPI1
-12: SPI2
-22: TIMER0
-23: TIMER1
-24: TIMER2
-25: TIMER3
-27: DMA
-28: PIO
-29: TOUCH_PANEL
-30: AUDIO_CODEC
-31: LRADC
-32: MMC0
-33: MMC1
-34: MMC2
-37: NAND
-38: USB OTG
-39: USB EHCI
-40: USB OHCI
-42: CSI
-44: LCDCTRL
-47: DEFEBE
-49: PMU
-53: VE
-54: SS
-66: PLE_PFM
-67: TIMER4
-68: TIMER5
-69: GPU_GP
-70: GPU_GPMMU
-71: GPU_PP0
-72: GPU_PPMMU0
-73: GPU_PMU
-74: GPU_RSV0
-75: GPU_RSV1
-76: GPU_RSV2
-77: GPU_RSV3
-78: GPU_RSV4
-79: GPU_RSV5
-80: GPU_RSV6
-82: SYNC_TIMER0
-83: SYNC_TIMER1
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e98261cb05bd..9bd3a85d880f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -317,6 +317,7 @@ config ARCH_INTEGRATOR
         select NEED_MACH_MEMORY_H
         select PLAT_VERSATILE
         select SPARSE_IRQ
+        select USE_OF
         select VERSATILE_FPGA_IRQ
         help
           Support for ARM's Integrator platform.
@@ -723,6 +724,7 @@ config ARCH_S3C64XX
         select ARM_VIC
         select CLKDEV_LOOKUP
         select CLKSRC_SAMSUNG_PWM
+        select COMMON_CLK
         select CPU_V6
         select GENERIC_CLOCKEVENTS
         select GPIO_SAMSUNG
@@ -736,7 +738,6 @@ config ARCH_S3C64XX
         select S3C_DEV_NAND
         select S3C_GPIO_TRACK
         select SAMSUNG_ATAGS
-        select SAMSUNG_CLKSRC
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_WAKEMASK
         select SAMSUNG_WDT_RESET
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9762c84b4198..d597c6b8488b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -386,6 +386,13 @@ choice
                   when u-boot hands over to the kernel, the system
                   silently crashes, with no serial output at all.
 
+        config DEBUG_VF_UART
+                bool "Vybrid UART"
+                depends on SOC_VF610
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Vybrid based platforms.
+
         config DEBUG_NOMADIK_UART
                 bool "Kernel low-level debugging messages via NOMADIK UART"
                 depends on ARCH_NOMADIK
@@ -906,6 +913,7 @@ config DEBUG_LL_INCLUDE
         default "debug/tegra.S" if DEBUG_TEGRA_UART
         default "debug/ux500.S" if DEBUG_UX500_UART
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT
+        default "debug/vf.S" if DEBUG_VF_UART
         default "debug/vt8500.S" if DEBUG_VT8500_UART0
         default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
         default "mach/debug-macro.S"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index e8559b753c9d..bc22557d7a6a 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -19,6 +19,14 @@
                 bootargs = "console=ttyAMA0";
         };
 
+        psci {
+                compatible      = "arm,psci";
+                method          = "smc";
+                cpu_suspend     = <0x84000002>;
+                cpu_off         = <0x84000004>;
+                cpu_on          = <0x84000006>;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c46651e4d966..177d9e791a01 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -380,7 +380,9 @@
                         };
 
                         anatop: anatop@020c8000 {
-                                compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+                                compatible = "fsl,imx6sl-anatop",
+                                             "fsl,imx6q-anatop",
+                                             "syscon", "simple-bus";
                                 reg = <0x020c8000 0x1000>;
                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 813b91d7bea2..0f06f8687b0b 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -5,6 +5,11 @@
 /include/ "skeleton.dtsi"
 
 / {
+        core-module@10000000 {
+                compatible = "arm,core-module-integrator";
+                reg = <0x10000000 0x200>;
+        };
+
         timer@13000000 {
                 reg = <0x13000000 0x100>;
                 interrupt-parent = <&pic>;
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index b6b82eca8d1e..e6be9315ff0a 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -19,8 +19,11 @@
         };
 
         syscon {
-                /* AP system controller registers */
+                compatible = "arm,integrator-ap-syscon";
                 reg = <0x11000000 0x100>;
+                interrupt-parent = <&pic>;
+                /* These are the logical module IRQs */
+                interrupts = <9>, <10>, <11>, <12>;
         };
 
         timer0: timer@13000000 {
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 72693a69f830..7deb3a3182b4 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -13,8 +13,8 @@
                 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
         };
 
-        cpcon {
-                /* CP controller registers */
+        syscon {
+                compatible = "arm,integrator-cp-syscon";
                 reg = <0xcb000000 0x100>;
         };
 
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
new file mode 100644
index 000000000000..d6713b113258
--- /dev/null
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -0,0 +1,821 @@
+/*
+ * Device Tree Source for Keystone 2 clock tree
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clocks {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        refclkmain: refclkmain {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <122880000>;
+                clock-output-names = "refclk-main";
+        };
+
+        mainpllclk: mainpllclk@2310110 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,main-pll-clock";
+                clocks = <&refclkmain>;
+                reg = <0x02620350 4>, <0x02310110 4>;
+                reg-names = "control", "multiplier";
+                fixed-postdiv = <2>;
+        };
+
+        papllclk: papllclk@2620358 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkmain>;
+                clock-output-names = "pa-pll-clk";
+                reg = <0x02620358 4>;
+                reg-names = "control";
+                fixed-postdiv = <6>;
+        };
+
+        ddr3allclk: ddr3apllclk@2620360 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkmain>;
+                clock-output-names = "ddr-3a-pll-clk";
+                reg = <0x02620360 4>;
+                reg-names = "control";
+                fixed-postdiv = <6>;
+        };
+
+        ddr3bllclk: ddr3bpllclk@2620368 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkmain>;
+                clock-output-names = "ddr-3b-pll-clk";
+                reg = <0x02620368 4>;
+                reg-names = "control";
+                fixed-postdiv = <6>;
+        };
+
+        armpllclk: armpllclk@2620370 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkmain>;
+                clock-output-names = "arm-pll-clk";
+                reg = <0x02620370 4>;
+                reg-names = "control";
+                fixed-postdiv = <6>;
+        };
+
+        mainmuxclk: mainmuxclk@2310108 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-mux-clock";
+                clocks = <&mainpllclk>, <&refclkmain>;
+                reg = <0x02310108 4>;
+                bit-shift = <23>;
+                bit-mask = <1>;
+                clock-output-names = "mainmuxclk";
+        };
+
+        chipclk1: chipclk1 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&mainmuxclk>;
+                clock-div = <1>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk1";
+        };
+
+        chipclk1rstiso: chipclk1rstiso {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&mainmuxclk>;
+                clock-div = <1>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk1rstiso";
+        };
+
+        gemtraceclk: gemtraceclk@2310120 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-divider-clock";
+                clocks = <&mainmuxclk>;
+                reg = <0x02310120 4>;
+                bit-shift = <0>;
+                bit-mask = <8>;
+                clock-output-names = "gemtraceclk";
+        };
+
+        chipstmxptclk: chipstmxptclk {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-divider-clock";
+                clocks = <&mainmuxclk>;
+                reg = <0x02310164 4>;
+                bit-shift = <0>;
+                bit-mask = <8>;
+                clock-output-names = "chipstmxptclk";
+        };
+
+        chipclk12: chipclk12 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1>;
+                clock-div = <2>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk12";
+        };
+
+        chipclk13: chipclk13 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1>;
+                clock-div = <3>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk13";
+        };
+
+        chipclk14: chipclk14 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1>;
+                clock-div = <4>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk14";
+        };
+
+        chipclk16: chipclk16 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1>;
+                clock-div = <6>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk16";
+        };
+
+        chipclk112: chipclk112 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1>;
+                clock-div = <12>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk112";
+        };
+
+        chipclk124: chipclk124 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1>;
+                clock-div = <24>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk114";
+        };
+
+        chipclk1rstiso13: chipclk1rstiso13 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1rstiso>;
+                clock-div = <3>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk1rstiso13";
+        };
+
+        chipclk1rstiso14: chipclk1rstiso14 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1rstiso>;
+                clock-div = <4>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk1rstiso14";
+        };
+
+        chipclk1rstiso16: chipclk1rstiso16 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1rstiso>;
+                clock-div = <6>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk1rstiso16";
+        };
+
+        chipclk1rstiso112: chipclk1rstiso112 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&chipclk1rstiso>;
+                clock-div = <12>;
+                clock-mult = <1>;
+                clock-output-names = "chipclk1rstiso112";
+        };
+
+        clkmodrst0: clkmodrst0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk16>;
+                clock-output-names = "modrst0";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+
+        clkusb: clkusb {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk16>;
+                clock-output-names = "usb";
+                reg = <0x02350008 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkaemifspi: clkaemifspi {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk16>;
+                clock-output-names = "aemif-spi";
+                reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+
+        clkdebugsstrc: clkdebugsstrc {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "debugss-trc";
+                reg = <0x02350014 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clktetbtrc: clktetbtrc {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tetb-trc";
+                reg = <0x02350018 0xb00>, <0x02350004 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <1>;
+        };
+
+        clkpa: clkpa {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk16>;
+                clock-output-names = "pa";
+                reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <2>;
+        };
+
+        clkcpgmac: clkcpgmac {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkpa>;
+                clock-output-names = "cpgmac";
+                reg = <0x02350020 0xb00>, <0x02350008 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <2>;
+        };
+
+        clksa: clksa {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkpa>;
+                clock-output-names = "sa";
+                reg = <0x02350024 0xb00>, <0x02350008 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <2>;
+        };
+
+        clkpcie: clkpcie {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "pcie";
+                reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <3>;
+        };
+
+        clksrio: clksrio {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1rstiso13>;
+                clock-output-names = "srio";
+                reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <4>;
+        };
+
+        clkhyperlink0: clkhyperlink0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "hyperlink-0";
+                reg = <0x02350030 0xb00>, <0x02350014 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <5>;
+        };
+
+        clksr: clksr {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1rstiso112>;
+                clock-output-names = "sr";
+                reg = <0x02350034 0xb00>, <0x02350018 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <6>;
+        };
+
+        clkmsmcsram: clkmsmcsram {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "msmcsram";
+                reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <7>;
+        };
+
+        clkgem0: clkgem0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem0";
+                reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <8>;
+        };
+
+        clkgem1: clkgem1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem1";
+                reg = <0x02350040 0xb00>, <0x02350024 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <9>;
+        };
+
+        clkgem2: clkgem2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem2";
+                reg = <0x02350044 0xb00>, <0x02350028 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <10>;
+        };
+
+        clkgem3: clkgem3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem3";
+                reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <11>;
+        };
+
+        clkgem4: clkgem4 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem4";
+                reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <12>;
+        };
+
+        clkgem5: clkgem5 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem5";
+                reg = <0x02350050 0xb00>, <0x02350034 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <13>;
+        };
+
+        clkgem6: clkgem6 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem6";
+                reg = <0x02350054 0xb00>, <0x02350038 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <14>;
+        };
+
+        clkgem7: clkgem7 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem7";
+                reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <15>;
+        };
+
+        clkddr30: clkddr30 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "ddr3-0";
+                reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <16>;
+        };
+
+        clkddr31: clkddr31 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "ddr3-1";
+                reg = <0x02350060 0xb00>, <0x02350040 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <16>;
+        };
+
+        clktac: clktac {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tac";
+                reg = <0x02350064 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <17>;
+        };
+
+        clkrac01: clktac01 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "rac-01";
+                reg = <0x02350068 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <17>;
+        };
+
+        clkrac23: clktac23 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "rac-23";
+                reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <18>;
+        };
+
+        clkfftc0: clkfftc0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-0";
+                reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <19>;
+        };
+
+        clkfftc1: clkfftc1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-1";
+                reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <19>;
+        };
+
+        clkfftc2: clkfftc2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-2";
+                reg = <0x02350078 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+
+        clkfftc3: clkfftc3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-3";
+                reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+
+        clkfftc4: clkfftc4 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-4";
+                reg = <0x02350080 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+
+        clkfftc5: clkfftc5 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-5";
+                reg = <0x02350084 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+
+        clkaif: clkaif {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "aif";
+                reg = <0x02350088 0xb00>, <0x02350054 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <21>;
+        };
+
+        clktcp3d0: clktcp3d0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-0";
+                reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <22>;
+        };
+
+        clktcp3d1: clktcp3d1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-1";
+                reg = <0x02350090 0xb00>, <0x02350058 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <22>;
+        };
+
+        clktcp3d2: clktcp3d2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-2";
+                reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <23>;
+        };
+
+        clktcp3d3: clktcp3d3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-3";
+                reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <23>;
+        };
+
+        clkvcp0: clkvcp0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-0";
+                reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+
+        clkvcp1: clkvcp1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-1";
+                reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+
+        clkvcp2: clkvcp2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-2";
+                reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+
+        clkvcp3: clkvcp3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-3";
+                reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+
+        clkvcp4: clkvcp4 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-4";
+                reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+
+        clkvcp5: clkvcp5 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-5";
+                reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+
+        clkvcp6: clkvcp6 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-6";
+                reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+
+        clkvcp7: clkvcp7 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-7";
+                reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+
+        clkbcp: clkbcp {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "bcp";
+                reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <26>;
+        };
+
+        clkdxb: clkdxb {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "dxb";
+                reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <27>;
+        };
+
+        clkhyperlink1: clkhyperlink1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "hyperlink-1";
+                reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <28>;
+        };
+
+        clkxge: clkxge {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "xge";
+                reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <29>;
+        };
+
+        clkwdtimer0: clkwdtimer0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "timer0";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkwdtimer1: clkwdtimer1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "timer1";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkwdtimer2: clkwdtimer2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "timer2";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkwdtimer3: clkwdtimer3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "timer3";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkuart0: clkuart0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "uart0";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkuart1: clkuart1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "uart1";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkaemif: clkaemif {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkaemifspi>;
+                clock-output-names = "aemif";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkusim: clkusim {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "usim";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clki2c: clki2c {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "i2c";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkspi: clkspi {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkaemifspi>;
+                clock-output-names = "spi";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkgpio: clkgpio {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "gpio";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+
+        clkkeymgr: clkkeymgr {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "keymgr";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
index a68e34bbecb2..100bdf52b847 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dts
@@ -100,13 +100,15 @@
                         reg = <0x023100e8 4>;   /* pll reset control reg */
                 };
 
+                /include/ "keystone-clocks.dtsi"
+
                 uart0: serial@02530c00 {
                         compatible = "ns16550a";
                         current-speed = <115200>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         reg = <0x02530c00 0x100>;
-                        clock-frequency = <133120000>;
+                        clocks  = <&clkuart0>;
                         interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
                 };
 
@@ -116,9 +118,66 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         reg = <0x02531000 0x100>;
-                        clock-frequency = <133120000>;
+                        clocks  = <&clkuart1>;
                         interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
                 };
 
+                i2c0: i2c@2530000 {
+                        compatible = "ti,davinci-i2c";
+                        reg = <0x02530000 0x400>;
+                        clock-frequency = <100000>;
+                        clocks = <&clki2c>;
+                        interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        dtt@50 {
+                                compatible = "at,24c1024";
+                                reg = <0x50>;
+                        };
+                };
+
+                i2c1: i2c@2530400 {
+                        compatible = "ti,davinci-i2c";
+                        reg = <0x02530400 0x400>;
+                        clock-frequency = <100000>;
+                        clocks = <&clki2c>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
+                };
+
+                i2c2: i2c@2530800 {
+                        compatible = "ti,davinci-i2c";
+                        reg = <0x02530800 0x400>;
+                        clock-frequency = <100000>;
+                        clocks = <&clki2c>;
+                        interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
+                };
+
+                spi0: spi@21000400 {
+                        compatible = "ti,dm6441-spi";
+                        reg = <0x21000400 0x200>;
+                        num-cs = <4>;
+                        ti,davinci-spi-intr-line = <0>;
+                        interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&clkspi>;
+                };
+
+                spi1: spi@21000600 {
+                        compatible = "ti,dm6441-spi";
+                        reg = <0x21000600 0x200>;
+                        num-cs = <4>;
+                        ti,davinci-spi-intr-line = <0>;
+                        interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&clkspi>;
+                };
+
+                spi2: spi@21000800 {
+                        compatible = "ti,dm6441-spi";
+                        reg = <0x21000800 0x200>;
+                        num-cs = <4>;
+                        ti,davinci-spi-intr-line = <0>;
+                        interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&clkspi>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
new file mode 100644
index 000000000000..46b82aa7dc4e
--- /dev/null
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -0,0 +1,36 @@
+/*
+ * Device Tree Source for the r7s72100 SoC
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+        compatible = "renesas,r7s72100";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+        };
+
+        gic: interrupt-controller@e8201000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0xe8201000 0x1000>,
+                        <0xe8202000 0x1000>;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
new file mode 100644
index 000000000000..bbed43bd9be9
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Device Tree Source for the r8a7791 SoC
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+        compatible = "renesas,r8a7791";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                        clock-frequency = <1300000000>;
+                };
+        };
+
+        gic: interrupt-controller@f1001000 {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0xf1001000 0 0x1000>,
+                        <0 0xf1002000 0 0x1000>,
+                        <0 0xf1004000 0 0x2000>,
+                        <0 0xf1006000 0 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+};
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 6e4931097dd4..287ac1d7aac7 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -25,10 +24,9 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_ERRATA_743622=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -50,7 +48,6 @@ CONFIG_UNIX_DIAG=y
 CONFIG_NET_KEY=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
-CONFIG_ARPD=y
 CONFIG_SYN_COOKIES=y
 CONFIG_TCP_MD5SIG=y
 CONFIG_IPV6=y
@@ -95,7 +92,6 @@ CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_TEST=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -117,12 +113,12 @@ CONFIG_CONFIGFS_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
-CONFIG_DEBUG_INFO=y
 # CONFIG_FTRACE is not set
 CONFIG_CRC_CCITT=y
 CONFIG_CRC_T10DIF=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 5d488c24b132..8d0c5a018ed7 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -132,7 +132,6 @@ CONFIG_TOUCHSCREEN_MC13783=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MMA8450=y
 CONFIG_SERIO_SERPORT=m
-CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_IMX=y
@@ -188,22 +187,33 @@ CONFIG_SND_SOC_PHYCORE_AC97=y
 CONFIG_SND_SOC_EUKREA_TLV320=y
 CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
 CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_PHY=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
 CONFIG_RTC_DRV_MC13XXX=y
@@ -246,7 +256,6 @@ CONFIG_UDF_FS=m
 CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=m
 CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
@@ -261,6 +270,7 @@ CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
+CONFIG_PROVE_LOCKING=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_FTRACE is not set
 # CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index a8314c3ee84d..5bae19557591 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -1,15 +1,17 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
-CONFIG_TINY_RCU=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_INTEGRATOR=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_ARCH_INTEGRATOR_CP=y
+CONFIG_INTEGRATOR_IMPD1=y
 CONFIG_CPU_ARM720T=y
 CONFIG_CPU_ARM920T=y
 CONFIG_CPU_ARM922T=y
@@ -18,12 +20,9 @@ CONFIG_CPU_ARM1020=y
 CONFIG_CPU_ARM1022=y
 CONFIG_CPU_ARM1026=y
 CONFIG_PCI=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
+# CONFIG_ATAGS is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
@@ -44,24 +43,20 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_AFS_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
 CONFIG_E100=y
 CONFIG_SMC91X=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
 CONFIG_FB=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_ARMCLCD=y
@@ -71,19 +66,23 @@ CONFIG_FB_MATROX_MYSTIQUE=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL030=y
+CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_EXT2_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 1f36b823905f..9943e5da74f1 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -123,7 +123,9 @@ CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DAVINCI=y
 CONFIG_SPI=y
+CONFIG_SPI_DAVINCI=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 119fc378fc52..4a5903e04827 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -6,6 +6,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_KEYSTONE=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 4555c025629a..6150108e15de 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -76,7 +76,6 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_TSC2007=m
 # CONFIG_SERIO is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -91,7 +90,6 @@ CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
 CONFIG_SPI_MXS=y
-CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
@@ -115,9 +113,12 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_PHY=y
 CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_MXS=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
new file mode 100644
index 000000000000..d57a85badb5e
--- /dev/null
+++ b/arch/arm/configs/sunxi_defconfig
@@ -0,0 +1,61 @@
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_NETDEVICES=y
+CONFIG_SUN4I_EMAC=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_8250_DW=y
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_SUNXI_WATCHDOG=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_COMMON_CLK_DEBUG=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_NLS=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index f2de51f0bd18..f489fdaa19b8 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
@@ -8,11 +7,9 @@ CONFIG_CGROUPS=y
 CONFIG_CPUSETS=y
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
 # CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_MODULES=y
@@ -23,14 +20,22 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_VEXPRESS_CA9X4=y
+CONFIG_ARCH_VEXPRESS_DCSCB=y
+CONFIG_ARCH_VEXPRESS_TC2_PM=y
 # CONFIG_SWP_EMULATE is not set
 CONFIG_SMP=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_MCPM=y
 CONFIG_VMSPLIT_2G=y
-CONFIG_HOTPLUG_CPU=y
+CONFIG_NR_CPUS=8
+CONFIG_ARM_PSCI=y
 CONFIG_AEABI=y
+CONFIG_CMA=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M"
+CONFIG_CMDLINE="console=ttyAMA0"
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -44,37 +49,46 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ARM_INTEGRATOR=y
-CONFIG_MISC_DEVICES=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_UBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_VIRTIO_BLK=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_SCSI_VIRTIO=y
 CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+CONFIG_VIRTIO_NET=y
+CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C=y
+CONFIG_I2C_VERSATILE=y
+CONFIG_SENSORS_VEXPRESS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_VEXPRESS=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -103,38 +117,45 @@ CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_ISP1760_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
 CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
+CONFIG_9P_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S
new file mode 100644
index 000000000000..ba12cc44b2cb
--- /dev/null
+++ b/arch/arm/include/debug/vf.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =0x40028000        @ physical
+        ldr     \rv, =0xfe028000        @ virtual
+        .endm
+
+        .macro  senduart, rd, rx
+        strb    \rd, [\rx, #0x7]        @ Data Register
+        .endm
+
+        .macro  busyuart, rd, rx
+1001:   ldrb    \rd, [\rx, #0x4]        @ Status Register 1
+        tst     \rd, #1 << 6            @ TC
+        beq     1001b                   @ wait until transmit done
+        .endm
+
+        .macro  waituart,rd,rx
+        .endm
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
index 70ded3fb42d9..570a48cc3d64 100644
--- a/arch/arm/kernel/psci_smp.c
+++ b/arch/arm/kernel/psci_smp.c
@@ -14,7 +14,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/irqchip/arm-gic.h>
 #include <linux/smp.h>
 #include <linux/of.h>
 
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 69d67f714a2f..9fe6d88737ed 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -1,5 +1,16 @@
 config ARCH_BCM
-        bool "Broadcom SoC" if ARCH_MULTI_V7
+        bool "Broadcom SoC Support"
+        depends on ARCH_MULTIPLATFORM
+        help
+          This enables support for Broadcom ARM based SoC
+          chips
+
+if ARCH_BCM
+
+menu "Broadcom SoC Selection"
+
+config ARCH_BCM_MOBILE
+        bool "Broadcom Mobile SoC" if ARCH_MULTI_V7
         depends on MMU
         select ARCH_REQUIRE_GPIOLIB
         select ARM_ERRATA_754322
@@ -9,12 +20,17 @@ config ARCH_BCM
         select CLKSRC_OF
         select GENERIC_CLOCKEVENTS
         select GENERIC_TIME
-        select GPIO_BCM
+        select GPIO_BCM_KONA
         select SPARSE_IRQ
         select TICK_ONESHOT
         select CACHE_L2X0
+        select HAVE_ARM_ARCH_TIMER
         help
-          This enables support for system based on Broadcom SoCs.
+          This enables support for systems based on Broadcom mobile SoCs.
           It currently supports the 'BCM281XX' family, which includes
           BCM11130, BCM11140, BCM11351, BCM28145 and
           BCM28155 variants.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index e3d03033a7e2..c2ccd5a0f772 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,6 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
-obj-$(CONFIG_ARCH_BCM)          := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_bcm_kona_smc_asm.o       :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index 26b2390492b8..cb3dc364405c 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -67,7 +67,7 @@ static void __init board_init(void)
 
 static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, };
 
-DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
+DT_MACHINE_START(BCM11351_DT, "BCM281xx Broadcom Application Processor")
         .init_machine = board_init,
         .restart = bcm_kona_restart,
         .dt_compat = bcm11351_dt_compat,
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index c4bdc0a1c36e..30a44e2df47e 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -74,7 +74,7 @@ static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler)
         if (handler != NULL) {
                 da830_evm_usb_ocic_handler = handler;
 
-                error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED |
+                error = request_irq(irq, da830_evm_usb_ocic_irq,
                                     IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                     "OHCI over-current indicator", NULL);
                 if (error)
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index ab98c75cabb4..e0de2da41b5c 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -211,7 +211,7 @@ static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler)
                 hawk_usb_ocic_handler = handler;
 
                 error = request_irq(irq, omapl138_hawk_usb_ocic_irq,
-                                        IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                                        IRQF_TRIGGER_RISING |
                                         IRQF_TRIGGER_FALLING,
                                         "OHCI over-current indicator", NULL);
                 if (error)
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 7a55b5c95971..56c6eb5266ad 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -181,7 +181,7 @@ static struct timer_s timers[] = {
                 .name      = "clockevent",
                 .opts      = TIMER_OPTS_DISABLED,
                 .irqaction = {
-                        .flags   = IRQF_DISABLED | IRQF_TIMER,
+                        .flags   = IRQF_TIMER,
                         .handler = timer_interrupt,
                 }
         },
@@ -190,7 +190,7 @@ static struct timer_s timers[] = {
                 .period     = ~0,
                 .opts       = TIMER_OPTS_PERIODIC,
                 .irqaction = {
-                        .flags   = IRQF_DISABLED | IRQF_TIMER,
+                        .flags   = IRQF_TIMER,
                         .handler = freerun_interrupt,
                 }
         },
@@ -331,7 +331,6 @@ static void davinci_set_mode(enum clock_event_mode mode,
 
 static struct clock_event_device clockevent_davinci = {
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
         .set_next_event = davinci_set_next_event,
         .set_mode       = davinci_set_mode,
 };
@@ -397,14 +396,10 @@ void __init davinci_timer_init(void)
 
         /* setup clockevent */
         clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
-        clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
-                                         clockevent_davinci.shift);
-        clockevent_davinci.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
-        clockevent_davinci.min_delta_ns = 50000; /* 50 usec */
 
         clockevent_davinci.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_davinci);
+        clockevents_config_and_register(&clockevent_davinci,
+                                        davinci_clock_tick_rate, 1, 0xfffffffe);
 
         for (i=0; i< ARRAY_SIZE(timers); i++)
                 timer32_config(&timers[i]);
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 616408d76be5..fe98df44579c 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -10,6 +10,7 @@ config ARCH_HIGHBANK
         select ARM_ERRATA_775420
         select ARM_ERRATA_798181
         select ARM_GIC
+        select ARM_PSCI
         select ARM_TIMER_SP804
         select CACHE_L2X0
         select COMMON_CLK
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 8a1ef576d79f..55840f414d3e 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -3,6 +3,4 @@ obj-y					:= highbank.o system.o smc.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
 
-obj-$(CONFIG_SMP)                       += platsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_PM_SLEEP)                  += pm.o
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index aea1ec5ab6f8..7ec5edcd1336 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -3,7 +3,6 @@
 
 #include <linux/reboot.h>
 
-extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void highbank_restart(enum reboot_mode, const char *);
 extern void __iomem *scu_base_addr;
 
@@ -14,8 +13,5 @@ static inline void highbank_pm_init(void) {}
 #endif
 
 extern void highbank_smc1(int fn, int arg);
-extern void highbank_cpu_die(unsigned int cpu);
-
-extern struct smp_operations highbank_smp_ops;
 
 #endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index e6d6eacea9d0..b3d7e5634b83 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -24,10 +24,9 @@
 #include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/amba/bus.h>
+#include <linux/platform_device.h>
 
-#include <asm/cacheflush.h>
-#include <asm/cputype.h>
-#include <asm/smp_plat.h>
+#include <asm/psci.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -48,17 +47,6 @@ static void __init highbank_scu_map_io(void)
         scu_base_addr = ioremap(base, SZ_4K);
 }
 
-#define HB_JUMP_TABLE_PHYS(cpu)         (0x40 + (0x10 * (cpu)))
-#define HB_JUMP_TABLE_VIRT(cpu)         phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
-
-void highbank_set_cpu_jump(int cpu, void *jump_addr)
-{
-        cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
-        writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
-        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
-        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
-                          HB_JUMP_TABLE_PHYS(cpu) + 15);
-}
 
 static void highbank_l2x0_disable(void)
 {
@@ -138,6 +126,10 @@ static struct notifier_block highbank_platform_nb = {
         .notifier_call = highbank_platform_notifier,
 };
 
+static struct platform_device highbank_cpuidle_device = {
+        .name = "cpuidle-calxeda",
+};
+
 static void __init highbank_init(void)
 {
         struct device_node *np;
@@ -154,6 +146,9 @@ static void __init highbank_init(void)
         bus_register_notifier(&amba_bustype, &highbank_amba_nb);
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+        if (psci_ops.cpu_suspend)
+                platform_device_register(&highbank_cpuidle_device);
 }
 
 static const char *highbank_match[] __initconst = {
@@ -166,7 +161,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
         .dma_zone_size  = (4ULL * SZ_1G),
 #endif
-        .smp            = smp_ops(highbank_smp_ops),
         .init_irq       = highbank_init_irq,
         .init_machine   = highbank_init,
         .dt_compat      = highbank_match,
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
deleted file mode 100644
index a019e4e86e51..000000000000
--- a/arch/arm/mach-highbank/hotplug.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2011 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/kernel.h>
-#include <asm/cacheflush.h>
-
-#include "core.h"
-#include "sysregs.h"
-
-extern void secondary_startup(void);
-
-/*
- * platform-specific code to shutdown a CPU
- *
- */
-void __ref highbank_cpu_die(unsigned int cpu)
-{
-        highbank_set_cpu_jump(cpu, phys_to_virt(0));
-
-        flush_cache_louis();
-        highbank_set_core_pwr();
-
-        while (1)
-                cpu_do_idle();
-}
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
deleted file mode 100644
index 32d75cf55cbc..000000000000
--- a/arch/arm/mach-highbank/platsmp.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <asm/smp_scu.h>
-
-#include "core.h"
-
-extern void secondary_startup(void);
-
-static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        highbank_set_cpu_jump(cpu, secondary_startup);
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
-        return 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-static void __init highbank_smp_init_cpus(void)
-{
-        unsigned int i, ncores = 4;
-
-        /* sanity check */
-        if (ncores > NR_CPUS) {
-                printk(KERN_WARNING
-                       "highbank: no. of cores (%d) greater than configured "
-                       "maximum of %d - clipping\n",
-                       ncores, NR_CPUS);
-                ncores = NR_CPUS;
-        }
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
-{
-        if (scu_base_addr)
-                scu_enable(scu_base_addr);
-}
-
-struct smp_operations highbank_smp_ops __initdata = {
-        .smp_init_cpus          = highbank_smp_init_cpus,
-        .smp_prepare_cpus       = highbank_smp_prepare_cpus,
-        .smp_boot_secondary     = highbank_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = highbank_cpu_die,
-#endif
-};
diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c
index 04eddb4f4380..7f2bd85eb935 100644
--- a/arch/arm/mach-highbank/pm.c
+++ b/arch/arm/mach-highbank/pm.c
@@ -16,27 +16,19 @@
 
 #include <linux/cpu_pm.h>
 #include <linux/init.h>
-#include <linux/io.h>
 #include <linux/suspend.h>
 
-#include <asm/cacheflush.h>
-#include <asm/proc-fns.h>
 #include <asm/suspend.h>
-
-#include "core.h"
-#include "sysregs.h"
+#include <asm/psci.h>
 
 static int highbank_suspend_finish(unsigned long val)
 {
-        outer_flush_all();
-        outer_disable();
-
-        highbank_set_pwr_suspend();
-
-        cpu_do_idle();
+        const struct psci_power_state ps = {
+                .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+                .affinity_level = 1,
+        };
 
-        highbank_clear_pwr_request();
-        return 0;
+        return psci_ops.cpu_suspend(ps, __pa(cpu_resume));
 }
 
 static int highbank_pm_enter(suspend_state_t state)
@@ -44,15 +36,11 @@ static int highbank_pm_enter(suspend_state_t state)
         cpu_pm_enter();
         cpu_cluster_pm_enter();
 
-        highbank_set_cpu_jump(0, cpu_resume);
         cpu_suspend(0, highbank_suspend_finish);
 
         cpu_cluster_pm_exit();
         cpu_pm_exit();
 
-        highbank_smc1(0x102, 0x1);
-        if (scu_base_addr)
-                scu_enable(scu_base_addr);
         return 0;
 }
 
@@ -63,5 +51,8 @@ static const struct platform_suspend_ops highbank_pm_ops = {
 
 void __init highbank_pm_init(void)
 {
+        if (!psci_ops.cpu_suspend)
+                return;
+
         suspend_set_ops(&highbank_pm_ops);
 }
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a91909b95601..7a6e6f710068 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -11,6 +11,7 @@ config ARCH_MXC
         select GENERIC_IRQ_CHIP
         select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
         select MULTI_IRQ_HANDLER
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -24,7 +25,7 @@ config MXC_IRQ_PRIOR
         help
           Select this if you want to use prioritized IRQ handling.
           This feature prevents higher priority ISR to be interrupted
-          by lower priority IRQ even IRQF_DISABLED flag is not set.
+          by lower priority IRQ.
           This may be useful in embedded applications, where are strong
           requirements for timing.
           Say N here, unless you have a specialized requirement.
@@ -793,6 +794,8 @@ config SOC_IMX6Q
         select HAVE_IMX_SRC
         select HAVE_SMP
         select MFD_SYSCON
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
         select PINCTRL
         select PINCTRL_IMX6Q
         select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5383c589ad71..bbe1f5bb799c 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -102,6 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+# i.MX6SL reuses pm-imx6q.c
+obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o
 endif
 
 # i.MX5 based machines
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index ad3b755abb78..4a40bbb46183 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -16,6 +16,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include "common.h"
+#include "hardware.h"
 
 #define REG_SET         0x4
 #define REG_CLR         0x8
@@ -26,6 +27,7 @@
 #define ANADIG_USB1_CHRG_DETECT 0x1b0
 #define ANADIG_USB2_CHRG_DETECT 0x210
 #define ANADIG_DIGPROG          0x260
+#define ANADIG_DIGPROG_IMX6SL   0x280
 
 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG    0x40000
 #define BM_ANADIG_REG_CORE_FET_ODRIVE           0x20000000
@@ -76,21 +78,38 @@ static void imx_anatop_usb_chrg_detect_disable(void)
                 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
 }
 
-u32 imx_anatop_get_digprog(void)
+void __init imx_init_revision_from_anatop(void)
 {
         struct device_node *np;
         void __iomem *anatop_base;
-        static u32 digprog;
-
-        if (digprog)
-                return digprog;
+        unsigned int revision;
+        u32 digprog;
+        u16 offset = ANADIG_DIGPROG;
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
         anatop_base = of_iomap(np, 0);
         WARN_ON(!anatop_base);
-        digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG);
+        if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
+                offset = ANADIG_DIGPROG_IMX6SL;
+        digprog = readl_relaxed(anatop_base + offset);
+        iounmap(anatop_base);
+
+        switch (digprog & 0xff) {
+        case 0:
+                revision = IMX_CHIP_REVISION_1_0;
+                break;
+        case 1:
+                revision = IMX_CHIP_REVISION_1_1;
+                break;
+        case 2:
+                revision = IMX_CHIP_REVISION_1_2;
+                break;
+        default:
+                revision = IMX_CHIP_REVISION_UNKNOWN;
+        }
 
-        return digprog;
+        mxc_set_cpu_type(digprog >> 16 & 0xff);
+        imx_set_soc_revision(revision);
 }
 
 void __init imx_anatop_init(void)
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index ceaac9cd7b42..ce37af26ff8c 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -14,6 +14,9 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include "crm-regs-imx5.h"
 #include "clk.h"
@@ -472,8 +475,9 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
 
 static void __init mx53_clocks_init(struct device_node *np)
 {
-        int i;
+        int i, irq;
         unsigned long r;
+        void __iomem *base;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
         clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -559,14 +563,17 @@ static void __init mx53_clocks_init(struct device_node *np)
         clk_set_rate(clk[esdhc_a_podf], 200000000);
         clk_set_rate(clk[esdhc_b_podf], 200000000);
 
-        /* System timer */
-        mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
-
         clk_prepare_enable(clk[iim_gate]);
         imx_print_silicon_rev("i.MX53", mx53_revision());
         clk_disable_unprepare(clk[iim_gate]);
 
         r = clk_round_rate(clk[usboh3_per_gate], 54000000);
         clk_set_rate(clk[usboh3_per_gate], r);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
 }
 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 9181a241d3a8..d756d91fd741 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -14,7 +14,6 @@
 #include <linux/types.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
@@ -25,155 +24,6 @@
 #include "common.h"
 #include "hardware.h"
 
-#define CCR                             0x0
-#define BM_CCR_WB_COUNT                 (0x7 << 16)
-#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
-#define BM_CCR_RBC_EN                   (0x1 << 27)
-
-#define CCGR0                           0x68
-#define CCGR1                           0x6c
-#define CCGR2                           0x70
-#define CCGR3                           0x74
-#define CCGR4                           0x78
-#define CCGR5                           0x7c
-#define CCGR6                           0x80
-#define CCGR7                           0x84
-
-#define CLPCR                           0x54
-#define BP_CLPCR_LPM                    0
-#define BM_CLPCR_LPM                    (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
-#define BM_CLPCR_SBYOS                  (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
-#define BM_CLPCR_VSTBY                  (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT             9
-#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
-
-#define CGPR                            0x64
-#define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
-
-static void __iomem *ccm_base;
-
-void imx6q_set_chicken_bit(void)
-{
-        u32 val = readl_relaxed(ccm_base + CGPR);
-
-        val |= BM_CGPR_CHICKEN_BIT;
-        writel_relaxed(val, ccm_base + CGPR);
-}
-
-static void imx6q_enable_rbc(bool enable)
-{
-        u32 val;
-        static bool last_rbc_mode;
-
-        if (last_rbc_mode == enable)
-                return;
-        /*
-         * need to mask all interrupts in GPC before
-         * operating RBC configurations
-         */
-        imx_gpc_mask_all();
-
-        /* configure RBC enable bit */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_EN;
-        val |= enable ? BM_CCR_RBC_EN : 0;
-        writel_relaxed(val, ccm_base + CCR);
-
-        /* configure RBC count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_BYPASS_COUNT;
-        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
-        writel(val, ccm_base + CCR);
-
-        /*
-         * need to delay at least 2 cycles of CKIL(32K)
-         * due to hardware design requirement, which is
-         * ~61us, here we use 65us for safe
-         */
-        udelay(65);
-
-        /* restore GPC interrupt mask settings */
-        imx_gpc_restore_all();
-
-        last_rbc_mode = enable;
-}
-
-static void imx6q_enable_wb(bool enable)
-{
-        u32 val;
-        static bool last_wb_mode;
-
-        if (last_wb_mode == enable)
-                return;
-
-        /* configure well bias enable bit */
-        val = readl_relaxed(ccm_base + CLPCR);
-        val &= ~BM_CLPCR_WB_PER_AT_LPM;
-        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
-        writel_relaxed(val, ccm_base + CLPCR);
-
-        /* configure well bias count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_WB_COUNT;
-        val |= enable ? BM_CCR_WB_COUNT : 0;
-        writel_relaxed(val, ccm_base + CCR);
-
-        last_wb_mode = enable;
-}
-
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-        u32 val = readl_relaxed(ccm_base + CLPCR);
-
-        val &= ~BM_CLPCR_LPM;
-        switch (mode) {
-        case WAIT_CLOCKED:
-                imx6q_enable_wb(false);
-                imx6q_enable_rbc(false);
-                break;
-        case WAIT_UNCLOCKED:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
-                break;
-        case STOP_POWER_ON:
-                val |= 0x2 << BP_CLPCR_LPM;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val &= ~BM_CLPCR_VSTBY;
-                val &= ~BM_CLPCR_SBYOS;
-                break;
-        case STOP_POWER_OFF:
-                val |= 0x2 << BP_CLPCR_LPM;
-                val |= 0x3 << BP_CLPCR_STBY_COUNT;
-                val |= BM_CLPCR_VSTBY;
-                val |= BM_CLPCR_SBYOS;
-                imx6q_enable_wb(true);
-                imx6q_enable_rbc(true);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        writel_relaxed(val, ccm_base + CLPCR);
-
-        return 0;
-}
-
 static const char *step_sels[]  = { "osc", "pll2_pfd2_396m", };
 static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
 static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
@@ -182,7 +32,7 @@ static const char *periph2_clk2_sels[]	= { "pll3_usb_otg", "pll2_bus", };
 static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
 static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
 static const char *axi_sels[]           = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
-static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
+static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
 static const char *gpu_axi_sels[]       = { "axi", "ahb", };
 static const char *gpu2d_core_sels[]    = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
 static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
@@ -196,7 +46,7 @@ static const char *ipu2_di0_sels[]	= { "ipu2_di0_pre", "dummy", "dummy", "ldb_di
 static const char *ipu2_di1_sels[]      = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *hsi_tx_sels[]        = { "pll3_120m", "pll2_pfd2_396m", };
 static const char *pcie_axi_sels[]      = { "axi", "ahb", };
-static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
+static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *enfc_sels[]  = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
 static const char *emi_sels[]           = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
@@ -205,7 +55,7 @@ static const char *vdo_axi_sels[]	= { "axi", "ahb", };
 static const char *vpu_axi_sels[]       = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
                                     "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
-                                    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
+                                    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
 static const char *cko2_sels[] = {
         "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
         "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
@@ -217,6 +67,11 @@ static const char *cko2_sels[] = {
         "uart_serial", "spdif", "asrc", "hsi_tx",
 };
 static const char *cko_sels[] = { "cko1", "cko2", };
+static const char *lvds_sels[] = {
+        "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
+        "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
+        "pcie_ref", "sata_ref",
+};
 
 enum mx6q_clks {
         dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
@@ -251,7 +106,8 @@ enum mx6q_clks {
         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
         sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
         usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
-        spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max
+        spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
+        lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -300,7 +156,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         WARN_ON(!base);
 
         /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
-        if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
+        if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
                 post_div_table[1].div = 1;
                 post_div_table[2].div = 1;
                 video_div_table[1].div = 1;
@@ -342,6 +198,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
                         &imx_ccm_lock);
 
+        clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+        clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+
+        /*
+         * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
+         * independently configured as clock inputs or outputs.  We treat
+         * the "output_enable" bit as a gate, even though it's really just
+         * enabling clock output.
+         */
+        clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
+        clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
+
         /*                                name              parent_name        reg       idx */
         clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
         clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
@@ -359,13 +227,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
 
         clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
         clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
         clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
         np = ccm_node;
         base = of_iomap(np, 0);
         WARN_ON(!base);
-        ccm_base = base;
+
+        imx6q_pm_set_ccm_base(base);
 
         /*                                  name                reg       shift width parent_names     num_parents */
         clk[step]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
@@ -573,7 +443,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
         clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
 
-        if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
+        if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
+            cpu_is_imx6dl()) {
                 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
                 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
         }
@@ -603,8 +474,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         if (ret)
                 pr_warn("failed to set up CLKO: %d\n", ret);
 
-        /* Set initial power mode */
-        imx6q_set_lpm(WAIT_CLOCKED);
+        /* All existing boards with PCIe use LVDS1 */
+        if (IS_ENABLED(CONFIG_PCI_IMX6))
+                clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
         base = of_iomap(np, 0);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index a5c3c5d21aee..c0c4ef55e35b 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -127,6 +127,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         base = of_iomap(np, 0);
         WARN_ON(!base);
 
+        /* Reuse imx6q pm code */
+        imx6q_pm_set_ccm_base(base);
+
         /*                                              name                reg       shift width parent_names     num_parents */
         clks[IMX6SL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
         clks[IMX6SL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 28e8ca0871e8..7cbe22d0c6e9 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -13,70 +13,73 @@
 
 #include <linux/reboot.h>
 
+struct irq_data;
 struct platform_device;
 struct pt_regs;
 struct clk;
 enum mxc_cpu_pwr_mode;
 
-extern void mx1_map_io(void);
-extern void mx21_map_io(void);
-extern void mx25_map_io(void);
-extern void mx27_map_io(void);
-extern void mx31_map_io(void);
-extern void mx35_map_io(void);
-extern void mx51_map_io(void);
-extern void mx53_map_io(void);
-extern void imx1_init_early(void);
-extern void imx21_init_early(void);
-extern void imx25_init_early(void);
-extern void imx27_init_early(void);
-extern void imx31_init_early(void);
-extern void imx35_init_early(void);
-extern void imx51_init_early(void);
-extern void imx53_init_early(void);
-extern void mxc_init_irq(void __iomem *);
-extern void tzic_init_irq(void __iomem *);
-extern void mx1_init_irq(void);
-extern void mx21_init_irq(void);
-extern void mx25_init_irq(void);
-extern void mx27_init_irq(void);
-extern void mx31_init_irq(void);
-extern void mx35_init_irq(void);
-extern void mx51_init_irq(void);
-extern void mx53_init_irq(void);
-extern void imx1_soc_init(void);
-extern void imx21_soc_init(void);
-extern void imx25_soc_init(void);
-extern void imx27_soc_init(void);
-extern void imx31_soc_init(void);
-extern void imx35_soc_init(void);
-extern void imx51_soc_init(void);
-extern void imx51_init_late(void);
-extern void imx53_init_late(void);
-extern void epit_timer_init(void __iomem *base, int irq);
-extern void mxc_timer_init(void __iomem *, int);
-extern int mx1_clocks_init(unsigned long fref);
-extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
-extern int mx25_clocks_init(void);
-extern int mx27_clocks_init(unsigned long fref);
-extern int mx31_clocks_init(unsigned long fref);
-extern int mx35_clocks_init(void);
-extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
+void mx1_map_io(void);
+void mx21_map_io(void);
+void mx25_map_io(void);
+void mx27_map_io(void);
+void mx31_map_io(void);
+void mx35_map_io(void);
+void mx51_map_io(void);
+void mx53_map_io(void);
+void imx1_init_early(void);
+void imx21_init_early(void);
+void imx25_init_early(void);
+void imx27_init_early(void);
+void imx31_init_early(void);
+void imx35_init_early(void);
+void imx51_init_early(void);
+void imx53_init_early(void);
+void mxc_init_irq(void __iomem *);
+void tzic_init_irq(void __iomem *);
+void mx1_init_irq(void);
+void mx21_init_irq(void);
+void mx25_init_irq(void);
+void mx27_init_irq(void);
+void mx31_init_irq(void);
+void mx35_init_irq(void);
+void mx51_init_irq(void);
+void mx53_init_irq(void);
+void imx1_soc_init(void);
+void imx21_soc_init(void);
+void imx25_soc_init(void);
+void imx27_soc_init(void);
+void imx31_soc_init(void);
+void imx35_soc_init(void);
+void imx51_soc_init(void);
+void imx51_init_late(void);
+void imx53_init_late(void);
+void epit_timer_init(void __iomem *base, int irq);
+void mxc_timer_init(void __iomem *, int);
+int mx1_clocks_init(unsigned long fref);
+int mx21_clocks_init(unsigned long lref, unsigned long fref);
+int mx25_clocks_init(void);
+int mx27_clocks_init(unsigned long fref);
+int mx31_clocks_init(unsigned long fref);
+int mx35_clocks_init(void);
+int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
-extern int mx25_clocks_init_dt(void);
-extern int mx27_clocks_init_dt(void);
-extern int mx31_clocks_init_dt(void);
-extern struct platform_device *mxc_register_gpio(char *name, int id,
+int mx25_clocks_init_dt(void);
+int mx27_clocks_init_dt(void);
+int mx31_clocks_init_dt(void);
+struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
-extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(enum reboot_mode, const char *);
-extern void mxc_arch_reset_init(void __iomem *);
-extern void mxc_arch_reset_init_dt(void);
-extern int mx53_revision(void);
-extern int imx6q_revision(void);
-extern int mx53_display_revision(void);
-extern void imx_set_aips(void __iomem *);
-extern int mxc_device_init(void);
+void mxc_set_cpu_type(unsigned int type);
+void mxc_restart(enum reboot_mode, const char *);
+void mxc_arch_reset_init(void __iomem *);
+void mxc_arch_reset_init_dt(void);
+int mx53_revision(void);
+void imx_set_aips(void __iomem *);
+int mxc_device_init(void);
+void imx_set_soc_revision(unsigned int rev);
+unsigned int imx_get_soc_revision(void);
+void imx_init_revision_from_anatop(void);
+struct device *imx_soc_device_init(void);
 
 enum mxc_cpu_pwr_mode {
         WAIT_CLOCKED,           /* wfi only */
@@ -93,8 +96,8 @@ enum mx3_cpu_pwr_mode {
         MX3_SLEEP,
 };
 
-extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
-extern void imx_print_silicon_rev(const char *cpu, int srev);
+void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
+void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
@@ -108,54 +111,61 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
 
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
-extern u32 imx_get_cpu_arg(int cpu);
-extern void imx_set_cpu_arg(int cpu, u32 arg);
-extern void v7_cpu_resume(void);
+void imx_enable_cpu(int cpu, bool enable);
+void imx_set_cpu_jump(int cpu, void *jump_addr);
+u32 imx_get_cpu_arg(int cpu);
+void imx_set_cpu_arg(int cpu, u32 arg);
+void v7_cpu_resume(void);
 #ifdef CONFIG_SMP
-extern void v7_secondary_startup(void);
-extern void imx_scu_map_io(void);
-extern void imx_smp_prepare(void);
-extern void imx_scu_standby_enable(void);
+void v7_secondary_startup(void);
+void imx_scu_map_io(void);
+void imx_smp_prepare(void);
+void imx_scu_standby_enable(void);
 #else
 static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 static inline void imx_scu_standby_enable(void) {}
 #endif
-extern void imx_src_init(void);
-extern void imx_src_prepare_restart(void);
-extern void imx_gpc_init(void);
-extern void imx_gpc_pre_suspend(void);
-extern void imx_gpc_post_resume(void);
-extern void imx_gpc_mask_all(void);
-extern void imx_gpc_restore_all(void);
-extern void imx_anatop_init(void);
-extern void imx_anatop_pre_suspend(void);
-extern void imx_anatop_post_resume(void);
-extern u32 imx_anatop_get_digprog(void);
-extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-extern void imx6q_set_chicken_bit(void);
-
-extern void imx_cpu_die(unsigned int cpu);
-extern int imx_cpu_kill(unsigned int cpu);
+void imx_src_init(void);
+#ifdef CONFIG_HAVE_IMX_SRC
+void imx_src_prepare_restart(void);
+#else
+static inline void imx_src_prepare_restart(void) {}
+#endif
+void imx_gpc_init(void);
+void imx_gpc_pre_suspend(void);
+void imx_gpc_post_resume(void);
+void imx_gpc_mask_all(void);
+void imx_gpc_restore_all(void);
+void imx_gpc_irq_mask(struct irq_data *d);
+void imx_gpc_irq_unmask(struct irq_data *d);
+void imx_anatop_init(void);
+void imx_anatop_pre_suspend(void);
+void imx_anatop_post_resume(void);
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+void imx6q_set_chicken_bit(void);
+
+void imx_cpu_die(unsigned int cpu);
+int imx_cpu_kill(unsigned int cpu);
 
 #ifdef CONFIG_PM
-extern void imx6q_pm_init(void);
-extern void imx5_pm_init(void);
+void imx6q_pm_init(void);
+void imx6q_pm_set_ccm_base(void __iomem *base);
+void imx5_pm_init(void);
 #else
 static inline void imx6q_pm_init(void) {}
+static inline void imx6q_pm_set_ccm_base(void __iomem *base) {}
 static inline void imx5_pm_init(void) {}
 #endif
 
 #ifdef CONFIG_NEON
-extern int mx51_neon_fixup(void);
+int mx51_neon_fixup(void);
 #else
 static inline int mx51_neon_fixup(void) { return 0; }
 #endif
 
 #ifdef CONFIG_CACHE_L2X0
-extern void imx_init_l2cache(void);
+void imx_init_l2cache(void);
 #else
 static inline void imx_init_l2cache(void) {}
 #endif
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index e70e3acbf9bd..ba3b498a67ec 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -1,6 +1,9 @@
-
+#include <linux/err.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 
 #include "hardware.h"
 #include "common.h"
@@ -8,11 +11,23 @@
 unsigned int __mxc_cpu_type;
 EXPORT_SYMBOL(__mxc_cpu_type);
 
+static unsigned int imx_soc_revision;
+
 void mxc_set_cpu_type(unsigned int type)
 {
         __mxc_cpu_type = type;
 }
 
+void imx_set_soc_revision(unsigned int rev)
+{
+        imx_soc_revision = rev;
+}
+
+unsigned int imx_get_soc_revision(void)
+{
+        return imx_soc_revision;
+}
+
 void imx_print_silicon_rev(const char *cpu, int srev)
 {
         if (srev == IMX_CHIP_REVISION_UNKNOWN)
@@ -44,3 +59,81 @@ void __init imx_set_aips(void __iomem *base)
         reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
         __raw_writel(reg, base + 0x50);
 }
+
+struct device * __init imx_soc_device_init(void)
+{
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device_node *root;
+        const char *soc_id;
+        int ret;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return NULL;
+
+        soc_dev_attr->family = "Freescale i.MX";
+
+        root = of_find_node_by_path("/");
+        ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+        of_node_put(root);
+        if (ret)
+                goto free_soc;
+
+        switch (__mxc_cpu_type) {
+        case MXC_CPU_MX1:
+                soc_id = "i.MX1";
+                break;
+        case MXC_CPU_MX21:
+                soc_id = "i.MX21";
+                break;
+        case MXC_CPU_MX25:
+                soc_id = "i.MX25";
+                break;
+        case MXC_CPU_MX27:
+                soc_id = "i.MX27";
+                break;
+        case MXC_CPU_MX31:
+                soc_id = "i.MX31";
+                break;
+        case MXC_CPU_MX35:
+                soc_id = "i.MX35";
+                break;
+        case MXC_CPU_MX51:
+                soc_id = "i.MX51";
+                break;
+        case MXC_CPU_MX53:
+                soc_id = "i.MX53";
+                break;
+        case MXC_CPU_IMX6SL:
+                soc_id = "i.MX6SL";
+                break;
+        case MXC_CPU_IMX6DL:
+                soc_id = "i.MX6DL";
+                break;
+        case MXC_CPU_IMX6Q:
+                soc_id = "i.MX6Q";
+                break;
+        default:
+                soc_id = "Unknown";
+        }
+        soc_dev_attr->soc_id = soc_id;
+
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
+                                           (imx_soc_revision >> 4) & 0xf,
+                                           imx_soc_revision & 0xf);
+        if (!soc_dev_attr->revision)
+                goto free_soc;
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev))
+                goto free_rev;
+
+        return soc_device_to_device(soc_dev);
+
+free_rev:
+        kfree(soc_dev_attr->revision);
+free_soc:
+        kfree(soc_dev_attr);
+        return NULL;
+}
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
index e02de188ae83..074b1a81ba76 100644
--- a/arch/arm/mach-imx/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -171,7 +171,7 @@ static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction epit_timer_irq = {
         .name           = "i.MX EPIT Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = epit_timer_interrupt,
 };
 
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 44a65e9ff1fc..586e0171a652 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -90,7 +90,7 @@ void imx_gpc_restore_all(void)
                 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
 }
 
-static void imx_gpc_irq_unmask(struct irq_data *d)
+void imx_gpc_irq_unmask(struct irq_data *d)
 {
         void __iomem *reg;
         u32 val;
@@ -105,7 +105,7 @@ static void imx_gpc_irq_unmask(struct irq_data *d)
         writel_relaxed(val, reg);
 }
 
-static void imx_gpc_irq_mask(struct irq_data *d)
+void imx_gpc_irq_mask(struct irq_data *d)
 {
         void __iomem *reg;
         u32 val;
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 3daf1ed90579..b35e99cc5e5b 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -52,7 +52,9 @@ void imx_cpu_die(unsigned int cpu)
          * the register being cleared to kill the cpu.
          */
         imx_set_cpu_arg(cpu, ~0);
-        cpu_do_idle();
+
+        while (1)
+                cpu_do_idle();
 }
 
 int imx_cpu_kill(unsigned int cpu)
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 368a6e3f5926..58b864a3fc20 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -404,8 +404,7 @@ static int armadillo5x0_sdhc1_init(struct device *dev,
 
         /* When supported the trigger type have to be BOTH */
         ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
-                          detect_irq,
-                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          detect_irq, IRQF_TRIGGER_FALLING,
                           "sdhc-detect", data);
 
         if (ret)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 3be0fa0e9796..0f9f24116daa 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -13,7 +13,6 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/cpu.h>
-#include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -38,64 +37,6 @@
 #include "cpuidle.h"
 #include "hardware.h"
 
-static u32 chip_revision;
-
-int imx6q_revision(void)
-{
-        return chip_revision;
-}
-
-static void __init imx6q_init_revision(void)
-{
-        u32 rev = imx_anatop_get_digprog();
-
-        switch (rev & 0xff) {
-        case 0:
-                chip_revision = IMX_CHIP_REVISION_1_0;
-                break;
-        case 1:
-                chip_revision = IMX_CHIP_REVISION_1_1;
-                break;
-        case 2:
-                chip_revision = IMX_CHIP_REVISION_1_2;
-                break;
-        default:
-                chip_revision = IMX_CHIP_REVISION_UNKNOWN;
-        }
-
-        mxc_set_cpu_type(rev >> 16 & 0xff);
-}
-
-static void imx6q_restart(enum reboot_mode mode, const char *cmd)
-{
-        struct device_node *np;
-        void __iomem *wdog_base;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
-        wdog_base = of_iomap(np, 0);
-        if (!wdog_base)
-                goto soft;
-
-        imx_src_prepare_restart();
-
-        /* enable wdog */
-        writew_relaxed(1 << 2, wdog_base);
-        /* write twice to ensure the request will not get ignored */
-        writew_relaxed(1 << 2, wdog_base);
-
-        /* wait for reset to assert ... */
-        mdelay(500);
-
-        pr_err("Watchdog reset failed to assert reset\n");
-
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-
-soft:
-        /* we'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
-
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
@@ -190,12 +131,20 @@ static void __init imx6q_1588_init(void)
 
 static void __init imx6q_init_machine(void)
 {
+        struct device *parent;
+
         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
-                              imx6q_revision());
+                              imx_get_soc_revision());
+
+        mxc_arch_reset_init_dt();
+
+        parent = imx_soc_device_init();
+        if (parent == NULL)
+                pr_warn("failed to initialize soc device\n");
 
         imx6q_enet_phy_init();
 
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 
         imx_anatop_init();
         imx6q_pm_init();
@@ -270,7 +219,7 @@ static void __init imx6q_init_late(void)
          * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
          * to run cpuidle on them.
          */
-        if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
+        if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
                 imx6q_cpuidle_init();
 
         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
@@ -287,7 +236,7 @@ static void __init imx6q_map_io(void)
 
 static void __init imx6q_init_irq(void)
 {
-        imx6q_init_revision();
+        imx_init_revision_from_anatop();
         imx_init_l2cache();
         imx_src_init();
         imx_gpc_init();
@@ -307,5 +256,5 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
         .init_machine   = imx6q_init_machine,
         .init_late      = imx6q_init_late,
         .dt_compat      = imx6q_dt_compat,
-        .restart        = imx6q_restart,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index c70bd7c64974..2f952e3fcf89 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -10,20 +10,51 @@
 #include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/regmap.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
 
+static void __init imx6sl_fec_init(void)
+{
+        struct regmap *gpr;
+
+        /* set FEC clock from internal PLL clock source */
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr");
+        if (!IS_ERR(gpr)) {
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                        IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0);
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                        IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0);
+        } else {
+                pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
+        }
+}
+
 static void __init imx6sl_init_machine(void)
 {
+        struct device *parent;
+
         mxc_arch_reset_init_dt();
 
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        parent = imx_soc_device_init();
+        if (parent == NULL)
+                pr_warn("failed to initialize soc device\n");
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
+
+        imx6sl_fec_init();
+        imx_anatop_init();
+        /* Reuse imx6q pm code */
+        imx6q_pm_init();
 }
 
 static void __init imx6sl_init_irq(void)
 {
+        imx_init_revision_from_anatop();
         imx_init_l2cache();
         imx_src_init();
         imx_gpc_init();
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 1ed916175d41..50044a21b388 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -311,7 +311,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
         }
 
         ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
-                          detect_irq, IRQF_DISABLED |
+                          detect_irq,
                           IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
                           "sdhc1-detect", data);
         if (ret) {
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index bc0261e99d39..45303bd62902 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -371,8 +371,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 #endif
 
         ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
-                        IRQF_DISABLED | IRQF_TRIGGER_FALLING,
-                                "sdhc-detect", data);
+                        IRQF_TRIGGER_FALLING, "sdhc-detect", data);
         if (ret)
                 goto err_gpio_free_2;
 
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index eb3cce38c70d..d1d52600f458 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/map.h>
 
@@ -88,8 +89,15 @@ void __init imx51_init_early(void)
 
 void __init imx53_init_early(void)
 {
+        struct device_node *np;
+        void __iomem *base;
+
         mxc_set_cpu_type(MXC_CPU_MX53);
-        mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        mxc_iomux_v3_init(base);
         imx_src_init();
 }
 
@@ -100,7 +108,14 @@ void __init mx51_init_irq(void)
 
 void __init mx53_init_irq(void)
 {
-        tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
+        struct device_node *np;
+        void __iomem *base;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+
+        tzic_init_irq(base);
 }
 
 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index d4361b80c5fb..649fe49ce85e 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -130,8 +130,7 @@ static int mxc_mmc1_init(struct device *dev,
         gpio_direction_input(gpio_wp);
 
         ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
-                          detect_irq,
-                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          detect_irq, IRQF_TRIGGER_FALLING,
                           "MMC detect", data);
         if (ret)
                 goto exit_free_wp;
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 8629e5be7ecd..b08ab3ad4a6d 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -34,6 +34,7 @@
 #define MXC_CPU_MX35            35
 #define MXC_CPU_MX51            51
 #define MXC_CPU_MX53            53
+#define MXC_CPU_IMX6SL          0x60
 #define MXC_CPU_IMX6DL          0x61
 #define MXC_CPU_IMX6Q           0x63
 
@@ -152,6 +153,11 @@ extern unsigned int __mxc_cpu_type;
 #endif
 
 #ifndef __ASSEMBLY__
+static inline bool cpu_is_imx6sl(void)
+{
+        return __mxc_cpu_type == MXC_CPU_IMX6SL;
+}
+
 static inline bool cpu_is_imx6dl(void)
 {
         return __mxc_cpu_type == MXC_CPU_IMX6DL;
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 204942749e21..aecd9f8037e0 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -10,9 +10,15 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
 #include <linux/suspend.h>
 #include <asm/cacheflush.h>
 #include <asm/proc-fns.h>
@@ -22,6 +28,147 @@
 #include "common.h"
 #include "hardware.h"
 
+#define CCR                             0x0
+#define BM_CCR_WB_COUNT                 (0x7 << 16)
+#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
+#define BM_CCR_RBC_EN                   (0x1 << 27)
+
+#define CLPCR                           0x54
+#define BP_CLPCR_LPM                    0
+#define BM_CLPCR_LPM                    (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
+#define BM_CLPCR_SBYOS                  (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
+#define BM_CLPCR_VSTBY                  (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT             9
+#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+
+#define CGPR                            0x64
+#define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
+
+static void __iomem *ccm_base;
+
+void imx6q_set_chicken_bit(void)
+{
+        u32 val = readl_relaxed(ccm_base + CGPR);
+
+        val |= BM_CGPR_CHICKEN_BIT;
+        writel_relaxed(val, ccm_base + CGPR);
+}
+
+static void imx6q_enable_rbc(bool enable)
+{
+        u32 val;
+
+        /*
+         * need to mask all interrupts in GPC before
+         * operating RBC configurations
+         */
+        imx_gpc_mask_all();
+
+        /* configure RBC enable bit */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_EN;
+        val |= enable ? BM_CCR_RBC_EN : 0;
+        writel_relaxed(val, ccm_base + CCR);
+
+        /* configure RBC count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_BYPASS_COUNT;
+        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+        writel(val, ccm_base + CCR);
+
+        /*
+         * need to delay at least 2 cycles of CKIL(32K)
+         * due to hardware design requirement, which is
+         * ~61us, here we use 65us for safe
+         */
+        udelay(65);
+
+        /* restore GPC interrupt mask settings */
+        imx_gpc_restore_all();
+}
+
+static void imx6q_enable_wb(bool enable)
+{
+        u32 val;
+
+        /* configure well bias enable bit */
+        val = readl_relaxed(ccm_base + CLPCR);
+        val &= ~BM_CLPCR_WB_PER_AT_LPM;
+        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+        writel_relaxed(val, ccm_base + CLPCR);
+
+        /* configure well bias count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_WB_COUNT;
+        val |= enable ? BM_CCR_WB_COUNT : 0;
+        writel_relaxed(val, ccm_base + CCR);
+}
+
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+        struct irq_desc *iomuxc_irq_desc;
+        u32 val = readl_relaxed(ccm_base + CLPCR);
+
+        val &= ~BM_CLPCR_LPM;
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+                break;
+        case STOP_POWER_ON:
+                val |= 0x2 << BP_CLPCR_LPM;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                break;
+        case STOP_POWER_OFF:
+                val |= 0x2 << BP_CLPCR_LPM;
+                val |= 0x3 << BP_CLPCR_STBY_COUNT;
+                val |= BM_CLPCR_VSTBY;
+                val |= BM_CLPCR_SBYOS;
+                if (cpu_is_imx6sl()) {
+                        val |= BM_CLPCR_BYPASS_PMIC_READY;
+                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+                } else {
+                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /*
+         * Unmask the always pending IOMUXC interrupt #32 as wakeup source to
+         * deassert dsm_request signal, so that we can ensure dsm_request
+         * is not asserted when we're going to write CLPCR register to set LPM.
+         * After setting up LPM bits, we need to mask this wakeup source.
+         */
+        iomuxc_irq_desc = irq_to_desc(32);
+        imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
+        writel_relaxed(val, ccm_base + CLPCR);
+        imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
+
+        return 0;
+}
+
 static int imx6q_suspend_finish(unsigned long val)
 {
         cpu_do_idle();
@@ -33,14 +180,19 @@ static int imx6q_pm_enter(suspend_state_t state)
         switch (state) {
         case PM_SUSPEND_MEM:
                 imx6q_set_lpm(STOP_POWER_OFF);
+                imx6q_enable_wb(true);
+                imx6q_enable_rbc(true);
                 imx_gpc_pre_suspend();
                 imx_anatop_pre_suspend();
                 imx_set_cpu_jump(0, v7_cpu_resume);
                 /* Zzz ... */
                 cpu_suspend(0, imx6q_suspend_finish);
-                imx_smp_prepare();
+                if (cpu_is_imx6q() || cpu_is_imx6dl())
+                        imx_smp_prepare();
                 imx_anatop_post_resume();
                 imx_gpc_post_resume();
+                imx6q_enable_rbc(false);
+                imx6q_enable_wb(false);
                 imx6q_set_lpm(WAIT_CLOCKED);
                 break;
         default:
@@ -55,7 +207,29 @@ static const struct platform_suspend_ops imx6q_pm_ops = {
         .valid = suspend_valid_only_mem,
 };
 
+void __init imx6q_pm_set_ccm_base(void __iomem *base)
+{
+        ccm_base = base;
+}
+
 void __init imx6q_pm_init(void)
 {
+        struct regmap *gpr;
+
+        WARN_ON(!ccm_base);
+
+        /*
+         * Force IOMUXC irq pending, so that the interrupt to GPC can be
+         * used to deassert dsm_request signal when the signal gets
+         * asserted unexpectedly.
+         */
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr))
+                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
+                                   IMX6Q_GPR1_GINT);
+
+        /* Set initial power mode */
+        imx6q_set_lpm(WAIT_CLOCKED);
+
         suspend_set_ops(&imx6q_pm_ops);
 }
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 10a6b1a8c5ac..4754373e7e7d 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -91,6 +91,7 @@ void imx_enable_cpu(int cpu, bool enable)
         spin_lock(&scr_lock);
         val = readl_relaxed(src_base + SRC_SCR);
         val = enable ? val | mask : val & ~mask;
+        val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
         writel_relaxed(val, src_base + SRC_SCR);
         spin_unlock(&scr_lock);
 }
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 80c177c36c5f..e6edcd38b282 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -42,6 +42,9 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
+        if (cpu_is_imx6q() || cpu_is_imx6dl())
+                imx_src_prepare_restart();
+
         if (wdog_clk)
                 clk_enable(wdog_clk);
 
@@ -52,6 +55,8 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
 
         /* Assert SRS signal */
         __raw_writew(wcr_enable, wdog_base);
+        /* write twice to ensure the request will not get ignored */
+        __raw_writew(wcr_enable, wdog_base);
 
         /* wait for reset to assert... */
         mdelay(500);
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index cd46529e9eaa..9b6638aadeaa 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -250,7 +250,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction mxc_timer_irq = {
         .name           = "i.MX Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = mxc_timer_interrupt,
 };
 
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/cm.h
index 202e6a57f100..4ecff7bff482 100644
--- a/arch/arm/mach-integrator/include/mach/cm.h
+++ b/arch/arm/mach-integrator/cm.h
@@ -1,9 +1,12 @@
 /*
- * update the core module control register.
+ * access the core module control register.
  */
+u32 cm_get(void);
 void cm_control(u32, u32);
 
-#define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL)
+struct device_node;
+void cm_init(void);
+void cm_clear_irqs(void);
 
 #define CM_CTRL_LED                     (1 << 0)
 #define CM_CTRL_nMBDET                  (1 << 1)
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 4cdfd7365925..00ddf20ed91b 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -22,77 +22,30 @@
 #include <linux/amba/serial.h>
 #include <linux/io.h>
 #include <linux/stat.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <mach/cm.h>
-#include <mach/irqs.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
 
+#include "cm.h"
 #include "common.h"
 
-#ifdef CONFIG_ATAGS
-
-#define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
-#define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
-#define INTEGRATOR_UART1_IRQ    { IRQ_UARTINT1 }
-#define KMI0_IRQ                { IRQ_KMIINT0 }
-#define KMI1_IRQ                { IRQ_KMIINT1 }
-
-static AMBA_APB_DEVICE(rtc, "rtc", 0,
-        INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
-
-static AMBA_APB_DEVICE(uart0, "uart0", 0,
-        INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL);
-
-static AMBA_APB_DEVICE(uart1, "uart1", 0,
-        INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL);
-
-static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
-static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
-
-static struct amba_device *amba_devs[] __initdata = {
-        &rtc_device,
-        &uart0_device,
-        &uart1_device,
-        &kmi0_device,
-        &kmi1_device,
-};
+static DEFINE_RAW_SPINLOCK(cm_lock);
+static void __iomem *cm_base;
 
-int __init integrator_init(bool is_cp)
+/**
+ * cm_get - get the value from the CM_CTRL register
+ */
+u32 cm_get(void)
 {
-        int i;
-
-        /*
-         * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
-         * hard-code them. The Integator/CP and forward have proper cell IDs.
-         * Else we leave them undefined to the bus driver can autoprobe them.
-         */
-        if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) {
-                rtc_device.periphid     = 0x00041030;
-                uart0_device.periphid   = 0x00041010;
-                uart1_device.periphid   = 0x00041010;
-                kmi0_device.periphid    = 0x00041050;
-                kmi1_device.periphid    = 0x00041050;
-                uart0_device.dev.platform_data = &ap_uart_data;
-                uart1_device.dev.platform_data = &ap_uart_data;
-        }
-
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-
-        return 0;
+        return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
 }
 
-#endif
-
-static DEFINE_RAW_SPINLOCK(cm_lock);
-
 /**
  * cm_control - update the CM_CTRL register.
  * @mask: bits to change
@@ -104,12 +57,80 @@ void cm_control(u32 mask, u32 set)
         u32 val;
 
         raw_spin_lock_irqsave(&cm_lock, flags);
-        val = readl(CM_CTRL) & ~mask;
-        writel(val | set, CM_CTRL);
+        val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask;
+        writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
         raw_spin_unlock_irqrestore(&cm_lock, flags);
 }
 
-EXPORT_SYMBOL(cm_control);
+static const char *integrator_arch_str(u32 id)
+{
+        switch ((id >> 16) & 0xff) {
+        case 0x00:
+                return "ASB little-endian";
+        case 0x01:
+                return "AHB little-endian";
+        case 0x03:
+                return "AHB-Lite system bus, bi-endian";
+        case 0x04:
+                return "AHB";
+        case 0x08:
+                return "AHB system bus, ASB processor bus";
+        default:
+                return "Unknown";
+        }
+}
+
+static const char *integrator_fpga_str(u32 id)
+{
+        switch ((id >> 12) & 0xf) {
+        case 0x01:
+                return "XC4062";
+        case 0x02:
+                return "XC4085";
+        case 0x03:
+                return "XVC600";
+        case 0x04:
+                return "EPM7256AE (Altera PLD)";
+        default:
+                return "Unknown";
+        }
+}
+
+void cm_clear_irqs(void)
+{
+        /* disable core module IRQs */
+        writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET +
+                IRQ_ENABLE_CLEAR);
+}
+
+static const struct of_device_id cm_match[] = {
+        { .compatible = "arm,core-module-integrator"},
+        { },
+};
+
+void cm_init(void)
+{
+        struct device_node *cm = of_find_matching_node(NULL, cm_match);
+        u32 val;
+
+        if (!cm) {
+                pr_crit("no core module node found in device tree\n");
+                return;
+        }
+        cm_base = of_iomap(cm, 0);
+        if (!cm_base) {
+                pr_crit("could not remap core module\n");
+                return;
+        }
+        cm_clear_irqs();
+        val = readl(cm_base + INTEGRATOR_HDR_ID_OFFSET);
+        pr_info("Detected ARM core module:\n");
+        pr_info("    Manufacturer: %02x\n", (val >> 24));
+        pr_info("    Architecture: %s\n", integrator_arch_str(val));
+        pr_info("    FPGA: %s\n", integrator_fpga_str(val));
+        pr_info("    Build: %02x\n", (val >> 4) & 0xFF);
+        pr_info("    Rev: %c\n", ('A' + (val & 0x03)));
+}
 
 /*
  * We need to stop things allocating the low memory; ideally we need a
@@ -145,27 +166,7 @@ static ssize_t intcp_get_arch(struct device *dev,
                               struct device_attribute *attr,
                               char *buf)
 {
-        const char *arch;
-
-        switch ((integrator_id >> 16) & 0xff) {
-        case 0x00:
-                arch = "ASB little-endian";
-                break;
-        case 0x01:
-                arch = "AHB little-endian";
-                break;
-        case 0x03:
-                arch = "AHB-Lite system bus, bi-endian";
-                break;
-        case 0x04:
-                arch = "AHB";
-                break;
-        default:
-                arch = "Unknown";
-                break;
-        }
-
-        return sprintf(buf, "%s\n", arch);
+        return sprintf(buf, "%s\n", integrator_arch_str(integrator_id));
 }
 
 static struct device_attribute intcp_arch_attr =
@@ -175,24 +176,7 @@ static ssize_t intcp_get_fpga(struct device *dev,
                               struct device_attribute *attr,
                               char *buf)
 {
-        const char *fpga;
-
-        switch ((integrator_id >> 12) & 0xf) {
-        case 0x01:
-                fpga = "XC4062";
-                break;
-        case 0x02:
-                fpga = "XC4085";
-                break;
-        case 0x04:
-                fpga = "EPM7256AE (Altera PLD)";
-                break;
-        default:
-                fpga = "Unknown";
-                break;
-        }
-
-        return sprintf(buf, "%s\n", fpga);
+        return sprintf(buf, "%s\n", integrator_fpga_str(integrator_id));
 }
 
 static struct device_attribute intcp_fpga_attr =
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h
deleted file mode 100644
index eff0adad9ae3..000000000000
--- a/arch/arm/mach-integrator/include/mach/irqs.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/irqs.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Interrupt numbers, all of the above are just static reservations
- * used so they can be encoded into device resources. They will finally
- * be done away with when switching to device tree.
- */
-#define IRQ_PIC_START                   64
-#define IRQ_SOFTINT                     (IRQ_PIC_START+0)
-#define IRQ_UARTINT0                    (IRQ_PIC_START+1)
-#define IRQ_UARTINT1                    (IRQ_PIC_START+2)
-#define IRQ_KMIINT0                     (IRQ_PIC_START+3)
-#define IRQ_KMIINT1                     (IRQ_PIC_START+4)
-#define IRQ_TIMERINT0                   (IRQ_PIC_START+5)
-#define IRQ_TIMERINT1                   (IRQ_PIC_START+6)
-#define IRQ_TIMERINT2                   (IRQ_PIC_START+7)
-#define IRQ_RTCINT                      (IRQ_PIC_START+8)
-#define IRQ_AP_EXPINT0                  (IRQ_PIC_START+9)
-#define IRQ_AP_EXPINT1                  (IRQ_PIC_START+10)
-#define IRQ_AP_EXPINT2                  (IRQ_PIC_START+11)
-#define IRQ_AP_EXPINT3                  (IRQ_PIC_START+12)
-#define IRQ_AP_PCIINT0                  (IRQ_PIC_START+13)
-#define IRQ_AP_PCIINT1                  (IRQ_PIC_START+14)
-#define IRQ_AP_PCIINT2                  (IRQ_PIC_START+15)
-#define IRQ_AP_PCIINT3                  (IRQ_PIC_START+16)
-#define IRQ_AP_V3INT                    (IRQ_PIC_START+17)
-#define IRQ_AP_CPINT0                   (IRQ_PIC_START+18)
-#define IRQ_AP_CPINT1                   (IRQ_PIC_START+19)
-#define IRQ_AP_LBUSTIMEOUT              (IRQ_PIC_START+20)
-#define IRQ_AP_APCINT                   (IRQ_PIC_START+21)
-#define IRQ_CP_CLCDCINT                 (IRQ_PIC_START+22)
-#define IRQ_CP_MMCIINT0                 (IRQ_PIC_START+23)
-#define IRQ_CP_MMCIINT1                 (IRQ_PIC_START+24)
-#define IRQ_CP_AACIINT                  (IRQ_PIC_START+25)
-#define IRQ_CP_CPPLDINT                 (IRQ_PIC_START+26)
-#define IRQ_CP_ETHINT                   (IRQ_PIC_START+27)
-#define IRQ_CP_TSPENINT                 (IRQ_PIC_START+28)
-#define IRQ_PIC_END                     (IRQ_PIC_START+28)
-
-#define IRQ_CIC_START                   (IRQ_PIC_END+1)
-#define IRQ_CM_SOFTINT                  (IRQ_CIC_START+0)
-#define IRQ_CM_COMMRX                   (IRQ_CIC_START+1)
-#define IRQ_CM_COMMTX                   (IRQ_CIC_START+2)
-#define IRQ_CIC_END                     (IRQ_CIC_START+2)
-
-/*
- * IntegratorCP only
- */
-#define IRQ_SIC_START                   (IRQ_CIC_END+1)
-#define IRQ_SIC_CP_SOFTINT              (IRQ_SIC_START+0)
-#define IRQ_SIC_CP_RI0                  (IRQ_SIC_START+1)
-#define IRQ_SIC_CP_RI1                  (IRQ_SIC_START+2)
-#define IRQ_SIC_CP_CARDIN               (IRQ_SIC_START+3)
-#define IRQ_SIC_CP_LMINT0               (IRQ_SIC_START+4)
-#define IRQ_SIC_CP_LMINT1               (IRQ_SIC_START+5)
-#define IRQ_SIC_CP_LMINT2               (IRQ_SIC_START+6)
-#define IRQ_SIC_CP_LMINT3               (IRQ_SIC_START+7)
-#define IRQ_SIC_CP_LMINT4               (IRQ_SIC_START+8)
-#define IRQ_SIC_CP_LMINT5               (IRQ_SIC_START+9)
-#define IRQ_SIC_CP_LMINT6               (IRQ_SIC_START+10)
-#define IRQ_SIC_CP_LMINT7               (IRQ_SIC_START+11)
-#define IRQ_SIC_END                     (IRQ_SIC_START+11)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index d9e95e612fcb..d50dc2dbfd89 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -51,13 +51,13 @@
 #include <asm/mach-types.h>
 
 #include <mach/lm.h>
-#include <mach/irqs.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
+#include "cm.h"
 #include "common.h"
 #include "pci_v3.h"
 
@@ -146,7 +146,7 @@ static int irq_suspend(void)
 static void irq_resume(void)
 {
         /* disable all irq sources */
-        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+        cm_clear_irqs();
         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 
@@ -402,8 +402,6 @@ void __init ap_init_early(void)
 {
 }
 
-#ifdef CONFIG_OF
-
 static void __init ap_of_timer_init(void)
 {
         struct device_node *node;
@@ -450,8 +448,7 @@ static const struct of_device_id fpga_irq_of_match[] __initconst = {
 
 static void __init ap_init_irq_of(void)
 {
-        /* disable core module IRQs */
-        writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+        cm_init();
         of_irq_init(fpga_irq_of_match);
         integrator_clk_init(false);
 }
@@ -473,6 +470,11 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
         { /* sentinel */ },
 };
 
+static const struct of_device_id ap_syscon_match[] = {
+        { .compatible = "arm,integrator-ap-syscon"},
+        { },
+};
+
 static void __init ap_init_of(void)
 {
         unsigned long sc_dec;
@@ -489,7 +491,8 @@ static void __init ap_init_of(void)
         root = of_find_node_by_path("/");
         if (!root)
                 return;
-        syscon = of_find_node_by_path("/syscon");
+
+        syscon = of_find_matching_node(root, ap_syscon_match);
         if (!syscon)
                 return;
 
@@ -541,7 +544,7 @@ static void __init ap_init_of(void)
                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
                 lmdev->resource.flags = IORESOURCE_MEM;
-                lmdev->irq = IRQ_AP_EXPINT0 + i;
+                lmdev->irq = irq_of_parse_and_map(syscon, i);
                 lmdev->id = i;
 
                 lm_device_register(lmdev);
@@ -564,136 +567,3 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
         .restart        = integrator_restart,
         .dt_compat      = ap_dt_board_compat,
 MACHINE_END
-
-#endif
-
-#ifdef CONFIG_ATAGS
-
-/*
- * For the ATAG boot some static mappings are needed. This will
- * go away with the ATAG support down the road.
- */
-
-static struct map_desc ap_io_desc_atag[] __initdata = {
-        {
-                .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        },
-};
-
-static void __init ap_map_io_atag(void)
-{
-        iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
-        ap_map_io();
-}
-
-/*
- * This is where non-devicetree initialization code is collected and stashed
- * for eventual deletion.
- */
-
-static struct platform_device pci_v3_device = {
-        .name           = "pci-v3",
-        .id             = 0,
-};
-
-static struct resource cfi_flash_resource = {
-        .start          = INTEGRATOR_FLASH_BASE,
-        .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device cfi_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &ap_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &cfi_flash_resource,
-};
-
-static void __init ap_timer_init(void)
-{
-        struct clk *clk;
-        unsigned long rate;
-
-        clk = clk_get_sys("ap_timer", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        rate = clk_get_rate(clk);
-
-        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-
-        integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
-        integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
-                                IRQ_TIMERINT1);
-}
-
-#define INTEGRATOR_SC_VALID_INT 0x003fffff
-
-static void __init ap_init_irq(void)
-{
-        /* Disable all interrupts initially. */
-        /* Do the core module ones */
-        writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-
-        /* do the header card stuff next */
-        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-
-        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-                -1, INTEGRATOR_SC_VALID_INT, NULL);
-        integrator_clk_init(false);
-}
-
-static void __init ap_init(void)
-{
-        unsigned long sc_dec;
-        int i;
-
-        platform_device_register(&pci_v3_device);
-        platform_device_register(&cfi_flash_device);
-
-        ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
-        sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
-        for (i = 0; i < 4; i++) {
-                struct lm_device *lmdev;
-
-                if ((sc_dec & (16 << i)) == 0)
-                        continue;
-
-                lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
-                if (!lmdev)
-                        continue;
-
-                lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-                lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-                lmdev->resource.flags = IORESOURCE_MEM;
-                lmdev->irq = IRQ_AP_EXPINT0 + i;
-                lmdev->id = i;
-
-                lm_device_register(lmdev);
-        }
-
-        integrator_init(false);
-}
-
-MACHINE_START(INTEGRATOR, "ARM-Integrator")
-        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .atag_offset    = 0x100,
-        .reserve        = integrator_reserve,
-        .map_io         = ap_map_io_atag,
-        .init_early     = ap_init_early,
-        .init_irq       = ap_init_irq,
-        .handle_irq     = fpga_handle_irq,
-        .init_time      = ap_timer_init,
-        .init_machine   = ap_init,
-        .restart        = integrator_restart,
-MACHINE_END
-
-#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 8c60fcb08a98..1df6e7602cad 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -36,9 +36,7 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 
-#include <mach/cm.h>
 #include <mach/lm.h>
-#include <mach/irqs.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
@@ -50,6 +48,7 @@
 #include <plat/clcd.h>
 #include <plat/sched_clock.h>
 
+#include "cm.h"
 #include "common.h"
 
 /* Base address to the CP controller */
@@ -249,7 +248,6 @@ static void __init intcp_init_early(void)
 #endif
 }
 
-#ifdef CONFIG_OF
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
         { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
         { /* Sentinel */ }
@@ -257,6 +255,7 @@ static const struct of_device_id fpga_irq_of_match[] __initconst = {
 
 static void __init intcp_init_irq_of(void)
 {
+        cm_init();
         of_irq_init(fpga_irq_of_match);
         integrator_clk_init(true);
 }
@@ -287,6 +286,11 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
         { /* sentinel */ },
 };
 
+static const struct of_device_id intcp_syscon_match[] = {
+        { .compatible = "arm,integrator-cp-syscon"},
+        { },
+};
+
 static void __init intcp_init_of(void)
 {
         struct device_node *root;
@@ -301,7 +305,8 @@ static void __init intcp_init_of(void)
         root = of_find_node_by_path("/");
         if (!root)
                 return;
-        cpcon = of_find_node_by_path("/cpcon");
+
+        cpcon = of_find_matching_node(root, intcp_syscon_match);
         if (!cpcon)
                 return;
 
@@ -354,175 +359,3 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
         .restart        = integrator_restart,
         .dt_compat      = intcp_dt_board_compat,
 MACHINE_END
-
-#endif
-
-#ifdef CONFIG_ATAGS
-
-/*
- * For the ATAG boot some static mappings are needed. This will
- * go away with the ATAG support down the road.
- */
-
-static struct map_desc intcp_io_desc_atag[] __initdata = {
-        {
-                .virtual        = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
-                .pfn            = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        },
-};
-
-static void __init intcp_map_io_atag(void)
-{
-        iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
-        intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
-        intcp_map_io();
-}
-
-
-/*
- * This is where non-devicetree initialization code is collected and stashed
- * for eventual deletion.
- */
-
-#define INTCP_FLASH_SIZE                SZ_32M
-
-static struct resource intcp_flash_resource = {
-        .start          = INTCP_PA_FLASH_BASE,
-        .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device intcp_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &intcp_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &intcp_flash_resource,
-};
-
-#define INTCP_ETH_SIZE                  0x10
-
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .start  = INTEGRATOR_CP_ETH_BASE,
-                .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CP_ETHINT,
-                .end    = IRQ_CP_ETHINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device smc91x_device = {
-        .name           = "smc91x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-};
-
-static struct platform_device *intcp_devs[] __initdata = {
-        &intcp_flash_device,
-        &smc91x_device,
-};
-
-#define INTCP_VA_CIC_BASE               __io_address(INTEGRATOR_HDR_BASE + 0x40)
-#define INTCP_VA_PIC_BASE               __io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE               __io_address(INTEGRATOR_CP_SIC_BASE)
-
-static void __init intcp_init_irq(void)
-{
-        u32 pic_mask, cic_mask, sic_mask;
-
-        /* These masks are for the HW IRQ registers */
-        pic_mask = ~((~0u) << (11 - 0));
-        pic_mask |= (~((~0u) << (29 - 22))) << 22;
-        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-
-        /*
-         * Disable all interrupt sources
-         */
-        writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-
-        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-                      -1, pic_mask, NULL);
-
-        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-                      -1, cic_mask, NULL);
-
-        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-                      IRQ_CP_CPPLDINT, sic_mask, NULL);
-
-        integrator_clk_init(true);
-}
-
-#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
-#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
-#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
-
-static void __init cp_timer_init(void)
-{
-        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-
-        sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
-        sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
-}
-
-#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
-#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
-
-static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
-        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
-
-static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
-        INTEGRATOR_CP_AACI_IRQS, NULL);
-
-static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
-        { IRQ_CP_CLCDCINT }, &clcd_data);
-
-static struct amba_device *amba_devs[] __initdata = {
-        &mmc_device,
-        &aaci_device,
-        &clcd_device,
-};
-
-static void __init intcp_init(void)
-{
-        int i;
-
-        platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
-
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-        integrator_init(true);
-}
-
-MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
-        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .atag_offset    = 0x100,
-        .reserve        = integrator_reserve,
-        .map_io         = intcp_map_io_atag,
-        .init_early     = intcp_init_early,
-        .init_irq       = intcp_init_irq,
-        .handle_irq     = fpga_handle_irq,
-        .init_time      = cp_timer_init,
-        .init_machine   = intcp_init,
-        .restart        = integrator_restart,
-MACHINE_END
-
-#endif
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 7a7f6d3273bf..cb6ac58f5e07 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -11,10 +11,11 @@
 #include <linux/slab.h>
 #include <linux/leds.h>
 
-#include <mach/cm.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 
+#include "cm.h"
+
 #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
 
 #define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE)
@@ -78,7 +79,7 @@ static void cm_led_set(struct led_classdev *cdev,
 
 static enum led_brightness cm_led_get(struct led_classdev *cdev)
 {
-        u32 reg = readl(CM_CTRL);
+        u32 reg = cm_get();
 
         return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF;
 }
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index bef100527c42..c9c5a33bc802 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -36,7 +36,6 @@
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <mach/irqs.h>
 
 #include <asm/mach/map.h>
 #include <asm/signal.h>
@@ -605,7 +604,7 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         return 1;
 }
 
-static irqreturn_t v3_irq(int dummy, void *devid)
+static irqreturn_t v3_irq(int irq, void *devid)
 {
 #ifdef CONFIG_DEBUG_LL
         struct pt_regs *regs = get_irq_regs();
@@ -615,7 +614,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
         extern void printascii(const char *);
 
         sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
-                "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
+                "ISTAT=%02x\n", irq, pc, instr,
                 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
                 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
                 v3_readb(V3_LB_ISTAT));
@@ -809,32 +808,6 @@ static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
         return pci_common_swizzle(dev, pinp);
 }
 
-static int irq_tab[4] __initdata = {
-        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
-};
-
-/*
- * map the specified device/slot/pin to an IRQ.  This works out such
- * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
- */
-static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int intnr = ((slot - 9) + (pin - 1)) & 3;
-
-        return irq_tab[intnr];
-}
-
-static struct hw_pci pci_v3 __initdata = {
-        .swizzle                = pci_v3_swizzle,
-        .setup                  = pci_v3_setup,
-        .nr_controllers         = 1,
-        .ops                    = &pci_v3_ops,
-        .preinit                = pci_v3_preinit,
-        .postinit               = pci_v3_postinit,
-};
-
-#ifdef CONFIG_OF
-
 static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         struct of_irq oirq;
@@ -851,14 +824,36 @@ static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
                                      oirq.size);
 }
 
-static int __init pci_v3_dtprobe(struct platform_device *pdev,
-                                struct device_node *np)
+static struct hw_pci pci_v3 __initdata = {
+        .swizzle                = pci_v3_swizzle,
+        .setup                  = pci_v3_setup,
+        .nr_controllers         = 1,
+        .ops                    = &pci_v3_ops,
+        .preinit                = pci_v3_preinit,
+        .postinit               = pci_v3_postinit,
+};
+
+static int __init pci_v3_probe(struct platform_device *pdev)
 {
+        struct device_node *np = pdev->dev.of_node;
         struct of_pci_range_parser parser;
         struct of_pci_range range;
         struct resource *res;
         int irq, ret;
 
+        /* Remap the Integrator system controller */
+        ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100);
+        if (!ap_syscon_base) {
+                dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
+                return -ENODEV;
+        }
+
+        /* Device tree probe path */
+        if (!np) {
+                dev_err(&pdev->dev, "no device tree node for PCIv3\n");
+                return -ENODEV;
+        }
+
         if (of_pci_range_parser_init(&parser, np))
                 return -EINVAL;
 
@@ -925,76 +920,6 @@ static int __init pci_v3_dtprobe(struct platform_device *pdev,
         return 0;
 }
 
-#else
-
-static inline int pci_v3_dtprobe(struct platform_device *pdev,
-                                  struct device_node *np)
-{
-        return -EINVAL;
-}
-
-#endif
-
-static int __init pci_v3_probe(struct platform_device *pdev)
-{
-        struct device_node *np = pdev->dev.of_node;
-        int ret;
-
-        /* Remap the Integrator system controller */
-        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
-        if (!ap_syscon_base) {
-                dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
-                return -ENODEV;
-        }
-
-        /* Device tree probe path */
-        if (np)
-                return pci_v3_dtprobe(pdev, np);
-
-        pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
-        if (!pci_v3_base) {
-                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
-                return -ENODEV;
-        }
-
-        ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
-        if (ret) {
-                dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
-                        ret);
-                return -ENODEV;
-        }
-
-        conf_mem.name = "PCIv3 config";
-        conf_mem.start = PHYS_PCI_CONFIG_BASE;
-        conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
-        conf_mem.flags = IORESOURCE_MEM;
-
-        io_mem.name = "PCIv3 I/O";
-        io_mem.start = PHYS_PCI_IO_BASE;
-        io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
-        io_mem.flags = IORESOURCE_MEM;
-
-        non_mem_pci = 0x00000000;
-        non_mem_pci_sz = SZ_256M;
-        non_mem.name = "PCIv3 non-prefetched mem";
-        non_mem.start = PHYS_PCI_MEM_BASE;
-        non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1;
-        non_mem.flags = IORESOURCE_MEM;
-
-        pre_mem_pci = 0x10000000;
-        pre_mem_pci_sz = SZ_256M;
-        pre_mem.name = "PCIv3 prefetched mem";
-        pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M;
-        pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1;
-        pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
-        pci_v3.map_irq = pci_v3_map_irq;
-
-        pci_common_init_dev(&pdev->dev, &pci_v3);
-
-        return 0;
-}
-
 static const struct of_device_id pci_ids[] = {
         { .compatible = "v3,v360epc-pci", },
         {},
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 366d1a3b418d..f20c53e75ed9 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -9,6 +9,8 @@ config ARCH_KEYSTONE
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_ERRATA_798181 if SMP
+        select COMMON_CLK_KEYSTONE
+        select TI_EDMA
         help
           Support for boards based on the Texas Instruments Keystone family of
           SoCs.
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index ddc52b05dc84..25d92396fbfa 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -4,3 +4,6 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
 
 obj-$(CONFIG_SMP)                       += platsmp.o
+
+# PM domain driver for Keystone SOCs
+obj-$(CONFIG_ARCH_KEYSTONE)             += pm_domain.o
diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c
new file mode 100644
index 000000000000..29625232e954
--- /dev/null
+++ b/arch/arm/mach-keystone/pm_domain.c
@@ -0,0 +1,82 @@
+/*
+ * PM domain driver for Keystone2 devices
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * Based on Kevins work on DAVINCI SOCs
+ *      Kevin Hilman <khilman@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_clock.h>
+#include <linux/platform_device.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#ifdef CONFIG_PM_RUNTIME
+static int keystone_pm_runtime_suspend(struct device *dev)
+{
+        int ret;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        ret = pm_generic_runtime_suspend(dev);
+        if (ret)
+                return ret;
+
+        ret = pm_clk_suspend(dev);
+        if (ret) {
+                pm_generic_runtime_resume(dev);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int keystone_pm_runtime_resume(struct device *dev)
+{
+        dev_dbg(dev, "%s\n", __func__);
+
+        pm_clk_resume(dev);
+
+        return pm_generic_runtime_resume(dev);
+}
+#endif
+
+static struct dev_pm_domain keystone_pm_domain = {
+        .ops = {
+                SET_RUNTIME_PM_OPS(keystone_pm_runtime_suspend,
+                                   keystone_pm_runtime_resume, NULL)
+                USE_PLATFORM_PM_SLEEP_OPS
+        },
+};
+
+static struct pm_clk_notifier_block platform_domain_notifier = {
+        .pm_domain = &keystone_pm_domain,
+};
+
+static struct of_device_id of_keystone_table[] = {
+        {.compatible = "ti,keystone"},
+        { /* end of list */ },
+};
+
+int __init keystone_pm_runtime_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, of_keystone_table);
+        if (!np)
+                return 0;
+
+        of_clk_init(NULL);
+        pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier);
+
+        return 0;
+}
+subsys_initcall(keystone_pm_runtime_init);
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index d1f8e3d0793b..144b51102939 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,5 +1,7 @@
 obj-y                           += common.o pcie.o
 obj-$(CONFIG_KIRKWOOD_LEGACY)   += irq.o mpp.o
+obj-$(CONFIG_PM)                += pm.o
+
 obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index a32a3e507a9d..c9f6fd2d90f5 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -13,6 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_net.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
 #include <linux/dma-mapping.h>
@@ -43,14 +45,6 @@ static void __init kirkwood_legacy_clk_init(void)
         clkspec.np = np;
         clkspec.args_count = 1;
 
-        clkspec.args[0] = CGC_BIT_PEX0;
-        orion_clkdev_add("0", "pcie",
-                         of_clk_get_from_provider(&clkspec));
-
-        clkspec.args[0] = CGC_BIT_PEX1;
-        orion_clkdev_add("1", "pcie",
-                         of_clk_get_from_provider(&clkspec));
-
         /*
          * The ethernet interfaces forget the MAC address assigned by
          * u-boot if the clocks are turned off. Until proper DT support
@@ -65,11 +59,83 @@ static void __init kirkwood_legacy_clk_init(void)
         clk_prepare_enable(clk);
 }
 
-static void __init kirkwood_dt_init_early(void)
+#define MV643XX_ETH_MAC_ADDR_LOW        0x0414
+#define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
+
+static void __init kirkwood_dt_eth_fixup(void)
 {
-        mvebu_mbus_init("marvell,kirkwood-mbus",
-                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
-                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
+        struct device_node *np;
+
+        /*
+         * The ethernet interfaces forget the MAC address assigned by u-boot
+         * if the clocks are turned off. Usually, u-boot on kirkwood boards
+         * has no DT support to properly set local-mac-address property.
+         * As a workaround, we get the MAC address from mv643xx_eth registers
+         * and update the port device node if no valid MAC address is set.
+         */
+        for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") {
+                struct device_node *pnp = of_get_parent(np);
+                struct clk *clk;
+                struct property *pmac;
+                void __iomem *io;
+                u8 *macaddr;
+                u32 reg;
+
+                if (!pnp)
+                        continue;
+
+                /* skip disabled nodes or nodes with valid MAC address*/
+                if (!of_device_is_available(pnp) || of_get_mac_address(np))
+                        goto eth_fixup_skip;
+
+                clk = of_clk_get(pnp, 0);
+                if (IS_ERR(clk))
+                        goto eth_fixup_skip;
+
+                io = of_iomap(pnp, 0);
+                if (!io)
+                        goto eth_fixup_no_map;
+
+                /* ensure port clock is not gated to not hang CPU */
+                clk_prepare_enable(clk);
+
+                /* store MAC address register contents in local-mac-address */
+                pr_err(FW_INFO "%s: local-mac-address is not set\n",
+                       np->full_name);
+
+                pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL);
+                if (!pmac)
+                        goto eth_fixup_no_mem;
+
+                pmac->value = pmac + 1;
+                pmac->length = 6;
+                pmac->name = kstrdup("local-mac-address", GFP_KERNEL);
+                if (!pmac->name) {
+                        kfree(pmac);
+                        goto eth_fixup_no_mem;
+                }
+
+                macaddr = pmac->value;
+                reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH);
+                macaddr[0] = (reg >> 24) & 0xff;
+                macaddr[1] = (reg >> 16) & 0xff;
+                macaddr[2] = (reg >> 8) & 0xff;
+                macaddr[3] = reg & 0xff;
+
+                reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW);
+                macaddr[4] = (reg >> 8) & 0xff;
+                macaddr[5] = reg & 0xff;
+
+                of_update_property(np, pmac);
+
+eth_fixup_no_mem:
+                iounmap(io);
+                clk_disable_unprepare(clk);
+eth_fixup_no_map:
+                clk_put(clk);
+eth_fixup_skip:
+                of_node_put(pnp);
+        }
 }
 
 static void __init kirkwood_dt_init(void)
@@ -90,11 +156,12 @@ static void __init kirkwood_dt_init(void)
         kirkwood_l2_init();
 
         kirkwood_cpufreq_init();
-
+        kirkwood_cpuidle_init();
         /* Setup clocks for legacy devices */
         kirkwood_legacy_clk_init();
 
-        kirkwood_cpuidle_init();
+        kirkwood_pm_init();
+        kirkwood_dt_eth_fixup();
 
 #ifdef CONFIG_KEXEC
         kexec_reinit = kirkwood_enable_pcie;
@@ -114,7 +181,6 @@ static const char * const kirkwood_dt_board_compat[] = {
 DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
         /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
         .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_dt_init_early,
         .init_machine   = kirkwood_dt_init,
         .restart        = kirkwood_restart,
         .dt_compat      = kirkwood_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 176761134a66..f3407a5db216 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -721,6 +721,7 @@ void __init kirkwood_init(void)
         kirkwood_xor1_init();
         kirkwood_crypto_init();
 
+        kirkwood_pm_init();
         kirkwood_cpuidle_init();
 #ifdef CONFIG_KEXEC
         kexec_reinit = kirkwood_enable_pcie;
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 1296de94febf..05fd648df543 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,6 +58,12 @@ void kirkwood_cpufreq_init(void);
 void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
+#ifdef CONFIG_PM
+void kirkwood_pm_init(void);
+#else
+static inline void kirkwood_pm_init(void) {};
+#endif
+
 /* board init functions for boards not fully converted to fdt */
 #ifdef CONFIG_MACH_MV88F6281GTW_GE_DT
 void mv88f6281gtw_ge_init(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 91242c944d7a..8b9d1c9ff199 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -78,4 +78,6 @@
 #define CGC_TDM                 (1 << 20)
 #define CGC_RESERVED            (0x6 << 21)
 
+#define MEMORY_PM_CTRL          (BRIDGE_VIRT_BASE + 0x118)
+
 #endif
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c
new file mode 100644
index 000000000000..8783a7184e73
--- /dev/null
+++ b/arch/arm/mach-kirkwood/pm.c
@@ -0,0 +1,73 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/bridge-regs.h>
+
+static void __iomem *ddr_operation_base;
+
+static void kirkwood_low_power(void)
+{
+        u32 mem_pm_ctrl;
+
+        mem_pm_ctrl = readl(MEMORY_PM_CTRL);
+
+        /* Set peripherals to low-power mode */
+        writel_relaxed(~0, MEMORY_PM_CTRL);
+
+        /* Set DDR in self-refresh */
+        writel_relaxed(0x7, ddr_operation_base);
+
+        /*
+         * Set CPU in wait-for-interrupt state.
+         * This disables the CPU core clocks,
+         * the array clocks, and also the L2 controller.
+         */
+        cpu_do_idle();
+
+        writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL);
+}
+
+static int kirkwood_suspend_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                kirkwood_low_power();
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static int kirkwood_pm_valid_standby(suspend_state_t state)
+{
+        return state == PM_SUSPEND_STANDBY;
+}
+
+static const struct platform_suspend_ops kirkwood_suspend_ops = {
+        .enter = kirkwood_suspend_enter,
+        .valid = kirkwood_pm_valid_standby,
+};
+
+int __init kirkwood_pm_init(void)
+{
+        ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
+        suspend_set_ops(&kirkwood_suspend_ops);
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index afb457c3135b..cb7b527d61bd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -112,13 +112,13 @@ obj-$(CONFIG_ARCH_OMAP2)		+= prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
-obj-$(CONFIG_SOC_AM43XX)                += prm33xx.o cm33xx.o
 omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
                                            prcm_mpu44xx.o prminst44xx.o \
                                            vc44xx_data.o vp44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_DRA7XX)                += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_AM43XX)                += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -146,6 +146,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
 obj-$(CONFIG_SOC_AM43XX)                += $(powerdomain-common)
+obj-$(CONFIG_SOC_AM43XX)                += powerdomains43xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += powerdomains54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)                += $(powerdomain-common)
@@ -165,6 +166,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
 obj-$(CONFIG_SOC_AM43XX)                += $(clockdomain-common)
+obj-$(CONFIG_SOC_AM43XX)                += clockdomains43xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += clockdomains54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)                += $(clockdomain-common)
@@ -210,6 +212,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_43xx_interconnect_data.o
+obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_43xx_ipblock_data.o
+obj-$(CONFIG_SOC_AM43XX)                += omap_hwmod_43xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += omap_hwmod_33xx_43xx_interconnect_data.o
+obj-$(CONFIG_SOC_AM43XX)                += omap_hwmod_33xx_43xx_ipblock_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += omap_hwmod_54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)                += omap_hwmod_7xx_data.o
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 4b03394fa0c5..f17f00697cc0 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -132,7 +132,7 @@ struct clockdomain {
         u8 _flags;
         const u8 dep_bit;
         const u8 prcm_partition;
-        const s16 cm_inst;
+        const u16 cm_inst;
         const u16 clkdm_offs;
         struct clkdm_dep *wkdep_srcs;
         struct clkdm_dep *sleepdep_srcs;
@@ -218,6 +218,7 @@ extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void __init omap54xx_clockdomains_init(void);
 extern void __init dra7xx_clockdomains_init(void);
+void am43xx_clockdomains_init(void);
 
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
 extern struct clkdm_ops am33xx_clkdm_operations;
+extern struct clkdm_ops am43xx_clkdm_operations;
 
 extern struct clkdm_dep gfx_24xx_wkdeps[];
 extern struct clkdm_dep dsp_24xx_wkdeps[];
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
new file mode 100644
index 000000000000..6d71c6082a24
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -0,0 +1,196 @@
+/*
+ * AM43xx Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "prcm44xx.h"
+#include "prcm43xx.h"
+
+static struct clockdomain l4_cefuse_43xx_clkdm = {
+        .name             = "l4_cefuse_clkdm",
+        .pwrdm            = { .name = "cefuse_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_CEFUSE_INST,
+        .clkdm_offs       = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain mpu_43xx_clkdm = {
+        .name             = "mpu_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_MPU_INST,
+        .clkdm_offs       = AM43XX_CM_MPU_MPU_CDOFFS,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4ls_43xx_clkdm = {
+        .name             = "l4ls_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_L4LS_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain tamper_43xx_clkdm = {
+        .name             = "tamper_clkdm",
+        .pwrdm            = { .name = "tamper_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_TAMPER_INST,
+        .clkdm_offs       = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_rtc_43xx_clkdm = {
+        .name             = "l4_rtc_clkdm",
+        .pwrdm            = { .name = "rtc_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_RTC_INST,
+        .clkdm_offs       = AM43XX_CM_RTC_RTC_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain pruss_ocp_43xx_clkdm = {
+        .name             = "pruss_ocp_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_ICSS_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain ocpwp_l3_43xx_clkdm = {
+        .name             = "ocpwp_l3_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_tsc_43xx_clkdm = {
+        .name             = "l3s_tsc_clkdm",
+        .pwrdm            = { .name = "wkup_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_WKUP_INST,
+        .clkdm_offs       = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain dss_43xx_clkdm = {
+        .name             = "dss_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_DSS_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_aon_43xx_clkdm = {
+        .name             = "l3_aon_clkdm",
+        .pwrdm            = { .name = "wkup_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_WKUP_INST,
+        .clkdm_offs       = AM43XX_CM_WKUP_L3_AON_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain emif_43xx_clkdm = {
+        .name             = "emif_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_EMIF_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_aon_43xx_clkdm = {
+        .name             = "l4_wkup_aon_clkdm",
+        .pwrdm            = { .name = "wkup_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_WKUP_INST,
+        .clkdm_offs       = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
+};
+
+static struct clockdomain l3_43xx_clkdm = {
+        .name             = "l3_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_L3_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_43xx_clkdm = {
+        .name             = "l4_wkup_clkdm",
+        .pwrdm            = { .name = "wkup_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_WKUP_INST,
+        .clkdm_offs       = AM43XX_CM_WKUP_WKUP_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain cpsw_125mhz_43xx_clkdm = {
+        .name             = "cpsw_125mhz_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_CPSW_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l3_43xx_clkdm = {
+        .name             = "gfx_l3_clkdm",
+        .pwrdm            = { .name = "gfx_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_GFX_INST,
+        .clkdm_offs       = AM43XX_CM_GFX_GFX_L3_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_43xx_clkdm = {
+        .name             = "l3s_clkdm",
+        .pwrdm            = { .name = "per_pwrdm" },
+        .prcm_partition   = AM43XX_CM_PARTITION,
+        .cm_inst          = AM43XX_CM_PER_INST,
+        .clkdm_offs       = AM43XX_CM_PER_L3S_CDOFFS,
+        .flags            = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain *clockdomains_am43xx[] __initdata = {
+        &l4_cefuse_43xx_clkdm,
+        &mpu_43xx_clkdm,
+        &l4ls_43xx_clkdm,
+        &tamper_43xx_clkdm,
+        &l4_rtc_43xx_clkdm,
+        &pruss_ocp_43xx_clkdm,
+        &ocpwp_l3_43xx_clkdm,
+        &l3s_tsc_43xx_clkdm,
+        &dss_43xx_clkdm,
+        &l3_aon_43xx_clkdm,
+        &emif_43xx_clkdm,
+        &l4_wkup_aon_43xx_clkdm,
+        &l3_43xx_clkdm,
+        &l4_wkup_43xx_clkdm,
+        &cpsw_125mhz_43xx_clkdm,
+        &gfx_l3_43xx_clkdm,
+        &l3s_43xx_clkdm,
+        NULL
+};
+
+void __init am43xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&am43xx_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_am43xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 325a51576576..40a22e5649ae 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -48,13 +48,13 @@
 /* Private functions */
 
 /* Read a register in a CM instance */
-static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
+static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
 {
         return __raw_readl(cm_base + inst + idx);
 }
 
 /* Write into a register in a CM */
-static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
+static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
 {
         __raw_writel(val, cm_base + inst + idx);
 }
@@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
  * will handle the shift itself.
  */
-static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
+static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
 {
         u32 v;
 
@@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
  * Returns true if the clockdomain referred to by (@inst, @cdoffs)
  * is in hardware-supervised idle mode, or 0 otherwise.
  */
-bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
 {
         u32 v;
 
@@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
  * Put a clockdomain referred to by (@inst, @cdoffs) into
  * hardware-supervised idle mode.  No return value.
  */
-void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
 }
@@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
  * software-supervised idle mode, i.e., controlled manually by the
  * Linux OMAP clockdomain code.  No return value.
  */
-void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
 }
@@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
  * Put a clockdomain referred to by (@inst, @cdoffs) into idle
  * No return value.
  */
-void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
 }
@@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
  * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
  * waking it up.  No return value.
  */
-void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
 }
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 9d1f4fcdebbb..cfb8891b0c0e 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -377,13 +377,13 @@
 
 
 #ifndef __ASSEMBLER__
-extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
 
-#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
+#ifdef CONFIG_SOC_AM33XX
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
                                         u16 clkctrl_offs);
 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f0290f5566fe..731ca134348c 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
 /* Public functions */
 
 /* Read a register in a CM instance */
-u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
 {
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 }
 
 /* Write into a register in a CM instance */
-void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
 {
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
@@ -129,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
 }
 
 /* Read-modify-write a register in CM1. Caller must lock */
-u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
                                    s16 idx)
 {
         u32 v;
@@ -142,12 +142,12 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
         return v;
 }
 
-u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
+u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
 {
         return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
 }
 
-u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
+u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
 {
         return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
 }
@@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
  * will handle the shift itself.
  */
-static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
+static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
 {
         u32 v;
 
@@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
  * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
  * is in hardware-supervised idle mode, or 0 otherwise.
  */
-bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
         u32 v;
 
@@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
  * hardware-supervised idle mode.  No return value.
  */
-void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
 }
@@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
  * software-supervised idle mode, i.e., controlled manually by the
  * Linux OMAP clockdomain code.  No return value.
  */
-void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
 }
@@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
  * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
  * waking it up.  No return value.
  */
-void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
 {
         _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
 }
@@ -483,3 +483,12 @@ struct clkdm_ops omap4_clkdm_operations = {
         .clkdm_clk_enable       = omap4_clkdm_clk_enable,
         .clkdm_clk_disable      = omap4_clkdm_clk_disable,
 };
+
+struct clkdm_ops am43xx_clkdm_operations = {
+        .clkdm_sleep            = omap4_clkdm_sleep,
+        .clkdm_wakeup           = omap4_clkdm_wakeup,
+        .clkdm_allow_idle       = omap4_clkdm_allow_idle,
+        .clkdm_deny_idle        = omap4_clkdm_deny_idle,
+        .clkdm_clk_enable       = omap4_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap4_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index bd7bab889745..7f56ea444bc4 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -11,11 +11,11 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
 #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
 
-extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
 extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
 extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
                                          u16 clkctrl_offs);
@@ -27,14 +27,14 @@ extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
  * In an ideal world, we would not export these low-level functions,
  * but this will probably take some time to fix properly
  */
-extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
-extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
-extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
-                                           s16 inst, s16 idx);
-extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
-                                           s16 idx);
-extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
-                                           s16 idx);
+u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
+void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
+u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+                                   u16 inst, s16 idx);
+u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst,
+                                   s16 idx);
+u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
+                                     s16 idx);
 extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
                                            u32 mask);
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index ef32d11c4bca..9428c5f9d4f2 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -588,8 +588,8 @@ void __init omap5xxx_check_revision(void)
         case 0xb942:
                 switch (rev) {
                 case 0:
-                        omap_revision = OMAP5430_REV_ES1_0;
-                        break;
+                        /* No support for ES1.0 Test chip */
+                        BUG();
                 case 1:
                 default:
                         omap_revision = OMAP5430_REV_ES2_0;
@@ -599,8 +599,8 @@ void __init omap5xxx_check_revision(void)
         case 0xb998:
                 switch (rev) {
                 case 0:
-                        omap_revision = OMAP5432_REV_ES1_0;
-                        break;
+                        /* No support for ES1.0 Test chip */
+                        BUG();
                 case 1:
                 default:
                         omap_revision = OMAP5432_REV_ES2_0;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff2113ce4014..c90f64765a3d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -594,7 +594,13 @@ void __init am43xx_init_early(void)
                                   NULL);
         omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
         omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+        omap_prm_base_init();
+        omap_cm_base_init();
         omap3xxx_check_revision();
+        am43xx_powerdomains_init();
+        am43xx_clockdomains_init();
+        am43xx_hwmod_init();
+        omap_hwmod_init_postsetup();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 0e729170c46b..a5ee09d20ac9 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -42,6 +42,8 @@
 #define OMAP4_MON_L2X0_AUXCTRL_INDEX    0x109
 #define OMAP4_MON_L2X0_PREFETCH_INDEX   0x113
 
+#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
+
 /* Secure PPA(Primary Protected Application) APIs */
 #define OMAP4_PPA_L2_POR_INDEX          0x23
 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX   0x25
@@ -60,5 +62,7 @@ extern int omap_barrier_reserve_memblock(void);
 static inline void omap_barrier_reserve_memblock(void)
 { }
 #endif
+
+void set_cntfreq(void);
 #endif /* __ASSEMBLER__ */
 #endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 891211093295..75e95d4fb448 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -66,6 +66,13 @@ static void omap4_secondary_init(unsigned int cpu)
                                                         4, 0, 0, 0, 0, 0);
 
         /*
+         * Configure the CNTFRQ register for the secondary cpu's which
+         * indicates the frequency of the cpu local timers.
+         */
+        if (soc_is_omap54xx() || soc_is_dra7xx())
+                set_cntfreq();
+
+        /*
          * Synchronise with the boot thread.
          */
         spin_lock(&boot_lock);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d9ee0ff094d4..e3f0ecaf87dd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2357,25 +2357,29 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
 /**
  * _init_mpu_rt_base - populate the virtual address for a hwmod
  * @oh: struct omap_hwmod * to locate the virtual address
+ * @data: (unused, caller should pass NULL)
+ * @np: struct device_node * of the IP block's device node in the DT data
  *
  * Cache the virtual address used by the MPU to access this IP block's
  * registers.  This address is needed early so the OCP registers that
  * are part of the device's address space can be ioremapped properly.
- * No return value.
+ *
+ * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and
+ * -ENXIO on absent or invalid register target address space.
  */
-static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
+static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
+                                    struct device_node *np)
 {
         struct omap_hwmod_addr_space *mem;
         void __iomem *va_start = NULL;
-        struct device_node *np;
 
         if (!oh)
-                return;
+                return -EINVAL;
 
         _save_mpu_port_index(oh);
 
         if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
-                return;
+                return -ENXIO;
 
         mem = _find_mpu_rt_addr_space(oh);
         if (!mem) {
@@ -2383,25 +2387,24 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
                          oh->name);
 
                 /* Extract the IO space from device tree blob */
-                if (!of_have_populated_dt())
-                        return;
+                if (!np)
+                        return -ENXIO;
 
-                np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
-                if (np)
-                        va_start = of_iomap(np, oh->mpu_rt_idx);
+                va_start = of_iomap(np, oh->mpu_rt_idx);
         } else {
                 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
         }
 
         if (!va_start) {
                 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
-                return;
+                return -ENXIO;
         }
 
         pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
                  oh->name, va_start);
 
         oh->_mpu_rt_va = va_start;
+        return 0;
 }
 
 /**
@@ -2414,18 +2417,28 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
  * registered at this point.  This is the first of two phases for
  * hwmod initialization.  Code called here does not touch any hardware
  * registers, it simply prepares internal data structures.  Returns 0
- * upon success or if the hwmod isn't registered, or -EINVAL upon
- * failure.
+ * upon success or if the hwmod isn't registered or if the hwmod's
+ * address space is not defined, or -EINVAL upon failure.
  */
 static int __init _init(struct omap_hwmod *oh, void *data)
 {
         int r;
+        struct device_node *np = NULL;
 
         if (oh->_state != _HWMOD_STATE_REGISTERED)
                 return 0;
 
-        if (oh->class->sysc)
-                _init_mpu_rt_base(oh, NULL);
+        if (of_have_populated_dt())
+                np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
+
+        if (oh->class->sysc) {
+                r = _init_mpu_rt_base(oh, NULL, np);
+                if (r < 0) {
+                        WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
+                             oh->name);
+                        return 0;
+                }
+        }
 
         r = _init_clocks(oh, NULL);
         if (r < 0) {
@@ -2433,6 +2446,12 @@ static int __init _init(struct omap_hwmod *oh, void *data)
                 return -EINVAL;
         }
 
+        if (np)
+                if (of_find_property(np, "ti,no-reset-on-init", NULL))
+                        oh->flags |= HWMOD_INIT_NO_RESET;
+                if (of_find_property(np, "ti,no-idle-on-init", NULL))
+                        oh->flags |= HWMOD_INIT_NO_IDLE;
+
         oh->_state = _HWMOD_STATE_INITIALIZED;
 
         return 0;
@@ -4125,6 +4144,14 @@ void __init omap_hwmod_init(void)
                 soc_ops.init_clkdm = _init_clkdm;
                 soc_ops.update_context_lost = _omap4_update_context_lost;
                 soc_ops.get_context_lost = _omap4_get_context_lost;
+        } else if (soc_is_am43xx()) {
+                soc_ops.enable_module = _omap4_enable_module;
+                soc_ops.disable_module = _omap4_disable_module;
+                soc_ops.wait_target_ready = _omap4_wait_target_ready;
+                soc_ops.assert_hardreset = _omap4_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
         } else if (soc_is_am33xx()) {
                 soc_ops.enable_module = _am33xx_enable_module;
                 soc_ops.disable_module = _am33xx_disable_module;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d02acf9308d3..0f97d635ff90 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -752,6 +752,7 @@ extern int omap44xx_hwmod_init(void);
 extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
 extern int dra7xx_hwmod_init(void);
+int am43xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
new file mode 100644
index 000000000000..130332c0534d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -0,0 +1,163 @@
+/*
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ *
+ * Data common for AM335x and AM43x
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H
+
+extern struct omap_hwmod_ocp_if am33xx_mpu__l3_main;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s;
+extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls;
+extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr;
+extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
+extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
+extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main;
+extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
+extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio1;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio2;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3;
+extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
+extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0;
+extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0;
+extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
+extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1;
+extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1;
+extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
+extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2;
+extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2;
+extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2;
+extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3;
+extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1;
+extern struct omap_hwmod_ocp_if am33xx_l3_s__mmc2;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart2;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart3;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart4;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart5;
+extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
+extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
+
+extern struct omap_hwmod am33xx_l3_main_hwmod;
+extern struct omap_hwmod am33xx_l3_s_hwmod;
+extern struct omap_hwmod am33xx_l3_instr_hwmod;
+extern struct omap_hwmod am33xx_l4_ls_hwmod;
+extern struct omap_hwmod am33xx_l4_wkup_hwmod;
+extern struct omap_hwmod am33xx_mpu_hwmod;
+extern struct omap_hwmod am33xx_pruss_hwmod;
+extern struct omap_hwmod am33xx_gfx_hwmod;
+extern struct omap_hwmod am33xx_prcm_hwmod;
+extern struct omap_hwmod am33xx_aes0_hwmod;
+extern struct omap_hwmod am33xx_sha0_hwmod;
+extern struct omap_hwmod am33xx_ocmcram_hwmod;
+extern struct omap_hwmod am33xx_smartreflex0_hwmod;
+extern struct omap_hwmod am33xx_smartreflex1_hwmod;
+extern struct omap_hwmod am33xx_cpgmac0_hwmod;
+extern struct omap_hwmod am33xx_mdio_hwmod;
+extern struct omap_hwmod am33xx_dcan0_hwmod;
+extern struct omap_hwmod am33xx_dcan1_hwmod;
+extern struct omap_hwmod am33xx_elm_hwmod;
+extern struct omap_hwmod am33xx_epwmss0_hwmod;
+extern struct omap_hwmod am33xx_ecap0_hwmod;
+extern struct omap_hwmod am33xx_eqep0_hwmod;
+extern struct omap_hwmod am33xx_ehrpwm0_hwmod;
+extern struct omap_hwmod am33xx_epwmss1_hwmod;
+extern struct omap_hwmod am33xx_ecap1_hwmod;
+extern struct omap_hwmod am33xx_eqep1_hwmod;
+extern struct omap_hwmod am33xx_ehrpwm1_hwmod;
+extern struct omap_hwmod am33xx_epwmss2_hwmod;
+extern struct omap_hwmod am33xx_ecap2_hwmod;
+extern struct omap_hwmod am33xx_eqep2_hwmod;
+extern struct omap_hwmod am33xx_ehrpwm2_hwmod;
+extern struct omap_hwmod am33xx_gpio1_hwmod;
+extern struct omap_hwmod am33xx_gpio2_hwmod;
+extern struct omap_hwmod am33xx_gpio3_hwmod;
+extern struct omap_hwmod am33xx_gpmc_hwmod;
+extern struct omap_hwmod am33xx_i2c1_hwmod;
+extern struct omap_hwmod am33xx_i2c2_hwmod;
+extern struct omap_hwmod am33xx_i2c3_hwmod;
+extern struct omap_hwmod am33xx_mailbox_hwmod;
+extern struct omap_hwmod am33xx_mcasp0_hwmod;
+extern struct omap_hwmod am33xx_mcasp1_hwmod;
+extern struct omap_hwmod am33xx_mmc0_hwmod;
+extern struct omap_hwmod am33xx_mmc1_hwmod;
+extern struct omap_hwmod am33xx_mmc2_hwmod;
+extern struct omap_hwmod am33xx_rtc_hwmod;
+extern struct omap_hwmod am33xx_spi0_hwmod;
+extern struct omap_hwmod am33xx_spi1_hwmod;
+extern struct omap_hwmod am33xx_spinlock_hwmod;
+extern struct omap_hwmod am33xx_timer1_hwmod;
+extern struct omap_hwmod am33xx_timer2_hwmod;
+extern struct omap_hwmod am33xx_timer3_hwmod;
+extern struct omap_hwmod am33xx_timer4_hwmod;
+extern struct omap_hwmod am33xx_timer5_hwmod;
+extern struct omap_hwmod am33xx_timer6_hwmod;
+extern struct omap_hwmod am33xx_timer7_hwmod;
+extern struct omap_hwmod am33xx_tpcc_hwmod;
+extern struct omap_hwmod am33xx_tptc0_hwmod;
+extern struct omap_hwmod am33xx_tptc1_hwmod;
+extern struct omap_hwmod am33xx_tptc2_hwmod;
+extern struct omap_hwmod am33xx_uart1_hwmod;
+extern struct omap_hwmod am33xx_uart2_hwmod;
+extern struct omap_hwmod am33xx_uart3_hwmod;
+extern struct omap_hwmod am33xx_uart4_hwmod;
+extern struct omap_hwmod am33xx_uart5_hwmod;
+extern struct omap_hwmod am33xx_uart6_hwmod;
+extern struct omap_hwmod am33xx_wd_timer1_hwmod;
+
+extern struct omap_hwmod_class am33xx_l4_hwmod_class;
+extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
+extern struct omap_hwmod_class am33xx_control_hwmod_class;
+extern struct omap_hwmod_class am33xx_gpio_hwmod_class;
+extern struct omap_hwmod_class am33xx_timer_hwmod_class;
+extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
+extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
+extern struct omap_hwmod_class am33xx_spi_hwmod_class;
+
+extern struct omap_gpio_dev_attr gpio_dev_attr;
+extern struct omap2_mcspi_dev_attr mcspi_attrib;
+
+void omap_hwmod_am33xx_reg(void);
+void omap_hwmod_am43xx_reg(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
new file mode 100644
index 000000000000..e2db378b849e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -0,0 +1,643 @@
+/*
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ *
+ * Interconnects common for AM335x and AM43x
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/sizes.h>
+#include "omap_hwmod.h"
+#include "omap_hwmod_33xx_43xx_common_data.h"
+
+/* mpu -> l3 main */
+struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> l3 s */
+struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_s_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_ls_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_instr_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_prcm_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+        .master         = &am33xx_pruss_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+        .master         = &am33xx_gfx_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_gfx_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> rtc */
+struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_rtc_hwmod,
+        .clk            = "clkdiv32k_ick",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+        .master         = &am33xx_cpgmac0_hwmod,
+        .slave          = &am33xx_mdio_hwmod,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_elm_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_elm_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_epwmss0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_epwmss0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
+        .master         = &am33xx_epwmss0_hwmod,
+        .slave          = &am33xx_ecap0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
+        .master         = &am33xx_epwmss0_hwmod,
+        .slave          = &am33xx_eqep0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
+        .master         = &am33xx_epwmss0_hwmod,
+        .slave          = &am33xx_ehrpwm0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+
+static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_epwmss1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_epwmss1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
+        .master         = &am33xx_epwmss1_hwmod,
+        .slave          = &am33xx_ecap1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
+        .master         = &am33xx_epwmss1_hwmod,
+        .slave          = &am33xx_eqep1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
+        .master         = &am33xx_epwmss1_hwmod,
+        .slave          = &am33xx_ehrpwm1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_epwmss2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_epwmss2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
+        .master         = &am33xx_epwmss2_hwmod,
+        .slave          = &am33xx_ecap2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
+        .master         = &am33xx_epwmss2_hwmod,
+        .slave          = &am33xx_eqep2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
+        .master         = &am33xx_epwmss2_hwmod,
+        .slave          = &am33xx_ehrpwm2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x50000000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_gpmc_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_gpmc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* i2c2 */
+struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x480C8000,
+                .pa_end         = 0x480C8000 + (SZ_4K - 1),
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4 ls -> mailbox */
+struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mailbox_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mailbox_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spinlock_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+        {
+                .pa_start       = 0x48038000,
+                .pa_end         = 0x48038000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+        {
+                .pa_start       = 0x4803C000,
+                .pa_end         = 0x4803C000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+        {
+                .pa_start       = 0x48060100,
+                .pa_end         = 0x48060100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x481d8100,
+                .pa_end         = 0x481d8100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x47810100,
+                .pa_end         = 0x47810100 + SZ_64K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mmc2_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mmc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer4_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer5_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer6_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer7_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tpcc_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+        {
+                .pa_start       = 0x49800000,
+                .pa_end         = 0x49800000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc0_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+        {
+                .pa_start       = 0x49900000,
+                .pa_end         = 0x49900000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc1_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+        {
+                .pa_start       = 0x49a00000,
+                .pa_end         = 0x49a00000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc2_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart4_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart5_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart6_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> ocmc */
+struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_ocmcram_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> sha0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
+        {
+                .pa_start       = 0x53100000,
+                .pa_end         = 0x53100000 + SZ_512 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_sha0_hwmod,
+        .clk            = "sha0_fck",
+        .addr           = am33xx_sha0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> AES0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
+        {
+                .pa_start       = 0x53500000,
+                .pa_end         = 0x53500000 + SZ_1M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_aes0_hwmod,
+        .clk            = "aes0_fck",
+        .addr           = am33xx_aes0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
new file mode 100644
index 000000000000..0f178623e7da
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -0,0 +1,1469 @@
+/*
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ *
+ * Hwmod common for AM335x and AM43x
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include "omap_hwmod.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "omap_hwmod_33xx_43xx_common_data.h"
+#include "prcm43xx.h"
+
+#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
+#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
+#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+        .name           = "l3",
+};
+
+struct omap_hwmod am33xx_l3_main_hwmod = {
+        .name           = "l3_main",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l3_s */
+struct omap_hwmod am33xx_l3_s_hwmod = {
+        .name           = "l3_s",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+};
+
+/* l3_instr */
+struct omap_hwmod am33xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+struct omap_hwmod_class am33xx_l4_hwmod_class = {
+        .name           = "l4",
+};
+
+/* l4_ls */
+struct omap_hwmod am33xx_l4_ls_hwmod = {
+        .name           = "l4_ls",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l4_wkup */
+struct omap_hwmod am33xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+struct omap_hwmod am33xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &am33xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+        .name           = "wkup_m3",
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+        .name   = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+        { .name = "pruss", .rst_shift = 1 },
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+struct omap_hwmod am33xx_pruss_hwmod = {
+        .name           = "pruss",
+        .class          = &am33xx_pruss_hwmod_class,
+        .clkdm_name     = "pruss_ocp_clkdm",
+        .main_clk       = "pruss_ocp_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_pruss_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+        .name   = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+        { .name = "gfx", .rst_shift = 0, .st_shift = 0},
+};
+
+struct omap_hwmod am33xx_gfx_hwmod = {
+        .name           = "gfx",
+        .class          = &am33xx_gfx_hwmod_class,
+        .clkdm_name     = "gfx_l3_clkdm",
+        .main_clk       = "gfx_fck_div_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_gfx_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+        .name   = "prcm",
+};
+
+/* prcm */
+struct omap_hwmod am33xx_prcm_hwmod = {
+        .name           = "prcm",
+        .class          = &am33xx_prcm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/*
+ * 'aes0' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
+        .rev_offs       = 0x80,
+        .sysc_offs      = 0x84,
+        .syss_offs      = 0x88,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
+        .name           = "aes0",
+        .sysc           = &am33xx_aes0_sysc,
+};
+
+struct omap_hwmod am33xx_aes0_hwmod = {
+        .name           = "aes",
+        .class          = &am33xx_aes0_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .main_clk       = "aes0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* sha0 HIB2 (the 'P' (public) device) */
+static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
+        .rev_offs       = 0x100,
+        .sysc_offs      = 0x110,
+        .syss_offs      = 0x114,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+        .name           = "sha0",
+        .sysc           = &am33xx_sha0_sysc,
+};
+
+struct omap_hwmod am33xx_sha0_hwmod = {
+        .name           = "sham",
+        .class          = &am33xx_sha0_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+        .name = "ocmcram",
+};
+
+struct omap_hwmod am33xx_ocmcram_hwmod = {
+        .name           = "ocmcram",
+        .class          = &am33xx_ocmcram_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+        .name           = "smartreflex",
+};
+
+/* smartreflex0 */
+struct omap_hwmod am33xx_smartreflex0_hwmod = {
+        .name           = "smartreflex0",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .main_clk       = "smartreflex0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* smartreflex1 */
+struct omap_hwmod am33xx_smartreflex1_hwmod = {
+        .name           = "smartreflex1",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .main_clk       = "smartreflex1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'control' module class
+ */
+struct omap_hwmod_class am33xx_control_hwmod_class = {
+        .name           = "control",
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x8,
+        .syss_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+                           MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+        .name           = "cpgmac0",
+        .sysc           = &am33xx_cpgmac_sysc,
+};
+
+struct omap_hwmod am33xx_cpgmac0_hwmod = {
+        .name           = "cpgmac0",
+        .class          = &am33xx_cpgmac0_hwmod_class,
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "cpsw_125mhz_gclk",
+        .mpu_rt_idx     = 1,
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * mdio class
+ */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+        .name           = "davinci_mdio",
+};
+
+struct omap_hwmod am33xx_mdio_hwmod = {
+        .name           = "davinci_mdio",
+        .class          = &am33xx_mdio_hwmod_class,
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .main_clk       = "cpsw_125mhz_gclk",
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+        .name = "d_can",
+};
+
+/* dcan0 */
+struct omap_hwmod am33xx_dcan0_hwmod = {
+        .name           = "d_can0",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dcan0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* dcan1 */
+struct omap_hwmod am33xx_dcan1_hwmod = {
+        .name           = "d_can1",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dcan1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+        .name           = "elm",
+        .sysc           = &am33xx_elm_sysc,
+};
+
+struct omap_hwmod am33xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &am33xx_elm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* pwmss  */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                        MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+        .name           = "epwmss",
+        .sysc           = &am33xx_epwmss_sysc,
+};
+
+static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
+        .name           = "ecap",
+};
+
+static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
+        .name           = "eqep",
+};
+
+struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
+        .name           = "ehrpwm",
+};
+
+/* epwmss0 */
+struct omap_hwmod am33xx_epwmss0_hwmod = {
+        .name           = "epwmss0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap0 */
+struct omap_hwmod am33xx_ecap0_hwmod = {
+        .name           = "ecap0",
+        .class          = &am33xx_ecap_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* eqep0 */
+struct omap_hwmod am33xx_eqep0_hwmod = {
+        .name           = "eqep0",
+        .class          = &am33xx_eqep_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* ehrpwm0 */
+struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+        .name           = "ehrpwm0",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* epwmss1 */
+struct omap_hwmod am33xx_epwmss1_hwmod = {
+        .name           = "epwmss1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap1 */
+struct omap_hwmod am33xx_ecap1_hwmod = {
+        .name           = "ecap1",
+        .class          = &am33xx_ecap_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* eqep1 */
+struct omap_hwmod am33xx_eqep1_hwmod = {
+        .name           = "eqep1",
+        .class          = &am33xx_eqep_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* ehrpwm1 */
+struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+        .name           = "ehrpwm1",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* epwmss2 */
+struct omap_hwmod am33xx_epwmss2_hwmod = {
+        .name           = "epwmss2",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap2 */
+struct omap_hwmod am33xx_ecap2_hwmod = {
+        .name           = "ecap2",
+        .class          = &am33xx_ecap_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* eqep2 */
+struct omap_hwmod am33xx_eqep2_hwmod = {
+        .name           = "eqep2",
+        .class          = &am33xx_eqep_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/* ehrpwm2 */
+struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+        .name           = "ehrpwm2",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+        .name           = "gpio",
+        .sysc           = &am33xx_gpio_sysc,
+        .rev            = 2,
+};
+
+struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+struct omap_hwmod am33xx_gpio1_hwmod = {
+        .name           = "gpio2",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+struct omap_hwmod am33xx_gpio2_hwmod = {
+        .name           = "gpio3",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+struct omap_hwmod am33xx_gpio3_hwmod = {
+        .name           = "gpio4",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+        .name           = "gpmc",
+        .sysc           = &gpmc_sysc,
+};
+
+struct omap_hwmod am33xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &am33xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3s_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &am33xx_i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_2,
+        .reset          = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+struct omap_hwmod am33xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c1 */
+struct omap_hwmod am33xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4 = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c3 */
+struct omap_hwmod am33xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &am33xx_mailbox_sysc,
+};
+
+struct omap_hwmod am33xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &am33xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm = {
+                .omap4 = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+        .name           = "mcasp",
+        .sysc           = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+struct omap_hwmod am33xx_mcasp0_hwmod = {
+        .name           = "mcasp0",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .main_clk       = "mcasp0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mcasp1 */
+struct omap_hwmod am33xx_mcasp1_hwmod = {
+        .name           = "mcasp1",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .main_clk       = "mcasp1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+        .name           = "mmc",
+        .sysc           = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+struct omap_hwmod am33xx_mmc0_hwmod = {
+        .name           = "mmc1",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+struct omap_hwmod am33xx_mmc1_hwmod = {
+        .name           = "mmc2",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+struct omap_hwmod am33xx_mmc2_hwmod = {
+        .name           = "mmc3",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+        .rev_offs       = 0x0074,
+        .sysc_offs      = 0x0078,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
+                          SIDLE_SMART | SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+        .name           = "rtc",
+        .sysc           = &am33xx_rtc_sysc,
+};
+
+struct omap_hwmod am33xx_rtc_hwmod = {
+        .name           = "rtc",
+        .class          = &am33xx_rtc_hwmod_class,
+        .clkdm_name     = "l4_rtc_clkdm",
+        .main_clk       = "clk_32768_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0110,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class am33xx_spi_hwmod_class = {
+        .name           = "mcspi",
+        .sysc           = &am33xx_mcspi_sysc,
+        .rev            = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+struct omap2_mcspi_dev_attr mcspi_attrib = {
+        .num_chipselect = 2,
+};
+struct omap_hwmod am33xx_spi0_hwmod = {
+        .name           = "spi0",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+/* spi1 */
+struct omap_hwmod am33xx_spi1_hwmod = {
+        .name           = "spi1",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+
+static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+        .name           = "spinlock",
+        .sysc           = &am33xx_spinlock_sysc,
+};
+
+struct omap_hwmod am33xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &am33xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+struct omap_hwmod_class am33xx_timer_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer1ms_sysc,
+};
+
+struct omap_hwmod am33xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &am33xx_timer1ms_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .main_clk       = "timer1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer2_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer3_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer4_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer5_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer6_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer7_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+        .name           = "tpcc",
+};
+
+struct omap_hwmod am33xx_tpcc_hwmod = {
+        .name           = "tpcc",
+        .class          = &am33xx_tpcc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+        .name           = "tptc",
+        .sysc           = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+struct omap_hwmod am33xx_tptc0_hwmod = {
+        .name           = "tptc0",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tptc1 */
+struct omap_hwmod am33xx_tptc1_hwmod = {
+        .name           = "tptc1",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tptc2 */
+struct omap_hwmod am33xx_tptc2_hwmod = {
+        .name           = "tptc2",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name           = "uart",
+        .sysc           = &uart_sysc,
+};
+
+struct omap_hwmod am33xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &uart_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart3 */
+struct omap_hwmod am33xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+struct omap_hwmod am33xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE_ACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class_sysconfig wdt_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &wdt_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+struct omap_hwmod am33xx_wd_timer1_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &am33xx_wd_timer_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wdt1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static void omap_hwmod_am33xx_clkctrl(void)
+{
+        CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_smartreflex0_hwmod,
+                AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_smartreflex1_hwmod,
+                AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
+}
+
+static void omap_hwmod_am33xx_rst(void)
+{
+        RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
+        RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
+        RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
+}
+
+void omap_hwmod_am33xx_reg(void)
+{
+        omap_hwmod_am33xx_clkctrl();
+        omap_hwmod_am33xx_rst();
+}
+
+static void omap_hwmod_am43xx_clkctrl(void)
+{
+        CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_smartreflex0_hwmod,
+                AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_smartreflex1_hwmod,
+                AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
+        CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
+}
+
+static void omap_hwmod_am43xx_rst(void)
+{
+        RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
+        RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
+        RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
+}
+
+void omap_hwmod_am43xx_reg(void)
+{
+        omap_hwmod_am43xx_clkctrl();
+        omap_hwmod_am43xx_rst();
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 215894f8910d..6b406ca4bd3b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -29,6 +29,7 @@
 #include "i2c.h"
 #include "mmc.h"
 #include "wd_timer.h"
+#include "omap_hwmod_33xx_43xx_common_data.h"
 
 /*
  * IP blocks
@@ -52,7 +53,7 @@ static struct omap_hwmod am33xx_emif_hwmod = {
         .name           = "emif",
         .class          = &am33xx_emif_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "dpll_ddr_m2_div2_ck",
         .prcm           = {
                 .omap4  = {
@@ -62,79 +63,12 @@ static struct omap_hwmod am33xx_emif_hwmod = {
         },
 };
 
-/*
- * 'l3' class
- * instance(s): l3_main, l3_s, l3_instr
- */
-static struct omap_hwmod_class am33xx_l3_hwmod_class = {
-        .name           = "l3",
-};
-
-static struct omap_hwmod am33xx_l3_main_hwmod = {
-        .name           = "l3_main",
-        .class          = &am33xx_l3_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* l3_s */
-static struct omap_hwmod am33xx_l3_s_hwmod = {
-        .name           = "l3_s",
-        .class          = &am33xx_l3_hwmod_class,
-        .clkdm_name     = "l3s_clkdm",
-};
-
-/* l3_instr */
-static struct omap_hwmod am33xx_l3_instr_hwmod = {
-        .name           = "l3_instr",
-        .class          = &am33xx_l3_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * 'l4' class
- * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
- */
-static struct omap_hwmod_class am33xx_l4_hwmod_class = {
-        .name           = "l4",
-};
-
-/* l4_ls */
-static struct omap_hwmod am33xx_l4_ls_hwmod = {
-        .name           = "l4_ls",
-        .class          = &am33xx_l4_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /* l4_hs */
 static struct omap_hwmod am33xx_l4_hs_hwmod = {
         .name           = "l4_hs",
         .class          = &am33xx_l4_hwmod_class,
         .clkdm_name     = "l4hs_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "l4hs_gclk",
         .prcm           = {
                 .omap4  = {
@@ -144,50 +78,6 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = {
         },
 };
 
-
-/* l4_wkup */
-static struct omap_hwmod am33xx_l4_wkup_hwmod = {
-        .name           = "l4_wkup",
-        .class          = &am33xx_l4_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * 'mpu' class
- */
-static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
-        .name   = "mpu",
-};
-
-static struct omap_hwmod am33xx_mpu_hwmod = {
-        .name           = "mpu",
-        .class          = &am33xx_mpu_hwmod_class,
-        .clkdm_name     = "mpu_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "dpll_mpu_m2_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * 'wakeup m3' class
- * Wakeup controller sub-system under wakeup domain
- */
-static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
-        .name           = "wkup_m3",
-};
-
 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 };
@@ -213,78 +103,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 };
 
 /*
- * 'pru-icss' class
- * Programmable Real-Time Unit and Industrial Communication Subsystem
- */
-static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
-        .name   = "pruss",
-};
-
-static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
-        { .name = "pruss", .rst_shift = 1 },
-};
-
-/* pru-icss */
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod am33xx_pruss_hwmod = {
-        .name           = "pruss",
-        .class          = &am33xx_pruss_hwmod_class,
-        .clkdm_name     = "pruss_ocp_clkdm",
-        .main_clk       = "pruss_ocp_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
-                        .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .rst_lines      = am33xx_pruss_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
-};
-
-/* gfx */
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
-        .name   = "gfx",
-};
-
-static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-        { .name = "gfx", .rst_shift = 0, .st_shift = 0},
-};
-
-static struct omap_hwmod am33xx_gfx_hwmod = {
-        .name           = "gfx",
-        .class          = &am33xx_gfx_hwmod_class,
-        .clkdm_name     = "gfx_l3_clkdm",
-        .main_clk       = "gfx_fck_div_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
-                        .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
-                        .rstst_offs     = AM33XX_RM_GFX_RSTST_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .rst_lines      = am33xx_gfx_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
-};
-
-/*
- * 'prcm' class
- * power and reset manager (whole prcm infrastructure)
- */
-static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
-        .name   = "prcm",
-};
-
-/* prcm */
-static struct omap_hwmod am33xx_prcm_hwmod = {
-        .name           = "prcm",
-        .class          = &am33xx_prcm_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-};
-
-/*
  * 'adc/tsc' class
  * TouchScreen Controller (Anolog-To-Digital Converter)
  */
@@ -388,79 +206,6 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
 #endif
 
 /*
- * 'aes0' class
- */
-static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
-        .rev_offs       = 0x80,
-        .sysc_offs      = 0x84,
-        .syss_offs      = 0x88,
-        .sysc_flags     = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
-        .name           = "aes0",
-        .sysc           = &am33xx_aes0_sysc,
-};
-
-static struct omap_hwmod am33xx_aes0_hwmod = {
-        .name           = "aes",
-        .class          = &am33xx_aes0_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .main_clk       = "aes0_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
-        .rev_offs       = 0x100,
-        .sysc_offs      = 0x110,
-        .syss_offs      = 0x114,
-        .sysc_flags     = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
-        .name           = "sha0",
-        .sysc           = &am33xx_sha0_sysc,
-};
-
-static struct omap_hwmod am33xx_sha0_hwmod = {
-        .name           = "sham",
-        .class          = &am33xx_sha0_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* ocmcram */
-static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
-        .name = "ocmcram",
-};
-
-static struct omap_hwmod am33xx_ocmcram_hwmod = {
-        .name           = "ocmcram",
-        .class          = &am33xx_ocmcram_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'debugss' class
  * debug sub system
  */
@@ -488,51 +233,11 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
         .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
 };
 
-/* 'smartreflex' class */
-static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
-        .name           = "smartreflex",
-};
-
-/* smartreflex0 */
-static struct omap_hwmod am33xx_smartreflex0_hwmod = {
-        .name           = "smartreflex0",
-        .class          = &am33xx_smartreflex_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .main_clk       = "smartreflex0_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* smartreflex1 */
-static struct omap_hwmod am33xx_smartreflex1_hwmod = {
-        .name           = "smartreflex1",
-        .class          = &am33xx_smartreflex_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .main_clk       = "smartreflex1_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * 'control' module class
- */
-static struct omap_hwmod_class am33xx_control_hwmod_class = {
-        .name           = "control",
-};
-
 static struct omap_hwmod am33xx_control_hwmod = {
         .name           = "control",
         .class          = &am33xx_control_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "dpll_core_m4_div2_ck",
         .prcm           = {
                 .omap4  = {
@@ -542,288 +247,6 @@ static struct omap_hwmod am33xx_control_hwmod = {
         },
 };
 
-/*
- * 'cpgmac' class
- * cpsw/cpgmac sub system
- */
-static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x8,
-        .syss_offs      = 0x4,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
-                           MSTANDBY_NO),
-        .sysc_fields    = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
-        .name           = "cpgmac0",
-        .sysc           = &am33xx_cpgmac_sysc,
-};
-
-static struct omap_hwmod am33xx_cpgmac0_hwmod = {
-        .name           = "cpgmac0",
-        .class          = &am33xx_cpgmac0_hwmod_class,
-        .clkdm_name     = "cpsw_125mhz_clkdm",
-        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-        .main_clk       = "cpsw_125mhz_gclk",
-        .mpu_rt_idx     = 1,
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * mdio class
- */
-static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
-        .name           = "davinci_mdio",
-};
-
-static struct omap_hwmod am33xx_mdio_hwmod = {
-        .name           = "davinci_mdio",
-        .class          = &am33xx_mdio_hwmod_class,
-        .clkdm_name     = "cpsw_125mhz_clkdm",
-        .main_clk       = "cpsw_125mhz_gclk",
-};
-
-/*
- * dcan class
- */
-static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
-        .name = "d_can",
-};
-
-/* dcan0 */
-static struct omap_hwmod am33xx_dcan0_hwmod = {
-        .name           = "d_can0",
-        .class          = &am33xx_dcan_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "dcan0_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* dcan1 */
-static struct omap_hwmod am33xx_dcan1_hwmod = {
-        .name           = "d_can1",
-        .class          = &am33xx_dcan_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "dcan1_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* elm */
-static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-                        SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_elm_hwmod_class = {
-        .name           = "elm",
-        .sysc           = &am33xx_elm_sysc,
-};
-
-static struct omap_hwmod am33xx_elm_hwmod = {
-        .name           = "elm",
-        .class          = &am33xx_elm_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* pwmss  */
-static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x4,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                        SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                        MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
-        .name           = "epwmss",
-        .sysc           = &am33xx_epwmss_sysc,
-};
-
-static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
-        .name           = "ecap",
-};
-
-static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
-        .name           = "eqep",
-};
-
-static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
-        .name           = "ehrpwm",
-};
-
-/* epwmss0 */
-static struct omap_hwmod am33xx_epwmss0_hwmod = {
-        .name           = "epwmss0",
-        .class          = &am33xx_epwmss_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* ecap0 */
-static struct omap_hwmod am33xx_ecap0_hwmod = {
-        .name           = "ecap0",
-        .class          = &am33xx_ecap_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* eqep0 */
-static struct omap_hwmod am33xx_eqep0_hwmod = {
-        .name           = "eqep0",
-        .class          = &am33xx_eqep_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* ehrpwm0 */
-static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
-        .name           = "ehrpwm0",
-        .class          = &am33xx_ehrpwm_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* epwmss1 */
-static struct omap_hwmod am33xx_epwmss1_hwmod = {
-        .name           = "epwmss1",
-        .class          = &am33xx_epwmss_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* ecap1 */
-static struct omap_hwmod am33xx_ecap1_hwmod = {
-        .name           = "ecap1",
-        .class          = &am33xx_ecap_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* eqep1 */
-static struct omap_hwmod am33xx_eqep1_hwmod = {
-        .name           = "eqep1",
-        .class          = &am33xx_eqep_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* ehrpwm1 */
-static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
-        .name           = "ehrpwm1",
-        .class          = &am33xx_ehrpwm_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* epwmss2 */
-static struct omap_hwmod am33xx_epwmss2_hwmod = {
-        .name           = "epwmss2",
-        .class          = &am33xx_epwmss_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* ecap2 */
-static struct omap_hwmod am33xx_ecap2_hwmod = {
-        .name           = "ecap2",
-        .class          = &am33xx_ecap_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* eqep2 */
-static struct omap_hwmod am33xx_eqep2_hwmod = {
-        .name           = "eqep2",
-        .class          = &am33xx_eqep_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/* ehrpwm2 */
-static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
-        .name           = "ehrpwm2",
-        .class          = &am33xx_ehrpwm_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-};
-
-/*
- * 'gpio' class: for gpio 0,1,2,3
- */
-static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0114,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                          SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                          SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
-        .name           = "gpio",
-        .sysc           = &am33xx_gpio_sysc,
-        .rev            = 2,
-};
-
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-        .bank_width     = 32,
-        .dbck_flag      = true,
-};
-
 /* gpio0 */
 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio0_dbclk" },
@@ -846,174 +269,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
         .dev_attr       = &gpio_dev_attr,
 };
 
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio1_hwmod = {
-        .name           = "gpio2",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio1_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio2_hwmod = {
-        .name           = "gpio3",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio2_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio3_hwmod = {
-        .name           = "gpio4",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio3_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpmc */
-static struct omap_hwmod_class_sysconfig gpmc_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x10,
-        .syss_offs      = 0x14,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
-                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
-        .name           = "gpmc",
-        .sysc           = &gpmc_sysc,
-};
-
-static struct omap_hwmod am33xx_gpmc_hwmod = {
-        .name           = "gpmc",
-        .class          = &am33xx_gpmc_hwmod_class,
-        .clkdm_name     = "l3s_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .main_clk       = "l3s_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* 'i2c' class */
-static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0090,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
-                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
-        .name           = "i2c",
-        .sysc           = &am33xx_i2c_sysc,
-        .rev            = OMAP_I2C_IP_VERSION_2,
-        .reset          = &omap_i2c_reset,
-};
-
-static struct omap_i2c_dev_attr i2c_dev_attr = {
-        .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
-};
-
-/* i2c1 */
-static struct omap_hwmod am33xx_i2c1_hwmod = {
-        .name           = "i2c1",
-        .class          = &i2c_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &i2c_dev_attr,
-};
-
-/* i2c1 */
-static struct omap_hwmod am33xx_i2c2_hwmod = {
-        .name           = "i2c2",
-        .class          = &i2c_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4 = {
-                        .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &i2c_dev_attr,
-};
-
-/* i2c3 */
-static struct omap_hwmod am33xx_i2c3_hwmod = {
-        .name           = "i2c3",
-        .class          = &i2c_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &i2c_dev_attr,
-};
-
-
 /* lcdc */
 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
         .rev_offs       = 0x0,
@@ -1043,600 +298,6 @@ static struct omap_hwmod am33xx_lcdc_hwmod = {
 };
 
 /*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
-        .name   = "mailbox",
-        .sysc   = &am33xx_mailbox_sysc,
-};
-
-static struct omap_hwmod am33xx_mailbox_hwmod = {
-        .name           = "mailbox",
-        .class          = &am33xx_mailbox_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * 'mcasp' class
- */
-static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x4,
-        .sysc_flags     = SYSC_HAS_SIDLEMODE,
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
-        .name           = "mcasp",
-        .sysc           = &am33xx_mcasp_sysc,
-};
-
-/* mcasp0 */
-static struct omap_hwmod am33xx_mcasp0_hwmod = {
-        .name           = "mcasp0",
-        .class          = &am33xx_mcasp_hwmod_class,
-        .clkdm_name     = "l3s_clkdm",
-        .main_clk       = "mcasp0_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mcasp1 */
-static struct omap_hwmod am33xx_mcasp1_hwmod = {
-        .name           = "mcasp1",
-        .class          = &am33xx_mcasp_hwmod_class,
-        .clkdm_name     = "l3s_clkdm",
-        .main_clk       = "mcasp1_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* 'mmc' class */
-static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
-        .rev_offs       = 0x1fc,
-        .sysc_offs      = 0x10,
-        .syss_offs      = 0x14,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
-        .name           = "mmc",
-        .sysc           = &am33xx_mmc_sysc,
-};
-
-/* mmc0 */
-static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
-        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod am33xx_mmc0_hwmod = {
-        .name           = "mmc1",
-        .class          = &am33xx_mmc_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "mmc_clk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &am33xx_mmc0_dev_attr,
-};
-
-/* mmc1 */
-static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
-        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod am33xx_mmc1_hwmod = {
-        .name           = "mmc2",
-        .class          = &am33xx_mmc_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "mmc_clk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &am33xx_mmc1_dev_attr,
-};
-
-/* mmc2 */
-static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
-        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-static struct omap_hwmod am33xx_mmc2_hwmod = {
-        .name           = "mmc3",
-        .class          = &am33xx_mmc_hwmod_class,
-        .clkdm_name     = "l3s_clkdm",
-        .main_clk       = "mmc_clk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &am33xx_mmc2_dev_attr,
-};
-
-/*
- * 'rtc' class
- * rtc subsystem
- */
-static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
-        .rev_offs       = 0x0074,
-        .sysc_offs      = 0x0078,
-        .sysc_flags     = SYSC_HAS_SIDLEMODE,
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
-                          SIDLE_SMART | SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
-        .name           = "rtc",
-        .sysc           = &am33xx_rtc_sysc,
-};
-
-static struct omap_hwmod am33xx_rtc_hwmod = {
-        .name           = "rtc",
-        .class          = &am33xx_rtc_hwmod_class,
-        .clkdm_name     = "l4_rtc_clkdm",
-        .main_clk       = "clk_32768_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* 'spi' class */
-static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0110,
-        .syss_offs      = 0x0114,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-                          SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_spi_hwmod_class = {
-        .name           = "mcspi",
-        .sysc           = &am33xx_mcspi_sysc,
-        .rev            = OMAP4_MCSPI_REV,
-};
-
-/* spi0 */
-static struct omap2_mcspi_dev_attr mcspi_attrib = {
-        .num_chipselect = 2,
-};
-static struct omap_hwmod am33xx_spi0_hwmod = {
-        .name           = "spi0",
-        .class          = &am33xx_spi_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &mcspi_attrib,
-};
-
-/* spi1 */
-static struct omap_hwmod am33xx_spi1_hwmod = {
-        .name           = "spi1",
-        .class          = &am33xx_spi_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &mcspi_attrib,
-};
-
-/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the
- * processes running on multiple processors
- */
-static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
-        .name           = "spinlock",
-};
-
-static struct omap_hwmod am33xx_spinlock_hwmod = {
-        .name           = "spinlock",
-        .class          = &am33xx_spinlock_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* 'timer 2-7' class */
-static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_timer_hwmod_class = {
-        .name           = "timer",
-        .sysc           = &am33xx_timer_sysc,
-};
-
-/* timer1 1ms */
-static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
-                        SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
-        .name           = "timer",
-        .sysc           = &am33xx_timer1ms_sysc,
-};
-
-static struct omap_hwmod am33xx_timer1_hwmod = {
-        .name           = "timer1",
-        .class          = &am33xx_timer1ms_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .main_clk       = "timer1_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_timer2_hwmod = {
-        .name           = "timer2",
-        .class          = &am33xx_timer_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "timer2_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_timer3_hwmod = {
-        .name           = "timer3",
-        .class          = &am33xx_timer_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "timer3_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_timer4_hwmod = {
-        .name           = "timer4",
-        .class          = &am33xx_timer_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "timer4_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_timer5_hwmod = {
-        .name           = "timer5",
-        .class          = &am33xx_timer_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "timer5_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_timer6_hwmod = {
-        .name           = "timer6",
-        .class          = &am33xx_timer_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "timer6_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_timer7_hwmod = {
-        .name           = "timer7",
-        .class          = &am33xx_timer_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "timer7_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* tpcc */
-static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
-        .name           = "tpcc",
-};
-
-static struct omap_hwmod am33xx_tpcc_hwmod = {
-        .name           = "tpcc",
-        .class          = &am33xx_tpcc_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x10,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                          SYSC_HAS_MIDLEMODE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-/* 'tptc' class */
-static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
-        .name           = "tptc",
-        .sysc           = &am33xx_tptc_sysc,
-};
-
-/* tptc0 */
-static struct omap_hwmod am33xx_tptc0_hwmod = {
-        .name           = "tptc0",
-        .class          = &am33xx_tptc_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* tptc1 */
-static struct omap_hwmod am33xx_tptc1_hwmod = {
-        .name           = "tptc1",
-        .class          = &am33xx_tptc_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* tptc2 */
-static struct omap_hwmod am33xx_tptc2_hwmod = {
-        .name           = "tptc2",
-        .class          = &am33xx_tptc_hwmod_class,
-        .clkdm_name     = "l3_clkdm",
-        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-        .main_clk       = "l3_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* 'uart' class */
-static struct omap_hwmod_class_sysconfig uart_sysc = {
-        .rev_offs       = 0x50,
-        .sysc_offs      = 0x54,
-        .syss_offs      = 0x58,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
-                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
-        .name           = "uart",
-        .sysc           = &uart_sysc,
-};
-
-/* uart1 */
-static struct omap_hwmod am33xx_uart1_hwmod = {
-        .name           = "uart1",
-        .class          = &uart_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_uart2_hwmod = {
-        .name           = "uart2",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart3 */
-static struct omap_hwmod am33xx_uart3_hwmod = {
-        .name           = "uart3",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_uart4_hwmod = {
-        .name           = "uart4",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_uart5_hwmod = {
-        .name           = "uart5",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-static struct omap_hwmod am33xx_uart6_hwmod = {
-        .name           = "uart6",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* 'wd_timer' class */
-static struct omap_hwmod_class_sysconfig wdt_sysc = {
-        .rev_offs       = 0x0,
-        .sysc_offs      = 0x10,
-        .syss_offs      = 0x14,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
-                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                        SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
-        .name           = "wd_timer",
-        .sysc           = &wdt_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable,
-};
-
-/*
- * XXX: device.c file uses hardcoded name for watchdog timer
- * driver "wd_timer2, so we are also using same name as of now...
- */
-static struct omap_hwmod am33xx_wd_timer1_hwmod = {
-        .name           = "wd_timer2",
-        .class          = &am33xx_wd_timer_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE,
-        .main_clk       = "wdt1_fck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'usb_otg' class
  * high-speed on-the-go universal serial bus (usb_otg) controller
  */
@@ -1690,14 +351,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* mpu -> l3 main */
-static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
-        .master         = &am33xx_mpu_hwmod,
-        .slave          = &am33xx_l3_main_hwmod,
-        .clk            = "dpll_mpu_m2_ck",
-        .user           = OCP_USER_MPU,
-};
-
 /* l3 main -> l4 hs */
 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
         .master         = &am33xx_l3_main_hwmod,
@@ -1706,62 +359,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3 main -> l3 s */
-static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_l3_s_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 s -> l4 per/ls */
-static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_l4_ls_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 s -> l4 wkup */
-static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_l4_wkup_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 main -> l3 instr */
-static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_l3_instr_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> prcm */
-static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
-        .master         = &am33xx_mpu_hwmod,
-        .slave          = &am33xx_prcm_hwmod,
-        .clk            = "dpll_mpu_m2_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 s -> l3 main*/
-static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_l3_main_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* pru-icss -> l3 main */
-static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
-        .master         = &am33xx_pruss_hwmod,
-        .slave          = &am33xx_l3_main_hwmod,
-        .clk            = "l3_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* wkup m3 -> l4 wkup */
 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
         .master         = &am33xx_wkup_m3_hwmod,
@@ -1770,14 +367,6 @@ static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* gfx -> l3 main */
-static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
-        .master         = &am33xx_gfx_hwmod,
-        .slave          = &am33xx_l3_main_hwmod,
-        .clk            = "dpll_core_m4_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4 wkup -> wkup m3 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -1794,14 +383,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3 main -> gfx */
-static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_gfx_hwmod,
-        .clk            = "dpll_core_m4_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main -> debugss */
 static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
         {
@@ -1844,54 +425,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
         .user           = OCP_USER_MPU,
 };
 
-/* l4 wkup -> rtc */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am33xx_rtc_hwmod,
-        .clk            = "clkdiv32k_ick",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 per/ls -> DCAN0 */
-static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_dcan0_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> DCAN1 */
-static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_dcan1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> GPIO2 */
-static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_gpio1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> gpio3 */
-static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_gpio2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> gpio4 */
-static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_gpio3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* L4 WKUP -> I2C1 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -1933,177 +466,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
-        .master         = &am33xx_cpgmac0_hwmod,
-        .slave          = &am33xx_mdio_hwmod,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
-        {
-                .pa_start       = 0x48080000,
-                .pa_end         = 0x48080000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_elm_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_elm_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
-        {
-                .pa_start       = 0x48300000,
-                .pa_end         = 0x48300000 + SZ_16 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_epwmss0_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_epwmss0_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
-        .master         = &am33xx_epwmss0_hwmod,
-        .slave          = &am33xx_ecap0_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
-        .master         = &am33xx_epwmss0_hwmod,
-        .slave          = &am33xx_eqep0_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
-        .master         = &am33xx_epwmss0_hwmod,
-        .slave          = &am33xx_ehrpwm0_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-
-static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
-        {
-                .pa_start       = 0x48302000,
-                .pa_end         = 0x48302000 + SZ_16 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_epwmss1_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_epwmss1_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
-        .master         = &am33xx_epwmss1_hwmod,
-        .slave          = &am33xx_ecap1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
-        .master         = &am33xx_epwmss1_hwmod,
-        .slave          = &am33xx_eqep1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
-        .master         = &am33xx_epwmss1_hwmod,
-        .slave          = &am33xx_ehrpwm1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
-        {
-                .pa_start       = 0x48304000,
-                .pa_end         = 0x48304000 + SZ_16 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_epwmss2_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_epwmss2_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
-        .master         = &am33xx_epwmss2_hwmod,
-        .slave          = &am33xx_ecap2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
-        .master         = &am33xx_epwmss2_hwmod,
-        .slave          = &am33xx_eqep2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
-        .master         = &am33xx_epwmss2_hwmod,
-        .slave          = &am33xx_ehrpwm2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l3s cfg -> gpmc */
-static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
-        {
-                .pa_start       = 0x50000000,
-                .pa_end         = 0x50000000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_gpmc_hwmod,
-        .clk            = "l3s_gclk",
-        .addr           = am33xx_gpmc_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* i2c2 */
-static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_i2c2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_i2c3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
         {
                 .pa_start       = 0x4830E000,
@@ -2121,138 +483,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x480C8000,
-                .pa_end         = 0x480C8000 + (SZ_4K - 1),
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4 ls -> mailbox */
-static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mailbox_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mailbox_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> spinlock */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_spinlock_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcasp0 */
-static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
-        {
-                .pa_start       = 0x48038000,
-                .pa_end         = 0x48038000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mcasp0_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mcasp0_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcasp1 */
-static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
-        {
-                .pa_start       = 0x4803C000,
-                .pa_end         = 0x4803C000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mcasp1_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mcasp1_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mmc0 */
-static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
-        {
-                .pa_start       = 0x48060100,
-                .pa_end         = 0x48060100 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mmc0_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mmc0_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mmc1 */
-static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
-        {
-                .pa_start       = 0x481d8100,
-                .pa_end         = 0x481d8100 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mmc1_hwmod,
-        .clk            = "l4ls_gclk",
-        .addr           = am33xx_mmc1_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l3 s -> mmc2 */
-static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
-        {
-                .pa_start       = 0x47810100,
-                .pa_end         = 0x47810100 + SZ_64K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_mmc2_hwmod,
-        .clk            = "l3s_gclk",
-        .addr           = am33xx_mmc2_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcspi0 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_spi0_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcspi1 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_spi1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 /* l4 wkup -> timer1 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -2261,116 +491,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l4 per -> timer2 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_timer2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 per -> timer3 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_timer3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 per -> timer4 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_timer4_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 per -> timer5 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_timer5_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 per -> timer6 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_timer6_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 per -> timer7 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_timer7_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc */
-static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_tpcc_hwmod,
-        .clk            = "l3_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc0 */
-static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
-        {
-                .pa_start       = 0x49800000,
-                .pa_end         = 0x49800000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_tptc0_hwmod,
-        .clk            = "l3_gclk",
-        .addr           = am33xx_tptc0_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc1 */
-static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
-        {
-                .pa_start       = 0x49900000,
-                .pa_end         = 0x49900000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_tptc1_hwmod,
-        .clk            = "l3_gclk",
-        .addr           = am33xx_tptc1_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc2 */
-static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
-        {
-                .pa_start       = 0x49a00000,
-                .pa_end         = 0x49a00000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_tptc2_hwmod,
-        .clk            = "l3_gclk",
-        .addr           = am33xx_tptc2_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
 /* l4 wkup -> uart1 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -2379,46 +499,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l4 ls -> uart2 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart3 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart4 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart4_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart5 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart5_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart6 */
-static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart6_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 /* l4 wkup -> wd_timer1 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -2437,47 +517,39 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
         .flags          = OCPIF_SWSUP_IDLE,
 };
 
-/* l3 main -> ocmc */
-static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_ocmcram_hwmod,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 main -> sha0 HIB2 */
-static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
-        {
-                .pa_start       = 0x53100000,
-                .pa_end         = 0x53100000 + SZ_512 - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
+/* rng */
+static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
+        .rev_offs       = 0x1fe0,
+        .sysc_offs      = 0x1fe4,
+        .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
+        .idlemodes      = SIDLE_FORCE | SIDLE_NO,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
-static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_sha0_hwmod,
-        .clk            = "sha0_fck",
-        .addr           = am33xx_sha0_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class am33xx_rng_hwmod_class = {
+        .name           = "rng",
+        .sysc           = &am33xx_rng_sysc,
 };
 
-/* l3 main -> AES0 HIB2 */
-static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
-        {
-                .pa_start       = 0x53500000,
-                .pa_end         = 0x53500000 + SZ_1M - 1,
-                .flags          = ADDR_TYPE_RT
+static struct omap_hwmod am33xx_rng_hwmod = {
+        .name           = "rng",
+        .class          = &am33xx_rng_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "rng_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
         },
-        { }
 };
 
-static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
-        .master         = &am33xx_l3_main_hwmod,
-        .slave          = &am33xx_aes0_hwmod,
-        .clk            = "aes0_fck",
-        .addr           = am33xx_aes0_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_rng_hwmod,
+        .clk            = "rng_fck",
+        .user           = OCP_USER_MPU,
 };
 
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
@@ -2559,11 +631,13 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_cpgmac0__mdio,
         &am33xx_l3_main__sha0,
         &am33xx_l3_main__aes0,
+        &am33xx_l4_per__rng,
         NULL,
 };
 
 int __init am33xx_hwmod_init(void)
 {
+        omap_hwmod_am33xx_reg();
         omap_hwmod_init();
         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 0c3a427da544..9e56fabd7fa3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3693,6 +3693,53 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/*
+ * 'ssi' class
+ * synchronous serial interface (multichannel and full-duplex serial if)
+ */
+
+static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
+        .name   = "ssi",
+        .sysc   = &omap34xx_ssi_sysc,
+};
+
+static struct omap_hwmod omap34xx_ssi_hwmod = {
+        .name           = "ssi",
+        .class          = &omap34xx_ssi_hwmod_class,
+        .clkdm_name     = "core_l4_clkdm",
+        .main_clk       = "ssi_ssr_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id            = 1,
+                        .module_bit             = OMAP3430_EN_SSI_SHIFT,
+                        .module_offs            = CORE_MOD,
+                        .idlest_reg_id          = 1,
+                        .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
+                },
+        },
+};
+
+/* L4 CORE -> SSI */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_ssi_hwmod,
+        .clk            = "ssi_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
@@ -3818,6 +3865,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
 #ifdef CONFIG_OMAP_IOMMU_IVA2
         &omap3xxx_l3_main__mmu_iva,
 #endif
+        &omap34xx_l4_core__ssi,
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
new file mode 100644
index 000000000000..9002fca76699
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -0,0 +1,758 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ *
+ * Hwmod present only in AM43x and those that differ other than register
+ * offsets as compared to AM335x.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include "omap_hwmod.h"
+#include "omap_hwmod_33xx_43xx_common_data.h"
+#include "prcm43xx.h"
+
+/* IP blocks */
+static struct omap_hwmod am43xx_l4_hs_hwmod = {
+        .name           = "l4_hs",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "l4hs_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+        { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod am43xx_wkup_m3_hwmod = {
+        .name           = "wkup_m3",
+        .class          = &am33xx_wkup_m3_hwmod_class,
+        .clkdm_name     = "l4_wkup_aon_clkdm",
+        /* Keep hardreset asserted */
+        .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
+        .main_clk       = "sys_clkin_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
+                        .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_wkup_m3_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+static struct omap_hwmod am43xx_control_hwmod = {
+        .name           = "control",
+        .class          = &am33xx_control_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE,
+        .main_clk       = "sys_clkin_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod am43xx_gpio0_hwmod = {
+        .name           = "gpio1",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "sys_clkin_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio0_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
+        .name   = "synctimer",
+        .sysc   = &am43xx_synctimer_sysc,
+};
+
+static struct omap_hwmod am43xx_synctimer_hwmod = {
+        .name           = "counter_32k",
+        .class          = &am43xx_synctimer_hwmod_class,
+        .clkdm_name     = "l4_wkup_aon_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "synctimer_32kclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer8_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer9_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer10_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "timer11_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_epwmss3_hwmod = {
+        .name           = "epwmss3",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
+        .name           = "ehrpwm3",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+static struct omap_hwmod am43xx_epwmss4_hwmod = {
+        .name           = "epwmss4",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
+        .name           = "ehrpwm4",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+static struct omap_hwmod am43xx_epwmss5_hwmod = {
+        .name           = "epwmss5",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
+        .name           = "ehrpwm5",
+        .class          = &am33xx_ehrpwm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+};
+
+static struct omap_hwmod am43xx_spi2_hwmod = {
+        .name           = "spi2",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+static struct omap_hwmod am43xx_spi3_hwmod = {
+        .name           = "spi3",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+static struct omap_hwmod am43xx_spi4_hwmod = {
+        .name           = "spi4",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod am43xx_gpio4_hwmod = {
+        .name           = "gpio5",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod am43xx_gpio5_hwmod = {
+        .name           = "gpio6",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
+        .name   = "ocp2scp",
+};
+
+static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
+        .name           = "ocp2scp0",
+        .class          = &am43xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
+        .name           = "ocp2scp1",
+        .class          = &am43xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+                                SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                                SIDLE_SMART_WKUP | MSTANDBY_FORCE |
+                                MSTANDBY_NO | MSTANDBY_SMART |
+                                MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
+        .name   = "usb_otg_ss",
+        .sysc   = &am43xx_usb_otg_ss_sysc,
+};
+
+static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
+        .name           = "usb_otg_ss0",
+        .class          = &am43xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .main_clk       = "l3s_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
+        .name           = "usb_otg_ss1",
+        .class          = &am43xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .main_clk       = "l3s_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                                SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
+        .name   = "qspi",
+        .sysc   = &am43xx_qspi_sysc,
+};
+
+static struct omap_hwmod am43xx_qspi_hwmod = {
+        .name           = "qspi",
+        .class          = &am43xx_qspi_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .main_clk       = "l3s_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* Interfaces */
+static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am43xx_l4_hs_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
+        .master         = &am43xx_wkup_m3_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am43xx_wkup_m3_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_pruss_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex0_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex1_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am43xx_control_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_i2c1_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am43xx_gpio0_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
+        .master         = &am43xx_l4_hs_hwmod,
+        .slave          = &am33xx_cpgmac0_hwmod,
+        .clk            = "cpsw_125mhz_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_timer1_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_uart1_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wd_timer1_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am43xx_synctimer_hwmod,
+        .clk            = "sys_clkin_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_timer8_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_timer9_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_timer10_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_timer11_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_epwmss3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
+        .master         = &am43xx_epwmss3_hwmod,
+        .slave          = &am43xx_ehrpwm3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_epwmss4_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
+        .master         = &am43xx_epwmss4_hwmod,
+        .slave          = &am43xx_ehrpwm4_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_epwmss5_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
+        .master         = &am43xx_epwmss5_hwmod,
+        .slave          = &am43xx_ehrpwm5_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_spi2_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_spi3_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_spi4_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_gpio4_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_gpio5_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_ocp2scp0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_ocp2scp1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am43xx_usb_otg_ss0_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am43xx_usb_otg_ss1_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am43xx_qspi_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
+        &am33xx_l4_wkup__synctimer,
+        &am43xx_l4_ls__timer8,
+        &am43xx_l4_ls__timer9,
+        &am43xx_l4_ls__timer10,
+        &am43xx_l4_ls__timer11,
+        &am43xx_l4_ls__epwmss3,
+        &am43xx_epwmss3__ehrpwm3,
+        &am43xx_l4_ls__epwmss4,
+        &am43xx_epwmss4__ehrpwm4,
+        &am43xx_l4_ls__epwmss5,
+        &am43xx_epwmss5__ehrpwm5,
+        &am43xx_l4_ls__mcspi2,
+        &am43xx_l4_ls__mcspi3,
+        &am43xx_l4_ls__mcspi4,
+        &am43xx_l4_ls__gpio4,
+        &am43xx_l4_ls__gpio5,
+        &am43xx_l3_main__pruss,
+        &am33xx_mpu__l3_main,
+        &am33xx_mpu__prcm,
+        &am33xx_l3_s__l4_ls,
+        &am33xx_l3_s__l4_wkup,
+        &am43xx_l3_main__l4_hs,
+        &am33xx_l3_main__l3_s,
+        &am33xx_l3_main__l3_instr,
+        &am33xx_l3_main__gfx,
+        &am33xx_l3_s__l3_main,
+        &am33xx_pruss__l3_main,
+        &am43xx_wkup_m3__l4_wkup,
+        &am33xx_gfx__l3_main,
+        &am43xx_l4_wkup__wkup_m3,
+        &am43xx_l4_wkup__control,
+        &am43xx_l4_wkup__smartreflex0,
+        &am43xx_l4_wkup__smartreflex1,
+        &am43xx_l4_wkup__uart1,
+        &am43xx_l4_wkup__timer1,
+        &am43xx_l4_wkup__i2c1,
+        &am43xx_l4_wkup__gpio0,
+        &am43xx_l4_wkup__wd_timer1,
+        &am43xx_l3_s__qspi,
+        &am33xx_l4_per__dcan0,
+        &am33xx_l4_per__dcan1,
+        &am33xx_l4_per__gpio1,
+        &am33xx_l4_per__gpio2,
+        &am33xx_l4_per__gpio3,
+        &am33xx_l4_per__i2c2,
+        &am33xx_l4_per__i2c3,
+        &am33xx_l4_per__mailbox,
+        &am33xx_l4_ls__mcasp0,
+        &am33xx_l4_ls__mcasp1,
+        &am33xx_l4_ls__mmc0,
+        &am33xx_l4_ls__mmc1,
+        &am33xx_l3_s__mmc2,
+        &am33xx_l4_ls__timer2,
+        &am33xx_l4_ls__timer3,
+        &am33xx_l4_ls__timer4,
+        &am33xx_l4_ls__timer5,
+        &am33xx_l4_ls__timer6,
+        &am33xx_l4_ls__timer7,
+        &am33xx_l3_main__tpcc,
+        &am33xx_l4_ls__uart2,
+        &am33xx_l4_ls__uart3,
+        &am33xx_l4_ls__uart4,
+        &am33xx_l4_ls__uart5,
+        &am33xx_l4_ls__uart6,
+        &am33xx_l4_ls__elm,
+        &am33xx_l4_ls__epwmss0,
+        &am33xx_epwmss0__ecap0,
+        &am33xx_epwmss0__eqep0,
+        &am33xx_epwmss0__ehrpwm0,
+        &am33xx_l4_ls__epwmss1,
+        &am33xx_epwmss1__ecap1,
+        &am33xx_epwmss1__eqep1,
+        &am33xx_epwmss1__ehrpwm1,
+        &am33xx_l4_ls__epwmss2,
+        &am33xx_epwmss2__ecap2,
+        &am33xx_epwmss2__eqep2,
+        &am33xx_epwmss2__ehrpwm2,
+        &am33xx_l3_s__gpmc,
+        &am33xx_l4_ls__mcspi0,
+        &am33xx_l4_ls__mcspi1,
+        &am33xx_l3_main__tptc0,
+        &am33xx_l3_main__tptc1,
+        &am33xx_l3_main__tptc2,
+        &am33xx_l3_main__ocmc,
+        &am43xx_l4_hs__cpgmac0,
+        &am33xx_cpgmac0__mdio,
+        &am33xx_l3_main__sha0,
+        &am33xx_l3_main__aes0,
+        &am43xx_l4_ls__ocp2scp0,
+        &am43xx_l4_ls__ocp2scp1,
+        &am43xx_l3_s__usbotgss0,
+        &am43xx_l3_s__usbotgss1,
+        NULL,
+};
+
+int __init am43xx_hwmod_init(void)
+{
+        omap_hwmod_am43xx_reg();
+        omap_hwmod_init();
+        return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 9c3b504477d7..1e5b12cb8246 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -914,7 +914,7 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
         .name           = "emif1",
         .class          = &omap44xx_emif_hwmod_class,
         .clkdm_name     = "l3_emif_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "ddrphy_ck",
         .prcm = {
                 .omap4 = {
@@ -930,7 +930,7 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
         .name           = "emif2",
         .class          = &omap44xx_emif_hwmod_class,
         .clkdm_name     = "l3_emif_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "ddrphy_ck",
         .prcm = {
                 .omap4 = {
@@ -2193,7 +2193,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &omap44xx_mpu_hwmod_class,
         .clkdm_name     = "mpuss_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "dpll_mpu_m2_ck",
         .prcm = {
                 .omap4 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index cde415570e04..9e08d6994a0b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -352,7 +352,7 @@ static struct omap_hwmod omap54xx_emif1_hwmod = {
         .name           = "emif1",
         .class          = &omap54xx_emif_hwmod_class,
         .clkdm_name     = "emif_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "dpll_core_h11x2_ck",
         .prcm = {
                 .omap4 = {
@@ -368,7 +368,7 @@ static struct omap_hwmod omap54xx_emif2_hwmod = {
         .name           = "emif2",
         .class          = &omap54xx_emif_hwmod_class,
         .clkdm_name     = "emif_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "dpll_core_h11x2_ck",
         .prcm = {
                 .omap4 = {
@@ -1135,7 +1135,7 @@ static struct omap_hwmod omap54xx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &omap54xx_mpu_hwmod_class,
         .clkdm_name     = "mpu_clkdm",
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .flags          = HWMOD_INIT_NO_IDLE,
         .main_clk       = "dpll_mpu_m2_ck",
         .prcm = {
                 .omap4 = {
@@ -1146,6 +1146,77 @@ static struct omap_hwmod omap54xx_mpu_hwmod = {
 };
 
 /*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the processes
+ * running on multiple processors
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
+        .name   = "spinlock",
+        .sysc   = &omap54xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod omap54xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &omap54xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
+        .name   = "ocp2scp",
+        .sysc   = &omap54xx_ocp2scp_sysc,
+};
+
+/* ocp2scp1 */
+static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
+        .name           = "ocp2scp1",
+        .class          = &omap54xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
  * 'timer' class
  * general purpose timer module with accurate 1ms tick
  * This class contains several variants: ['timer_1ms', 'timer']
@@ -1465,6 +1536,123 @@ static struct omap_hwmod omap54xx_uart6_hwmod = {
 };
 
 /*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
+        .name   = "usb_host_hs",
+        .sysc   = &omap54xx_usb_host_hs_sysc,
+};
+
+static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap54xx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
+        .main_clk       = "l3init_60m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
+        .name   = "usb_tll_hs",
+        .sysc   = &omap54xx_usb_tll_hs_sysc,
+};
+
+static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap54xx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
  * 'usb_otg_ss' class
  * 2.0 super speed (usb_otg_ss) controller
  */
@@ -1960,6 +2148,22 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_spinlock_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> ocp2scp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_ocp2scp1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
         .master         = &omap54xx_l4_wkup_hwmod,
@@ -2096,6 +2300,22 @@ static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> usb_host_hs */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_usb_host_hs_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> usb_tll_hs */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_usb_tll_hs_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_cfg -> usb_otg_ss */
 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
         .master         = &omap54xx_l4_cfg_hwmod,
@@ -2163,6 +2383,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l4_per__mmc4,
         &omap54xx_l4_per__mmc5,
         &omap54xx_l4_cfg__mpu,
+        &omap54xx_l4_cfg__spinlock,
+        &omap54xx_l4_cfg__ocp2scp1,
         &omap54xx_l4_wkup__timer1,
         &omap54xx_l4_per__timer2,
         &omap54xx_l4_per__timer3,
@@ -2180,6 +2402,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l4_per__uart4,
         &omap54xx_l4_per__uart5,
         &omap54xx_l4_per__uart6,
+        &omap54xx_l4_cfg__usb_host_hs,
+        &omap54xx_l4_cfg__usb_tll_hs,
         &omap54xx_l4_cfg__usb_otg_ss,
         &omap54xx_l4_wkup__wd_timer2,
         NULL,
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index baf3d8bf6bea..da5a59ae77b6 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -257,6 +257,7 @@ extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
 extern void omap54xx_powerdomains_init(void);
 extern void dra7xx_powerdomains_init(void);
+void am43xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c
new file mode 100644
index 000000000000..95fee54c38ab
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains43xx_data.c
@@ -0,0 +1,136 @@
+/*
+ * AM43xx Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prcm43xx.h"
+
+static struct powerdomain gfx_43xx_pwrdm = {
+        .name             = "gfx_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = AM43XX_PRM_GFX_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* gfx_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain mpu_43xx_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = AM43XX_PRM_MPU_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
+                [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [2] = PWRSTS_OFF_RET,   /* mpu_ram */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* mpu_l1 */
+                [1] = PWRSTS_ON,        /* mpu_l2 */
+                [2] = PWRSTS_ON,        /* mpu_ram */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain rtc_43xx_pwrdm = {
+        .name             = "rtc_pwrdm",
+        .voltdm           = { .name = "rtc" },
+        .prcm_offs        = AM43XX_PRM_RTC_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+
+static struct powerdomain wkup_43xx_pwrdm = {
+        .name             = "wkup_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = AM43XX_PRM_WKUP_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* debugss_mem */
+        },
+};
+
+static struct powerdomain tamper_43xx_pwrdm = {
+        .name             = "tamper_pwrdm",
+        .voltdm           = { .name = "tamper" },
+        .prcm_offs        = AM43XX_PRM_TAMPER_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+
+static struct powerdomain cefuse_43xx_pwrdm = {
+        .name             = "cefuse_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = AM43XX_PRM_CEFUSE_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain per_43xx_pwrdm = {
+        .name             = "per_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = AM43XX_PRM_PER_INST,
+        .prcm_partition   = AM43XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 4,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* icss_mem */
+                [1] = PWRSTS_OFF_RET,   /* per_mem */
+                [2] = PWRSTS_OFF_RET,   /* ram1_mem */
+                [3] = PWRSTS_OFF_RET,   /* ram2_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* icss_mem */
+                [1] = PWRSTS_ON,        /* per_mem */
+                [2] = PWRSTS_ON,        /* ram1_mem */
+                [3] = PWRSTS_ON,        /* ram2_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+static struct powerdomain *powerdomains_am43xx[] __initdata = {
+        &gfx_43xx_pwrdm,
+        &mpu_43xx_pwrdm,
+        &rtc_43xx_pwrdm,
+        &wkup_43xx_pwrdm,
+        &tamper_43xx_pwrdm,
+        &cefuse_43xx_pwrdm,
+        &per_43xx_pwrdm,
+        NULL
+};
+
+static int am43xx_check_vcvp(void)
+{
+        return 0;
+}
+
+void __init am43xx_powerdomains_init(void)
+{
+        omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp;
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_am43xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
new file mode 100644
index 000000000000..7785be984edd
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -0,0 +1,146 @@
+/*
+ * AM43x PRCM defines
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
+
+#define AM43XX_PRM_PARTITION                            1
+#define AM43XX_CM_PARTITION                             1
+
+/* PRM instances */
+#define AM43XX_PRM_OCP_SOCKET_INST                      0x0000
+#define AM43XX_PRM_MPU_INST                             0x0300
+#define AM43XX_PRM_GFX_INST                             0x0400
+#define AM43XX_PRM_RTC_INST                             0x0500
+#define AM43XX_PRM_TAMPER_INST                          0x0600
+#define AM43XX_PRM_CEFUSE_INST                          0x0700
+#define AM43XX_PRM_PER_INST                             0x0800
+#define AM43XX_PRM_WKUP_INST                            0x2000
+#define AM43XX_PRM_DEVICE_INST                          0x4000
+
+/* RM RSTCTRL offsets */
+#define AM43XX_RM_PER_RSTCTRL_OFFSET                    0x0010
+#define AM43XX_RM_GFX_RSTCTRL_OFFSET                    0x0010
+#define AM43XX_RM_WKUP_RSTCTRL_OFFSET                   0x0010
+
+/* RM RSTST offsets */
+#define AM43XX_RM_GFX_RSTST_OFFSET                      0x0014
+#define AM43XX_RM_WKUP_RSTST_OFFSET                     0x0014
+
+/* CM instances */
+#define AM43XX_CM_WKUP_INST                             0x2800
+#define AM43XX_CM_DEVICE_INST                           0x4100
+#define AM43XX_CM_DPLL_INST                             0x4200
+#define AM43XX_CM_MPU_INST                              0x8300
+#define AM43XX_CM_GFX_INST                              0x8400
+#define AM43XX_CM_RTC_INST                              0x8500
+#define AM43XX_CM_TAMPER_INST                           0x8600
+#define AM43XX_CM_CEFUSE_INST                           0x8700
+#define AM43XX_CM_PER_INST                              0x8800
+
+/* CD offsets */
+#define AM43XX_CM_WKUP_L3_AON_CDOFFS                    0x0000
+#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS                   0x0100
+#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS               0x0200
+#define AM43XX_CM_WKUP_WKUP_CDOFFS                      0x0300
+#define AM43XX_CM_MPU_MPU_CDOFFS                        0x0000
+#define AM43XX_CM_GFX_GFX_L3_CDOFFS                     0x0000
+#define AM43XX_CM_RTC_RTC_CDOFFS                        0x0000
+#define AM43XX_CM_TAMPER_TAMPER_CDOFFS                  0x0000
+#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS                  0x0000
+#define AM43XX_CM_PER_L3_CDOFFS                         0x0000
+#define AM43XX_CM_PER_L3S_CDOFFS                        0x0200
+#define AM43XX_CM_PER_ICSS_CDOFFS                       0x0300
+#define AM43XX_CM_PER_L4LS_CDOFFS                       0x0400
+#define AM43XX_CM_PER_EMIF_CDOFFS                       0x0700
+#define AM43XX_CM_PER_DSS_CDOFFS                        0x0a00
+#define AM43XX_CM_PER_CPSW_CDOFFS                       0x0b00
+#define AM43XX_CM_PER_OCPWP_L3_CDOFFS                   0x0c00
+
+/* CLK CTRL offsets */
+#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET              0x0580
+#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET              0x0588
+#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET              0x0590
+#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET              0x0598
+#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET              0x05a0
+#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET              0x0428
+#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET              0x0430
+#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET                0x0468
+#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET            0x0438
+#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET            0x0440
+#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET            0x0448
+#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET              0x0478
+#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET              0x0480
+#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET              0x0488
+#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET               0x04a8
+#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET               0x04b0
+#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET           0x04b8
+#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET               0x04c0
+#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET               0x04c8
+#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET               0x0500
+#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET               0x0508
+#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET           0x0528
+#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET             0x0530
+#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET             0x0538
+#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET             0x0540
+#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET             0x0548
+#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET             0x0550
+#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET             0x0558
+#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET           0x0228
+#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET           0x0360
+#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET      0x0350
+#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET      0x0358
+#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET             0x0348
+#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET            0x0328
+#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET              0x0340
+#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET             0x0368
+#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET           0x0120
+#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET              0x0338
+#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET            0x0220
+#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET                0x0020
+#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET               0x0248
+#define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET               0x0258
+#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET               0x0220
+#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET             0x0238
+#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET             0x0240
+#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET               0x0420
+#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET                 0x0020
+#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET               0x0078
+#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET              0x0080
+#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET              0x0088
+#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET              0x0090
+#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET            0x0b20
+#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET              0x0320
+#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET                0x0020
+#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET               0x00a0
+#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET                0x0020
+#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET           0x0040
+#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET            0x0050
+#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET               0x0058
+#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET               0x0028
+#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET             0x0560
+#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET             0x0568
+#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET            0x0570
+#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET            0x0578
+#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET         0x0230
+#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET            0x0450
+#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET            0x0458
+#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET            0x0460
+#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET               0x0510
+#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET               0x0518
+#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET               0x0520
+#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET              0x0490
+#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET              0x0498
+#define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET        0x0260
+#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET     0x05B8
+#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET        0x0268
+#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET     0x05C0
+
+#endif
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 4588df1447ed..076bd90a6ce0 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -455,9 +455,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 
 #define OMAP54XX_CLASS          0x54000054
-#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
 #define OMAP5430_REV_ES2_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
-#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
 #define OMAP5432_REV_ES2_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
 
 void omap2xxx_check_revision(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 538e7cda5eea..3ca81e0ada5e 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -55,6 +55,7 @@
 #include "soc.h"
 #include "common.h"
 #include "powerdomain.h"
+#include "omap-secure.h"
 
 #define REALTIME_COUNTER_BASE                           0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
@@ -66,6 +67,15 @@
 static struct omap_dm_timer clkev;
 static struct clock_event_device clockevent_gpt;
 
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+static unsigned long arch_timer_freq;
+
+void set_cntfreq(void)
+{
+        omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
+}
+#endif
+
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &clockevent_gpt;
@@ -515,6 +525,10 @@ static void __init realtime_counter_init(void)
                 num = 8;
                 den = 25;
                 break;
+        case 20000000:
+                num = 192;
+                den = 625;
+                break;
         case 2600000:
                 num = 384;
                 den = 1625;
@@ -542,6 +556,9 @@ static void __init realtime_counter_init(void)
         reg |= den;
         __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 
+        arch_timer_freq = (rate / den) * num;
+        set_cntfreq();
+
         iounmap(base);
 }
 #else
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 31d0c9101272..645a8fe55f8d 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -12,7 +12,7 @@ obj-				:=
 
 # Core
 
-obj-y                           += common.o clock.o
+obj-y                           += common.o
 
 # Core support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
deleted file mode 100644
index c1bcc4a6d3a8..000000000000
--- a/arch/arm/mach-s3c64xx/clock.c
+++ /dev/null
@@ -1,1007 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/clock.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX Base clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pll.h>
-
-#include "regs-sys.h"
-
-/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
- * ext_xtal_mux for want of an actual name from the manual.
-*/
-
-static struct clk clk_ext_xtal_mux = {
-        .name           = "ext_xtal",
-};
-
-#define clk_fin_apll clk_ext_xtal_mux
-#define clk_fin_mpll clk_ext_xtal_mux
-#define clk_fin_epll clk_ext_xtal_mux
-
-#define clk_fout_mpll   clk_mpll
-#define clk_fout_epll   clk_epll
-
-struct clk clk_h2 = {
-        .name           = "hclk2",
-        .rate           = 0,
-};
-
-struct clk clk_27m = {
-        .name           = "clk_27m",
-        .rate           = 27000000,
-};
-
-static int clk_48m_ctrl(struct clk *clk, int enable)
-{
-        unsigned long flags;
-        u32 val;
-
-        /* can't rely on clock lock, this register has other usages */
-        local_irq_save(flags);
-
-        val = __raw_readl(S3C64XX_OTHERS);
-        if (enable)
-                val |= S3C64XX_OTHERS_USBMASK;
-        else
-                val &= ~S3C64XX_OTHERS_USBMASK;
-
-        __raw_writel(val, S3C64XX_OTHERS);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-struct clk clk_48m = {
-        .name           = "clk_48m",
-        .rate           = 48000000,
-        .enable         = clk_48m_ctrl,
-};
-
-struct clk clk_xusbxti = {
-        .name           = "xusbxti",
-        .rate           = 48000000,
-};
-
-static int inline s3c64xx_gate(void __iomem *reg,
-                                struct clk *clk,
-                                int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        u32 con;
-
-        con = __raw_readl(reg);
-
-        if (enable)
-                con |= ctrlbit;
-        else
-                con &= ~ctrlbit;
-
-        __raw_writel(con, reg);
-        return 0;
-}
-
-static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
-{
-        return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
-}
-
-static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
-{
-        return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
-}
-
-int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
-{
-        return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
-}
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "nand",
-                .parent         = &clk_h,
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_RTC,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_IIC,
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C6410_CLKCON_PCLK_I2C1,
-        }, {
-                .name           = "keypad",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_KEYPAD,
-        }, {
-                .name           = "spi",
-                .devname        = "s3c6410-spi.0",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
-        }, {
-                .name           = "spi",
-                .devname        = "s3c6410-spi.1",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
-        }, {
-                .name           = "48m",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
-        }, {
-                .name           = "48m",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
-        }, {
-                .name           = "48m",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
-        }, {
-                .name           = "cfcon",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
-        }, {
-                .name           = "dma0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_DMA0,
-        }, {
-                .name           = "dma1",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
-        }, {
-                .name           = "3dse",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_3DSE,
-        }, {
-                .name           = "hclk_secur",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_SECUR,
-        }, {
-                .name           = "sdma1",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_SDMA1,
-        }, {
-                .name           = "sdma0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_SDMA0,
-        }, {
-                .name           = "hclk_jpeg",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_JPEG,
-        }, {
-                .name           = "camif",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_CAMIF,
-        }, {
-                .name           = "hclk_scaler",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_SCALER,
-        }, {
-                .name           = "2d",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_2D,
-        }, {
-                .name           = "tv",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_TV,
-        }, {
-                .name           = "post0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_POST0,
-        }, {
-                .name           = "rot",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_ROT,
-        }, {
-                .name           = "hclk_mfc",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_MFC,
-        }, {
-                .name           = "pclk_mfc",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_MFC,
-        }, {
-                .name           = "dac27",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_DAC27,
-        }, {
-                .name           = "tv27",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_TV27,
-        }, {
-                .name           = "scaler27",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SCALER27,
-        }, {
-                .name           = "sclk_scaler",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SCALER,
-        }, {
-                .name           = "post0_27",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_POST0_27,
-        }, {
-                .name           = "secur",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SECUR,
-        }, {
-                .name           = "sclk_mfc",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_MFC,
-        }, {
-                .name           = "sclk_jpeg",
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_JPEG,
-        },
-};
-
-static struct clk clk_48m_spi0 = {
-        .name           = "spi_48m",
-        .devname        = "s3c6410-spi.0",
-        .parent         = &clk_48m,
-        .enable         = s3c64xx_sclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
-};
-
-static struct clk clk_48m_spi1 = {
-        .name           = "spi_48m",
-        .devname        = "s3c6410-spi.1",
-        .parent         = &clk_48m,
-        .enable         = s3c64xx_sclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
-};
-
-static struct clk clk_i2s0 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.0",
-        .parent         = &clk_p,
-        .enable         = s3c64xx_pclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
-};
-
-static struct clk clk_i2s1 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.1",
-        .parent         = &clk_p,
-        .enable         = s3c64xx_pclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
-};
-
-#ifdef CONFIG_CPU_S3C6410
-static struct clk clk_i2s2 = {
-        .name           = "iis",
-        .devname        = "samsung-i2s.2",
-        .parent         = &clk_p,
-        .enable         = s3c64xx_pclk_ctrl,
-        .ctrlbit        = S3C6410_CLKCON_PCLK_IIS2,
-};
-#endif
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "lcd",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_LCD,
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
-        }, {
-                .name           = "usb-host",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
-        }, {
-                .name           = "otg",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_USB,
-        }, {
-                .name           = "timers",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_PWM,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.0",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_UART0,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.1",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_UART1,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.2",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_UART2,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c6400-uart.3",
-                .parent         = &clk_p,
-                .enable         = s3c64xx_pclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_PCLK_UART3,
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C_CLKCON_PCLK_WDT,
-        },
-};
-
-static struct clk clk_hsmmc0 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.0",
-        .parent         = &clk_h,
-        .enable         = s3c64xx_hclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
-};
-
-static struct clk clk_hsmmc1 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_h,
-        .enable         = s3c64xx_hclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
-};
-
-static struct clk clk_hsmmc2 = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.2",
-        .parent         = &clk_h,
-        .enable         = s3c64xx_hclk_ctrl,
-        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
-};
-
-static struct clk clk_fout_apll = {
-        .name           = "fout_apll",
-};
-
-static struct clk *clk_src_apll_list[] = {
-        [0] = &clk_fin_apll,
-        [1] = &clk_fout_apll,
-};
-
-static struct clksrc_sources clk_src_apll = {
-        .sources        = clk_src_apll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
-};
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1  },
-        .sources        = &clk_src_apll,
-};
-
-static struct clk *clk_src_epll_list[] = {
-        [0] = &clk_fin_epll,
-        [1] = &clk_fout_epll,
-};
-
-static struct clksrc_sources clk_src_epll = {
-        .sources        = clk_src_epll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1  },
-        .sources        = &clk_src_epll,
-};
-
-static struct clk *clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &clk_fout_mpll,
-};
-
-static struct clksrc_sources clk_src_mpll = {
-        .sources        = clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1  },
-        .sources        = &clk_src_mpll,
-};
-
-static unsigned int armclk_mask;
-
-static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        u32 clkdiv;
-
-        /* divisor mask starts at bit0, so no need to shift */
-        clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
-
-        return rate / (clkdiv + 1);
-}
-
-static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
-                                                unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        u32 div;
-
-        if (parent < rate)
-                return parent;
-
-        div = (parent / rate) - 1;
-        if (div > armclk_mask)
-                div = armclk_mask;
-
-        return parent / (div + 1);
-}
-
-static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        u32 div;
-        u32 val;
-
-        if (rate < parent / (armclk_mask + 1))
-                return -EINVAL;
-
-        rate = clk_round_rate(clk, rate);
-        div = clk_get_rate(clk->parent) / rate;
-
-        val = __raw_readl(S3C_CLK_DIV0);
-        val &= ~armclk_mask;
-        val |= (div - 1);
-        __raw_writel(val, S3C_CLK_DIV0);
-
-        return 0;
-
-}
-
-static struct clk clk_arm = {
-        .name           = "armclk",
-        .parent         = &clk_mout_apll.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c64xx_clk_arm_get_rate,
-                .set_rate       = s3c64xx_clk_arm_set_rate,
-                .round_rate     = s3c64xx_clk_arm_round_rate,
-        },
-};
-
-static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-
-        if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
-                rate /= 2;
-
-        return rate;
-}
-
-static struct clk_ops clk_dout_ops = {
-        .get_rate       = s3c64xx_clk_doutmpll_get_rate,
-};
-
-static struct clk clk_dout_mpll = {
-        .name           = "dout_mpll",
-        .parent         = &clk_mout_mpll.clk,
-        .ops            = &clk_dout_ops,
-};
-
-static struct clk *clkset_spi_mmc_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_fin_epll,
-        &clk_27m,
-};
-
-static struct clksrc_sources clkset_spi_mmc = {
-        .sources        = clkset_spi_mmc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
-};
-
-static struct clk *clkset_irda_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        NULL,
-        &clk_27m,
-};
-
-static struct clksrc_sources clkset_irda = {
-        .sources        = clkset_irda_list,
-        .nr_sources     = ARRAY_SIZE(clkset_irda_list),
-};
-
-static struct clk *clkset_uart_list[] = {
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        NULL,
-        NULL
-};
-
-static struct clksrc_sources clkset_uart = {
-        .sources        = clkset_uart_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
-};
-
-static struct clk *clkset_uhost_list[] = {
-        &clk_48m,
-        &clk_mout_epll.clk,
-        &clk_dout_mpll,
-        &clk_fin_epll,
-};
-
-static struct clksrc_sources clkset_uhost = {
-        .sources        = clkset_uhost_list,
-        .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
-};
-
-/* The peripheral clocks are all controlled via clocksource followed
- * by an optional divider and gate stage. We currently roll this into
- * one clock which hides the intermediate clock from the mux.
- *
- * Note, the JPEG clock can only be an even divider...
- *
- * The scaler and LCD clocks depend on the S3C64XX version, and also
- * have a common parent divisor so are not included here.
- */
-
-/* clocks that feed other parts of the clock source tree */
-
-static struct clk clk_iis_cd0 = {
-        .name           = "iis_cdclk0",
-};
-
-static struct clk clk_iis_cd1 = {
-        .name           = "iis_cdclk1",
-};
-
-static struct clk clk_iisv4_cd = {
-        .name           = "iis_cdclk_v4",
-};
-
-static struct clk clk_pcm_cd = {
-        .name           = "pcm_cdclk",
-};
-
-static struct clk *clkset_audio0_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_dout_mpll,
-        [2] = &clk_fin_epll,
-        [3] = &clk_iis_cd0,
-        [4] = &clk_pcm_cd,
-};
-
-static struct clksrc_sources clkset_audio0 = {
-        .sources        = clkset_audio0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
-};
-
-static struct clk *clkset_audio1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_dout_mpll,
-        [2] = &clk_fin_epll,
-        [3] = &clk_iis_cd1,
-        [4] = &clk_pcm_cd,
-};
-
-static struct clksrc_sources clkset_audio1 = {
-        .sources        = clkset_audio1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
-};
-
-#ifdef CONFIG_CPU_S3C6410
-static struct clk *clkset_audio2_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_dout_mpll,
-        [2] = &clk_fin_epll,
-        [3] = &clk_iisv4_cd,
-        [4] = &clk_pcm_cd,
-};
-
-static struct clksrc_sources clkset_audio2 = {
-        .sources        = clkset_audio2_list,
-        .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
-};
-#endif
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "usb-bus-host",
-                        .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
-                .sources        = &clkset_uhost,
-        }, {
-                .clk    = {
-                        .name           = "irda-bus",
-                        .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4  },
-                .sources        = &clkset_irda,
-        }, {
-                .clk    = {
-                        .name           = "camera",
-                        .ctrlbit        = S3C_CLKCON_SCLK_CAM,
-                        .enable         = s3c64xx_sclk_ctrl,
-                        .parent         = &clk_h2,
-                },
-                .reg_div        = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
-        },
-};
-
-/* Where does UCLK0 come from? */
-static struct clksrc_clk clk_sclk_uclk = {
-        .clk    = {
-                .name           = "uclk1",
-                .ctrlbit        = S3C_CLKCON_SCLK_UART,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
-        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
-        .sources        = &clkset_uart,
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "mmc_bus",
-                .devname        = "s3c-sdhci.0",
-                .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
-        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
-        .sources        = &clkset_spi_mmc,
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "mmc_bus",
-                .devname        = "s3c-sdhci.1",
-                .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
-        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
-        .sources        = &clkset_spi_mmc,
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "mmc_bus",
-                .devname        = "s3c-sdhci.2",
-                .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
-        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
-        .sources        = &clkset_spi_mmc,
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "spi-bus",
-                .devname        = "s3c6410-spi.0",
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
-        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
-        .sources = &clkset_spi_mmc,
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "spi-bus",
-                .devname        = "s3c6410-spi.1",
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
-        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
-        .sources = &clkset_spi_mmc,
-};
-
-static struct clksrc_clk clk_audio_bus0 = {
-        .clk    = {
-                .name           = "audio-bus",
-                .devname        = "samsung-i2s.0",
-                .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3  },
-        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4  },
-        .sources        = &clkset_audio0,
-};
-
-static struct clksrc_clk clk_audio_bus1 = {
-        .clk    = {
-                .name           = "audio-bus",
-                .devname        = "samsung-i2s.1",
-                .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3  },
-        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4  },
-        .sources        = &clkset_audio1,
-};
-
-#ifdef CONFIG_CPU_S3C6410
-static struct clksrc_clk clk_audio_bus2 = {
-        .clk    = {
-                .name           = "audio-bus",
-                .devname        = "samsung-i2s.2",
-                .ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
-                .enable         = s3c64xx_sclk_ctrl,
-        },
-        .reg_src        = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3  },
-        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4  },
-        .sources        = &clkset_audio2,
-};
-#endif
-/* Clock initialisation code */
-
-static struct clksrc_clk *init_parents[] = {
-        &clk_mout_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uclk,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_audio_bus0,
-        &clk_audio_bus1,
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_hsmmc0,
-        &clk_hsmmc1,
-        &clk_hsmmc2,
-        &clk_48m_spi0,
-        &clk_48m_spi1,
-        &clk_i2s0,
-        &clk_i2s1,
-};
-
-static struct clk_lookup s3c64xx_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
-        CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
-        CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
-        CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
-        CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
-#ifdef CONFIG_CPU_S3C6410
-        CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
-        CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),
-#endif
-};
-
-#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
-
-void __init_or_cpufreq s3c64xx_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long hclk2;
-        unsigned long pclk;
-        unsigned long epll;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned int ptr;
-        u32 clkdiv0;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        clkdiv0 = __raw_readl(S3C_CLK_DIV0);
-        printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        /* For now assume the mux always selects the crystal */
-        clk_ext_xtal_mux.parent = xtal_clk;
-
-        epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
-                                __raw_readl(S3C_EPLL_CON1));
-        mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
-        apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
-
-        fclk = mpll;
-
-        printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
-               apll, mpll, epll);
-
-        if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
-                /* Synchronous mode */
-                hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
-        else
-                /* Asynchronous mode */
-                hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
-
-        hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
-        pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
-
-        printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
-               hclk2, hclk, pclk);
-
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
-
-        clk_h2.rate = hclk2;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-        clk_f.rate = fclk;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s3c_set_clksrc(init_parents[ptr], true);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks1[] __initdata = {
-        &clk_ext_xtal_mux,
-        &clk_iis_cd0,
-        &clk_iis_cd1,
-        &clk_iisv4_cd,
-        &clk_pcm_cd,
-        &clk_mout_epll.clk,
-        &clk_mout_mpll.clk,
-        &clk_dout_mpll,
-        &clk_arm,
-};
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_epll,
-        &clk_27m,
-        &clk_48m,
-        &clk_h2,
-        &clk_xusbxti,
-};
-
-/**
- * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
- * @xtal: The rate for the clock crystal feeding the PLLs.
- * @armclk_divlimit: Divisor mask for ARMCLK.
- *
- * Register the clocks for the S3C6400 and S3C6410 SoC range, such
- * as ARMCLK as well as the necessary parent clocks.
- *
- * This call does not setup the clocks, which is left to the
- * s3c64xx_setup_clocks() call which may be needed by the cpufreq
- * or resume code to re-set the clocks if the bootloader has changed
- * them.
- */
-void __init s3c64xx_register_clocks(unsigned long xtal, 
-                                    unsigned armclk_divlimit)
-{
-        unsigned int cnt;
-
-        armclk_mask = armclk_divlimit;
-
-        s3c24xx_register_baseclocks(xtal);
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
-                s3c_disable_clocks(clk_cdev[cnt], 1);
-
-        s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
-                s3c_register_clksrc(clksrc_cdev[cnt], 1);
-        clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
-}
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 73d79cf5e141..7d3cb58f1856 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/clk-provider.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
@@ -38,7 +39,6 @@
 #include <mach/regs-gpio.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/gpio-cfg.h>
@@ -50,6 +50,19 @@
 
 #include "common.h"
 
+/* External clock frequency */
+static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
+
+void __init s3c64xx_set_xtal_freq(unsigned long freq)
+{
+        xtal_f = freq;
+}
+
+void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
+{
+        xusbxti_f = freq;
+}
+
 /* uart registration process */
 
 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -67,7 +80,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = S3C6400_CPU_ID,
                 .idmask         = S3C64XX_CPU_MASK,
                 .map_io         = s3c6400_map_io,
-                .init_clocks    = s3c6400_init_clocks,
                 .init_uarts     = s3c64xx_init_uarts,
                 .init           = s3c6400_init,
                 .name           = name_s3c6400,
@@ -75,7 +87,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = S3C6410_CPU_ID,
                 .idmask         = S3C64XX_CPU_MASK,
                 .map_io         = s3c6410_map_io,
-                .init_clocks    = s3c6410_init_clocks,
                 .init_uarts     = s3c64xx_init_uarts,
                 .init           = s3c6410_init,
                 .name           = name_s3c6410,
@@ -213,8 +224,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
         /*
          * FIXME: there is no better place to put this at the moment
-         * (samsung_wdt_reset_init needs clocks)
+         * (s3c64xx_clk_init needs ioremap and must happen before init_time
+         * samsung_wdt_reset_init needs clocks)
          */
+        s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 
         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index e8f990b37665..bd3bd562011e 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -22,21 +22,21 @@
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
-void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
-void s3c64xx_setup_clocks(void);
-
 void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
+void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
+        unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
+void s3c64xx_set_xtal_freq(unsigned long freq);
+void s3c64xx_set_xusbxti_freq(unsigned long freq);
+
 #ifdef CONFIG_CPU_S3C6400
 
 extern  int s3c6400_init(void);
 extern void s3c6400_init_irq(void);
 extern void s3c6400_map_io(void);
-extern void s3c6400_init_clocks(int xtal);
 
 #else
-#define s3c6400_init_clocks NULL
 #define s3c6400_map_io NULL
 #define s3c6400_init NULL
 #endif
@@ -46,10 +46,8 @@ extern void s3c6400_init_clocks(int xtal);
 extern  int s3c6410_init(void);
 extern void s3c6410_init_irq(void);
 extern void s3c6410_map_io(void);
-extern void s3c6410_init_clocks(int xtal);
 
 #else
-#define s3c6410_init_clocks NULL
 #define s3c6410_map_io NULL
 #define s3c6410_init NULL
 #endif
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 759846c28d12..c511dfaae148 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -677,7 +677,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
                 goto err_map;
         }
 
-        clk_enable(dmac->clk);
+        clk_prepare_enable(dmac->clk);
 
         dmac->regs = regs;
         dmac->chanbase = chbase;
@@ -711,7 +711,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
         return 0;
 
 err_clk:
-        clk_disable(dmac->clk);
+        clk_disable_unprepare(dmac->clk);
         clk_put(dmac->clk);
 err_map:
         iounmap(regs);
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
index 05332b998ec0..4f44aac77092 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -15,145 +15,21 @@
 #ifndef __PLAT_REGS_CLOCK_H
 #define __PLAT_REGS_CLOCK_H __FILE__
 
+/*
+ * FIXME: Remove remaining definitions
+ */
+
 #define S3C_CLKREG(x)           (S3C_VA_SYS + (x))
 
-#define S3C_APLL_LOCK           S3C_CLKREG(0x00)
-#define S3C_MPLL_LOCK           S3C_CLKREG(0x04)
-#define S3C_EPLL_LOCK           S3C_CLKREG(0x08)
-#define S3C_APLL_CON            S3C_CLKREG(0x0C)
-#define S3C_MPLL_CON            S3C_CLKREG(0x10)
-#define S3C_EPLL_CON0           S3C_CLKREG(0x14)
-#define S3C_EPLL_CON1           S3C_CLKREG(0x18)
-#define S3C_CLK_SRC             S3C_CLKREG(0x1C)
-#define S3C_CLK_DIV0            S3C_CLKREG(0x20)
-#define S3C_CLK_DIV1            S3C_CLKREG(0x24)
-#define S3C_CLK_DIV2            S3C_CLKREG(0x28)
-#define S3C_CLK_OUT             S3C_CLKREG(0x2C)
-#define S3C_HCLK_GATE           S3C_CLKREG(0x30)
 #define S3C_PCLK_GATE           S3C_CLKREG(0x34)
-#define S3C_SCLK_GATE           S3C_CLKREG(0x38)
-#define S3C_MEM0_GATE           S3C_CLKREG(0x3C)
 #define S3C6410_CLK_SRC2        S3C_CLKREG(0x10C)
 #define S3C_MEM_SYS_CFG         S3C_CLKREG(0x120)
 
-/* CLKDIV0 */
-#define S3C6400_CLKDIV0_PCLK_MASK       (0xf << 12)
-#define S3C6400_CLKDIV0_PCLK_SHIFT      (12)
-#define S3C6400_CLKDIV0_HCLK2_MASK      (0x7 << 9)
-#define S3C6400_CLKDIV0_HCLK2_SHIFT     (9)
-#define S3C6400_CLKDIV0_HCLK_MASK       (0x1 << 8)
-#define S3C6400_CLKDIV0_HCLK_SHIFT      (8)
-#define S3C6400_CLKDIV0_MPLL_MASK       (0x1 << 4)
-#define S3C6400_CLKDIV0_MPLL_SHIFT      (4)
-
-#define S3C6400_CLKDIV0_ARM_MASK        (0x7 << 0)
-#define S3C6410_CLKDIV0_ARM_MASK        (0xf << 0)
-#define S3C6400_CLKDIV0_ARM_SHIFT       (0)
-
-/* HCLK GATE Registers */
-#define S3C_CLKCON_HCLK_3DSE    (1<<31)
-#define S3C_CLKCON_HCLK_UHOST   (1<<29)
-#define S3C_CLKCON_HCLK_SECUR   (1<<28)
-#define S3C_CLKCON_HCLK_SDMA1   (1<<27)
-#define S3C_CLKCON_HCLK_SDMA0   (1<<26)
-#define S3C_CLKCON_HCLK_IROM    (1<<25)
-#define S3C_CLKCON_HCLK_DDR1    (1<<24)
-#define S3C_CLKCON_HCLK_DDR0    (1<<23)
-#define S3C_CLKCON_HCLK_MEM1    (1<<22)
-#define S3C_CLKCON_HCLK_MEM0    (1<<21)
-#define S3C_CLKCON_HCLK_USB     (1<<20)
-#define S3C_CLKCON_HCLK_HSMMC2  (1<<19)
-#define S3C_CLKCON_HCLK_HSMMC1  (1<<18)
-#define S3C_CLKCON_HCLK_HSMMC0  (1<<17)
-#define S3C_CLKCON_HCLK_MDP     (1<<16)
-#define S3C_CLKCON_HCLK_DHOST   (1<<15)
-#define S3C_CLKCON_HCLK_IHOST   (1<<14)
-#define S3C_CLKCON_HCLK_DMA1    (1<<13)
-#define S3C_CLKCON_HCLK_DMA0    (1<<12)
-#define S3C_CLKCON_HCLK_JPEG    (1<<11)
-#define S3C_CLKCON_HCLK_CAMIF   (1<<10)
-#define S3C_CLKCON_HCLK_SCALER  (1<<9)
-#define S3C_CLKCON_HCLK_2D      (1<<8)
-#define S3C_CLKCON_HCLK_TV      (1<<7)
-#define S3C_CLKCON_HCLK_POST0   (1<<5)
-#define S3C_CLKCON_HCLK_ROT     (1<<4)
-#define S3C_CLKCON_HCLK_LCD     (1<<3)
-#define S3C_CLKCON_HCLK_TZIC    (1<<2)
-#define S3C_CLKCON_HCLK_INTC    (1<<1)
-#define S3C_CLKCON_HCLK_MFC     (1<<0)
-
 /* PCLK GATE Registers */
-#define S3C6410_CLKCON_PCLK_I2C1        (1<<27)
-#define S3C6410_CLKCON_PCLK_IIS2        (1<<26)
-#define S3C_CLKCON_PCLK_SKEY            (1<<24)
-#define S3C_CLKCON_PCLK_CHIPID          (1<<23)
-#define S3C_CLKCON_PCLK_SPI1            (1<<22)
-#define S3C_CLKCON_PCLK_SPI0            (1<<21)
-#define S3C_CLKCON_PCLK_HSIRX           (1<<20)
-#define S3C_CLKCON_PCLK_HSITX           (1<<19)
-#define S3C_CLKCON_PCLK_GPIO            (1<<18)
-#define S3C_CLKCON_PCLK_IIC             (1<<17)
-#define S3C_CLKCON_PCLK_IIS1            (1<<16)
-#define S3C_CLKCON_PCLK_IIS0            (1<<15)
-#define S3C_CLKCON_PCLK_AC97            (1<<14)
-#define S3C_CLKCON_PCLK_TZPC            (1<<13)
-#define S3C_CLKCON_PCLK_TSADC           (1<<12)
-#define S3C_CLKCON_PCLK_KEYPAD          (1<<11)
-#define S3C_CLKCON_PCLK_IRDA            (1<<10)
-#define S3C_CLKCON_PCLK_PCM1            (1<<9)
-#define S3C_CLKCON_PCLK_PCM0            (1<<8)
-#define S3C_CLKCON_PCLK_PWM             (1<<7)
-#define S3C_CLKCON_PCLK_RTC             (1<<6)
-#define S3C_CLKCON_PCLK_WDT             (1<<5)
 #define S3C_CLKCON_PCLK_UART3           (1<<4)
 #define S3C_CLKCON_PCLK_UART2           (1<<3)
 #define S3C_CLKCON_PCLK_UART1           (1<<2)
 #define S3C_CLKCON_PCLK_UART0           (1<<1)
-#define S3C_CLKCON_PCLK_MFC             (1<<0)
-
-/* SCLK GATE Registers */
-#define S3C_CLKCON_SCLK_UHOST           (1<<30)
-#define S3C_CLKCON_SCLK_MMC2_48         (1<<29)
-#define S3C_CLKCON_SCLK_MMC1_48         (1<<28)
-#define S3C_CLKCON_SCLK_MMC0_48         (1<<27)
-#define S3C_CLKCON_SCLK_MMC2            (1<<26)
-#define S3C_CLKCON_SCLK_MMC1            (1<<25)
-#define S3C_CLKCON_SCLK_MMC0            (1<<24)
-#define S3C_CLKCON_SCLK_SPI1_48         (1<<23)
-#define S3C_CLKCON_SCLK_SPI0_48         (1<<22)
-#define S3C_CLKCON_SCLK_SPI1            (1<<21)
-#define S3C_CLKCON_SCLK_SPI0            (1<<20)
-#define S3C_CLKCON_SCLK_DAC27           (1<<19)
-#define S3C_CLKCON_SCLK_TV27            (1<<18)
-#define S3C_CLKCON_SCLK_SCALER27        (1<<17)
-#define S3C_CLKCON_SCLK_SCALER          (1<<16)
-#define S3C_CLKCON_SCLK_LCD27           (1<<15)
-#define S3C_CLKCON_SCLK_LCD             (1<<14)
-#define S3C6400_CLKCON_SCLK_POST1_27    (1<<13)
-#define S3C6410_CLKCON_FIMC             (1<<13)
-#define S3C_CLKCON_SCLK_POST0_27        (1<<12)
-#define S3C6400_CLKCON_SCLK_POST1       (1<<11)
-#define S3C6410_CLKCON_SCLK_AUDIO2      (1<<11)
-#define S3C_CLKCON_SCLK_POST0           (1<<10)
-#define S3C_CLKCON_SCLK_AUDIO1          (1<<9)
-#define S3C_CLKCON_SCLK_AUDIO0          (1<<8)
-#define S3C_CLKCON_SCLK_SECUR           (1<<7)
-#define S3C_CLKCON_SCLK_IRDA            (1<<6)
-#define S3C_CLKCON_SCLK_UART            (1<<5)
-#define S3C_CLKCON_SCLK_ONENAND         (1<<4)
-#define S3C_CLKCON_SCLK_MFC             (1<<3)
-#define S3C_CLKCON_SCLK_CAM             (1<<2)
-#define S3C_CLKCON_SCLK_JPEG            (1<<1)
-
-/* CLKSRC */
-
-#define S3C6400_CLKSRC_APLL_MOUT        (1 << 0)
-#define S3C6400_CLKSRC_MPLL_MOUT        (1 << 1)
-#define S3C6400_CLKSRC_EPLL_MOUT        (1 << 2)
-#define S3C6400_CLKSRC_APLL_MOUT_SHIFT  (0)
-#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT  (1)
-#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT  (2)
-#define S3C6400_CLKSRC_MFC              (1 << 4)
 
 /* MEM_SYS_CFG */
 #define MEM_SYS_CFG_INDEP_CF            0x4000
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 35e3f54574ef..d266dd5f7060 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {
 static void __init anw6410_map_io(void)
 {
         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index eb8e5a1aca42..1a911df9e451 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {
 static void __init crag6410_map_io(void)
 {
         s3c64xx_init_io(NULL, 0);
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index f39569e0f2e6..e8064044ef79 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {
 static void __init hmt_map_io(void)
 {
         s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index fc043e3ecdf8..58d46a3d7b78 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)
         u32 tmp;
 
         s3c64xx_init_io(NULL, 0);
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 7e2c3908f1f8..2067b0bf55b4 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};
 static void __init ncp_map_io(void)
 {
         s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 86d980b448fd..0f47237be3b2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -337,13 +337,6 @@ err:
         return ret;
 }
 
-static int __init smartq_usb_otg_init(void)
-{
-        clk_xusbxti.rate = 12000000;
-
-        return 0;
-}
-
 static int __init smartq_wifi_init(void)
 {
         int ret;
@@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};
 void __init smartq_map_io(void)
 {
         s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
+        s3c64xx_set_xusbxti_freq(12000000);
         s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
@@ -399,7 +393,6 @@ void __init smartq_machine_init(void)
         WARN_ON(smartq_lcd_setup_gpio());
         WARN_ON(smartq_power_off_init());
         WARN_ON(smartq_usb_host_init());
-        WARN_ON(smartq_usb_otg_init());
         WARN_ON(smartq_wifi_init());
 
         platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index d70c0843aea2..27381cfcabbe 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};
 static void __init smdk6400_map_io(void)
 {
         s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d90b450c5645..2a7b32ca5c96 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)
         u32 tmp;
 
         s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
-        s3c24xx_init_clocks(12000000);
+        s3c64xx_set_xtal_freq(12000000);
         s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 6a1f91fea678..8cdb824a3b43 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -194,29 +194,8 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)
 #endif
 
 static struct sleep_save core_save[] = {
-        SAVE_ITEM(S3C_APLL_LOCK),
-        SAVE_ITEM(S3C_MPLL_LOCK),
-        SAVE_ITEM(S3C_EPLL_LOCK),
-        SAVE_ITEM(S3C_CLK_SRC),
-        SAVE_ITEM(S3C_CLK_DIV0),
-        SAVE_ITEM(S3C_CLK_DIV1),
-        SAVE_ITEM(S3C_CLK_DIV2),
-        SAVE_ITEM(S3C_CLK_OUT),
-        SAVE_ITEM(S3C_HCLK_GATE),
-        SAVE_ITEM(S3C_PCLK_GATE),
-        SAVE_ITEM(S3C_SCLK_GATE),
-        SAVE_ITEM(S3C_MEM0_GATE),
-
-        SAVE_ITEM(S3C_EPLL_CON1),
-        SAVE_ITEM(S3C_EPLL_CON0),
-
         SAVE_ITEM(S3C64XX_MEM0DRVCON),
         SAVE_ITEM(S3C64XX_MEM1DRVCON),
-
-#ifndef CONFIG_CPU_FREQ
-        SAVE_ITEM(S3C_APLL_CON),
-        SAVE_ITEM(S3C_MPLL_CON),
-#endif
 };
 
 static struct sleep_save misc_save[] = {
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 4869714c6f1b..331fe8e58145 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -58,12 +58,6 @@ void __init s3c6400_map_io(void)
         s3c64xx_onenand1_setname("s3c6400-onenand");
 }
 
-void __init s3c6400_init_clocks(int xtal)
-{
-        s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
-        s3c64xx_setup_clocks();
-}
-
 void __init s3c6400_init_irq(void)
 {
         /* VIC0 does not have IRQS 5..7,
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 31c29fdf1800..7e6fa125584a 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -62,13 +62,6 @@ void __init s3c6410_map_io(void)
         s3c_cfcon_setname("s3c64xx-pata");
 }
 
-void __init s3c6410_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
-        s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
-        s3c64xx_setup_clocks();
-}
-
 void __init s3c6410_init_irq(void)
 {
         /* VIC0 is missing IRQ7, VIC1 is fully populated. */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1f94c310c477..5dd5f9f7897a 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -101,12 +101,24 @@ config ARCH_R8A7790
         select SH_CLK_CPG
         select RENESAS_IRQC
 
+config ARCH_R8A7791
+        bool "R-Car M2 (R8A77910)"
+        select ARM_GIC
+        select CPU_V7
+        select SH_CLK_CPG
+
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
 
+config ARCH_R7S72100
+        bool "RZ/A1H (R7S72100)"
+        select ARM_GIC
+        select CPU_V7
+        select SH_CLK_CPG
+
 comment "SH-Mobile Board Type"
 
 config MACH_APE6EVM
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 2705bfa8c113..f2d40edadcc9 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -15,7 +15,10 @@ obj-$(CONFIG_ARCH_R8A7740)	+= setup-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7778)      += setup-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += setup-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o
+obj-$(CONFIG_ARCH_R8A7790)      += setup-r8a7790.o setup-rcar-gen2.o
+obj-$(CONFIG_ARCH_R8A7791)      += setup-r8a7791.o setup-rcar-gen2.o
 obj-$(CONFIG_ARCH_EMEV2)        += setup-emev2.o
+obj-$(CONFIG_ARCH_R7S72100)     += setup-r7s72100.o
 
 # Clock objects
 ifndef CONFIG_COMMON_CLK
@@ -27,13 +30,17 @@ obj-$(CONFIG_ARCH_R8A7740)	+= clock-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7778)      += clock-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += clock-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)      += clock-r8a7790.o
+obj-$(CONFIG_ARCH_R8A7791)      += clock-r8a7791.o
 obj-$(CONFIG_ARCH_EMEV2)        += clock-emev2.o
+obj-$(CONFIG_ARCH_R7S72100)     += clock-r7s72100.o
 endif
 
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7790)      += smp-r8a7790.o platsmp-apmu.o
+smp-$(CONFIG_ARCH_R8A7791)      += smp-r8a7791.o platsmp-apmu.o
 smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o platsmp-scu.o
 
 # IRQ objects
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 2856f51ff8a6..1a1a4a888632 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -38,8 +38,9 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+        .smp            = smp_ops(r8a7790_smp_ops),
         .init_early     = r8a7790_init_early,
+        .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_add_standard_devices,
-        .init_time      = r8a7790_timer_init,
         .dt_compat      = lager_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 66edb7e10089..fd6146ca7a5a 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -186,8 +186,9 @@ static const char * const lager_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+        .smp            = smp_ops(r8a7790_smp_ops),
         .init_early     = r8a7790_init_early,
-        .init_time      = r8a7790_timer_init,
+        .init_time      = rcar_gen2_timer_init,
         .init_machine   = lager_init,
         .dt_compat      = lager_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
new file mode 100644
index 000000000000..4aba20ca127e
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -0,0 +1,202 @@
+/*
+ * r7a72100 clock framework support
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2012  Phil Edworthy
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+#include <mach/r7s72100.h>
+
+/* registers */
+#define FRQCR           0xfcfe0010
+#define FRQCR2          0xfcfe0014
+#define STBCR3          0xfcfe0420
+#define STBCR4          0xfcfe0424
+
+#define PLL_RATE 30
+
+static struct clk_mapping cpg_mapping = {
+        .phys   = 0xfcfe0000,
+        .len    = 0x1000,
+};
+
+/* Fixed 32 KHz root clock for RTC */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 13330000,
+        .mapping        = &cpg_mapping,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        return clk->parent->rate * PLL_RATE;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long bus_recalc(struct clk *clk)
+{
+        return clk->parent->rate * 2 / 3;
+}
+
+static struct sh_clk_ops bus_clk_ops = {
+        .recalc         = bus_recalc,
+};
+
+static struct clk bus_clk = {
+        .ops            = &bus_clk_ops,
+        .parent         = &pll_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long peripheral0_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 12;
+}
+
+static struct sh_clk_ops peripheral0_clk_ops = {
+        .recalc         = peripheral0_recalc,
+};
+
+static struct clk peripheral0_clk = {
+        .ops            = &peripheral0_clk_ops,
+        .parent         = &pll_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long peripheral1_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 6;
+}
+
+static struct sh_clk_ops peripheral1_clk_ops = {
+        .recalc         = peripheral1_recalc,
+};
+
+static struct clk peripheral1_clk = {
+        .ops            = &peripheral1_clk_ops,
+        .parent         = &pll_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &pll_clk,
+        &bus_clk,
+        &peripheral0_clk,
+        &peripheral1_clk,
+};
+
+static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
+static int multipliers[] = { 1, 2, 1, 1 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
+        .multipliers = multipliers,
+        .nr_multipliers = ARRAY_SIZE(multipliers),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_I,
+        DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+        SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
+
+/* The mask field specifies the div2 entries that are valid */
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]  = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
+                                        | CLK_ENABLE_ON_INIT),
+};
+
+enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
+        MSTP33, MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
+        [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
+        [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
+        [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
+        [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
+        [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
+        [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
+        [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
+        [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
+};
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+        CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP clocks */
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
+        CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
+};
+
+void __init r7s72100_clock_init(void)
+{
+        int k, ret = 0;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+
+        if (!ret)
+                shmobile_clk_init();
+        else
+                panic("failed to setup rza1 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5bd2e851e3c7..571409b611d3 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
-        MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
+        MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
         MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
         MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
         MSTP411, MSTP410, MSTP409,
@@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 18, 0), /* DMAC */
         [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 0, 0), /* IIC2 */
         [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
         [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
@@ -578,6 +579,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
+        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
+        CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index c4bf2d8fb111..fb6af83858e3 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -69,6 +69,15 @@ static struct clk extal_clk = {
         .mapping = &cpg_mapping,
 };
 
+static struct clk audio_clk_a = {
+};
+
+static struct clk audio_clk_b = {
+};
+
+static struct clk audio_clk_c = {
+};
+
 /*
  * clock ratio of these clock will be updated
  * on r8a7778_clock_init()
@@ -100,18 +109,23 @@ static struct clk *main_clks[] = {
         &p_clk,
         &g_clk,
         &z_clk,
+        &audio_clk_a,
+        &audio_clk_b,
+        &audio_clk_c,
 };
 
 enum {
         MSTP331,
         MSTP323, MSTP322, MSTP321,
+        MSTP311, MSTP310,
+        MSTP309, MSTP308, MSTP307,
         MSTP114,
         MSTP110, MSTP109,
         MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
-        MSTP016, MSTP015,
-        MSTP007,
+        MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
+        MSTP009, MSTP008, MSTP007,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
@@ -119,6 +133,11 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
         [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
+        [MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
+        [MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3,  9, 0), /* SSI6 */
+        [MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3,  8, 0), /* SSI7 */
+        [MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3,  7, 0), /* SSI8 */
         [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
         [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
         [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1,  9, 0), /* VIN1 */
@@ -135,11 +154,20 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
         [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
         [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
+        [MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
+        [MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
+        [MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  9, 0), /* SSI3 */
+        [MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  8, 0), /* SRU */
         [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  7, 0), /* HSPI */
 };
 
 static struct clk_lookup lookups[] = {
         /* main */
+        CLKDEV_CON_ID("audio_clk_a",    &audio_clk_a),
+        CLKDEV_CON_ID("audio_clk_b",    &audio_clk_b),
+        CLKDEV_CON_ID("audio_clk_c",    &audio_clk_c),
+        CLKDEV_CON_ID("audio_clk_internal",     &s1_clk),
         CLKDEV_CON_ID("shyway_clk",     &s_clk),
         CLKDEV_CON_ID("peripheral_clk", &p_clk),
 
@@ -153,6 +181,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
         CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
         CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
+        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
         CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
         CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
         CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
@@ -168,6 +197,17 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
         CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
         CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
+        CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
+
+        CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
+        CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
+        CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
+        CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
+        CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
+        CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
+        CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
+        CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
+        CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
 };
 
 void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index bd6ad922eb7e..1f7080fab0a5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -200,7 +200,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
-        CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
+        CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index fc36d3db0b4d..a64f965c7da1 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -52,6 +52,7 @@
 #define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
 #define SMSTPCR8 0xe6150990
+#define SMSTPCR9 0xe6150994
 
 #define SDCKCR          0xE6150074
 #define SD2CKCR         0xE6150078
@@ -181,8 +182,9 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+        MSTP931, MSTP930, MSTP929, MSTP928,
         MSTP813,
-        MSTP721, MSTP720,
+        MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
         MSTP717, MSTP716,
         MSTP522,
         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
@@ -192,7 +194,16 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
+        [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
+        [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
+        [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
         [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
+        [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
+        [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
+        [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
+        [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
+        [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
         [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
@@ -251,6 +262,11 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
 
         /* MSTP */
+        CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
+        CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
+        CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
+        CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
+        CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -261,6 +277,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
+        CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
+        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
+        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
         CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
@@ -290,7 +310,7 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7790_clock_init(void)
 {
-        u32 mode = r8a7790_read_mode_pins();
+        u32 mode = rcar_gen2_read_mode_pins();
         int k, ret = 0;
 
         switch (mode & (MD(14) | MD(13))) {
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
new file mode 100644
index 000000000000..c9a26f16ce5b
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -0,0 +1,237 @@
+/*
+ * r8a7791 clock framework support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/clock.h>
+#include <mach/common.h>
+
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7791_CLOCK_ROOT() below
+ */
+
+#define MD(nr)  (1 << nr)
+
+#define CPG_BASE 0xe6150000
+#define CPG_LEN 0x1000
+
+#define SMSTPCR0        0xE6150130
+#define SMSTPCR1        0xE6150134
+#define SMSTPCR2        0xe6150138
+#define SMSTPCR3        0xE615013C
+#define SMSTPCR5        0xE6150144
+#define SMSTPCR7        0xe615014c
+#define SMSTPCR8        0xE6150990
+#define SMSTPCR9        0xE6150994
+#define SMSTPCR10       0xE6150998
+#define SMSTPCR11       0xE615099C
+
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
+
+static struct clk_mapping cpg_mapping = {
+        .phys   = CPG_BASE,
+        .len    = CPG_LEN,
+};
+
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7791_clock_init() */
+        .mapping        = &cpg_mapping,
+};
+
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7791_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+
+static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &hp_clk,
+        &p_clk,
+        &rclk_clk,
+        &mp_clk,
+        &cp_clk,
+};
+
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+        MSTP719, MSTP718, MSTP715, MSTP714,
+        MSTP216, MSTP207, MSTP206,
+        MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
+        MSTP124,
+        MSTP_NR
+};
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
+        [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
+        [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
+        [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
+        [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
+        [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
+        [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
+        [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
+        [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
+};
+
+static struct clk_lookup lookups[] = {
+
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("rclk",           &rclk_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+        CLKDEV_CON_ID("peripheral_clk", &hp_clk),
+
+        /* MSTP */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
+        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
+        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
+        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
+        CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
+        CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
+        CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+};
+
+#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
+void __init r8a7791_clock_init(void)
+{
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
+        int k, ret = 0;
+
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                shmobile_clk_init();
+        else
+                goto epanic;
+
+        return;
+
+epanic:
+        panic("failed to setup r8a7791 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index f93751caf5cb..e5be5c88644b 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -40,6 +40,9 @@ shmobile_boot_fn:
         .globl  shmobile_boot_arg
 shmobile_boot_arg:
 2:      .space  4
+        .globl  shmobile_boot_size
+shmobile_boot_size:
+        .long   . - shmobile_boot_vector
 
 /*
  * Per-CPU SMP boot function/argument selection code based on MPIDR
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 7b938681e756..e31980590eb4 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -9,16 +9,23 @@ extern void shmobile_setup_console(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
 extern unsigned long shmobile_boot_arg;
+extern unsigned long shmobile_boot_size;
 extern void shmobile_smp_boot(void);
 extern void shmobile_smp_sleep(void);
 extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
                               unsigned long arg);
+extern int shmobile_smp_cpu_disable(unsigned int cpu);
+extern void shmobile_invalidate_start(void);
 extern void shmobile_boot_scu(void);
 extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
-extern int shmobile_smp_scu_boot_secondary(unsigned int cpu,
-                                           struct task_struct *idle);
 extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
 extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
+extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus);
+extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
+                                            struct task_struct *idle);
+extern void shmobile_smp_apmu_cpu_die(unsigned int cpu);
+extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu);
+extern void shmobile_invalidate_start(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -39,7 +46,6 @@ static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
 extern void __iomem *shmobile_scu_base;
-extern void shmobile_smp_init_cpus(unsigned int ncores);
 
 static inline void __init shmobile_init_late(void)
 {
diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/include/mach/r7s72100.h
new file mode 100644
index 000000000000..5f34b20ecd4a
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r7s72100.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_R7S72100_H__
+#define __ASM_R7S72100_H__
+
+void r7s72100_add_dt_devices(void);
+void r7s72100_clock_init(void);
+void r7s72100_init_early(void);
+
+#endif /* __ASM_R7S72100_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index 5214338a6a47..ce8bdd1d8a8a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -1,6 +1,15 @@
 #ifndef __ASM_R8A73A4_H__
 #define __ASM_R8A73A4_H__
 
+/* DMA slave IDs */
+enum {
+        SHDMA_SLAVE_INVALID,
+        SHDMA_SLAVE_MMCIF0_TX,
+        SHDMA_SLAVE_MMCIF0_RX,
+        SHDMA_SLAVE_MMCIF1_TX,
+        SHDMA_SLAVE_MMCIF1_RX,
+};
+
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_add_dt_devices(void);
 void r8a73a4_clock_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 48933def0d55..441886c9714b 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +22,13 @@
 #include <linux/sh_eth.h>
 #include <linux/platform_data/camera-rcar.h>
 
+/* HPB-DMA slave IDs */
+enum {
+        HPBDMA_SLAVE_DUMMY,
+        HPBDMA_SLAVE_SDHI0_TX,
+        HPBDMA_SLAVE_SDHI0_RX,
+};
+
 extern void r8a7778_add_standard_devices(void);
 extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_dt_devices(void);
@@ -30,6 +38,9 @@ extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_init_irq_extpin_dt(int irlm);
 extern void r8a7778_pinmux_init(void);
 
+extern int r8a7778_usb_phy_power(bool enable);
+
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 11c740047e14..17af34ed89c8 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -6,6 +6,13 @@
 #include <linux/sh_eth.h>
 #include <linux/platform_data/camera-rcar.h>
 
+/* HPB-DMA slave IDs */
+enum {
+        HPBDMA_SLAVE_DUMMY,
+        HPBDMA_SLAVE_SDHI0_TX,
+        HPBDMA_SLAVE_SDHI0_RX,
+};
+
 struct platform_device;
 
 struct r8a7779_pm_ch {
@@ -26,6 +33,7 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
 
 extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq_extpin(int irlm);
+extern void r8a7779_init_irq_extpin_dt(int irlm);
 extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 177a8372abb7..5fbfa28b40b6 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -1,14 +1,13 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
 
+#include <mach/rcar-gen2.h>
+
 void r8a7790_add_standard_devices(void);
 void r8a7790_add_dt_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
 void r8a7790_init_early(void);
-void r8a7790_timer_init(void);
-
-#define MD(nr) BIT(nr)
-u32 r8a7790_read_mode_pins(void);
+extern struct smp_operations r8a7790_smp_ops;
 
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
new file mode 100644
index 000000000000..051ead3c286e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_R8A7791_H__
+#define __ASM_R8A7791_H__
+
+void r8a7791_add_standard_devices(void);
+void r8a7791_add_dt_devices(void);
+void r8a7791_clock_init(void);
+void r8a7791_init_early(void);
+extern struct smp_operations r8a7791_smp_ops;
+
+#endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h
new file mode 100644
index 000000000000..43f606eb2d82
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_RCAR_GEN2_H__
+#define __ASM_RCAR_GEN2_H__
+
+void rcar_gen2_timer_init(void);
+#define MD(nr) BIT(nr)
+u32 rcar_gen2_read_mode_pins(void);
+
+#endif /* __ASM_RCAR_GEN2_H__ */
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
new file mode 100644
index 000000000000..1da5a72d9642
--- /dev/null
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -0,0 +1,195 @@
+/*
+ * SMP support for SoCs with APMU
+ *
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+#include <mach/common.h>
+
+static struct {
+        void __iomem *iomem;
+        int bit;
+} apmu_cpus[CONFIG_NR_CPUS];
+
+#define WUPCR_OFFS 0x10
+#define PSTR_OFFS 0x40
+#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
+
+static int apmu_power_on(void __iomem *p, int bit)
+{
+        /* request power on */
+        writel_relaxed(BIT(bit), p + WUPCR_OFFS);
+
+        /* wait for APMU to finish */
+        while (readl_relaxed(p + WUPCR_OFFS) != 0)
+                ;
+
+        return 0;
+}
+
+static int apmu_power_off(void __iomem *p, int bit)
+{
+        /* request Core Standby for next WFI */
+        writel_relaxed(3, p + CPUNCR_OFFS(bit));
+        return 0;
+}
+
+static int apmu_power_off_poll(void __iomem *p, int bit)
+{
+        int k;
+
+        for (k = 0; k < 1000; k++) {
+                if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)
+                        return 1;
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
+{
+        void __iomem *p = apmu_cpus[cpu].iomem;
+
+        return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
+}
+
+static void apmu_init_cpu(struct resource *res, int cpu, int bit)
+{
+        if (apmu_cpus[cpu].iomem)
+                return;
+
+        apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
+        apmu_cpus[cpu].bit = bit;
+
+        pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit,
+                 res->start, resource_size(res));
+}
+
+static struct {
+        struct resource iomem;
+        int cpus[4];
+} apmu_config[] = {
+        {
+                .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+                .cpus = { 0, 1, 2, 3 },
+        },
+        {
+                .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
+                .cpus = { 0x100, 0x101, 0x102, 0x103 },
+        }
+};
+
+static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
+{
+        u32 id;
+        int k;
+        int bit, index;
+        bool is_allowed;
+
+        for (k = 0; k < ARRAY_SIZE(apmu_config); k++) {
+                /* only enable the cluster that includes the boot CPU */
+                is_allowed = false;
+                for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
+                        id = apmu_config[k].cpus[bit];
+                        if (id >= 0) {
+                                if (id == cpu_logical_map(0))
+                                        is_allowed = true;
+                        }
+                }
+                if (!is_allowed)
+                        continue;
+
+                for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
+                        id = apmu_config[k].cpus[bit];
+                        if (id >= 0) {
+                                index = get_logical_index(id);
+                                if (index >= 0)
+                                        fn(&apmu_config[k].iomem, index, bit);
+                        }
+                }
+        }
+}
+
+void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
+{
+        /* install boot code shared by all CPUs */
+        shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
+        shmobile_boot_arg = MPIDR_HWID_BITMASK;
+
+        /* perform per-cpu setup */
+        apmu_parse_cfg(apmu_init_cpu);
+}
+
+int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        /* For this particular CPU register boot vector */
+        shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
+
+        return apmu_wrap(cpu, apmu_power_on);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+/* nicked from arch/arm/mach-exynos/hotplug.c */
+static inline void cpu_enter_lowpower_a15(void)
+{
+        unsigned int v;
+
+        asm volatile(
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+                : "=&r" (v)
+                : "Ir" (CR_C)
+                : "cc");
+
+        flush_cache_louis();
+
+        asm volatile(
+        /*
+         * Turn off coherency
+         */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+                : "=&r" (v)
+                : "Ir" (0x40)
+                : "cc");
+
+        isb();
+        dsb();
+}
+
+void shmobile_smp_apmu_cpu_die(unsigned int cpu)
+{
+        /* For this particular CPU deregister boot vector */
+        shmobile_smp_hook(cpu, 0, 0);
+
+        /* Select next sleep mode using the APMU */
+        apmu_wrap(cpu, apmu_power_off);
+
+        /* Do ARM specific CPU shutdown */
+        cpu_enter_lowpower_a15();
+
+        /* jump to shared mach-shmobile sleep / reset code */
+        shmobile_smp_sleep();
+}
+
+int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
+{
+        return apmu_wrap(cpu, apmu_power_off_poll);
+}
+#endif
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
index c96f50160be6..673ad6e80869 100644
--- a/arch/arm/mach-shmobile/platsmp-scu.c
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -7,6 +7,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -16,6 +17,26 @@
 #include <asm/smp_scu.h>
 #include <mach/common.h>
 
+static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
+                                          unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (long)hcpu;
+
+        switch (action) {
+        case CPU_UP_PREPARE:
+                /* For this particular CPU register SCU SMP boot vector */
+                shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
+                                  (unsigned long)shmobile_scu_base);
+                break;
+        };
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block shmobile_smp_scu_notifier = {
+        .notifier_call = shmobile_smp_scu_notifier_call,
+};
+
 void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus)
 {
         /* install boot code shared by all CPUs */
@@ -25,14 +46,9 @@ void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus)
         /* enable SCU and cache coherency on booting CPU */
         scu_enable(shmobile_scu_base);
         scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
-}
 
-int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        /* For this particular CPU register SCU boot vector */
-        shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
-                          (unsigned long)shmobile_scu_base);
-        return 0;
+        /* Use CPU notifier for reset vector control */
+        register_cpu_notifier(&shmobile_smp_scu_notifier);
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index d4ae616bcedb..9ebc246b8d7d 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -11,25 +11,10 @@
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
-#include <linux/smp.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <mach/common.h>
 
-void __init shmobile_smp_init_cpus(unsigned int ncores)
-{
-        unsigned int i;
-
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                        ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
 extern unsigned long shmobile_smp_fn[];
 extern unsigned long shmobile_smp_arg[];
 extern unsigned long shmobile_smp_mpidr[];
@@ -44,3 +29,10 @@ void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg)
         shmobile_smp_arg[cpu] = arg;
         flush_cache_all();
 }
+
+#ifdef CONFIG_HOTPLUG_CPU
+int shmobile_smp_cpu_disable(unsigned int cpu)
+{
+        return 0; /* Hotplug of any CPU is supported */
+}
+#endif
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
new file mode 100644
index 000000000000..d4eb509a1c87
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -0,0 +1,88 @@
+/*
+ * r7s72100 processor support
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <linux/serial_sci.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/r7s72100.h>
+#include <asm/mach/arch.h>
+
+#define SCIF_DATA(index, baseaddr, irq)                                 \
+[index] = {                                                             \
+        .type           = PORT_SCIF,                                    \
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,               \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
+        .scbrr_algo_id  = SCBRR_ALGO_2,                                 \
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
+                          SCSCR_REIE,                                   \
+        .mapbase        = baseaddr,                                     \
+        .irqs           = { irq + 1, irq + 2, irq + 3, irq },           \
+}
+
+enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 };
+
+static const struct plat_sci_port scif[] __initconst = {
+        SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */
+        SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */
+        SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */
+        SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */
+        SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */
+        SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
+        SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
+        SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
+};
+
+static inline void r7s72100_register_scif(int idx)
+{
+        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
+                                      sizeof(struct plat_sci_port));
+}
+
+void __init r7s72100_add_dt_devices(void)
+{
+        r7s72100_register_scif(SCIF0);
+        r7s72100_register_scif(SCIF1);
+        r7s72100_register_scif(SCIF2);
+        r7s72100_register_scif(SCIF3);
+        r7s72100_register_scif(SCIF4);
+        r7s72100_register_scif(SCIF5);
+        r7s72100_register_scif(SCIF6);
+        r7s72100_register_scif(SCIF7);
+}
+
+void __init r7s72100_init_early(void)
+{
+        shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */
+}
+
+#ifdef CONFIG_USE_OF
+static const char *r7s72100_boards_compat_dt[] __initdata = {
+        "renesas,r7s72100",
+        NULL,
+};
+
+DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
+        .init_early     = r7s72100_init_early,
+        .dt_compat      = r7s72100_boards_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 53a896275cae..b0f2749071be 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -22,8 +22,10 @@
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 #include <mach/common.h>
+#include <mach/dma-register.h>
 #include <mach/irqs.h>
 #include <mach/r8a73a4.h>
 #include <asm/mach/arch.h>
@@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
         r8a7790_register_cmt(10);
 }
 
+/* DMA */
+static const struct sh_dmae_slave_config dma_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_MMCIF0_TX,
+                .addr           = 0xee200034,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF0_RX,
+                .addr           = 0xee200034,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF1_TX,
+                .addr           = 0xee220034,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xe1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF1_RX,
+                .addr           = 0xee220034,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xe2,
+        },
+};
+
+#define DMAE_CHANNEL(a, b)                              \
+        {                                               \
+                .offset         = (a) - 0x20,           \
+                .dmars          = (a) - 0x20 + 0x40,    \
+                .chclr_bit      = (b),                  \
+                .chclr_offset   = 0x80 - 0x20,          \
+        }
+
+static const struct sh_dmae_channel dma_channels[] = {
+        DMAE_CHANNEL(0x8000, 0),
+        DMAE_CHANNEL(0x8080, 1),
+        DMAE_CHANNEL(0x8100, 2),
+        DMAE_CHANNEL(0x8180, 3),
+        DMAE_CHANNEL(0x8200, 4),
+        DMAE_CHANNEL(0x8280, 5),
+        DMAE_CHANNEL(0x8300, 6),
+        DMAE_CHANNEL(0x8380, 7),
+        DMAE_CHANNEL(0x8400, 8),
+        DMAE_CHANNEL(0x8480, 9),
+        DMAE_CHANNEL(0x8500, 10),
+        DMAE_CHANNEL(0x8580, 11),
+        DMAE_CHANNEL(0x8600, 12),
+        DMAE_CHANNEL(0x8680, 13),
+        DMAE_CHANNEL(0x8700, 14),
+        DMAE_CHANNEL(0x8780, 15),
+        DMAE_CHANNEL(0x8800, 16),
+        DMAE_CHANNEL(0x8880, 17),
+        DMAE_CHANNEL(0x8900, 18),
+        DMAE_CHANNEL(0x8980, 19),
+};
+
+static const struct sh_dmae_pdata dma_pdata = {
+        .slave          = dma_slaves,
+        .slave_num      = ARRAY_SIZE(dma_slaves),
+        .channel        = dma_channels,
+        .channel_num    = ARRAY_SIZE(dma_channels),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chclr_present  = 1,
+        .chclr_bitwise  = 1,
+};
+
+static struct resource dma_resources[] = {
+        DEFINE_RES_MEM(0xe6700020, 0x89e0),
+        DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
+        {
+                /* IRQ for channels 0-19 */
+                .start  = gic_spi(200),
+                .end    = gic_spi(219),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+#define r8a73a4_register_dmac()                                                 \
+        platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0,    \
+                                dma_resources, ARRAY_SIZE(dma_resources),       \
+                                &dma_pdata, sizeof(dma_pdata))
+
 void __init r8a73a4_add_standard_devices(void)
 {
         r8a73a4_add_dt_devices();
         r8a73a4_register_irqc(0);
         r8a73a4_register_irqc(1);
         r8a73a4_register_thermal();
+        r8a73a4_register_dmac();
 }
 
 void __init r8a73a4_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 468ee6551184..03fcc5974ef9 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/dma-rcar-hpbdma.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
@@ -95,29 +96,46 @@ static struct sh_timer_config sh_tmu1_platform_data __initdata = {
                 &sh_tmu##idx##_platform_data,           \
                 sizeof(sh_tmu##idx##_platform_data))
 
-/* USB */
-static struct usb_phy *phy;
+int r8a7778_usb_phy_power(bool enable)
+{
+        static struct usb_phy *phy = NULL;
+        int ret = 0;
+
+        if (!phy)
+                phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+        if (IS_ERR(phy)) {
+                pr_err("kernel doesn't have usb phy driver\n");
+                return PTR_ERR(phy);
+        }
+
+        if (enable)
+                ret = usb_phy_init(phy);
+        else
+                usb_phy_shutdown(phy);
 
+        return ret;
+}
+
+/* USB */
 static int usb_power_on(struct platform_device *pdev)
 {
-        if (IS_ERR(phy))
-                return PTR_ERR(phy);
+        int ret = r8a7778_usb_phy_power(true);
+
+        if (ret)
+                return ret;
 
         pm_runtime_enable(&pdev->dev);
         pm_runtime_get_sync(&pdev->dev);
 
-        usb_phy_init(phy);
-
         return 0;
 }
 
 static void usb_power_off(struct platform_device *pdev)
 {
-        if (IS_ERR(phy))
+        if (r8a7778_usb_phy_power(false))
                 return;
 
-        usb_phy_shutdown(phy);
-
         pm_runtime_put_sync(&pdev->dev);
         pm_runtime_disable(&pdev->dev);
 }
@@ -291,6 +309,88 @@ void __init r8a7778_add_dt_devices(void)
         r8a7778_register_tmu(1);
 }
 
+/* HPB-DMA */
+
+/* Asynchronous mode register (ASYNCMDR) bits */
+#define HPB_DMAE_ASYNCMDR_ASMD22_MASK   BIT(2)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI  0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD21_MASK   BIT(1)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI  0       /* SDHI0 */
+
+static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
+        {
+                .id     = HPBDMA_SLAVE_SDHI0_TX,
+                .addr   = 0xffe4c000 + 0x30,
+                .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
+                          HPB_DMAE_DCR_DMDL |
+                          HPB_DMAE_DCR_DPDS_16BIT,
+                .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
+                          HPB_DMAE_ASYNCRSTR_ASRST22 |
+                          HPB_DMAE_ASYNCRSTR_ASRST23,
+                .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
+                .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
+                .port   = 0x0D0C,
+                .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
+                .dma_ch = 21,
+        }, {
+                .id     = HPBDMA_SLAVE_SDHI0_RX,
+                .addr   = 0xffe4c000 + 0x30,
+                .dcr    = HPB_DMAE_DCR_SMDL |
+                          HPB_DMAE_DCR_SPDS_16BIT |
+                          HPB_DMAE_DCR_DPDS_16BIT,
+                .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
+                          HPB_DMAE_ASYNCRSTR_ASRST22 |
+                          HPB_DMAE_ASYNCRSTR_ASRST23,
+                .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
+                .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
+                .port   = 0x0D0C,
+                .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
+                .dma_ch = 22,
+        },
+};
+
+static const struct hpb_dmae_channel hpb_dmae_channels[] = {
+        HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
+        HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
+};
+
+static struct hpb_dmae_pdata dma_platform_data __initdata = {
+        .slaves                 = hpb_dmae_slaves,
+        .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
+        .channels               = hpb_dmae_channels,
+        .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
+        .ts_shift               = {
+                [XMIT_SZ_8BIT]  = 0,
+                [XMIT_SZ_16BIT] = 1,
+                [XMIT_SZ_32BIT] = 2,
+        },
+        .num_hw_channels        = 39,
+};
+
+static struct resource hpb_dmae_resources[] __initdata = {
+        /* Channel registers */
+        DEFINE_RES_MEM(0xffc08000, 0x1000),
+        /* Common registers */
+        DEFINE_RES_MEM(0xffc09000, 0x170),
+        /* Asynchronous reset registers */
+        DEFINE_RES_MEM(0xffc00300, 4),
+        /* Asynchronous mode registers */
+        DEFINE_RES_MEM(0xffc00400, 4),
+        /* IRQ for DMA channels */
+        DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
+};
+
+static void __init r8a7778_register_hpb_dmae(void)
+{
+        platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
+                                          hpb_dmae_resources,
+                                          ARRAY_SIZE(hpb_dmae_resources),
+                                          &dma_platform_data,
+                                          sizeof(dma_platform_data));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
         r8a7778_add_dt_devices();
@@ -301,12 +401,12 @@ void __init r8a7778_add_standard_devices(void)
         r8a7778_register_hspi(0);
         r8a7778_register_hspi(1);
         r8a7778_register_hspi(2);
+
+        r8a7778_register_hpb_dmae();
 }
 
 void __init r8a7778_init_late(void)
 {
-        phy = usb_get_phy(USB_PHY_TYPE_USB2);
-
         platform_device_register_full(&ehci_info);
         platform_device_register_full(&ohci_info);
 }
@@ -328,7 +428,7 @@ static struct resource irqpin_resources[] __initdata = {
         DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
 };
 
-void __init r8a7778_init_irq_extpin(int irlm)
+void __init r8a7778_init_irq_extpin_dt(int irlm)
 {
         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
         unsigned long tmp;
@@ -346,7 +446,11 @@ void __init r8a7778_init_irq_extpin(int irlm)
         tmp |= (1 << 21); /* LVLMODE = 1 */
         iowrite32(tmp, icr0);
         iounmap(icr0);
+}
 
+void __init r8a7778_init_irq_extpin(int irlm)
+{
+        r8a7778_init_irq_extpin_dt(irlm);
         if (irlm)
                 platform_device_register_resndata(
                         &platform_bus, "renesas_intc_irqpin", -1,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index ecd0148ee1e1..13049e9d691c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/dma-rcar-hpbdma.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
@@ -97,7 +98,7 @@ static struct resource irqpin0_resources[] __initdata = {
         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
 };
 
-void __init r8a7779_init_irq_extpin(int irlm)
+void __init r8a7779_init_irq_extpin_dt(int irlm)
 {
         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
         u32 tmp;
@@ -115,7 +116,11 @@ void __init r8a7779_init_irq_extpin(int irlm)
         tmp |= (1 << 21); /* LVLMODE = 1 */
         iowrite32(tmp, icr0);
         iounmap(icr0);
+}
 
+void __init r8a7779_init_irq_extpin(int irlm)
+{
+        r8a7779_init_irq_extpin_dt(irlm);
         if (irlm)
                 platform_device_register_resndata(
                         &platform_bus, "renesas_intc_irqpin", -1,
@@ -632,6 +637,158 @@ static struct platform_device_info *vin_info_table[] __initdata = {
         &vin3_info,
 };
 
+/* HPB-DMA */
+
+/* Asynchronous mode register bits */
+#define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
+#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
+#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
+#define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
+#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
+#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
+#define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
+#define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
+#define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
+#define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
+#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
+#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
+#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
+
+static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
+        {
+                .id     = HPBDMA_SLAVE_SDHI0_TX,
+                .addr   = 0xffe4c000 + 0x30,
+                .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
+                          HPB_DMAE_DCR_DMDL |
+                          HPB_DMAE_DCR_DPDS_16BIT,
+                .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
+                          HPB_DMAE_ASYNCRSTR_ASRST22 |
+                          HPB_DMAE_ASYNCRSTR_ASRST23,
+                .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
+                          HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
+                .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
+                          HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
+                .port   = 0x0D0C,
+                .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
+                .dma_ch = 21,
+        }, {
+                .id     = HPBDMA_SLAVE_SDHI0_RX,
+                .addr   = 0xffe4c000 + 0x30,
+                .dcr    = HPB_DMAE_DCR_SMDL |
+                          HPB_DMAE_DCR_SPDS_16BIT |
+                          HPB_DMAE_DCR_DPDS_16BIT,
+                .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
+                          HPB_DMAE_ASYNCRSTR_ASRST22 |
+                          HPB_DMAE_ASYNCRSTR_ASRST23,
+                .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
+                          HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
+                .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
+                          HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
+                .port   = 0x0D0C,
+                .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
+                .dma_ch = 22,
+        },
+};
+
+static const struct hpb_dmae_channel hpb_dmae_channels[] = {
+        HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
+        HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
+};
+
+static struct hpb_dmae_pdata dma_platform_data __initdata = {
+        .slaves                 = hpb_dmae_slaves,
+        .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
+        .channels               = hpb_dmae_channels,
+        .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
+        .ts_shift               = {
+                [XMIT_SZ_8BIT]  = 0,
+                [XMIT_SZ_16BIT] = 1,
+                [XMIT_SZ_32BIT] = 2,
+        },
+        .num_hw_channels        = 44,
+};
+
+static struct resource hpb_dmae_resources[] __initdata = {
+        /* Channel registers */
+        DEFINE_RES_MEM(0xffc08000, 0x1000),
+        /* Common registers */
+        DEFINE_RES_MEM(0xffc09000, 0x170),
+        /* Asynchronous reset registers */
+        DEFINE_RES_MEM(0xffc00300, 4),
+        /* Asynchronous mode registers */
+        DEFINE_RES_MEM(0xffc00400, 4),
+        /* IRQ for DMA channels */
+        DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
+};
+
+static void __init r8a7779_register_hpb_dmae(void)
+{
+        platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
+                                          hpb_dmae_resources,
+                                          ARRAY_SIZE(hpb_dmae_resources),
+                                          &dma_platform_data,
+                                          sizeof(dma_platform_data));
+}
+
 static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -665,6 +822,7 @@ void __init r8a7779_add_standard_devices(void)
                             ARRAY_SIZE(r8a7779_devices_dt));
         platform_add_devices(r8a7779_standard_devices,
                             ARRAY_SIZE(r8a7779_standard_devices));
+        r8a7779_register_hpb_dmae();
 }
 
 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index e0d29a265c2d..c47bcebbcb00 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/clocksource.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
@@ -203,71 +202,6 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_thermal();
 }
 
-#define MODEMR 0xe6160060
-
-u32 __init r8a7790_read_mode_pins(void)
-{
-        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
-        u32 mode;
-
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
-
-        return mode;
-}
-
-#define CNTCR 0
-#define CNTFID0 0x20
-
-void __init r8a7790_timer_init(void)
-{
-#ifdef CONFIG_ARM_ARCH_TIMER
-        u32 mode = r8a7790_read_mode_pins();
-        void __iomem *base;
-        int extal_mhz = 0;
-        u32 freq;
-
-        /* At Linux boot time the r8a7790 arch timer comes up
-         * with the counter disabled. Moreover, it may also report
-         * a potentially incorrect fixed 13 MHz frequency. To be
-         * correct these registers need to be updated to use the
-         * frequency EXTAL / 2 which can be determined by the MD pins.
-         */
-
-        switch (mode & (MD(14) | MD(13))) {
-        case 0:
-                extal_mhz = 15;
-                break;
-        case MD(13):
-                extal_mhz = 20;
-                break;
-        case MD(14):
-                extal_mhz = 26;
-                break;
-        case MD(13) | MD(14):
-                extal_mhz = 30;
-                break;
-        }
-
-        /* The arch timer frequency equals EXTAL / 2 */
-        freq = extal_mhz * (1000000 / 2);
-
-        /* Remap "armgcnt address map" space */
-        base = ioremap(0xe6080000, PAGE_SIZE);
-
-        /* Update registers with correct frequency */
-        iowrite32(freq, base + CNTFID0);
-        asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
-
-        /* make sure arch timer is started by setting bit 0 of CNTCR */
-        iowrite32(1, base + CNTCR);
-        iounmap(base);
-#endif /* CONFIG_ARM_ARCH_TIMER */
-
-        clocksource_of_init();
-}
-
 void __init r8a7790_init_early(void)
 {
 #ifndef CONFIG_ARM_ARCH_TIMER
@@ -283,8 +217,9 @@ static const char * const r8a7790_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
+        .smp            = smp_ops(r8a7790_smp_ops),
         .init_early     = r8a7790_init_early,
-        .init_time      = r8a7790_timer_init,
+        .init_time      = rcar_gen2_timer_init,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
new file mode 100644
index 000000000000..d9393d61ee27
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -0,0 +1,184 @@
+/*
+ * r8a7791 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <linux/platform_data/irq-renesas-irqc.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/r8a7791.h>
+#include <mach/rcar-gen2.h>
+#include <asm/mach/arch.h>
+
+#define SCIF_COMMON(scif_type, baseaddr, irq)                   \
+        .type           = scif_type,                            \
+        .mapbase        = baseaddr,                             \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
+        .irqs           = SCIx_IRQ_MUXED(irq)
+
+#define SCIFA_DATA(index, baseaddr, irq)                \
+[index] = {                                             \
+        SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
+        .scbrr_algo_id  = SCBRR_ALGO_4,                 \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
+}
+
+#define SCIFB_DATA(index, baseaddr, irq)        \
+[index] = {                                     \
+        SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
+        .scbrr_algo_id  = SCBRR_ALGO_4,         \
+        .scscr = SCSCR_RE | SCSCR_TE,           \
+}
+
+#define SCIF_DATA(index, baseaddr, irq)         \
+[index] = {                                             \
+        SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
+        .scbrr_algo_id  = SCBRR_ALGO_2,                 \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
+}
+
+#define HSCIF_DATA(index, baseaddr, irq)                \
+[index] = {                                             \
+        SCIF_COMMON(PORT_HSCIF, baseaddr, irq),         \
+        .scbrr_algo_id  = SCBRR_ALGO_6,                 \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
+}
+
+enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
+        SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
+
+static const struct plat_sci_port scif[] __initconst = {
+        SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
+        SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
+        SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
+        SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
+        SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
+        SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
+        SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
+        SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
+        SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
+        SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
+        SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
+        SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
+        SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
+        SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
+        SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
+};
+
+static inline void r8a7791_register_scif(int idx)
+{
+        platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
+                                      sizeof(struct plat_sci_port));
+}
+
+static const struct sh_timer_config cmt00_platform_data __initconst = {
+        .name = "CMT00",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static const struct resource cmt00_resources[] __initconst = {
+        DEFINE_RES_MEM(0xffca0510, 0x0c),
+        DEFINE_RES_MEM(0xffca0500, 0x04),
+        DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
+};
+
+#define r8a7791_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
+static struct renesas_irqc_config irqc0_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
+};
+
+static struct resource irqc0_resources[] = {
+        DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
+        DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
+        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
+        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
+        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
+        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
+        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
+        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
+};
+
+#define r8a7791_register_irqc(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "renesas_irqc", \
+                                          idx, irqc##idx##_resources,   \
+                                          ARRAY_SIZE(irqc##idx##_resources), \
+                                          &irqc##idx##_data,            \
+                                          sizeof(struct renesas_irqc_config))
+
+void __init r8a7791_add_dt_devices(void)
+{
+        r8a7791_register_scif(SCIFA0);
+        r8a7791_register_scif(SCIFA1);
+        r8a7791_register_scif(SCIFB0);
+        r8a7791_register_scif(SCIFB1);
+        r8a7791_register_scif(SCIFB2);
+        r8a7791_register_scif(SCIFA2);
+        r8a7791_register_scif(SCIF0);
+        r8a7791_register_scif(SCIF1);
+        r8a7791_register_scif(SCIF2);
+        r8a7791_register_scif(SCIF3);
+        r8a7791_register_scif(SCIF4);
+        r8a7791_register_scif(SCIF5);
+        r8a7791_register_scif(SCIFA3);
+        r8a7791_register_scif(SCIFA4);
+        r8a7791_register_scif(SCIFA5);
+        r8a7791_register_cmt(00);
+}
+
+void __init r8a7791_add_standard_devices(void)
+{
+        r8a7791_add_dt_devices();
+        r8a7791_register_irqc(0);
+}
+
+void __init r8a7791_init_early(void)
+{
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
+#endif
+}
+
+#ifdef CONFIG_USE_OF
+static const char *r8a7791_boards_compat_dt[] __initdata = {
+        "renesas,r8a7791",
+        NULL,
+};
+
+DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
+        .smp            = smp_ops(r8a7791_smp_ops),
+        .init_early     = r8a7791_init_early,
+        .init_time      = rcar_gen2_timer_init,
+        .dt_compat      = r8a7791_boards_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
new file mode 100644
index 000000000000..5734c24bf6c7
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -0,0 +1,91 @@
+/*
+ * R-Car Generation 2 support
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/clocksource.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <mach/common.h>
+#include <mach/rcar-gen2.h>
+#include <asm/mach/arch.h>
+
+#define MODEMR 0xe6160060
+
+u32 __init rcar_gen2_read_mode_pins(void)
+{
+        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+        u32 mode;
+
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        return mode;
+}
+
+#define CNTCR 0
+#define CNTFID0 0x20
+
+void __init rcar_gen2_timer_init(void)
+{
+#ifdef CONFIG_ARM_ARCH_TIMER
+        u32 mode = rcar_gen2_read_mode_pins();
+        void __iomem *base;
+        int extal_mhz = 0;
+        u32 freq;
+
+        /* At Linux boot time the r8a7790 arch timer comes up
+         * with the counter disabled. Moreover, it may also report
+         * a potentially incorrect fixed 13 MHz frequency. To be
+         * correct these registers need to be updated to use the
+         * frequency EXTAL / 2 which can be determined by the MD pins.
+         */
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                extal_mhz = 15;
+                break;
+        case MD(13):
+                extal_mhz = 20;
+                break;
+        case MD(14):
+                extal_mhz = 26;
+                break;
+        case MD(13) | MD(14):
+                extal_mhz = 30;
+                break;
+        }
+
+        /* The arch timer frequency equals EXTAL / 2 */
+        freq = extal_mhz * (1000000 / 2);
+
+        /* Remap "armgcnt address map" space */
+        base = ioremap(0xe6080000, PAGE_SIZE);
+
+        /* Update registers with correct frequency */
+        iowrite32(freq, base + CNTFID0);
+        asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+        /* make sure arch timer is started by setting bit 0 of CNTCR */
+        iowrite32(1, base + CNTCR);
+        iounmap(base);
+#endif /* CONFIG_ARM_ARCH_TIMER */
+
+        clocksource_of_init();
+}
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 522de5ebb55f..f2ca92308f75 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -34,12 +34,6 @@
 
 static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int ret;
-
-        ret = shmobile_smp_scu_boot_secondary(cpu, idle);
-        if (ret)
-                return ret;
-
         arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
         return 0;
 }
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 0f05e9fb722f..627c1f0d9478 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -87,10 +87,6 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
         unsigned int lcpu = cpu_logical_map(cpu);
         int ret;
 
-        ret = shmobile_smp_scu_boot_secondary(cpu, idle);
-        if (ret)
-                return ret;
-
         if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[lcpu];
 
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
new file mode 100644
index 000000000000..015e2753de1f
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -0,0 +1,67 @@
+/*
+ * SMP support for r8a7790
+ *
+ * Copyright (C) 2012-2013 Renesas Solutions Corp.
+ * Copyright (C) 2012 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/smp_plat.h>
+#include <mach/common.h>
+
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA7BAR          0x0030
+#define CA15RESCNT      0x0040
+#define CA7RESCNT       0x0044
+#define MERAM           0xe8080000
+
+static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
+{
+        void __iomem *p;
+        u32 bar;
+
+        /* let APMU code install data related to shmobile_boot_vector */
+        shmobile_smp_apmu_prepare_cpus(max_cpus);
+
+        /* MERAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(MERAM, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (MERAM >> 8) & 0xfffffc00;
+        writel_relaxed(bar, p + CA15BAR);
+        writel_relaxed(bar, p + CA7BAR);
+        writel_relaxed(bar | 0x10, p + CA15BAR);
+        writel_relaxed(bar | 0x10, p + CA7BAR);
+
+        /* enable clocks to all CPUs */
+        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
+                       p + CA15RESCNT);
+        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
+                       p + CA7RESCNT);
+        iounmap(p);
+}
+
+struct smp_operations r8a7790_smp_ops __initdata = {
+        .smp_prepare_cpus       = r8a7790_smp_prepare_cpus,
+        .smp_boot_secondary     = shmobile_smp_apmu_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = shmobile_smp_cpu_disable,
+        .cpu_die                = shmobile_smp_apmu_cpu_die,
+        .cpu_kill               = shmobile_smp_apmu_cpu_kill,
+#endif
+};
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
new file mode 100644
index 000000000000..2df5bd190fe4
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -0,0 +1,62 @@
+/*
+ * SMP support for r8a7791
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/smp_plat.h>
+#include <mach/common.h>
+#include <mach/r8a7791.h>
+
+#define RST             0xe6160000
+#define CA15BAR         0x0020
+#define CA15RESCNT      0x0040
+#define RAM             0xe6300000
+
+static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
+{
+        void __iomem *p;
+        u32 bar;
+
+        /* let APMU code install data related to shmobile_boot_vector */
+        shmobile_smp_apmu_prepare_cpus(max_cpus);
+
+        /* RAM for jump stub, because BAR requires 256KB aligned address */
+        p = ioremap_nocache(RAM, shmobile_boot_size);
+        memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+        iounmap(p);
+
+        /* setup reset vectors */
+        p = ioremap_nocache(RST, 0x63);
+        bar = (RAM >> 8) & 0xfffffc00;
+        writel_relaxed(bar, p + CA15BAR);
+        writel_relaxed(bar | 0x10, p + CA15BAR);
+
+        /* enable clocks to all CPUs */
+        writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
+                       p + CA15RESCNT);
+        iounmap(p);
+}
+
+struct smp_operations r8a7791_smp_ops __initdata = {
+        .smp_prepare_cpus       = r8a7791_smp_prepare_cpus,
+        .smp_boot_secondary     = shmobile_smp_apmu_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = shmobile_smp_cpu_disable,
+        .cpu_die                = shmobile_smp_apmu_cpu_die,
+        .cpu_kill               = shmobile_smp_apmu_cpu_kill,
+#endif
+};
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 0baa24443793..13ba36a6831f 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -46,11 +46,6 @@ void __init sh73a0_register_twd(void)
 static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned int lcpu = cpu_logical_map(cpu);
-        int ret;
-
-        ret = shmobile_smp_scu_boot_secondary(cpu, idle);
-        if (ret)
-                return ret;
 
         if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3)
                 __raw_writel(1 << lcpu, WUPCR); /* wake up */
@@ -71,18 +66,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
         shmobile_smp_scu_prepare_cpus(max_cpus);
 }
 
-#ifdef CONFIG_HOTPLUG_CPU
-static int sh73a0_cpu_disable(unsigned int cpu)
-{
-        return 0; /* CPU0 and CPU1 supported */
-}
-#endif /* CONFIG_HOTPLUG_CPU */
-
 struct smp_operations sh73a0_smp_ops __initdata = {
         .smp_prepare_cpus       = sh73a0_smp_prepare_cpus,
         .smp_boot_secondary     = sh73a0_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
-        .cpu_disable            = sh73a0_cpu_disable,
+        .cpu_disable            = shmobile_smp_cpu_disable,
         .cpu_die                = shmobile_smp_scu_cpu_die,
         .cpu_kill               = shmobile_smp_scu_cpu_kill,
 #endif
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3ab2f65f8a50..c9e72c89066a 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,14 +1,14 @@
 config ARCH_SUNXI
         bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
+        select ARM_GIC
         select CLKSRC_MMIO
         select CLKSRC_OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
+        select HAVE_SMP
         select PINCTRL
+        select PINCTRL_SUNXI
         select SPARSE_IRQ
         select SUN4I_TIMER
-        select PINCTRL_SUNXI
-        select ARM_GIC
-        select HAVE_SMP
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 90dda6228510..61d3a387f01c 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -90,14 +90,13 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd)
 }
 
 static struct of_device_id sunxi_restart_ids[] = {
-        { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
-        { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
+        { .compatible = "allwinner,sun4i-wdt" },
+        { .compatible = "allwinner,sun6i-wdt" },
         { /*sentinel*/ }
 };
 
 static void sunxi_setup_restart(void)
 {
-        const struct of_device_id *of_id;
         struct device_node *np;
 
         np = of_find_matching_node(NULL, sunxi_restart_ids);
@@ -106,11 +105,6 @@ static void sunxi_setup_restart(void)
 
         wdt_base = of_iomap(np, 0);
         WARN(!wdt_base, "failed to map watchdog base address");
-
-        of_id = of_match_node(sunxi_restart_ids, np);
-        WARN(!of_id, "restart function not available");
-
-        arm_pm_restart = of_id->data;
 }
 
 static void __init sunxi_dt_init(void)
@@ -124,12 +118,33 @@ static const char * const sunxi_board_dt_compat[] = {
         "allwinner,sun4i-a10",
         "allwinner,sun5i-a10s",
         "allwinner,sun5i-a13",
-        "allwinner,sun6i-a31",
-        "allwinner,sun7i-a20",
         NULL,
 };
 
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
         .init_machine   = sunxi_dt_init,
         .dt_compat      = sunxi_board_dt_compat,
+        .restart        = sun4i_restart,
+MACHINE_END
+
+static const char * const sun6i_board_dt_compat[] = {
+        "allwinner,sun6i-a31",
+        NULL,
+};
+
+DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
+        .init_machine   = sunxi_dt_init,
+        .dt_compat      = sun6i_board_dt_compat,
+        .restart        = sun6i_restart,
+MACHINE_END
+
+static const char * const sun7i_board_dt_compat[] = {
+        "allwinner,sun7i-a20",
+        NULL,
+};
+
+DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
+        .init_machine   = sunxi_dt_init,
+        .dt_compat      = sun7i_board_dt_compat,
+        .restart        = sun4i_restart,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 56bb6c35d958..0bf04a0bca9d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -59,6 +59,14 @@ config ARCH_TEGRA_114_SOC
           Support for NVIDIA Tegra T114 processor family, based on the
           ARM CortexA15MP CPU
 
+config ARCH_TEGRA_124_SOC
+        bool "Enable support for Tegra124 family"
+        select ARM_L1_CACHE_SHIFT_6
+        select HAVE_ARM_ARCH_TIMER
+        help
+          Support for NVIDIA Tegra T124 processor family, based on the
+          ARM CortexA15MP CPU
+
 config TEGRA_AHB
         bool "Enable AHB driver for NVIDIA Tegra SoCs"
         default y
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 97eb48e977e5..019bb1758662 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -35,5 +35,10 @@ obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)        += sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)        += pm-tegra30.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)        += cpuidle-tegra114.o
+endif
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-paz00.o
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 0961dfcf83a4..7bc5d8d667fe 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -39,7 +39,9 @@ void __init tegra_cpuidle_init(void)
                         tegra30_cpuidle_init();
                 break;
         case TEGRA114:
-                if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+        case TEGRA124:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                         tegra114_cpuidle_init();
                 break;
         }
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 5348543382bf..ce8ab8abf061 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
                 break;
         case TEGRA30:
         case TEGRA114:
+        case TEGRA124:
                 /* clear wfe bitmap */
                 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
                 /* clear wfi bitmap */
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
                 break;
         case TEGRA30:
         case TEGRA114:
+        case TEGRA124:
                 /* clear wfe bitmap */
                 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
                 /* clear wfi bitmap */
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f3b5d0d7b620..d4639c506622 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -21,14 +21,26 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/export.h>
+#include <linux/random.h>
 #include <linux/tegra-soc.h>
 
 #include "fuse.h"
 #include "iomap.h"
 #include "apbio.h"
 
+/* Tegra20 only */
 #define FUSE_UID_LOW            0x108
 #define FUSE_UID_HIGH           0x10c
+
+/* Tegra30 and later */
+#define FUSE_VENDOR_CODE        0x200
+#define FUSE_FAB_CODE           0x204
+#define FUSE_LOT_CODE_0         0x208
+#define FUSE_LOT_CODE_1         0x20c
+#define FUSE_WAFER_ID           0x210
+#define FUSE_X_COORDINATE       0x214
+#define FUSE_Y_COORDINATE       0x218
+
 #define FUSE_SKU_INFO           0x110
 
 #define TEGRA20_FUSE_SPARE_BIT          0x200
@@ -112,21 +124,51 @@ u32 tegra_read_chipid(void)
         return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
 }
 
+static void __init tegra20_fuse_init_randomness(void)
+{
+        u32 randomness[2];
+
+        randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
+        randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
+
+        add_device_randomness(randomness, sizeof(randomness));
+}
+
+/* Applies to Tegra30 or later */
+static void __init tegra30_fuse_init_randomness(void)
+{
+        u32 randomness[7];
+
+        randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
+        randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
+        randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
+        randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
+        randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
+        randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
+        randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
+
+        add_device_randomness(randomness, sizeof(randomness));
+}
+
 void __init tegra_init_fuse(void)
 {
         u32 id;
+        u32 randomness[5];
 
         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
         reg |= 1 << 28;
         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
         reg = tegra_fuse_readl(FUSE_SKU_INFO);
+        randomness[0] = reg;
         tegra_sku_id = reg & 0xFF;
 
         reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
+        randomness[1] = reg;
         tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
 
         id = tegra_read_chipid();
+        randomness[2] = id;
         tegra_chip_id = (id >> 8) & 0xff;
 
         switch (tegra_chip_id) {
@@ -149,6 +191,18 @@ void __init tegra_init_fuse(void)
 
         tegra_revision = tegra_get_revision(id);
         tegra_init_speedo_data();
+        randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
+        randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;
+
+        add_device_randomness(randomness, sizeof(randomness));
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                tegra20_fuse_init_randomness();
+        case TEGRA30:
+        case TEGRA114:
+        default:
+                tegra30_fuse_init_randomness();
+        }
 
         pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
                 tegra_revision_name[tegra_revision],
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index def79683bef6..c01d04785d67 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -29,6 +29,7 @@
 #define TEGRA20         0x20
 #define TEGRA30         0x30
 #define TEGRA114        0x35
+#define TEGRA124        0x40
 
 #ifndef __ASSEMBLY__
 enum tegra_revision {
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 04de2e860923..ff26af26bd0c 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -57,4 +57,6 @@ void __init tegra_hotplug_init(void)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index cbee57fc4fd8..26b1c2ad0ceb 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -105,6 +105,9 @@
 #define TEGRA_EMC1_BASE                 0x7001A800
 #define TEGRA_EMC1_SIZE                 SZ_2K
 
+#define TEGRA124_EMC_BASE               0x7001B000
+#define TEGRA124_EMC_SIZE               SZ_2K
+
 #define TEGRA_CSITE_BASE                0x70040000
 #define TEGRA_CSITE_SIZE                SZ_256K
 
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2d0203627fbb..eb72ae709124 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -176,6 +176,8 @@ static int tegra_boot_secondary(unsigned int cpu,
                 return tegra30_boot_secondary(cpu, idle);
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
                 return tegra114_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
+                return tegra114_boot_secondary(cpu, idle);
 
         return -EINVAL;
 }
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88af1cc1..4ae0286b468d 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
                 break;
         case TEGRA30:
         case TEGRA114:
+        case TEGRA124:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                         tegra_tear_down_cpu = tegra30_tear_down_cpu;
                 break;
         }
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
                 break;
         case TEGRA30:
         case TEGRA114:
+        case TEGRA124:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                         tegra30_lp1_iram_hook();
                 break;
         default:
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
                 break;
         case TEGRA30:
         case TEGRA114:
+        case TEGRA124:
                 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                         tegra30_sleep_core_init();
                 break;
         default:
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 93a4dbcde27e..fb7920201ab4 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -20,6 +20,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/tegra-powergate.h>
 
 #include "flowctrl.h"
 #include "fuse.h"
@@ -43,12 +44,6 @@
 #define PMC_CPUPWRGOOD_TIMER    0xc8
 #define PMC_CPUPWROFF_TIMER     0xcc
 
-#define TEGRA_POWERGATE_PCIE    3
-#define TEGRA_POWERGATE_VDEC    4
-#define TEGRA_POWERGATE_CPU1    9
-#define TEGRA_POWERGATE_CPU2    10
-#define TEGRA_POWERGATE_CPU3    11
-
 static u8 tegra_cpu_domains[] = {
         0xFF,                   /* not available for CPU0 */
         TEGRA_POWERGATE_CPU1,
@@ -288,6 +283,7 @@ void tegra_pmc_suspend_init(void)
 #endif
 
 static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra124-pmc" },
         { .compatible = "nvidia,tegra114-pmc" },
         { .compatible = "nvidia,tegra30-pmc" },
         { .compatible = "nvidia,tegra20-pmc" },
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f076f0f80fcd..85d28e756bb7 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -42,8 +42,16 @@
 
 static int tegra_num_powerdomains;
 static int tegra_num_cpu_domains;
-static u8 *tegra_cpu_domains;
-static u8 tegra30_cpu_domains[] = {
+static const u8 *tegra_cpu_domains;
+
+static const u8 tegra30_cpu_domains[] = {
+        TEGRA_POWERGATE_CPU,
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+
+static const u8 tegra114_cpu_domains[] = {
         TEGRA_POWERGATE_CPU0,
         TEGRA_POWERGATE_CPU1,
         TEGRA_POWERGATE_CPU2,
@@ -189,6 +197,11 @@ int __init tegra_powergate_init(void)
                 tegra_num_cpu_domains = 4;
                 tegra_cpu_domains = tegra30_cpu_domains;
                 break;
+        case TEGRA114:
+                tegra_num_powerdomains = 23;
+                tegra_num_cpu_domains = 4;
+                tegra_cpu_domains = tegra114_cpu_domains;
+                break;
         default:
                 /* Unknown Tegra variant. Disable powergating */
                 tegra_num_powerdomains = 0;
@@ -229,6 +242,27 @@ static const char * const powergate_name_t30[] = {
         [TEGRA_POWERGATE_3D1]   = "3d1",
 };
 
+static const char * const powergate_name_t114[] = {
+        [TEGRA_POWERGATE_CPU]   = "cpu0",
+        [TEGRA_POWERGATE_3D]    = "3d",
+        [TEGRA_POWERGATE_VENC]  = "venc",
+        [TEGRA_POWERGATE_VDEC]  = "vdec",
+        [TEGRA_POWERGATE_MPE]   = "mpe",
+        [TEGRA_POWERGATE_HEG]   = "heg",
+        [TEGRA_POWERGATE_CPU1]  = "cpu1",
+        [TEGRA_POWERGATE_CPU2]  = "cpu2",
+        [TEGRA_POWERGATE_CPU3]  = "cpu3",
+        [TEGRA_POWERGATE_CELP]  = "celp",
+        [TEGRA_POWERGATE_CPU0]  = "cpu0",
+        [TEGRA_POWERGATE_C0NC]  = "c0nc",
+        [TEGRA_POWERGATE_C1NC]  = "c1nc",
+        [TEGRA_POWERGATE_DIS]   = "dis",
+        [TEGRA_POWERGATE_DISB]  = "disb",
+        [TEGRA_POWERGATE_XUSBA] = "xusba",
+        [TEGRA_POWERGATE_XUSBB] = "xusbb",
+        [TEGRA_POWERGATE_XUSBC] = "xusbc",
+};
+
 static int powergate_show(struct seq_file *s, void *data)
 {
         int i;
@@ -236,9 +270,14 @@ static int powergate_show(struct seq_file *s, void *data)
         seq_printf(s, " powergate powered\n");
         seq_printf(s, "------------------\n");
 
-        for (i = 0; i < tegra_num_powerdomains; i++)
+        for (i = 0; i < tegra_num_powerdomains; i++) {
+                if (!powergate_name[i])
+                        continue;
+
                 seq_printf(s, " %9s %7s\n", powergate_name[i],
                         tegra_powergate_is_powered(i) ? "yes" : "no");
+        }
+
         return 0;
 }
 
@@ -265,6 +304,9 @@ int __init tegra_powergate_debugfs_init(void)
         case TEGRA30:
                 powergate_name = powergate_name_t30;
                 break;
+        case TEGRA114:
+                powergate_name = powergate_name_t114;
+                break;
         }
 
         if (powergate_name) {
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index f527b2c2dea7..8c1ba4fea384 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -45,17 +45,11 @@
 ENTRY(tegra_resume)
         check_cpu_part_num 0xc09, r8, r9
         bleq    v7_invalidate_l1
-        blne    tegra_init_l2_for_a15
 
         cpu_id  r0
-        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
-        cmp     r6, #TEGRA114
-        beq     no_cpu0_chk
-
         cmp     r0, #0                          @ CPU0?
  THUMB( it      ne )
         bne     cpu_resume                      @ no
-no_cpu0_chk:
 
         /* Are we on Tegra20? */
         cmp     r6, #TEGRA20
@@ -75,7 +69,7 @@ no_cpu0_chk:
 
         mov32   r9, 0xc09
         cmp     r8, r9
-        bne     not_ca9
+        bne     end_ca9_scu_l2_resume
 #ifdef CONFIG_HAVE_ARM_SCU
         /* enable SCU */
         mov32   r0, TEGRA_ARM_PERIF_BASE
@@ -86,7 +80,10 @@ no_cpu0_chk:
 
         /* L2 cache resume & re-enable */
         l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
-not_ca9:
+end_ca9_scu_l2_resume:
+        mov32   r9, 0xc0f
+        cmp     r8, r9
+        bleq    tegra_init_l2_for_a15
 
         b       cpu_resume
 ENDPROC(tegra_resume)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index c6fc15cb25df..b16d4a57fa59 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -383,7 +383,7 @@ _pll_m_c_x_done:
         add     r1, r1, #LOCK_DELAY
         wait_until r1, r7, r3
 
-        adr     r5, tegra30_sdram_pad_save
+        adr     r5, tegra_sdram_pad_save
 
         ldr     r4, [r5, #0x18]         @ restore CLK_SOURCE_MSELECT
         str     r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
@@ -408,8 +408,12 @@ _pll_m_c_x_done:
         cmp     r10, #TEGRA30
         movweq  r0, #:lower16:TEGRA_EMC_BASE    @ r0 reserved for emc base
         movteq  r0, #:upper16:TEGRA_EMC_BASE
-        movwne  r0, #:lower16:TEGRA_EMC0_BASE
-        movtne  r0, #:upper16:TEGRA_EMC0_BASE
+        cmp     r10, #TEGRA114
+        movweq  r0, #:lower16:TEGRA_EMC0_BASE
+        movteq  r0, #:upper16:TEGRA_EMC0_BASE
+        cmp     r10, #TEGRA124
+        movweq  r0, #:lower16:TEGRA124_EMC_BASE
+        movteq  r0, #:upper16:TEGRA124_EMC_BASE
 
 exit_self_refresh:
         ldr     r1, [r5, #0xC]          @ restore EMC_XM2VTTGENPADCTRL
@@ -538,6 +542,7 @@ tegra30_sdram_pad_address:
         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+tegra30_sdram_pad_address_end:
 
 tegra114_sdram_pad_address:
         .word   TEGRA_EMC0_BASE + EMC_CFG                               @0x0
@@ -553,16 +558,28 @@ tegra114_sdram_pad_address:
         .word   TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL                 @0x28
         .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL                  @0x2c
         .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
+tegra114_sdram_pad_adress_end:
+
+tegra124_sdram_pad_address:
+        .word   TEGRA124_EMC_BASE + EMC_CFG                             @0x0
+        .word   TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL                   @0x4
+        .word   TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL               @0x8
+        .word   TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL                @0xc
+        .word   TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2               @0x10
+        .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
+        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
+        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+tegra124_sdram_pad_address_end:
 
 tegra30_sdram_pad_size:
-        .word   tegra114_sdram_pad_address - tegra30_sdram_pad_address
+        .word   tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
 
 tegra114_sdram_pad_size:
-        .word   tegra30_sdram_pad_size - tegra114_sdram_pad_address
+        .word   tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
 
-        .type   tegra30_sdram_pad_save, %object
-tegra30_sdram_pad_save:
-        .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+        .type   tegra_sdram_pad_save, %object
+tegra_sdram_pad_save:
+        .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
         .long   0
         .endr
 
@@ -693,13 +710,18 @@ halted:
  */
 tegra30_sdram_self_refresh:
 
-        adr     r8, tegra30_sdram_pad_save
+        adr     r8, tegra_sdram_pad_save
         tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
         cmp     r10, #TEGRA30
         adreq   r2, tegra30_sdram_pad_address
         ldreq   r3, tegra30_sdram_pad_size
-        adrne   r2, tegra114_sdram_pad_address
-        ldrne   r3, tegra114_sdram_pad_size
+        cmp     r10, #TEGRA114
+        adreq   r2, tegra114_sdram_pad_address
+        ldreq   r3, tegra114_sdram_pad_size
+        cmp     r10, #TEGRA124
+        adreq   r2, tegra124_sdram_pad_address
+        ldreq   r3, tegra30_sdram_pad_size
+
         mov     r9, #0
 
 padsave:
@@ -717,7 +739,10 @@ padsave_done:
 
         cmp     r10, #TEGRA30
         ldreq   r0, =TEGRA_EMC_BASE     @ r0 reserved for emc base addr
-        ldrne   r0, =TEGRA_EMC0_BASE
+        cmp     r10, #TEGRA114
+        ldreq   r0, =TEGRA_EMC0_BASE
+        cmp     r10, #TEGRA124
+        ldreq   r0, =TEGRA124_EMC_BASE
 
 enter_self_refresh:
         cmp     r10, #TEGRA30
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 386115ae5c03..ce553d557c31 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -173,6 +173,7 @@ static void __init tegra_dt_init_late(void)
 }
 
 static const char * const tegra_dt_board_compat[] = {
+        "nvidia,tegra124",
         "nvidia,tegra114",
         "nvidia,tegra30",
         "nvidia,tegra20",
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03a10d1..335beb341355 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -87,8 +87,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 #endif
 
 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
+# define soc_is_s3c6400()       is_samsung_s3c6400()
+# define soc_is_s3c6410()       is_samsung_s3c6410()
 # define soc_is_s3c64xx()       (is_samsung_s3c6400() || is_samsung_s3c6410())
 #else
+# define soc_is_s3c6400()       0
+# define soc_is_s3c6410()       0
 # define soc_is_s3c64xx()       0
 #endif
 
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380086d5..8eb4799237f0 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5420)    += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)    += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)       += clk-exynos-audss.o
-ifdef CONFIG_COMMON_CLK
 obj-$(CONFIG_ARCH_S3C64XX)      += clk-s3c64xx.o
-endif
diff --git a/drivers/cpufreq/integrator-cpufreq.c b/drivers/cpufreq/integrator-cpufreq.c
index f7c99df0880b..3d79bca47433 100644
--- a/drivers/cpufreq/integrator-cpufreq.c
+++ b/drivers/cpufreq/integrator-cpufreq.c
@@ -15,18 +15,19 @@
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/icst.h>
 
-static struct cpufreq_driver integrator_driver;
+static void __iomem *cm_base;
+/* The cpufreq driver only use the OSC register */
+#define INTEGRATOR_HDR_OSC_OFFSET       0x08
+#define INTEGRATOR_HDR_LOCK_OFFSET      0x14
 
-#define CM_ID   __io_address(INTEGRATOR_HDR_ID)
-#define CM_OSC  __io_address(INTEGRATOR_HDR_OSC)
-#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
-#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
+static struct cpufreq_driver integrator_driver;
 
 static const struct icst_params lclk_params = {
         .ref            = 24000000,
@@ -100,7 +101,7 @@ static int integrator_set_target(struct cpufreq_policy *policy,
         BUG_ON(cpu != smp_processor_id());
 
         /* get current setting */
-        cm_osc = __raw_readl(CM_OSC);
+        cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);
 
         if (machine_is_integrator()) {
                 vco.s = (cm_osc >> 8) & 7;
@@ -128,7 +129,7 @@ static int integrator_set_target(struct cpufreq_policy *policy,
 
         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 
-        cm_osc = __raw_readl(CM_OSC);
+        cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);
 
         if (machine_is_integrator()) {
                 cm_osc &= 0xfffff800;
@@ -138,9 +139,9 @@ static int integrator_set_target(struct cpufreq_policy *policy,
         }
         cm_osc |= vco.v;
 
-        __raw_writel(0xa05f, CM_LOCK);
-        __raw_writel(cm_osc, CM_OSC);
-        __raw_writel(0, CM_LOCK);
+        __raw_writel(0xa05f, cm_base + INTEGRATOR_HDR_LOCK_OFFSET);
+        __raw_writel(cm_osc, cm_base + INTEGRATOR_HDR_OSC_OFFSET);
+        __raw_writel(0, cm_base + INTEGRATOR_HDR_LOCK_OFFSET);
 
         /*
          * Restore the CPUs allowed mask.
@@ -165,7 +166,7 @@ static unsigned int integrator_get(unsigned int cpu)
         BUG_ON(cpu != smp_processor_id());
 
         /* detect memory etc. */
-        cm_osc = __raw_readl(CM_OSC);
+        cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);
 
         if (machine_is_integrator()) {
                 vco.s = (cm_osc >> 8) & 7;
@@ -202,19 +203,43 @@ static struct cpufreq_driver integrator_driver = {
         .name           = "integrator",
 };
 
-static int __init integrator_cpu_init(void)
+static int __init integrator_cpufreq_probe(struct platform_device *pdev)
 {
+        struct resource *res;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -ENODEV;
+
+        cm_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!cm_base)
+                return -ENODEV;
+
         return cpufreq_register_driver(&integrator_driver);
 }
 
-static void __exit integrator_cpu_exit(void)
+static void __exit integrator_cpufreq_remove(struct platform_device *pdev)
 {
         cpufreq_unregister_driver(&integrator_driver);
 }
 
+static const struct of_device_id integrator_cpufreq_match[] = {
+        { .compatible = "arm,core-module-integrator"},
+        { },
+};
+
+static struct platform_driver integrator_cpufreq_driver = {
+        .driver = {
+                .name = "integrator-cpufreq",
+                .owner = THIS_MODULE,
+                .of_match_table = integrator_cpufreq_match,
+        },
+        .remove = __exit_p(integrator_cpufreq_remove),
+};
+
+module_platform_driver_probe(integrator_cpufreq_driver,
+                             integrator_cpufreq_probe);
+
 MODULE_AUTHOR ("Russell M. King");
 MODULE_DESCRIPTION ("cpufreq driver for ARM Integrator CPUs");
 MODULE_LICENSE ("GPL");
-
-module_init(integrator_cpu_init);
-module_exit(integrator_cpu_exit);
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index 8e3660322308..d6f57d5d9631 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -4,7 +4,7 @@
 
 config ARM_HIGHBANK_CPUIDLE
         bool "CPU Idle Driver for Calxeda processors"
-        depends on ARCH_HIGHBANK
+        depends on ARM_PSCI
         select ARM_CPU_SUSPEND
         help
           Select this to enable cpuidle on Calxeda processors.
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
index 346058479572..36795639df0d 100644
--- a/drivers/cpuidle/cpuidle-calxeda.c
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -21,53 +21,30 @@
  */
 
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
 #include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/suspend.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
 #include <asm/cpuidle.h>
-#include <asm/proc-fns.h>
-#include <asm/smp_scu.h>
 #include <asm/suspend.h>
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-
-extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
-extern void __iomem *scu_base_addr;
-
-static noinline void calxeda_idle_restore(void)
-{
-        set_cr(get_cr() | CR_C);
-        set_auxcr(get_auxcr() | 0x40);
-        scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
-}
+#include <asm/psci.h>
 
 static int calxeda_idle_finish(unsigned long val)
 {
-        /* Already flushed cache, but do it again as the outer cache functions
-         * dirty the cache with spinlocks */
-        flush_cache_all();
-
-        set_auxcr(get_auxcr() & ~0x40);
-        set_cr(get_cr() & ~CR_C);
-
-        scu_power_mode(scu_base_addr, SCU_PM_DORMANT);
-
-        cpu_do_idle();
-
-        /* Restore things if we didn't enter power-gating */
-        calxeda_idle_restore();
-        return 1;
+        const struct psci_power_state ps = {
+                .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+        };
+        return psci_ops.cpu_suspend(ps, __pa(cpu_resume));
 }
 
 static int calxeda_pwrdown_idle(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index)
 {
-        highbank_set_cpu_jump(smp_processor_id(), cpu_resume);
+        cpu_pm_enter();
         cpu_suspend(0, calxeda_idle_finish);
+        cpu_pm_exit();
+
         return index;
 }
 
@@ -88,11 +65,17 @@ static struct cpuidle_driver calxeda_idle_driver = {
         .state_count = 2,
 };
 
-static int __init calxeda_cpuidle_init(void)
+static int __init calxeda_cpuidle_probe(struct platform_device *pdev)
 {
-        if (!of_machine_is_compatible("calxeda,highbank"))
-                return -ENODEV;
-
         return cpuidle_register(&calxeda_idle_driver, NULL);
 }
-module_init(calxeda_cpuidle_init);
+
+static struct platform_driver calxeda_cpuidle_plat_driver = {
+        .driver = {
+                .name = "cpuidle-calxeda",
+                .owner = THIS_MODULE,
+        },
+        .probe = calxeda_cpuidle_probe,
+};
+
+module_platform_driver(calxeda_cpuidle_plat_driver);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f238cfd33847..56fe803adcb1 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -195,7 +195,7 @@ config SIRF_DMA
 
 config TI_EDMA
         bool "TI EDMA support"
-        depends on ARCH_DAVINCI || ARCH_OMAP
+        depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE
         select DMA_ENGINE
         select DMA_VIRTUAL_CHANNELS
         select TI_PRIV_EDMA
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
index be3429e08d90..f90101b9cdb9 100644
--- a/drivers/usb/host/ohci-s3c2410.c
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -64,10 +64,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)
 
         dev_dbg(&dev->dev, "s3c2410_start_hc:\n");
 
-        clk_enable(usb_clk);
+        clk_prepare_enable(usb_clk);
         mdelay(2);                      /* let the bus clock stabilise */
 
-        clk_enable(clk);
+        clk_prepare_enable(clk);
 
         if (info != NULL) {
                 info->hcd       = hcd;
@@ -92,8 +92,8 @@ static void s3c2410_stop_hc(struct platform_device *dev)
                         (info->enable_oc)(info, 0);
         }
 
-        clk_disable(clk);
-        clk_disable(usb_clk);
+        clk_disable_unprepare(clk);
+        clk_disable_unprepare(usb_clk);
 }
 
 /* ohci_s3c2410_hub_status_data
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index b6bdcd66c07d..7086b2248c8f 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -363,4 +363,9 @@
 #define IMX6Q_GPR13_SATA_TX_LVL_1_240_V         (0x1f << 2)
 #define IMX6Q_GPR13_SATA_MPLL_CLK_EN            BIT(1)
 #define IMX6Q_GPR13_SATA_TX_EDGE_RATE           BIT(0)
+
+/* For imx6sl iomux gpr register field define */
+#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
+#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index 55c29a8d5015..c98cfa406952 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -34,8 +34,15 @@ struct clk;
 #define TEGRA_POWERGATE_CPU3    11
 #define TEGRA_POWERGATE_CELP    12
 #define TEGRA_POWERGATE_3D1     13
+#define TEGRA_POWERGATE_CPU0    14
+#define TEGRA_POWERGATE_C0NC    15
+#define TEGRA_POWERGATE_C1NC    16
+#define TEGRA_POWERGATE_DIS     18
+#define TEGRA_POWERGATE_DISB    19
+#define TEGRA_POWERGATE_XUSBA   20
+#define TEGRA_POWERGATE_XUSBB   21
+#define TEGRA_POWERGATE_XUSBC   22
 
-#define TEGRA_POWERGATE_CPU0    TEGRA_POWERGATE_CPU
 #define TEGRA_POWERGATE_3D0     TEGRA_POWERGATE_3D
 
 int tegra_powergate_is_powered(int id);